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//sata_command_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
`define RESET_TIMEOUT 32'h00000002
module sata_command_layer (
input rst, //reset
input linkup,
input clk,
input data_in_clk,
input data_in_clk_valid,
input data_out_clk,
input data_out_clk_valid,
//User Interface
output command_layer_ready,
output reg sata_busy,
input send_sync_escape,
input [15:0] user_features,
//XXX: New Stb
// input write_data_stb,
// input read_data_stb,
output hard_drive_error,
input execute_command_stb,
input command_layer_reset,
output reg pio_data_ready,
input [7:0] hard_drive_command,
input [15:0] sector_count,
input [47:0] sector_address,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output user_din_empty,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
//Transfer Layer Interface
input transport_layer_ready,
output reg sync_escape,
output t_send_command_stb,
output reg t_send_control_stb,
output t_send_data_stb,
input t_dma_activate_stb,
input t_d2h_reg_stb,
input t_pio_setup_stb,
input t_d2h_data_stb,
input t_dma_setup_stb,
input t_set_device_bits_stb,
input t_remote_abort,
input t_xmit_error,
input t_read_crc_error,
//PIO
input t_pio_response,
input t_pio_direction,
input [15:0] t_pio_transfer_count,
input [7:0] t_pio_e_status,
//Host to Device Register Values
output [7:0] h2d_command,
output reg [15:0] h2d_features,
output [7:0] h2d_control,
output [3:0] h2d_port_mult,
output [7:0] h2d_device,
output [47:0] h2d_lba,
output [15:0] h2d_sector_count,
//Device to Host Register Values
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
output d2h_error_bbk, //Bad Block
output d2h_error_unc, //Uncorrectable Error
output d2h_error_mc, //Removable Media Error
output d2h_error_idnf, //request sector's ID Field could not be found
output d2h_error_mcr, //Removable Media Error
output d2h_error_abrt, //Abort (from invalid command, drive not ready, write fault)
output d2h_error_tk0nf, //Track 0 not found
output d2h_error_amnf, //Data Address Mark is not found after finding correct ID
output d2h_status_bsy, //Set to 1 when drive has access to command block, no other bits are valid when 1
// Set after reset
// Set after soft reset (srst)
// Set immediately after host writes to command register
output d2h_status_drdy, //Drive is ready to accept command
output d2h_status_dwf, //Drive Write Fault
output d2h_status_dsc, //Drive Seek Complete
output d2h_status_drq, //Data Request, Drive is ready to send data to the host
output d2h_status_corr, //Correctable Data bit (an error that was encountered but was corrected)
output d2h_status_idx, //once per disc revolution this bit is set to one then back to zero
output d2h_status_err, //error bit, if this bit is high check the error flags
//command layer data interface
input t_if_strobe,
output [31:0] t_if_data,
output t_if_ready,
input t_if_activate,
output [23:0] t_if_size,
input t_of_strobe,
input [31:0] t_of_data,
output [1:0] t_of_ready,
input [1:0] t_of_activate,
output [23:0] t_of_size,
//Debug
output [3:0] cl_c_state,
output [3:0] cl_w_state
);
//Parameters
parameter IDLE = 4'h0;
parameter PIO_WAIT_FOR_DATA = 4'h1;
parameter PIO_WRITE_DATA = 4'h2;
parameter WAIT_FOR_DMA_ACT = 4'h1;
parameter WAIT_FOR_WRITE_DATA = 4'h2;
parameter SEND_DATA = 4'h3;
//Registers/Wires
reg [3:0] cntrl_state;
reg srst;
reg [7:0] status;
wire idle;
reg cntrl_send_data_stb;
reg send_command_stb;
wire dev_busy;
wire dev_data_req;
//Write State Machine
reg [3:0] write_state;
reg dma_send_data_stb;
reg dma_act_detected_en;
reg enable_tl_data_ready;
//Ping Pong FIFOs
wire [1:0] if_write_ready;
wire [1:0] if_write_activate;
wire [23:0] if_write_size;
wire if_write_strobe;
wire [31:0] if_write_data;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire if_reset;
wire [31:0] of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_read_size;
wire of_write_strobe;
wire out_fifo_starved;
wire of_read_ready;
wire [31:0] of_read_data;
wire of_read_activate;
wire [23:0] of_write_size;
wire of_read_strobe;
wire of_reset;
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_in (
.reset (if_reset ), //XXX: Veify that new PPFIFO doesn't need an external reset
//write side
//XXX: This can be different clocks
.write_clock (data_in_clk ),
.write_data (if_write_data ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_size ),
.write_strobe (if_write_strobe ),
//.starved (if_starved ),
.starved (user_din_empty ),
//read side
//XXX: This can be different clocks
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data ),
.inactive ( )
);
//Output FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_out (
.reset (of_reset ),
//.reset (0),
//write side
//XXX: This can be different clocks
.write_clock (clk ),
.write_data (of_write_data ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
//.starved (out_fifo_starved ),
.starved ( ),
//read side
//XXX: This can be different clocks
.read_clock (data_out_clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data ),
.inactive ( )
);
//Asynchronous Logic
//Attach output of Input FIFO to TL
assign t_if_ready = if_read_ready && enable_tl_data_ready;
assign t_if_size = if_read_size;
assign t_if_data = if_read_data;
assign if_read_activate = t_if_activate;
assign if_read_strobe = t_if_strobe;
//Attach input of output FIFO to TL
assign t_of_ready = of_write_ready;
//assign t_of_size = of_write_size;
assign t_of_size = 24'h00800;
assign of_write_data = t_of_data;
assign of_write_activate = t_of_activate;
assign of_write_strobe = t_of_strobe;
assign of_reset = (rst && data_out_clk_valid);
assign if_reset = (rst && data_in_clk_valid);
assign if_write_data = user_din;
assign if_write_strobe = user_din_stb;
assign user_din_ready = if_write_ready;
assign if_write_activate = user_din_activate;
assign user_din_size = if_write_size;
assign user_dout = of_read_data;
assign user_dout_ready = of_read_ready;
assign of_read_activate = user_dout_activate;
assign user_dout_size = of_read_size;
assign of_read_strobe = user_dout_stb;
assign d2h_status_bsy = d2h_status[7];
assign d2h_status_drdy = d2h_status[6];
assign d2h_status_dwf = d2h_status[5];
assign d2h_status_dsc = d2h_status[4];
assign d2h_status_drq = d2h_status[3];
assign d2h_status_corr = d2h_status[2];
assign d2h_status_idx = d2h_status[1];
assign d2h_status_err = d2h_status[0];
assign d2h_error_bbk = d2h_error[7];
assign d2h_error_unc = d2h_error[6];
assign d2h_error_mc = d2h_error[5];
assign d2h_error_idnf = d2h_error[4];
assign d2h_error_mcr = d2h_error[3];
assign d2h_error_abrt = d2h_error[2];
assign d2h_error_tk0nf = d2h_error[1];
assign d2h_error_amnf = d2h_error[0];
//Strobes
//assign t_send_command_stb = read_data_stb || write_data_stb || execute_command_stb;
assign t_send_command_stb = execute_command_stb;
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
//IDLE
assign idle = (cntrl_state == IDLE) &&
(write_state == IDLE) &&
transport_layer_ready;
assign command_layer_ready = idle;
assign h2d_command = hard_drive_command;
assign h2d_sector_count = sector_count;
assign h2d_lba = sector_address;
//XXX: The individual bits should be controlled directly
assign h2d_control = {5'h00, srst, 2'b00};
//XXX: This should be controlled from a higher level
assign h2d_port_mult = 4'h0;
//XXX: This should be controlled from a higher level
assign h2d_device = `D2H_REG_DEVICE;
assign dev_busy = status[`STATUS_BUSY_BIT];
assign dev_data_req = status[`STATUS_DRQ_BIT];
assign hard_drive_error = status[`STATUS_ERR_BIT];
assign cl_c_state = cntrl_state;
assign cl_w_state = write_state;
//Synchronous Logic
//Control State Machine
always @ (posedge clk) begin
if (rst || (!linkup)) begin
cntrl_state <= IDLE;
h2d_features <= `D2H_REG_FEATURES;
srst <= 0;
//Strobes
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
status <= 0;
sata_busy <= 0;
sync_escape <= 0;
end
else begin
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
//Reset Count
if (t_d2h_reg_stb) begin
//Receiving a register strobe from the device
sata_busy <= 0;
h2d_features <= `D2H_REG_FEATURES;
end
/*
if (t_send_command_stb || t_send_control_stb) begin
sata_busy <= 1;
end
*/
if (execute_command_stb) begin
h2d_features <= user_features;
sata_busy <= 1;
end
case (cntrl_state)
IDLE: begin
//Soft Reset will break out of any flow
if (command_layer_reset && !srst) begin
srst <= 1;
t_send_control_stb <= 1;
end
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//User Initiated commands
if (!command_layer_reset && srst) begin
srst <= 0;
t_send_control_stb <= 1;
end
end
//Device Initiated Transfers
if(t_pio_setup_stb) begin
if (t_pio_direction) begin
//Read from device
cntrl_state <= PIO_WAIT_FOR_DATA;
end
else begin
//Write to device
cntrl_state <= PIO_WRITE_DATA;
end
end
if (t_set_device_bits_stb) begin
status <= d2h_status;
//status register was updated
end
if (t_d2h_reg_stb) begin
status <= d2h_status;
end
end
PIO_WAIT_FOR_DATA: begin
if (t_d2h_data_stb) begin
//the next peice of data is related to the PIO
pio_data_ready <= 1;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
PIO_WRITE_DATA: begin
if (if_read_activate) begin
cntrl_send_data_stb <= 0;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
default: begin
cntrl_state <= IDLE;
end
endcase
if (send_sync_escape) begin
cntrl_state <= IDLE;
sync_escape <= 1;
sata_busy <= 0;
end
end
end
//Write State Machine
always @ (posedge clk) begin
if (rst || !linkup) begin
write_state <= IDLE;
dma_send_data_stb <= 0;
enable_tl_data_ready <= 0;
dma_act_detected_en <= 0;
end
else begin
dma_send_data_stb <= 0;
if (t_dma_activate_stb) begin
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
dma_act_detected_en <= 1;
end
case (write_state)
IDLE: begin
enable_tl_data_ready <= 0;
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//if (write_data_stb) begin
if (dma_act_detected_en) begin
//send a request to write data
write_state <= WAIT_FOR_DMA_ACT;
end
end
end
WAIT_FOR_DMA_ACT: begin
if (dma_act_detected_en) begin
dma_act_detected_en <= 0;
enable_tl_data_ready <= 1;
write_state <= WAIT_FOR_WRITE_DATA;
end
end
WAIT_FOR_WRITE_DATA: begin
if (if_read_activate) begin
enable_tl_data_ready <= 0;
write_state <= SEND_DATA;
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
//Send the Data FIS
dma_send_data_stb <= 1;
dma_act_detected_en <= 0;
write_state <= IDLE;
end
end
default: begin
write_state <= IDLE;
end
endcase
//if (command_layer_reset || !reset_timeout) begin
if (command_layer_reset) begin
//Break out of the normal flow and return to IDLE
write_state <= IDLE;
end
if (t_d2h_reg_stb) begin
//Whenever I read a register transfer from the device I need to go back to IDLE
write_state <= IDLE;
end
if (send_sync_escape) begin
write_state <= IDLE;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND2B_FUNCTIONAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2b (
VPWR,
VGND,
X ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
// Local signals
wire X not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_FUNCTIONAL_PP_V |
// Module m_paper implements all features of the 4-bit paper processor.
module m_paper;
reg r_low = 1'b0; // logic low register
reg r_high = 1'b1; // logic high register
reg r_clock = 1'b0; // clock pulse register
reg r_reset = 1'b1; // reset value register
wire w_low, w_high, w_clock, w_reset; // low, high, clock, and reset wires
assign w_low = r_low; // assign low wire to low register
assign w_high = r_high; // assign high wire to high register
assign w_clock = r_clock; // assign clock wire to clock register
assign w_reset = r_reset; // assign reset wire to reset register
wire [1:0] w_bus_addr; // address bus/program counter output bus)
wire [3:0] w_bus_data; // data bus
wire w_inc, w_jno, w_hlt, w_nop; // inc, jno, hlt, and nop wires
wire [1:0] w_bus_pc_in; // program counter input bus
wire [1:0] w_bus_pr_out, w_bus_pr_in; // program register i/o buses
wire w_sr_out, w_sr_in; // status register i/o wires
m_memory mem_0 (w_bus_data, w_bus_addr); // instantiate memory module
m_program_counter pc_0 (w_bus_addr, w_bus_pc_in, w_clock, w_reset); // instantiate program counter
m_program_register pr_0 (w_bus_pr_out, w_bus_pr_in, w_clock, w_reset); // instantiate program register
m_status_register sr_0 (w_sr_out, w_sr_in, w_clock, w_reset); // instantiate status register
m_opdecode opdc_0 (w_inc, w_jno, w_hlt, w_nop, w_bus_data); // instantiate opdecode module
m_ckt_inc ckt_inc_0 (w_bus_pr_in, w_sr_in, w_bus_pr_out, w_inc, w_low); // instantiate increment circuit
m_ckt_jno ckt_jno_0 (w_bus_pc_in, w_bus_addr, w_bus_data, w_jno, w_sr_out, w_low, w_high); // instantiate jump if not overflowed circuit
//m_ckt_hlt ckt_hlt_0 (); // instantiate halt circuit
//m_ckt_nop ckt_nop_0 (); // instantiate no operation circuit
initial begin // do initially:
$dumpfile ("paper.vcd"); // dump output to paper.vcd
$dumpvars (0, m_paper); // dump variables from mpaper module
$monitor ("pc: %b, pr: %b, s: %b, data: %b", w_bus_addr, w_bus_pr_out, w_sr_out, w_bus_data);
#2 r_reset = 1'b0; // wait 2s, reset all circuit elements
end
always #1 begin // every 1s:
r_clock = ~w_clock; // invert clock signal
if (w_hlt) begin
$display ("HLT call: Halting system.");
$finish; // halt simulation if hlt called
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O32A_FUNCTIONAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_FUNCTIONAL_PP_V |
// altera_mem_if_ddr3_phy_0001_qsys_sequencer.v
// This file was auto-generated from qsys_sequencer_110_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:49:55
`timescale 1 ps / 1 ps
module altera_mem_if_ddr3_phy_0001_qsys_sequencer (
input wire clock_clk, // clock.clk
input wire reset_reset_n, // reset.reset_n
input wire reset_n_scc_clk, // scc.reset_n_scc_clk
input wire scc_clk, // .scc_clk
output wire scc_data, // .scc_data
output wire [1:0] scc_dqs_ena, // .scc_dqs_ena
output wire [1:0] scc_dqs_io_ena, // .scc_dqs_io_ena
output wire [15:0] scc_dq_ena, // .scc_dq_ena
output wire [1:0] scc_dm_ena, // .scc_dm_ena
output wire scc_upd, // .scc_upd
input wire [1:0] capture_strobe_tracking, // .capture_strobe_tracking
input wire phy_clk, // phy.phy_clk
input wire phy_reset_n, // .phy_reset_n
output wire [4:0] phy_read_latency_counter, // .phy_read_latency_counter
output wire [1:0] phy_read_increment_vfifo_fr, // .phy_read_increment_vfifo_fr
output wire [1:0] phy_read_increment_vfifo_hr, // .phy_read_increment_vfifo_hr
output wire [1:0] phy_read_increment_vfifo_qr, // .phy_read_increment_vfifo_qr
output wire phy_reset_mem_stable, // .phy_reset_mem_stable
output wire [5:0] phy_afi_wlat, // .phy_afi_wlat
output wire [5:0] phy_afi_rlat, // .phy_afi_rlat
output wire phy_mux_sel, // .phy_mux_sel
output wire phy_cal_success, // .phy_cal_success
output wire phy_cal_fail, // .phy_cal_fail
output wire [31:0] phy_cal_debug_info, // .phy_cal_debug_info
output wire [1:0] phy_read_fifo_reset, // .phy_read_fifo_reset
output wire [1:0] phy_vfifo_rd_en_override, // .phy_vfifo_rd_en_override
input wire [7:0] calib_skip_steps, // calib.calib_skip_steps
input wire afi_clk, // afi.afi_clk
input wire afi_reset_n, // .afi_reset_n
output wire [25:0] afi_address, // .afi_address
output wire [5:0] afi_bank, // .afi_bank
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_odt, // .afi_odt
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [3:0] afi_dqs_en, // .afi_dqs_en
output wire [1:0] afi_mem_reset_n, // .afi_mem_reset_n
output wire [63:0] afi_wdata, // .afi_wdata
output wire [3:0] afi_wdata_valid, // .afi_wdata_valid
output wire [7:0] afi_dm, // .afi_dm
output wire afi_rdata_en, // .afi_rdata_en
output wire afi_rdata_en_full, // .afi_rdata_en_full
input wire [63:0] afi_rdata, // .afi_rdata
input wire afi_rdata_valid // .afi_rdata_valid
);
wire cpu_inst_instruction_master_waitrequest; // cpu_inst_instruction_master_translator:av_waitrequest -> cpu_inst:i_waitrequest
wire [16:0] cpu_inst_instruction_master_address; // cpu_inst:i_address -> cpu_inst_instruction_master_translator:av_address
wire cpu_inst_instruction_master_read; // cpu_inst:i_read -> cpu_inst_instruction_master_translator:av_read
wire [31:0] cpu_inst_instruction_master_readdata; // cpu_inst_instruction_master_translator:av_readdata -> cpu_inst:i_readdata
wire cpu_inst_data_master_waitrequest; // cpu_inst_data_master_translator:av_waitrequest -> cpu_inst:d_waitrequest
wire [31:0] cpu_inst_data_master_writedata; // cpu_inst:d_writedata -> cpu_inst_data_master_translator:av_writedata
wire [18:0] cpu_inst_data_master_address; // cpu_inst:d_address -> cpu_inst_data_master_translator:av_address
wire cpu_inst_data_master_write; // cpu_inst:d_write -> cpu_inst_data_master_translator:av_write
wire cpu_inst_data_master_read; // cpu_inst:d_read -> cpu_inst_data_master_translator:av_read
wire [31:0] cpu_inst_data_master_readdata; // cpu_inst_data_master_translator:av_readdata -> cpu_inst:d_readdata
wire cpu_inst_data_master_debugaccess; // cpu_inst:jtag_debug_module_debugaccess_to_roms -> cpu_inst_data_master_translator:av_debugaccess
wire [3:0] cpu_inst_data_master_byteenable; // cpu_inst:d_byteenable -> cpu_inst_data_master_translator:av_byteenable
wire [31:0] sequencer_rom_s1_translator_avalon_anti_slave_0_writedata; // sequencer_rom_s1_translator:av_writedata -> sequencer_rom:writedata
wire [11:0] sequencer_rom_s1_translator_avalon_anti_slave_0_address; // sequencer_rom_s1_translator:av_address -> sequencer_rom:address
wire sequencer_rom_s1_translator_avalon_anti_slave_0_chipselect; // sequencer_rom_s1_translator:av_chipselect -> sequencer_rom:chipselect
wire sequencer_rom_s1_translator_avalon_anti_slave_0_clken; // sequencer_rom_s1_translator:av_clken -> sequencer_rom:clken
wire sequencer_rom_s1_translator_avalon_anti_slave_0_write; // sequencer_rom_s1_translator:av_write -> sequencer_rom:write
wire [31:0] sequencer_rom_s1_translator_avalon_anti_slave_0_readdata; // sequencer_rom:readdata -> sequencer_rom_s1_translator:av_readdata
wire sequencer_rom_s1_translator_avalon_anti_slave_0_debugaccess; // sequencer_rom_s1_translator:av_debugaccess -> sequencer_rom:debugaccess
wire [3:0] sequencer_rom_s1_translator_avalon_anti_slave_0_byteenable; // sequencer_rom_s1_translator:av_byteenable -> sequencer_rom:byteenable
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // cpu_inst_jtag_debug_module_translator:av_writedata -> cpu_inst:jtag_debug_module_writedata
wire [8:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_address; // cpu_inst_jtag_debug_module_translator:av_address -> cpu_inst:jtag_debug_module_address
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // cpu_inst_jtag_debug_module_translator:av_chipselect -> cpu_inst:jtag_debug_module_select
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_write; // cpu_inst_jtag_debug_module_translator:av_write -> cpu_inst:jtag_debug_module_write
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // cpu_inst:jtag_debug_module_readdata -> cpu_inst_jtag_debug_module_translator:av_readdata
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // cpu_inst_jtag_debug_module_translator:av_begintransfer -> cpu_inst:jtag_debug_module_begintransfer
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // cpu_inst_jtag_debug_module_translator:av_debugaccess -> cpu_inst:jtag_debug_module_debugaccess
wire [3:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // cpu_inst_jtag_debug_module_translator:av_byteenable -> cpu_inst:jtag_debug_module_byteenable
wire [31:0] sequencer_ram_s1_translator_avalon_anti_slave_0_writedata; // sequencer_ram_s1_translator:av_writedata -> sequencer_ram:writedata
wire [8:0] sequencer_ram_s1_translator_avalon_anti_slave_0_address; // sequencer_ram_s1_translator:av_address -> sequencer_ram:address
wire sequencer_ram_s1_translator_avalon_anti_slave_0_chipselect; // sequencer_ram_s1_translator:av_chipselect -> sequencer_ram:chipselect
wire sequencer_ram_s1_translator_avalon_anti_slave_0_clken; // sequencer_ram_s1_translator:av_clken -> sequencer_ram:clken
wire sequencer_ram_s1_translator_avalon_anti_slave_0_write; // sequencer_ram_s1_translator:av_write -> sequencer_ram:write
wire [31:0] sequencer_ram_s1_translator_avalon_anti_slave_0_readdata; // sequencer_ram:readdata -> sequencer_ram_s1_translator:av_readdata
wire [3:0] sequencer_ram_s1_translator_avalon_anti_slave_0_byteenable; // sequencer_ram_s1_translator:av_byteenable -> sequencer_ram:byteenable
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_rw_mgr_inst:avl_waitrequest -> sequencer_rw_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_rw_mgr_inst_avl_translator:av_writedata -> sequencer_rw_mgr_inst:avl_writedata
wire [12:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_rw_mgr_inst_avl_translator:av_address -> sequencer_rw_mgr_inst:avl_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_rw_mgr_inst_avl_translator:av_write -> sequencer_rw_mgr_inst:avl_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_rw_mgr_inst_avl_translator:av_read -> sequencer_rw_mgr_inst:avl_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_rw_mgr_inst:avl_readdata -> sequencer_rw_mgr_inst_avl_translator:av_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_phy_mgr_inst:avl_waitrequest -> sequencer_phy_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_phy_mgr_inst_avl_translator:av_writedata -> sequencer_phy_mgr_inst:avl_writedata
wire [12:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_phy_mgr_inst_avl_translator:av_address -> sequencer_phy_mgr_inst:avl_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_phy_mgr_inst_avl_translator:av_write -> sequencer_phy_mgr_inst:avl_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_phy_mgr_inst_avl_translator:av_read -> sequencer_phy_mgr_inst:avl_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_phy_mgr_inst:avl_readdata -> sequencer_phy_mgr_inst_avl_translator:av_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_data_mgr_inst:avl_waitrequest -> sequencer_data_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_data_mgr_inst_avl_translator:av_writedata -> sequencer_data_mgr_inst:avl_writedata
wire [12:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_data_mgr_inst_avl_translator:av_address -> sequencer_data_mgr_inst:avl_address
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_data_mgr_inst_avl_translator:av_write -> sequencer_data_mgr_inst:avl_write
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_data_mgr_inst_avl_translator:av_read -> sequencer_data_mgr_inst:avl_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_data_mgr_inst:avl_readdata -> sequencer_data_mgr_inst_avl_translator:av_readdata
wire sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_ptr_mgr_inst:avl_waitrequest -> sequencer_ptr_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_ptr_mgr_inst_avl_translator:av_writedata -> sequencer_ptr_mgr_inst:avl_writedata
wire [12:0] sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_ptr_mgr_inst_avl_translator:av_address -> sequencer_ptr_mgr_inst:avl_address
wire sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_ptr_mgr_inst_avl_translator:av_write -> sequencer_ptr_mgr_inst:avl_write
wire sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_ptr_mgr_inst_avl_translator:av_read -> sequencer_ptr_mgr_inst:avl_read
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_ptr_mgr_inst:avl_readdata -> sequencer_ptr_mgr_inst_avl_translator:av_readdata
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_scc_mgr_inst:avl_waitrequest -> sequencer_scc_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_scc_mgr_inst_avl_translator:av_writedata -> sequencer_scc_mgr_inst:avl_writedata
wire [12:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_scc_mgr_inst_avl_translator:av_address -> sequencer_scc_mgr_inst:avl_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_scc_mgr_inst_avl_translator:av_write -> sequencer_scc_mgr_inst:avl_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_scc_mgr_inst_avl_translator:av_read -> sequencer_scc_mgr_inst:avl_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_scc_mgr_inst:avl_readdata -> sequencer_scc_mgr_inst_avl_translator:av_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_rom_s1_translator:uav_waitrequest -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rom_s1_translator:uav_burstcount
wire [31:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rom_s1_translator:uav_writedata
wire [18:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rom_s1_translator:uav_address
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rom_s1_translator:uav_write
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rom_s1_translator:uav_lock
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rom_s1_translator:uav_read
wire [31:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_rom_s1_translator:uav_readdata -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_rom_s1_translator:uav_readdatavalid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rom_s1_translator:uav_debugaccess
wire [3:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rom_s1_translator:uav_byteenable
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // cpu_inst_jtag_debug_module_translator:uav_waitrequest -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> cpu_inst_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> cpu_inst_jtag_debug_module_translator:uav_writedata
wire [18:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> cpu_inst_jtag_debug_module_translator:uav_address
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> cpu_inst_jtag_debug_module_translator:uav_write
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> cpu_inst_jtag_debug_module_translator:uav_lock
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> cpu_inst_jtag_debug_module_translator:uav_read
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // cpu_inst_jtag_debug_module_translator:uav_readdata -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // cpu_inst_jtag_debug_module_translator:uav_readdatavalid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> cpu_inst_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> cpu_inst_jtag_debug_module_translator:uav_byteenable
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_ram_s1_translator:uav_waitrequest -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_ram_s1_translator:uav_burstcount
wire [31:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_ram_s1_translator:uav_writedata
wire [18:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_ram_s1_translator:uav_address
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_ram_s1_translator:uav_write
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_ram_s1_translator:uav_lock
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_ram_s1_translator:uav_read
wire [31:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_ram_s1_translator:uav_readdata -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_ram_s1_translator:uav_readdatavalid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_ram_s1_translator:uav_debugaccess
wire [3:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_ram_s1_translator:uav_byteenable
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_ptr_mgr_inst_avl_translator:uav_waitrequest -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_ptr_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_ptr_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_ptr_mgr_inst_avl_translator:uav_address
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_ptr_mgr_inst_avl_translator:uav_write
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_ptr_mgr_inst_avl_translator:uav_lock
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_ptr_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_ptr_mgr_inst_avl_translator:uav_readdata -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_ptr_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_ptr_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_ptr_mgr_inst_avl_translator:uav_byteenable
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [75:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [75:0] cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [75:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [75:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [75:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [75:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [75:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [75:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [75:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [75:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [75:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [7:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [75:0] limiter_rsp_src_data; // limiter:rsp_src_data -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [75:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [75:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_001_rsp_src_ready; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cpu_inst:reset_n, cpu_inst_data_master_translator:reset, cpu_inst_data_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_instruction_master_translator:reset, cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_jtag_debug_module_translator:reset, cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, irq_mapper:reset, limiter:reset, limiter_001:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sequencer_data_mgr_inst:avl_reset_n, sequencer_data_mgr_inst_avl_translator:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_phy_mgr_inst_avl_translator:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_ptr_mgr_inst:avl_reset_n, sequencer_ptr_mgr_inst_avl_translator:reset, sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_ram:reset, sequencer_ram_s1_translator:reset, sequencer_ram_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rom:reset, sequencer_rom_s1_translator:reset, sequencer_rom_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rw_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst_avl_translator:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_scc_mgr_inst:avl_reset_n, sequencer_scc_mgr_inst_avl_translator:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [75:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [7:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [75:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [7:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [75:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [75:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [75:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [7:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [75:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [7:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [75:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [7:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [75:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [7:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [75:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data
wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [75:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [75:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [75:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [75:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [75:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [75:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [7:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [75:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [7:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [75:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [75:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [75:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [7:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [75:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [7:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_001_src2_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [75:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_demux_001_src3_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [75:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_001_src4_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [75:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [75:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src6_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [75:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src7_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [75:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire [7:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire [31:0] cpu_inst_d_irq_irq; // irq_mapper:sender_irq -> cpu_inst:d_irq
sequencer_scc_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_READ_DQS_WIDTH (2),
.MEM_WRITE_DQS_WIDTH (2),
.MEM_DQ_WIDTH (16),
.MEM_DM_WIDTH (2),
.DLL_DELAY_CHAIN_LENGTH (8),
.FAMILY ("STRATIXIV"),
.DQS_TRK_ENABLED (0)
) sequencer_scc_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.reset_n_scc_clk (reset_n_scc_clk), // scc.reset_n_scc_clk
.scc_clk (scc_clk), // .scc_clk
.scc_data (scc_data), // .scc_data
.scc_dqs_ena (scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (scc_dm_ena), // .scc_dm_ena
.scc_upd (scc_upd), // .scc_upd
.capture_strobe_tracking (capture_strobe_tracking) // .capture_strobe_tracking
);
sequencer_ptr_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13)
) sequencer_ptr_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
sequencer_phy_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (5),
.MEM_READ_DQS_WIDTH (2),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (14),
.CALIB_LFIFO_OFFSET (5),
.CALIB_SKIP_STEPS_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (5),
.MEM_T_RL (7),
.CTL_REGDIMM_ENABLED (0)
) sequencer_phy_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.phy_clk (phy_clk), // phy.phy_clk
.phy_reset_n (phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (phy_read_latency_counter), // .phy_read_latency_counter
.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_afi_wlat (phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (phy_afi_rlat), // .phy_afi_rlat
.phy_mux_sel (phy_mux_sel), // .phy_mux_sel
.phy_cal_success (phy_cal_success), // .phy_cal_success
.phy_cal_fail (phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.calib_skip_steps (calib_skip_steps) // calib.calib_skip_steps
);
sequencer_data_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (5),
.MEM_READ_DQS_WIDTH (2),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (14),
.CALIB_LFIFO_OFFSET (5),
.CALIB_SKIP_STEPS_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (5),
.MEM_T_RL (7),
.CTL_REGDIMM_ENABLED (0),
.SEQUENCER_VERSION (0)
) sequencer_data_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
rw_manager_ddr3 #(
.RATE ("Half"),
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_ADDRESS_WIDTH (13),
.MEM_CONTROL_WIDTH (1),
.MEM_DQ_WIDTH (16),
.MEM_DM_WIDTH (2),
.MEM_NUMBER_OF_RANKS (1),
.MEM_CLK_EN_WIDTH (1),
.MEM_BANK_WIDTH (3),
.MEM_ODT_WIDTH (1),
.MEM_CHIP_SELECT_WIDTH (1),
.MEM_READ_DQS_WIDTH (2),
.MEM_WRITE_DQS_WIDTH (2),
.AFI_RATIO (2),
.AC_BUS_WIDTH (27),
.HCX_COMPAT_MODE (0),
.DEVICE_FAMILY ("STRATIXIV"),
.AC_ROM_INIT_FILE_NAME ("altera_mem_if_ddr3_phy_0001_AC_ROM.hex"),
.INST_ROM_INIT_FILE_NAME ("altera_mem_if_ddr3_phy_0001_inst_ROM.hex")
) sequencer_rw_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.afi_clk (afi_clk), // afi.afi_clk
.afi_reset_n (afi_reset_n), // .afi_reset_n
.afi_address (afi_address), // .afi_address
.afi_bank (afi_bank), // .afi_bank
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_cke (afi_cke), // .afi_cke
.afi_odt (afi_odt), // .afi_odt
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_dqs_en (afi_dqs_en), // .afi_dqs_en
.afi_mem_reset_n (afi_mem_reset_n), // .afi_mem_reset_n
.afi_wdata (afi_wdata), // .afi_wdata
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_dm (afi_dm), // .afi_dm
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.csr_clk (), // csr.csr_clk
.csr_ena (), // .csr_ena
.csr_dout_phy (), // .csr_dout_phy
.csr_dout () // .csr_dout
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram sequencer_ram (
.clk (clock_clk), // clk1.clk
.address (sequencer_ram_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (sequencer_ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (sequencer_ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (sequencer_ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (sequencer_ram_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (sequencer_ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (sequencer_ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_rom sequencer_rom (
.clk (clock_clk), // clk1.clk
.address (sequencer_rom_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (sequencer_rom_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (sequencer_rom_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (sequencer_rom_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (sequencer_rom_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (sequencer_rom_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.debugaccess (sequencer_rom_s1_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.byteenable (sequencer_rom_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst cpu_inst (
.clk (clock_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_inst_data_master_address), // data_master.address
.d_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.d_read (cpu_inst_data_master_read), // .read
.d_readdata (cpu_inst_data_master_readdata), // .readdata
.d_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.d_write (cpu_inst_data_master_write), // .write
.d_writedata (cpu_inst_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_inst_data_master_debugaccess), // .debugaccess
.i_address (cpu_inst_instruction_master_address), // instruction_master.address
.i_read (cpu_inst_instruction_master_read), // .read
.i_readdata (cpu_inst_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_inst_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_begintransfer (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.jtag_debug_module_byteenable (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_readdata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_select (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.jtag_debug_module_write (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_debugaccess (cpu_inst_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rom_s1_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rom_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_rom_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (sequencer_rom_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_rom_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_rom_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (sequencer_rom_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (sequencer_rom_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_debugaccess (sequencer_rom_s1_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_inst_jtag_debug_module_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_readdata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.av_byteenable (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_ram_s1_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_ram_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_ram_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (sequencer_ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (sequencer_ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (sequencer_ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rw_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_phy_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_data_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_ptr_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.PKT_BEGIN_BURST (66),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3)
) cpu_inst_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.PKT_BEGIN_BURST (66),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (7)
) cpu_inst_data_master_translator_avalon_universal_master_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_001_rsp_src_valid), // rp.valid
.rp_data (limiter_001_rsp_src_data), // .data
.rp_channel (limiter_001_rsp_src_channel), // .channel
.rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_001_rsp_src_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_rom_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_001_src_valid), // .valid
.cp_data (cmd_xbar_mux_001_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_001_src_channel), // .channel
.rf_sink_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_ram_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src2_valid), // .valid
.cp_data (cmd_xbar_demux_001_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src2_channel), // .channel
.rf_sink_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
.cp_data (cmd_xbar_demux_001_src3_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
.rf_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
.cp_data (cmd_xbar_demux_001_src6_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
.rf_sink_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_addr_router addr_router (
.sink_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_addr_router_001 addr_router_001 (
.sink_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router id_router (
.sink_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router id_router_001 (
.sink_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_002 (
.sink_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_003 (
.sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_004 (
.sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_005 (
.sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_006 (
.sink_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_007 (
.sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_TRANS_POSTED (56),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (0),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_TRANS_POSTED (56),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (0),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clock_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_demux cmd_xbar_demux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_mux cmd_xbar_mux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux rsp_xbar_demux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_002 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_003 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_004 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_005 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_006 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_007 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_mux rsp_xbar_mux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_irq_mapper irq_mapper (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sender_irq (cpu_inst_d_irq_irq) // sender.irq
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_4_V
`define SKY130_FD_SC_LS__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_4_V
|
// a FIFO buffer, provides a way of storing
// data from UART and can empty it later
module fifo
(
input wire clk,
input wire reset,
input wire rd,
input wire wr,
input wire [B-1:0] w_data,
output wire empty,
output wire full,
output wire [B-1:0] r_data
);
parameter B = 8; // number of bits
parameter W = 4; // number of address bits
reg [B-1:0] array_reg[2**W-1:0];
reg [W-1:0] w_ptr_reg, w_ptr_next;
reg [W-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire [W-1:0] w_ptr_succ, r_ptr_succ;
wire [1:0] wr_op;
wire wr_en;
integer i;
always @ (posedge clk, posedge reset) begin
if (reset) begin
for (i = 0; i <= 2**W-1; i = i+1)
array_reg[i] <= 0;
end
else begin
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
end
end
assign r_data = array_reg[r_ptr_reg];
assign wr_en = wr && !full_reg;
always @ (posedge clk, posedge reset) begin
if (reset) begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end
else begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
assign w_ptr_succ = w_ptr_reg + 1;
assign r_ptr_succ = r_ptr_reg + 1;
// state machine works as follows
// READ:, it checks
// if the queue is empty, if it is not
// it will increment the queue, otherwise it does nothing
// WRITE: it checks if the queue is full before writing,
// if it is, then it will just be a nop waiting
// READ/WRITE: if read and write happens at the same time,
// we increment the counter for both of them, since it is assume
// they will get the same data
assign wr_op = {wr, rd};
always @ (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg) begin
w_ptr_next <= w_ptr_reg;
r_ptr_next <= r_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg;
case (wr_op)
// nop
2'b00: begin
end
// read
2'b01: begin
if (!empty_reg) begin
r_ptr_next <= r_ptr_succ;
full_next <= 0;
if (r_ptr_succ == w_ptr_reg)
empty_next <= 1;
end
end
// write
2'b10: begin
if (!full_reg) begin
w_ptr_next <= w_ptr_succ;
empty_next <= 0;
if (w_ptr_succ == r_ptr_reg)
full_next <= 1;
end
end
// read/write
default: begin
w_ptr_next <= w_ptr_succ;
w_ptr_next <= r_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:28:24 03/24/2014
// Design Name:
// Module Name: decode
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*********************************************************************************
6 5 5 5 5 6
+---------+--------+--------+--------+--------+----------+
R-type format| Op-code | Rs | Rt | Rd | SA |Funct-code|
+---------+--------+--------+--------+--------+--------+-+
6 5 5 16
+---------+--------+--------+----------------------------+
I-type format| Op-code | Rs | Rt | 2's complement constant |
+---------+--------+--------+----------------------------+
6 26
+---------+----------------------------------------------+
J-type format| Op-code | jump_target |
+---------+----------------------------------------------+
^ ^
| |
bit 31 bit 0
*********************************************************************************/
module decode(/*AUTOARG*/
//Inputs
clk, ID_stall, inst_in, regrs_data, regrt_data, PCin,
//Outputs
PCout, ret_addr, aluc,op_a,op_b,op_sa,sign,nop, ssnop,jump, branch, rs, rt, rd,
load, store, move, load_op, store_op, move_op, regwrite, memread, memwrite, memaddr, memtoreg, regdst);
input clk;
input ID_stall;
input [31:0] inst_in;
reg [31:0] inst;
input [31:0] regrs_data, regrt_data;
input [31:0] PCin;
output reg [31:0] PCout, ret_addr;
//Alu
wire add, sub, mul, div, madd, msub;
wire [2:0] shift;
wire [3:0] _logic;
wire cmp;
wire [2:0] clzo;
output [20:0] aluc;
assign aluc = {add, sub, mul, div, madd, msub, shift, _logic, cmp, clzo};
output [31:0] op_a, op_b, op_sa;
output sign;
output reg [4:0] rs, rt, rd;
output nop, ssnop;
output jump;
output reg branch;
//output base, offset;
output load, store, move;
output wire [8:0] load_op;
output wire [5:0] store_op;
output wire [3:0] move_op;
output regwrite, memwrite, memread, memtoreg;
output [31:0] memaddr;
output [4:0] regdst;// write reg
wire [5:0] op = inst[31:26];
wire [5:0] func = inst[5:0];
wire cop0 = (op == 6'b010000);
wire imm_op = (op[5:3] == 3'b001);
wire regimm = (op == 6'b000001);
wire special = (op == 6'b000000);
wire special2 = (op == 6'b011100);
wire special3 = (op == 6'b011111);
//target_offset -> sign_extend(offset || 00)
//PC -> PC + target_offset
wire [15:0] offset = inst[15:0];
wire [31:0] target_offset = PCin + (offset[15] ? {14'h3fff, offset, 2'b00} : {14'h0000, offset, 2'b00});
assign memaddr = regrs_data + offset;
wire [31:0] immediate = inst[15] ? {16'hffff, inst[15:0]} : {16'b0, inst[15:0]};
assign op_a = (special | special2) ? regrt_data : immediate;
assign op_b = regrs_data;
assign op_sa = inst[10:6];
//PC -> PC[GPRLEN-1..28] || instr_index || 00
wire [25:0] inst_idx = inst[25:0];
assign add = (special && func[5:1]==5'b10000) || (op==5'b00100);
assign sub = (special && func[5:1]==5'b10001);
assign mul = (special2 & func == 6'b000010) || (special && func[5:1]==5'b01100);
assign div = (special && func[5:1]==5'b01101);
assign msub = (special2 && func[5:1]==5'b00010);
assign madd = (special2 && func[5:1]==5'b00000);
assign sign = (add && op[0]) || ((add | sub | mul | div| madd | msub)&&func[0]);
wire sll = (special && func == 6'b000000);
wire sllv = (special && func == 6'b000100);
wire sra = (special && func == 6'b000011);
wire srav = (special && func == 6'b000111);
wire srl = (special && func == 6'b000010);
wire srlv = (special && func == 6'b000110);
assign shift = {(sll|sllv), (sra|srav), (srl|srlv)};
wire _and = (special && func == 6'b100100);
wire _andi = (op == 6'b001100);
wire _or = (special && func == 6'b100101);
wire _ori = (op == 6'b001101);
wire _nor = (special && func == 6'b100111);
wire _xor = (special && func == 6'b100110);
wire _xori = (op == 6'b001110);
assign _logic = {_xor, _nor, (_and|_andi), (_or|_ori)};
// jump
wire j = op == 6'b000010;
wire jal = op == 6'b000011;
wire jalr = (special && func == 6'b001001);
wire jr = (special && func == 6'b001000);
//wire jump = (op[5:1] == 5'b00001) || (special && func[5:1] == 5'b00100);
//assign jump = {j, jal, jalr, jr};
assign jump = j | jal | jalr | jr;
// branch
wire b = (op == 6'b000100 && rs == 5'b00000 && rt == 5'b00000);
wire bal = (regimm && rs == 5'b00000 && rt == 5'b10001);
wire beq = op == 6'b000100;
wire beql = op == 6'b010100;
wire bgez = (regimm && rt == 5'b00001);
wire bgezal = (regimm && rt == 5'b10001);
wire bgezall = (regimm && rt == 5'b10011);
wire bgezl = (regimm && rt == 5'b00011);
wire bgtz = op == 6'b000111;
wire bgtzl = op == 6'b010111;
wire blez = op == 6'b000110;
wire blezl = op == 6'b010110;
wire bltz = (regimm && rt == 5'b00000);
wire bltzal = (regimm && rt == 5'b10000);
wire bltzall = (regimm && rt == 5'b10010);
wire bltzl = (regimm && rt == 5'b00010);
wire bne = op == 6'b000101;
wire bnel = op == 6'b010101;
//assign branch = b | bal | beq | beql | bgtz | bgtzl | blez | blezl | bne | bnel | regimm;
always @* begin
case ({b,bal,beq,beql,bgez,bgezal,bgezall,bgezl,bgtz,bgtzl,blez,blezl,bltz,bltzal,bltzall,bltzl,bne,bnel})
18'b10000000000000000 : branch <= 1; // b
18'b01000000000000000 : branch <= 1; // bal
// beq, beql
18'b00100000000000000 ,
18'b00010000000000000 : branch <= (regrs_data == regrt_data) ? 1 : 0;
// bgez,bgezal,bgezall,bgezl
18'b00001000000000000 , //begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
18'b00000100000000000 , //begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
18'b00000010000000000 , //begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
18'b00000001000000000 : begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
// blez,blezl
18'b00000000100000000 , //begin branch <= (regrs_data > 32'b0) ? 1 : 0; end
18'b00000000010000000 : begin branch <= (regrs_data > 32'b0) ? 1 : 0; end
// bltz,bltzal,bltzall,bltzl
18'b00000000001000000 , //begin branch <= (regrs_data <= 32'b0) ? 1 : 0; end
18'b00000000000100000 , //begin branch <= (regrs_data <= 32'b0) ? 1 : 0; end
18'b00000000000010000 , //begin branch <= (regrs_data < 32'b0) ? 1 : 0; end
18'b00000000000001000 , //begin branch <= (regrs_data < 32'b0) ? 1 : 0; end
18'b00000000000000100 : begin branch <= (regrs_data < 32'b0) ? 1 : 0; end
// bne, bnel
18'b00000000000000010 , //begin branch <= (regrs_data != regrt_data) ? 1 : 0; end
18'b00000000000000001 : begin branch <= (regrs_data != regrt_data) ? 1 : 0; end
endcase
end
wire break = (special && func == 6'b001101);
wire cache = op == 6'b101111;
wire clo = special2 && (func == 6'b100001);
wire clz = special2 && (func == 6'b100000);
assign cloz = {clz, clo};
// load
wire lb = (op == 6'b100000);
wire lbu = (op == 6'b100100);
wire lh = (op == 6'b100001);
wire lhu = (op == 6'b100101);
wire ll = (op == 6'b110000);
wire lui = (op == 6'b001111);
wire lw = (op == 6'b100011);
wire lwl = (op == 6'b100010);
wire lwr = (op == 6'b100110);
assign load = (lb | lbu | lh | lhu | ll | lui | lw | lwl | lwr);
assign load_op = {lb, lbu, lh, lhu, ll, lui, lw, lwl, lwr};
// store
wire sb = (op == 6'b101000);
wire sc = (op == 6'b111000);
wire sh = (op == 6'b101001);
wire sw = (op == 6'b101011);
wire swl = (op == 6'b101010);
wire swr = (op == 6'b101110);
assign store = (sb | sc | sh | sw | swl | swr);
assign store_op = {sb, sc, sh, sw, swl, swr};
// sync
wire sync = (special && func == 6'b001111);
wire stype = inst[10:6];
// trap
// teq teqi tge tgei tgeiu tgeu tlt tlti tltiu tltu tne tnei
wire teq = (special && func == 6'b110100);
wire teqi = (regimm && rt == 5'b01100);
wire tge = (special && func == 6'b110000);
wire tgei = (regimm && rt == 5'b01000);
wire tgeiu = (regimm && rt == 5'b01001);
wire tgeu = (special && func == 5'b11001);
wire tlt = (special && func == 6'b110010);
wire tlti = (regimm && rt == 5'b01010);
wire tltiu = (regimm && rt == 5'b01011);
wire tltu = (special && func == 6'b110011);
wire tne = (special && func == 6'b110110);
wire tnei = (regimm && rt == 5'b01110);
// wait
//wire _wait = (cop0 && co == 1 && func == 6'b100000);
// MFHI MFLO MOVN MOVZ MTHI MTLO
wire mfhi = (special && func == 6'b010000);
wire mflo = (special && func == 6'b010010);
wire movn = (special && func == 6'b001011);
wire movz = (special && func == 6'b001010);
assign move = (mfhi | mflo | movn | movz);
assign move_op = {mfhi, mflo, movn, movz};
// PREF PREFX to move data between memory and cache
// prefetch_memory(GPR[base] + offset)
// prefetch_memory(GPR[base] + GPR[index])
wire pref = (op == 6'b110011);
//wire prefx = (op == 6'b010011 && func == 6'b001111);
assign regwrite = (add|sub|(|shift)|(|_logic)|move|load|bal|bgezal|bgezall|bgezl|bltzal|bltzall|jal|jalr);
assign memwrite = store;
assign memread = load;
assign memtoreg = load;
assign regdst = (special && (op != 6'b001000)) ? rd : rt;
always @(posedge clk) begin
inst <= ID_stall ? inst : inst_in;
case ({ID_stall, j, jal, jalr, jr,branch})
6'b100000 : PCout <= PCin;
6'b010000 : PCout <= {PCin[31:28], inst_idx, 2'b00};
6'b001000 : PCout <= {PCin[31:28], inst_idx, 2'b00};
6'b000100 : PCout <= regrs_data;
6'b000010 : PCout <= regrs_data;
6'b000001 : PCout <= target_offset;
endcase
end
always @* begin
rs <= inst[25:21];
rt <= inst[20:16];
if (bal | bgezal | bgezall | bgezl | bltzal | bltzall | jal | jalr) begin
ret_addr <= PCin + 32'h0000008;
rd <= 5'b11111;
end else begin
rd <= inst[15:11];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_LP__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_BLACKBOX_V
|
module sha1_update(
input clk,
input start,
input [511:0] data_in,
input [159:0] hash_state_in,
output done,
output reg [159:0] hash_state_out
);
localparam IDLE = 2'd0;
localparam COMPRESSING = 2'd1;
localparam DONE = 2'd2;
reg [1:0] sm_state;
reg [1:0] sm_next_state;
reg [511:0] w;
wire [159:0] compression_state_loopback;
reg [ 31:0] w_roundi;
reg [ 6:0] round;
reg next_round;
wire [ 31:0] next_w;
initial begin
round = 7'd0;
w = 512'd0;
sm_state = IDLE;
end
sha1_compression rnd_compression(
.hash_state_in(hash_state_out),
.w(w_roundi),
.round(round),
.hash_state_out(compression_state_loopback)
);
assign next_w = w[511:480] ^ w[447:416] ^ w[255:224] ^ w[95:64];
assign done = sm_state == DONE;
always @ (*) begin
next_round = 1'b0;
case (sm_state)
IDLE : sm_next_state = start ? COMPRESSING : IDLE;
COMPRESSING : {sm_next_state, next_round} = round == 7'd79 ? {DONE, 1'b0} : {COMPRESSING, 1'b1};
DONE : sm_next_state = IDLE;
endcase
w_roundi = (round > 15) ? w[31:0] : w >> (10'd480 - (round << 5));
end
always @ (posedge clk) begin
if (start) begin
w <= data_in;
hash_state_out <= hash_state_in;
round <= 7'd0;
end
else begin
if (round >= 15) w <= {w[479:0], {next_w[30:0], next_w[31]}};
if (next_round) round <= round + 1'b1;
if (sm_next_state == DONE) begin
hash_state_out <= {
compression_state_loopback[159:128] + hash_state_in[159:128],
compression_state_loopback[127:96 ] + hash_state_in[127:96 ],
compression_state_loopback[ 95:64 ] + hash_state_in[ 95:64 ],
compression_state_loopback[ 63:32 ] + hash_state_in[ 63:32 ],
compression_state_loopback[ 31:0 ] + hash_state_in[ 31:0 ]
};
end
else hash_state_out <= compression_state_loopback;
end
sm_state <= sm_next_state;
end
endmodule
|
/* This file is part of jt51.
jt51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
jt51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with jt51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 7th 2017
*/
`timescale 1ns / 1ps
module jt51_fir_ram
#(parameter data_width=8, parameter addr_width=7)
(
input [(data_width-1):0] data,
input [(addr_width-1):0] addr,
input we, clk,
output [(data_width-1):0] q
);
(* ramstyle = "no_rw_check" *) reg [data_width-1:0] ram[2**addr_width-1:0];
reg [addr_width-1:0] addr_reg;
always @ (posedge clk) begin
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29455 $
// $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A synchronization module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Both assertion and deassertions is
// synchronized to the clock.
module PositiveReset (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
//(* keep = "true" *)
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, 1'b0} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK ) // reset is read synchronous with clock
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY -1 ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = 0 ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // PositiveReset
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* UDP arbitrated multiplexer
*/
module udp_arb_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* UDP frame inputs
*/
input wire [S_COUNT-1:0] s_udp_hdr_valid,
output wire [S_COUNT-1:0] s_udp_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*4-1:0] s_ip_version,
input wire [S_COUNT*4-1:0] s_ip_ihl,
input wire [S_COUNT*6-1:0] s_ip_dscp,
input wire [S_COUNT*2-1:0] s_ip_ecn,
input wire [S_COUNT*16-1:0] s_ip_length,
input wire [S_COUNT*16-1:0] s_ip_identification,
input wire [S_COUNT*3-1:0] s_ip_flags,
input wire [S_COUNT*13-1:0] s_ip_fragment_offset,
input wire [S_COUNT*8-1:0] s_ip_ttl,
input wire [S_COUNT*8-1:0] s_ip_protocol,
input wire [S_COUNT*16-1:0] s_ip_header_checksum,
input wire [S_COUNT*32-1:0] s_ip_source_ip,
input wire [S_COUNT*32-1:0] s_ip_dest_ip,
input wire [S_COUNT*16-1:0] s_udp_source_port,
input wire [S_COUNT*16-1:0] s_udp_dest_port,
input wire [S_COUNT*16-1:0] s_udp_length,
input wire [S_COUNT*16-1:0] s_udp_checksum,
input wire [S_COUNT*DATA_WIDTH-1:0] s_udp_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_udp_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_udp_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_udp_payload_axis_tready,
input wire [S_COUNT-1:0] s_udp_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_udp_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_udp_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [DATA_WIDTH-1:0] m_udp_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_udp_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_udp_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_udp_payload_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_udp_hdr_ready_reg = {S_COUNT{1'b0}}, s_udp_hdr_ready_next;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
reg [15:0] m_udp_source_port_reg = 16'd0, m_udp_source_port_next;
reg [15:0] m_udp_dest_port_reg = 16'd0, m_udp_dest_port_next;
reg [15:0] m_udp_length_reg = 16'd0, m_udp_length_next;
reg [15:0] m_udp_checksum_reg = 16'd0, m_udp_checksum_next;
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = (m_udp_payload_axis_tready_int_reg && grant_valid) << grant_encoded;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_udp_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_udp_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_udp_payload_axis_tvalid[grant_encoded];
wire current_s_tready = s_udp_payload_axis_tready[grant_encoded];
wire current_s_tlast = s_udp_payload_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_udp_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_udp_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_udp_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_udp_hdr_valid & ~grant;
assign acknowledge = grant & s_udp_payload_axis_tvalid & s_udp_payload_axis_tready & s_udp_payload_axis_tlast;
always @* begin
frame_next = frame_reg;
s_udp_hdr_ready_next = {S_COUNT{1'b0}};
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
m_udp_source_port_next = m_udp_source_port_reg;
m_udp_dest_port_next = m_udp_dest_port_reg;
m_udp_length_next = m_udp_length_reg;
m_udp_checksum_next = m_udp_checksum_reg;
if (s_udp_payload_axis_tvalid[grant_encoded] && s_udp_payload_axis_tready[grant_encoded]) begin
// end of frame detection
if (s_udp_payload_axis_tlast[grant_encoded]) begin
frame_next = 1'b0;
end
end
if (!frame_reg && grant_valid && (m_udp_hdr_ready || !m_udp_hdr_valid)) begin
// start of frame
frame_next = 1'b1;
s_udp_hdr_ready_next = grant;
m_udp_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48];
m_eth_type_next = s_eth_type[grant_encoded*16 +: 16];
m_ip_version_next = s_ip_version[grant_encoded*4 +: 4];
m_ip_ihl_next = s_ip_ihl[grant_encoded*4 +: 4];
m_ip_dscp_next = s_ip_dscp[grant_encoded*6 +: 6];
m_ip_ecn_next = s_ip_ecn[grant_encoded*2 +: 2];
m_ip_length_next = s_ip_length[grant_encoded*16 +: 16];
m_ip_identification_next = s_ip_identification[grant_encoded*16 +: 16];
m_ip_flags_next = s_ip_flags[grant_encoded*3 +: 3];
m_ip_fragment_offset_next = s_ip_fragment_offset[grant_encoded*13 +: 13];
m_ip_ttl_next = s_ip_ttl[grant_encoded*8 +: 8];
m_ip_protocol_next = s_ip_protocol[grant_encoded*8 +: 8];
m_ip_header_checksum_next = s_ip_header_checksum[grant_encoded*16 +: 16];
m_ip_source_ip_next = s_ip_source_ip[grant_encoded*32 +: 32];
m_ip_dest_ip_next = s_ip_dest_ip[grant_encoded*32 +: 32];
m_udp_source_port_next = s_udp_source_port[grant_encoded*16 +: 16];
m_udp_dest_port_next = s_udp_dest_port[grant_encoded*16 +: 16];
m_udp_length_next = s_udp_length[grant_encoded*16 +: 16];
m_udp_checksum_next = s_udp_checksum[grant_encoded*16 +: 16];
end
// pass through selected packet data
m_udp_payload_axis_tdata_int = current_s_tdata;
m_udp_payload_axis_tkeep_int = current_s_tkeep;
m_udp_payload_axis_tvalid_int = current_s_tvalid && m_udp_payload_axis_tready_int_reg && grant_valid;
m_udp_payload_axis_tlast_int = current_s_tlast;
m_udp_payload_axis_tid_int = current_s_tid;
m_udp_payload_axis_tdest_int = current_s_tdest;
m_udp_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
frame_reg <= frame_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
m_udp_source_port_reg <= m_udp_source_port_next;
m_udp_dest_port_reg <= m_udp_dest_port_next;
m_udp_length_reg <= m_udp_length_next;
m_udp_checksum_reg <= m_udp_checksum_next;
if (rst) begin
frame_reg <= 1'b0;
s_udp_hdr_ready_reg <= {S_COUNT{1'b0}};
m_udp_hdr_valid_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_udp_payload_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tkeep = KEEP_ENABLE ? m_udp_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tid = ID_ENABLE ? m_udp_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_udp_payload_axis_tdest = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_udp_payload_axis_tuser = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_udp_payload_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tkeep_reg <= temp_m_udp_payload_axis_tkeep_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tid_reg <= temp_m_udp_payload_axis_tid_reg;
m_udp_payload_axis_tdest_reg <= temp_m_udp_payload_axis_tdest_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A222OI_BEHAVIORAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_SYMBOL_V
`define SKY130_FD_SC_MS__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:58:10 03/31/2015
// Design Name:
// Module Name: pg_to_bpbg
// bproject Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pg_to_PG(
input [15:0] p,
input [15:0] g,
output [3:0] bp,
output [3:0] bg
);
assign bg[0]=g[3 ]|p[3 ]&g[2 ]|p[3 ]&p[2 ]&g[1 ]|p[3 ]&p[2 ]&p[1 ]&g[0 ],
bg[1]=g[7 ]|p[7 ]&g[6 ]|p[7 ]&p[6 ]&g[5 ]|p[7 ]&p[6 ]&p[5 ]&g[4 ],
bg[2]=g[11]|p[11]&g[10]|p[11]&p[10]&g[9 ]|p[11]&p[10]&p[9 ]&g[8 ],
bg[3]=g[15]|p[15]&g[14]|p[15]&p[14]&g[13]|p[15]&p[14]&p[13]&g[12];
assign bp[0]=p[3]&p[2]&p[1]&p[0],
bp[1]=p[7]&p[6]&p[5]&p[4],
bp[2]=p[11]&p[10]&p[9]&p[8],
bp[3]=p[15]&p[14]&p[13]&p[12];
endmodule
|
module vga( input pxl_clk,
input reset_n,
output reg [9:0] hcount,
output reg [9:0] vcount,
output reg vsync,
output reg hsync );
always @ (posedge pxl_clk or negedge reset_n)
begin : hcounter
if (!reset_n) hcount <= 0;
else if (hcount <= 799) hcount <= hcount + 1'b1;
else hcount <= 0;
end
always @ (posedge pxl_clk or negedge reset_n)
begin : vcounter
if (!reset_n) vcount <= 0;
else if (hcount == 799 && vcount <= 521) vcount <= vcount + 1'b1;
else if (vcount <= 521) vcount <= vcount;
else vcount <= 0;
end
/********************************
640 pixels video
16 pixels front porch
96 pixels horizontal sync
48 pixels back porch
*********************************/
always @ (hcount)
begin : hsync_decoder
if (hcount >= 656 && hcount <= 752) hsync <= 0;
else hsync <= 1;
end
/********************************
480 lines video
2 lines front porch
10 lines vertical sync
29 lines back porch
*********************************/
always @ (vcount)
begin : vsync_decoder
if (vcount >= 482 && vcount <= 492) vsync <= 0;
else vsync <= 1;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/13/2017 11:49:08 AM
// Design Name:
// Module Name: VICTIM_CACHE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VICTIM_CACHE #(
parameter BLOCK_WIDTH = 512 ,
parameter TAG_WIDTH = 26 ,
parameter MEMORY_LATENCY = "HIGH_LATENCY" ,
localparam MEMORY_DEPTH = 4 ,
localparam ADDRESS_WIDTH = clog2(MEMORY_DEPTH-1)
) (
input CLK ,
input [TAG_WIDTH - 1 : 0] WRITE_TAG_ADDRESS ,
input [BLOCK_WIDTH - 1 : 0] WRITE_DATA ,
input WRITE_ENABLE ,
input [TAG_WIDTH - 1 : 0] READ_TAG_ADDRESS ,
input READ_ENBLE ,
output READ_HIT ,
output [BLOCK_WIDTH - 1 : 0] READ_DATA
);
reg [TAG_WIDTH - 1 : 0] tag [MEMORY_DEPTH - 1 : 0] ;
reg [BLOCK_WIDTH - 1 : 0] memory [MEMORY_DEPTH - 1 : 0] ;
reg valid [MEMORY_DEPTH - 1 : 0] ;
reg read_hit_out_reg_1 ;
reg [BLOCK_WIDTH - 1 : 0] data_out_reg_1 ;
reg [ADDRESS_WIDTH - 1 : 0] record_counter ;
wire full ;
wire empty ;
assign full = ( record_counter == (MEMORY_DEPTH - 1) ) ;
assign empty = ( record_counter == 0 ) ;
integer i;
initial
begin
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
tag [ i ] = {TAG_WIDTH{1'b0}};
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
memory [ i ] = {BLOCK_WIDTH{1'b0}};
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
valid [ i ] = 1'b0;
record_counter = {ADDRESS_WIDTH{1'b0}} ;
read_hit_out_reg_1 = 1'b0 ;
data_out_reg_1 = {BLOCK_WIDTH{1'b0}} ;
end
always @(posedge CLK)
begin
if (WRITE_ENABLE & !full)
begin
tag [ record_counter ] <= WRITE_TAG_ADDRESS ;
memory [ record_counter ] <= WRITE_DATA ;
valid [ record_counter ] <= 1'b1 ;
record_counter <= record_counter + 1 ;
end
if (WRITE_ENABLE & full)
begin
for (i = 0; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
valid [ i ] <= valid [ i + 1 ] ;
end
tag [ record_counter ] <= WRITE_TAG_ADDRESS ;
memory [ record_counter ] <= WRITE_DATA ;
valid [ record_counter ] <= 1'b1 ;
end
if (READ_ENBLE & !empty)
begin
if( (tag [ 0 ] == READ_TAG_ADDRESS) & valid [ 0 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 0 ] ;
record_counter <= record_counter - 1 ;
for (i = 0; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 1 ] == READ_TAG_ADDRESS) & valid [ 1 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 1 ] ;
record_counter <= record_counter - 1 ;
for (i = 1; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 2 ] == READ_TAG_ADDRESS) & valid [ 2 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 2 ] ;
record_counter <= record_counter - 1 ;
for (i = 2; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 3 ] == READ_TAG_ADDRESS) & valid [ 3 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 3 ] ;
record_counter <= record_counter - 1 ;
for (i = 3; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else
begin
read_hit_out_reg_1 <= 1'b0 ;
data_out_reg_1 <= {BLOCK_WIDTH{1'b0}} ;
end
end
if (READ_ENBLE & empty)
begin
read_hit_out_reg_1 <= 1'b0 ;
data_out_reg_1 <= {BLOCK_WIDTH{1'b0}} ;
end
end
generate
if (MEMORY_LATENCY == "LOW_LATENCY")
begin
assign READ_HIT = read_hit_out_reg_1 ;
assign READ_DATA = data_out_reg_1 ;
end
else
begin
reg read_hit_out_reg_2 = 1'b0 ;
reg [BLOCK_WIDTH - 1 :0] data_out_reg_2 = {BLOCK_WIDTH{1'b0}} ;
initial
begin
read_hit_out_reg_2 <= 1'b0 ;
data_out_reg_2 <= {BLOCK_WIDTH{1'b0}} ;
end
always @(posedge CLK)
begin
if (READ_ENBLE)
begin
read_hit_out_reg_2 <= read_hit_out_reg_1 ;
data_out_reg_2 <= data_out_reg_1 ;
end
end
assign READ_HIT = read_hit_out_reg_2 ;
assign READ_DATA = data_out_reg_2 ;
end
endgenerate
function integer clog2;
input integer depth;
for (clog2 = 0; depth > 0; clog2 = clog2 + 1)
depth = depth >> 1;
endfunction
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:zbroji:1.0
// IP Revision: 1405201610
(* X_CORE_INFO = "zbroji_top,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "ZynqDesign_zbroji_0_0,zbroji_top,{}" *)
(* CORE_GENERATION_INFO = "ZynqDesign_zbroji_0_0,zbroji_top,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=zbroji,x_ipVersion=1.0,x_ipCoreRevision=1405201610,x_ipLanguage=VHDL,C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH=6,C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ZynqDesign_zbroji_0_0 (
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB,
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY,
interrupt,
aclk,
aresetn
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWADDR" *)
input wire [5 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WDATA" *)
input wire [31 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WSTRB" *)
input wire [3 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BRESP" *)
output wire [1 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BVALID" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BREADY" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARADDR" *)
input wire [5 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RDATA" *)
output wire [31 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RRESP" *)
output wire [1 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RVALID" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RREADY" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
input wire aresetn;
zbroji_top #(
.C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH(6),
.C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH(32)
) inst (
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR),
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB(s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY),
.interrupt(interrupt),
.aclk(aclk),
.aresetn(aresetn)
);
endmodule
|
`default_nettype none
`include "processor.h"
module interrupt_control(
//System
input wire iCLOCK,
input wire inRESET,
//Interrupt Configlation Table
input wire iICT_VALID,
input wire [5:0] iICT_ENTRY,
input wire iICT_CONF_MASK,
input wire iICT_CONF_VALID,
input wire [1:0] iICT_CONF_LEVEL,
//Core Info
input wire [31:0] iSYSREGINFO_PSR,
//External
input wire iEXT_ACTIVE,
input wire [5:0] iEXT_NUM,
output wire oEXT_ACK,
//output oEXT_BUSY,
//Core-ALU
input wire iFAULT_ACTIVE,
input wire [6:0] iFAULT_NUM,
input wire [31:0] iFAULT_FI0R,
input wire [31:0] iFAULT_FI1R,
///To Exception Manager
input wire iEXCEPTION_LOCK,
output wire oEXCEPTION_ACTIVE,
output wire [6:0] oEXCEPTION_IRQ_NUM,
output wire [31:0] oEXCEPTION_IRQ_FI0R,
output wire [31:0] oEXCEPTION_IRQ_FI1R,
input wire iEXCEPTION_IRQ_ACK
);
localparam STT_IDLE = 2'h0;
localparam STT_COMP_WAIT = 2'h1;
/****************************************************
Register and Wire
***************************************************/
//Interrupt Valid
wire software_interrupt_valid;
wire hardware_interrupt_valid;
//Interrupt Config Table
reg ict_conf_mask[0:63];
reg ict_conf_valid[0:63];
reg [1:0] ict_conf_level[0:63];
//Instruction State
reg [1:0] b_state;
reg [6:0] b_irq_num;
reg b_irq_type;
reg b_irq_ack;
reg [31:0] b_irq_fi0r;
reg [31:0] b_irq_fi1r;
//Generate
integer i;
/****************************************************
Instruction Config Table
***************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_valid [i] = 1'b0;
end
if(`PROCESSOR_DATA_RESET_EN)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_mask [i] = 1'b0;
ict_conf_level [i] = 2'h0;
end
end
end
else begin
if(iICT_VALID)begin
ict_conf_mask [iICT_ENTRY] <= iICT_CONF_MASK;
ict_conf_valid [iICT_ENTRY] <= iICT_CONF_VALID;
ict_conf_level [iICT_ENTRY] <= iICT_CONF_LEVEL;
end
end
end
assign software_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iFAULT_ACTIVE;
assign hardware_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM]));
//Hardware Irq Latch
reg b_hw_irq_valid;
reg [6:0] b_hw_irq_num;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_hw_irq_valid <= 1'b0;
b_hw_irq_num <= 7'h0;
end
else begin
if(!b_hw_irq_valid)begin
if(iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM])))begin
b_hw_irq_valid <= 1'b1;
b_hw_irq_num <= {1'b0, iEXT_NUM};
end
end
else begin
if(!software_interrupt_valid && b_state == STT_IDLE && !iEXCEPTION_LOCK)begin
b_hw_irq_valid <= 1'b0;
end
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= STT_IDLE;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_state <= STT_COMP_WAIT;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b1;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_state <= STT_COMP_WAIT;
b_irq_type <= 1'b1;
b_irq_ack <= 1'b1;
end
end
STT_COMP_WAIT :
begin
b_irq_ack <= 1'b0;
if(iEXCEPTION_IRQ_ACK)begin
b_state <= STT_IDLE;
end
end
default :
begin
b_state <= STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_num <= {7{1'b0}};
b_irq_fi0r <= 32'h0;
b_irq_fi1r <= 32'h0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_irq_num <= iFAULT_NUM;
b_irq_fi0r <= iFAULT_FI0R;
b_irq_fi1r <= iFAULT_FI1R;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_irq_num <= b_hw_irq_num;
b_irq_fi0r <= 32'h0;
b_irq_fi1r <= 32'h0;
end
end
default :
begin
b_irq_num <= b_irq_num;
b_irq_fi0r <= b_irq_fi0r;
b_irq_fi1r <= b_irq_fi1r;
end
endcase
end
end
assign oEXT_ACK = b_irq_ack && b_irq_type;//(b_state == `STT_COMP_WAIT && !software_interrupt_valid)? hardware_interrupt_valid : 1'b0;
assign oEXCEPTION_ACTIVE = (b_state == STT_COMP_WAIT)? !iEXCEPTION_IRQ_ACK : software_interrupt_valid || hardware_interrupt_valid || b_hw_irq_valid;//(b_state == `STT_COMP_WAIT)? !iFREE_IRQ_SETCONDITION : software_interrupt_valid || hardware_interrupt_valid;
assign oEXCEPTION_IRQ_NUM = (b_state == STT_COMP_WAIT)? b_irq_num : ((software_interrupt_valid)? iFAULT_NUM : {1'b0, iEXT_NUM});
assign oEXCEPTION_IRQ_FI0R = b_irq_fi0r;
assign oEXCEPTION_IRQ_FI1R = b_irq_fi1r;
endmodule
`default_nettype wire
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=125 clk0_duty_cycle=50 clk0_multiply_by=8 clk0_phase_shift="0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=adc_pll" operation_mode="no_compensation" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_adc_pll_adc_pll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module adc_pll_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 125,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 8,
pll1.clk0_phase_shift = "0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "no_compensation",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //adc_pll_altpll
//VALID FILE
|
/* Simple external interrupt controller for MIPSfpga+ system
* managed using AHB-Lite bus
* Copyright(c) 2017 Stanislav Zhelnio
* https://github.com/zhelnio/ahb_lite_eic
*/
`include "mfp_eic_core.vh"
//reg width params
`define EIC_EICR_WIDTH 1 // control register width
`define EIC_ALIGNED_WIDTH 64 // summary total aligned reg width
//new_reg_value module commands
`define EIC_C_NONE 3'b000 //no changes
`define EIC_C_CLR0 3'b001 //clear all in word0
`define EIC_C_CLR1 3'b010 //clear all in word1
`define EIC_C_SET0 3'b011 //set all in word0
`define EIC_C_SET1 3'b100 //set all in word1
`define EIC_C_VAL0 3'b101 //set word0
`define EIC_C_VAL1 3'b110 //set word1
`define EIC_C_CLRA 3'b111 //clear all
// reg bits
`define EICR_EE 1'b0 //EIC enabled
module mfp_eic_core
(
input CLK,
input RESETn,
//signal inputs (should be synchronized!)
input [ `EIC_CHANNELS - 1 : 0 ] signal,
//register access
input [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr,
output reg [ 31 : 0 ] read_data,
input [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr,
input [ 31 : 0 ] write_data,
input write_enable,
//EIC processor interface
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present,
input EIC_IAck,
input [ 7 : 0 ] EIC_IPL,
input [ 5 : 0 ] EIC_IVN,
input [ 17 : 1 ] EIC_ION
);
//registers interface part
wire [ 31 : 0 ] EICR;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIMSK;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIFR;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EISMSK;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIIPR;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIACM;
//register involved part
reg [ `EIC_EICR_WIDTH - 1 : 0 ] EICR_inv;
reg [ `EIC_CHANNELS - 1 : 0 ] EIMSK_inv;
reg [ 2*`EIC_SENSE_CHANNELS - 1 : 0 ] EISMSK_inv;
wire [ `EIC_CHANNELS - 1 : 0 ] EIFR_inv;
reg [ `EIC_CHANNELS - 1 : 0 ] EIACM_inv;
//register align and combination
assign EIMSK = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, EIMSK_inv };
assign EISMSK = { { `EIC_ALIGNED_WIDTH - 2*`EIC_SENSE_CHANNELS { 1'b0 } }, EISMSK_inv};
assign EIFR = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, EIFR_inv };
assign EIIPR = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, signal };
assign EIACM = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, EIACM_inv };
assign EICR = { { 32 - `EIC_EICR_WIDTH { 1'b0 } }, EICR_inv };
assign EIC_Present = EICR_inv[`EICR_EE];
//register read operations
always @ (*)
case(read_addr)
default : read_data = 32'b0;
`EIC_REG_EICR : read_data = EICR;
`EIC_REG_EIMSK_0 : read_data = EIMSK [ 31:0 ];
`EIC_REG_EIMSK_1 : read_data = EIMSK [ 63:32 ];
`EIC_REG_EIFR_0 : read_data = EIFR [ 31:0 ];
`EIC_REG_EIFR_1 : read_data = EIFR [ 63:32 ];
`EIC_REG_EIFRS_0 : read_data = 32'b0;
`EIC_REG_EIFRS_1 : read_data = 32'b0;
`EIC_REG_EIFRC_0 : read_data = 32'b0;
`EIC_REG_EIFRC_1 : read_data = 32'b0;
`EIC_REG_EISMSK_0 : read_data = EISMSK [ 31:0 ];
`EIC_REG_EISMSK_1 : read_data = EISMSK [ 63:32 ];
`EIC_REG_EIIPR_0 : read_data = EIIPR [ 31:0 ];
`EIC_REG_EIIPR_1 : read_data = EIIPR [ 63:32 ];
`EIC_REG_EIACM_0 : read_data = EIACM [ 31:0 ];
`EIC_REG_EIACM_1 : read_data = EIACM [ 63:32 ];
endcase
//register write operations
wire [ `EIC_CHANNELS - 1 : 0 ] EIFR_wr_data;
wire [ `EIC_CHANNELS - 1 : 0 ] EIFR_wr_enable;
wire [ `EIC_CHANNELS - 1 : 0 ] EIMSK_new;
wire [ `EIC_CHANNELS - 1 : 0 ] EISMSK_new;
wire [ `EIC_EICR_WIDTH - 1 : 0 ] EICR_new;
wire [ `EIC_CHANNELS - 1 : 0 ] EIACM_new;
reg [ 17 : 0 ] write_cmd;
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIFR_dt (.in(EIFR_inv), .out(EIFR_wr_data), .word(write_data), .cmd(write_cmd[ 2:0 ]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIFR_wr (.in(EIFR_inv), .out(EIFR_wr_enable), .word(write_data), .cmd(write_cmd[ 5:3 ]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIMSK (.in(EIMSK_inv), .out(EIMSK_new), .word(write_data), .cmd(write_cmd[ 8:6 ]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EISMSK (.in(EISMSK_inv), .out(EISMSK_new), .word(write_data), .cmd(write_cmd[11:9 ]));
new_reg_value #(.USED(`EIC_EICR_WIDTH)) nrv_EICR (.in(EICR_inv), .out(EICR_new), .word(write_data), .cmd(write_cmd[14:12]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIACM (.in(EIACM_inv), .out(EIACM_new), .word(write_data), .cmd(write_cmd[17:15]));
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] __write_addr = write_enable ? write_addr : `EIC_REG_NONE;
always @ (*) begin
case(__write_addr)
default : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EICR : write_cmd = { `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIMSK_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIMSK_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIFR_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_SET0, `EIC_C_VAL0 };
`EIC_REG_EIFR_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_SET1, `EIC_C_VAL1 };
`EIC_REG_EIFRS_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_VAL0 };
`EIC_REG_EIFRS_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_VAL1 };
`EIC_REG_EIFRC_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_CLR0 };
`EIC_REG_EIFRC_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_CLR1 };
`EIC_REG_EISMSK_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EISMSK_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIACM_0 : write_cmd = { `EIC_C_VAL0, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIACM_1 : write_cmd = { `EIC_C_VAL1, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
endcase
end
always @ (posedge CLK)
if(~RESETn) begin
EIMSK_inv <= { `EIC_CHANNELS { 1'b0 } };
EISMSK_inv <= { `EIC_CHANNELS { 1'b0 } };
EICR_inv <= { `EIC_EICR_WIDTH { 1'b0 } };
EIACM_inv <= { `EIC_CHANNELS { 1'b0 } };
end
else
case(__write_addr)
default : ;
`EIC_REG_EICR : EICR_inv <= EICR_new;
`EIC_REG_EIMSK_0 : EIMSK_inv <= EIMSK_new;
`EIC_REG_EIMSK_1 : EIMSK_inv <= EIMSK_new;
`EIC_REG_EISMSK_0 : EISMSK_inv <= EISMSK_new;
`EIC_REG_EISMSK_1 : EISMSK_inv <= EISMSK_new;
`EIC_REG_EIACM_0 : EIACM_inv <= EIACM_new;
`EIC_REG_EIACM_1 : EIACM_inv <= EIACM_new;
endcase
//current interrupt processing by CPU (EIC_IVN, EIC_ION -> irqNumberCur, irqFlagCur)
wire [ 7 : 0 ] irqNumberCur;
wire [ `EIC_CHANNELS - 1 : 0 ] irqFlagCur = (1 << irqNumberCur);
handler_params_decoder handler_params_decoder
(
.irqVector ( EIC_IVN ),
.irqOffset ( EIC_ION ),
.irqNumber ( irqNumberCur )
);
// auto clear flag logic
wire [ `EIC_CHANNELS - 1 : 0 ] requestWR = EIC_IAck ? EIFR_wr_enable | (EIACM_inv & irqFlagCur)
: EIFR_wr_enable;
wire [ `EIC_CHANNELS - 1 : 0 ] requestIn = EIC_IAck ? EIFR_wr_data & ~(EIACM_inv & irqFlagCur)
: EIFR_wr_data;
//interrupt input logic (signal -> request)
wire [ `EIC_SENSE_CHANNELS - 1 : 0 ] sensed;
wire [ `EIC_CHANNELS - 1 : 0 ] mask = EICR_inv[`EICR_EE] ? EIMSK_inv
: { `EIC_CHANNELS {1'b0}};
generate
genvar i, j;
for (i = 0; i < `EIC_SENSE_CHANNELS; i = i + 1)
begin : sirq
interrupt_sence sense
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.senceMask ( EISMSK_inv [ (1+i*2):(i*2) ] ),
.signalIn ( signal [i] ),
.signalOut ( sensed [i] )
);
interrupt_channel channel
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.signalMask ( mask [i] ),
.signalIn ( sensed [i] ),
.requestWR ( requestWR [i] ),
.requestIn ( requestIn [i] ),
.requestOut ( EIFR_inv [i] )
);
end
for (j = `EIC_SENSE_CHANNELS; j < `EIC_CHANNELS; j = j + 1)
begin : irq
interrupt_channel channel
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.signalMask ( mask [j] ),
.signalIn ( signal [j] ),
.requestWR ( requestWR [j] ),
.requestIn ( requestIn [j] ),
.requestOut ( EIFR_inv [j] )
);
end
endgenerate
//interrupt priority decode (EIFR -> irqNumber)
wire irqDetected;
wire [ 5 : 0 ] irqNumberL;
wire [ 7 : 0 ] irqNumber = { 2'b0, irqNumberL };
priority_encoder64 priority_encoder //use priority_encoder255 for more interrupt inputs
(
.in ( EIFR ),
.detect ( irqDetected ),
.out ( irqNumberL )
);
//interrupt priority encode (irqNumber -> handler_params)
handler_params_encoder handler_params_encoder
(
.irqNumber ( irqNumber ),
.irqDetected ( irqDetected ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector )
);
endmodule
//helper for partialy updating register value
module new_reg_value
#(
parameter USED = 8
)
(
input [ USED - 1 : 0 ] in, //input value
output reg [ USED - 1 : 0 ] out, //output value
input [ 31 : 0 ] word, //new data value
input [ 2 : 0 ] cmd //update command (see EIC_C_* defines)
);
localparam BYTE1_SIZE = (USED > 32) ? (USED - 32) : 0;
localparam BYTE1_MAX = (BYTE1_SIZE > 0) ? (BYTE1_SIZE - 1) : 0;
localparam BYTE1_START = (BYTE1_SIZE > 0) ? 32 : 0;
localparam BYTE1_END = (BYTE1_SIZE > 0) ? (USED - 1) : 0;
always @ (*) begin
if(USED < 33)
case(cmd)
default : out = in;
`EIC_C_CLR0 : out = { USED {1'b0} };
`EIC_C_CLR1 : out = in;
`EIC_C_SET0 : out = { USED {1'b1} };
`EIC_C_SET1 : out = in;
`EIC_C_VAL0 : out = word [ USED - 1 : 0 ];
`EIC_C_VAL1 : out = in;
`EIC_C_CLRA : out = { USED {1'b0} };
endcase
else
case(cmd)
default : out = in;
`EIC_C_CLR0 : out = { in [ BYTE1_END : BYTE1_START ], 32'b0 };
`EIC_C_CLR1 : out = { { BYTE1_SIZE { 1'b0 } }, in [ 31 : 0 ] };
`EIC_C_SET0 : out = { in [ BYTE1_END : BYTE1_START ], ~32'b0 };
`EIC_C_SET1 : out = { { BYTE1_SIZE { 1'b1 } }, in [ 31 : 0 ] };
`EIC_C_VAL0 : out = { in [ BYTE1_END : BYTE1_START ], word };
`EIC_C_VAL1 : out = { word [ BYTE1_MAX : 0 ], in [ 31 : 0 ] };
`EIC_C_CLRA : out = { USED {1'b0} };
endcase
end
endmodule
//single interrupt channel
module interrupt_channel
(
input CLK,
input RESETn,
input signalMask, // Interrupt mask (0 - disabled, 1 - enabled)
input signalIn, // Interrupt intput signal
input requestWR, // forced interrupt flag change
input requestIn, // forced interrupt flag value
output reg requestOut // interrupt flag
);
wire request = requestWR ? requestIn :
(signalMask & signalIn | requestOut);
always @ (posedge CLK)
if(~RESETn)
requestOut <= 1'b0;
else
requestOut <= request;
endmodule
//Interrupt sense control
module interrupt_sence
(
input CLK,
input RESETn,
input [1:0] senceMask,
input signalIn,
output reg signalOut
);
// senceMask:
parameter MASK_LOW = 2'b00, // The low level of signalIn generates an interrupt request
MASK_ANY = 2'b01, // Any logical change on signalIn generates an interrupt request
MASK_FALL = 2'b10, // The falling edge of signalIn generates an interrupt request
MASK_RIZE = 2'b11; // The rising edge of signalIn generates an interrupt request
parameter S_RESET = 0,
S_INIT0 = 1,
S_INIT1 = 2,
S_WORK = 3;
reg [ 1 : 0 ] State, Next;
reg [ 1 : 0 ] signal;
always @ (posedge CLK)
if(~RESETn)
State <= S_INIT0;
else
State <= Next;
always @ (posedge CLK)
case(State)
S_RESET : signal <= 2'b0;
default : signal <= { signal[0], signalIn };
endcase
always @ (*) begin
case (State)
S_RESET : Next = S_INIT0;
S_INIT0 : Next = S_INIT1;
default : Next = S_WORK;
endcase
case( { State, senceMask } )
{ S_WORK, MASK_LOW } : signalOut = ~signal[1] & ~signal[0];
{ S_WORK, MASK_ANY } : signalOut = signal[1] ^ signal[0];
{ S_WORK, MASK_FALL } : signalOut = signal[1] & ~signal[0];
{ S_WORK, MASK_RIZE } : signalOut = ~signal[1] & signal[0];
default : signalOut = 1'b0;
endcase
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: drom32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module drom32 (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../rom_data.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../rom_data.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module top_model (
input [7:0] input_8_bit,
input reset_n,
output decimal_point,
output [6:0] segments,
output [2:0] digit,
output CS_o,
output RD_o,
output WR_o
);
integer digital_value;
wire clk;
wire clk_slow;
reg [3:0] units_place;
reg [3:0] tens_place;
reg [3:0] hundreds_place;
reg [3:0] thousands_place;
wire [3:0] data_o;
//digital to analog conversion
always@(*) begin
digital_value = input_8_bit;// * (5000 / 255); //convert from 0-255 to 0volts to 5volts
thousands_place = (((digital_value * 5000) / 255) % 10000) / 1000;
hundreds_place = (((digital_value * 5000) / 255) % 1000) / 100;
tens_place = (((digital_value * 5000) / 255) % 100) / 10;
units_place = ((digital_value * 5000) / 255) % 10;
end
//This is an instance of a special, built in module that accesses the chip's oscillator
//"2.08" specifies the operating frequency, 2.03 MHz. Other clock frequencies can be found in the MachX02's documentation
OSCH #("2.08") osc_int (
.STDBY(1'b0), //Specifies active state
.OSC(clk), //Outputs clock signal to 'clk' net
.SEDSTDBY() //Leaves SEDSTDBY pin unconnected
);
clock_counter divider1 (
.reset_n(reset_n),
.clk_i(clk),
.clk_o(clk_slow)
);
ADCinterface ADC1 (
.clk(clk),
.reset_n(reset_n),
.CS_n(CS_o),
.RD_n(RD_o),
.WR_n(WR_o)
);
digit_state_machine DSM1 (
.units(units_place),
.tens(tens_place),
.hundreds(hundreds_place),
.thousands(thousands_place),
.reset_n(reset_n),
.clk(clk_slow),
.digit_select(digit),
.data(data_o),
.decimal_point(decimal_point)
);
decoder d1(
.data(data_o),
.segments(segments)
);
endmodule
|
// megafunction wizard: %RAM: 3-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt3pram
// ============================================================
// File Name: IMG_TRI_BUFFER.v
// Megafunction Name(s):
// alt3pram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module IMG_TRI_BUFFER (
data,
rdaddress_a,
rdaddress_b,
rdclock,
wraddress,
wrclock,
wren,
qa,
qb);
input [7:0] data;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [7:0] qa;
output [7:0] qb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRqa NUMERIC "0"
// Retrieval info: PRIVATE: CLRqb NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"
// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGqa NUMERIC "1"
// Retrieval info: PRIVATE: REGqb NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"
// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"
// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"
// Retrieval info: PRIVATE: REGwrite NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden_a NUMERIC "0"
// Retrieval info: PRIVATE: rden_b NUMERIC "0"
// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF"
// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "OUTCLOCK"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "OUTCLOCK"
// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "OUTCLOCK"
// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "OUTCLOCK"
// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD NUMERIC "11"
// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF"
// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: qa 0 0 8 0 OUTPUT NODEFVAL qa[7..0]
// Retrieval info: USED_PORT: qb 0 0 8 0 OUTPUT NODEFVAL qb[7..0]
// Retrieval info: USED_PORT: rdaddress_a 0 0 11 0 INPUT NODEFVAL rdaddress_a[10..0]
// Retrieval info: USED_PORT: rdaddress_b 0 0 11 0 INPUT NODEFVAL rdaddress_b[10..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL wraddress[10..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: qa 0 0 8 0 @qa 0 0 8 0
// Retrieval info: CONNECT: qb 0 0 8 0 @qb 0 0 8 0
// Retrieval info: CONNECT: @wraddress 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @rdaddress_a 0 0 11 0 rdaddress_a 0 0 11 0
// Retrieval info: CONNECT: @rdaddress_b 0 0 11 0 rdaddress_b 0 0 11 0
// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
module test_bsg
#(parameter width_p=4,
parameter output_width_p=2*width_p-1,
parameter cycle_time_p=10,
parameter reset_cycles_lo_p=-1,
parameter reset_cycles_hi_p=-1
);
wire clk_lo;
logic reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk_lo)
, .async_reset_o(reset)
);
logic [31:0] ctr;
always @(posedge clk_lo)
if (reset)
ctr <= '0;
else
ctr <= ctr + 1'b1;
wire [output_width_p-1:0] res;
bsg_adder_one_hot #(.width_p(width_p),.output_width_p(output_width_p))
foo (.a_i(1'b1 << ctr[1:0]), .b_i(1'b1 << ctr[3:2]), .o(res));
always @(negedge clk_lo)
begin
$display("%b %b -> %b\n", 1 << ctr[1:0], 1 << ctr[3:2], res);
if (ctr == 5'b10000)
$finish();
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_BLACKBOX_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_4_V
`define SKY130_FD_SC_LS__O21AI_4_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_4_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table1_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#50
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:23:22 10/18/2015
// Design Name:
// Module Name: fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo
#(
B = 8, //Num of bits in data word
W = 4 //Num addr bits of FIFO
//Num words in FIFO=2^FIFO_W
)
(
input wire clk, reset,
input wire wr, rd,
input wire [B-1:0] w_data,
output wire full, empty,
output wire [B-1:0] r_data
);
//signal declaration
reg [B-1:0] array_reg [0:2**W-1]; //register array
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
//body
//register file write operation
always @(posedge clk)
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
//register file read operation
assign r_data = array_reg[r_ptr_reg];
//write enable only when FIFO is not full
assign wr_en = wr & ~full_reg;
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset)
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next; //Indice para leer el sig bit
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
//next-state logic for read and write pointers
always @*
begin
//successive pointer values
w_ptr_succ = w_ptr_reg + 4'b0001;
r_ptr_succ = r_ptr_reg + 4'b0001;
// default: keep old values
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
// 2'b00: no op
2'b01: //read
if (~empty_reg) //not empty
begin
r_ptr_next = r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: //write
if (~full_reg) //not full
begin
w_ptr_next = w_ptr_succ;
empty_next = 1'b0;
if (w_ptr_succ==r_ptr_reg)
full_next = 1'b1;
end
2'b11: //write and read
begin
w_ptr_next = w_ptr_succ;
r_ptr_next = r_ptr_succ;
end
endcase
end
//output
assign full = full_reg;
assign empty = empty_reg;
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 1
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam IDLE = 4'h0;
localparam EXECUTE = 4'h1;
localparam RESET = 4'h2;
localparam PING_RESPONSE = 4'h3;
localparam WRITE_DATA = 4'h4;
localparam WRITE_RESPONSE = 4'h5;
localparam GET_WRITE_DATA = 4'h6;
localparam READ_RESPONSE = 4'h7;
localparam READ_MORE_DATA = 4'h8;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_bram s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(2);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
execute_command <= 1;
end //while command is not finished
while (command_finished) begin
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count > 0) begin
timeout_count <= timeout_count - 1;
end
if (execute_command && timeout_count == 0) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
state <= IDLE;
command_finished <= 1;
timeout_count <= `TIMEOUT_COUNT;
data_write_count <= 1;
end //end reached the end of a timeout
case (state)
IDLE: begin
if (execute_command & ~command_finished) begin
$display ("TB: #:C:A:D = %h:%h:%h:%h", r_in_data_count, r_in_command, r_in_address, r_in_data);
timeout_count <= `TIMEOUT_COUNT;
state <= EXECUTE;
end
end
EXECUTE: begin
if (w_master_ready) begin
//send the command over
r_in_ready <= 1;
case (r_in_command & 32'h0000FFFF)
0: begin
//ping
state <= PING_RESPONSE;
end
1: begin
//write
if (r_in_data_count > 1) begin
$display ("TB: \tWrote double word %d: %h", data_write_count, r_in_data);
state <= WRITE_DATA;
timeout_count <= `TIMEOUT_COUNT;
data_write_count <= data_write_count + 1;
end
else begin
if (data_write_count > 1) begin
$display ("TB: \tWrote double word %d: %h", data_write_count, r_in_data);
end
state <= WRITE_RESPONSE;
end
end
2: begin
//read
state <= READ_RESPONSE;
end
3: begin
//reset
state <= RESET;
end
endcase
end
end
RESET: begin
//reset the system
r_ih_reset <= 1;
command_finished <= 1;
state <= IDLE;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000000))) begin
$display ("TB: Read a successful ping reponse");
end
else begin
$display ("TB: Ping response is incorrect!");
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
command_finished <= 1;
state <= IDLE;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000001))) begin
$display ("TB: Read a successful write reponse");
end
else begin
$display ("TB: Write response is incorrect!");
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= IDLE;
command_finished <= 1;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
//XXX: should request more data be a strobe?
request_more_data <= 0;
r_in_ready <= 1;
r_in_data_count <= r_in_data_count -1;
state <= EXECUTE;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000002))) begin
$display ("TB: Read a successful read response");
if (w_out_data_count > 0) begin
state <= READ_MORE_DATA;
//reset the NACK timeout
timeout_count <= `TIMEOUT_COUNT;
end
else begin
state <= IDLE;
command_finished <= 1;
end
end
else begin
$display ("TB: Read response is incorrect");
command_finished <= 1;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
r_out_ready <= 0;
if (w_out_status == (~(32'h00000002))) begin
$display ("TB: Read a 32bit data packet");
$display ("Tb: \tRead Data: %h", w_out_data);
end
else begin
$display ("TB: Read reponse is incorrect");
end
//read the output data count to determine if there is more data
if (w_out_data_count == 0) begin
state <= IDLE;
command_finished <= 1;
end
end
end
default: begin
$display ("TB: state is wrong");
state <= IDLE;
end //somethine wrong here
endcase //state machine
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
endmodule
|
module muladd_wrap (
input ck,
input rst,
input [63:0] i_a, i_b, i_c, //a + b * c
input i_vld,
output o_rdy,
output [63:0] o_res,
output o_vld
);
parameter ENTRY_DEPTH = 32;
wire ef_afull;
wire ef_pop;
wire ef_empty;
wire [63:0] ef_a, ef_b, ef_c;
fifo #(
.WIDTH(64+64+64),
.DEPTH(ENTRY_DEPTH),
.PIPE(1),
.AFULLCNT(ENTRY_DEPTH - 2)
) entry_fifo (
.clk(ck),
.reset(rst),
.push(i_vld),
.din({i_a, i_b, i_c}),
.afull(ef_afull),
.oclk(ck),
.pop(ef_pop),
.dout({ef_a, ef_b, ef_c}),
.empty(ef_empty)
);
wire mult_rdy;
wire [63:0] mult_res;
wire mult_vld;
assign ef_pop = !ef_empty & mult_rdy;
// Black box instantiation
mul_64b_dp multiplier (.clk(ck), .a(ef_b), .b(ef_c), .operation_nd(ef_pop), .operation_rfd(mult_rdy), .result(mult_res), .rdy(mult_vld));
reg [63:0] r_t2_a, r_t3_a, r_t4_a, r_t5_a, r_t6_a, r_t7_a;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
if (ef_pop) begin
r_t2_a <= ef_a;
end else begin
r_t2_a <= r_t2_a;
end
r_t3_a <= r_t2_a;
r_t4_a <= r_t3_a;
r_t5_a <= r_t4_a;
r_t6_a <= r_t5_a;
r_t7_a <= r_t6_a;
end
parameter MID_DEPTH = 32;
wire mf_afull;
wire mf_pop;
wire mf_empty;
wire [63:0] mf_a, mf_bc;
fifo #(
.WIDTH(64+64),
.DEPTH(MID_DEPTH),
.PIPE(1),
.AFULLCNT(MID_DEPTH - 2)
) mid_fifo (
.clk(ck),
.reset(rst),
.push(mult_vld),
.din({r_t7_a, mult_res}),
.afull(mf_afull),
.oclk(ck),
.pop(mf_pop),
.dout({mf_a, mf_bc}),
.empty(mf_empty)
);
wire add_rdy;
wire [63:0] add_res;
wire add_vld;
assign mf_pop = !mf_empty & add_rdy;
// Black box instantiation
add_64b_dp adder (.clk(ck), .a(mf_a), .b(mf_bc), .operation_nd(mf_pop), .operation_rfd(add_rdy), .result(add_res), .rdy(add_vld));
// Outputs
assign o_rdy = !ef_afull;
assign o_res = add_res;
assign o_vld = add_vld;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_V |
/*
* cache_byte.v - Byte oriented memory cache
*
* This cache sits between the SDRAM controller and the CPU to provide single bytes from the
* SDRAM data blocks
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`default_nettype none
module cache_byte (
// Control
input wire clock_i,
input wire reset_i,
output wire busy_o,
// Byte interface - ack now needed as this is exclusive
input wire benable_i,
input wire brd_i,
input wire bwr_i,
output reg bvalid_o, // Signals bdat_o is valid for a read or write is complete
input wire [23:0] badr_i, // 24 bits/16M byte range
input wire [7:0] bdat_i,
output reg [7:0] bdat_o,
// Word interface - ack used to transfer through an arbiter
output reg wenable_o,
input wire wack_i,
output reg wrd_o,
output reg wwr_o,
input wire wvalid_i, // Is the SDRAM controller outputting a VALID signal (input or output in progress)
output reg [22:0] wadr_o, // 23 bits/8M word range
output wire [15:0] wdat_o, // Data to SDRAM controller
input wire [15:0] wdat_i // Data from SDRAM controller
);
// Parameters =================================================================================
// Constants ==================================================================================
parameter IDLE = 0, INIT1 = 1, INIT2 = 2, SEARCH = 3, READ1 = 4, READ2 = 5, READ3 = 6, OUTPUT1 = 7,
WRITE1 = 8, XXXXXX = 9, OUTPUT2 = 10, FLUSH1 = 11, FLUSH2 = 12, FLUSH3 = 13;
// Wire definitions ===========================================================================
// Convenience wires
wire [12:0] calc_tag; // Tag (address) for current row, used to store in tags list
wire [6:0] calc_row; // Cache row (either way)
wire [3:0] calc_index; // Cache byte index (byte/word location within row)
wire [1:0] way0_flag; // Direct pointer to row flag
wire [1:0] way1_flag; // Direct pointer to row flag
wire [12:0] way0_tag; // Direct pointer to row tag
wire [12:0] way1_tag; // Direct pointer to row tag
wire [7:0] bdato_wire; // Wire from cache memory
wire [15:0] wdato_wire; // Wire from cache memory
// Simulation wires
`ifdef SIM
wire calc_mru; // Most recently used for current row
wire [15:0] fifo0, fifo1; // Allows debug/GTKWave on fifo array
`endif
// Registers ==================================================================================
reg [12:0] way0_tags [0:127]; // Way 0 tags (addresses) 14-bits
reg [12:0] way1_tags [0:127]; // Way 1 tags (addresses) 14-bits
reg [1:0] way0_flags [0:127]; // Way 0 Flags
reg [1:0] way1_flags [0:127]; // Way 1 Flags
reg mru [0:127]; // Most recently used flags for victim selection
reg hit_way = 0; // Which way achieved the hit?
reg write_ctl = 0; // Cache write control signal for byte port (A)
reg [3:0] state = INIT1; // State machine state
// Working registers, word port enable, word read, word write, byte port valid, word port write enable
reg wenable = 0, wrd = 0, wwr = 0, bvalid = 0, wwe = 0;
// Word address (note it's 23 bits)
reg [22:0] wadr;
// Byte data output holding register
reg [7:0] bdato;
// Word (SDRAM) output fifo buffer
reg [15:0] wdat_fifo[0:1];
// Alternate edge SDRAM data capture (read data is on posedge SDRAM_CLK but NEGEDGE of memory logic clock)
reg [15:0] mem_dat_alt;
// Captured instruction
reg [23:0] badr; // Byte address is full 24-bit range (16MB)
reg [7:0] bdati; // Input data from the byte port to be stored
reg brd, bwr; // Which instruction? Rd/Wr?
// Read/Write row index pointer, addresses each word in turn on the row
reg [2:0] block_ptr; // Cycles for read/write store, cycles through words on the row
// GP counter - used for timeouts, counting bytes/words etc
reg [7:0] general_cntr;
reg advance_cntr = 0; // Flag that signals if the general counter should advance
// Assignments ================================================================================
// Pre-calculate the tag for later, so we can refer to the tag rather than recalculate it
assign calc_tag = badr[23:11];
// Which row of the cache?
assign calc_row = badr[10:4];
// Note this cale index is 4 bits, indicating byte port operation
assign calc_index = badr[3:0];
// Quick handle to the flags
assign way0_flag = way0_flags[calc_row];
assign way1_flag = way1_flags[calc_row];
// Quick handle to the tags
assign way0_tag = way0_tags[calc_row];
assign way1_tag = way1_tags[calc_row];
// Output to the word interface is out of the bottom of the 3 word FIFO
assign wdat_o = wdat_fifo[0];
`ifdef SIM
assign calc_mru = mru[calc_row]; // For GTKWave debugging
assign fifo1 = wdat_fifo[1]; // Allows debug/GTKWave on fifo array
assign fifo0 = wdat_fifo[0]; // Allows debug/GTKWave on fifo array
`endif
// Busy Flag
assign busy_o = (state != IDLE);
// Module connections =========================================================================
// This is an altera module to the block ram for the cache data. Port A is the byte port and
// port B is the word port, so the address lines are one bit bigger on the A port
cache_d cache_inst (
// The byte address is Way, then row, then index, and switch the LSB to give correct byte order
.address_a ( {hit_way,calc_row,calc_index[3:1],~calc_index[0] } ),
// Way is MSB, then Row, then Index
.address_b ( {hit_way,calc_row,block_ptr} ),
// Both clocks are the same, but could be independent
.clock_a ( clock_i ),
.clock_b ( clock_i ),
// Port A data comes from the byte port
.data_a ( bdati ),
// Port B data comes from the SDRAM port
.data_b ( mem_dat_alt/*wdat_i TODO: Check */),
// Port A is write then the byte port requests it
.wren_a ( write_ctl ),
// Port B is write when we're in a read mode (write enable signalled) and the SDRAM signals it's outputting data
.wren_b ( wvalid_i & wwe ),
// Output ports for A+B
.q_a ( bdato_wire ),
.q_b ( wdato_wire )
);
// Simulation branches and control ============================================================
// Other logic ================================================================================
// Main finite state machine, positive clock edge logic
always @(posedge clock_i)
if( reset_i ) state <= INIT1;
else case( state )
// Clear out key variables. Note the cache data is not cleared
INIT1: begin
wenable <= 1'b0; wrd <= 1'b0; wwr <= 1'b0; bvalid <= 1'b0;
wadr <= 23'd0; bdato <= 8'd0;
state <= INIT2;
end
// Clear out flags array and MRU - if these are clean, then the tags and cache don't need to be 0'd
INIT2: begin
way0_flags[general_cntr] <= 2'd0;
way1_flags[general_cntr] <= 2'd0;
mru[general_cntr] <= 1'b0;
if( ~general_cntr[6:0] == 7'd0 ) state <= IDLE; // Last byte 7f
end
// Wait for a command, note that the byte port is the master port. No requests appear on the word port
IDLE: begin
// If we were advancing the counter, then it's no longer necessary here
advance_cntr <= 1'b0;
// Disable the write enable flag for the cache memory, to prevent overwriting if another port causes valid_i
wwe <= 1'b0;
if( benable_i & (brd_i | bwr_i))
begin
// Store instruction parameters for later as the command will cease after one clock cycle
brd <= brd_i;
bwr <= bwr_i;
badr <= badr_i;
bdati <= bdat_i;
bvalid <= 1'b0; // Reset valid from last operation
// Point to next state
state <= SEARCH;
end
end
// Try to locate the correct cache row, if it's in the cache
SEARCH : begin
// Not empty way and tag hit (address matched) - cache hit!
if( ( way0_flag != 2'd0 ) && (way0_tag == calc_tag) )
begin
// Indicate this was WAY0
hit_way <= 1'b0;
// Update the most recently used flag
mru[calc_row] <= 1'b0;
$display("Cache HIT! Way 0"); // Debug messages
// If we're reading from cache, go straight to output
if( brd ) state <= OUTPUT1;
else
// Otherwise store the data received on the byte port
if( bwr ) state <= WRITE1;
// Fail safe - if we somehow get here, then go back to idle
else state <= IDLE;
end
else
// Not empty way and tag hit (address matched) - cache hit!
if( ( way1_flag != 2'd0 ) && (way1_tag == calc_tag) )
begin
// Indicate this was WAY1
hit_way <= 1'b1;
// Update the most recently used flag
mru[calc_row] <= 1'b1;
$display("Cache HIT! Way 1"); // Debug messages
// If we're reading from cache, go straight to output
if( brd ) state <= OUTPUT1;
else
// Otherwise store the data received on the byte port
if( bwr ) state <= WRITE1;
// Fail safe - if we somehow get here, then go back to idle
else state <= IDLE;
end
// Otherwise it's a cache miss, so select a victim cache way/line
else begin
// If way 0 or way 1 is empty, just read/write to that way
if( way0_flag == 2'd0 )
begin
hit_way <= 1'b0;
state <= READ1;
end
else
if ( way1_flag == 2'd0 )
begin
hit_way <= 1'b1;
state <= READ1;
end
// Otherwise both ways full, so select a row for replacement
else begin
// Calculate victim way
hit_way <= ~mru[calc_row]; // Select the way least recently used (not (~) most recent used)
$display("At %08d Row replacement for %d, 0x%06x, victim way %d, victim tag: 0x%04x", $time, calc_row, badr, ~mru[calc_row], ~mru[calc_row] ? way1_tags[calc_row] : way0_tags[calc_row]);
// If way is clean (no writes, so way is consistent with underlying SDRAM) then just discard way data
if( ( way0_flag == 2'b01 ) && mru[calc_row] ) state <= READ1;
else
if( ( way1_flag == 2'b01 ) && ~mru[calc_row] ) state <= READ1;
// Otherwise, if the way is dirty (has a write added to it since reading from SDRAM), flush it to memory first
else begin
$display("At %08d dirty flush for %d, 0x%06x, victim way %d", $time, calc_row, badr, ~mru[calc_row]);
state = FLUSH1;
end
end
end
end
// Reading from memory is a multi-state operation, first set the word (SDRAM) read signals
// This work in conjunction with the 2-clock R-C delay in the SDRAM
READ1 : begin
if( ~wack_i ) // If ACK is high then still ACKing a previous cycle(such as a flush), so wait
begin
wenable <= 1'b1; // Enable the word port
// wwe <= 1'b1; // Write enable the cache data block ram
wrd <= 1'b1; // Signal a read from the word port
// Discard LSB because we're reading words not bytes, but start from the first address needed,
// so we can immediately output the required byte after the first word is read from the SDRAM
wadr <= badr[23:1];
state <= READ2;
end
end
// Wait for the arbiter ack signal. If the SDRAM bus is in use, then we have to wait for the operation to complete
// before we can assert our request. The ACK input from the arbiter gives us that signal
READ2 : begin
if( wack_i ) begin
wwe <= 1'b1; // Write enable the cache data block ram
wenable <= 1'b0; // Deassert the word enable signal
wrd <= 1'b0; // and the read signal - the SDRAM controller has recorded the operation already
advance_cntr <= 0; // This signal ensures we don't advance the counter until ready
state <= READ3;
end
end
// Wait for the valid signal from the SDRAM controller, indicating data is available on the word input port
READ3 : if( wvalid_i ) begin
$display("Read %04x in to cache word memory location %x", mem_dat_alt/*wdat_i*/, block_ptr);
// Return the first byte immediately, for performance reasons
if( general_cntr == 3'd7 ) begin
// bdato <= badr[0] ? wdat_i[7:0] : wdat_i[15:8]; // Return the correct byte from the word
bdato <= badr[0] ? mem_dat_alt[7:0] : mem_dat_alt[15:8]; // Return the correct byte from the word
if( brd ) bvalid <= 1'b1; // Signal to the byte port that the data on the output is valid
end
// Update the flags and tag with the read data upon completion
if( general_cntr == 0 ) begin
// Update the flags + tag
if( hit_way == 1'b0 )
begin
way0_flags[calc_row] <= 2'b01;
way0_tags[calc_row] <= calc_tag;
end
else
begin
way1_flags[calc_row] <= 2'b01;
way1_tags[calc_row] <= calc_tag;
end
// Mark the way recently used
mru[calc_row] <= hit_way;
// If read, then we're done
if( ~bwr ) state <= IDLE;
// Otherwise go write to the cache ram from the byte port
else state <= WRITE1;
end
// Signal that we start to advance the counter every clock now (on the falling edge, next)
else advance_cntr <= 1;
end
// The data requested from the byte port is in the cache, so simply return that
// Give the cache ram 1 cycle to retrieve the data, then output
OUTPUT1 : state <= OUTPUT2;
// The cache ram itself is clocked constantly, so it always presents data on its output port, one clock delayed
OUTPUT2 : begin
// This data is transferred to the output ports on the falling edge of the clock, see the negedge block below
bdato <= bdato_wire[7:0];
bvalid <= 1;
state <= IDLE;
end
// Cache holds the correct memory line, so now just write data into the cache data memory
WRITE1 : begin
// Indicate cached write is complete (early indicator)
bvalid <= 1'b1;
// Update the flags with the dirty bit for either way 0 or 1
if( hit_way == 1'b0 ) way0_flags[calc_row] <= 2'b11;
else way1_flags[calc_row] <= 2'b11;
// Finished write to cache data, so return idle
state <= IDLE;
end
// This state flushes a dirty cache (written) back to the SDRAM
FLUSH1 : begin
// Stop the valid signal overwriting the cache, by disabling the write enable flag
wwe <= 1'b0;
// Enable the word port
wenable <= 1'b1;
// Indicate it's a write operation
wwr <= 1'b1;
// Output the address to the SDRAM port
wadr <= {(hit_way) ? way1_tag : way0_tag, calc_row, block_ptr }; // 23 bits of word address
// Move to the next step
state <= FLUSH2;
end
// This state waits for the SDRAM controller to indicate it's accepted the command
FLUSH2 : begin
if( wack_i ) begin
// Deassert the enable and write signals, but even while we're waiting,
// the data is being queued through the FIFO
wenable <= 1'b0;
wwr <= 1'b0;
advance_cntr <= 1'b0;
state <= FLUSH3;
end
end
// By now two bytes are queued in the FIFO, we wait for the valid signal before queuing any more
FLUSH3 : begin
advance_cntr <= wvalid_i; // Advance the counter if the SDRAM is ready
if( general_cntr == 7'd0 ) state <= READ1; // Flushed finished, go to read process
end
// Default operation just in case of a corruption - default is to reinitialise controller
default: state <= INIT1; // Self reset on unknown
endcase
// Update output signals on falling edge
always @(negedge clock_i)
begin
// Store memory line state for reading
mem_dat_alt <= wdat_i;
// Take action based on state
case( state )
// This state prepares to fill the arrays
INIT1: general_cntr <= ~8'd0;
// This state points to the next array location
INIT2: general_cntr <= general_cntr + 1'b1;
// Idle / wait processing
IDLE: begin
// Stop the write to the byte cache ram
write_ctl <= 1'b0;
end
// This state prepares to read 8 words
READ1: begin
general_cntr <= 3'd7;
// Move data through the FIFO - just in case the last operation was a flush - takes an extra clock cycle to output
wdat_fifo[0] <= wdat_fifo[1];
end
// This state prepares the cache line pointer
READ2: block_ptr <= wadr[2:0];
// This state will advance the counter if the SDRAM has signalled it's ready
READ3: begin
if( advance_cntr ) begin
// Adjust the address to the next location - this wraps if reading from a the middle of 16 byte block
block_ptr <= block_ptr + 1'b1;
general_cntr <= general_cntr - 1'b1;
end
end
// Write signal for the byte cache memory, it's reset automatically on idle
WRITE1 : write_ctl <= 1'b1;
// Flush 8 words, 2 is pre-loaded in FLUSH2 state, so counter is 6 rather than 8
FLUSH1 : begin
general_cntr <= 3'd6;
block_ptr <= 0;
end
// Fill top of cache, BUT only 2 bytes - if WACK takes a while we dont want to overflow the fifo!
FLUSH2 : if(block_ptr != 3'd2) begin
{wdat_fifo[0],wdat_fifo[1]} <= {wdat_fifo[1], wdato_wire};
block_ptr <= block_ptr + 1'b1;
end
// If the advance cntr flag is set, then we can continue to fill the FIFO
FLUSH3 : if( advance_cntr ) begin
// fill the fifo from the top
{wdat_fifo[0],wdat_fifo[1]} <= {wdat_fifo[1], wdato_wire};
// Adjust the address to the next location - this wraps if reading from a the middle of 8 word block
block_ptr <= block_ptr + 1'b1;
// Count down from 7 to 0
general_cntr <= general_cntr - 1'b1;
end
endcase
// Always update these output state signals for the word port
wenable_o <= wenable;
wrd_o <= wrd;
wwr_o <= wwr;
wadr_o <= wadr;
// Always update these output state signals for the byte port
bvalid_o <= bvalid;
bdat_o <= bdato;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_M_V
`define SKY130_FD_SC_LP__A211OI_M_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_m (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_m (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_M_V
|
// TimeHoldOver_Qsys_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_mm_interconnect_0 (
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [23:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
output wire nios2_gen2_0_data_master_readdatavalid, // .readdatavalid
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [23:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire nios2_gen2_0_instruction_master_readdatavalid, // .readdatavalid
output wire [4:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_address, // avalon_mapped_timer_reg_buf_0_avalon_slave_0.address
output wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_write, // .write
output wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_read, // .read
input wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata, // .readdata
output wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata, // .writedata
output wire [1:0] io_update_s1_address, // io_update_s1.address
output wire io_update_s1_write, // .write
input wire [31:0] io_update_s1_readdata, // .readdata
output wire [31:0] io_update_s1_writedata, // .writedata
output wire io_update_s1_chipselect, // .chipselect
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [9:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [1:0] pps_interrupt_s1_address, // pps_interrupt_s1.address
output wire pps_interrupt_s1_write, // .write
input wire [31:0] pps_interrupt_s1_readdata, // .readdata
output wire [31:0] pps_interrupt_s1_writedata, // .writedata
output wire pps_interrupt_s1_chipselect, // .chipselect
output wire [21:0] sdram_tri_controller_0_s1_address, // sdram_tri_controller_0_s1.address
output wire sdram_tri_controller_0_s1_write, // .write
output wire sdram_tri_controller_0_s1_read, // .read
input wire [15:0] sdram_tri_controller_0_s1_readdata, // .readdata
output wire [15:0] sdram_tri_controller_0_s1_writedata, // .writedata
output wire [1:0] sdram_tri_controller_0_s1_byteenable, // .byteenable
input wire sdram_tri_controller_0_s1_readdatavalid, // .readdatavalid
input wire sdram_tri_controller_0_s1_waitrequest, // .waitrequest
output wire [2:0] uart_0_s1_address, // uart_0_s1.address
output wire uart_0_s1_write, // .write
output wire uart_0_s1_read, // .read
input wire [15:0] uart_0_s1_readdata, // .readdata
output wire [15:0] uart_0_s1_writedata, // .writedata
output wire uart_0_s1_begintransfer, // .begintransfer
output wire uart_0_s1_chipselect, // .chipselect
output wire [2:0] uart_1_s1_address, // uart_1_s1.address
output wire uart_1_s1_write, // .write
output wire uart_1_s1_read, // .read
input wire [15:0] uart_1_s1_readdata, // .readdata
output wire [15:0] uart_1_s1_writedata, // .writedata
output wire uart_1_s1_begintransfer, // .begintransfer
output wire uart_1_s1_chipselect, // .chipselect
output wire [2:0] uart_2_s1_address, // uart_2_s1.address
output wire uart_2_s1_write, // .write
output wire uart_2_s1_read, // .read
input wire [15:0] uart_2_s1_readdata, // .readdata
output wire [15:0] uart_2_s1_writedata, // .writedata
output wire uart_2_s1_begintransfer, // .begintransfer
output wire uart_2_s1_chipselect, // .chipselect
output wire [2:0] uart_3_s1_address, // uart_3_s1.address
output wire uart_3_s1_write, // .write
output wire uart_3_s1_read, // .read
input wire [15:0] uart_3_s1_readdata, // .readdata
output wire [15:0] uart_3_s1_writedata, // .writedata
output wire uart_3_s1_begintransfer, // .begintransfer
output wire uart_3_s1_chipselect, // .chipselect
output wire [7:0] vic_0_csr_access_address, // vic_0_csr_access.address
output wire vic_0_csr_access_write, // .write
output wire vic_0_csr_access_read, // .read
input wire [31:0] vic_0_csr_access_readdata, // .readdata
output wire [31:0] vic_0_csr_access_writedata // .writedata
);
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [23:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [23:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdata; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_readdata -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_readdata
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_waitrequest; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_waitrequest -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_waitrequest
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_debugaccess; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_debugaccess -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_debugaccess
wire [23:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_address; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_address -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_address
wire [3:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_byteenable; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_byteenable -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_byteenable
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_read; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_read -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_read
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdatavalid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_readdatavalid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_readdatavalid
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_lock; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_lock -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_lock
wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_writedata; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_writedata -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_writedata
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_write; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_write -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_write
wire [2:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_burstcount; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_burstcount -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_burstcount
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [102:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_ready
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_startofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_startofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_endofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_endofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_valid
wire [102:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_startofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_valid
wire [101:0] cmd_mux_src_data; // cmd_mux:src_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_data
wire cmd_mux_src_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_ready -> cmd_mux:src_ready
wire [10:0] cmd_mux_src_channel; // cmd_mux:src_channel -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_endofpacket
wire [31:0] vic_0_csr_access_agent_m0_readdata; // vic_0_csr_access_translator:uav_readdata -> vic_0_csr_access_agent:m0_readdata
wire vic_0_csr_access_agent_m0_waitrequest; // vic_0_csr_access_translator:uav_waitrequest -> vic_0_csr_access_agent:m0_waitrequest
wire vic_0_csr_access_agent_m0_debugaccess; // vic_0_csr_access_agent:m0_debugaccess -> vic_0_csr_access_translator:uav_debugaccess
wire [23:0] vic_0_csr_access_agent_m0_address; // vic_0_csr_access_agent:m0_address -> vic_0_csr_access_translator:uav_address
wire [3:0] vic_0_csr_access_agent_m0_byteenable; // vic_0_csr_access_agent:m0_byteenable -> vic_0_csr_access_translator:uav_byteenable
wire vic_0_csr_access_agent_m0_read; // vic_0_csr_access_agent:m0_read -> vic_0_csr_access_translator:uav_read
wire vic_0_csr_access_agent_m0_readdatavalid; // vic_0_csr_access_translator:uav_readdatavalid -> vic_0_csr_access_agent:m0_readdatavalid
wire vic_0_csr_access_agent_m0_lock; // vic_0_csr_access_agent:m0_lock -> vic_0_csr_access_translator:uav_lock
wire [31:0] vic_0_csr_access_agent_m0_writedata; // vic_0_csr_access_agent:m0_writedata -> vic_0_csr_access_translator:uav_writedata
wire vic_0_csr_access_agent_m0_write; // vic_0_csr_access_agent:m0_write -> vic_0_csr_access_translator:uav_write
wire [2:0] vic_0_csr_access_agent_m0_burstcount; // vic_0_csr_access_agent:m0_burstcount -> vic_0_csr_access_translator:uav_burstcount
wire vic_0_csr_access_agent_rf_source_valid; // vic_0_csr_access_agent:rf_source_valid -> vic_0_csr_access_agent_rsp_fifo:in_valid
wire [102:0] vic_0_csr_access_agent_rf_source_data; // vic_0_csr_access_agent:rf_source_data -> vic_0_csr_access_agent_rsp_fifo:in_data
wire vic_0_csr_access_agent_rf_source_ready; // vic_0_csr_access_agent_rsp_fifo:in_ready -> vic_0_csr_access_agent:rf_source_ready
wire vic_0_csr_access_agent_rf_source_startofpacket; // vic_0_csr_access_agent:rf_source_startofpacket -> vic_0_csr_access_agent_rsp_fifo:in_startofpacket
wire vic_0_csr_access_agent_rf_source_endofpacket; // vic_0_csr_access_agent:rf_source_endofpacket -> vic_0_csr_access_agent_rsp_fifo:in_endofpacket
wire vic_0_csr_access_agent_rsp_fifo_out_valid; // vic_0_csr_access_agent_rsp_fifo:out_valid -> vic_0_csr_access_agent:rf_sink_valid
wire [102:0] vic_0_csr_access_agent_rsp_fifo_out_data; // vic_0_csr_access_agent_rsp_fifo:out_data -> vic_0_csr_access_agent:rf_sink_data
wire vic_0_csr_access_agent_rsp_fifo_out_ready; // vic_0_csr_access_agent:rf_sink_ready -> vic_0_csr_access_agent_rsp_fifo:out_ready
wire vic_0_csr_access_agent_rsp_fifo_out_startofpacket; // vic_0_csr_access_agent_rsp_fifo:out_startofpacket -> vic_0_csr_access_agent:rf_sink_startofpacket
wire vic_0_csr_access_agent_rsp_fifo_out_endofpacket; // vic_0_csr_access_agent_rsp_fifo:out_endofpacket -> vic_0_csr_access_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> vic_0_csr_access_agent:cp_valid
wire [101:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> vic_0_csr_access_agent:cp_data
wire cmd_mux_001_src_ready; // vic_0_csr_access_agent:cp_ready -> cmd_mux_001:src_ready
wire [10:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> vic_0_csr_access_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> vic_0_csr_access_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> vic_0_csr_access_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [23:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [102:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [102:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [101:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_002_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire [10:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] uart_0_s1_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
wire uart_0_s1_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
wire uart_0_s1_agent_m0_debugaccess; // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
wire [23:0] uart_0_s1_agent_m0_address; // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
wire [3:0] uart_0_s1_agent_m0_byteenable; // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
wire uart_0_s1_agent_m0_read; // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
wire uart_0_s1_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
wire uart_0_s1_agent_m0_lock; // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
wire [31:0] uart_0_s1_agent_m0_writedata; // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
wire uart_0_s1_agent_m0_write; // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
wire [2:0] uart_0_s1_agent_m0_burstcount; // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
wire uart_0_s1_agent_rf_source_valid; // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_0_s1_agent_rf_source_data; // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
wire uart_0_s1_agent_rf_source_ready; // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
wire uart_0_s1_agent_rf_source_startofpacket; // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
wire uart_0_s1_agent_rf_source_endofpacket; // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
wire uart_0_s1_agent_rsp_fifo_out_valid; // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
wire [102:0] uart_0_s1_agent_rsp_fifo_out_data; // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
wire uart_0_s1_agent_rsp_fifo_out_ready; // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
wire uart_0_s1_agent_rsp_fifo_out_startofpacket; // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
wire uart_0_s1_agent_rsp_fifo_out_endofpacket; // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> uart_0_s1_agent:cp_valid
wire [101:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> uart_0_s1_agent:cp_data
wire cmd_mux_003_src_ready; // uart_0_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [10:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> uart_0_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
wire [31:0] uart_1_s1_agent_m0_readdata; // uart_1_s1_translator:uav_readdata -> uart_1_s1_agent:m0_readdata
wire uart_1_s1_agent_m0_waitrequest; // uart_1_s1_translator:uav_waitrequest -> uart_1_s1_agent:m0_waitrequest
wire uart_1_s1_agent_m0_debugaccess; // uart_1_s1_agent:m0_debugaccess -> uart_1_s1_translator:uav_debugaccess
wire [23:0] uart_1_s1_agent_m0_address; // uart_1_s1_agent:m0_address -> uart_1_s1_translator:uav_address
wire [3:0] uart_1_s1_agent_m0_byteenable; // uart_1_s1_agent:m0_byteenable -> uart_1_s1_translator:uav_byteenable
wire uart_1_s1_agent_m0_read; // uart_1_s1_agent:m0_read -> uart_1_s1_translator:uav_read
wire uart_1_s1_agent_m0_readdatavalid; // uart_1_s1_translator:uav_readdatavalid -> uart_1_s1_agent:m0_readdatavalid
wire uart_1_s1_agent_m0_lock; // uart_1_s1_agent:m0_lock -> uart_1_s1_translator:uav_lock
wire [31:0] uart_1_s1_agent_m0_writedata; // uart_1_s1_agent:m0_writedata -> uart_1_s1_translator:uav_writedata
wire uart_1_s1_agent_m0_write; // uart_1_s1_agent:m0_write -> uart_1_s1_translator:uav_write
wire [2:0] uart_1_s1_agent_m0_burstcount; // uart_1_s1_agent:m0_burstcount -> uart_1_s1_translator:uav_burstcount
wire uart_1_s1_agent_rf_source_valid; // uart_1_s1_agent:rf_source_valid -> uart_1_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_1_s1_agent_rf_source_data; // uart_1_s1_agent:rf_source_data -> uart_1_s1_agent_rsp_fifo:in_data
wire uart_1_s1_agent_rf_source_ready; // uart_1_s1_agent_rsp_fifo:in_ready -> uart_1_s1_agent:rf_source_ready
wire uart_1_s1_agent_rf_source_startofpacket; // uart_1_s1_agent:rf_source_startofpacket -> uart_1_s1_agent_rsp_fifo:in_startofpacket
wire uart_1_s1_agent_rf_source_endofpacket; // uart_1_s1_agent:rf_source_endofpacket -> uart_1_s1_agent_rsp_fifo:in_endofpacket
wire uart_1_s1_agent_rsp_fifo_out_valid; // uart_1_s1_agent_rsp_fifo:out_valid -> uart_1_s1_agent:rf_sink_valid
wire [102:0] uart_1_s1_agent_rsp_fifo_out_data; // uart_1_s1_agent_rsp_fifo:out_data -> uart_1_s1_agent:rf_sink_data
wire uart_1_s1_agent_rsp_fifo_out_ready; // uart_1_s1_agent:rf_sink_ready -> uart_1_s1_agent_rsp_fifo:out_ready
wire uart_1_s1_agent_rsp_fifo_out_startofpacket; // uart_1_s1_agent_rsp_fifo:out_startofpacket -> uart_1_s1_agent:rf_sink_startofpacket
wire uart_1_s1_agent_rsp_fifo_out_endofpacket; // uart_1_s1_agent_rsp_fifo:out_endofpacket -> uart_1_s1_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> uart_1_s1_agent:cp_valid
wire [101:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> uart_1_s1_agent:cp_data
wire cmd_mux_004_src_ready; // uart_1_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [10:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> uart_1_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> uart_1_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> uart_1_s1_agent:cp_endofpacket
wire [31:0] uart_2_s1_agent_m0_readdata; // uart_2_s1_translator:uav_readdata -> uart_2_s1_agent:m0_readdata
wire uart_2_s1_agent_m0_waitrequest; // uart_2_s1_translator:uav_waitrequest -> uart_2_s1_agent:m0_waitrequest
wire uart_2_s1_agent_m0_debugaccess; // uart_2_s1_agent:m0_debugaccess -> uart_2_s1_translator:uav_debugaccess
wire [23:0] uart_2_s1_agent_m0_address; // uart_2_s1_agent:m0_address -> uart_2_s1_translator:uav_address
wire [3:0] uart_2_s1_agent_m0_byteenable; // uart_2_s1_agent:m0_byteenable -> uart_2_s1_translator:uav_byteenable
wire uart_2_s1_agent_m0_read; // uart_2_s1_agent:m0_read -> uart_2_s1_translator:uav_read
wire uart_2_s1_agent_m0_readdatavalid; // uart_2_s1_translator:uav_readdatavalid -> uart_2_s1_agent:m0_readdatavalid
wire uart_2_s1_agent_m0_lock; // uart_2_s1_agent:m0_lock -> uart_2_s1_translator:uav_lock
wire [31:0] uart_2_s1_agent_m0_writedata; // uart_2_s1_agent:m0_writedata -> uart_2_s1_translator:uav_writedata
wire uart_2_s1_agent_m0_write; // uart_2_s1_agent:m0_write -> uart_2_s1_translator:uav_write
wire [2:0] uart_2_s1_agent_m0_burstcount; // uart_2_s1_agent:m0_burstcount -> uart_2_s1_translator:uav_burstcount
wire uart_2_s1_agent_rf_source_valid; // uart_2_s1_agent:rf_source_valid -> uart_2_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_2_s1_agent_rf_source_data; // uart_2_s1_agent:rf_source_data -> uart_2_s1_agent_rsp_fifo:in_data
wire uart_2_s1_agent_rf_source_ready; // uart_2_s1_agent_rsp_fifo:in_ready -> uart_2_s1_agent:rf_source_ready
wire uart_2_s1_agent_rf_source_startofpacket; // uart_2_s1_agent:rf_source_startofpacket -> uart_2_s1_agent_rsp_fifo:in_startofpacket
wire uart_2_s1_agent_rf_source_endofpacket; // uart_2_s1_agent:rf_source_endofpacket -> uart_2_s1_agent_rsp_fifo:in_endofpacket
wire uart_2_s1_agent_rsp_fifo_out_valid; // uart_2_s1_agent_rsp_fifo:out_valid -> uart_2_s1_agent:rf_sink_valid
wire [102:0] uart_2_s1_agent_rsp_fifo_out_data; // uart_2_s1_agent_rsp_fifo:out_data -> uart_2_s1_agent:rf_sink_data
wire uart_2_s1_agent_rsp_fifo_out_ready; // uart_2_s1_agent:rf_sink_ready -> uart_2_s1_agent_rsp_fifo:out_ready
wire uart_2_s1_agent_rsp_fifo_out_startofpacket; // uart_2_s1_agent_rsp_fifo:out_startofpacket -> uart_2_s1_agent:rf_sink_startofpacket
wire uart_2_s1_agent_rsp_fifo_out_endofpacket; // uart_2_s1_agent_rsp_fifo:out_endofpacket -> uart_2_s1_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> uart_2_s1_agent:cp_valid
wire [101:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> uart_2_s1_agent:cp_data
wire cmd_mux_005_src_ready; // uart_2_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [10:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> uart_2_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> uart_2_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> uart_2_s1_agent:cp_endofpacket
wire [31:0] uart_3_s1_agent_m0_readdata; // uart_3_s1_translator:uav_readdata -> uart_3_s1_agent:m0_readdata
wire uart_3_s1_agent_m0_waitrequest; // uart_3_s1_translator:uav_waitrequest -> uart_3_s1_agent:m0_waitrequest
wire uart_3_s1_agent_m0_debugaccess; // uart_3_s1_agent:m0_debugaccess -> uart_3_s1_translator:uav_debugaccess
wire [23:0] uart_3_s1_agent_m0_address; // uart_3_s1_agent:m0_address -> uart_3_s1_translator:uav_address
wire [3:0] uart_3_s1_agent_m0_byteenable; // uart_3_s1_agent:m0_byteenable -> uart_3_s1_translator:uav_byteenable
wire uart_3_s1_agent_m0_read; // uart_3_s1_agent:m0_read -> uart_3_s1_translator:uav_read
wire uart_3_s1_agent_m0_readdatavalid; // uart_3_s1_translator:uav_readdatavalid -> uart_3_s1_agent:m0_readdatavalid
wire uart_3_s1_agent_m0_lock; // uart_3_s1_agent:m0_lock -> uart_3_s1_translator:uav_lock
wire [31:0] uart_3_s1_agent_m0_writedata; // uart_3_s1_agent:m0_writedata -> uart_3_s1_translator:uav_writedata
wire uart_3_s1_agent_m0_write; // uart_3_s1_agent:m0_write -> uart_3_s1_translator:uav_write
wire [2:0] uart_3_s1_agent_m0_burstcount; // uart_3_s1_agent:m0_burstcount -> uart_3_s1_translator:uav_burstcount
wire uart_3_s1_agent_rf_source_valid; // uart_3_s1_agent:rf_source_valid -> uart_3_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_3_s1_agent_rf_source_data; // uart_3_s1_agent:rf_source_data -> uart_3_s1_agent_rsp_fifo:in_data
wire uart_3_s1_agent_rf_source_ready; // uart_3_s1_agent_rsp_fifo:in_ready -> uart_3_s1_agent:rf_source_ready
wire uart_3_s1_agent_rf_source_startofpacket; // uart_3_s1_agent:rf_source_startofpacket -> uart_3_s1_agent_rsp_fifo:in_startofpacket
wire uart_3_s1_agent_rf_source_endofpacket; // uart_3_s1_agent:rf_source_endofpacket -> uart_3_s1_agent_rsp_fifo:in_endofpacket
wire uart_3_s1_agent_rsp_fifo_out_valid; // uart_3_s1_agent_rsp_fifo:out_valid -> uart_3_s1_agent:rf_sink_valid
wire [102:0] uart_3_s1_agent_rsp_fifo_out_data; // uart_3_s1_agent_rsp_fifo:out_data -> uart_3_s1_agent:rf_sink_data
wire uart_3_s1_agent_rsp_fifo_out_ready; // uart_3_s1_agent:rf_sink_ready -> uart_3_s1_agent_rsp_fifo:out_ready
wire uart_3_s1_agent_rsp_fifo_out_startofpacket; // uart_3_s1_agent_rsp_fifo:out_startofpacket -> uart_3_s1_agent:rf_sink_startofpacket
wire uart_3_s1_agent_rsp_fifo_out_endofpacket; // uart_3_s1_agent_rsp_fifo:out_endofpacket -> uart_3_s1_agent:rf_sink_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> uart_3_s1_agent:cp_valid
wire [101:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> uart_3_s1_agent:cp_data
wire cmd_mux_006_src_ready; // uart_3_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [10:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> uart_3_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> uart_3_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> uart_3_s1_agent:cp_endofpacket
wire [15:0] sdram_tri_controller_0_s1_agent_m0_readdata; // sdram_tri_controller_0_s1_translator:uav_readdata -> sdram_tri_controller_0_s1_agent:m0_readdata
wire sdram_tri_controller_0_s1_agent_m0_waitrequest; // sdram_tri_controller_0_s1_translator:uav_waitrequest -> sdram_tri_controller_0_s1_agent:m0_waitrequest
wire sdram_tri_controller_0_s1_agent_m0_debugaccess; // sdram_tri_controller_0_s1_agent:m0_debugaccess -> sdram_tri_controller_0_s1_translator:uav_debugaccess
wire [23:0] sdram_tri_controller_0_s1_agent_m0_address; // sdram_tri_controller_0_s1_agent:m0_address -> sdram_tri_controller_0_s1_translator:uav_address
wire [1:0] sdram_tri_controller_0_s1_agent_m0_byteenable; // sdram_tri_controller_0_s1_agent:m0_byteenable -> sdram_tri_controller_0_s1_translator:uav_byteenable
wire sdram_tri_controller_0_s1_agent_m0_read; // sdram_tri_controller_0_s1_agent:m0_read -> sdram_tri_controller_0_s1_translator:uav_read
wire sdram_tri_controller_0_s1_agent_m0_readdatavalid; // sdram_tri_controller_0_s1_translator:uav_readdatavalid -> sdram_tri_controller_0_s1_agent:m0_readdatavalid
wire sdram_tri_controller_0_s1_agent_m0_lock; // sdram_tri_controller_0_s1_agent:m0_lock -> sdram_tri_controller_0_s1_translator:uav_lock
wire [15:0] sdram_tri_controller_0_s1_agent_m0_writedata; // sdram_tri_controller_0_s1_agent:m0_writedata -> sdram_tri_controller_0_s1_translator:uav_writedata
wire sdram_tri_controller_0_s1_agent_m0_write; // sdram_tri_controller_0_s1_agent:m0_write -> sdram_tri_controller_0_s1_translator:uav_write
wire [1:0] sdram_tri_controller_0_s1_agent_m0_burstcount; // sdram_tri_controller_0_s1_agent:m0_burstcount -> sdram_tri_controller_0_s1_translator:uav_burstcount
wire sdram_tri_controller_0_s1_agent_rf_source_valid; // sdram_tri_controller_0_s1_agent:rf_source_valid -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_valid
wire [84:0] sdram_tri_controller_0_s1_agent_rf_source_data; // sdram_tri_controller_0_s1_agent:rf_source_data -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_data
wire sdram_tri_controller_0_s1_agent_rf_source_ready; // sdram_tri_controller_0_s1_agent_rsp_fifo:in_ready -> sdram_tri_controller_0_s1_agent:rf_source_ready
wire sdram_tri_controller_0_s1_agent_rf_source_startofpacket; // sdram_tri_controller_0_s1_agent:rf_source_startofpacket -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_startofpacket
wire sdram_tri_controller_0_s1_agent_rf_source_endofpacket; // sdram_tri_controller_0_s1_agent:rf_source_endofpacket -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_endofpacket
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_valid; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_valid -> sdram_tri_controller_0_s1_agent:rf_sink_valid
wire [84:0] sdram_tri_controller_0_s1_agent_rsp_fifo_out_data; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_data -> sdram_tri_controller_0_s1_agent:rf_sink_data
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_ready; // sdram_tri_controller_0_s1_agent:rf_sink_ready -> sdram_tri_controller_0_s1_agent_rsp_fifo:out_ready
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_startofpacket; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_startofpacket -> sdram_tri_controller_0_s1_agent:rf_sink_startofpacket
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_endofpacket; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_endofpacket -> sdram_tri_controller_0_s1_agent:rf_sink_endofpacket
wire sdram_tri_controller_0_s1_agent_rdata_fifo_src_valid; // sdram_tri_controller_0_s1_agent:rdata_fifo_src_valid -> sdram_tri_controller_0_s1_agent_rdata_fifo:in_valid
wire [17:0] sdram_tri_controller_0_s1_agent_rdata_fifo_src_data; // sdram_tri_controller_0_s1_agent:rdata_fifo_src_data -> sdram_tri_controller_0_s1_agent_rdata_fifo:in_data
wire sdram_tri_controller_0_s1_agent_rdata_fifo_src_ready; // sdram_tri_controller_0_s1_agent_rdata_fifo:in_ready -> sdram_tri_controller_0_s1_agent:rdata_fifo_src_ready
wire [31:0] io_update_s1_agent_m0_readdata; // io_update_s1_translator:uav_readdata -> io_update_s1_agent:m0_readdata
wire io_update_s1_agent_m0_waitrequest; // io_update_s1_translator:uav_waitrequest -> io_update_s1_agent:m0_waitrequest
wire io_update_s1_agent_m0_debugaccess; // io_update_s1_agent:m0_debugaccess -> io_update_s1_translator:uav_debugaccess
wire [23:0] io_update_s1_agent_m0_address; // io_update_s1_agent:m0_address -> io_update_s1_translator:uav_address
wire [3:0] io_update_s1_agent_m0_byteenable; // io_update_s1_agent:m0_byteenable -> io_update_s1_translator:uav_byteenable
wire io_update_s1_agent_m0_read; // io_update_s1_agent:m0_read -> io_update_s1_translator:uav_read
wire io_update_s1_agent_m0_readdatavalid; // io_update_s1_translator:uav_readdatavalid -> io_update_s1_agent:m0_readdatavalid
wire io_update_s1_agent_m0_lock; // io_update_s1_agent:m0_lock -> io_update_s1_translator:uav_lock
wire [31:0] io_update_s1_agent_m0_writedata; // io_update_s1_agent:m0_writedata -> io_update_s1_translator:uav_writedata
wire io_update_s1_agent_m0_write; // io_update_s1_agent:m0_write -> io_update_s1_translator:uav_write
wire [2:0] io_update_s1_agent_m0_burstcount; // io_update_s1_agent:m0_burstcount -> io_update_s1_translator:uav_burstcount
wire io_update_s1_agent_rf_source_valid; // io_update_s1_agent:rf_source_valid -> io_update_s1_agent_rsp_fifo:in_valid
wire [102:0] io_update_s1_agent_rf_source_data; // io_update_s1_agent:rf_source_data -> io_update_s1_agent_rsp_fifo:in_data
wire io_update_s1_agent_rf_source_ready; // io_update_s1_agent_rsp_fifo:in_ready -> io_update_s1_agent:rf_source_ready
wire io_update_s1_agent_rf_source_startofpacket; // io_update_s1_agent:rf_source_startofpacket -> io_update_s1_agent_rsp_fifo:in_startofpacket
wire io_update_s1_agent_rf_source_endofpacket; // io_update_s1_agent:rf_source_endofpacket -> io_update_s1_agent_rsp_fifo:in_endofpacket
wire io_update_s1_agent_rsp_fifo_out_valid; // io_update_s1_agent_rsp_fifo:out_valid -> io_update_s1_agent:rf_sink_valid
wire [102:0] io_update_s1_agent_rsp_fifo_out_data; // io_update_s1_agent_rsp_fifo:out_data -> io_update_s1_agent:rf_sink_data
wire io_update_s1_agent_rsp_fifo_out_ready; // io_update_s1_agent:rf_sink_ready -> io_update_s1_agent_rsp_fifo:out_ready
wire io_update_s1_agent_rsp_fifo_out_startofpacket; // io_update_s1_agent_rsp_fifo:out_startofpacket -> io_update_s1_agent:rf_sink_startofpacket
wire io_update_s1_agent_rsp_fifo_out_endofpacket; // io_update_s1_agent_rsp_fifo:out_endofpacket -> io_update_s1_agent:rf_sink_endofpacket
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> io_update_s1_agent:cp_valid
wire [101:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> io_update_s1_agent:cp_data
wire cmd_mux_008_src_ready; // io_update_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [10:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> io_update_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> io_update_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> io_update_s1_agent:cp_endofpacket
wire [31:0] pps_interrupt_s1_agent_m0_readdata; // pps_interrupt_s1_translator:uav_readdata -> pps_interrupt_s1_agent:m0_readdata
wire pps_interrupt_s1_agent_m0_waitrequest; // pps_interrupt_s1_translator:uav_waitrequest -> pps_interrupt_s1_agent:m0_waitrequest
wire pps_interrupt_s1_agent_m0_debugaccess; // pps_interrupt_s1_agent:m0_debugaccess -> pps_interrupt_s1_translator:uav_debugaccess
wire [23:0] pps_interrupt_s1_agent_m0_address; // pps_interrupt_s1_agent:m0_address -> pps_interrupt_s1_translator:uav_address
wire [3:0] pps_interrupt_s1_agent_m0_byteenable; // pps_interrupt_s1_agent:m0_byteenable -> pps_interrupt_s1_translator:uav_byteenable
wire pps_interrupt_s1_agent_m0_read; // pps_interrupt_s1_agent:m0_read -> pps_interrupt_s1_translator:uav_read
wire pps_interrupt_s1_agent_m0_readdatavalid; // pps_interrupt_s1_translator:uav_readdatavalid -> pps_interrupt_s1_agent:m0_readdatavalid
wire pps_interrupt_s1_agent_m0_lock; // pps_interrupt_s1_agent:m0_lock -> pps_interrupt_s1_translator:uav_lock
wire [31:0] pps_interrupt_s1_agent_m0_writedata; // pps_interrupt_s1_agent:m0_writedata -> pps_interrupt_s1_translator:uav_writedata
wire pps_interrupt_s1_agent_m0_write; // pps_interrupt_s1_agent:m0_write -> pps_interrupt_s1_translator:uav_write
wire [2:0] pps_interrupt_s1_agent_m0_burstcount; // pps_interrupt_s1_agent:m0_burstcount -> pps_interrupt_s1_translator:uav_burstcount
wire pps_interrupt_s1_agent_rf_source_valid; // pps_interrupt_s1_agent:rf_source_valid -> pps_interrupt_s1_agent_rsp_fifo:in_valid
wire [102:0] pps_interrupt_s1_agent_rf_source_data; // pps_interrupt_s1_agent:rf_source_data -> pps_interrupt_s1_agent_rsp_fifo:in_data
wire pps_interrupt_s1_agent_rf_source_ready; // pps_interrupt_s1_agent_rsp_fifo:in_ready -> pps_interrupt_s1_agent:rf_source_ready
wire pps_interrupt_s1_agent_rf_source_startofpacket; // pps_interrupt_s1_agent:rf_source_startofpacket -> pps_interrupt_s1_agent_rsp_fifo:in_startofpacket
wire pps_interrupt_s1_agent_rf_source_endofpacket; // pps_interrupt_s1_agent:rf_source_endofpacket -> pps_interrupt_s1_agent_rsp_fifo:in_endofpacket
wire pps_interrupt_s1_agent_rsp_fifo_out_valid; // pps_interrupt_s1_agent_rsp_fifo:out_valid -> pps_interrupt_s1_agent:rf_sink_valid
wire [102:0] pps_interrupt_s1_agent_rsp_fifo_out_data; // pps_interrupt_s1_agent_rsp_fifo:out_data -> pps_interrupt_s1_agent:rf_sink_data
wire pps_interrupt_s1_agent_rsp_fifo_out_ready; // pps_interrupt_s1_agent:rf_sink_ready -> pps_interrupt_s1_agent_rsp_fifo:out_ready
wire pps_interrupt_s1_agent_rsp_fifo_out_startofpacket; // pps_interrupt_s1_agent_rsp_fifo:out_startofpacket -> pps_interrupt_s1_agent:rf_sink_startofpacket
wire pps_interrupt_s1_agent_rsp_fifo_out_endofpacket; // pps_interrupt_s1_agent_rsp_fifo:out_endofpacket -> pps_interrupt_s1_agent:rf_sink_endofpacket
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> pps_interrupt_s1_agent:cp_valid
wire [101:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> pps_interrupt_s1_agent:cp_data
wire cmd_mux_009_src_ready; // pps_interrupt_s1_agent:cp_ready -> cmd_mux_009:src_ready
wire [10:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> pps_interrupt_s1_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> pps_interrupt_s1_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> pps_interrupt_s1_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [23:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [102:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [102:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [101:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_010_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_010:src_ready
wire [10:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router:sink_valid
wire [101:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [101:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_valid -> router_002:sink_valid
wire [101:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_data -> router_002:sink_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_ready; // router_002:sink_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_ready
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_startofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_startofpacket -> router_002:sink_startofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_endofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [101:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [10:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire vic_0_csr_access_agent_rp_valid; // vic_0_csr_access_agent:rp_valid -> router_003:sink_valid
wire [101:0] vic_0_csr_access_agent_rp_data; // vic_0_csr_access_agent:rp_data -> router_003:sink_data
wire vic_0_csr_access_agent_rp_ready; // router_003:sink_ready -> vic_0_csr_access_agent:rp_ready
wire vic_0_csr_access_agent_rp_startofpacket; // vic_0_csr_access_agent:rp_startofpacket -> router_003:sink_startofpacket
wire vic_0_csr_access_agent_rp_endofpacket; // vic_0_csr_access_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [101:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [10:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
wire [101:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_004:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [101:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [10:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire uart_0_s1_agent_rp_valid; // uart_0_s1_agent:rp_valid -> router_005:sink_valid
wire [101:0] uart_0_s1_agent_rp_data; // uart_0_s1_agent:rp_data -> router_005:sink_data
wire uart_0_s1_agent_rp_ready; // router_005:sink_ready -> uart_0_s1_agent:rp_ready
wire uart_0_s1_agent_rp_startofpacket; // uart_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire uart_0_s1_agent_rp_endofpacket; // uart_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [101:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [10:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire uart_1_s1_agent_rp_valid; // uart_1_s1_agent:rp_valid -> router_006:sink_valid
wire [101:0] uart_1_s1_agent_rp_data; // uart_1_s1_agent:rp_data -> router_006:sink_data
wire uart_1_s1_agent_rp_ready; // router_006:sink_ready -> uart_1_s1_agent:rp_ready
wire uart_1_s1_agent_rp_startofpacket; // uart_1_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire uart_1_s1_agent_rp_endofpacket; // uart_1_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [101:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [10:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire uart_2_s1_agent_rp_valid; // uart_2_s1_agent:rp_valid -> router_007:sink_valid
wire [101:0] uart_2_s1_agent_rp_data; // uart_2_s1_agent:rp_data -> router_007:sink_data
wire uart_2_s1_agent_rp_ready; // router_007:sink_ready -> uart_2_s1_agent:rp_ready
wire uart_2_s1_agent_rp_startofpacket; // uart_2_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire uart_2_s1_agent_rp_endofpacket; // uart_2_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [101:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [10:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire uart_3_s1_agent_rp_valid; // uart_3_s1_agent:rp_valid -> router_008:sink_valid
wire [101:0] uart_3_s1_agent_rp_data; // uart_3_s1_agent:rp_data -> router_008:sink_data
wire uart_3_s1_agent_rp_ready; // router_008:sink_ready -> uart_3_s1_agent:rp_ready
wire uart_3_s1_agent_rp_startofpacket; // uart_3_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire uart_3_s1_agent_rp_endofpacket; // uart_3_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [101:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [10:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sdram_tri_controller_0_s1_agent_rp_valid; // sdram_tri_controller_0_s1_agent:rp_valid -> router_009:sink_valid
wire [83:0] sdram_tri_controller_0_s1_agent_rp_data; // sdram_tri_controller_0_s1_agent:rp_data -> router_009:sink_data
wire sdram_tri_controller_0_s1_agent_rp_ready; // router_009:sink_ready -> sdram_tri_controller_0_s1_agent:rp_ready
wire sdram_tri_controller_0_s1_agent_rp_startofpacket; // sdram_tri_controller_0_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sdram_tri_controller_0_s1_agent_rp_endofpacket; // sdram_tri_controller_0_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire io_update_s1_agent_rp_valid; // io_update_s1_agent:rp_valid -> router_010:sink_valid
wire [101:0] io_update_s1_agent_rp_data; // io_update_s1_agent:rp_data -> router_010:sink_data
wire io_update_s1_agent_rp_ready; // router_010:sink_ready -> io_update_s1_agent:rp_ready
wire io_update_s1_agent_rp_startofpacket; // io_update_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire io_update_s1_agent_rp_endofpacket; // io_update_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [101:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [10:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire pps_interrupt_s1_agent_rp_valid; // pps_interrupt_s1_agent:rp_valid -> router_011:sink_valid
wire [101:0] pps_interrupt_s1_agent_rp_data; // pps_interrupt_s1_agent:rp_data -> router_011:sink_data
wire pps_interrupt_s1_agent_rp_ready; // router_011:sink_ready -> pps_interrupt_s1_agent:rp_ready
wire pps_interrupt_s1_agent_rp_startofpacket; // pps_interrupt_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire pps_interrupt_s1_agent_rp_endofpacket; // pps_interrupt_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [101:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [10:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_012:sink_valid
wire [101:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_012:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_012:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_010:sink_valid
wire [101:0] router_012_src_data; // router_012:src_data -> rsp_demux_010:sink_data
wire router_012_src_ready; // rsp_demux_010:sink_ready -> router_012:src_ready
wire [10:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_010:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_010:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_010:sink_endofpacket
wire router_src_valid; // router:src_valid -> nios2_gen2_0_data_master_limiter:cmd_sink_valid
wire [101:0] router_src_data; // router:src_data -> nios2_gen2_0_data_master_limiter:cmd_sink_data
wire router_src_ready; // nios2_gen2_0_data_master_limiter:cmd_sink_ready -> router:src_ready
wire [10:0] router_src_channel; // router:src_channel -> nios2_gen2_0_data_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_endofpacket
wire [101:0] nios2_gen2_0_data_master_limiter_cmd_src_data; // nios2_gen2_0_data_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire nios2_gen2_0_data_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> nios2_gen2_0_data_master_limiter:cmd_src_ready
wire [10:0] nios2_gen2_0_data_master_limiter_cmd_src_channel; // nios2_gen2_0_data_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire nios2_gen2_0_data_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire nios2_gen2_0_data_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_gen2_0_data_master_limiter:rsp_sink_valid
wire [101:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_gen2_0_data_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // nios2_gen2_0_data_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [10:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_gen2_0_data_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_valid; // nios2_gen2_0_data_master_limiter:rsp_src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [101:0] nios2_gen2_0_data_master_limiter_rsp_src_data; // nios2_gen2_0_data_master_limiter:rsp_src_data -> nios2_gen2_0_data_master_agent:rp_data
wire nios2_gen2_0_data_master_limiter_rsp_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> nios2_gen2_0_data_master_limiter:rsp_src_ready
wire [10:0] nios2_gen2_0_data_master_limiter_rsp_src_channel; // nios2_gen2_0_data_master_limiter:rsp_src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire nios2_gen2_0_data_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> nios2_gen2_0_instruction_master_limiter:cmd_sink_valid
wire [101:0] router_001_src_data; // router_001:src_data -> nios2_gen2_0_instruction_master_limiter:cmd_sink_data
wire router_001_src_ready; // nios2_gen2_0_instruction_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [10:0] router_001_src_channel; // router_001:src_channel -> nios2_gen2_0_instruction_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_endofpacket
wire [101:0] nios2_gen2_0_instruction_master_limiter_cmd_src_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire nios2_gen2_0_instruction_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_gen2_0_instruction_master_limiter:cmd_src_ready
wire [10:0] nios2_gen2_0_instruction_master_limiter_cmd_src_channel; // nios2_gen2_0_instruction_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_instruction_master_limiter:rsp_sink_valid
wire [101:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_instruction_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_instruction_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [10:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_valid; // nios2_gen2_0_instruction_master_limiter:rsp_src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [101:0] nios2_gen2_0_instruction_master_limiter_rsp_src_data; // nios2_gen2_0_instruction_master_limiter:rsp_src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire nios2_gen2_0_instruction_master_limiter_rsp_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> nios2_gen2_0_instruction_master_limiter:rsp_src_ready
wire [10:0] nios2_gen2_0_instruction_master_limiter_rsp_src_channel; // nios2_gen2_0_instruction_master_limiter:rsp_src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire sdram_tri_controller_0_s1_burst_adapter_source0_valid; // sdram_tri_controller_0_s1_burst_adapter:source0_valid -> sdram_tri_controller_0_s1_agent:cp_valid
wire [83:0] sdram_tri_controller_0_s1_burst_adapter_source0_data; // sdram_tri_controller_0_s1_burst_adapter:source0_data -> sdram_tri_controller_0_s1_agent:cp_data
wire sdram_tri_controller_0_s1_burst_adapter_source0_ready; // sdram_tri_controller_0_s1_agent:cp_ready -> sdram_tri_controller_0_s1_burst_adapter:source0_ready
wire [10:0] sdram_tri_controller_0_s1_burst_adapter_source0_channel; // sdram_tri_controller_0_s1_burst_adapter:source0_channel -> sdram_tri_controller_0_s1_agent:cp_channel
wire sdram_tri_controller_0_s1_burst_adapter_source0_startofpacket; // sdram_tri_controller_0_s1_burst_adapter:source0_startofpacket -> sdram_tri_controller_0_s1_agent:cp_startofpacket
wire sdram_tri_controller_0_s1_burst_adapter_source0_endofpacket; // sdram_tri_controller_0_s1_burst_adapter:source0_endofpacket -> sdram_tri_controller_0_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [101:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [10:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [101:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [10:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [101:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [10:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [101:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [10:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [101:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [10:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [101:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [10:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [101:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [10:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [101:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [10:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [101:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [10:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_src9_valid; // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
wire [101:0] cmd_demux_src9_data; // cmd_demux:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
wire [10:0] cmd_demux_src9_channel; // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_src9_startofpacket; // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_src9_endofpacket; // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_src10_valid; // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
wire [101:0] cmd_demux_src10_data; // cmd_demux:src10_data -> cmd_mux_010:sink0_data
wire cmd_demux_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
wire [10:0] cmd_demux_src10_channel; // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
wire cmd_demux_src10_startofpacket; // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
wire cmd_demux_src10_endofpacket; // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [101:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [10:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [101:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [10:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire [101:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire [10:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
wire [101:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
wire [10:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink1_valid
wire [101:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink1_data
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink1_ready -> cmd_demux_001:src4_ready
wire [10:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink1_channel
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink1_startofpacket
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink1_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink1_valid
wire [101:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink1_data
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink1_ready -> cmd_demux_001:src5_ready
wire [10:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink1_channel
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink1_startofpacket
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink1_endofpacket
wire cmd_demux_001_src6_valid; // cmd_demux_001:src6_valid -> cmd_mux_006:sink1_valid
wire [101:0] cmd_demux_001_src6_data; // cmd_demux_001:src6_data -> cmd_mux_006:sink1_data
wire cmd_demux_001_src6_ready; // cmd_mux_006:sink1_ready -> cmd_demux_001:src6_ready
wire [10:0] cmd_demux_001_src6_channel; // cmd_demux_001:src6_channel -> cmd_mux_006:sink1_channel
wire cmd_demux_001_src6_startofpacket; // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink1_startofpacket
wire cmd_demux_001_src6_endofpacket; // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink1_endofpacket
wire cmd_demux_001_src7_valid; // cmd_demux_001:src7_valid -> cmd_mux_007:sink1_valid
wire [101:0] cmd_demux_001_src7_data; // cmd_demux_001:src7_data -> cmd_mux_007:sink1_data
wire cmd_demux_001_src7_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src7_ready
wire [10:0] cmd_demux_001_src7_channel; // cmd_demux_001:src7_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_001_src7_startofpacket; // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_001_src7_endofpacket; // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink1_endofpacket
wire cmd_demux_001_src8_valid; // cmd_demux_001:src8_valid -> cmd_mux_008:sink1_valid
wire [101:0] cmd_demux_001_src8_data; // cmd_demux_001:src8_data -> cmd_mux_008:sink1_data
wire cmd_demux_001_src8_ready; // cmd_mux_008:sink1_ready -> cmd_demux_001:src8_ready
wire [10:0] cmd_demux_001_src8_channel; // cmd_demux_001:src8_channel -> cmd_mux_008:sink1_channel
wire cmd_demux_001_src8_startofpacket; // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink1_startofpacket
wire cmd_demux_001_src8_endofpacket; // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink1_endofpacket
wire cmd_demux_001_src9_valid; // cmd_demux_001:src9_valid -> cmd_mux_009:sink1_valid
wire [101:0] cmd_demux_001_src9_data; // cmd_demux_001:src9_data -> cmd_mux_009:sink1_data
wire cmd_demux_001_src9_ready; // cmd_mux_009:sink1_ready -> cmd_demux_001:src9_ready
wire [10:0] cmd_demux_001_src9_channel; // cmd_demux_001:src9_channel -> cmd_mux_009:sink1_channel
wire cmd_demux_001_src9_startofpacket; // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink1_startofpacket
wire cmd_demux_001_src9_endofpacket; // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink1_endofpacket
wire cmd_demux_001_src10_valid; // cmd_demux_001:src10_valid -> cmd_mux_010:sink1_valid
wire [101:0] cmd_demux_001_src10_data; // cmd_demux_001:src10_data -> cmd_mux_010:sink1_data
wire cmd_demux_001_src10_ready; // cmd_mux_010:sink1_ready -> cmd_demux_001:src10_ready
wire [10:0] cmd_demux_001_src10_channel; // cmd_demux_001:src10_channel -> cmd_mux_010:sink1_channel
wire cmd_demux_001_src10_startofpacket; // cmd_demux_001:src10_startofpacket -> cmd_mux_010:sink1_startofpacket
wire cmd_demux_001_src10_endofpacket; // cmd_demux_001:src10_endofpacket -> cmd_mux_010:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [101:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [10:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [101:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [10:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [101:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [10:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [101:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [10:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [101:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [10:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire [101:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [10:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [101:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [10:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
wire [101:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
wire [10:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [101:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [10:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src1_valid; // rsp_demux_004:src1_valid -> rsp_mux_001:sink4_valid
wire [101:0] rsp_demux_004_src1_data; // rsp_demux_004:src1_data -> rsp_mux_001:sink4_data
wire rsp_demux_004_src1_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src1_ready
wire [10:0] rsp_demux_004_src1_channel; // rsp_demux_004:src1_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src1_startofpacket; // rsp_demux_004:src1_startofpacket -> rsp_mux_001:sink4_startofpacket
wire rsp_demux_004_src1_endofpacket; // rsp_demux_004:src1_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [101:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [10:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_001:sink5_valid
wire [101:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_001:sink5_data
wire rsp_demux_005_src1_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src1_ready
wire [10:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink5_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [101:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [10:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_001:sink6_valid
wire [101:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_001:sink6_data
wire rsp_demux_006_src1_ready; // rsp_mux_001:sink6_ready -> rsp_demux_006:src1_ready
wire [10:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_001:sink6_channel
wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink6_startofpacket
wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink6_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [101:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [10:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink7_valid
wire [101:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink7_data
wire rsp_demux_007_src1_ready; // rsp_mux_001:sink7_ready -> rsp_demux_007:src1_ready
wire [10:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink7_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink7_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [101:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [10:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_008_src1_valid; // rsp_demux_008:src1_valid -> rsp_mux_001:sink8_valid
wire [101:0] rsp_demux_008_src1_data; // rsp_demux_008:src1_data -> rsp_mux_001:sink8_data
wire rsp_demux_008_src1_ready; // rsp_mux_001:sink8_ready -> rsp_demux_008:src1_ready
wire [10:0] rsp_demux_008_src1_channel; // rsp_demux_008:src1_channel -> rsp_mux_001:sink8_channel
wire rsp_demux_008_src1_startofpacket; // rsp_demux_008:src1_startofpacket -> rsp_mux_001:sink8_startofpacket
wire rsp_demux_008_src1_endofpacket; // rsp_demux_008:src1_endofpacket -> rsp_mux_001:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
wire [101:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
wire [10:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
wire rsp_demux_009_src1_valid; // rsp_demux_009:src1_valid -> rsp_mux_001:sink9_valid
wire [101:0] rsp_demux_009_src1_data; // rsp_demux_009:src1_data -> rsp_mux_001:sink9_data
wire rsp_demux_009_src1_ready; // rsp_mux_001:sink9_ready -> rsp_demux_009:src1_ready
wire [10:0] rsp_demux_009_src1_channel; // rsp_demux_009:src1_channel -> rsp_mux_001:sink9_channel
wire rsp_demux_009_src1_startofpacket; // rsp_demux_009:src1_startofpacket -> rsp_mux_001:sink9_startofpacket
wire rsp_demux_009_src1_endofpacket; // rsp_demux_009:src1_endofpacket -> rsp_mux_001:sink9_endofpacket
wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
wire [101:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux:sink10_data
wire rsp_demux_010_src0_ready; // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
wire [10:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
wire rsp_demux_010_src1_valid; // rsp_demux_010:src1_valid -> rsp_mux_001:sink10_valid
wire [101:0] rsp_demux_010_src1_data; // rsp_demux_010:src1_data -> rsp_mux_001:sink10_data
wire rsp_demux_010_src1_ready; // rsp_mux_001:sink10_ready -> rsp_demux_010:src1_ready
wire [10:0] rsp_demux_010_src1_channel; // rsp_demux_010:src1_channel -> rsp_mux_001:sink10_channel
wire rsp_demux_010_src1_startofpacket; // rsp_demux_010:src1_startofpacket -> rsp_mux_001:sink10_startofpacket
wire rsp_demux_010_src1_endofpacket; // rsp_demux_010:src1_endofpacket -> rsp_mux_001:sink10_endofpacket
wire router_009_src_valid; // router_009:src_valid -> sdram_tri_controller_0_s1_rsp_width_adapter:in_valid
wire [83:0] router_009_src_data; // router_009:src_data -> sdram_tri_controller_0_s1_rsp_width_adapter:in_data
wire router_009_src_ready; // sdram_tri_controller_0_s1_rsp_width_adapter:in_ready -> router_009:src_ready
wire [10:0] router_009_src_channel; // router_009:src_channel -> sdram_tri_controller_0_s1_rsp_width_adapter:in_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> sdram_tri_controller_0_s1_rsp_width_adapter:in_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> sdram_tri_controller_0_s1_rsp_width_adapter:in_endofpacket
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_valid; // sdram_tri_controller_0_s1_rsp_width_adapter:out_valid -> rsp_demux_007:sink_valid
wire [101:0] sdram_tri_controller_0_s1_rsp_width_adapter_src_data; // sdram_tri_controller_0_s1_rsp_width_adapter:out_data -> rsp_demux_007:sink_data
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_ready; // rsp_demux_007:sink_ready -> sdram_tri_controller_0_s1_rsp_width_adapter:out_ready
wire [10:0] sdram_tri_controller_0_s1_rsp_width_adapter_src_channel; // sdram_tri_controller_0_s1_rsp_width_adapter:out_channel -> rsp_demux_007:sink_channel
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_startofpacket; // sdram_tri_controller_0_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_007:sink_startofpacket
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_endofpacket; // sdram_tri_controller_0_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_007:sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sdram_tri_controller_0_s1_cmd_width_adapter:in_valid
wire [101:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sdram_tri_controller_0_s1_cmd_width_adapter:in_data
wire cmd_mux_007_src_ready; // sdram_tri_controller_0_s1_cmd_width_adapter:in_ready -> cmd_mux_007:src_ready
wire [10:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sdram_tri_controller_0_s1_cmd_width_adapter:in_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sdram_tri_controller_0_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sdram_tri_controller_0_s1_cmd_width_adapter:in_endofpacket
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_valid; // sdram_tri_controller_0_s1_cmd_width_adapter:out_valid -> sdram_tri_controller_0_s1_burst_adapter:sink0_valid
wire [83:0] sdram_tri_controller_0_s1_cmd_width_adapter_src_data; // sdram_tri_controller_0_s1_cmd_width_adapter:out_data -> sdram_tri_controller_0_s1_burst_adapter:sink0_data
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_ready; // sdram_tri_controller_0_s1_burst_adapter:sink0_ready -> sdram_tri_controller_0_s1_cmd_width_adapter:out_ready
wire [10:0] sdram_tri_controller_0_s1_cmd_width_adapter_src_channel; // sdram_tri_controller_0_s1_cmd_width_adapter:out_channel -> sdram_tri_controller_0_s1_burst_adapter:sink0_channel
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_startofpacket; // sdram_tri_controller_0_s1_cmd_width_adapter:out_startofpacket -> sdram_tri_controller_0_s1_burst_adapter:sink0_startofpacket
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_endofpacket; // sdram_tri_controller_0_s1_cmd_width_adapter:out_endofpacket -> sdram_tri_controller_0_s1_burst_adapter:sink0_endofpacket
wire [10:0] nios2_gen2_0_data_master_limiter_cmd_valid_data; // nios2_gen2_0_data_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [10:0] nios2_gen2_0_instruction_master_limiter_cmd_valid_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire vic_0_csr_access_agent_rdata_fifo_src_valid; // vic_0_csr_access_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] vic_0_csr_access_agent_rdata_fifo_src_data; // vic_0_csr_access_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire vic_0_csr_access_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> vic_0_csr_access_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> vic_0_csr_access_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> vic_0_csr_access_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // vic_0_csr_access_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> vic_0_csr_access_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire uart_0_s1_agent_rdata_fifo_src_valid; // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] uart_0_s1_agent_rdata_fifo_src_data; // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire uart_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
wire uart_1_s1_agent_rdata_fifo_src_valid; // uart_1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] uart_1_s1_agent_rdata_fifo_src_data; // uart_1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire uart_1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> uart_1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> uart_1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> uart_1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // uart_1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> uart_1_s1_agent:rdata_fifo_sink_error
wire uart_2_s1_agent_rdata_fifo_src_valid; // uart_2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] uart_2_s1_agent_rdata_fifo_src_data; // uart_2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire uart_2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> uart_2_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> uart_2_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> uart_2_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // uart_2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> uart_2_s1_agent:rdata_fifo_sink_error
wire uart_3_s1_agent_rdata_fifo_src_valid; // uart_3_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] uart_3_s1_agent_rdata_fifo_src_data; // uart_3_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
wire uart_3_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> uart_3_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> uart_3_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> uart_3_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // uart_3_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> uart_3_s1_agent:rdata_fifo_sink_error
wire sdram_tri_controller_0_s1_agent_rdata_fifo_out_valid; // sdram_tri_controller_0_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_007:in_0_valid
wire [17:0] sdram_tri_controller_0_s1_agent_rdata_fifo_out_data; // sdram_tri_controller_0_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_007:in_0_data
wire sdram_tri_controller_0_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter_007:in_0_ready -> sdram_tri_controller_0_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> sdram_tri_controller_0_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> sdram_tri_controller_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // sdram_tri_controller_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> sdram_tri_controller_0_s1_agent:rdata_fifo_sink_error
wire io_update_s1_agent_rdata_fifo_src_valid; // io_update_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] io_update_s1_agent_rdata_fifo_src_data; // io_update_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
wire io_update_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> io_update_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> io_update_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> io_update_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // io_update_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> io_update_s1_agent:rdata_fifo_sink_error
wire pps_interrupt_s1_agent_rdata_fifo_src_valid; // pps_interrupt_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
wire [33:0] pps_interrupt_s1_agent_rdata_fifo_src_data; // pps_interrupt_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
wire pps_interrupt_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> pps_interrupt_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> pps_interrupt_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> pps_interrupt_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_009_out_0_ready; // pps_interrupt_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> pps_interrupt_s1_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_010:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_010:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_010:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_010_out_0_valid; // avalon_st_adapter_010:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_010_out_0_data; // avalon_st_adapter_010:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_010_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
wire [0:0] avalon_st_adapter_010_out_0_error; // avalon_st_adapter_010:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_data_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (5),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (avalon_mapped_timer_reg_buf_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (avalon_mapped_timer_reg_buf_0_avalon_slave_0_write), // .write
.av_read (avalon_mapped_timer_reg_buf_0_avalon_slave_0_read), // .read
.av_readdata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata), // .readdata
.av_writedata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) vic_0_csr_access_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (vic_0_csr_access_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (vic_0_csr_access_agent_m0_burstcount), // .burstcount
.uav_read (vic_0_csr_access_agent_m0_read), // .read
.uav_write (vic_0_csr_access_agent_m0_write), // .write
.uav_waitrequest (vic_0_csr_access_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (vic_0_csr_access_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (vic_0_csr_access_agent_m0_byteenable), // .byteenable
.uav_readdata (vic_0_csr_access_agent_m0_readdata), // .readdata
.uav_writedata (vic_0_csr_access_agent_m0_writedata), // .writedata
.uav_lock (vic_0_csr_access_agent_m0_lock), // .lock
.uav_debugaccess (vic_0_csr_access_agent_m0_debugaccess), // .debugaccess
.av_address (vic_0_csr_access_address), // avalon_anti_slave_0.address
.av_write (vic_0_csr_access_write), // .write
.av_read (vic_0_csr_access_read), // .read
.av_readdata (vic_0_csr_access_readdata), // .readdata
.av_writedata (vic_0_csr_access_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_0_s1_agent_m0_read), // .read
.uav_write (uart_0_s1_agent_m0_write), // .write
.uav_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_0_s1_address), // avalon_anti_slave_0.address
.av_write (uart_0_s1_write), // .write
.av_read (uart_0_s1_read), // .read
.av_readdata (uart_0_s1_readdata), // .readdata
.av_writedata (uart_0_s1_writedata), // .writedata
.av_begintransfer (uart_0_s1_begintransfer), // .begintransfer
.av_chipselect (uart_0_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_1_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_1_s1_agent_m0_read), // .read
.uav_write (uart_1_s1_agent_m0_write), // .write
.uav_waitrequest (uart_1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_1_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_1_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_1_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_1_s1_address), // avalon_anti_slave_0.address
.av_write (uart_1_s1_write), // .write
.av_read (uart_1_s1_read), // .read
.av_readdata (uart_1_s1_readdata), // .readdata
.av_writedata (uart_1_s1_writedata), // .writedata
.av_begintransfer (uart_1_s1_begintransfer), // .begintransfer
.av_chipselect (uart_1_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_2_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_2_s1_agent_m0_read), // .read
.uav_write (uart_2_s1_agent_m0_write), // .write
.uav_waitrequest (uart_2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_2_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_2_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_2_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_2_s1_address), // avalon_anti_slave_0.address
.av_write (uart_2_s1_write), // .write
.av_read (uart_2_s1_read), // .read
.av_readdata (uart_2_s1_readdata), // .readdata
.av_writedata (uart_2_s1_writedata), // .writedata
.av_begintransfer (uart_2_s1_begintransfer), // .begintransfer
.av_chipselect (uart_2_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_3_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_3_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_3_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_3_s1_agent_m0_read), // .read
.uav_write (uart_3_s1_agent_m0_write), // .write
.uav_waitrequest (uart_3_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_3_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_3_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_3_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_3_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_3_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_3_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_3_s1_address), // avalon_anti_slave_0.address
.av_write (uart_3_s1_write), // .write
.av_read (uart_3_s1_read), // .read
.av_readdata (uart_3_s1_readdata), // .readdata
.av_writedata (uart_3_s1_writedata), // .writedata
.av_begintransfer (uart_3_s1_begintransfer), // .begintransfer
.av_chipselect (uart_3_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_tri_controller_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_tri_controller_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_tri_controller_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_tri_controller_0_s1_agent_m0_read), // .read
.uav_write (sdram_tri_controller_0_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_tri_controller_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_tri_controller_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_tri_controller_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_tri_controller_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_tri_controller_0_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_tri_controller_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_tri_controller_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_tri_controller_0_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_tri_controller_0_s1_write), // .write
.av_read (sdram_tri_controller_0_s1_read), // .read
.av_readdata (sdram_tri_controller_0_s1_readdata), // .readdata
.av_writedata (sdram_tri_controller_0_s1_writedata), // .writedata
.av_byteenable (sdram_tri_controller_0_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_tri_controller_0_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_tri_controller_0_s1_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) io_update_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (io_update_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (io_update_s1_agent_m0_burstcount), // .burstcount
.uav_read (io_update_s1_agent_m0_read), // .read
.uav_write (io_update_s1_agent_m0_write), // .write
.uav_waitrequest (io_update_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (io_update_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (io_update_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (io_update_s1_agent_m0_readdata), // .readdata
.uav_writedata (io_update_s1_agent_m0_writedata), // .writedata
.uav_lock (io_update_s1_agent_m0_lock), // .lock
.uav_debugaccess (io_update_s1_agent_m0_debugaccess), // .debugaccess
.av_address (io_update_s1_address), // avalon_anti_slave_0.address
.av_write (io_update_s1_write), // .write
.av_readdata (io_update_s1_readdata), // .readdata
.av_writedata (io_update_s1_writedata), // .writedata
.av_chipselect (io_update_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pps_interrupt_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pps_interrupt_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pps_interrupt_s1_agent_m0_burstcount), // .burstcount
.uav_read (pps_interrupt_s1_agent_m0_read), // .read
.uav_write (pps_interrupt_s1_agent_m0_write), // .write
.uav_waitrequest (pps_interrupt_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pps_interrupt_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pps_interrupt_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pps_interrupt_s1_agent_m0_readdata), // .readdata
.uav_writedata (pps_interrupt_s1_agent_m0_writedata), // .writedata
.uav_lock (pps_interrupt_s1_agent_m0_lock), // .lock
.uav_debugaccess (pps_interrupt_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pps_interrupt_s1_address), // avalon_anti_slave_0.address
.av_write (pps_interrupt_s1_write), // .write
.av_readdata (pps_interrupt_s1_readdata), // .readdata
.av_writedata (pps_interrupt_s1_writedata), // .writedata
.av_chipselect (pps_interrupt_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_QOS_H (80),
.PKT_QOS_L (80),
.PKT_DATA_SIDEBAND_H (78),
.PKT_DATA_SIDEBAND_L (78),
.PKT_ADDR_SIDEBAND_H (77),
.PKT_ADDR_SIDEBAND_L (77),
.PKT_BURST_TYPE_H (76),
.PKT_BURST_TYPE_L (75),
.PKT_CACHE_H (96),
.PKT_CACHE_L (93),
.PKT_THREAD_ID_H (89),
.PKT_THREAD_ID_L (89),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_EXCLUSIVE (65),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_QOS_H (80),
.PKT_QOS_L (80),
.PKT_DATA_SIDEBAND_H (78),
.PKT_DATA_SIDEBAND_L (78),
.PKT_ADDR_SIDEBAND_H (77),
.PKT_ADDR_SIDEBAND_L (77),
.PKT_BURST_TYPE_H (76),
.PKT_BURST_TYPE_L (75),
.PKT_CACHE_H (96),
.PKT_CACHE_L (93),
.PKT_THREAD_ID_H (89),
.PKT_THREAD_ID_L (89),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_EXCLUSIVE (65),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) vic_0_csr_access_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (vic_0_csr_access_agent_m0_address), // m0.address
.m0_burstcount (vic_0_csr_access_agent_m0_burstcount), // .burstcount
.m0_byteenable (vic_0_csr_access_agent_m0_byteenable), // .byteenable
.m0_debugaccess (vic_0_csr_access_agent_m0_debugaccess), // .debugaccess
.m0_lock (vic_0_csr_access_agent_m0_lock), // .lock
.m0_readdata (vic_0_csr_access_agent_m0_readdata), // .readdata
.m0_readdatavalid (vic_0_csr_access_agent_m0_readdatavalid), // .readdatavalid
.m0_read (vic_0_csr_access_agent_m0_read), // .read
.m0_waitrequest (vic_0_csr_access_agent_m0_waitrequest), // .waitrequest
.m0_writedata (vic_0_csr_access_agent_m0_writedata), // .writedata
.m0_write (vic_0_csr_access_agent_m0_write), // .write
.rp_endofpacket (vic_0_csr_access_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (vic_0_csr_access_agent_rp_ready), // .ready
.rp_valid (vic_0_csr_access_agent_rp_valid), // .valid
.rp_data (vic_0_csr_access_agent_rp_data), // .data
.rp_startofpacket (vic_0_csr_access_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (vic_0_csr_access_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (vic_0_csr_access_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (vic_0_csr_access_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (vic_0_csr_access_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (vic_0_csr_access_agent_rsp_fifo_out_data), // .data
.rf_source_ready (vic_0_csr_access_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (vic_0_csr_access_agent_rf_source_valid), // .valid
.rf_source_startofpacket (vic_0_csr_access_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (vic_0_csr_access_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (vic_0_csr_access_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (vic_0_csr_access_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (vic_0_csr_access_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (vic_0_csr_access_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) vic_0_csr_access_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (vic_0_csr_access_agent_rf_source_data), // in.data
.in_valid (vic_0_csr_access_agent_rf_source_valid), // .valid
.in_ready (vic_0_csr_access_agent_rf_source_ready), // .ready
.in_startofpacket (vic_0_csr_access_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (vic_0_csr_access_agent_rf_source_endofpacket), // .endofpacket
.out_data (vic_0_csr_access_agent_rsp_fifo_out_data), // out.data
.out_valid (vic_0_csr_access_agent_rsp_fifo_out_valid), // .valid
.out_ready (vic_0_csr_access_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (vic_0_csr_access_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (vic_0_csr_access_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_0_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_0_s1_agent_m0_lock), // .lock
.m0_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_0_s1_agent_m0_read), // .read
.m0_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.m0_write (uart_0_s1_agent_m0_write), // .write
.rp_endofpacket (uart_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_0_s1_agent_rp_ready), // .ready
.rp_valid (uart_0_s1_agent_rp_valid), // .valid
.rp_data (uart_0_s1_agent_rp_data), // .data
.rp_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (uart_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (uart_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_0_s1_agent_rf_source_data), // in.data
.in_valid (uart_0_s1_agent_rf_source_valid), // .valid
.in_ready (uart_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_1_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_1_s1_agent_m0_lock), // .lock
.m0_readdata (uart_1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_1_s1_agent_m0_read), // .read
.m0_waitrequest (uart_1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_1_s1_agent_m0_writedata), // .writedata
.m0_write (uart_1_s1_agent_m0_write), // .write
.rp_endofpacket (uart_1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_1_s1_agent_rp_ready), // .ready
.rp_valid (uart_1_s1_agent_rp_valid), // .valid
.rp_data (uart_1_s1_agent_rp_data), // .data
.rp_startofpacket (uart_1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (uart_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (uart_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_1_s1_agent_rf_source_data), // in.data
.in_valid (uart_1_s1_agent_rf_source_valid), // .valid
.in_ready (uart_1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_2_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_2_s1_agent_m0_lock), // .lock
.m0_readdata (uart_2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_2_s1_agent_m0_read), // .read
.m0_waitrequest (uart_2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_2_s1_agent_m0_writedata), // .writedata
.m0_write (uart_2_s1_agent_m0_write), // .write
.rp_endofpacket (uart_2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_2_s1_agent_rp_ready), // .ready
.rp_valid (uart_2_s1_agent_rp_valid), // .valid
.rp_data (uart_2_s1_agent_rp_data), // .data
.rp_startofpacket (uart_2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (uart_2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (uart_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_2_s1_agent_rf_source_data), // in.data
.in_valid (uart_2_s1_agent_rf_source_valid), // .valid
.in_ready (uart_2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_3_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_3_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_3_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_3_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_3_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_3_s1_agent_m0_lock), // .lock
.m0_readdata (uart_3_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_3_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_3_s1_agent_m0_read), // .read
.m0_waitrequest (uart_3_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_3_s1_agent_m0_writedata), // .writedata
.m0_write (uart_3_s1_agent_m0_write), // .write
.rp_endofpacket (uart_3_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_3_s1_agent_rp_ready), // .ready
.rp_valid (uart_3_s1_agent_rp_valid), // .valid
.rp_data (uart_3_s1_agent_rp_data), // .data
.rp_startofpacket (uart_3_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (uart_3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_3_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_3_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_3_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_3_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_3_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_3_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_3_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (uart_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_3_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_3_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_3_s1_agent_rf_source_data), // in.data
.in_valid (uart_3_s1_agent_rf_source_valid), // .valid
.in_ready (uart_3_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_3_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_3_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_3_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_3_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_3_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (83),
.PKT_ORI_BURST_SIZE_L (81),
.PKT_RESPONSE_STATUS_H (80),
.PKT_RESPONSE_STATUS_L (79),
.PKT_BURST_SIZE_H (56),
.PKT_BURST_SIZE_L (54),
.PKT_TRANS_LOCK (46),
.PKT_BEGIN_BURST (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (72),
.PKT_BURSTWRAP_H (53),
.PKT_BURSTWRAP_L (51),
.PKT_BYTE_CNT_H (50),
.PKT_BYTE_CNT_L (48),
.PKT_ADDR_H (41),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (42),
.PKT_TRANS_POSTED (43),
.PKT_TRANS_WRITE (44),
.PKT_TRANS_READ (45),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (66),
.PKT_SRC_ID_L (63),
.PKT_DEST_ID_H (70),
.PKT_DEST_ID_L (67),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (84),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sdram_tri_controller_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_tri_controller_0_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_tri_controller_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_tri_controller_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_tri_controller_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_tri_controller_0_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_tri_controller_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_tri_controller_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_tri_controller_0_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_tri_controller_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_tri_controller_0_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_tri_controller_0_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_tri_controller_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_tri_controller_0_s1_agent_rp_ready), // .ready
.rp_valid (sdram_tri_controller_0_s1_agent_rp_valid), // .valid
.rp_data (sdram_tri_controller_0_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_tri_controller_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_tri_controller_0_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_tri_controller_0_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_tri_controller_0_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_tri_controller_0_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_tri_controller_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_tri_controller_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_tri_controller_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_tri_controller_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_tri_controller_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_tri_controller_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_tri_controller_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_tri_controller_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_tri_controller_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (85),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_tri_controller_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_tri_controller_0_s1_agent_rf_source_data), // in.data
.in_valid (sdram_tri_controller_0_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_tri_controller_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_tri_controller_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_tri_controller_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_tri_controller_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_tri_controller_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_tri_controller_0_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_tri_controller_0_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_tri_controller_0_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) io_update_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (io_update_s1_agent_m0_address), // m0.address
.m0_burstcount (io_update_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (io_update_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (io_update_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (io_update_s1_agent_m0_lock), // .lock
.m0_readdata (io_update_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (io_update_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (io_update_s1_agent_m0_read), // .read
.m0_waitrequest (io_update_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (io_update_s1_agent_m0_writedata), // .writedata
.m0_write (io_update_s1_agent_m0_write), // .write
.rp_endofpacket (io_update_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (io_update_s1_agent_rp_ready), // .ready
.rp_valid (io_update_s1_agent_rp_valid), // .valid
.rp_data (io_update_s1_agent_rp_data), // .data
.rp_startofpacket (io_update_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (io_update_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (io_update_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (io_update_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (io_update_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (io_update_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (io_update_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (io_update_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (io_update_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (io_update_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (io_update_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (io_update_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (io_update_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (io_update_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) io_update_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (io_update_s1_agent_rf_source_data), // in.data
.in_valid (io_update_s1_agent_rf_source_valid), // .valid
.in_ready (io_update_s1_agent_rf_source_ready), // .ready
.in_startofpacket (io_update_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (io_update_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (io_update_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (io_update_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (io_update_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (io_update_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (io_update_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pps_interrupt_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pps_interrupt_s1_agent_m0_address), // m0.address
.m0_burstcount (pps_interrupt_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pps_interrupt_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pps_interrupt_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pps_interrupt_s1_agent_m0_lock), // .lock
.m0_readdata (pps_interrupt_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pps_interrupt_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pps_interrupt_s1_agent_m0_read), // .read
.m0_waitrequest (pps_interrupt_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pps_interrupt_s1_agent_m0_writedata), // .writedata
.m0_write (pps_interrupt_s1_agent_m0_write), // .write
.rp_endofpacket (pps_interrupt_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pps_interrupt_s1_agent_rp_ready), // .ready
.rp_valid (pps_interrupt_s1_agent_rp_valid), // .valid
.rp_data (pps_interrupt_s1_agent_rp_data), // .data
.rp_startofpacket (pps_interrupt_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (pps_interrupt_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pps_interrupt_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pps_interrupt_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pps_interrupt_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pps_interrupt_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pps_interrupt_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pps_interrupt_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pps_interrupt_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pps_interrupt_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pps_interrupt_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
.rdata_fifo_src_ready (pps_interrupt_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pps_interrupt_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pps_interrupt_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pps_interrupt_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pps_interrupt_s1_agent_rf_source_data), // in.data
.in_valid (pps_interrupt_s1_agent_rf_source_valid), // .valid
.in_ready (pps_interrupt_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pps_interrupt_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pps_interrupt_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pps_interrupt_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pps_interrupt_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pps_interrupt_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pps_interrupt_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pps_interrupt_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_010_src_ready), // cp.ready
.cp_valid (cmd_mux_010_src_valid), // .valid
.cp_data (cmd_mux_010_src_data), // .data
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_010_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_010_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_010_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_010_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_010_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
TimeHoldOver_Qsys_mm_interconnect_0_router router (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router router_001 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_002 (
.sink_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_003 (
.sink_ready (vic_0_csr_access_agent_rp_ready), // sink.ready
.sink_valid (vic_0_csr_access_agent_rp_valid), // .valid
.sink_data (vic_0_csr_access_agent_rp_data), // .data
.sink_startofpacket (vic_0_csr_access_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (vic_0_csr_access_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_004 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_005 (
.sink_ready (uart_0_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_0_s1_agent_rp_valid), // .valid
.sink_data (uart_0_s1_agent_rp_data), // .data
.sink_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_006 (
.sink_ready (uart_1_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_1_s1_agent_rp_valid), // .valid
.sink_data (uart_1_s1_agent_rp_data), // .data
.sink_startofpacket (uart_1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_007 (
.sink_ready (uart_2_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_2_s1_agent_rp_valid), // .valid
.sink_data (uart_2_s1_agent_rp_data), // .data
.sink_startofpacket (uart_2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_008 (
.sink_ready (uart_3_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_3_s1_agent_rp_valid), // .valid
.sink_data (uart_3_s1_agent_rp_data), // .data
.sink_startofpacket (uart_3_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_3_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_009 router_009 (
.sink_ready (sdram_tri_controller_0_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_tri_controller_0_s1_agent_rp_valid), // .valid
.sink_data (sdram_tri_controller_0_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_tri_controller_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_tri_controller_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_010 (
.sink_ready (io_update_s1_agent_rp_ready), // sink.ready
.sink_valid (io_update_s1_agent_rp_valid), // .valid
.sink_data (io_update_s1_agent_rp_data), // .data
.sink_startofpacket (io_update_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (io_update_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_011 (
.sink_ready (pps_interrupt_s1_agent_rp_ready), // sink.ready
.sink_valid (pps_interrupt_s1_agent_rp_valid), // .valid
.sink_data (pps_interrupt_s1_agent_rp_data), // .data
.sink_startofpacket (pps_interrupt_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pps_interrupt_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_012 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.VALID_WIDTH (11),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_data_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.VALID_WIDTH (11),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_instruction_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (41),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (61),
.PKT_BYTE_CNT_H (50),
.PKT_BYTE_CNT_L (48),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (56),
.PKT_BURST_SIZE_L (54),
.PKT_BURST_TYPE_H (58),
.PKT_BURST_TYPE_L (57),
.PKT_BURSTWRAP_H (53),
.PKT_BURSTWRAP_L (51),
.PKT_TRANS_COMPRESSED_READ (42),
.PKT_TRANS_WRITE (44),
.PKT_TRANS_READ (45),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (84),
.ST_CHANNEL_W (11),
.OUT_BYTE_CNT_H (49),
.OUT_BURSTWRAP_H (53),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3),
.ADAPTER_VERSION ("13.1")
) sdram_tri_controller_0_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sdram_tri_controller_0_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sdram_tri_controller_0_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (sdram_tri_controller_0_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sdram_tri_controller_0_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (sdram_tri_controller_0_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_tri_controller_0_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_tri_controller_0_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_tri_controller_0_s1_burst_adapter_source0_ready) // .ready
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_src9_ready), // src9.ready
.src9_valid (cmd_demux_src9_valid), // .valid
.src9_data (cmd_demux_src9_data), // .data
.src9_channel (cmd_demux_src9_channel), // .channel
.src9_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_src10_ready), // src10.ready
.src10_valid (cmd_demux_src10_valid), // .valid
.src10_data (cmd_demux_src10_data), // .data
.src10_channel (cmd_demux_src10_channel), // .channel
.src10_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_src10_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_demux_001_src6_valid), // .valid
.src6_data (cmd_demux_001_src6_data), // .data
.src6_channel (cmd_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_demux_001_src7_valid), // .valid
.src7_data (cmd_demux_001_src7_data), // .data
.src7_channel (cmd_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_demux_001_src8_valid), // .valid
.src8_data (cmd_demux_001_src8_data), // .data
.src8_channel (cmd_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_001_src9_ready), // src9.ready
.src9_valid (cmd_demux_001_src9_valid), // .valid
.src9_data (cmd_demux_001_src9_data), // .data
.src9_channel (cmd_demux_001_src9_channel), // .channel
.src9_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_001_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_001_src10_ready), // src10.ready
.src10_valid (cmd_demux_001_src10_valid), // .valid
.src10_data (cmd_demux_001_src10_data), // .data
.src10_channel (cmd_demux_001_src10_channel), // .channel
.src10_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_001_src10_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src3_valid), // .valid
.sink1_channel (cmd_demux_001_src3_channel), // .channel
.sink1_data (cmd_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src4_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src4_valid), // .valid
.sink1_channel (cmd_demux_001_src4_channel), // .channel
.sink1_data (cmd_demux_001_src4_data), // .data
.sink1_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src5_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src5_valid), // .valid
.sink1_channel (cmd_demux_001_src5_channel), // .channel
.sink1_data (cmd_demux_001_src5_data), // .data
.sink1_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src6_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src6_valid), // .valid
.sink1_channel (cmd_demux_001_src6_channel), // .channel
.sink1_data (cmd_demux_001_src6_data), // .data
.sink1_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src6_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src7_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src7_valid), // .valid
.sink1_channel (cmd_demux_001_src7_channel), // .channel
.sink1_data (cmd_demux_001_src7_data), // .data
.sink1_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src7_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src8_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src8_valid), // .valid
.sink1_channel (cmd_demux_001_src8_channel), // .channel
.sink1_data (cmd_demux_001_src8_data), // .data
.sink1_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src8_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_src9_valid), // .valid
.sink0_channel (cmd_demux_src9_channel), // .channel
.sink0_data (cmd_demux_src9_data), // .data
.sink0_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src9_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src9_valid), // .valid
.sink1_channel (cmd_demux_001_src9_channel), // .channel
.sink1_data (cmd_demux_001_src9_data), // .data
.sink1_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src9_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_010_src_ready), // src.ready
.src_valid (cmd_mux_010_src_valid), // .valid
.src_data (cmd_mux_010_src_data), // .data
.src_channel (cmd_mux_010_src_channel), // .channel
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src10_ready), // sink0.ready
.sink0_valid (cmd_demux_src10_valid), // .valid
.sink0_channel (cmd_demux_src10_channel), // .channel
.sink0_data (cmd_demux_src10_data), // .data
.sink0_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src10_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src10_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src10_valid), // .valid
.sink1_channel (cmd_demux_001_src10_channel), // .channel
.sink1_data (cmd_demux_001_src10_data), // .data
.sink1_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src10_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_demux_004_src1_valid), // .valid
.src1_data (rsp_demux_004_src1_data), // .data
.src1_channel (rsp_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_004_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_demux_006_src1_valid), // .valid
.src1_data (rsp_demux_006_src1_data), // .data
.src1_channel (rsp_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sdram_tri_controller_0_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sdram_tri_controller_0_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sdram_tri_controller_0_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sdram_tri_controller_0_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_008_src1_ready), // src1.ready
.src1_valid (rsp_demux_008_src1_valid), // .valid
.src1_data (rsp_demux_008_src1_data), // .data
.src1_channel (rsp_demux_008_src1_channel), // .channel
.src1_startofpacket (rsp_demux_008_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_008_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_009_src1_ready), // src1.ready
.src1_valid (rsp_demux_009_src1_valid), // .valid
.src1_data (rsp_demux_009_src1_data), // .data
.src1_channel (rsp_demux_009_src1_channel), // .channel
.src1_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_009_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_demux_010_src0_valid), // .valid
.src0_data (rsp_demux_010_src0_data), // .data
.src0_channel (rsp_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_010_src1_ready), // src1.ready
.src1_valid (rsp_demux_010_src1_valid), // .valid
.src1_data (rsp_demux_010_src1_data), // .data
.src1_channel (rsp_demux_010_src1_channel), // .channel
.src1_startofpacket (rsp_demux_010_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_010_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src0_valid), // .valid
.sink10_channel (rsp_demux_010_src0_channel), // .channel
.sink10_data (rsp_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src1_valid), // .valid
.sink3_channel (rsp_demux_003_src1_channel), // .channel
.sink3_data (rsp_demux_003_src1_data), // .data
.sink3_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src1_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src1_valid), // .valid
.sink4_channel (rsp_demux_004_src1_channel), // .channel
.sink4_data (rsp_demux_004_src1_data), // .data
.sink4_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src1_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src1_valid), // .valid
.sink5_channel (rsp_demux_005_src1_channel), // .channel
.sink5_data (rsp_demux_005_src1_data), // .data
.sink5_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src1_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src1_valid), // .valid
.sink6_channel (rsp_demux_006_src1_channel), // .channel
.sink6_data (rsp_demux_006_src1_data), // .data
.sink6_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src1_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src1_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src1_valid), // .valid
.sink7_channel (rsp_demux_007_src1_channel), // .channel
.sink7_data (rsp_demux_007_src1_data), // .data
.sink7_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src1_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src1_valid), // .valid
.sink8_channel (rsp_demux_008_src1_channel), // .channel
.sink8_data (rsp_demux_008_src1_data), // .data
.sink8_startofpacket (rsp_demux_008_src1_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src1_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src1_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src1_valid), // .valid
.sink9_channel (rsp_demux_009_src1_channel), // .channel
.sink9_data (rsp_demux_009_src1_data), // .data
.sink9_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src1_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src1_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src1_valid), // .valid
.sink10_channel (rsp_demux_010_src1_channel), // .channel
.sink10_data (rsp_demux_010_src1_data), // .data
.sink10_startofpacket (rsp_demux_010_src1_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (41),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (50),
.IN_PKT_BYTE_CNT_L (48),
.IN_PKT_TRANS_COMPRESSED_READ (42),
.IN_PKT_TRANS_WRITE (44),
.IN_PKT_BURSTWRAP_H (53),
.IN_PKT_BURSTWRAP_L (51),
.IN_PKT_BURST_SIZE_H (56),
.IN_PKT_BURST_SIZE_L (54),
.IN_PKT_RESPONSE_STATUS_H (80),
.IN_PKT_RESPONSE_STATUS_L (79),
.IN_PKT_TRANS_EXCLUSIVE (47),
.IN_PKT_BURST_TYPE_H (58),
.IN_PKT_BURST_TYPE_L (57),
.IN_PKT_ORI_BURST_SIZE_L (81),
.IN_PKT_ORI_BURST_SIZE_H (83),
.IN_ST_DATA_W (84),
.OUT_PKT_ADDR_H (59),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (68),
.OUT_PKT_BYTE_CNT_L (66),
.OUT_PKT_TRANS_COMPRESSED_READ (60),
.OUT_PKT_BURST_SIZE_H (74),
.OUT_PKT_BURST_SIZE_L (72),
.OUT_PKT_RESPONSE_STATUS_H (98),
.OUT_PKT_RESPONSE_STATUS_L (97),
.OUT_PKT_TRANS_EXCLUSIVE (65),
.OUT_PKT_BURST_TYPE_H (76),
.OUT_PKT_BURST_TYPE_L (75),
.OUT_PKT_ORI_BURST_SIZE_L (99),
.OUT_PKT_ORI_BURST_SIZE_H (101),
.OUT_ST_DATA_W (102),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_tri_controller_0_s1_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_009_src_valid), // sink.valid
.in_channel (router_009_src_channel), // .channel
.in_startofpacket (router_009_src_startofpacket), // .startofpacket
.in_endofpacket (router_009_src_endofpacket), // .endofpacket
.in_ready (router_009_src_ready), // .ready
.in_data (router_009_src_data), // .data
.out_endofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_tri_controller_0_s1_rsp_width_adapter_src_data), // .data
.out_channel (sdram_tri_controller_0_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_tri_controller_0_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (59),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (68),
.IN_PKT_BYTE_CNT_L (66),
.IN_PKT_TRANS_COMPRESSED_READ (60),
.IN_PKT_TRANS_WRITE (62),
.IN_PKT_BURSTWRAP_H (71),
.IN_PKT_BURSTWRAP_L (69),
.IN_PKT_BURST_SIZE_H (74),
.IN_PKT_BURST_SIZE_L (72),
.IN_PKT_RESPONSE_STATUS_H (98),
.IN_PKT_RESPONSE_STATUS_L (97),
.IN_PKT_TRANS_EXCLUSIVE (65),
.IN_PKT_BURST_TYPE_H (76),
.IN_PKT_BURST_TYPE_L (75),
.IN_PKT_ORI_BURST_SIZE_L (99),
.IN_PKT_ORI_BURST_SIZE_H (101),
.IN_ST_DATA_W (102),
.OUT_PKT_ADDR_H (41),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (50),
.OUT_PKT_BYTE_CNT_L (48),
.OUT_PKT_TRANS_COMPRESSED_READ (42),
.OUT_PKT_BURST_SIZE_H (56),
.OUT_PKT_BURST_SIZE_L (54),
.OUT_PKT_RESPONSE_STATUS_H (80),
.OUT_PKT_RESPONSE_STATUS_L (79),
.OUT_PKT_TRANS_EXCLUSIVE (47),
.OUT_PKT_BURST_TYPE_H (58),
.OUT_PKT_BURST_TYPE_L (57),
.OUT_PKT_ORI_BURST_SIZE_L (81),
.OUT_PKT_ORI_BURST_SIZE_H (83),
.OUT_ST_DATA_W (84),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_tri_controller_0_s1_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_007_src_valid), // sink.valid
.in_channel (cmd_mux_007_src_channel), // .channel
.in_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_007_src_ready), // .ready
.in_data (cmd_mux_007_src_data), // .data
.out_endofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_tri_controller_0_s1_cmd_width_adapter_src_data), // .data
.out_channel (sdram_tri_controller_0_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sdram_tri_controller_0_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (vic_0_csr_access_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (vic_0_csr_access_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (vic_0_csr_access_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_2_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_2_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_2_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_3_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_3_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_3_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_007 #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sdram_tri_controller_0_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (io_update_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (io_update_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (io_update_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_009 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pps_interrupt_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (pps_interrupt_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (pps_interrupt_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_010 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_010_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_010_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_010_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_010_out_0_error) // .error
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_mc_controller
(
input ref_clk, // 100 MHz
input ctrl_data_clk,
// physical interface
output fmc_en_o,
output pwm_ah_o,
output pwm_al_o,
output pwm_bh_o,
output pwm_bl_o,
output pwm_ch_o,
output pwm_cl_o,
output [3:0] gpo_o,
// controller connections
input pwm_a_i,
input pwm_b_i,
input pwm_c_i,
input ctrl_data_valid_i,
input [31:0] ctrl_data0_i,
input [31:0] ctrl_data1_i,
input [31:0] ctrl_data2_i,
input [31:0] ctrl_data3_i,
input [31:0] ctrl_data4_i,
input [31:0] ctrl_data5_i,
input [31:0] ctrl_data6_i,
input [31:0] ctrl_data7_i,
// interconnection with other modules
output[1:0] sensors_o,
input [2:0] position_i,
// channel interface
output adc_clk_o,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
output adc_enable_c3,
output adc_enable_c4,
output adc_enable_c5,
output adc_enable_c6,
output adc_enable_c7,
output adc_valid_c0,
output adc_valid_c1,
output adc_valid_c2,
output adc_valid_c3,
output adc_valid_c4,
output adc_valid_c5,
output adc_valid_c6,
output adc_valid_c7,
output [31:0] adc_data_c0,
output [31:0] adc_data_c1,
output [31:0] adc_data_c2,
output [31:0] adc_data_c3,
output [31:0] adc_data_c4,
output [31:0] adc_data_c5,
output [31:0] adc_data_c6,
output [31:0] adc_data_c7,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg pwm_gen_clk = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire up_rreq_s;
wire up_wreq_s;
wire [13:0] up_raddr_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire [31:0] up_control_rdata_s;
wire [31:0] rdata_c0_s;
wire [31:0] rdata_c1_s;
wire [31:0] rdata_c2_s;
wire [31:0] rdata_c3_s;
wire [31:0] rdata_c4_s;
wire [31:0] rdata_c5_s;
wire [31:0] rdata_c6_s;
wire [31:0] rdata_c7_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire up_control_wack_s;
wire up_control_rack_s;
wire wack_c0_s;
wire rack_c0_s;
wire wack_c1_s;
wire rack_c1_s;
wire wack_c2_s;
wire rack_c2_s;
wire wack_c3_s;
wire rack_c3_s;
wire wack_c4_s;
wire rack_c4_s;
wire wack_c5_s;
wire rack_c5_s;
wire wack_c6_s;
wire rack_c6_s;
wire wack_c7_s;
wire rack_c7_s;
wire run_s;
wire star_delta_s;
wire dir_s;
wire [10:0] pwm_open_s;
wire [10:0] pwm_s;
wire dpwm_ah_s;
wire dpwm_al_s;
wire dpwm_bh_s;
wire dpwm_bl_s;
wire dpwm_ch_s;
wire dpwm_cl_s;
wire foc_ctrl_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ctrl_data_clk;
assign adc_valid_c0 = ctrl_data_valid_i;
assign adc_valid_c1 = ctrl_data_valid_i;
assign adc_valid_c2 = ctrl_data_valid_i;
assign adc_valid_c3 = ctrl_data_valid_i;
assign adc_valid_c4 = ctrl_data_valid_i;
assign adc_valid_c5 = ctrl_data_valid_i;
assign adc_valid_c6 = ctrl_data_valid_i;
assign adc_valid_c7 = ctrl_data_valid_i;
assign adc_data_c0 = ctrl_data0_i;
assign adc_data_c1 = ctrl_data1_i;
assign adc_data_c2 = ctrl_data2_i;
assign adc_data_c3 = ctrl_data3_i;
assign adc_data_c4 = ctrl_data4_i;
assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign ctrl_rst_o = !run_s;
// monitor signals
assign fmc_en_o = run_s;
assign pwm_s = pwm_open_s ;
assign pwm_ah_o = foc_ctrl_s ? !pwm_a_i : dpwm_ah_s;
assign pwm_al_o = foc_ctrl_s ? pwm_a_i : dpwm_al_s;
assign pwm_bh_o = foc_ctrl_s ? !pwm_b_i : dpwm_bh_s;
assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s;
assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s;
assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s;
// clock generation
always @(posedge ref_clk)
begin
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if(up_rstn == 0) begin
up_rdata <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
end else begin
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s;
up_rack <= up_control_rack_s | up_adc_common_rack_s | rack_c0_s | rack_c1_s | rack_c2_s | rack_c3_s | rack_c4_s | rack_c5_s | rack_c6_s | rack_c7_s;
up_wack <= up_control_wack_s | up_adc_common_wack_s | wack_c0_s | wack_c1_s | wack_c2_s | wack_c3_s | wack_c4_s | wack_c5_s | wack_c6_s | wack_c7_s;
end
end
// main (device interface)
motor_driver
#( .PWM_BITS(11))
motor_driver_inst(
.clk_i(ctrl_data_clk),
.pwm_clk_i(pwm_gen_clk),
.rst_n_i(up_rstn) ,
.run_i(run_s),
.star_delta_i(star_delta_s),
.dir_i(dir_s),
.position_i(position_i),
.pwm_duty_i(pwm_s),
.AH_o(dpwm_ah_s),
.BH_o(dpwm_bh_s),
.CH_o(dpwm_ch_s),
.AL_o(dpwm_al_s),
.BL_o(dpwm_bl_s),
.CL_o(dpwm_cl_s));
control_registers control_reg_inst(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_control_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_control_rdata_s),
.up_rack (up_control_rack_s),
.run_o(run_s),
.break_o(),
.dir_o(dir_s),
.star_delta_o(star_delta_s),
.sensors_o(sensors_o),
.kp_o(),
.ki_o(),
.kd_o(),
.kp1_o(),
.ki1_o(),
.kd1_o(),
.gpo_o(gpo_o),
.reference_speed_o(),
.oloop_matlab_o(foc_ctrl_s),
.err_i(32'h0),
.calibrate_adcs_o(),
.pwm_open_o(pwm_open_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c0),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c0_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c0_s),
.up_rack (rack_c0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c1),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c1_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c1_s),
.up_rack (rack_c1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c2),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c2_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c2_s),
.up_rack (rack_c2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c3),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c3_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c3_s),
.up_rack (rack_c3_s));
up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c4),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c4_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c4_s),
.up_rack (rack_c4_s));
up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c5),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c5_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c5_s),
.up_rack (rack_c5_s));
up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c6),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c6_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c6_s),
.up_rack (rack_c6_s));
up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c7),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c7_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c7_s),
.up_rack (rack_c7_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd7),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ============================================================================
// FFs
module CESR_MUX(input CE, SR, output CE_OUT, SR_OUT);
parameter _TECHMAP_CONSTMSK_CE_ = 0;
parameter _TECHMAP_CONSTVAL_CE_ = 0;
parameter _TECHMAP_CONSTMSK_SR_ = 0;
parameter _TECHMAP_CONSTVAL_SR_ = 0;
localparam CEUSED = _TECHMAP_CONSTMSK_CE_ == 0 || _TECHMAP_CONSTVAL_CE_ == 0;
localparam SRUSED = _TECHMAP_CONSTMSK_SR_ == 0 || _TECHMAP_CONSTVAL_SR_ == 1;
if(CEUSED) begin
assign CE_OUT = CE;
end else begin
CE_VCC ce(
.VCC(CE_OUT)
);
end
if(SRUSED) begin
assign SR_OUT = SR;
end else begin
SR_GND sr(
.GND(SR_OUT)
);
end
endmodule
module FD (output reg Q, input C, D);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(1'b1),
.SR(1'b0),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
endmodule
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(R),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
endmodule
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(S),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDSE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .S(SR_SIG));
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(CLR),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDCE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .CLR(SR_SIG));
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(PRE),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDPE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .PRE(SR_SIG));
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(R),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
endmodule
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(S),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDSE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .S(SR_SIG));
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(CLR),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDCE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .CLR(SR_SIG));
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(PRE),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDPE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .PRE(SR_SIG));
endmodule
// ============================================================================
// LUTs
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
\$lut #(
.WIDTH(1),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A(I0),
.Y(O)
);
endmodule
module LUT2(output O, input I0, I1);
parameter [3:0] INIT = 0;
\$lut #(
.WIDTH(2),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I1, I0}),
.Y(O)
);
endmodule
module LUT3(output O, input I0, I1, I2);
parameter [7:0] INIT = 0;
\$lut #(
.WIDTH(3),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I2, I1, I0}),
.Y(O)
);
endmodule
module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
\$lut #(
.WIDTH(4),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I3, I2, I1, I0}),
.Y(O)
);
endmodule
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
\$lut #(
.WIDTH(5),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I4, I3, I2, I1, I0}),
.Y(O)
);
endmodule
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire T0, T1;
\$lut #(
.WIDTH(5),
.LUT(INIT[31:0])
) fpga_lut_0 (
.A({I4, I3, I2, I1, I0}),
.Y(T0)
);
\$lut #(
.WIDTH(5),
.LUT(INIT[63:32])
) fpga_lut_1 (
.A({I4, I3, I2, I1, I0}),
.Y(T1)
);
MUXF6 fpga_mux_0 (.O(O), .I0(T0), .I1(T1), .S(I5));
endmodule
// ============================================================================
// Distributed RAMs
module RAM128X1S (
output O,
input D, WCLK, WE,
input A6, A5, A4, A3, A2, A1, A0
);
parameter [127:0] INIT = 128'bx;
parameter IS_WCLK_INVERTED = 0;
wire low_lut_o6;
wire high_lut_o6;
wire [5:0] A = {A5, A4, A3, A2, A1, A0};
// DPRAM64_for_RAM128X1D is used here because RAM128X1S only consumes half of the
// slice, but WA7USED is slice wide. The packer should be able to pack two
// RAM128X1S in a slice, but it should not be able to pack RAM128X1S and
// a RAM64X1[SD]. It is unclear if RAM32X1[SD] or RAM32X2S can be packed
// with a RAM128X1S, so for now it is forbidden.
//
// Note that a RAM128X1D does not require [SD]PRAM128 because it consumes
// the entire slice.
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram0 (
.DI(D),
.A(A),
.WA(A),
.WA7(A6),
.CLK(WCLK),
.WE(WE),
.O(low_lut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(1)
) ram1 (
.DI(D),
.A(A),
.WA(A),
.WA7(A6),
.CLK(WCLK),
.WE(WE),
.O(high_lut_o6)
);
MUXF7 ram_f7_mux (.O(O), .I0(low_lut_o6), .I1(high_lut_o6), .S(A6));
endmodule
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter [127:0] INIT = 128'bx;
parameter IS_WCLK_INVERTED = 0;
wire dlut_o6;
wire clut_o6;
wire blut_o6;
wire alut_o6;
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram0 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(dlut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(1)
) ram1 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(clut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram2 (
.DI(D),
.A(DPRA[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(blut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram3 (
.DI(D),
.A(DPRA[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(alut_o6)
);
wire SPO_FORCE;
wire DPO_FORCE;
MUXF7 f7b_mux (.O(SPO_FORCE), .I0(dlut_o6), .I1(clut_o6), .S(A[6]));
MUXF7 f7a_mux (.O(DPO_FORCE), .I0(blut_o6), .I1(alut_o6), .S(DPRA[6]));
DRAM_2_OUTPUT_STUB stub (
.SPO(SPO_FORCE), .DPO(DPO_FORCE),
.SPO_OUT(SPO), .DPO_OUT(DPO));
endmodule
module RAM256X1S (
output O,
input D, WCLK, WE,
input [7:0] A
);
parameter [256:0] INIT = 256'bx;
parameter IS_WCLK_INVERTED = 0;
wire dlut_o6;
wire clut_o6;
wire blut_o6;
wire alut_o6;
wire f7b_o;
wire f7a_o;
DPRAM64 #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(0),
.HIGH_WA8_SELECT(0)
) ram0 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(dlut_o6)
);
DPRAM64 #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(1),
.HIGH_WA8_SELECT(0)
) ram1 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(clut_o6)
);
DPRAM64 #(
.INIT(INIT[191:128]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(0),
.HIGH_WA8_SELECT(1)
) ram2 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(blut_o6)
);
DPRAM64 #(
.INIT(INIT[255:192]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(1),
.HIGH_WA8_SELECT(1)
) ram3 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(alut_o6)
);
MUXF7 f7b_mux (.O(f7b_o), .I0(dlut_o6), .I1(clut_o6), .S(A[6]));
MUXF7 f7a_mux (.O(f7a_o), .I0(blut_o6), .I1(alut_o6), .S(A[6]));
MUXF8 f8_mux (.O(O), .I0(f7b_o), .I1(f7a_o), .S(A[7]));
endmodule
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter [31:0] INIT = 32'bx;
parameter IS_WCLK_INVERTED = 0;
wire [4:0] WA = {A4, A3, A2, A1, A0};
wire [4:0] DPRA = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
wire SPO_FORCE, DPO_FORCE;
DPRAM32 #(
.INIT_00(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram0 (
.DI(D),
.A(WA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(SPO_FORCE)
);
DPRAM32 #(
.INIT_00(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram1 (
.DI(D),
.A(DPRA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(DPO_FORCE)
);
DRAM_2_OUTPUT_STUB stub (
.SPO(SPO_FORCE), .DPO(DPO_FORCE),
.SPO_OUT(SPO), .DPO_OUT(DPO));
endmodule
module RAM32X1S (
output O,
input D, WCLK, WE,
input A0, A1, A2, A3, A4
);
parameter [31:0] INIT = 32'bx;
parameter IS_WCLK_INVERTED = 0;
SPRAM32 #(
.INIT_00(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_S (
.DI(D),
.A({A4, A3, A2, A1, A0}),
.WA({A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O)
);
endmodule
module RAM32X2S (
output O0, O1,
input D0, D1, WCLK, WE,
input A0, A1, A2, A3, A4
);
parameter [31:0] INIT_00 = 32'bx;
parameter [31:0] INIT_01 = 32'bx;
parameter IS_WCLK_INVERTED = 0;
DPRAM32 #(
.INIT_00(INIT_00),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram0 (
.DI(D0),
.A({A4, A3, A2, A1, A0}),
.WA({A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O0)
);
DPRAM32 #(
.INIT_00(INIT_01),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram1 (
.DI(D1),
.A({A4, A3, A2, A1, A0}),
.WA({A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O1),
);
endmodule
module RAM32M (
output [1:0] DOA, DOB, DOC, DOD,
input [1:0] DIA, DIB, DIC, DID,
input [4:0] ADDRA, ADDRB, ADDRC, ADDRD,
input WE, WCLK
);
parameter [63:0] INIT_A = 64'bx;
parameter [63:0] INIT_B = 64'bx;
parameter [63:0] INIT_C = 64'bx;
parameter [63:0] INIT_D = 64'bx;
parameter IS_WCLK_INVERTED = 0;
wire [1:0] DOD_TO_STUB;
wire [1:0] DOC_TO_STUB;
wire [1:0] DOB_TO_STUB;
wire [1:0] DOA_TO_STUB;
function [31:0] every_other_bit_32;
input [63:0] in;
input odd;
integer i;
for (i = 0; i < 32; i = i + 1) begin
every_other_bit_32[i] = in[i * 2 + odd];
end
endfunction
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_A, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_a1 (
.DI(DIA[1]),
.A(ADDRA),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOA_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_A, 1'b0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_a0 (
.DI(DIA[0]),
.A(ADDRA),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOA_TO_STUB[0])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_B, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_b1 (
.DI(DIB[1]),
.A(ADDRB),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOB_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_B, 1'b0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_b0 (
.DI(DIB[0]),
.A(ADDRB),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOB_TO_STUB[0])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_C, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_c1 (
.DI(DIC[1]),
.A(ADDRC),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOC_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_C, 1'b0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_c0 (
.DI(DIC[0]),
.A(ADDRC),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOC_TO_STUB[0])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_D, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_d1 (
.DI(DID[1]),
.A(ADDRD),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOD_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_D, 0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_d0 (
.DI(DID[0]),
.A(ADDRD),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOD_TO_STUB[0])
);
DRAM_8_OUTPUT_STUB stub (
.DOD1(DOD_TO_STUB[1]), .DOD1_OUT(DOD[1]),
.DOC1(DOC_TO_STUB[1]), .DOC1_OUT(DOC[1]),
.DOB1(DOB_TO_STUB[1]), .DOB1_OUT(DOB[1]),
.DOA1(DOA_TO_STUB[1]), .DOA1_OUT(DOA[1]),
.DOD0(DOD_TO_STUB[0]), .DOD0_OUT(DOD[0]),
.DOC0(DOC_TO_STUB[0]), .DOC0_OUT(DOC[0]),
.DOB0(DOB_TO_STUB[0]), .DOB0_OUT(DOB[0]),
.DOA0(DOA_TO_STUB[0]), .DOA0_OUT(DOA[0])
);
endmodule
module RAM64M (
output DOA, DOB, DOC, DOD,
input DIA, DIB, DIC, DID,
input [5:0] ADDRA, ADDRB, ADDRC, ADDRD,
input WE, WCLK
);
parameter [63:0] INIT_A = 64'bx;
parameter [63:0] INIT_B = 64'bx;
parameter [63:0] INIT_C = 64'bx;
parameter [63:0] INIT_D = 64'bx;
parameter IS_WCLK_INVERTED = 0;
wire DOD_TO_STUB;
wire DOC_TO_STUB;
wire DOB_TO_STUB;
wire DOA_TO_STUB;
DPRAM64 #(
.INIT(INIT_D),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_d (
.DI(DID),
.A(ADDRD),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOD_TO_STUB)
);
DPRAM64 #(
.INIT(INIT_C),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_c (
.DI(DIC),
.A(ADDRC),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOC_TO_STUB)
);
DPRAM64 #(
.INIT(INIT_B),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_b (
.DI(DIB),
.A(ADDRB),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOB_TO_STUB)
);
DPRAM64 #(
.INIT(INIT_A),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_a (
.DI(DIA),
.A(ADDRA),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOA_TO_STUB)
);
DRAM_4_OUTPUT_STUB stub (
.DOD(DOD_TO_STUB), .DOD_OUT(DOD),
.DOC(DOC_TO_STUB), .DOC_OUT(DOC),
.DOB(DOB_TO_STUB), .DOB_OUT(DOB),
.DOA(DOA_TO_STUB), .DOA_OUT(DOA)
);
endmodule
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter [63:0] INIT = 64'bx;
parameter IS_WCLK_INVERTED = 0;
wire [5:0] WA = {A5, A4, A3, A2, A1, A0};
wire [5:0] DPRA = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
wire SPO_FORCE, DPO_FORCE;
DPRAM64 #(
.INIT(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram1 (
.DI(D),
.A(WA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(SPO_FORCE)
);
wire Dstub;
DI64_STUB stub1 (
.DI(D),
.DO(Dstub)
);
DPRAM64 #(
.INIT(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram0 (
.DI(Dstub),
.A(DPRA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(DPO_FORCE)
);
DRAM_2_OUTPUT_STUB stub (
.SPO(SPO_FORCE), .DPO(DPO_FORCE),
.SPO_OUT(SPO), .DPO_OUT(DPO));
endmodule
module RAM64X1S (
output O,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5
);
parameter [63:0] INIT = 64'bx;
parameter IS_WCLK_INVERTED = 0;
DPRAM64 #(
.INIT(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram0 (
.DI(D),
.A({A5, A4, A3, A2, A1, A0}),
.WA({A5, A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O)
);
endmodule
// ============================================================================
// Block RAMs
module RAMB18E1 (
input CLKARDCLK,
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input [13:0] ADDRARDADDR,
input [13:0] ADDRBWRADDR,
input [15:0] DIADI,
input [15:0] DIBDI,
input [1:0] DIPADIP,
input [1:0] DIPBDIP,
input [1:0] WEA,
input [3:0] WEBWE,
output [15:0] DOADO,
output [15:0] DOBDO,
output [1:0] DOPADOP,
output [1:0] DOPBDOP
);
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTMSK_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGB_ = 0;
parameter RAM_MODE = "TDP";
parameter SIM_DEVICE = "7SERIES";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
reg _TECHMAP_FAIL_;
reg GENERATE_ERROR;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
localparam INV_CLKARDCLK = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKARDCLK_ ^ IS_CLKARDCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? ~IS_CLKARDCLK_INVERTED : IS_CLKARDCLK_INVERTED;
wire clkardclk = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? 1'b1 : CLKARDCLK;
localparam INV_CLKBWRCLK = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKBWRCLK_ ^ IS_CLKBWRCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? ~IS_CLKBWRCLK_INVERTED : IS_CLKBWRCLK_INVERTED;
wire clkbwrclk = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? 1'b1 : CLKBWRCLK;
localparam INV_RSTRAMARSTRAM = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ ^ IS_RSTRAMARSTRAM_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? ~IS_RSTRAMARSTRAM_INVERTED : IS_RSTRAMARSTRAM_INVERTED;
wire rstramarstram = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? 1'b1 : RSTRAMARSTRAM;
localparam INV_RSTRAMB = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMB_ ^ IS_RSTRAMB_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? ~IS_RSTRAMB_INVERTED : IS_RSTRAMB_INVERTED;
wire rstramb = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? 1'b1 : RSTRAMB;
localparam INV_RSTREGARSTREG = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGARSTREG_ ^ IS_RSTREGARSTREG_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? ~IS_RSTREGARSTREG_INVERTED : IS_RSTREGARSTREG_INVERTED;
wire rstregarstreg = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? 1'b1 : RSTREGARSTREG;
localparam INV_RSTREGB = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGB_ ^ IS_RSTREGB_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? ~IS_RSTREGB_INVERTED : IS_RSTREGB_INVERTED;
wire rstregb = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? 1'b1 : RSTREGB;
initial begin
_TECHMAP_FAIL_ <= 0;
if(READ_WIDTH_A != 0
&& READ_WIDTH_A != 1
&& READ_WIDTH_A != 2
&& READ_WIDTH_A != 4
&& READ_WIDTH_A != 9
&& READ_WIDTH_A != 18
&& READ_WIDTH_A != 36)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(READ_WIDTH_B != 0
&& READ_WIDTH_B != 1
&& READ_WIDTH_B != 2
&& READ_WIDTH_B != 4
&& READ_WIDTH_B != 9
&& READ_WIDTH_B != 18)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_WIDTH_A != 0
&& WRITE_WIDTH_A != 1
&& WRITE_WIDTH_A != 2
&& WRITE_WIDTH_A != 4
&& WRITE_WIDTH_A != 9
&& WRITE_WIDTH_A != 18)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_WIDTH_B != 0
&& WRITE_WIDTH_B != 1
&& WRITE_WIDTH_B != 2
&& WRITE_WIDTH_B != 4
&& WRITE_WIDTH_B != 9
&& WRITE_WIDTH_B != 18
&& WRITE_WIDTH_B != 36)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(READ_WIDTH_A > 18 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_WIDTH_B > 18 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE" && WRITE_MODE_A != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE" && WRITE_MODE_B != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
localparam EFF_READ_WIDTH_A = (RAM_MODE == "SDP" && READ_WIDTH_A == 36) ? 18 : READ_WIDTH_A;
localparam EFF_READ_WIDTH_B = (RAM_MODE == "SDP" && READ_WIDTH_A == 36) ? 18 : READ_WIDTH_B;
localparam EFF_WRITE_WIDTH_A = (RAM_MODE == "SDP" && WRITE_WIDTH_B == 36) ? 18 : WRITE_WIDTH_A;
localparam EFF_WRITE_WIDTH_B = (RAM_MODE == "SDP" && WRITE_WIDTH_B == 36) ? 18 : WRITE_WIDTH_B;
wire REGCLKA;
wire REGCLKB;
wire [7:0] WEBWE_WIDE;
wire [3:0] WEA_WIDE;
if(WRITE_WIDTH_A < 18) begin
assign WEA_WIDE[3] = WEA[0];
assign WEA_WIDE[2] = WEA[0];
assign WEA_WIDE[1] = WEA[0];
assign WEA_WIDE[0] = WEA[0];
end else if(WRITE_WIDTH_A == 18) begin
assign WEA_WIDE[3] = WEA[1];
assign WEA_WIDE[2] = WEA[1];
assign WEA_WIDE[1] = WEA[0];
assign WEA_WIDE[0] = WEA[0];
end
if(WRITE_WIDTH_B < 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3] = WEBWE[0];
assign WEBWE_WIDE[2] = WEBWE[0];
assign WEBWE_WIDE[1] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
end else if(WRITE_WIDTH_B == 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3] = WEBWE[1];
assign WEBWE_WIDE[2] = WEBWE[1];
assign WEBWE_WIDE[1] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
end else begin
assign WEA_WIDE[3:0] = 4'b0;
assign WEBWE_WIDE[7] = WEBWE[3];
assign WEBWE_WIDE[6] = WEBWE[3];
assign WEBWE_WIDE[5] = WEBWE[2];
assign WEBWE_WIDE[4] = WEBWE[2];
assign WEBWE_WIDE[3] = WEBWE[1];
assign WEBWE_WIDE[2] = WEBWE[1];
assign WEBWE_WIDE[1] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
end
assign REGCLKA = DOA_REG ? CLKARDCLK : 1'b1;
localparam ZINV_REGCLKARDRCLK = (DOA_REG && !IS_CLKARDCLK_INVERTED);
assign REGCLKB = DOB_REG ? CLKBWRCLK : 1'b1;
localparam ZINV_REGCLKB = (DOB_REG && !IS_CLKBWRCLK_INVERTED);
RAMB18E1_VPR #(
.IN_USE(READ_WIDTH_A != 0 || READ_WIDTH_B != 0 || WRITE_WIDTH_A != 0 || WRITE_WIDTH_B != 0),
.ZINIT_A(INIT_A ^ {18{1'b1}}),
.ZINIT_B(INIT_B ^ {18{1'b1}}),
.ZSRVAL_A(SRVAL_A ^ {18{1'b1}}),
.ZSRVAL_B(SRVAL_B ^ {18{1'b1}}),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.ZINV_CLKARDCLK(!IS_CLKARDCLK_INVERTED ^ INV_CLKARDCLK),
.ZINV_CLKBWRCLK(!IS_CLKBWRCLK_INVERTED ^ INV_CLKBWRCLK),
.ZINV_ENARDEN(!IS_ENARDEN_INVERTED),
.ZINV_ENBWREN(!IS_ENBWREN_INVERTED),
.ZINV_RSTRAMARSTRAM(!IS_RSTRAMARSTRAM_INVERTED ^ INV_RSTRAMARSTRAM),
.ZINV_RSTRAMB(!IS_RSTRAMB_INVERTED ^ INV_RSTRAMB),
.ZINV_RSTREGARSTREG(!IS_RSTREGARSTREG_INVERTED ^ INV_RSTREGARSTREG),
.ZINV_RSTREGB(!IS_RSTREGB_INVERTED ^ INV_RSTREGB),
.ZINV_REGCLKARDRCLK(ZINV_REGCLKARDRCLK),
.ZINV_REGCLKB(ZINV_REGCLKB),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
// Assign special parameters relative to the RAMB site location.
// These is needed after the findings gathered with https://github.com/SymbiFlow/prjxray/pull/1263
// The rules to assign the correct READ_WIDTH_A parameter are the following:
// - Y0 RAMB18 and SDP mode: READ_WIDTH_A must be 1
// - Y1 RAMB18 and SDP mode: READ_WIDTH_A must be 18
// - No SDP: READ_WIDTH_A assumes the right value based on EFF_READ_WIDTH_A
.Y0_READ_WIDTH_A_1(READ_WIDTH_A == 36 || EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 0),
.Y1_READ_WIDTH_A_1(READ_WIDTH_A != 36 && (EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 0)),
.Y0_READ_WIDTH_A_18(READ_WIDTH_A != 36 && EFF_READ_WIDTH_A == 18),
.Y1_READ_WIDTH_A_18(READ_WIDTH_A == 36 || EFF_READ_WIDTH_A == 18),
.READ_WIDTH_A_1(EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 0),
.READ_WIDTH_A_2(EFF_READ_WIDTH_A == 2),
.READ_WIDTH_A_4(EFF_READ_WIDTH_A == 4),
.READ_WIDTH_A_9(EFF_READ_WIDTH_A == 9),
.READ_WIDTH_A_18(EFF_READ_WIDTH_A == 18),
.SDP_READ_WIDTH_36(READ_WIDTH_A == 36),
.READ_WIDTH_B_1(EFF_READ_WIDTH_B == 1 || EFF_READ_WIDTH_B == 0),
.READ_WIDTH_B_2(EFF_READ_WIDTH_B == 2),
.READ_WIDTH_B_4(EFF_READ_WIDTH_B == 4),
.READ_WIDTH_B_9(EFF_READ_WIDTH_B == 9),
.READ_WIDTH_B_18(EFF_READ_WIDTH_B == 18),
.WRITE_WIDTH_A_1(EFF_WRITE_WIDTH_A == 1 || EFF_WRITE_WIDTH_A == 0),
.WRITE_WIDTH_A_2(EFF_WRITE_WIDTH_A == 2),
.WRITE_WIDTH_A_4(EFF_WRITE_WIDTH_A == 4),
.WRITE_WIDTH_A_9(EFF_WRITE_WIDTH_A == 9),
.WRITE_WIDTH_A_18(EFF_WRITE_WIDTH_A == 18),
.WRITE_WIDTH_B_1(EFF_WRITE_WIDTH_B == 1 || EFF_WRITE_WIDTH_B == 0),
.WRITE_WIDTH_B_2(EFF_WRITE_WIDTH_B == 2),
.WRITE_WIDTH_B_4(EFF_WRITE_WIDTH_B == 4),
.WRITE_WIDTH_B_9(EFF_WRITE_WIDTH_B == 9),
.WRITE_WIDTH_B_18(EFF_WRITE_WIDTH_B == 18 || EFF_WRITE_WIDTH_B == 36),
.SDP_WRITE_WIDTH_36(WRITE_WIDTH_B == 36),
.WRITE_MODE_A_NO_CHANGE(WRITE_MODE_A == "NO_CHANGE" || (WRITE_MODE_A == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_A_READ_FIRST(WRITE_MODE_A == "READ_FIRST"),
.WRITE_MODE_B_NO_CHANGE(WRITE_MODE_B == "NO_CHANGE" || (WRITE_MODE_B == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_B_READ_FIRST(WRITE_MODE_B == "READ_FIRST")
) _TECHMAP_REPLACE_ (
.CLKARDCLK(clkardclk),
.REGCLKARDRCLK(REGCLKA),
.CLKBWRCLK(clkbwrclk),
.REGCLKB(REGCLKB),
.ENARDEN(ENARDEN),
.ENBWREN(ENBWREN),
.REGCEAREGCE(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMARSTRAM(rstramarstram),
.RSTRAMB(rstramb),
.RSTREGARSTREG(rstregarstreg),
.RSTREGB(rstregb),
.ADDRATIEHIGH(2'b11),
.ADDRARDADDR(ADDRARDADDR),
.ADDRBTIEHIGH(2'b11),
.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIBDI(DIBDI),
.DIPADIP(DIPADIP),
.DIPBDIP(DIPBDIP),
.WEA(WEA_WIDE),
.WEBWE(WEBWE_WIDE),
.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP)
);
endmodule
function [255:0] every_other_bit_256;
input [511:0] in;
input odd;
integer i;
for (i = 0; i < 256; i = i + 1) begin
every_other_bit_256[i] = in[i * 2 + odd];
end
endfunction
module RAMB36E1 (
input CLKARDCLK,
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input [14:0] ADDRARDADDR,
input [14:0] ADDRBWRADDR,
input [31:0] DIADI,
input [31:0] DIBDI,
input [3:0] DIPADIP,
input [3:0] DIPBDIP,
input [3:0] WEA,
input [7:0] WEBWE,
output [31:0] DOADO,
output [31:0] DOBDO,
output [3:0] DOPADOP,
output [3:0] DOPBDOP
);
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
`define INIT_BLOCK(pre) \
parameter ``pre``0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``A = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``B = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``C = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``D = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``E = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``F = 256'h0000000000000000000000000000000000000000000000000000000000000000
`INIT_BLOCK(INITP_0);
`INIT_BLOCK(INIT_0);
`INIT_BLOCK(INIT_1);
`INIT_BLOCK(INIT_2);
`INIT_BLOCK(INIT_3);
`INIT_BLOCK(INIT_4);
`INIT_BLOCK(INIT_5);
`INIT_BLOCK(INIT_6);
`INIT_BLOCK(INIT_7);
`undef INIT_BLOCK
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTMSK_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGB_ = 0;
parameter RAM_MODE = "TDP";
parameter SIM_DEVICE = "7SERIES";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
reg _TECHMAP_FAIL_;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
localparam INV_CLKARDCLK = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKARDCLK_ ^ IS_CLKARDCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? ~IS_CLKARDCLK_INVERTED : IS_CLKARDCLK_INVERTED;
wire clkardclk = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? 1'b1 : CLKARDCLK;
localparam INV_CLKBWRCLK = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKBWRCLK_ ^ IS_CLKBWRCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? ~IS_CLKBWRCLK_INVERTED : IS_CLKBWRCLK_INVERTED;
wire clkbwrclk = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? 1'b1 : CLKBWRCLK;
localparam INV_RSTRAMARSTRAM = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ ^ IS_RSTRAMARSTRAM_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? ~IS_RSTRAMARSTRAM_INVERTED : IS_RSTRAMARSTRAM_INVERTED;
wire rstramarstram = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? 1'b1 : RSTRAMARSTRAM;
localparam INV_RSTRAMB = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMB_ ^ IS_RSTRAMB_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? ~IS_RSTRAMB_INVERTED : IS_RSTRAMB_INVERTED;
wire rstramb = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? 1'b1 : RSTRAMB;
localparam INV_RSTREGARSTREG = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGARSTREG_ ^ IS_RSTREGARSTREG_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? ~IS_RSTREGARSTREG_INVERTED : IS_RSTREGARSTREG_INVERTED;
wire rstregarstreg = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? 1'b1 : RSTREGARSTREG;
localparam INV_RSTREGB = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGB_ ^ IS_RSTREGB_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? ~IS_RSTREGB_INVERTED : IS_RSTREGB_INVERTED;
wire rstregb = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? 1'b1 : RSTREGB;
initial begin
_TECHMAP_FAIL_ <= 0;
`define INVALID_WIDTH(x) \
((x) != 0 \
&& (x) != 1 \
&& (x) != 2 \
&& (x) != 4 \
&& (x) != 9 \
&& (x) != 18 \
&& (x) != 36)
`define INVALID_WIDTH_WIDE(x) \
(`INVALID_WIDTH(x) \
&& (x) != 72)
if(`INVALID_WIDTH_WIDE(READ_WIDTH_A))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(`INVALID_WIDTH(READ_WIDTH_B))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(`INVALID_WIDTH(WRITE_WIDTH_A))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(`INVALID_WIDTH_WIDE(WRITE_WIDTH_B))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
`undef INVALID_WIDTH
`undef INVALID_WIDTH_WIDE
if(READ_WIDTH_A > 36 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_WIDTH_B > 36 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE" && WRITE_MODE_A != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE" && WRITE_MODE_B != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
localparam EFF_READ_WIDTH_A = (RAM_MODE == "SDP" && READ_WIDTH_A > 36) ? 36 : READ_WIDTH_A;
localparam EFF_READ_WIDTH_B = (RAM_MODE == "SDP" && READ_WIDTH_A > 36) ? 36 : READ_WIDTH_B;
localparam EFF_WRITE_WIDTH_A = (RAM_MODE == "SDP" && WRITE_WIDTH_B > 36) ? 36 : WRITE_WIDTH_A;
localparam EFF_WRITE_WIDTH_B = (RAM_MODE == "SDP" && WRITE_WIDTH_B > 36) ? 36 : WRITE_WIDTH_B;
wire REGCLKA;
wire REGCLKB;
assign REGCLKA = DOA_REG ? CLKARDCLK : 1'b1;
localparam ZINV_REGCLKARDRCLK = (DOA_REG && !IS_CLKARDCLK_INVERTED);
assign REGCLKB = DOB_REG ? CLKBWRCLK : 1'b1;
localparam ZINV_REGCLKB = (DOB_REG && !IS_CLKBWRCLK_INVERTED);
wire [7:0] WEBWE_WIDE;
wire [3:0] WEA_WIDE;
wire [3:0] DIPADIP_MAPPED;
wire [3:0] DIPBDIP_MAPPED;
wire [31:0] DIADI_MAPPED;
wire [31:0] DIBDI_MAPPED;
if(WRITE_WIDTH_A == 1) begin
assign DIADI_MAPPED[31:2] = DIADI[31:2];
assign DIADI_MAPPED[1] = DIADI[0];
assign DIADI_MAPPED[0] = DIADI[0];
end else begin
assign DIADI_MAPPED = DIADI;
end
if(WRITE_WIDTH_B == 1) begin
assign DIBDI_MAPPED[31:2] = DIBDI[31:2];
assign DIBDI_MAPPED[1] = DIBDI[0];
assign DIBDI_MAPPED[0] = DIBDI[0];
end else begin
assign DIBDI_MAPPED = DIBDI;
end
if(WRITE_WIDTH_A < 18) begin
assign WEA_WIDE = {4{WEA[0]}};
assign DIPADIP_MAPPED[3:2] = DIPADIP[3:2];
assign DIPADIP_MAPPED[1] = DIPADIP[0];
assign DIPADIP_MAPPED[0] = DIPADIP[0];
end else if(WRITE_WIDTH_A == 18) begin
assign WEA_WIDE[3] = WEA[1];
assign WEA_WIDE[1] = WEA[1];
assign WEA_WIDE[2] = WEA[0];
assign WEA_WIDE[0] = WEA[0];
assign DIPADIP_MAPPED = DIPADIP;
end else if(WRITE_WIDTH_A == 36) begin
assign WEA_WIDE = WEA;
assign DIPADIP_MAPPED = DIPADIP;
end
if(WRITE_WIDTH_B < 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3:0] = {4{WEBWE[0]}};
assign DIPBDIP_MAPPED[3:2] = DIPBDIP[3:2];
assign DIPBDIP_MAPPED[1] = DIPBDIP[0];
assign DIPBDIP_MAPPED[0] = DIPBDIP[0];
end else if(WRITE_WIDTH_B == 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3] = WEBWE[1];
assign WEBWE_WIDE[1] = WEBWE[1];
assign WEBWE_WIDE[2] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
assign DIPBDIP_MAPPED = DIPBDIP;
end else if(WRITE_WIDTH_B == 36) begin
assign WEBWE_WIDE = WEBWE;
assign DIPBDIP_MAPPED = DIPBDIP;
end else if(WRITE_WIDTH_B == 72) begin
assign WEA_WIDE = 4'b0;
assign WEBWE_WIDE = WEBWE;
assign DIPBDIP_MAPPED = DIPBDIP;
end
RAMB36E1_PRIM #(
.IN_USE(READ_WIDTH_A != 0 || READ_WIDTH_B != 0 || WRITE_WIDTH_A != 0 || WRITE_WIDTH_B != 0),
.ZINIT_A(INIT_A ^ {36{1'b1}}),
.ZINIT_B(INIT_B ^ {36{1'b1}}),
.ZSRVAL_A(SRVAL_A ^ {36{1'b1}}),
.ZSRVAL_B(SRVAL_B ^ {36{1'b1}}),
`define INIT_PARAM_BLOCK_L(pre, n, d, upper) \
.``pre``_``n``0(every_other_bit_256({``pre``_``d``1, ``pre``_``d``0}, upper)), \
.``pre``_``n``1(every_other_bit_256({``pre``_``d``3, ``pre``_``d``2}, upper)), \
.``pre``_``n``2(every_other_bit_256({``pre``_``d``5, ``pre``_``d``4}, upper)), \
.``pre``_``n``3(every_other_bit_256({``pre``_``d``7, ``pre``_``d``6}, upper)), \
.``pre``_``n``4(every_other_bit_256({``pre``_``d``9, ``pre``_``d``8}, upper)), \
.``pre``_``n``5(every_other_bit_256({``pre``_``d``B, ``pre``_``d``A}, upper)), \
.``pre``_``n``6(every_other_bit_256({``pre``_``d``D, ``pre``_``d``C}, upper)), \
.``pre``_``n``7(every_other_bit_256({``pre``_``d``F, ``pre``_``d``E}, upper))
`define INIT_PARAM_BLOCK_H(pre, n, d, upper) \
.``pre``_``n``8(every_other_bit_256({``pre``_``d``1, ``pre``_``d``0}, upper)), \
.``pre``_``n``9(every_other_bit_256({``pre``_``d``3, ``pre``_``d``2}, upper)), \
.``pre``_``n``A(every_other_bit_256({``pre``_``d``5, ``pre``_``d``4}, upper)), \
.``pre``_``n``B(every_other_bit_256({``pre``_``d``7, ``pre``_``d``6}, upper)), \
.``pre``_``n``C(every_other_bit_256({``pre``_``d``9, ``pre``_``d``8}, upper)), \
.``pre``_``n``D(every_other_bit_256({``pre``_``d``B, ``pre``_``d``A}, upper)), \
.``pre``_``n``E(every_other_bit_256({``pre``_``d``D, ``pre``_``d``C}, upper)), \
.``pre``_``n``F(every_other_bit_256({``pre``_``d``F, ``pre``_``d``E}, upper))
`define INIT_PARAM_BLOCK(pre, n, lo, hi, upper) \
`INIT_PARAM_BLOCK_L(pre, n, lo, upper), \
`INIT_PARAM_BLOCK_H(pre, n, hi, upper)
`INIT_PARAM_BLOCK_L(INITP, 0, 0, 0),
`INIT_PARAM_BLOCK_H(INITP, 0, 0, 1),
`INIT_PARAM_BLOCK(INIT, 0, 0, 1, 0),
`INIT_PARAM_BLOCK(INIT, 1, 2, 3, 0),
`INIT_PARAM_BLOCK(INIT, 2, 4, 5, 0),
`INIT_PARAM_BLOCK(INIT, 3, 6, 7, 0),
`INIT_PARAM_BLOCK(INIT, 4, 0, 1, 1),
`INIT_PARAM_BLOCK(INIT, 5, 2, 3, 1),
`INIT_PARAM_BLOCK(INIT, 6, 4, 5, 1),
`INIT_PARAM_BLOCK(INIT, 7, 6, 7, 1),
`undef INIT_PARAM_BLOCK_L
`undef INIT_PARAM_BLOCK_H
`undef INIT_PARAM_BLOCK
.ZINV_CLKARDCLK(!IS_CLKARDCLK_INVERTED ^ INV_CLKARDCLK),
.ZINV_CLKBWRCLK(!IS_CLKBWRCLK_INVERTED ^ INV_CLKBWRCLK),
.ZINV_ENARDEN(!IS_ENARDEN_INVERTED),
.ZINV_ENBWREN(!IS_ENBWREN_INVERTED),
.ZINV_RSTRAMARSTRAM(!IS_RSTRAMARSTRAM_INVERTED ^ INV_RSTRAMARSTRAM),
.ZINV_RSTRAMB(!IS_RSTRAMB_INVERTED ^ INV_RSTRAMB),
.ZINV_RSTREGARSTREG(!IS_RSTREGARSTREG_INVERTED ^ INV_RSTREGARSTREG),
.ZINV_RSTREGB(!IS_RSTREGB_INVERTED ^ INV_RSTREGB),
.ZINV_REGCLKARDRCLK(ZINV_REGCLKARDRCLK),
.ZINV_REGCLKB(ZINV_REGCLKB),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
`define WIDTH_PARAM(name) \
.``name``_1(EFF_``name`` == 2 || EFF_``name`` == 1 || EFF_``name`` == 0), \
.``name``_2(EFF_``name`` == 4), \
.``name``_4(EFF_``name`` == 9), \
.``name``_9(EFF_``name`` == 18), \
.``name``_18(EFF_``name`` == 36)
`WIDTH_PARAM(READ_WIDTH_A),
.SDP_READ_WIDTH_36(READ_WIDTH_A > 36),
`WIDTH_PARAM(READ_WIDTH_B),
`WIDTH_PARAM(WRITE_WIDTH_A),
`WIDTH_PARAM(WRITE_WIDTH_B),
`undef WIDTH_PARAM
.BRAM36_READ_WIDTH_A_1(EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 9),
.BRAM36_READ_WIDTH_B_1(EFF_READ_WIDTH_B == 1 || EFF_READ_WIDTH_B == 9),
.BRAM36_WRITE_WIDTH_A_1(EFF_WRITE_WIDTH_A == 1 || EFF_WRITE_WIDTH_A == 9),
.BRAM36_WRITE_WIDTH_B_1(EFF_WRITE_WIDTH_B == 1 || EFF_WRITE_WIDTH_B == 9),
.SDP_WRITE_WIDTH_36(WRITE_WIDTH_B > 36),
.WRITE_MODE_A_NO_CHANGE(WRITE_MODE_A == "NO_CHANGE" || (WRITE_MODE_A == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_A_READ_FIRST(WRITE_MODE_A == "READ_FIRST"),
.WRITE_MODE_B_NO_CHANGE(WRITE_MODE_B == "NO_CHANGE" || (WRITE_MODE_B == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_B_READ_FIRST(WRITE_MODE_B == "READ_FIRST"),
.RSTREG_PRIORITY_A_RSTREG(1'b1),
.RSTREG_PRIORITY_B_RSTREG(1'b1),
.RAM_EXTENSION_A_NONE_OR_UPPER(1'b1),
.RAM_EXTENSION_B_NONE_OR_UPPER(1'b1),
.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE(1'b1),
.ZALMOST_EMPTY_OFFSET(13'b1111111111111),
.ZALMOST_FULL_OFFSET(13'b1111111111111)
) _TECHMAP_REPLACE_ (
`define DUP(pre, in) .``pre``U(in), .``pre``L(in)
`DUP(CLKARDCLK, clkardclk),
`DUP(REGCLKARDRCLK, REGCLKA),
`DUP(CLKBWRCLK, clkbwrclk),
`DUP(REGCLKB, REGCLKB),
`DUP(ENARDEN, ENARDEN),
`DUP(ENBWREN, ENBWREN),
`DUP(REGCEAREGCE, REGCEAREGCE),
`DUP(REGCEB, REGCEB),
.RSTRAMARSTRAMU(rstramarstram),
.RSTRAMARSTRAMLRST(rstramarstram),
`DUP(RSTRAMB, rstramb),
`DUP(RSTREGARSTREG, rstregarstreg),
`DUP(RSTREGB, rstregb),
.ADDRARDADDRU(ADDRARDADDR),
.ADDRARDADDRL({1'b1, ADDRARDADDR}),
.ADDRBWRADDRU(ADDRBWRADDR),
.ADDRBWRADDRL({1'b1, ADDRBWRADDR}),
.DIADI(DIADI_MAPPED),
.DIBDI(DIBDI_MAPPED),
.DIPADIP(DIPADIP_MAPPED),
.DIPBDIP(DIPBDIP_MAPPED),
`DUP(WEA, WEA_WIDE),
`DUP(WEBWE, WEBWE_WIDE),
.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP)
`undef DUP
);
endmodule // RAMB36E1
// ============================================================================
// SRLs
// The following three techmaps map SRLC32E, SRLC16E and SRL16E to their VPR
// counterparts.
//
// The initialization data for VPR SRLs need to have each bit duplicated and
// this is what these techmaps do. For now there is no support for CLK inversion
// as it is slice wide so the parameters is only there for compatibility.
//
// SRLC32E and SRLC16E are mapped directly to SRLC32E_VPR and SRLC16E_VPR
// respectively. Both of those primitives have Q31 (or Q15) outputs which
// correspond to the MC31 output of the physical bel. SRL16E does not
// provide that output hence it is mapped to SRLC16E with Q15 disconnected.
// It is then mapped to SRLC16E_VPR later on.
module SRLC32E (
output Q,
output Q31,
input [4:0] A,
input CE, CLK, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
// Duplicate bits of the init parameter to match the actual INIT data
// representation.
function [63:0] duplicate_bits;
input [31:0] bits;
integer i;
begin
for (i=0; i<32; i=i+1) begin
duplicate_bits[2*i+0] = bits[i];
duplicate_bits[2*i+1] = bits[i];
end
end
endfunction
localparam [63:0] INIT_VPR = duplicate_bits(INIT);
// Substitute
SRLC32E_VPR #
(
.INIT(INIT_VPR)
)
_TECHMAP_REPLACE_
(
.CLK(CLK),
.CE(CE),
.A(A),
.D(D),
.Q(Q),
.Q31(Q31)
);
endmodule
module SRLC16E (
output Q, Q15,
input A0, A1, A2, A3,
input CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [ 0:0] IS_CLK_INVERTED = 1'b0;
// Duplicate bits of the init parameter to match the actual INIT data
// representation.
function [31:0] duplicate_bits;
input [15:0] bits;
integer i;
begin
for (i=0; i<15; i=i+1) begin
duplicate_bits[2*i+0] = bits[i];
duplicate_bits[2*i+1] = bits[i];
end
end
endfunction
localparam [31:0] INIT_VPR = duplicate_bits(INIT);
// Substitute
SRLC16E_VPR #
(
.INIT(INIT_VPR)
)
_TECHMAP_REPLACE_
(
.CLK(CLK),
.CE(CE),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.D(D),
.Q(Q),
.Q15(Q15)
);
endmodule
module SRL16E (
output Q,
input A0, A1, A2, A3,
input CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [ 0:0] IS_CLK_INVERTED = 1'b0;
// Substitute with Q15 disconnected.
SRLC16E #
(
.INIT(INIT),
.IS_CLK_INVERTED(IS_CLK_INVERTED)
)
_TECHMAP_REPLACE_
(
.CLK(CLK),
.CE(CE),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.D(D),
.Q(Q),
.Q15()
);
endmodule
// ============================================================================
// IO
module IBUF (
input I,
output O
);
parameter IOSTANDARD = "LVCMOS33";
parameter IBUF_LOW_PWR = 0; // TODO: Map this to fasm
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
IBUF_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_IN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SLEW_FAST(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33_IN_ONLY(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS25_LVCMOS33_LVTTL_IN(
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL")
),
.SSTL135_SSTL15_IN(
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.O(O)
);
endmodule
module OBUF (
input I,
output O
);
parameter IOSTANDARD = "LVCMOS33";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
OBUFT # (
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.T(1'b0),
.O(O)
);
endmodule
module OBUFT (
input I,
input T,
output O
);
parameter IOSTANDARD = "LVCMOS33";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
parameter _TECHMAP_CONSTMSK_T_ = 1'bx;
parameter _TECHMAP_CONSTVAL_T_ = 1'bx;
wire t;
// When T=1'b0 Vivado routes it to const1 and enables an inverter in OLOGIC.
// To mimic this behavior insert a specialized inverter that will go to the
// OLOGIC site.
generate if (_TECHMAP_CONSTMSK_T_ == 1'b1 && _TECHMAP_CONSTVAL_T_ == 1'b0) begin
T_INV t_inv (
.TI (1'b1),
.TO (t)
);
end else begin
assign t = T;
end endgenerate
OBUFT_VPR # (
.LVCMOS12_DRIVE_I12(
(IOSTANDARD == "LVCMOS12" && DRIVE == 12)
),
.LVCMOS12_DRIVE_I4(
(IOSTANDARD == "LVCMOS12" && DRIVE == 4)
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SLEW_FAST(
(IOSTANDARD == "LVCMOS12" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "FAST") ||
(IOSTANDARD == "LVTTL" && SLEW == "FAST")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "LVCMOS12" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "SLOW") ||
(IOSTANDARD == "LVTTL" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS25_DRIVE_I8(
(IOSTANDARD == "LVCMOS12" && DRIVE == 8) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 8)
),
.LVCMOS15_DRIVE_I12(
(IOSTANDARD == "LVCMOS15" && DRIVE == 12)
),
.LVCMOS15_DRIVE_I8(
(IOSTANDARD == "LVCMOS15" && DRIVE == 8)
),
.LVCMOS15_LVCMOS18_LVCMOS25_DRIVE_I4(
(IOSTANDARD == "LVCMOS15" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 4)
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "LVCMOS15" && DRIVE == 16) ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS18_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS18" && DRIVE == 12) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 8)
),
.LVCMOS18_DRIVE_I16(
(IOSTANDARD == "LVCMOS18" && DRIVE == 16)
),
.LVCMOS18_DRIVE_I24(
(IOSTANDARD == "LVCMOS18" && DRIVE == 24)
),
.LVCMOS25_DRIVE_I12(
(IOSTANDARD == "LVCMOS25" && DRIVE == 12)
),
.LVCMOS25_DRIVE_I16(
(IOSTANDARD == "LVCMOS25" && DRIVE == 16)
),
.LVCMOS33_DRIVE_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS33" && DRIVE == 8) ||
(IOSTANDARD == "LVTTL" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 8)
),
.LVCMOS33_LVTTL_DRIVE_I4(
(IOSTANDARD == "LVCMOS33" && DRIVE == 4) ||
(IOSTANDARD == "LVTTL" && DRIVE == 4)
),
.LVTTL_DRIVE_I24(
(IOSTANDARD == "LVTTL" && DRIVE == 24)
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "SSTL135")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "SSTL15" && SLEW == "FAST")
),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) obuft (
.I(I),
.T(t),
.O(O)
);
endmodule
module IOBUF (
input I,
input T,
output O,
inout IO
);
parameter IOSTANDARD = "LVCMOS33";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter IBUF_LOW_PWR = 0; // TODO: Map this to fasm
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
IOBUF_VPR # (
.LVCMOS12_DRIVE_I12(
(IOSTANDARD == "LVCMOS12" && DRIVE == 12)
),
.LVCMOS12_DRIVE_I4(
(IOSTANDARD == "LVCMOS12" && DRIVE == 4)
),
.LVCMOS12_LVCMOS15_LVCMOS18_IN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SLEW_FAST(
(IOSTANDARD == "LVCMOS12" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "FAST") ||
(IOSTANDARD == "LVTTL" && SLEW == "FAST")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "LVCMOS12" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "SLOW") ||
(IOSTANDARD == "LVTTL" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS25_DRIVE_I8(
(IOSTANDARD == "LVCMOS12" && DRIVE == 8) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 8)
),
.LVCMOS15_DRIVE_I12(
(IOSTANDARD == "LVCMOS15" && DRIVE == 12)
),
.LVCMOS15_DRIVE_I8(
(IOSTANDARD == "LVCMOS15" && DRIVE == 8)
),
.LVCMOS15_LVCMOS18_LVCMOS25_DRIVE_I4(
(IOSTANDARD == "LVCMOS15" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 4)
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "LVCMOS15" && DRIVE == 16) ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS18_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS18" && DRIVE == 12) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 8)
),
.LVCMOS18_DRIVE_I16(
(IOSTANDARD == "LVCMOS18" && DRIVE == 16)
),
.LVCMOS18_DRIVE_I24(
(IOSTANDARD == "LVCMOS18" && DRIVE == 24)
),
.LVCMOS25_DRIVE_I12(
(IOSTANDARD == "LVCMOS25" && DRIVE == 12)
),
.LVCMOS25_DRIVE_I16(
(IOSTANDARD == "LVCMOS25" && DRIVE == 16)
),
.LVCMOS25_LVCMOS33_LVTTL_IN(
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL")
),
.LVCMOS33_DRIVE_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS33" && DRIVE == 8) ||
(IOSTANDARD == "LVTTL" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 8)
),
.LVCMOS33_LVTTL_DRIVE_I4(
(IOSTANDARD == "LVCMOS33" && DRIVE == 4) ||
(IOSTANDARD == "LVTTL" && DRIVE == 4)
),
.LVTTL_DRIVE_I24(
(IOSTANDARD == "LVTTL" && DRIVE == 24)
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "SSTL135")
),
.SSTL135_SSTL15_IN(
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "SSTL15" && SLEW == "FAST")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.T(T),
.O(O),
.IOPAD_$inp(IO),
.IOPAD_$out(IO)
);
endmodule
module OBUFTDS (
input I,
input T,
output O,
output OB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "FAST";
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
parameter HAS_OSERDES = 0; // Set inside yosys/synth.tcl
parameter _TECHMAP_CONSTMSK_T_ = 1'bx;
parameter _TECHMAP_CONSTVAL_T_ = 1'bx;
wire t;
// When T=1'b0 Vivado routes it to const1 and enables an inverter in OLOGIC.
// BUT, that happens only when there is an OSERDES with "TQ.BUF" mode.
//
// Presence of an OSERDES is detected in the sytnesis script and the parameter
// HAS_OSERDES is set.
generate if (_TECHMAP_CONSTMSK_T_ == 1'b1 && _TECHMAP_CONSTVAL_T_ == 1'b0 && HAS_OSERDES == 1) begin
T_INV t_inv (
.TI (1'b1),
.TO (t)
);
end else begin
assign t = T;
end endgenerate
wire complementary;
OBUFTDS_M_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.LVDS_25_DRIVE_I_FIXED(
(IOSTANDARD == "LVDS_25")
),
.LVDS_25_OUT(
(IOSTANDARD == "LVDS_25")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.TMDS_33_DRIVE_I_FIXED(
(IOSTANDARD == "TMDS_33")
),
.TMDS_33_OUT(
(IOSTANDARD == "TMDS_33")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) obuftds_m (
.I(I),
.T(t),
.O(O),
.OB(complementary)
);
OBUFTDS_S_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) obuftds_s (
.IB(complementary),
.OB(OB)
);
endmodule
module OBUFDS (
input I,
output O,
output OB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "FAST";
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
parameter HAS_OSERDES = 0; // Set inside yosys/synth.tcl
OBUFTDS # (
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.HAS_OSERDES(HAS_OSERDES),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.T(1'b0),
.O(O),
.OB(OB)
);
endmodule
module IOBUFDS (
input I,
input T,
output O,
inout IO,
inout IOB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "SLOW";
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
wire complementary_o;
wire complementary_i;
IOBUFDS_M_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.LVDS_25_DRIVE_I_FIXED(
(IOSTANDARD == "LVDS_25")
),
.LVDS_25_OUT(
(IOSTANDARD == "LVDS_25")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.LVDS_25_SSTL135_SSTL15_IN_DIFF(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15") ||
(IOSTANDARD == "LVDS_25")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.TMDS_33_IN_DIFF(
(IOSTANDARD == "TMDS_33")
),
.TMDS_33_DRIVE_I_FIXED(
(IOSTANDARD == "TMDS_33")
),
.TMDS_33_OUT(
(IOSTANDARD == "TMDS_33")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) iobufds_m (
.I(I),
.T(T),
.O(O),
.IOPAD_$inp(IO),
.IOPAD_$out(IO),
.IB(complementary_i),
.OB(complementary_o)
);
IOBUFDS_S_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.LVDS_25_SSTL135_SSTL15_IN_DIFF(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15") ||
(IOSTANDARD == "LVDS_25")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) iobufds_s (
.IB(complementary_o),
.OB(complementary_i),
.IOPAD_$inp(IOB),
.IOPAD_$out(IOB)
);
endmodule
// ============================================================================
// I/OSERDES
module OSERDESE2 (
input CLK,
input CLKDIV,
input D1,
input D2,
input D3,
input D4,
input D5,
input D6,
input D7,
input D8,
input OCE,
input RST,
input T1,
input T2,
input T3,
input T4,
input TCE,
output OFB,
output OQ,
output TFB,
output TQ
);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter DATA_WIDTH = 4;
parameter SERDES_MODE = "MASTER";
parameter TRISTATE_WIDTH = 4;
parameter IO_LOC_PAIRS = "NONE";
if (DATA_RATE_OQ == "DDR" &&
!(DATA_WIDTH == 4 || DATA_WIDTH == 6 || DATA_WIDTH == 8)) begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE_OQ == "SDR" &&
!(DATA_WIDTH >= 2 || DATA_WIDTH <= 8)) begin
wire _TECHMAP_FAIL_;
end
if ((DATA_RATE_TQ == "SDR" || DATA_RATE_TQ == "BUF") &&
TRISTATE_WIDTH != 1) begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE_OQ == "SDR" && DATA_RATE_TQ == "DDR") begin
wire _TECHMAP_FAIL_;
end
if (TRISTATE_WIDTH != 1 && TRISTATE_WIDTH != 4) begin
wire _TECHMAP_FAIL_;
end
// Inverter parameters
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter [0:0] IS_D3_INVERTED = 1'b0;
parameter [0:0] IS_D4_INVERTED = 1'b0;
parameter [0:0] IS_D5_INVERTED = 1'b0;
parameter [0:0] IS_D6_INVERTED = 1'b0;
parameter [0:0] IS_D7_INVERTED = 1'b0;
parameter [0:0] IS_D8_INVERTED = 1'b0;
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [0:0] IS_T1_INVERTED = 1'b0;
parameter [0:0] IS_T2_INVERTED = 1'b0;
parameter [0:0] IS_T3_INVERTED = 1'b0;
parameter [0:0] IS_T4_INVERTED = 1'b0;
localparam [0:0] INIT_OQ = 1'b0;
localparam [0:0] INIT_TQ = 1'b0;
localparam [0:0] SRVAL_OQ = 1'b0;
localparam [0:0] SRVAL_TQ = 1'b0;
parameter _TECHMAP_CONSTMSK_D1_ = 0;
parameter _TECHMAP_CONSTVAL_D1_ = 0;
parameter _TECHMAP_CONSTMSK_D2_ = 0;
parameter _TECHMAP_CONSTVAL_D2_ = 0;
parameter _TECHMAP_CONSTMSK_D3_ = 0;
parameter _TECHMAP_CONSTVAL_D3_ = 0;
parameter _TECHMAP_CONSTMSK_D4_ = 0;
parameter _TECHMAP_CONSTVAL_D4_ = 0;
parameter _TECHMAP_CONSTMSK_D5_ = 0;
parameter _TECHMAP_CONSTVAL_D5_ = 0;
parameter _TECHMAP_CONSTMSK_D6_ = 0;
parameter _TECHMAP_CONSTVAL_D6_ = 0;
parameter _TECHMAP_CONSTMSK_D7_ = 0;
parameter _TECHMAP_CONSTVAL_D7_ = 0;
parameter _TECHMAP_CONSTMSK_D8_ = 0;
parameter _TECHMAP_CONSTVAL_D8_ = 0;
parameter _TECHMAP_CONSTMSK_TQ_ = 1'bx;
parameter _TECHMAP_CONSTVAL_TQ_ = 1'bx;
localparam INV_D1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? !_TECHMAP_CONSTVAL_D1_ ^ IS_D1_INVERTED :
(_TECHMAP_CONSTVAL_D1_ === 0) ? ~IS_D1_INVERTED : IS_D1_INVERTED;
wire d1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D1_ === 0) ? 1'b1 : D1;
localparam INV_D2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? !_TECHMAP_CONSTVAL_D2_ ^ IS_D2_INVERTED :
(_TECHMAP_CONSTVAL_D2_ === 0) ? ~IS_D2_INVERTED : IS_D2_INVERTED;
wire d2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D2_ === 0) ? 1'b1 : D2;
localparam INV_D3 = (_TECHMAP_CONSTMSK_D3_ == 1) ? !_TECHMAP_CONSTVAL_D3_ ^ IS_D3_INVERTED :
(_TECHMAP_CONSTVAL_D3_ === 0) ? ~IS_D3_INVERTED : IS_D3_INVERTED;
wire d3 = (_TECHMAP_CONSTMSK_D3_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D3_ === 0) ? 1'b1 : D3;
localparam INV_D4 = (_TECHMAP_CONSTMSK_D4_ == 1) ? !_TECHMAP_CONSTVAL_D4_ ^ IS_D4_INVERTED :
(_TECHMAP_CONSTVAL_D4_ === 0) ? ~IS_D4_INVERTED : IS_D4_INVERTED;
wire d4 = (_TECHMAP_CONSTMSK_D4_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D4_ === 0) ? 1'b1 : D4;
localparam INV_D5 = (_TECHMAP_CONSTMSK_D5_ == 1) ? !_TECHMAP_CONSTVAL_D5_ ^ IS_D5_INVERTED :
(_TECHMAP_CONSTVAL_D5_ === 0) ? ~IS_D5_INVERTED : IS_D5_INVERTED;
wire d5 = (_TECHMAP_CONSTMSK_D5_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D5_ === 0) ? 1'b1 : D5;
localparam INV_D6 = (_TECHMAP_CONSTMSK_D6_ == 1) ? !_TECHMAP_CONSTVAL_D6_ ^ IS_D6_INVERTED :
(_TECHMAP_CONSTVAL_D6_ === 0) ? ~IS_D6_INVERTED : IS_D6_INVERTED;
wire d6 = (_TECHMAP_CONSTMSK_D6_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D6_ === 0) ? 1'b1 : D6;
localparam INV_D7 = (_TECHMAP_CONSTMSK_D7_ == 1) ? !_TECHMAP_CONSTVAL_D7_ ^ IS_D7_INVERTED :
(_TECHMAP_CONSTVAL_D7_ === 0) ? ~IS_D7_INVERTED : IS_D7_INVERTED;
wire d7 = (_TECHMAP_CONSTMSK_D7_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D7_ === 0) ? 1'b1 : D7;
localparam INV_D8 = (_TECHMAP_CONSTMSK_D8_ == 1) ? !_TECHMAP_CONSTVAL_D8_ ^ IS_D8_INVERTED :
(_TECHMAP_CONSTVAL_D8_ === 0) ? ~IS_D8_INVERTED : IS_D8_INVERTED;
wire d8 = (_TECHMAP_CONSTMSK_D8_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D8_ === 0) ? 1'b1 : D8;
localparam TQ_USED = (_TECHMAP_CONSTVAL_TQ_ === 1'bx && (DATA_RATE_TQ == "DDR" || DATA_RATE_TQ == "SDR")) ? 1'b1 : 1'b0;
parameter _TECHMAP_CONSTMSK_T1_ = 0;
parameter _TECHMAP_CONSTVAL_T1_ = 0;
parameter _TECHMAP_CONSTMSK_T2_ = 0;
parameter _TECHMAP_CONSTVAL_T2_ = 0;
parameter _TECHMAP_CONSTMSK_T3_ = 0;
parameter _TECHMAP_CONSTVAL_T3_ = 0;
parameter _TECHMAP_CONSTMSK_T4_ = 0;
parameter _TECHMAP_CONSTVAL_T4_ = 0;
localparam INV_T1 = (_TECHMAP_CONSTMSK_T1_ == 1) ? !_TECHMAP_CONSTVAL_T1_ ^ IS_T1_INVERTED :
(_TECHMAP_CONSTVAL_T1_ === 0) ? ~IS_T1_INVERTED : IS_T1_INVERTED;
wire t1 = (_TECHMAP_CONSTMSK_T1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T1_ === 0) ? 1'b1 : T1;
localparam INV_T2 = (_TECHMAP_CONSTMSK_T2_ == 1) ? !_TECHMAP_CONSTVAL_T2_ ^ IS_T2_INVERTED :
(_TECHMAP_CONSTVAL_T2_ === 0) ? ~IS_T2_INVERTED : IS_T2_INVERTED;
wire t2 = (_TECHMAP_CONSTMSK_T2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T2_ === 0) ? 1'b1 : T2;
localparam INV_T3 = (_TECHMAP_CONSTMSK_T3_ == 1) ? !_TECHMAP_CONSTVAL_T3_ ^ IS_T3_INVERTED :
(_TECHMAP_CONSTVAL_T3_ === 0) ? ~IS_T3_INVERTED : IS_T3_INVERTED;
wire t3 = (_TECHMAP_CONSTMSK_T3_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T3_ === 0) ? 1'b1 : T3;
localparam INV_T4 = (_TECHMAP_CONSTMSK_T4_ == 1) ? !_TECHMAP_CONSTVAL_T4_ ^ IS_T4_INVERTED :
(_TECHMAP_CONSTVAL_T4_ === 0) ? ~IS_T4_INVERTED : IS_T4_INVERTED;
wire t4 = (_TECHMAP_CONSTMSK_T4_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T4_ === 0) ? 1'b1 : T4;
OSERDESE2_VPR #(
.SERDES_MODE_SLAVE (SERDES_MODE == "SLAVE"),
.TRISTATE_WIDTH_W4 (TRISTATE_WIDTH == 4),
.DATA_RATE_OQ_DDR (DATA_RATE_OQ == "DDR"),
.DATA_RATE_OQ_SDR (DATA_RATE_OQ == "SDR"),
.DATA_RATE_TQ_BUF (DATA_RATE_TQ == "BUF"),
.DATA_RATE_TQ_DDR (DATA_RATE_TQ == "DDR"),
.DATA_RATE_TQ_SDR (DATA_RATE_TQ == "SDR"),
.DATA_WIDTH_DDR_W4 (DATA_RATE_OQ == "DDR" && DATA_WIDTH == 4),
.DATA_WIDTH_DDR_W6 (DATA_RATE_OQ == "DDR" && DATA_WIDTH == 6),
.DATA_WIDTH_DDR_W8 (DATA_RATE_OQ == "DDR" && DATA_WIDTH == 8),
.DATA_WIDTH_SDR_W2 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 2),
.DATA_WIDTH_SDR_W3 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 3),
.DATA_WIDTH_SDR_W4 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 4),
.DATA_WIDTH_SDR_W5 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 5),
.DATA_WIDTH_SDR_W6 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 6),
.DATA_WIDTH_SDR_W7 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 7),
.DATA_WIDTH_SDR_W8 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 8),
.ZINIT_OQ (!INIT_OQ),
.ZINIT_TQ (!INIT_TQ),
.ZSRVAL_OQ (!SRVAL_OQ),
.ZSRVAL_TQ (!SRVAL_TQ),
.IS_CLKDIV_INVERTED (IS_CLKDIV_INVERTED),
.IS_D1_INVERTED (INV_D1),
.IS_D2_INVERTED (INV_D2),
.IS_D3_INVERTED (INV_D3),
.IS_D4_INVERTED (INV_D4),
.IS_D5_INVERTED (INV_D5),
.IS_D6_INVERTED (INV_D6),
.IS_D7_INVERTED (INV_D7),
.IS_D8_INVERTED (INV_D8),
.ZINV_CLK (!IS_CLK_INVERTED),
.ZINV_T1 (!INV_T1),
.ZINV_T2 (!INV_T2),
.ZINV_T3 (!INV_T3),
.ZINV_T4 (!INV_T4),
.TQ_USED (TQ_USED)
) _TECHMAP_REPLACE_ (
.CLK (CLK),
.CLKDIV (CLKDIV),
.D1 (d1),
.D2 (d2),
.D3 (d3),
.D4 (d4),
.D5 (d5),
.D6 (d6),
.D7 (d7),
.D8 (d8),
.OCE (OCE),
.RST (RST),
.T1 (t1),
.T2 (t2),
.T3 (t3),
.T4 (t4),
.TCE (TCE),
.OFB (OFB),
.OQ (OQ),
.TFB (TFB),
.TQ (TQ)
);
endmodule
module ISERDESE2 (
input BITSLIP,
input CE1,
input CE2,
input CLK,
input CLKB,
input CLKDIV,
input RST,
input D,
input DDLY,
output Q1,
output Q2,
output Q3,
output Q4,
output Q5,
output Q6,
output Q7,
output Q8
);
parameter DATA_RATE = "DDR";
parameter DATA_WIDTH = 4;
parameter NUM_CE = 2;
parameter DYN_CLKDIV_INV_EN = "FALSE";
parameter DYN_CLK_INV_EN = "FALSE";
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter SERDES_MODE = "MASTER";
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
if (INTERFACE_TYPE == "NETWORKING") begin
if (DATA_RATE == "DDR" &&
(DATA_WIDTH != 4 &&
DATA_WIDTH != 6 &&
DATA_WIDTH != 8)) begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE == "SDR" &&
(DATA_WIDTH < 2 ||
DATA_WIDTH > 8)) begin
wire _TECHMAP_FAIL_;
end
end
if (INTERFACE_TYPE == "MEMORY" ||
INTERFACE_TYPE == "MEMORY_DDR3" ||
INTERFACE_TYPE == "MEMORY_QDR") begin
if (DATA_RATE == "SDR") begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE == "DDR" &&
(DATA_WIDTH != 4 &&
DATA_WIDTH != 6 &&
DATA_WIDTH != 8)) begin
wire _TECHMAP_FAIL_;
end
end
if (NUM_CE != 1 && NUM_CE != 2) begin
wire _TECHMAP_FAIL_ = 1'b1;
end
parameter _TECHMAP_CONSTMSK_D_ = 1'b1;
parameter _TECHMAP_CONSTVAL_D_ = 1'bx;
parameter _TECHMAP_CONSTMSK_DDLY_ = 1'b1;
parameter _TECHMAP_CONSTVAL_DDLY_ = 1'bx;
localparam [0:0] MEMORY_DDR3_4 = (INTERFACE_TYPE == "MEMORY_DDR3" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] MEMORY_DDR_4 = (INTERFACE_TYPE == "MEMORY" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] MEMORY_QDR_4 = (INTERFACE_TYPE == "MEMORY_QDR" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] NETWORKING_SDR_2 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 2);
localparam [0:0] NETWORKING_SDR_3 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 3);
localparam [0:0] NETWORKING_SDR_4 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 4);
localparam [0:0] NETWORKING_SDR_5 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 5);
localparam [0:0] NETWORKING_SDR_6 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 6);
localparam [0:0] NETWORKING_SDR_7 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 7);
localparam [0:0] NETWORKING_SDR_8 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 8);
localparam [0:0] NETWORKING_DDR_4 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] NETWORKING_DDR_6 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 6);
localparam [0:0] NETWORKING_DDR_8 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 8);
localparam [0:0] NETWORKING_DDR_10 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 10);
localparam [0:0] NETWORKING_DDR_14 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 14);
localparam [0:0] OVERSAMPLE_DDR_4 = (INTERFACE_TYPE == "OVERSAMPLE" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
if (_TECHMAP_CONSTMSK_D_ == 1'b1) begin
ISERDESE2_IDELAY_VPR #(
.MEMORY_DDR3_4 (MEMORY_DDR3_4),
.MEMORY_DDR_4 (MEMORY_DDR_4),
.MEMORY_QDR_4 (MEMORY_QDR_4),
.NETWORKING_SDR_2 (NETWORKING_SDR_2),
.NETWORKING_SDR_3 (NETWORKING_SDR_3),
.NETWORKING_SDR_4 (NETWORKING_SDR_4),
.NETWORKING_SDR_5 (NETWORKING_SDR_5),
.NETWORKING_SDR_6 (NETWORKING_SDR_6),
.NETWORKING_SDR_7 (NETWORKING_SDR_7),
.NETWORKING_SDR_8 (NETWORKING_SDR_8),
.NETWORKING_DDR_4 (NETWORKING_DDR_4),
.NETWORKING_DDR_6 (NETWORKING_DDR_6),
.NETWORKING_DDR_8 (NETWORKING_DDR_8),
.NETWORKING_DDR_10 (NETWORKING_DDR_10),
.NETWORKING_DDR_14 (NETWORKING_DDR_14),
.OVERSAMPLE_DDR_4 (OVERSAMPLE_DDR_4),
.NUM_CE_N1 (NUM_CE == 1),
.NUM_CE_N2 (NUM_CE == 2),
.IOBDELAY_IFD (IOBDELAY == "IFD" || IOBDELAY == "BOTH"),
.IOBDELAY_IBUF (IOBDELAY == "IBUF" || IOBDELAY == "BOTH"),
// Inverters
.ZINIT_Q1 (!INIT_Q1),
.ZINIT_Q2 (!INIT_Q2),
.ZINIT_Q3 (!INIT_Q3),
.ZINIT_Q4 (!INIT_Q4),
.ZSRVAL_Q1 (!SRVAL_Q1),
.ZSRVAL_Q2 (!SRVAL_Q2),
.ZSRVAL_Q3 (!SRVAL_Q3),
.ZSRVAL_Q4 (!SRVAL_Q4),
.ZINV_C (!IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.BITSLIP (BITSLIP),
.CE1 (CE1),
.CE2 (CE2),
.CLK (CLK),
.CLKB (CLKB),
.CLKDIV (CLKDIV),
.RST (RST),
.DDLY (DDLY),
.Q1 (Q1),
.Q2 (Q2),
.Q3 (Q3),
.Q4 (Q4),
.Q5 (Q5),
.Q6 (Q6),
.Q7 (Q7),
.Q8 (Q8)
);
end else if (_TECHMAP_CONSTMSK_DDLY_ == 1'b1) begin
ISERDESE2_NO_IDELAY_VPR #(
.MEMORY_DDR3_4 (MEMORY_DDR3_4),
.MEMORY_DDR_4 (MEMORY_DDR_4),
.MEMORY_QDR_4 (MEMORY_QDR_4),
.NETWORKING_SDR_2 (NETWORKING_SDR_2),
.NETWORKING_SDR_3 (NETWORKING_SDR_3),
.NETWORKING_SDR_4 (NETWORKING_SDR_4),
.NETWORKING_SDR_5 (NETWORKING_SDR_5),
.NETWORKING_SDR_6 (NETWORKING_SDR_6),
.NETWORKING_SDR_7 (NETWORKING_SDR_7),
.NETWORKING_SDR_8 (NETWORKING_SDR_8),
.NETWORKING_DDR_4 (NETWORKING_DDR_4),
.NETWORKING_DDR_6 (NETWORKING_DDR_6),
.NETWORKING_DDR_8 (NETWORKING_DDR_8),
.NETWORKING_DDR_10 (NETWORKING_DDR_10),
.NETWORKING_DDR_14 (NETWORKING_DDR_14),
.OVERSAMPLE_DDR_4 (OVERSAMPLE_DDR_4),
.NUM_CE_N1 (NUM_CE == 1),
.NUM_CE_N2 (NUM_CE == 2),
.IOBDELAY_IFD (IOBDELAY == "IFD" || IOBDELAY == "BOTH"),
.IOBDELAY_IBUF (IOBDELAY == "IBUF" || IOBDELAY == "BOTH"),
// Inverters
.ZINIT_Q1 (!INIT_Q1),
.ZINIT_Q2 (!INIT_Q2),
.ZINIT_Q3 (!INIT_Q3),
.ZINIT_Q4 (!INIT_Q4),
.ZSRVAL_Q1 (!SRVAL_Q1),
.ZSRVAL_Q2 (!SRVAL_Q2),
.ZSRVAL_Q3 (!SRVAL_Q3),
.ZSRVAL_Q4 (!SRVAL_Q4),
.ZINV_D (!IS_D_INVERTED),
.ZINV_C (!IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.BITSLIP (BITSLIP),
.CE1 (CE1),
.CE2 (CE2),
.CLK (CLK),
.CLKB (CLKB),
.CLKDIV (CLKDIV),
.RST (RST),
.D (D),
.Q1 (Q1),
.Q2 (Q2),
.Q3 (Q3),
.Q4 (Q4),
.Q5 (Q5),
.Q6 (Q6),
.Q7 (Q7),
.Q8 (Q8)
);
end else begin
wire _TECHMAP_FAIL_;
end
endmodule
// ============================================================================
// IDDR/ODDR
module IDDR_2CLK (
output Q1,
output Q2,
input C,
input CB,
input CE,
input D,
input R,
input S,
);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_CB_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
parameter _TECHMAP_CONSTMSK_R_ = 1'b1;
parameter _TECHMAP_CONSTVAL_R_ = 1'bx;
parameter _TECHMAP_CONSTMSK_S_ = 1'b1;
parameter _TECHMAP_CONSTVAL_S_ = 1'bx;
localparam [0:0] R_USED = (_TECHMAP_CONSTMSK_R_ != 1'b1);
localparam [0:0] S_USED = (_TECHMAP_CONSTMSK_S_ != 1'b1);
wire SR;
localparam SRVAL = (!R_USED) ? 1'b1 : 1'b0;
localparam SRUSED = 1'b1;
generate if (!R_USED && !S_USED) begin
assign SR = 1'b0;
end else if (R_USED && !S_USED) begin
assign SR = R;
end else if (!R_USED && S_USED) begin
assign SR = S;
end else begin
assign SR = 1'bx;
$error("Both S and R cannot be used simultaneously");
end endgenerate
localparam INIT_Q3 = (DDR_CLK_EDGE != "OPPOSITE_EDGE") ? INIT_Q1 : 1'b1;
localparam INIT_Q4 = (DDR_CLK_EDGE != "OPPOSITE_EDGE") ? INIT_Q2 : 1'b1;
localparam SRVAL34 = (DDR_CLK_EDGE != "OPPOSITE_EDGE") ? SRVAL : 1'b1;
IDDR_VPR #(
.ZINV_D (!IS_D_INVERTED),
.ZINV_C (!IS_C_INVERTED),
.SRTYPE_SYNC (SRTYPE == "SYNC"),
.SAME_EDGE (DDR_CLK_EDGE == "SAME_EDGE"),
.OPPOSITE_EDGE (DDR_CLK_EDGE == "OPPOSITE_EDGE"),
.ZINIT_Q1 (!INIT_Q1),
.ZINIT_Q2 (!INIT_Q2),
.ZINIT_Q3 (!INIT_Q3),
.ZINIT_Q4 (!INIT_Q4),
.ZSRVAL_Q12 (!SRVAL),
.ZSRVAL_Q34 (!SRVAL34)
) _TECHMAP_REPLACE_ (
.CK (C),
.CKB (CB),
.CE (CE),
.SR (SR),
.D (D),
.Q1 (Q1),
.Q2 (Q2)
);
endmodule
module IDDR (
output Q1,
output Q2,
input C,
input CE,
input D,
input R,
input S,
);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
IDDR_2CLK # (
.DDR_CLK_EDGE (DDR_CLK_EDGE),
.SRTYPE (SRTYPE),
.INIT_Q1 (INIT_Q1),
.INIT_Q2 (INIT_Q2),
.IS_C_INVERTED (IS_C_INVERTED),
.IS_CB_INVERTED (!IS_C_INVERTED),
.IS_D_INVERTED (IS_D_INVERTED)
) _TECHMAP_REPLACE_ (
.C (C),
.CB (C),
.CE (CE),
.S (S),
.R (R),
.D (D),
.Q1 (Q1),
.Q2 (Q2)
);
endmodule
module ODDR (
input C,
input CE,
input R,
input S,
input D1,
input D2,
output Q
);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
parameter _TECHMAP_CONSTMSK_R_ = 1'b1;
parameter _TECHMAP_CONSTVAL_R_ = 1'bx;
parameter _TECHMAP_CONSTMSK_S_ = 1'b1;
parameter _TECHMAP_CONSTVAL_S_ = 1'bx;
localparam [0:0] R_USED = (_TECHMAP_CONSTMSK_R_ != 1'b1);
localparam [0:0] S_USED = (_TECHMAP_CONSTMSK_S_ != 1'b1);
wire SR;
localparam SRVAL = (!R_USED) ? 1'b1 : 1'b0;
generate if (!R_USED && !S_USED) begin
assign SR = 1'b0;
end else if (R_USED && !S_USED) begin
assign SR = R;
end else if (!R_USED && S_USED) begin
assign SR = S;
end else begin
assign SR = 1'bx;
$error("Both S and R cannot be used simultaneously");
end endgenerate
parameter _TECHMAP_CONSTMSK_D1_ = 0;
parameter _TECHMAP_CONSTVAL_D1_ = 0;
parameter _TECHMAP_CONSTMSK_D2_ = 0;
parameter _TECHMAP_CONSTVAL_D2_ = 0;
localparam INV_D1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? !_TECHMAP_CONSTVAL_D1_ ^ IS_D1_INVERTED :
(_TECHMAP_CONSTVAL_D1_ === 0) ? IS_D1_INVERTED : !IS_D1_INVERTED;
wire d1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D1_ === 0) ? 1'b1 : D1;
localparam INV_D2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? !_TECHMAP_CONSTVAL_D2_ ^ IS_D2_INVERTED :
(_TECHMAP_CONSTVAL_D2_ === 0) ? IS_D2_INVERTED : !IS_D2_INVERTED;
wire d2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D2_ === 0) ? 1'b1 : D2;
ODDR_VPR # (
.ZINV_CLK (!IS_C_INVERTED),
.INV_D1 (INV_D1),
.INV_D2 (INV_D2),
.ZINV_D1 (!INV_D1),
.ZINV_D2 (!INV_D2),
.SRTYPE_SYNC ( SRTYPE == "SYNC"),
.SAME_EDGE ( (DDR_CLK_EDGE != "OPPOSITE_EDGE") ^ IS_C_INVERTED),
.ZINIT_Q (!INIT),
.ZSRVAL_Q (!SRVAL)
) _TECHMAP_REPLACE_ (
.CK (C),
.CE (CE),
.SR (SR),
.D1 (d1),
.D2 (d2),
.Q (Q)
);
endmodule
// ============================================================================
// IDELAYE2
module IDELAYE2 (
input C,
input CE,
input CINVCTRL,
input CNTVALUEIN0,
input CNTVALUEIN1,
input CNTVALUEIN2,
input CNTVALUEIN3,
input CNTVALUEIN4,
input DATAIN,
input IDATAIN,
input INC,
input LD,
input LDPIPEEN,
input REGRST,
output CNTVALUEOUT0,
output CNTVALUEOUT1,
output CNTVALUEOUT2,
output CNTVALUEOUT3,
output CNTVALUEOUT4,
output DATAOUT
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "IDATAIN";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter IDELAY_TYPE = "FIXED";
parameter PIPE_SEL = "FALSE";
parameter REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
parameter [4:0] IDELAY_VALUE = 5'b00000;
parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
localparam [4:0] ZIDELAY_VALUE = ~IDELAY_VALUE;
localparam [0:0] NOT_USING_CNTVALUEIN = (IDELAY_TYPE == "FIXED" || IDELAY_TYPE == "VARIABLE");
parameter _TECHMAP_CONSTMSK_IDATAIN_ = 1'b1;
parameter _TECHMAP_CONSTVAL_IDATAIN_ = 1'bx;
parameter _TECHMAP_CONSTMSK_DATAIN_ = 1'b1;
parameter _TECHMAP_CONSTVAL_DATAIN_ = 1'bx;
localparam [0:0] IDATAIN_USED = _TECHMAP_CONSTMSK_IDATAIN_ == 1'b0;
localparam [0:0] DATAIN_USED = _TECHMAP_CONSTMSK_DATAIN_ == 1'b0;
IDELAYE2_VPR #(
.IN_USE (IDATAIN_USED | DATAIN_USED),
.IDELAY_VALUE (IDELAY_VALUE),
.ZIDELAY_VALUE (ZIDELAY_VALUE),
.PIPE_SEL (PIPE_SEL == "TRUE"),
.CINVCTRL_SEL (CINVCTRL_SEL == "TRUE"),
.DELAY_SRC_DATAIN (DELAY_SRC == "DATAIN"),
.DELAY_SRC_IDATAIN (DELAY_SRC == "IDATAIN"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE == "TRUE"),
.IDELAY_TYPE_FIXED (IDELAY_TYPE == "FIXED"),
.IDELAY_TYPE_VAR_LOAD (IDELAY_TYPE == "VAR_LOAD"),
.IDELAY_TYPE_VARIABLE (IDELAY_TYPE == "VARIABLE"),
// Inverters
.IS_DATAIN_INVERTED (IS_DATAIN_INVERTED),
.IS_IDATAIN_INVERTED (IS_IDATAIN_INVERTED)
) _TECHMAP_REPLACE_ (
.C (C),
.CE (CE),
.CINVCTRL (CINVCTRL),
// CNTVALUEIN0-4 should be 1 if unused
.CNTVALUEIN0 (CNTVALUEIN0 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN1 (CNTVALUEIN1 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN2 (CNTVALUEIN2 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN3 (CNTVALUEIN3 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN4 (CNTVALUEIN4 | NOT_USING_CNTVALUEIN),
.DATAIN (DATAIN | ~DATAIN_USED),
.IDATAIN (IDATAIN | ~IDATAIN_USED),
.INC (INC),
.LD (LD),
.LDPIPEEN (LDPIPEEN),
.REGRST (REGRST),
.CNTVALUEOUT0 (CNTVALUEOUT0),
.CNTVALUEOUT1 (CNTVALUEOUT1),
.CNTVALUEOUT2 (CNTVALUEOUT2),
.CNTVALUEOUT3 (CNTVALUEOUT3),
.CNTVALUEOUT4 (CNTVALUEOUT4),
.DATAOUT (DATAOUT)
);
endmodule
// ============================================================================
// Clock Buffers
module BUFG (
input I,
output O
);
BUFGCTRL _TECHMAP_REPLACE_ (
.O(O),
.CE0(1'b1),
.CE1(1'b0),
.I0(I),
.I1(1'b1),
.IGNORE0(1'b0),
.IGNORE1(1'b1),
.S0(1'b1),
.S1(1'b0)
);
endmodule
module BUFGCE (
input I,
input CE,
output O,
);
BUFGCTRL _TECHMAP_REPLACE_ (
.O(O),
.CE0(CE),
.CE1(1'b0),
.I0(I),
.I1(1'b1),
.IGNORE0(1'b0),
.IGNORE1(1'b1),
.S0(1'b1),
.S1(1'b0)
);
endmodule
module BUFGMUX (
input I0,
input I1,
input S,
output O
);
BUFGCTRL #(
.IS_CE0_INVERTED(1'b1)
)_TECHMAP_REPLACE_ (
.O(O),
.CE0(S),
.CE1(S),
.I0(I0),
.I1(I1),
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.S0(1'b1),
.S1(1'b1)
);
endmodule
module BUFGCTRL (
output O,
input I0, input I1,
input S0, input S1,
input CE0, input CE1,
input IGNORE0, input IGNORE1
);
parameter [0:0] INIT_OUT = 1'b0;
parameter [0:0] PRESELECT_I0 = 1'b0;
parameter [0:0] PRESELECT_I1 = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_IGNORE0_ = 0;
parameter _TECHMAP_CONSTVAL_IGNORE0_ = 0;
parameter _TECHMAP_CONSTMSK_IGNORE1_ = 0;
parameter _TECHMAP_CONSTVAL_IGNORE1_ = 0;
parameter _TECHMAP_CONSTMSK_CE0_ = 0;
parameter _TECHMAP_CONSTVAL_CE0_ = 0;
parameter _TECHMAP_CONSTMSK_CE1_ = 0;
parameter _TECHMAP_CONSTVAL_CE1_ = 0;
parameter _TECHMAP_CONSTMSK_S0_ = 0;
parameter _TECHMAP_CONSTVAL_S0_ = 0;
parameter _TECHMAP_CONSTMSK_S1_ = 0;
parameter _TECHMAP_CONSTVAL_S1_ = 0;
localparam [0:0] INV_IGNORE0 = (
_TECHMAP_CONSTMSK_IGNORE0_ == 1 &&
_TECHMAP_CONSTVAL_IGNORE0_ == 0 &&
IS_IGNORE0_INVERTED == 0);
localparam [0:0] INV_IGNORE1 = (
_TECHMAP_CONSTMSK_IGNORE1_ == 1 &&
_TECHMAP_CONSTVAL_IGNORE1_ == 0 &&
IS_IGNORE1_INVERTED == 0);
localparam [0:0] INV_CE0 = (
_TECHMAP_CONSTMSK_CE0_ == 1 &&
_TECHMAP_CONSTVAL_CE0_ == 0 &&
IS_CE0_INVERTED == 0);
localparam [0:0] INV_CE1 = (
_TECHMAP_CONSTMSK_CE1_ == 1 &&
_TECHMAP_CONSTVAL_CE1_ == 0 &&
IS_CE1_INVERTED == 0);
localparam [0:0] INV_S0 = (
_TECHMAP_CONSTMSK_S0_ == 1 &&
_TECHMAP_CONSTVAL_S0_ == 0 &&
IS_S0_INVERTED == 0);
localparam [0:0] INV_S1 = (
_TECHMAP_CONSTMSK_S1_ == 1 &&
_TECHMAP_CONSTVAL_S1_ == 0 &&
IS_S1_INVERTED == 0);
BUFGCTRL_VPR #(
.INIT_OUT(INIT_OUT),
.ZPRESELECT_I0(PRESELECT_I0),
.ZPRESELECT_I1(PRESELECT_I1),
.IS_IGNORE0_INVERTED(!IS_IGNORE0_INVERTED ^ INV_IGNORE0),
.IS_IGNORE1_INVERTED(!IS_IGNORE1_INVERTED ^ INV_IGNORE1),
.ZINV_CE0(!IS_CE0_INVERTED ^ INV_CE0),
.ZINV_CE1(!IS_CE1_INVERTED ^ INV_CE1),
.ZINV_S0(!IS_S0_INVERTED ^ INV_S0),
.ZINV_S1(!IS_S1_INVERTED ^ INV_S1)
) _TECHMAP_REPLACE_ (
.O(O),
.CE0(CE0 ^ INV_CE0),
.CE1(CE1 ^ INV_CE1),
.I0(I0),
.I1(I1),
.IGNORE0(IGNORE0 ^ INV_IGNORE0),
.IGNORE1(IGNORE1 ^ INV_IGNORE1),
.S0(S0 ^ INV_S0),
.S1(S1 ^ INV_S1)
);
endmodule
module BUFH (
input I,
output O
);
BUFHCE _TECHMAP_REPLACE_ (
.O(O),
.I(I),
.CE(1)
);
endmodule
module BUFHCE (
input I,
input CE,
output O
);
parameter [0:0] INIT_OUT = 1'b0;
parameter [0:0] IS_CE_INVERTED = 1'b0;
parameter [0:0] _TECHMAP_CONSTMSK_CE_ = 0;
parameter [0:0] _TECHMAP_CONSTVAL_CE_ = 0;
localparam [0:0] INV_CE = (
_TECHMAP_CONSTMSK_CE_ == 1 &&
_TECHMAP_CONSTVAL_CE_ == 0 &&
IS_CE_INVERTED == 0);
BUFHCE_VPR #(
.INIT_OUT(INIT_OUT),
.ZINV_CE(!IS_CE_INVERTED ^ INV_CE)
) _TECHMAP_REPLACE_ (
.O(O),
.I(I),
.CE(CE)
);
endmodule
// ============================================================================
// PLL/MMCM
`define PLL_FRAC_PRECISION 10
`define PLL_FIXED_WIDTH 32
// Rounds a fixed point number to a given precision
function [`PLL_FIXED_WIDTH:1] pll_round_frac
(
input [`PLL_FIXED_WIDTH:1] decimal,
input [`PLL_FIXED_WIDTH:1] precision
);
if (decimal[(`PLL_FRAC_PRECISION - precision)] == 1'b1) begin
pll_round_frac = decimal + (1'b1 << (`PLL_FRAC_PRECISION - precision));
end else begin
pll_round_frac = decimal;
end
endfunction
// Computes content of the PLLs divider registers
function [13:0] pll_divider_regs
(
input [ 7:0] divide, // Max divide is 128
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
);
reg [`PLL_FIXED_WIDTH:1] duty_cycle_fix;
reg [`PLL_FIXED_WIDTH:1] duty_cycle_min;
reg [`PLL_FIXED_WIDTH:1] duty_cycle_max;
reg [6:0] high_time;
reg [6:0] low_time;
reg w_edge;
reg no_count;
reg [`PLL_FIXED_WIDTH:1] temp;
if (divide >= 64) begin
duty_cycle_min = ((divide - 64) * 100_000) / divide;
duty_cycle_max = (645 / divide) * 100_00;
if (duty_cycle > duty_cycle_max)
duty_cycle = duty_cycle_max;
if (duty_cycle < duty_cycle_min)
duty_cycle = duty_cycle_min;
end
duty_cycle_fix = (duty_cycle << `PLL_FRAC_PRECISION) / 100_000;
if (divide == 7'h01) begin
high_time = 7'h01;
w_edge = 1'b0;
low_time = 7'h01;
no_count = 1'b1;
end else begin
temp = pll_round_frac(duty_cycle_fix*divide, 1);
high_time = temp[`PLL_FRAC_PRECISION+7:`PLL_FRAC_PRECISION+1];
w_edge = temp[`PLL_FRAC_PRECISION];
if (high_time == 7'h00) begin
high_time = 7'h01;
w_edge = 1'b0;
end
if (high_time == divide) begin
high_time = divide - 1;
w_edge = 1'b1;
end
low_time = divide - high_time;
no_count = 1'b0;
end
pll_divider_regs = {w_edge, no_count, high_time[5:0], low_time[5:0]};
endfunction
// Computes the PLLs phase shift registers
function [10:0] pll_phase_regs
(
input [ 7:0] divide,
input signed [31:0] phase
);
reg [`PLL_FIXED_WIDTH:1] phase_in_cycles;
reg [`PLL_FIXED_WIDTH:1] phase_fixed;
reg [1:0] mx;
reg [5:0] delay_time;
reg [2:0] phase_mux;
reg [`PLL_FIXED_WIDTH:1] temp;
if(phase < 0) begin
phase_fixed = ((phase + 360000) << `PLL_FRAC_PRECISION) / 1000;
end else begin
phase_fixed = (phase << `PLL_FRAC_PRECISION) / 1000;
end
phase_in_cycles = (phase_fixed * divide) / 360;
temp = pll_round_frac(phase_in_cycles, 3);
mx = 2'b00;
phase_mux = temp[`PLL_FRAC_PRECISION:`PLL_FRAC_PRECISION-2];
delay_time = temp[`PLL_FRAC_PRECISION+6:`PLL_FRAC_PRECISION+1];
pll_phase_regs = {mx, phase_mux, delay_time};
endfunction
// Given PLL/MMCM divide, duty_cycle and phase calculates content of the
// CLKREG1 and CLKREG2.
function [31:0] pll_clkregs
(
input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle, // Multiplied by 100,000
input signed [31:0] phase // Phase is given in degrees (-360,000 to 360,000)
);
reg [13:0] pll_div; // EDGE, NO_COUNT, HIGH_TIME[5:0], LOW_TIME[5:0]
reg [10:0] pll_phase; // MX, PHASE_MUX[2:0], DELAY_TIME[5:0]
pll_div = pll_divider_regs(divide, duty_cycle);
pll_phase = pll_phase_regs(divide, phase);
pll_clkregs = {
// CLKREG2: RESERVED[6:0], MX[1:0], EDGE, NO_COUNT, DELAY_TIME[5:0]
6'h00, pll_phase[10:9], pll_div[13:12], pll_phase[5:0],
// CLKREG1: PHASE_MUX[3:0], RESERVED, HIGH_TIME[5:0], LOW_TIME[5:0]
pll_phase[8:6], 1'b0, pll_div[11:0]
};
endfunction
// This function takes the divide value and outputs the necessary lock values
function [39:0] pll_lktable_lookup
(
input [6:0] divide // Max divide is 64
);
reg [2559:0] lookup;
lookup = {
// This table is composed of:
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
40'b00110_00110_1111101000_1111101001_0000000001,
40'b00110_00110_1111101000_1111101001_0000000001,
40'b01000_01000_1111101000_1111101001_0000000001,
40'b01011_01011_1111101000_1111101001_0000000001,
40'b01110_01110_1111101000_1111101001_0000000001,
40'b10001_10001_1111101000_1111101001_0000000001,
40'b10011_10011_1111101000_1111101001_0000000001,
40'b10110_10110_1111101000_1111101001_0000000001,
40'b11001_11001_1111101000_1111101001_0000000001,
40'b11100_11100_1111101000_1111101001_0000000001,
40'b11111_11111_1110000100_1111101001_0000000001,
40'b11111_11111_1100111001_1111101001_0000000001,
40'b11111_11111_1011101110_1111101001_0000000001,
40'b11111_11111_1010111100_1111101001_0000000001,
40'b11111_11111_1010001010_1111101001_0000000001,
40'b11111_11111_1001110001_1111101001_0000000001,
40'b11111_11111_1000111111_1111101001_0000000001,
40'b11111_11111_1000100110_1111101001_0000000001,
40'b11111_11111_1000001101_1111101001_0000000001,
40'b11111_11111_0111110100_1111101001_0000000001,
40'b11111_11111_0111011011_1111101001_0000000001,
40'b11111_11111_0111000010_1111101001_0000000001,
40'b11111_11111_0110101001_1111101001_0000000001,
40'b11111_11111_0110010000_1111101001_0000000001,
40'b11111_11111_0110010000_1111101001_0000000001,
40'b11111_11111_0101110111_1111101001_0000000001,
40'b11111_11111_0101011110_1111101001_0000000001,
40'b11111_11111_0101011110_1111101001_0000000001,
40'b11111_11111_0101000101_1111101001_0000000001,
40'b11111_11111_0101000101_1111101001_0000000001,
40'b11111_11111_0100101100_1111101001_0000000001,
40'b11111_11111_0100101100_1111101001_0000000001,
40'b11111_11111_0100101100_1111101001_0000000001,
40'b11111_11111_0100010011_1111101001_0000000001,
40'b11111_11111_0100010011_1111101001_0000000001,
40'b11111_11111_0100010011_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001
};
pll_lktable_lookup = lookup[ ((64-divide)*40) +: 40];
endfunction
// This function takes the divide value and the bandwidth setting of the PLL
// and outputs the digital filter settings necessary.
function [9:0] pll_table_lookup
(
input [6:0] divide, // Max divide is 64
input [8*9:0] BANDWIDTH
);
reg [639:0] lookup_low;
reg [639:0] lookup_high;
reg [639:0] lookup_optimized;
reg [9:0] lookup_entry;
lookup_low = {
// CP_RES_LFHF
10'b0010_1111_00,
10'b0010_1111_00,
10'b0010_0111_00,
10'b0010_1101_00,
10'b0010_0101_00,
10'b0010_0101_00,
10'b0010_1001_00,
10'b0010_1110_00,
10'b0010_1110_00,
10'b0010_0001_00,
10'b0010_0001_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00
};
lookup_high = {
// CP_RES_LFHF
10'b0011_0111_00,
10'b0011_0111_00,
10'b0101_1111_00,
10'b0111_1111_00,
10'b0111_1011_00,
10'b1101_0111_00,
10'b1110_1011_00,
10'b1110_1101_00,
10'b1111_1101_00,
10'b1111_0111_00,
10'b1111_1011_00,
10'b1111_1101_00,
10'b1111_0011_00,
10'b1110_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b0100_0010_00,
10'b0100_0010_00,
10'b0100_0010_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0011_0100_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00
};
lookup_optimized = {
// CP_RES_LFHF
10'b0011_0111_00,
10'b0011_0111_00,
10'b0101_1111_00,
10'b0111_1111_00,
10'b0111_1011_00,
10'b1101_0111_00,
10'b1110_1011_00,
10'b1110_1101_00,
10'b1111_1101_00,
10'b1111_0111_00,
10'b1111_1011_00,
10'b1111_1101_00,
10'b1111_0011_00,
10'b1110_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b0100_0010_00,
10'b0100_0010_00,
10'b0100_0010_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0011_0100_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00
};
if (BANDWIDTH == "LOW") begin
pll_table_lookup = lookup_low[((64-divide)*10) +: 10];
end else if (BANDWIDTH == "HIGH") begin
pll_table_lookup = lookup_high[((64-divide)*10) +: 10];
end else if (BANDWIDTH == "OPTIMIZED") begin
pll_table_lookup = lookup_optimized[((64-divide)*10) +: 10];
end
endfunction
// ............................................................................
// IMPORTANT NOTE: Due to lack of support for real type parameters in Yosys
// the PLL parameters that define duty cycles and phase shifts have to be
// provided as integers! The DUTY_CYCLE is expressed as % of high time times
// 1000 whereas the PHASE is expressed in degrees times 1000.
// PLLE2_ADV
module PLLE2_ADV
(
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input PWRDWN,
input RST,
output LOCKED,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter _TECHMAP_CONSTMSK_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTVAL_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTMSK_RST_ = 0;
parameter _TECHMAP_CONSTVAL_RST_ = 0;
parameter _TECHMAP_CONSTMSK_PWRDWN_ = 0;
parameter _TECHMAP_CONSTVAL_PWRDWN_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTMSK_DCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DEN_ = 0;
parameter _TECHMAP_CONSTVAL_DEN_ = 0;
parameter _TECHMAP_CONSTMSK_DWE_ = 0;
parameter _TECHMAP_CONSTVAL_DWE_ = 0;
parameter IS_CLKINSEL_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_PWRDWN_INVERTED = 1'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
parameter COMPENSATION = "ZHOLD";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.01;
parameter CLKIN2_PERIOD = 0.0;
parameter REF_JITTER2 = 0.01;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter [5:0] CLKFBOUT_MULT = 1;
parameter CLKFBOUT_PHASE = 0;
parameter [6:0] CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed CLKOUT0_PHASE = 0;
parameter [6:0] CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed CLKOUT1_PHASE = 0;
parameter [6:0] CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed CLKOUT2_PHASE = 0;
parameter [6:0] CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed CLKOUT3_PHASE = 0;
parameter [6:0] CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed CLKOUT4_PHASE = 0;
parameter [6:0] CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed CLKOUT5_PHASE = 0;
// Compute PLL's registers content
localparam CLKFBOUT_REGS = pll_clkregs(CLKFBOUT_MULT, 50000, CLKFBOUT_PHASE);
localparam DIVCLK_REGS = pll_clkregs(DIVCLK_DIVIDE, 50000, 0);
localparam CLKOUT0_REGS = pll_clkregs(CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, CLKOUT0_PHASE);
localparam CLKOUT1_REGS = pll_clkregs(CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, CLKOUT1_PHASE);
localparam CLKOUT2_REGS = pll_clkregs(CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, CLKOUT2_PHASE);
localparam CLKOUT3_REGS = pll_clkregs(CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, CLKOUT3_PHASE);
localparam CLKOUT4_REGS = pll_clkregs(CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, CLKOUT4_PHASE);
localparam CLKOUT5_REGS = pll_clkregs(CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE);
// Handle inputs that should have certain logic levels when left unconnected
// If unconnected, CLKINSEL should be set to VCC by default
localparam INV_CLKINSEL = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? !_TECHMAP_CONSTVAL_CLKINSEL_ ^ IS_CLKINSEL_INVERTED:
(_TECHMAP_CONSTVAL_CLKINSEL_ === 0) ? IS_CLKINSEL_INVERTED : IS_CLKINSEL_INVERTED;
wire clkinsel = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKINSEL_ === 0) ? 1'b1 : CLKINSEL;
localparam INV_PWRDWN = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? !_TECHMAP_CONSTVAL_PWRDWN_ ^ IS_PWRDWN_INVERTED:
(_TECHMAP_CONSTVAL_PWRDWN_ === 0) ? ~IS_PWRDWN_INVERTED : IS_PWRDWN_INVERTED;
wire pwrdwn = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PWRDWN_ === 0) ? 1'b1 : PWRDWN;
localparam INV_RST = (_TECHMAP_CONSTMSK_RST_ == 1) ? !_TECHMAP_CONSTVAL_RST_ ^ IS_RST_INVERTED:
(_TECHMAP_CONSTVAL_RST_ === 0) ? ~IS_RST_INVERTED : IS_RST_INVERTED;
wire rst = (_TECHMAP_CONSTMSK_RST_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RST_ === 0) ? 1'b1 : RST;
wire dclk = (_TECHMAP_CONSTMSK_DCLK_ == 1) ? _TECHMAP_CONSTVAL_DCLK_ :
(_TECHMAP_CONSTVAL_DCLK_ == 0) ? 1'b0 : DCLK;
wire den = (_TECHMAP_CONSTMSK_DEN_ == 1) ? _TECHMAP_CONSTVAL_DEN_ :
(_TECHMAP_CONSTVAL_DEN_ == 0) ? 1'b0 : DEN;
wire dwe = (_TECHMAP_CONSTMSK_DWE_ == 1) ? _TECHMAP_CONSTVAL_DWE_ :
(_TECHMAP_CONSTVAL_DWE_ == 0) ? 1'b0 : DWE;
// The substituted cell
PLLE2_ADV_VPR #
(
// Inverters
.INV_CLKINSEL(INV_CLKINSEL),
.ZINV_PWRDWN (INV_PWRDWN),
.ZINV_RST (INV_RST),
// Straight mapped parameters
.STARTUP_WAIT(STARTUP_WAIT == "TRUE"),
// Lookup tables
.LKTABLE(pll_lktable_lookup(CLKFBOUT_MULT)),
.TABLE(pll_table_lookup(CLKFBOUT_MULT, BANDWIDTH)),
// FIXME: How to compute values the two below ?
.FILTREG1_RESERVED(12'b0000_00001000),
.LOCKREG3_RESERVED(1'b1),
// Clock feedback settings
.CLKFBOUT_CLKOUT1_HIGH_TIME (CLKFBOUT_REGS[11:6]),
.CLKFBOUT_CLKOUT1_LOW_TIME (CLKFBOUT_REGS[5:0]),
.CLKFBOUT_CLKOUT1_PHASE_MUX (CLKFBOUT_REGS[15:13]),
.CLKFBOUT_CLKOUT2_DELAY_TIME (CLKFBOUT_REGS[21:16]),
.CLKFBOUT_CLKOUT2_EDGE (CLKFBOUT_REGS[23]),
.CLKFBOUT_CLKOUT2_NO_COUNT (CLKFBOUT_REGS[22]),
// Internal VCO divider settings
.DIVCLK_DIVCLK_HIGH_TIME (DIVCLK_REGS[11:6]),
.DIVCLK_DIVCLK_LOW_TIME (DIVCLK_REGS[5:0]),
.DIVCLK_DIVCLK_NO_COUNT (DIVCLK_REGS[22]),
.DIVCLK_DIVCLK_EDGE (DIVCLK_REGS[23]),
// CLKOUT0
.CLKOUT0_CLKOUT1_HIGH_TIME (CLKOUT0_REGS[11:6]),
.CLKOUT0_CLKOUT1_LOW_TIME (CLKOUT0_REGS[5:0]),
.CLKOUT0_CLKOUT1_PHASE_MUX (CLKOUT0_REGS[15:13]),
.CLKOUT0_CLKOUT2_DELAY_TIME (CLKOUT0_REGS[21:16]),
.CLKOUT0_CLKOUT2_EDGE (CLKOUT0_REGS[23]),
.CLKOUT0_CLKOUT2_NO_COUNT (CLKOUT0_REGS[22]),
// CLKOUT1
.CLKOUT1_CLKOUT1_HIGH_TIME (CLKOUT1_REGS[11:6]),
.CLKOUT1_CLKOUT1_LOW_TIME (CLKOUT1_REGS[5:0]),
.CLKOUT1_CLKOUT1_PHASE_MUX (CLKOUT1_REGS[15:13]),
.CLKOUT1_CLKOUT2_DELAY_TIME (CLKOUT1_REGS[21:16]),
.CLKOUT1_CLKOUT2_EDGE (CLKOUT1_REGS[23]),
.CLKOUT1_CLKOUT2_NO_COUNT (CLKOUT1_REGS[22]),
// CLKOUT2
.CLKOUT2_CLKOUT1_HIGH_TIME (CLKOUT2_REGS[11:6]),
.CLKOUT2_CLKOUT1_LOW_TIME (CLKOUT2_REGS[5:0]),
.CLKOUT2_CLKOUT1_PHASE_MUX (CLKOUT2_REGS[15:13]),
.CLKOUT2_CLKOUT2_DELAY_TIME (CLKOUT2_REGS[21:16]),
.CLKOUT2_CLKOUT2_EDGE (CLKOUT2_REGS[23]),
.CLKOUT2_CLKOUT2_NO_COUNT (CLKOUT2_REGS[22]),
// CLKOUT3
.CLKOUT3_CLKOUT1_HIGH_TIME (CLKOUT3_REGS[11:6]),
.CLKOUT3_CLKOUT1_LOW_TIME (CLKOUT3_REGS[5:0]),
.CLKOUT3_CLKOUT1_PHASE_MUX (CLKOUT3_REGS[15:13]),
.CLKOUT3_CLKOUT2_DELAY_TIME (CLKOUT3_REGS[21:16]),
.CLKOUT3_CLKOUT2_EDGE (CLKOUT3_REGS[23]),
.CLKOUT3_CLKOUT2_NO_COUNT (CLKOUT3_REGS[22]),
// CLKOUT4
.CLKOUT4_CLKOUT1_HIGH_TIME (CLKOUT4_REGS[11:6]),
.CLKOUT4_CLKOUT1_LOW_TIME (CLKOUT4_REGS[5:0]),
.CLKOUT4_CLKOUT1_PHASE_MUX (CLKOUT4_REGS[15:13]),
.CLKOUT4_CLKOUT2_DELAY_TIME (CLKOUT4_REGS[21:16]),
.CLKOUT4_CLKOUT2_EDGE (CLKOUT4_REGS[23]),
.CLKOUT4_CLKOUT2_NO_COUNT (CLKOUT4_REGS[22]),
// CLKOUT5
.CLKOUT5_CLKOUT1_HIGH_TIME (CLKOUT5_REGS[11:6]),
.CLKOUT5_CLKOUT1_LOW_TIME (CLKOUT5_REGS[5:0]),
.CLKOUT5_CLKOUT1_PHASE_MUX (CLKOUT5_REGS[15:13]),
.CLKOUT5_CLKOUT2_DELAY_TIME (CLKOUT5_REGS[21:16]),
.CLKOUT5_CLKOUT2_EDGE (CLKOUT5_REGS[23]),
.CLKOUT5_CLKOUT2_NO_COUNT (CLKOUT5_REGS[22]),
// Clock output enable controls
.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKFBOUT_ === 1'bX),
.CLKOUT0_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT0_ === 1'bX),
.CLKOUT1_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT1_ === 1'bX),
.CLKOUT2_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT2_ === 1'bX),
.CLKOUT3_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT3_ === 1'bX),
.CLKOUT4_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT4_ === 1'bX),
.CLKOUT5_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT5_ === 1'bX)
)
_TECHMAP_REPLACE_
(
.CLKFBIN(CLKFBIN),
.CLKIN1(CLKIN1),
.CLKIN2(CLKIN2),
.CLKFBOUT(CLKFBOUT),
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKINSEL (clkinsel),
.PWRDWN (pwrdwn),
.RST (rst),
.LOCKED (LOCKED),
.DCLK (dclk),
.DEN (den),
.DWE (dwe),
.DRDY (DRDY),
.DADDR(DADDR),
.DI (DI),
.DO (DO)
);
endmodule
// PLLE2_BASE
module PLLE2_BASE
(
input CLKFBIN,
input CLKIN,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input RST,
output LOCKED
);
parameter IS_CLKINSEL_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.1;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter [5:0] CLKFBOUT_MULT = 1;
parameter signed CLKFBOUT_PHASE = 0;
parameter [6:0] CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed CLKOUT0_PHASE = 0;
parameter [6:0] CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed CLKOUT1_PHASE = 0;
parameter [6:0] CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed CLKOUT2_PHASE = 0;
parameter [6:0] CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed CLKOUT3_PHASE = 0;
parameter [6:0] CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed CLKOUT4_PHASE = 0;
parameter [6:0] CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed CLKOUT5_PHASE = 0;
// The substituted cell
PLLE2_ADV #
(
.IS_CLKINSEL_INVERTED(IS_CLKINSEL_INVERTED),
.IS_RST_INVERTED(IS_RST_INVERTED),
.IS_PWRDWN_INVERTED(1'b0),
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.REF_JITTER1(REF_JITTER1),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE)
)
_TECHMAP_REPLACE_
(
.CLKFBIN(CLKFBIN),
.CLKIN1(CLKIN),
.CLKINSEL(1'b1),
.CLKFBOUT(CLKFBOUT),
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.PWRDWN(1'b0),
.RST(RST),
.LOCKED(LOCKED),
.DCLK(1'b0),
.DEN(1'b0),
.DWE(1'b0),
.DRDY(),
.DADDR(7'd0),
.DI(16'd0),
.DO()
);
endmodule
// ............................................................................
// Given MMCM divide, duty_cycle and phase calculates content of the
// CLKREG1 and CLKREG2 when no fractional divide is used.
function [31:0] mmcm_clkregs
(
input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle, // Multiplied by 100,000
input signed [31:0] phase // Phase is given in degrees (-360,000 to 360,000)
);
// Identical to the PLL one
mmcm_clkregs = pll_clkregs(divide, duty_cycle, phase);
endfunction
// Computes content of CLKREG1 and CLKREG2 plus the shared part for fractional
// divider.
function [37:0] mmcm_clkregs_frac
(
input [17:0] divide, // Max divide is 128000 (int + 1000 * frac)
input [31:0] duty_cycle, // Multiplied by 100,000
input signed [31:0] phase // Phase is given in degrees (-360,000 to 360,000)
);
// Decompose the fractional divider
reg [7:0] divide_int;
reg [9:0] divide_frac;
divide_int = (divide / 1000);
divide_frac = (divide % 1000) / 125;
// Calculate wf_fall_time and wf_rise_time
reg [7:0] even_part_high;
reg [7:0] even_part_low;
reg [7:0] odd;
reg [9:0] odd_and_frac;
reg [7:0] lt_frac;
reg [7:0] ht_frac;
reg [7:0] pm_fall;
reg [7:0] pm_rise;
reg [0:0] wf_fall_frac;
reg [0:0] wf_rise_frac;
even_part_high = divide_int >> 1;
even_part_low = even_part_high;
odd = divide_int - even_part_high - even_part_low;
odd_and_frac = (8 * odd) + divide_frac;
lt_frac = even_part_high - (odd_and_frac <= 9);
ht_frac = even_part_low - (odd_and_frac <= 8);
pm_fall = {odd[6:0], 2'b00} + {6'h00, divide_frac[2:1]};
pm_rise = 0;
wf_fall_frac = ((odd_and_frac >= 2) && (odd_and_frac <= 9)) || ((divide_frac == 1) && (divide_int == 2));
wf_rise_frac = (odd_and_frac >= 1) && (odd_and_frac <= 8);
// Calculate phase shift in fractional cycles
reg [31:0] a_per_in_octets;
reg [31:0] a_phase_in_cycles;
reg [63:0] dt_calc;
reg [ 7:0] dt;
reg [ 7:0] pm_rise_frac_filtered;
reg [ 7:0] pm_fall_frac_filtered;
a_per_in_octets = (8 * divide_int) + divide_frac;
a_phase_in_cycles = (phase + 10) * a_per_in_octets / 360000;
dt_calc = ((phase + 10) * a_per_in_octets / 8 ) / 360000;
dt = dt_calc[7:0];
pm_rise_frac_filtered = a_phase_in_cycles % 8;
pm_fall_frac_filtered = (pm_fall + pm_rise_frac_filtered) % 8;
// Pack output data
mmcm_clkregs_frac = {
// Shared: RESERVED[1:0], FRAC_TIME[2:0], FRAC_WF_FALL
2'b11, pm_fall_frac_filtered[2:0], wf_fall_frac,
// CLKREG2: RESERVED[0:0], FRAC[2:0], FRAC_EN[0:0], FRAC_WF_R[0:0], MX[1:0], EDGE, NO_COUNT, DELAY_TIME[5:0]
1'b0, divide_frac[2:0], 1'b1, wf_rise_frac, 4'h0, dt[5:0],
// CLKREG1: PHASE_MUX[2:0], RESERVED, HIGH_TIME[5:0], LOW_TIME[5:0]
pm_rise_frac_filtered[2:0], 1'b0, ht_frac[5:0], lt_frac[5:0]
};
endfunction
// This function takes the divide value and outputs the necessary lock values
function [39:0] mmcm_lktable_lookup
(
input [6:0] divide // Max divide is 64
);
// The look-up table is identical to the one for PLL
mmcm_lktable_lookup = pll_lktable_lookup(divide);
endfunction
// This function takes the divide value and the bandwidth setting of a MMCM
// and outputs the digital filter settings necessary.
function [9:0] mmcm_table_lookup
(
input [6:0] divide, // Max divide is 64
input [8*9:0] BANDWIDTH,
input [0:0] SS_EN
);
reg [639:0] lookup_low;
reg [639:0] lookup_ss;
reg [639:0] lookup_high;
reg [639:0] lookup_optimized;
reg [9:0] lookup_entry;
lookup_low = {
// CP_RES_LFHF
10'b0010_1111_00,
10'b0010_1111_00,
10'b0010_1111_00,
10'b0010_1111_00,
10'b0010_0111_00,
10'b0010_1011_00,
10'b0010_1101_00,
10'b0010_0011_00,
10'b0010_0101_00,
10'b0010_0101_00,
10'b0010_1001_00,
10'b0010_1110_00,
10'b0010_1110_00,
10'b0010_1110_00,
10'b0010_1110_00,
10'b0010_0001_00,
10'b0010_0001_00,
10'b0010_0001_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00
};
lookup_ss = {
// CP_RES_LFHF
10'b0010_1111_11,
10'b0010_1111_11,
10'b0010_1111_11,
10'b0010_1111_11,
10'b0010_0111_11,
10'b0010_1011_11,
10'b0010_1101_11,
10'b0010_0011_11,
10'b0010_0101_11,
10'b0010_0101_11,
10'b0010_1001_11,
10'b0010_1110_11,
10'b0010_1110_11,
10'b0010_1110_11,
10'b0010_1110_11,
10'b0010_0001_11,
10'b0010_0001_11,
10'b0010_0001_11,
10'b0010_0110_11,
10'b0010_0110_11,
10'b0010_0110_11,
10'b0010_0110_11,
10'b0010_0110_11,
10'b0010_0110_11,
10'b0010_0110_11,
10'b0010_1010_11,
10'b0010_1010_11,
10'b0010_1010_11,
10'b0010_1010_11,
10'b0010_1010_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_1100_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11,
10'b0010_0010_11
};
lookup_high = {
// CP_RES_LFHF
10'b0010_1111_00,
10'b0100_1111_00,
10'b0101_1011_00,
10'b0111_0111_00,
10'b1101_0111_00,
10'b1110_1011_00,
10'b1110_1101_00,
10'b1111_0011_00,
10'b1110_0101_00,
10'b1111_0101_00,
10'b1111_1001_00,
10'b1101_0001_00,
10'b1111_1001_00,
10'b1111_1001_00,
10'b1111_1001_00,
10'b1111_1001_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0111_0001_00,
10'b0111_0001_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0110_0001_00,
10'b0110_0001_00,
10'b0101_0110_00,
10'b0101_0110_00,
10'b0101_0110_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0100_1010_00,
10'b0011_1100_00,
10'b0011_1100_00
};
lookup_optimized = {
// CP_RES_LFHF
10'b0010_1111_00,
10'b0100_1111_00,
10'b0101_1011_00,
10'b0111_0111_00,
10'b1101_0111_00,
10'b1110_1011_00,
10'b1110_1101_00,
10'b1111_0011_00,
10'b1110_0101_00,
10'b1111_0101_00,
10'b1111_1001_00,
10'b1101_0001_00,
10'b1111_1001_00,
10'b1111_1001_00,
10'b1111_1001_00,
10'b1111_1001_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0011_0100_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0111_0001_00,
10'b0111_0001_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0110_0001_00,
10'b0110_0001_00,
10'b0101_0110_00,
10'b0101_0110_00,
10'b0101_0110_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0100_1010_00,
10'b0011_1100_00,
10'b0011_1100_00
};
if (SS_EN == 1'b1) begin
mmcm_table_lookup = lookup_ss[((64-divide)*10) +: 10];
end else begin
if (BANDWIDTH == "LOW") begin
mmcm_table_lookup = lookup_low[((64-divide)*10) +: 10];
end else if (BANDWIDTH == "HIGH") begin
mmcm_table_lookup = lookup_high[((64-divide)*10) +: 10];
end else if (BANDWIDTH == "OPTIMIZED") begin
mmcm_table_lookup = lookup_optimized[((64-divide)*10) +: 10];
end
end
endfunction
// ............................................................................
// IMPORTANT NOTE: Due to lack of support for real type parameters in Yosys
// the MMCM parameters that define duty cycles and phase shifts have to be
// provided as integers! The DUTY_CYCLE is expressed as % of high time times
// 1000 whereas the PHASE is expressed in degrees times 1000. Fractional
// dividers are also expressed as multiplied times 1000.
// MMCME2_ADV
module MMCME2_ADV
(
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output CLKINSTOPPED,
output CLKFBSTOPPED,
input PWRDWN,
input RST,
output LOCKED,
input PSCLK,
input PSEN,
input PSINCDEC,
output PSDONE,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter _TECHMAP_CONSTMSK_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTVAL_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTMSK_RST_ = 0;
parameter _TECHMAP_CONSTVAL_RST_ = 0;
parameter _TECHMAP_CONSTMSK_PWRDWN_ = 0;
parameter _TECHMAP_CONSTVAL_PWRDWN_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUTB_= 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUTB_= 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT6_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT6_ = 0;
parameter _TECHMAP_CONSTMSK_PSCLK_ = 0;
parameter _TECHMAP_CONSTVAL_PSCLK_ = 0;
parameter _TECHMAP_CONSTMSK_PSEN_ = 0;
parameter _TECHMAP_CONSTVAL_PSEN_ = 0;
parameter _TECHMAP_CONSTMSK_PSINCDEC_ = 0;
parameter _TECHMAP_CONSTVAL_PSINCDEC_ = 0;
parameter _TECHMAP_CONSTMSK_DCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DEN_ = 0;
parameter _TECHMAP_CONSTVAL_DEN_ = 0;
parameter _TECHMAP_CONSTMSK_DWE_ = 0;
parameter _TECHMAP_CONSTVAL_DWE_ = 0;
parameter IS_CLKINSEL_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_PWRDWN_INVERTED = 1'b0;
parameter IS_PSEN_INVERTED = 1'b0;
parameter IS_PSINCDEC_INVERTED = 1'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
// Previously, the default COMPENSATION value was ZHOLD, resulting in non-functional
// bitstreams when the feedback loop is closed on-chip.
// Setting it to INTERNAL as the default creates working bitstreams for that case.
// This bug was not previously uncovered since the MMCM tests all explicitly
// specified a COMPENSATION value so the ZHOLD default was never used.
// Setting it here in the techmapper means that existing code using on-chip
// MMCM feedback without specifying a COMPENSATION value can be ported
// unmodified into the toolflow and will result in functional bitstreams.
// A test was added to test the case when relying on the default COMPENSATION value.
parameter COMPENSATION = "INTERNAL";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.01;
parameter CLKIN2_PERIOD = 0.0;
parameter REF_JITTER2 = 0.01;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter CLKFBOUT_MULT_F = 5000;
parameter signed [31:0] CLKFBOUT_PHASE = 0;
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
parameter CLKOUT0_DIVIDE_F = 1000;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT0_PHASE = 0;
parameter CLKOUT0_USE_FINE_PS = "FALSE";
parameter CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT1_PHASE = 0;
parameter CLKOUT1_USE_FINE_PS = "FALSE";
parameter CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT2_PHASE = 0;
parameter CLKOUT2_USE_FINE_PS = "FALSE";
parameter CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT3_PHASE = 0;
parameter CLKOUT3_USE_FINE_PS = "FALSE";
parameter CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT4_PHASE = 0;
parameter CLKOUT4_USE_FINE_PS = "FALSE";
parameter CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT5_PHASE = 0;
parameter CLKOUT5_USE_FINE_PS = "FALSE";
parameter CLKOUT6_DIVIDE = 1;
parameter CLKOUT6_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT6_PHASE = 0;
parameter CLKOUT6_USE_FINE_PS = "FALSE";
parameter CLKOUT4_CASCADE = 0;
parameter SS_EN = "FALSE";
parameter SS_MODE = "CENTER_HIGH";
parameter SS_MOD_PERIOD = 10000;
// Sanity check parameters
if (BANDWIDTH != "HIGH" && BANDWIDTH != "LOW" && BANDWIDTH != "OPTIMIZED") begin
wire _TECHMAP_FAIL_;
$error("BANDWIDTH must be one of: 'HIGH', 'LOW', 'OPTIMIZED'");
end
if (COMPENSATION != "ZHOLD" && COMPENSATION != "EXTERNAL" && COMPENSATION != "INTERNAL" && COMPENSATION != "BUF_IN") begin
wire _TECHMAP_FAIL_;
$error("COMPENSATION must be one of: 'ZHOLD', 'EXTERNAL', 'INTERNAL', 'BUF_IN'");
end
if (DIVCLK_DIVIDE < 1 || DIVCLK_DIVIDE > 106) begin
wire _TECHMAP_FAIL_;
$error("DIVCLK_DIVIDE must range from 1 to 106");
end
if (CLKFBOUT_MULT_F < 2000 || CLKFBOUT_MULT_F > 64000) begin
wire _TECHMAP_FAIL_;
$error("CLKFBOUT_MULT_F must range from 2000 to 64000");
end
if (CLKFBOUT_PHASE < -32'sd360000 || CLKFBOUT_PHASE > 32'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKFBOUT_PHASE must range from -360000 to 360000");
end
if (CLKOUT0_DIVIDE_F < 1000 || CLKOUT0_DIVIDE_F > 128000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT0_DIVIDE_F must range from 1000 to 128000");
end
if (CLKOUT1_DIVIDE < 1 || CLKOUT1_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT1_DIVIDE must range from 1 to 128");
end
if (CLKOUT2_DIVIDE < 1 || CLKOUT2_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT2_DIVIDE must range from 1 to 128");
end
if (CLKOUT3_DIVIDE < 1 || CLKOUT3_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT3_DIVIDE must range from 1 to 128");
end
if (CLKOUT4_DIVIDE < 1 || CLKOUT4_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT4_DIVIDE must range from 1 to 128");
end
if (CLKOUT5_DIVIDE < 1 || CLKOUT5_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT5_DIVIDE must range from 1 to 128");
end
if (CLKOUT6_DIVIDE < 1 || CLKOUT6_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT6_DIVIDE must range from 1 to 128");
end
if (CLKOUT0_PHASE < -'sd360000 || CLKOUT0_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT0_PHASE must range from -360000 to 360000");
end
if (CLKOUT1_PHASE < -'sd360000 || CLKOUT1_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT1_PHASE must range from -360000 to 360000");
end
if (CLKOUT2_PHASE < -'sd360000 || CLKOUT2_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT2_PHASE must range from -360000 to 360000");
end
if (CLKOUT3_PHASE < -'sd360000 || CLKOUT3_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT3_PHASE must range from -360000 to 360000");
end
if (CLKOUT4_PHASE < -'sd360000 || CLKOUT4_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT4_PHASE must range from -360000 to 360000");
end
if (CLKOUT5_PHASE < -'sd360000 || CLKOUT5_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT5_PHASE must range from -360000 to 360000");
end
if (CLKOUT6_PHASE < -'sd360000 || CLKOUT6_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT6_PHASE must range from -360000 to 360000");
end
if (CLKOUT0_DUTY_CYCLE < 1000 || CLKOUT0_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT0_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT1_DUTY_CYCLE < 1000 || CLKOUT1_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT1_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT2_DUTY_CYCLE < 1000 || CLKOUT2_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT2_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT3_DUTY_CYCLE < 1000 || CLKOUT3_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT3_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT4_DUTY_CYCLE < 1000 || CLKOUT4_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT4_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT5_DUTY_CYCLE < 1000 || CLKOUT5_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT5_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT6_DUTY_CYCLE < 1000 || CLKOUT6_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT6_DUTY_CYCLE must range from 1000 to 99000");
end
if (SS_EN != "TRUE" && SS_EN != "FALSE") begin
wire _TECHMAP_FAIL_;
$error("SS_EN must be either 'TRUE' or 'FALSE'");
end
if (SS_MODE != "DOWN_LOW" && SS_MODE != "DOWN_HIGH" && SS_MODE != "CENTER_LOW" && SS_MODE != "CENTER_HIGH") begin
wire _TECHMAP_FAIL_;
$error("SS_MODE must be one of: 'DOWN_LOW', 'DOWN_HIGH', 'CENTER_LOW', 'CENTER_HIGH'");
end
if (SS_MOD_PERIOD < 4000 || SS_MOD_PERIOD > 40000) begin
wire _TECHMAP_FAIL_;
$error("SS_MOD_PERIOD must range from 4000 to 40000");
end
// Round fractional dividers to multiples of 1/8.
// (125 / 2 = 62.5)
localparam CLKFBOUT_MULT_R = ((CLKFBOUT_MULT_F + 62) / 125) * 125;
localparam CLKOUT0_DIVIDE_R = ((CLKOUT0_DIVIDE_F + 62) / 125) * 125;
// Compute integer multipliers needed later for look-up tables
localparam CLKFBOUT_MULT = CLKFBOUT_MULT_R / 1000;
localparam CLKOUT0_DIVIDE = CLKOUT0_DIVIDE_R / 1000;
// Check whether fractional divider needs to be enabled on CLKFBOUT and
// CLKOUT0
localparam CLKFBOUT_FRAC_EN = (CLKFBOUT_MULT_R % 1000) != 0;
localparam CLKOUT0_FRAC_EN = (CLKOUT0_DIVIDE_R % 1000) != 0;
if (CLKOUT0_FRAC_EN && CLKOUT0_DUTY_CYCLE != 50000) begin
wire _TECHMAP_FAIL_;
$error("When CLKOUT0 uses fractional divider the duty cycle must be 50%");
end
// Check whether phase shift of CLKFBOUT and CLKOUT0 is a multiple of 45 deg.
// This is needed for determining content of POWER_REG.
localparam CLKFBOUT_PHASE_45 = (CLKFBOUT_PHASE % 45000) == 0;
localparam CLKOUT0_PHASE_45 = (CLKOUT0_PHASE % 45000) == 0;
// Handle registers controling fractional dividers
localparam CLKFBOUT_CALC = mmcm_clkregs(CLKFBOUT_MULT, 50000, CLKFBOUT_PHASE);
localparam CLKOUT0_CALC = mmcm_clkregs(CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, CLKOUT0_PHASE);
localparam CLKOUT5_CALC = mmcm_clkregs(CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE);
localparam CLKOUT6_CALC = mmcm_clkregs(CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, CLKOUT6_PHASE);
localparam CLKFBOUT_FRAC_CALC = mmcm_clkregs_frac(CLKFBOUT_MULT_R, 50000, CLKFBOUT_PHASE);
localparam CLKOUT0_FRAC_CALC = mmcm_clkregs_frac(CLKOUT0_DIVIDE_R, 50000, CLKOUT0_PHASE);
// Compute PLL's registers content
//
// When no fractional divider is enabled use the *_CALC content.
// For fractional divider use *_FRAC_CALC content but tak the "EDGE" bit
// from *_CALC. This is not documented in XAPP888 but has been observed in
// vendor tools.
//
// Additional part of *_FRAC_CALC data needs to end up in bits of
// CLKOUT5_REGS and CLKOUT6_REGS.
localparam CLKFBOUT_REGS = (CLKFBOUT_FRAC_EN) ? (CLKFBOUT_FRAC_CALC[31:0] | (CLKFBOUT_CALC[23] << 23)): CLKFBOUT_CALC;
localparam DIVCLK_REGS = mmcm_clkregs(DIVCLK_DIVIDE, 50000, 0);
localparam CLKOUT0_REGS = (CLKOUT0_FRAC_EN) ? (CLKOUT0_FRAC_CALC[31:0] | (CLKOUT0_CALC[23] << 23)): CLKOUT0_CALC;
localparam CLKOUT1_REGS = mmcm_clkregs(CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, CLKOUT1_PHASE);
localparam CLKOUT2_REGS = mmcm_clkregs(CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, CLKOUT2_PHASE);
localparam CLKOUT3_REGS = mmcm_clkregs(CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, CLKOUT3_PHASE);
localparam CLKOUT4_REGS = mmcm_clkregs(CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, CLKOUT4_PHASE);
// Substitute the shared part of CLKOUT5 and CLKOUT6 regs with data for
// CLKOUT0 and CLKFBOUT when factional divider is used for either of them.
//
// Additionaly copy the PHASE_MUX field to the PHASE_MUX_F fiels when
// fractional divider is not used. This behavior is not documented in
// XAPP888 but has been observed.
localparam CLKOUT5_REGS = (CLKOUT0_FRAC_EN) ? {CLKOUT5_CALC[31:30], CLKOUT0_FRAC_CALC[35:32], CLKOUT5_CALC[25:0]} :
{CLKOUT5_CALC[31:30], CLKOUT0_CALC[15:13], CLKOUT5_CALC[26:0]};
localparam CLKOUT6_REGS = (CLKFBOUT_FRAC_EN) ? {CLKOUT6_CALC[31:30], CLKFBOUT_FRAC_CALC[35:32], CLKOUT6_CALC[25:0]} :
{CLKOUT6_CALC[31:30], CLKFBOUT_CALC[15:13], CLKOUT6_CALC[26:0]};
// Handle inputs that should have certain logic levels when left unconnected
localparam INV_CLKINSEL = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? !_TECHMAP_CONSTVAL_CLKINSEL_ : IS_CLKINSEL_INVERTED;
wire clkinsel = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKINSEL_ == 0) ? 1'b1 :
CLKINSEL;
localparam INV_PWRDWN = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? !_TECHMAP_CONSTVAL_PWRDWN_ :
(_TECHMAP_CONSTVAL_PWRDWN_ == 0) ? ~IS_PWRDWN_INVERTED :
IS_PWRDWN_INVERTED;
wire pwrdwn = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PWRDWN_ == 0) ? 1'b1 : PWRDWN;
localparam INV_RST = (_TECHMAP_CONSTMSK_RST_ == 1) ? !_TECHMAP_CONSTVAL_RST_ :
(_TECHMAP_CONSTVAL_RST_ == 0) ? ~IS_RST_INVERTED :
IS_RST_INVERTED;
wire rst = (_TECHMAP_CONSTMSK_RST_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RST_ == 0) ? 1'b1 : RST;
wire dclk = (_TECHMAP_CONSTMSK_DCLK_ == 1) ? _TECHMAP_CONSTVAL_DCLK_ :
(_TECHMAP_CONSTVAL_DCLK_ == 0) ? 1'b0 : DCLK;
wire den = (_TECHMAP_CONSTMSK_DEN_ == 1) ? _TECHMAP_CONSTVAL_DEN_ :
(_TECHMAP_CONSTVAL_DEN_ == 0) ? 1'b0 : DEN;
wire dwe = (_TECHMAP_CONSTMSK_DWE_ == 1) ? _TECHMAP_CONSTVAL_DWE_ :
(_TECHMAP_CONSTVAL_DWE_ == 0) ? 1'b0 : DWE;
wire psclk = (_TECHMAP_CONSTMSK_PSCLK_ == 1) ? _TECHMAP_CONSTVAL_PSCLK_ :
(_TECHMAP_CONSTVAL_PSCLK_ == 0) ? 1'b0 : PSCLK;
localparam INV_PSEN = (_TECHMAP_CONSTMSK_PSEN_ == 1) ? !_TECHMAP_CONSTVAL_PSEN_ :
(_TECHMAP_CONSTVAL_PSEN_ == 0) ? ~IS_PSEN_INVERTED :
IS_PSEN_INVERTED;
wire psen = (_TECHMAP_CONSTMSK_PSEN_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PSEN_ == 0) ? 1'b1 : PSEN;
localparam INV_PSINCDEC = (_TECHMAP_CONSTMSK_PSINCDEC_ == 1) ? !_TECHMAP_CONSTVAL_PSINCDEC_ :
(_TECHMAP_CONSTVAL_PSINCDEC_ == 0) ? ~IS_PSINCDEC_INVERTED :
IS_PSINCDEC_INVERTED;
wire psincdec = (_TECHMAP_CONSTMSK_PSINCDEC_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PSINCDEC_ == 0) ? 1'b1 : PSINCDEC;
// The substituted cell
MMCME2_ADV_VPR #
(
// Inverters
.INV_CLKINSEL (INV_CLKINSEL),
.ZINV_PWRDWN (INV_PWRDWN),
.ZINV_RST (INV_RST),
.ZINV_PSEN (INV_PSEN),
.ZINV_PSINCDEC (INV_PSINCDEC),
// Compensation
.COMP_ZHOLD (COMPENSATION == "ZHOLD"),
.COMP_Z_ZHOLD (COMPENSATION != "ZHOLD"),
// Spread spectrum
.SS_EN (1'b0), // TODO: Disable for now
// Straight mapped parameters
.STARTUP_WAIT(STARTUP_WAIT == "TRUE"),
// Lookup tables
.LKTABLE(mmcm_lktable_lookup(CLKFBOUT_MULT)),
.TABLE(mmcm_table_lookup(CLKFBOUT_MULT, BANDWIDTH, (SS_EN == "TRUE"))),
// FIXME: How to compute values the two below ?
.FILTREG1_RESERVED(12'b0000_00001000),
.LOCKREG3_RESERVED(1'b1),
// Clock feedback settings
.CLKFBOUT_CLKOUT1_HIGH_TIME (CLKFBOUT_REGS[11:6]),
.CLKFBOUT_CLKOUT1_LOW_TIME (CLKFBOUT_REGS[5:0]),
.CLKFBOUT_CLKOUT1_PHASE_MUX (CLKFBOUT_REGS[15:13]),
.CLKFBOUT_CLKOUT2_DELAY_TIME (CLKFBOUT_REGS[21:16]),
.CLKFBOUT_CLKOUT2_EDGE (CLKFBOUT_REGS[23]),
.CLKFBOUT_CLKOUT2_FRAC (CLKFBOUT_REGS[30:28]),
.CLKFBOUT_CLKOUT2_FRAC_EN (CLKFBOUT_REGS[27]),
.CLKFBOUT_CLKOUT2_FRAC_WF_R (CLKFBOUT_REGS[26]),
.CLKFBOUT_CLKOUT2_NO_COUNT (CLKFBOUT_REGS[22]),
// Internal VCO divider settings
.DIVCLK_DIVCLK_HIGH_TIME (DIVCLK_REGS[11:6]),
.DIVCLK_DIVCLK_LOW_TIME (DIVCLK_REGS[5:0]),
.DIVCLK_DIVCLK_NO_COUNT (DIVCLK_REGS[22]),
.DIVCLK_DIVCLK_EDGE (DIVCLK_REGS[23]),
// CLKOUT0
.CLKOUT0_CLKOUT1_HIGH_TIME (CLKOUT0_REGS[11:6]),
.CLKOUT0_CLKOUT1_LOW_TIME (CLKOUT0_REGS[5:0]),
.CLKOUT0_CLKOUT1_PHASE_MUX (CLKOUT0_REGS[15:13]),
.CLKOUT0_CLKOUT2_DELAY_TIME (CLKOUT0_REGS[21:16]),
.CLKOUT0_CLKOUT2_EDGE (CLKOUT0_REGS[23]),
.CLKOUT0_CLKOUT2_FRAC (CLKOUT0_REGS[30:28]),
.CLKOUT0_CLKOUT2_FRAC_EN (CLKOUT0_REGS[27]),
.CLKOUT0_CLKOUT2_FRAC_WF_R (CLKOUT0_REGS[26]),
.CLKOUT0_CLKOUT2_NO_COUNT (CLKOUT0_REGS[22]),
// CLKOUT1
.CLKOUT1_CLKOUT1_HIGH_TIME (CLKOUT1_REGS[11:6]),
.CLKOUT1_CLKOUT1_LOW_TIME (CLKOUT1_REGS[5:0]),
.CLKOUT1_CLKOUT1_PHASE_MUX (CLKOUT1_REGS[15:13]),
.CLKOUT1_CLKOUT2_DELAY_TIME (CLKOUT1_REGS[21:16]),
.CLKOUT1_CLKOUT2_EDGE (CLKOUT1_REGS[23]),
.CLKOUT1_CLKOUT2_NO_COUNT (CLKOUT1_REGS[22]),
// CLKOUT2
.CLKOUT2_CLKOUT1_HIGH_TIME (CLKOUT2_REGS[11:6]),
.CLKOUT2_CLKOUT1_LOW_TIME (CLKOUT2_REGS[5:0]),
.CLKOUT2_CLKOUT1_PHASE_MUX (CLKOUT2_REGS[15:13]),
.CLKOUT2_CLKOUT2_DELAY_TIME (CLKOUT2_REGS[21:16]),
.CLKOUT2_CLKOUT2_EDGE (CLKOUT2_REGS[23]),
.CLKOUT2_CLKOUT2_NO_COUNT (CLKOUT2_REGS[22]),
// CLKOUT3
.CLKOUT3_CLKOUT1_HIGH_TIME (CLKOUT3_REGS[11:6]),
.CLKOUT3_CLKOUT1_LOW_TIME (CLKOUT3_REGS[5:0]),
.CLKOUT3_CLKOUT1_PHASE_MUX (CLKOUT3_REGS[15:13]),
.CLKOUT3_CLKOUT2_DELAY_TIME (CLKOUT3_REGS[21:16]),
.CLKOUT3_CLKOUT2_EDGE (CLKOUT3_REGS[23]),
.CLKOUT3_CLKOUT2_NO_COUNT (CLKOUT3_REGS[22]),
// CLKOUT4
.CLKOUT4_CLKOUT1_HIGH_TIME (CLKOUT4_REGS[11:6]),
.CLKOUT4_CLKOUT1_LOW_TIME (CLKOUT4_REGS[5:0]),
.CLKOUT4_CLKOUT1_PHASE_MUX (CLKOUT4_REGS[15:13]),
.CLKOUT4_CLKOUT2_DELAY_TIME (CLKOUT4_REGS[21:16]),
.CLKOUT4_CLKOUT2_EDGE (CLKOUT4_REGS[23]),
.CLKOUT4_CLKOUT2_NO_COUNT (CLKOUT4_REGS[22]),
// CLKOUT5
.CLKOUT5_CLKOUT1_HIGH_TIME (CLKOUT5_REGS[11:6]),
.CLKOUT5_CLKOUT1_LOW_TIME (CLKOUT5_REGS[5:0]),
.CLKOUT5_CLKOUT1_PHASE_MUX (CLKOUT5_REGS[15:13]),
.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME (CLKOUT5_REGS[21:16]),
.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE (CLKOUT5_REGS[23]),
.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT (CLKOUT5_REGS[22]),
.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F (CLKOUT5_REGS[29:27]),
.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F (CLKOUT5_REGS[26]),
// CLKOUT6
.CLKOUT6_CLKOUT1_HIGH_TIME (CLKOUT6_REGS[11:6]),
.CLKOUT6_CLKOUT1_LOW_TIME (CLKOUT6_REGS[5:0]),
.CLKOUT6_CLKOUT1_PHASE_MUX (CLKOUT6_REGS[15:13]),
.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME (CLKOUT6_REGS[21:16]),
.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE (CLKOUT6_REGS[23]),
.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT (CLKOUT6_REGS[22]),
.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F (CLKOUT6_REGS[29:27]),
.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F (CLKOUT6_REGS[26]),
// POWER_REG
// FIXME: Check whether this is always thar same content. XAPP888 says that
// "all the bits should be set when performing DRP". The values below has
// been observed to be used by vendor tools in some circumstances.
.POWER_REG ((CLKFBOUT_FRAC_EN || CLKOUT0_FRAC_EN || !CLKOUT0_PHASE_45) ? 16'b10011001_00000000 :
16'b00000001_00000000),
// Clock output enable controls
.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKFBOUT_ === 1'bX || _TECHMAP_CONSTVAL_CLKFBOUTB_ === 1'bX),
.CLKOUT0_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT0_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT0B_ === 1'bX),
.CLKOUT1_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT1_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT1B_ === 1'bX),
.CLKOUT2_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT2_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT2B_ === 1'bX),
.CLKOUT3_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT3_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT3B_ === 1'bX),
.CLKOUT4_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT4_ === 1'bX),
.CLKOUT5_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT5_ === 1'bX),
.CLKOUT6_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT6_ === 1'bX)
)
_TECHMAP_REPLACE_
(
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN1),
.CLKIN2 (CLKIN2),
.CLKINSEL (clkinsel),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.CLKINSTOPPED (CLKINSTOPPED),
.CLKFBSTOPPED (CLKFBSTOPPED),
.PWRDWN (pwrdwn),
.RST (rst),
.LOCKED (LOCKED),
.PSCLK (psclk),
.PSEN (psen),
.PSINCDEC (psincdec),
.PSDONE (PSDONE),
.DCLK (dclk),
.DEN (den),
.DWE (dwe),
.DRDY (DRDY),
.DADDR0 (DADDR[0]),
.DADDR1 (DADDR[1]),
.DADDR2 (DADDR[2]),
.DADDR3 (DADDR[3]),
.DADDR4 (DADDR[4]),
.DADDR5 (DADDR[5]),
.DADDR6 (DADDR[6]),
.DI0 (DI[0]),
.DI1 (DI[1]),
.DI2 (DI[2]),
.DI3 (DI[3]),
.DI4 (DI[4]),
.DI5 (DI[5]),
.DI6 (DI[6]),
.DI7 (DI[7]),
.DI8 (DI[8]),
.DI9 (DI[9]),
.DI10 (DI[10]),
.DI11 (DI[11]),
.DI12 (DI[12]),
.DI13 (DI[13]),
.DI14 (DI[14]),
.DI15 (DI[15]),
.DO0 (DO[0]),
.DO1 (DO[1]),
.DO2 (DO[2]),
.DO3 (DO[3]),
.DO4 (DO[4]),
.DO5 (DO[5]),
.DO6 (DO[6]),
.DO7 (DO[7]),
.DO8 (DO[8]),
.DO9 (DO[9]),
.DO10 (DO[10]),
.DO11 (DO[11]),
.DO12 (DO[12]),
.DO13 (DO[13]),
.DO14 (DO[14]),
.DO15 (DO[15])
);
endmodule
// ============================================================================
module INV(
output O,
input I
);
LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.O(O), .I0(I));
endmodule
// ============================================================================
// The Zynq PS7
module PS7 (
inout [14: 0] DDRA,
input [ 3: 0] DDRARB,
inout [ 2: 0] DDRBA,
inout DDRCASB,
inout DDRCKE,
inout DDRCKN,
inout DDRCKP,
inout DDRCSB,
inout [ 3: 0] DDRDM,
inout [31: 0] DDRDQ,
inout [ 3: 0] DDRDQSN,
inout [ 3: 0] DDRDQSP,
inout DDRDRSTB,
inout DDRODT,
inout DDRRASB,
inout DDRVRN,
inout DDRVRP,
inout DDRWEB,
input DMA0ACLK,
input DMA0DAREADY,
output [ 1: 0] DMA0DATYPE,
output DMA0DAVALID,
input DMA0DRLAST,
output DMA0DRREADY,
input [ 1: 0] DMA0DRTYPE,
input DMA0DRVALID,
output DMA0RSTN,
input DMA1ACLK,
input DMA1DAREADY,
output [ 1: 0] DMA1DATYPE,
output DMA1DAVALID,
input DMA1DRLAST,
output DMA1DRREADY,
input [ 1: 0] DMA1DRTYPE,
input DMA1DRVALID,
output DMA1RSTN,
input DMA2ACLK,
input DMA2DAREADY,
output [ 1: 0] DMA2DATYPE,
output DMA2DAVALID,
input DMA2DRLAST,
output DMA2DRREADY,
input [ 1: 0] DMA2DRTYPE,
input DMA2DRVALID,
output DMA2RSTN,
input DMA3ACLK,
input DMA3DAREADY,
output [ 1: 0] DMA3DATYPE,
output DMA3DAVALID,
input DMA3DRLAST,
output DMA3DRREADY,
input [ 1: 0] DMA3DRTYPE,
input DMA3DRVALID,
output DMA3RSTN,
input EMIOCAN0PHYRX,
output EMIOCAN0PHYTX,
input EMIOCAN1PHYRX,
output EMIOCAN1PHYTX,
input EMIOENET0EXTINTIN,
input EMIOENET0GMIICOL,
input EMIOENET0GMIICRS,
input EMIOENET0GMIIRXCLK,
input [ 7: 0] EMIOENET0GMIIRXD,
input EMIOENET0GMIIRXDV,
input EMIOENET0GMIIRXER,
input EMIOENET0GMIITXCLK,
output [ 7: 0] EMIOENET0GMIITXD,
output EMIOENET0GMIITXEN,
output EMIOENET0GMIITXER,
input EMIOENET0MDIOI,
output EMIOENET0MDIOMDC,
output EMIOENET0MDIOO,
output EMIOENET0MDIOTN,
output EMIOENET0PTPDELAYREQRX,
output EMIOENET0PTPDELAYREQTX,
output EMIOENET0PTPPDELAYREQRX,
output EMIOENET0PTPPDELAYREQTX,
output EMIOENET0PTPPDELAYRESPRX,
output EMIOENET0PTPPDELAYRESPTX,
output EMIOENET0PTPSYNCFRAMERX,
output EMIOENET0PTPSYNCFRAMETX,
output EMIOENET0SOFRX,
output EMIOENET0SOFTX,
input EMIOENET1EXTINTIN,
input EMIOENET1GMIICOL,
input EMIOENET1GMIICRS,
input EMIOENET1GMIIRXCLK,
input [ 7: 0] EMIOENET1GMIIRXD,
input EMIOENET1GMIIRXDV,
input EMIOENET1GMIIRXER,
input EMIOENET1GMIITXCLK,
output [ 7: 0] EMIOENET1GMIITXD,
output EMIOENET1GMIITXEN,
output EMIOENET1GMIITXER,
input EMIOENET1MDIOI,
output EMIOENET1MDIOMDC,
output EMIOENET1MDIOO,
output EMIOENET1MDIOTN,
output EMIOENET1PTPDELAYREQRX,
output EMIOENET1PTPDELAYREQTX,
output EMIOENET1PTPPDELAYREQRX,
output EMIOENET1PTPPDELAYREQTX,
output EMIOENET1PTPPDELAYRESPRX,
output EMIOENET1PTPPDELAYRESPTX,
output EMIOENET1PTPSYNCFRAMERX,
output EMIOENET1PTPSYNCFRAMETX,
output EMIOENET1SOFRX,
output EMIOENET1SOFTX,
input [63: 0] EMIOGPIOI,
output [63: 0] EMIOGPIOO,
output [63: 0] EMIOGPIOTN,
input EMIOI2C0SCLI,
output EMIOI2C0SCLO,
output EMIOI2C0SCLTN,
input EMIOI2C0SDAI,
output EMIOI2C0SDAO,
output EMIOI2C0SDATN,
input EMIOI2C1SCLI,
output EMIOI2C1SCLO,
output EMIOI2C1SCLTN,
input EMIOI2C1SDAI,
output EMIOI2C1SDAO,
output EMIOI2C1SDATN,
input EMIOPJTAGTCK,
input EMIOPJTAGTDI,
output EMIOPJTAGTDO,
output EMIOPJTAGTDTN,
input EMIOPJTAGTMS,
output EMIOSDIO0BUSPOW,
output [ 2: 0] EMIOSDIO0BUSVOLT,
input EMIOSDIO0CDN,
output EMIOSDIO0CLK,
input EMIOSDIO0CLKFB,
input EMIOSDIO0CMDI,
output EMIOSDIO0CMDO,
output EMIOSDIO0CMDTN,
input [ 3: 0] EMIOSDIO0DATAI,
output [ 3: 0] EMIOSDIO0DATAO,
output [ 3: 0] EMIOSDIO0DATATN,
output EMIOSDIO0LED,
input EMIOSDIO0WP,
output EMIOSDIO1BUSPOW,
output [ 2: 0] EMIOSDIO1BUSVOLT,
input EMIOSDIO1CDN,
output EMIOSDIO1CLK,
input EMIOSDIO1CLKFB,
input EMIOSDIO1CMDI,
output EMIOSDIO1CMDO,
output EMIOSDIO1CMDTN,
input [ 3: 0] EMIOSDIO1DATAI,
output [ 3: 0] EMIOSDIO1DATAO,
output [ 3: 0] EMIOSDIO1DATATN,
output EMIOSDIO1LED,
input EMIOSDIO1WP,
input EMIOSPI0MI,
output EMIOSPI0MO,
output EMIOSPI0MOTN,
input EMIOSPI0SCLKI,
output EMIOSPI0SCLKO,
output EMIOSPI0SCLKTN,
input EMIOSPI0SI,
output EMIOSPI0SO,
input EMIOSPI0SSIN,
output EMIOSPI0SSNTN,
output [ 2: 0] EMIOSPI0SSON,
output EMIOSPI0STN,
input EMIOSPI1MI,
output EMIOSPI1MO,
output EMIOSPI1MOTN,
input EMIOSPI1SCLKI,
output EMIOSPI1SCLKO,
output EMIOSPI1SCLKTN,
input EMIOSPI1SI,
output EMIOSPI1SO,
input EMIOSPI1SSIN,
output EMIOSPI1SSNTN,
output [ 2: 0] EMIOSPI1SSON,
output EMIOSPI1STN,
input EMIOSRAMINTIN,
input EMIOTRACECLK,
output EMIOTRACECTL,
output [31: 0] EMIOTRACEDATA,
input [ 2: 0] EMIOTTC0CLKI,
output [ 2: 0] EMIOTTC0WAVEO,
input [ 2: 0] EMIOTTC1CLKI,
output [ 2: 0] EMIOTTC1WAVEO,
input EMIOUART0CTSN,
input EMIOUART0DCDN,
input EMIOUART0DSRN,
output EMIOUART0DTRN,
input EMIOUART0RIN,
output EMIOUART0RTSN,
input EMIOUART0RX,
output EMIOUART0TX,
input EMIOUART1CTSN,
input EMIOUART1DCDN,
input EMIOUART1DSRN,
output EMIOUART1DTRN,
input EMIOUART1RIN,
output EMIOUART1RTSN,
input EMIOUART1RX,
output EMIOUART1TX,
output [ 1: 0] EMIOUSB0PORTINDCTL,
input EMIOUSB0VBUSPWRFAULT,
output EMIOUSB0VBUSPWRSELECT,
output [ 1: 0] EMIOUSB1PORTINDCTL,
input EMIOUSB1VBUSPWRFAULT,
output EMIOUSB1VBUSPWRSELECT,
input EMIOWDTCLKI,
output EMIOWDTRSTO,
input EVENTEVENTI,
output EVENTEVENTO,
output [ 1: 0] EVENTSTANDBYWFE,
output [ 1: 0] EVENTSTANDBYWFI,
output [ 3: 0] FCLKCLK,
input [ 3: 0] FCLKCLKTRIGN,
output [ 3: 0] FCLKRESETN,
input FPGAIDLEN,
input [ 3: 0] FTMDTRACEINATID,
input FTMDTRACEINCLOCK,
input [31: 0] FTMDTRACEINDATA,
input FTMDTRACEINVALID,
input [31: 0] FTMTF2PDEBUG,
input [ 3: 0] FTMTF2PTRIG,
output [ 3: 0] FTMTF2PTRIGACK,
output [31: 0] FTMTP2FDEBUG,
output [ 3: 0] FTMTP2FTRIG,
input [ 3: 0] FTMTP2FTRIGACK,
input [19: 0] IRQF2P,
output [28: 0] IRQP2F,
input MAXIGP0ACLK,
output [31: 0] MAXIGP0ARADDR,
output [ 1: 0] MAXIGP0ARBURST,
output [ 3: 0] MAXIGP0ARCACHE,
output MAXIGP0ARESETN,
output [11: 0] MAXIGP0ARID,
output [ 3: 0] MAXIGP0ARLEN,
output [ 1: 0] MAXIGP0ARLOCK,
output [ 2: 0] MAXIGP0ARPROT,
output [ 3: 0] MAXIGP0ARQOS,
input MAXIGP0ARREADY,
output [ 1: 0] MAXIGP0ARSIZE,
output MAXIGP0ARVALID,
output [31: 0] MAXIGP0AWADDR,
output [ 1: 0] MAXIGP0AWBURST,
output [ 3: 0] MAXIGP0AWCACHE,
output [11: 0] MAXIGP0AWID,
output [ 3: 0] MAXIGP0AWLEN,
output [ 1: 0] MAXIGP0AWLOCK,
output [ 2: 0] MAXIGP0AWPROT,
output [ 3: 0] MAXIGP0AWQOS,
input MAXIGP0AWREADY,
output [ 1: 0] MAXIGP0AWSIZE,
output MAXIGP0AWVALID,
input [11: 0] MAXIGP0BID,
output MAXIGP0BREADY,
input [ 1: 0] MAXIGP0BRESP,
input MAXIGP0BVALID,
input [31: 0] MAXIGP0RDATA,
input [11: 0] MAXIGP0RID,
input MAXIGP0RLAST,
output MAXIGP0RREADY,
input [ 1: 0] MAXIGP0RRESP,
input MAXIGP0RVALID,
output [31: 0] MAXIGP0WDATA,
output [11: 0] MAXIGP0WID,
output MAXIGP0WLAST,
input MAXIGP0WREADY,
output [ 3: 0] MAXIGP0WSTRB,
output MAXIGP0WVALID,
input MAXIGP1ACLK,
output [31: 0] MAXIGP1ARADDR,
output [ 1: 0] MAXIGP1ARBURST,
output [ 3: 0] MAXIGP1ARCACHE,
output MAXIGP1ARESETN,
output [11: 0] MAXIGP1ARID,
output [ 3: 0] MAXIGP1ARLEN,
output [ 1: 0] MAXIGP1ARLOCK,
output [ 2: 0] MAXIGP1ARPROT,
output [ 3: 0] MAXIGP1ARQOS,
input MAXIGP1ARREADY,
output [ 1: 0] MAXIGP1ARSIZE,
output MAXIGP1ARVALID,
output [31: 0] MAXIGP1AWADDR,
output [ 1: 0] MAXIGP1AWBURST,
output [ 3: 0] MAXIGP1AWCACHE,
output [11: 0] MAXIGP1AWID,
output [ 3: 0] MAXIGP1AWLEN,
output [ 1: 0] MAXIGP1AWLOCK,
output [ 2: 0] MAXIGP1AWPROT,
output [ 3: 0] MAXIGP1AWQOS,
input MAXIGP1AWREADY,
output [ 1: 0] MAXIGP1AWSIZE,
output MAXIGP1AWVALID,
input [11: 0] MAXIGP1BID,
output MAXIGP1BREADY,
input [ 1: 0] MAXIGP1BRESP,
input MAXIGP1BVALID,
input [31: 0] MAXIGP1RDATA,
input [11: 0] MAXIGP1RID,
input MAXIGP1RLAST,
output MAXIGP1RREADY,
input [ 1: 0] MAXIGP1RRESP,
input MAXIGP1RVALID,
output [31: 0] MAXIGP1WDATA,
output [11: 0] MAXIGP1WID,
output MAXIGP1WLAST,
input MAXIGP1WREADY,
output [ 3: 0] MAXIGP1WSTRB,
output MAXIGP1WVALID,
inout [53: 0] MIO,
inout PSCLK,
inout PSPORB,
inout PSSRSTB,
input SAXIACPACLK,
input [31: 0] SAXIACPARADDR,
input [ 1: 0] SAXIACPARBURST,
input [ 3: 0] SAXIACPARCACHE,
output SAXIACPARESETN,
input [ 2: 0] SAXIACPARID,
input [ 3: 0] SAXIACPARLEN,
input [ 1: 0] SAXIACPARLOCK,
input [ 2: 0] SAXIACPARPROT,
input [ 3: 0] SAXIACPARQOS,
output SAXIACPARREADY,
input [ 1: 0] SAXIACPARSIZE,
input [ 4: 0] SAXIACPARUSER,
input SAXIACPARVALID,
input [31: 0] SAXIACPAWADDR,
input [ 1: 0] SAXIACPAWBURST,
input [ 3: 0] SAXIACPAWCACHE,
input [ 2: 0] SAXIACPAWID,
input [ 3: 0] SAXIACPAWLEN,
input [ 1: 0] SAXIACPAWLOCK,
input [ 2: 0] SAXIACPAWPROT,
input [ 3: 0] SAXIACPAWQOS,
output SAXIACPAWREADY,
input [ 1: 0] SAXIACPAWSIZE,
input [ 4: 0] SAXIACPAWUSER,
input SAXIACPAWVALID,
output [ 2: 0] SAXIACPBID,
input SAXIACPBREADY,
output [ 1: 0] SAXIACPBRESP,
output SAXIACPBVALID,
output [63: 0] SAXIACPRDATA,
output [ 2: 0] SAXIACPRID,
output SAXIACPRLAST,
input SAXIACPRREADY,
output [ 1: 0] SAXIACPRRESP,
output SAXIACPRVALID,
input [63: 0] SAXIACPWDATA,
input [ 2: 0] SAXIACPWID,
input SAXIACPWLAST,
output SAXIACPWREADY,
input [ 7: 0] SAXIACPWSTRB,
input SAXIACPWVALID,
input SAXIGP0ACLK,
input [31: 0] SAXIGP0ARADDR,
input [ 1: 0] SAXIGP0ARBURST,
input [ 3: 0] SAXIGP0ARCACHE,
output SAXIGP0ARESETN,
input [ 5: 0] SAXIGP0ARID,
input [ 3: 0] SAXIGP0ARLEN,
input [ 1: 0] SAXIGP0ARLOCK,
input [ 2: 0] SAXIGP0ARPROT,
input [ 3: 0] SAXIGP0ARQOS,
output SAXIGP0ARREADY,
input [ 1: 0] SAXIGP0ARSIZE,
input SAXIGP0ARVALID,
input [31: 0] SAXIGP0AWADDR,
input [ 1: 0] SAXIGP0AWBURST,
input [ 3: 0] SAXIGP0AWCACHE,
input [ 5: 0] SAXIGP0AWID,
input [ 3: 0] SAXIGP0AWLEN,
input [ 1: 0] SAXIGP0AWLOCK,
input [ 2: 0] SAXIGP0AWPROT,
input [ 3: 0] SAXIGP0AWQOS,
output SAXIGP0AWREADY,
input [ 1: 0] SAXIGP0AWSIZE,
input SAXIGP0AWVALID,
output [ 5: 0] SAXIGP0BID,
input SAXIGP0BREADY,
output [ 1: 0] SAXIGP0BRESP,
output SAXIGP0BVALID,
output [31: 0] SAXIGP0RDATA,
output [ 5: 0] SAXIGP0RID,
output SAXIGP0RLAST,
input SAXIGP0RREADY,
output [ 1: 0] SAXIGP0RRESP,
output SAXIGP0RVALID,
input [31: 0] SAXIGP0WDATA,
input [ 5: 0] SAXIGP0WID,
input SAXIGP0WLAST,
output SAXIGP0WREADY,
input [ 3: 0] SAXIGP0WSTRB,
input SAXIGP0WVALID,
input SAXIGP1ACLK,
input [31: 0] SAXIGP1ARADDR,
input [ 1: 0] SAXIGP1ARBURST,
input [ 3: 0] SAXIGP1ARCACHE,
output SAXIGP1ARESETN,
input [ 5: 0] SAXIGP1ARID,
input [ 3: 0] SAXIGP1ARLEN,
input [ 1: 0] SAXIGP1ARLOCK,
input [ 2: 0] SAXIGP1ARPROT,
input [ 3: 0] SAXIGP1ARQOS,
output SAXIGP1ARREADY,
input [ 1: 0] SAXIGP1ARSIZE,
input SAXIGP1ARVALID,
input [31: 0] SAXIGP1AWADDR,
input [ 1: 0] SAXIGP1AWBURST,
input [ 3: 0] SAXIGP1AWCACHE,
input [ 5: 0] SAXIGP1AWID,
input [ 3: 0] SAXIGP1AWLEN,
input [ 1: 0] SAXIGP1AWLOCK,
input [ 2: 0] SAXIGP1AWPROT,
input [ 3: 0] SAXIGP1AWQOS,
output SAXIGP1AWREADY,
input [ 1: 0] SAXIGP1AWSIZE,
input SAXIGP1AWVALID,
output [ 5: 0] SAXIGP1BID,
input SAXIGP1BREADY,
output [ 1: 0] SAXIGP1BRESP,
output SAXIGP1BVALID,
output [31: 0] SAXIGP1RDATA,
output [ 5: 0] SAXIGP1RID,
output SAXIGP1RLAST,
input SAXIGP1RREADY,
output [ 1: 0] SAXIGP1RRESP,
output SAXIGP1RVALID,
input [31: 0] SAXIGP1WDATA,
input [ 5: 0] SAXIGP1WID,
input SAXIGP1WLAST,
output SAXIGP1WREADY,
input [ 3: 0] SAXIGP1WSTRB,
input SAXIGP1WVALID,
input SAXIHP0ACLK,
input [31: 0] SAXIHP0ARADDR,
input [ 1: 0] SAXIHP0ARBURST,
input [ 3: 0] SAXIHP0ARCACHE,
output SAXIHP0ARESETN,
input [ 5: 0] SAXIHP0ARID,
input [ 3: 0] SAXIHP0ARLEN,
input [ 1: 0] SAXIHP0ARLOCK,
input [ 2: 0] SAXIHP0ARPROT,
input [ 3: 0] SAXIHP0ARQOS,
output SAXIHP0ARREADY,
input [ 1: 0] SAXIHP0ARSIZE,
input SAXIHP0ARVALID,
input [31: 0] SAXIHP0AWADDR,
input [ 1: 0] SAXIHP0AWBURST,
input [ 3: 0] SAXIHP0AWCACHE,
input [ 5: 0] SAXIHP0AWID,
input [ 3: 0] SAXIHP0AWLEN,
input [ 1: 0] SAXIHP0AWLOCK,
input [ 2: 0] SAXIHP0AWPROT,
input [ 3: 0] SAXIHP0AWQOS,
output SAXIHP0AWREADY,
input [ 1: 0] SAXIHP0AWSIZE,
input SAXIHP0AWVALID,
output [ 5: 0] SAXIHP0BID,
input SAXIHP0BREADY,
output [ 1: 0] SAXIHP0BRESP,
output SAXIHP0BVALID,
output [ 2: 0] SAXIHP0RACOUNT,
output [ 7: 0] SAXIHP0RCOUNT,
output [63: 0] SAXIHP0RDATA,
input SAXIHP0RDISSUECAP1EN,
output [ 5: 0] SAXIHP0RID,
output SAXIHP0RLAST,
input SAXIHP0RREADY,
output [ 1: 0] SAXIHP0RRESP,
output SAXIHP0RVALID,
output [ 5: 0] SAXIHP0WACOUNT,
output [ 7: 0] SAXIHP0WCOUNT,
input [63: 0] SAXIHP0WDATA,
input [ 5: 0] SAXIHP0WID,
input SAXIHP0WLAST,
output SAXIHP0WREADY,
input SAXIHP0WRISSUECAP1EN,
input [ 7: 0] SAXIHP0WSTRB,
input SAXIHP0WVALID,
input SAXIHP1ACLK,
input [31: 0] SAXIHP1ARADDR,
input [ 1: 0] SAXIHP1ARBURST,
input [ 3: 0] SAXIHP1ARCACHE,
output SAXIHP1ARESETN,
input [ 5: 0] SAXIHP1ARID,
input [ 3: 0] SAXIHP1ARLEN,
input [ 1: 0] SAXIHP1ARLOCK,
input [ 2: 0] SAXIHP1ARPROT,
input [ 3: 0] SAXIHP1ARQOS,
output SAXIHP1ARREADY,
input [ 1: 0] SAXIHP1ARSIZE,
input SAXIHP1ARVALID,
input [31: 0] SAXIHP1AWADDR,
input [ 1: 0] SAXIHP1AWBURST,
input [ 3: 0] SAXIHP1AWCACHE,
input [ 5: 0] SAXIHP1AWID,
input [ 3: 0] SAXIHP1AWLEN,
input [ 1: 0] SAXIHP1AWLOCK,
input [ 2: 0] SAXIHP1AWPROT,
input [ 3: 0] SAXIHP1AWQOS,
output SAXIHP1AWREADY,
input [ 1: 0] SAXIHP1AWSIZE,
input SAXIHP1AWVALID,
output [ 5: 0] SAXIHP1BID,
input SAXIHP1BREADY,
output [ 1: 0] SAXIHP1BRESP,
output SAXIHP1BVALID,
output [ 2: 0] SAXIHP1RACOUNT,
output [ 7: 0] SAXIHP1RCOUNT,
output [63: 0] SAXIHP1RDATA,
input SAXIHP1RDISSUECAP1EN,
output [ 5: 0] SAXIHP1RID,
output SAXIHP1RLAST,
input SAXIHP1RREADY,
output [ 1: 0] SAXIHP1RRESP,
output SAXIHP1RVALID,
output [ 5: 0] SAXIHP1WACOUNT,
output [ 7: 0] SAXIHP1WCOUNT,
input [63: 0] SAXIHP1WDATA,
input [ 5: 0] SAXIHP1WID,
input SAXIHP1WLAST,
output SAXIHP1WREADY,
input SAXIHP1WRISSUECAP1EN,
input [ 7: 0] SAXIHP1WSTRB,
input SAXIHP1WVALID,
input SAXIHP2ACLK,
input [31: 0] SAXIHP2ARADDR,
input [ 1: 0] SAXIHP2ARBURST,
input [ 3: 0] SAXIHP2ARCACHE,
output SAXIHP2ARESETN,
input [ 5: 0] SAXIHP2ARID,
input [ 3: 0] SAXIHP2ARLEN,
input [ 1: 0] SAXIHP2ARLOCK,
input [ 2: 0] SAXIHP2ARPROT,
input [ 3: 0] SAXIHP2ARQOS,
output SAXIHP2ARREADY,
input [ 1: 0] SAXIHP2ARSIZE,
input SAXIHP2ARVALID,
input [31: 0] SAXIHP2AWADDR,
input [ 1: 0] SAXIHP2AWBURST,
input [ 3: 0] SAXIHP2AWCACHE,
input [ 5: 0] SAXIHP2AWID,
input [ 3: 0] SAXIHP2AWLEN,
input [ 1: 0] SAXIHP2AWLOCK,
input [ 2: 0] SAXIHP2AWPROT,
input [ 3: 0] SAXIHP2AWQOS,
output SAXIHP2AWREADY,
input [ 1: 0] SAXIHP2AWSIZE,
input SAXIHP2AWVALID,
output [ 5: 0] SAXIHP2BID,
input SAXIHP2BREADY,
output [ 1: 0] SAXIHP2BRESP,
output SAXIHP2BVALID,
output [ 2: 0] SAXIHP2RACOUNT,
output [ 7: 0] SAXIHP2RCOUNT,
output [63: 0] SAXIHP2RDATA,
input SAXIHP2RDISSUECAP1EN,
output [ 5: 0] SAXIHP2RID,
output SAXIHP2RLAST,
input SAXIHP2RREADY,
output [ 1: 0] SAXIHP2RRESP,
output SAXIHP2RVALID,
output [ 5: 0] SAXIHP2WACOUNT,
output [ 7: 0] SAXIHP2WCOUNT,
input [63: 0] SAXIHP2WDATA,
input [ 5: 0] SAXIHP2WID,
input SAXIHP2WLAST,
output SAXIHP2WREADY,
input SAXIHP2WRISSUECAP1EN,
input [ 7: 0] SAXIHP2WSTRB,
input SAXIHP2WVALID,
input SAXIHP3ACLK,
input [31: 0] SAXIHP3ARADDR,
input [ 1: 0] SAXIHP3ARBURST,
input [ 3: 0] SAXIHP3ARCACHE,
output SAXIHP3ARESETN,
input [ 5: 0] SAXIHP3ARID,
input [ 3: 0] SAXIHP3ARLEN,
input [ 1: 0] SAXIHP3ARLOCK,
input [ 2: 0] SAXIHP3ARPROT,
input [ 3: 0] SAXIHP3ARQOS,
output SAXIHP3ARREADY,
input [ 1: 0] SAXIHP3ARSIZE,
input SAXIHP3ARVALID,
input [31: 0] SAXIHP3AWADDR,
input [ 1: 0] SAXIHP3AWBURST,
input [ 3: 0] SAXIHP3AWCACHE,
input [ 5: 0] SAXIHP3AWID,
input [ 3: 0] SAXIHP3AWLEN,
input [ 1: 0] SAXIHP3AWLOCK,
input [ 2: 0] SAXIHP3AWPROT,
input [ 3: 0] SAXIHP3AWQOS,
output SAXIHP3AWREADY,
input [ 1: 0] SAXIHP3AWSIZE,
input SAXIHP3AWVALID,
output [ 5: 0] SAXIHP3BID,
input SAXIHP3BREADY,
output [ 1: 0] SAXIHP3BRESP,
output SAXIHP3BVALID,
output [ 2: 0] SAXIHP3RACOUNT,
output [ 7: 0] SAXIHP3RCOUNT,
output [63: 0] SAXIHP3RDATA,
input SAXIHP3RDISSUECAP1EN,
output [ 5: 0] SAXIHP3RID,
output SAXIHP3RLAST,
input SAXIHP3RREADY,
output [ 1: 0] SAXIHP3RRESP,
output SAXIHP3RVALID,
output [ 5: 0] SAXIHP3WACOUNT,
output [ 7: 0] SAXIHP3WCOUNT,
input [63: 0] SAXIHP3WDATA,
input [ 5: 0] SAXIHP3WID,
input SAXIHP3WLAST,
output SAXIHP3WREADY,
input SAXIHP3WRISSUECAP1EN,
input [ 7: 0] SAXIHP3WSTRB,
input SAXIHP3WVALID
);
// Techmap specific parameters.
parameter _TECHMAP_CONSTMSK_DDRARB_ = 0;
parameter _TECHMAP_CONSTVAL_DDRARB_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOCAN0PHYRX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOCAN0PHYRX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOCAN1PHYRX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOCAN1PHYRX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0EXTINTIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0EXTINTIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIICOL_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIICOL_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIICRS_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIICRS_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXD_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXD_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXER_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXER_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0MDIOI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0MDIOI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1EXTINTIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1EXTINTIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIICOL_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIICOL_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIICRS_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIICRS_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXD_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXD_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXER_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXER_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1MDIOI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1MDIOI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOGPIOI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOGPIOI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C0SCLI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C0SCLI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C0SDAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C0SDAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C1SCLI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C1SCLI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C1SDAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C1SDAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOPJTAGTCK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOPJTAGTCK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOPJTAGTDI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOPJTAGTDI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOPJTAGTMS_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOPJTAGTMS_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0CDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0CDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0CLKFB_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0CLKFB_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0CMDI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0CMDI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0DATAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0DATAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0WP_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0WP_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1CDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1CDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1CLKFB_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1CLKFB_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1CMDI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1CMDI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1DATAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1DATAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1WP_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1WP_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0MI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0MI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0SCLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0SCLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0SI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0SI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0SSIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0SSIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1MI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1MI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1SCLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1SCLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1SI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1SI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1SSIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1SSIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSRAMINTIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSRAMINTIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOTRACECLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOTRACECLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOTTC0CLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOTTC0CLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOTTC1CLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOTTC1CLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0CTSN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0CTSN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0DCDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0DCDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0DSRN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0DSRN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0RIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0RIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0RX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0RX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1CTSN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1CTSN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1DCDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1DCDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1DSRN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1DSRN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1RIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1RIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1RX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1RX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUSB0VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUSB0VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUSB1VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUSB1VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOWDTCLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOWDTCLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EVENTEVENTI_ = 0;
parameter _TECHMAP_CONSTVAL_EVENTEVENTI_ = 0;
parameter _TECHMAP_CONSTMSK_FCLKCLKTRIGN_ = 0;
parameter _TECHMAP_CONSTVAL_FCLKCLKTRIGN_ = 0;
parameter _TECHMAP_CONSTMSK_FPGAIDLEN_ = 0;
parameter _TECHMAP_CONSTVAL_FPGAIDLEN_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINATID_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINATID_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINCLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINCLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINDATA_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINDATA_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINVALID_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINVALID_ = 0;
parameter _TECHMAP_CONSTMSK_FTMTF2PDEBUG_ = 0;
parameter _TECHMAP_CONSTVAL_FTMTF2PDEBUG_ = 0;
parameter _TECHMAP_CONSTMSK_FTMTF2PTRIG_ = 0;
parameter _TECHMAP_CONSTVAL_FTMTF2PTRIG_ = 0;
parameter _TECHMAP_CONSTMSK_FTMTP2FTRIGACK_ = 0;
parameter _TECHMAP_CONSTVAL_FTMTP2FTRIGACK_ = 0;
parameter _TECHMAP_CONSTMSK_IRQF2P_ = 0;
parameter _TECHMAP_CONSTVAL_IRQF2P_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0ARREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0ARREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0AWREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0AWREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0BID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0BID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0BRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0BRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0BVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0BVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RDATA_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RDATA_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RLAST_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RLAST_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0WREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0WREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1ARREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1ARREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1AWREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1AWREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1BID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1BID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1BRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1BRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1BVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1BVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RDATA_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RDATA_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RLAST_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RLAST_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1WREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1WREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARUSER_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARUSER_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWUSER_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWUSER_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPBREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPBREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPRREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPRREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WVALID_ = 0;
// Detect all unconnected inputs and tie them to 0.
wire [3:0] ddrarb = (_TECHMAP_CONSTMSK_DDRARB_ == 4'd0 && _TECHMAP_CONSTVAL_DDRARB_ === 4'd0) ? 4'b0 : DDRARB;
wire [0:0] dma0aclk = (_TECHMAP_CONSTMSK_DMA0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0ACLK_ === 1'd0) ? 1'b0 : DMA0ACLK;
wire [0:0] dma0daready = (_TECHMAP_CONSTMSK_DMA0DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0DAREADY_ === 1'd0) ? 1'b0 : DMA0DAREADY;
wire [0:0] dma0drlast = (_TECHMAP_CONSTMSK_DMA0DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0DRLAST_ === 1'd0) ? 1'b0 : DMA0DRLAST;
wire [1:0] dma0drtype = (_TECHMAP_CONSTMSK_DMA0DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA0DRTYPE_ === 2'd0) ? 2'b0 : DMA0DRTYPE;
wire [0:0] dma0drvalid = (_TECHMAP_CONSTMSK_DMA0DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0DRVALID_ === 1'd0) ? 1'b0 : DMA0DRVALID;
wire [0:0] dma1aclk = (_TECHMAP_CONSTMSK_DMA1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1ACLK_ === 1'd0) ? 1'b0 : DMA1ACLK;
wire [0:0] dma1daready = (_TECHMAP_CONSTMSK_DMA1DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1DAREADY_ === 1'd0) ? 1'b0 : DMA1DAREADY;
wire [0:0] dma1drlast = (_TECHMAP_CONSTMSK_DMA1DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1DRLAST_ === 1'd0) ? 1'b0 : DMA1DRLAST;
wire [1:0] dma1drtype = (_TECHMAP_CONSTMSK_DMA1DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA1DRTYPE_ === 2'd0) ? 2'b0 : DMA1DRTYPE;
wire [0:0] dma1drvalid = (_TECHMAP_CONSTMSK_DMA1DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1DRVALID_ === 1'd0) ? 1'b0 : DMA1DRVALID;
wire [0:0] dma2aclk = (_TECHMAP_CONSTMSK_DMA2ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2ACLK_ === 1'd0) ? 1'b0 : DMA2ACLK;
wire [0:0] dma2daready = (_TECHMAP_CONSTMSK_DMA2DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2DAREADY_ === 1'd0) ? 1'b0 : DMA2DAREADY;
wire [0:0] dma2drlast = (_TECHMAP_CONSTMSK_DMA2DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2DRLAST_ === 1'd0) ? 1'b0 : DMA2DRLAST;
wire [1:0] dma2drtype = (_TECHMAP_CONSTMSK_DMA2DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA2DRTYPE_ === 2'd0) ? 2'b0 : DMA2DRTYPE;
wire [0:0] dma2drvalid = (_TECHMAP_CONSTMSK_DMA2DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2DRVALID_ === 1'd0) ? 1'b0 : DMA2DRVALID;
wire [0:0] dma3aclk = (_TECHMAP_CONSTMSK_DMA3ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3ACLK_ === 1'd0) ? 1'b0 : DMA3ACLK;
wire [0:0] dma3daready = (_TECHMAP_CONSTMSK_DMA3DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3DAREADY_ === 1'd0) ? 1'b0 : DMA3DAREADY;
wire [0:0] dma3drlast = (_TECHMAP_CONSTMSK_DMA3DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3DRLAST_ === 1'd0) ? 1'b0 : DMA3DRLAST;
wire [1:0] dma3drtype = (_TECHMAP_CONSTMSK_DMA3DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA3DRTYPE_ === 2'd0) ? 2'b0 : DMA3DRTYPE;
wire [0:0] dma3drvalid = (_TECHMAP_CONSTMSK_DMA3DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3DRVALID_ === 1'd0) ? 1'b0 : DMA3DRVALID;
wire [0:0] emiocan0phyrx = (_TECHMAP_CONSTMSK_EMIOCAN0PHYRX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOCAN0PHYRX_ === 1'd0) ? 1'b0 : EMIOCAN0PHYRX;
wire [0:0] emiocan1phyrx = (_TECHMAP_CONSTMSK_EMIOCAN1PHYRX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOCAN1PHYRX_ === 1'd0) ? 1'b0 : EMIOCAN1PHYRX;
wire [0:0] emioenet0extintin = (_TECHMAP_CONSTMSK_EMIOENET0EXTINTIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0EXTINTIN_ === 1'd0) ? 1'b0 : EMIOENET0EXTINTIN;
wire [0:0] emioenet0gmiicol = (_TECHMAP_CONSTMSK_EMIOENET0GMIICOL_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIICOL_ === 1'd0) ? 1'b0 : EMIOENET0GMIICOL;
wire [0:0] emioenet0gmiicrs = (_TECHMAP_CONSTMSK_EMIOENET0GMIICRS_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIICRS_ === 1'd0) ? 1'b0 : EMIOENET0GMIICRS;
wire [0:0] emioenet0gmiirxclk = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXCLK_ === 1'd0) ? 1'b0 : EMIOENET0GMIIRXCLK;
wire [7:0] emioenet0gmiirxd = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXD_ == 8'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXD_ === 8'd0) ? 8'b0 : EMIOENET0GMIIRXD;
wire [0:0] emioenet0gmiirxdv = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXDV_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXDV_ === 1'd0) ? 1'b0 : EMIOENET0GMIIRXDV;
wire [0:0] emioenet0gmiirxer = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXER_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXER_ === 1'd0) ? 1'b0 : EMIOENET0GMIIRXER;
wire [0:0] emioenet0gmiitxclk = (_TECHMAP_CONSTMSK_EMIOENET0GMIITXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIITXCLK_ === 1'd0) ? 1'b0 : EMIOENET0GMIITXCLK;
wire [0:0] emioenet0mdioi = (_TECHMAP_CONSTMSK_EMIOENET0MDIOI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0MDIOI_ === 1'd0) ? 1'b0 : EMIOENET0MDIOI;
wire [0:0] emioenet1extintin = (_TECHMAP_CONSTMSK_EMIOENET1EXTINTIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1EXTINTIN_ === 1'd0) ? 1'b0 : EMIOENET1EXTINTIN;
wire [0:0] emioenet1gmiicol = (_TECHMAP_CONSTMSK_EMIOENET1GMIICOL_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIICOL_ === 1'd0) ? 1'b0 : EMIOENET1GMIICOL;
wire [0:0] emioenet1gmiicrs = (_TECHMAP_CONSTMSK_EMIOENET1GMIICRS_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIICRS_ === 1'd0) ? 1'b0 : EMIOENET1GMIICRS;
wire [0:0] emioenet1gmiirxclk = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXCLK_ === 1'd0) ? 1'b0 : EMIOENET1GMIIRXCLK;
wire [7:0] emioenet1gmiirxd = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXD_ == 8'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXD_ === 8'd0) ? 8'b0 : EMIOENET1GMIIRXD;
wire [0:0] emioenet1gmiirxdv = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXDV_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXDV_ === 1'd0) ? 1'b0 : EMIOENET1GMIIRXDV;
wire [0:0] emioenet1gmiirxer = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXER_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXER_ === 1'd0) ? 1'b0 : EMIOENET1GMIIRXER;
wire [0:0] emioenet1gmiitxclk = (_TECHMAP_CONSTMSK_EMIOENET1GMIITXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIITXCLK_ === 1'd0) ? 1'b0 : EMIOENET1GMIITXCLK;
wire [0:0] emioenet1mdioi = (_TECHMAP_CONSTMSK_EMIOENET1MDIOI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1MDIOI_ === 1'd0) ? 1'b0 : EMIOENET1MDIOI;
wire [63:0] emiogpioi = (_TECHMAP_CONSTMSK_EMIOGPIOI_ == 64'd0 && _TECHMAP_CONSTVAL_EMIOGPIOI_ === 64'd0) ? 64'b0 : EMIOGPIOI;
wire [0:0] emioi2c0scli = (_TECHMAP_CONSTMSK_EMIOI2C0SCLI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C0SCLI_ === 1'd0) ? 1'b0 : EMIOI2C0SCLI;
wire [0:0] emioi2c0sdai = (_TECHMAP_CONSTMSK_EMIOI2C0SDAI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C0SDAI_ === 1'd0) ? 1'b0 : EMIOI2C0SDAI;
wire [0:0] emioi2c1scli = (_TECHMAP_CONSTMSK_EMIOI2C1SCLI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C1SCLI_ === 1'd0) ? 1'b0 : EMIOI2C1SCLI;
wire [0:0] emioi2c1sdai = (_TECHMAP_CONSTMSK_EMIOI2C1SDAI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C1SDAI_ === 1'd0) ? 1'b0 : EMIOI2C1SDAI;
wire [0:0] emiopjtagtck = (_TECHMAP_CONSTMSK_EMIOPJTAGTCK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOPJTAGTCK_ === 1'd0) ? 1'b0 : EMIOPJTAGTCK;
wire [0:0] emiopjtagtdi = (_TECHMAP_CONSTMSK_EMIOPJTAGTDI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOPJTAGTDI_ === 1'd0) ? 1'b0 : EMIOPJTAGTDI;
wire [0:0] emiopjtagtms = (_TECHMAP_CONSTMSK_EMIOPJTAGTMS_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOPJTAGTMS_ === 1'd0) ? 1'b0 : EMIOPJTAGTMS;
wire [0:0] emiosdio0cdn = (_TECHMAP_CONSTMSK_EMIOSDIO0CDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0CDN_ === 1'd0) ? 1'b0 : EMIOSDIO0CDN;
wire [0:0] emiosdio0clkfb = (_TECHMAP_CONSTMSK_EMIOSDIO0CLKFB_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0CLKFB_ === 1'd0) ? 1'b0 : EMIOSDIO0CLKFB;
wire [0:0] emiosdio0cmdi = (_TECHMAP_CONSTMSK_EMIOSDIO0CMDI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0CMDI_ === 1'd0) ? 1'b0 : EMIOSDIO0CMDI;
wire [3:0] emiosdio0datai = (_TECHMAP_CONSTMSK_EMIOSDIO0DATAI_ == 4'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0DATAI_ === 4'd0) ? 4'b0 : EMIOSDIO0DATAI;
wire [0:0] emiosdio0wp = (_TECHMAP_CONSTMSK_EMIOSDIO0WP_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0WP_ === 1'd0) ? 1'b0 : EMIOSDIO0WP;
wire [0:0] emiosdio1cdn = (_TECHMAP_CONSTMSK_EMIOSDIO1CDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1CDN_ === 1'd0) ? 1'b0 : EMIOSDIO1CDN;
wire [0:0] emiosdio1clkfb = (_TECHMAP_CONSTMSK_EMIOSDIO1CLKFB_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1CLKFB_ === 1'd0) ? 1'b0 : EMIOSDIO1CLKFB;
wire [0:0] emiosdio1cmdi = (_TECHMAP_CONSTMSK_EMIOSDIO1CMDI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1CMDI_ === 1'd0) ? 1'b0 : EMIOSDIO1CMDI;
wire [3:0] emiosdio1datai = (_TECHMAP_CONSTMSK_EMIOSDIO1DATAI_ == 4'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1DATAI_ === 4'd0) ? 4'b0 : EMIOSDIO1DATAI;
wire [0:0] emiosdio1wp = (_TECHMAP_CONSTMSK_EMIOSDIO1WP_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1WP_ === 1'd0) ? 1'b0 : EMIOSDIO1WP;
wire [0:0] emiospi0mi = (_TECHMAP_CONSTMSK_EMIOSPI0MI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0MI_ === 1'd0) ? 1'b0 : EMIOSPI0MI;
wire [0:0] emiospi0sclki = (_TECHMAP_CONSTMSK_EMIOSPI0SCLKI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0SCLKI_ === 1'd0) ? 1'b0 : EMIOSPI0SCLKI;
wire [0:0] emiospi0si = (_TECHMAP_CONSTMSK_EMIOSPI0SI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0SI_ === 1'd0) ? 1'b0 : EMIOSPI0SI;
wire [0:0] emiospi0ssin = (_TECHMAP_CONSTMSK_EMIOSPI0SSIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0SSIN_ === 1'd0) ? 1'b0 : EMIOSPI0SSIN;
wire [0:0] emiospi1mi = (_TECHMAP_CONSTMSK_EMIOSPI1MI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1MI_ === 1'd0) ? 1'b0 : EMIOSPI1MI;
wire [0:0] emiospi1sclki = (_TECHMAP_CONSTMSK_EMIOSPI1SCLKI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1SCLKI_ === 1'd0) ? 1'b0 : EMIOSPI1SCLKI;
wire [0:0] emiospi1si = (_TECHMAP_CONSTMSK_EMIOSPI1SI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1SI_ === 1'd0) ? 1'b0 : EMIOSPI1SI;
wire [0:0] emiospi1ssin = (_TECHMAP_CONSTMSK_EMIOSPI1SSIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1SSIN_ === 1'd0) ? 1'b0 : EMIOSPI1SSIN;
wire [0:0] emiosramintin = (_TECHMAP_CONSTMSK_EMIOSRAMINTIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSRAMINTIN_ === 1'd0) ? 1'b0 : EMIOSRAMINTIN;
wire [0:0] emiotraceclk = (_TECHMAP_CONSTMSK_EMIOTRACECLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOTRACECLK_ === 1'd0) ? 1'b0 : EMIOTRACECLK;
wire [2:0] emiottc0clki = (_TECHMAP_CONSTMSK_EMIOTTC0CLKI_ == 3'd0 && _TECHMAP_CONSTVAL_EMIOTTC0CLKI_ === 3'd0) ? 3'b0 : EMIOTTC0CLKI;
wire [2:0] emiottc1clki = (_TECHMAP_CONSTMSK_EMIOTTC1CLKI_ == 3'd0 && _TECHMAP_CONSTVAL_EMIOTTC1CLKI_ === 3'd0) ? 3'b0 : EMIOTTC1CLKI;
wire [0:0] emiouart0ctsn = (_TECHMAP_CONSTMSK_EMIOUART0CTSN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0CTSN_ === 1'd0) ? 1'b0 : EMIOUART0CTSN;
wire [0:0] emiouart0dcdn = (_TECHMAP_CONSTMSK_EMIOUART0DCDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0DCDN_ === 1'd0) ? 1'b0 : EMIOUART0DCDN;
wire [0:0] emiouart0dsrn = (_TECHMAP_CONSTMSK_EMIOUART0DSRN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0DSRN_ === 1'd0) ? 1'b0 : EMIOUART0DSRN;
wire [0:0] emiouart0rin = (_TECHMAP_CONSTMSK_EMIOUART0RIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0RIN_ === 1'd0) ? 1'b0 : EMIOUART0RIN;
wire [0:0] emiouart0rx = (_TECHMAP_CONSTMSK_EMIOUART0RX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0RX_ === 1'd0) ? 1'b0 : EMIOUART0RX;
wire [0:0] emiouart1ctsn = (_TECHMAP_CONSTMSK_EMIOUART1CTSN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1CTSN_ === 1'd0) ? 1'b0 : EMIOUART1CTSN;
wire [0:0] emiouart1dcdn = (_TECHMAP_CONSTMSK_EMIOUART1DCDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1DCDN_ === 1'd0) ? 1'b0 : EMIOUART1DCDN;
wire [0:0] emiouart1dsrn = (_TECHMAP_CONSTMSK_EMIOUART1DSRN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1DSRN_ === 1'd0) ? 1'b0 : EMIOUART1DSRN;
wire [0:0] emiouart1rin = (_TECHMAP_CONSTMSK_EMIOUART1RIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1RIN_ === 1'd0) ? 1'b0 : EMIOUART1RIN;
wire [0:0] emiouart1rx = (_TECHMAP_CONSTMSK_EMIOUART1RX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1RX_ === 1'd0) ? 1'b0 : EMIOUART1RX;
wire [0:0] emiousb0vbuspwrfault = (_TECHMAP_CONSTMSK_EMIOUSB0VBUSPWRFAULT_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUSB0VBUSPWRFAULT_ === 1'd0) ? 1'b0 : EMIOUSB0VBUSPWRFAULT;
wire [0:0] emiousb1vbuspwrfault = (_TECHMAP_CONSTMSK_EMIOUSB1VBUSPWRFAULT_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUSB1VBUSPWRFAULT_ === 1'd0) ? 1'b0 : EMIOUSB1VBUSPWRFAULT;
wire [0:0] emiowdtclki = (_TECHMAP_CONSTMSK_EMIOWDTCLKI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOWDTCLKI_ === 1'd0) ? 1'b0 : EMIOWDTCLKI;
wire [0:0] eventeventi = (_TECHMAP_CONSTMSK_EVENTEVENTI_ == 1'd0 && _TECHMAP_CONSTVAL_EVENTEVENTI_ === 1'd0) ? 1'b0 : EVENTEVENTI;
wire [3:0] fclkclktrign = (_TECHMAP_CONSTMSK_FCLKCLKTRIGN_ == 4'd0 && _TECHMAP_CONSTVAL_FCLKCLKTRIGN_ === 4'd0) ? 4'b0 : FCLKCLKTRIGN;
wire [0:0] fpgaidlen = (_TECHMAP_CONSTMSK_FPGAIDLEN_ == 1'd0 && _TECHMAP_CONSTVAL_FPGAIDLEN_ === 1'd0) ? 1'b0 : FPGAIDLEN;
wire [3:0] ftmdtraceinatid = (_TECHMAP_CONSTMSK_FTMDTRACEINATID_ == 4'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINATID_ === 4'd0) ? 4'b0 : FTMDTRACEINATID;
wire [0:0] ftmdtraceinclock = (_TECHMAP_CONSTMSK_FTMDTRACEINCLOCK_ == 1'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINCLOCK_ === 1'd0) ? 1'b0 : FTMDTRACEINCLOCK;
wire [31:0] ftmdtraceindata = (_TECHMAP_CONSTMSK_FTMDTRACEINDATA_ == 32'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINDATA_ === 32'd0) ? 32'b0 : FTMDTRACEINDATA;
wire [0:0] ftmdtraceinvalid = (_TECHMAP_CONSTMSK_FTMDTRACEINVALID_ == 1'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINVALID_ === 1'd0) ? 1'b0 : FTMDTRACEINVALID;
wire [31:0] ftmtf2pdebug = (_TECHMAP_CONSTMSK_FTMTF2PDEBUG_ == 32'd0 && _TECHMAP_CONSTVAL_FTMTF2PDEBUG_ === 32'd0) ? 32'b0 : FTMTF2PDEBUG;
wire [3:0] ftmtf2ptrig = (_TECHMAP_CONSTMSK_FTMTF2PTRIG_ == 4'd0 && _TECHMAP_CONSTVAL_FTMTF2PTRIG_ === 4'd0) ? 4'b0 : FTMTF2PTRIG;
wire [3:0] ftmtp2ftrigack = (_TECHMAP_CONSTMSK_FTMTP2FTRIGACK_ == 4'd0 && _TECHMAP_CONSTVAL_FTMTP2FTRIGACK_ === 4'd0) ? 4'b0 : FTMTP2FTRIGACK;
wire [19:0] irqf2p = (_TECHMAP_CONSTMSK_IRQF2P_ == 20'd0 && _TECHMAP_CONSTVAL_IRQF2P_ === 20'd0) ? 20'b0 : IRQF2P;
wire [0:0] maxigp0aclk = (_TECHMAP_CONSTMSK_MAXIGP0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0ACLK_ === 1'd0) ? 1'b0 : MAXIGP0ACLK;
wire [0:0] maxigp0arready = (_TECHMAP_CONSTMSK_MAXIGP0ARREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0ARREADY_ === 1'd0) ? 1'b0 : MAXIGP0ARREADY;
wire [0:0] maxigp0awready = (_TECHMAP_CONSTMSK_MAXIGP0AWREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0AWREADY_ === 1'd0) ? 1'b0 : MAXIGP0AWREADY;
wire [11:0] maxigp0bid = (_TECHMAP_CONSTMSK_MAXIGP0BID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP0BID_ === 12'd0) ? 12'b0 : MAXIGP0BID;
wire [1:0] maxigp0bresp = (_TECHMAP_CONSTMSK_MAXIGP0BRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP0BRESP_ === 2'd0) ? 2'b0 : MAXIGP0BRESP;
wire [0:0] maxigp0bvalid = (_TECHMAP_CONSTMSK_MAXIGP0BVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0BVALID_ === 1'd0) ? 1'b0 : MAXIGP0BVALID;
wire [31:0] maxigp0rdata = (_TECHMAP_CONSTMSK_MAXIGP0RDATA_ == 32'd0 && _TECHMAP_CONSTVAL_MAXIGP0RDATA_ === 32'd0) ? 32'b0 : MAXIGP0RDATA;
wire [11:0] maxigp0rid = (_TECHMAP_CONSTMSK_MAXIGP0RID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP0RID_ === 12'd0) ? 12'b0 : MAXIGP0RID;
wire [0:0] maxigp0rlast = (_TECHMAP_CONSTMSK_MAXIGP0RLAST_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0RLAST_ === 1'd0) ? 1'b0 : MAXIGP0RLAST;
wire [1:0] maxigp0rresp = (_TECHMAP_CONSTMSK_MAXIGP0RRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP0RRESP_ === 2'd0) ? 2'b0 : MAXIGP0RRESP;
wire [0:0] maxigp0rvalid = (_TECHMAP_CONSTMSK_MAXIGP0RVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0RVALID_ === 1'd0) ? 1'b0 : MAXIGP0RVALID;
wire [0:0] maxigp0wready = (_TECHMAP_CONSTMSK_MAXIGP0WREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0WREADY_ === 1'd0) ? 1'b0 : MAXIGP0WREADY;
wire [0:0] maxigp1aclk = (_TECHMAP_CONSTMSK_MAXIGP1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1ACLK_ === 1'd0) ? 1'b0 : MAXIGP1ACLK;
wire [0:0] maxigp1arready = (_TECHMAP_CONSTMSK_MAXIGP1ARREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1ARREADY_ === 1'd0) ? 1'b0 : MAXIGP1ARREADY;
wire [0:0] maxigp1awready = (_TECHMAP_CONSTMSK_MAXIGP1AWREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1AWREADY_ === 1'd0) ? 1'b0 : MAXIGP1AWREADY;
wire [11:0] maxigp1bid = (_TECHMAP_CONSTMSK_MAXIGP1BID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP1BID_ === 12'd0) ? 12'b0 : MAXIGP1BID;
wire [1:0] maxigp1bresp = (_TECHMAP_CONSTMSK_MAXIGP1BRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP1BRESP_ === 2'd0) ? 2'b0 : MAXIGP1BRESP;
wire [0:0] maxigp1bvalid = (_TECHMAP_CONSTMSK_MAXIGP1BVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1BVALID_ === 1'd0) ? 1'b0 : MAXIGP1BVALID;
wire [31:0] maxigp1rdata = (_TECHMAP_CONSTMSK_MAXIGP1RDATA_ == 32'd0 && _TECHMAP_CONSTVAL_MAXIGP1RDATA_ === 32'd0) ? 32'b0 : MAXIGP1RDATA;
wire [11:0] maxigp1rid = (_TECHMAP_CONSTMSK_MAXIGP1RID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP1RID_ === 12'd0) ? 12'b0 : MAXIGP1RID;
wire [0:0] maxigp1rlast = (_TECHMAP_CONSTMSK_MAXIGP1RLAST_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1RLAST_ === 1'd0) ? 1'b0 : MAXIGP1RLAST;
wire [1:0] maxigp1rresp = (_TECHMAP_CONSTMSK_MAXIGP1RRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP1RRESP_ === 2'd0) ? 2'b0 : MAXIGP1RRESP;
wire [0:0] maxigp1rvalid = (_TECHMAP_CONSTMSK_MAXIGP1RVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1RVALID_ === 1'd0) ? 1'b0 : MAXIGP1RVALID;
wire [0:0] maxigp1wready = (_TECHMAP_CONSTMSK_MAXIGP1WREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1WREADY_ === 1'd0) ? 1'b0 : MAXIGP1WREADY;
wire [0:0] saxiacpaclk = (_TECHMAP_CONSTMSK_SAXIACPACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPACLK_ === 1'd0) ? 1'b0 : SAXIACPACLK;
wire [31:0] saxiacparaddr = (_TECHMAP_CONSTMSK_SAXIACPARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIACPARADDR_ === 32'd0) ? 32'b0 : SAXIACPARADDR;
wire [1:0] saxiacparburst = (_TECHMAP_CONSTMSK_SAXIACPARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPARBURST_ === 2'd0) ? 2'b0 : SAXIACPARBURST;
wire [3:0] saxiacparcache = (_TECHMAP_CONSTMSK_SAXIACPARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPARCACHE_ === 4'd0) ? 4'b0 : SAXIACPARCACHE;
wire [2:0] saxiacparid = (_TECHMAP_CONSTMSK_SAXIACPARID_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPARID_ === 3'd0) ? 3'b0 : SAXIACPARID;
wire [3:0] saxiacparlen = (_TECHMAP_CONSTMSK_SAXIACPARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPARLEN_ === 4'd0) ? 4'b0 : SAXIACPARLEN;
wire [1:0] saxiacparlock = (_TECHMAP_CONSTMSK_SAXIACPARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPARLOCK_ === 2'd0) ? 2'b0 : SAXIACPARLOCK;
wire [2:0] saxiacparprot = (_TECHMAP_CONSTMSK_SAXIACPARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPARPROT_ === 3'd0) ? 3'b0 : SAXIACPARPROT;
wire [3:0] saxiacparqos = (_TECHMAP_CONSTMSK_SAXIACPARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPARQOS_ === 4'd0) ? 4'b0 : SAXIACPARQOS;
wire [1:0] saxiacparsize = (_TECHMAP_CONSTMSK_SAXIACPARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPARSIZE_ === 2'd0) ? 2'b0 : SAXIACPARSIZE;
wire [4:0] saxiacparuser = (_TECHMAP_CONSTMSK_SAXIACPARUSER_ == 5'd0 && _TECHMAP_CONSTVAL_SAXIACPARUSER_ === 5'd0) ? 5'b0 : SAXIACPARUSER;
wire [0:0] saxiacparvalid = (_TECHMAP_CONSTMSK_SAXIACPARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPARVALID_ === 1'd0) ? 1'b0 : SAXIACPARVALID;
wire [31:0] saxiacpawaddr = (_TECHMAP_CONSTMSK_SAXIACPAWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIACPAWADDR_ === 32'd0) ? 32'b0 : SAXIACPAWADDR;
wire [1:0] saxiacpawburst = (_TECHMAP_CONSTMSK_SAXIACPAWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPAWBURST_ === 2'd0) ? 2'b0 : SAXIACPAWBURST;
wire [3:0] saxiacpawcache = (_TECHMAP_CONSTMSK_SAXIACPAWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPAWCACHE_ === 4'd0) ? 4'b0 : SAXIACPAWCACHE;
wire [2:0] saxiacpawid = (_TECHMAP_CONSTMSK_SAXIACPAWID_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPAWID_ === 3'd0) ? 3'b0 : SAXIACPAWID;
wire [3:0] saxiacpawlen = (_TECHMAP_CONSTMSK_SAXIACPAWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPAWLEN_ === 4'd0) ? 4'b0 : SAXIACPAWLEN;
wire [1:0] saxiacpawlock = (_TECHMAP_CONSTMSK_SAXIACPAWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPAWLOCK_ === 2'd0) ? 2'b0 : SAXIACPAWLOCK;
wire [2:0] saxiacpawprot = (_TECHMAP_CONSTMSK_SAXIACPAWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPAWPROT_ === 3'd0) ? 3'b0 : SAXIACPAWPROT;
wire [3:0] saxiacpawqos = (_TECHMAP_CONSTMSK_SAXIACPAWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPAWQOS_ === 4'd0) ? 4'b0 : SAXIACPAWQOS;
wire [1:0] saxiacpawsize = (_TECHMAP_CONSTMSK_SAXIACPAWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPAWSIZE_ === 2'd0) ? 2'b0 : SAXIACPAWSIZE;
wire [4:0] saxiacpawuser = (_TECHMAP_CONSTMSK_SAXIACPAWUSER_ == 5'd0 && _TECHMAP_CONSTVAL_SAXIACPAWUSER_ === 5'd0) ? 5'b0 : SAXIACPAWUSER;
wire [0:0] saxiacpawvalid = (_TECHMAP_CONSTMSK_SAXIACPAWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPAWVALID_ === 1'd0) ? 1'b0 : SAXIACPAWVALID;
wire [0:0] saxiacpbready = (_TECHMAP_CONSTMSK_SAXIACPBREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPBREADY_ === 1'd0) ? 1'b0 : SAXIACPBREADY;
wire [0:0] saxiacprready = (_TECHMAP_CONSTMSK_SAXIACPRREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPRREADY_ === 1'd0) ? 1'b0 : SAXIACPRREADY;
wire [63:0] saxiacpwdata = (_TECHMAP_CONSTMSK_SAXIACPWDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIACPWDATA_ === 64'd0) ? 64'b0 : SAXIACPWDATA;
wire [2:0] saxiacpwid = (_TECHMAP_CONSTMSK_SAXIACPWID_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPWID_ === 3'd0) ? 3'b0 : SAXIACPWID;
wire [0:0] saxiacpwlast = (_TECHMAP_CONSTMSK_SAXIACPWLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPWLAST_ === 1'd0) ? 1'b0 : SAXIACPWLAST;
wire [7:0] saxiacpwstrb = (_TECHMAP_CONSTMSK_SAXIACPWSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIACPWSTRB_ === 8'd0) ? 8'b0 : SAXIACPWSTRB;
wire [0:0] saxiacpwvalid = (_TECHMAP_CONSTMSK_SAXIACPWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPWVALID_ === 1'd0) ? 1'b0 : SAXIACPWVALID;
wire [0:0] saxigp0aclk = (_TECHMAP_CONSTMSK_SAXIGP0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0ACLK_ === 1'd0) ? 1'b0 : SAXIGP0ACLK;
wire [31:0] saxigp0araddr = (_TECHMAP_CONSTMSK_SAXIGP0ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARADDR_ === 32'd0) ? 32'b0 : SAXIGP0ARADDR;
wire [1:0] saxigp0arburst = (_TECHMAP_CONSTMSK_SAXIGP0ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARBURST_ === 2'd0) ? 2'b0 : SAXIGP0ARBURST;
wire [3:0] saxigp0arcache = (_TECHMAP_CONSTMSK_SAXIGP0ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARCACHE_ === 4'd0) ? 4'b0 : SAXIGP0ARCACHE;
wire [5:0] saxigp0arid = (_TECHMAP_CONSTMSK_SAXIGP0ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARID_ === 6'd0) ? 6'b0 : SAXIGP0ARID;
wire [3:0] saxigp0arlen = (_TECHMAP_CONSTMSK_SAXIGP0ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARLEN_ === 4'd0) ? 4'b0 : SAXIGP0ARLEN;
wire [1:0] saxigp0arlock = (_TECHMAP_CONSTMSK_SAXIGP0ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARLOCK_ === 2'd0) ? 2'b0 : SAXIGP0ARLOCK;
wire [2:0] saxigp0arprot = (_TECHMAP_CONSTMSK_SAXIGP0ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARPROT_ === 3'd0) ? 3'b0 : SAXIGP0ARPROT;
wire [3:0] saxigp0arqos = (_TECHMAP_CONSTMSK_SAXIGP0ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARQOS_ === 4'd0) ? 4'b0 : SAXIGP0ARQOS;
wire [1:0] saxigp0arsize = (_TECHMAP_CONSTMSK_SAXIGP0ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARSIZE_ === 2'd0) ? 2'b0 : SAXIGP0ARSIZE;
wire [0:0] saxigp0arvalid = (_TECHMAP_CONSTMSK_SAXIGP0ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARVALID_ === 1'd0) ? 1'b0 : SAXIGP0ARVALID;
wire [31:0] saxigp0awaddr = (_TECHMAP_CONSTMSK_SAXIGP0AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWADDR_ === 32'd0) ? 32'b0 : SAXIGP0AWADDR;
wire [1:0] saxigp0awburst = (_TECHMAP_CONSTMSK_SAXIGP0AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWBURST_ === 2'd0) ? 2'b0 : SAXIGP0AWBURST;
wire [3:0] saxigp0awcache = (_TECHMAP_CONSTMSK_SAXIGP0AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWCACHE_ === 4'd0) ? 4'b0 : SAXIGP0AWCACHE;
wire [5:0] saxigp0awid = (_TECHMAP_CONSTMSK_SAXIGP0AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWID_ === 6'd0) ? 6'b0 : SAXIGP0AWID;
wire [3:0] saxigp0awlen = (_TECHMAP_CONSTMSK_SAXIGP0AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWLEN_ === 4'd0) ? 4'b0 : SAXIGP0AWLEN;
wire [1:0] saxigp0awlock = (_TECHMAP_CONSTMSK_SAXIGP0AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWLOCK_ === 2'd0) ? 2'b0 : SAXIGP0AWLOCK;
wire [2:0] saxigp0awprot = (_TECHMAP_CONSTMSK_SAXIGP0AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWPROT_ === 3'd0) ? 3'b0 : SAXIGP0AWPROT;
wire [3:0] saxigp0awqos = (_TECHMAP_CONSTMSK_SAXIGP0AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWQOS_ === 4'd0) ? 4'b0 : SAXIGP0AWQOS;
wire [1:0] saxigp0awsize = (_TECHMAP_CONSTMSK_SAXIGP0AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWSIZE_ === 2'd0) ? 2'b0 : SAXIGP0AWSIZE;
wire [0:0] saxigp0awvalid = (_TECHMAP_CONSTMSK_SAXIGP0AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWVALID_ === 1'd0) ? 1'b0 : SAXIGP0AWVALID;
wire [0:0] saxigp0bready = (_TECHMAP_CONSTMSK_SAXIGP0BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0BREADY_ === 1'd0) ? 1'b0 : SAXIGP0BREADY;
wire [0:0] saxigp0rready = (_TECHMAP_CONSTMSK_SAXIGP0RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0RREADY_ === 1'd0) ? 1'b0 : SAXIGP0RREADY;
wire [31:0] saxigp0wdata = (_TECHMAP_CONSTMSK_SAXIGP0WDATA_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP0WDATA_ === 32'd0) ? 32'b0 : SAXIGP0WDATA;
wire [5:0] saxigp0wid = (_TECHMAP_CONSTMSK_SAXIGP0WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP0WID_ === 6'd0) ? 6'b0 : SAXIGP0WID;
wire [0:0] saxigp0wlast = (_TECHMAP_CONSTMSK_SAXIGP0WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0WLAST_ === 1'd0) ? 1'b0 : SAXIGP0WLAST;
wire [3:0] saxigp0wstrb = (_TECHMAP_CONSTMSK_SAXIGP0WSTRB_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0WSTRB_ === 4'd0) ? 4'b0 : SAXIGP0WSTRB;
wire [0:0] saxigp0wvalid = (_TECHMAP_CONSTMSK_SAXIGP0WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0WVALID_ === 1'd0) ? 1'b0 : SAXIGP0WVALID;
wire [0:0] saxigp1aclk = (_TECHMAP_CONSTMSK_SAXIGP1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1ACLK_ === 1'd0) ? 1'b0 : SAXIGP1ACLK;
wire [31:0] saxigp1araddr = (_TECHMAP_CONSTMSK_SAXIGP1ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARADDR_ === 32'd0) ? 32'b0 : SAXIGP1ARADDR;
wire [1:0] saxigp1arburst = (_TECHMAP_CONSTMSK_SAXIGP1ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARBURST_ === 2'd0) ? 2'b0 : SAXIGP1ARBURST;
wire [3:0] saxigp1arcache = (_TECHMAP_CONSTMSK_SAXIGP1ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARCACHE_ === 4'd0) ? 4'b0 : SAXIGP1ARCACHE;
wire [5:0] saxigp1arid = (_TECHMAP_CONSTMSK_SAXIGP1ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARID_ === 6'd0) ? 6'b0 : SAXIGP1ARID;
wire [3:0] saxigp1arlen = (_TECHMAP_CONSTMSK_SAXIGP1ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARLEN_ === 4'd0) ? 4'b0 : SAXIGP1ARLEN;
wire [1:0] saxigp1arlock = (_TECHMAP_CONSTMSK_SAXIGP1ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARLOCK_ === 2'd0) ? 2'b0 : SAXIGP1ARLOCK;
wire [2:0] saxigp1arprot = (_TECHMAP_CONSTMSK_SAXIGP1ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARPROT_ === 3'd0) ? 3'b0 : SAXIGP1ARPROT;
wire [3:0] saxigp1arqos = (_TECHMAP_CONSTMSK_SAXIGP1ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARQOS_ === 4'd0) ? 4'b0 : SAXIGP1ARQOS;
wire [1:0] saxigp1arsize = (_TECHMAP_CONSTMSK_SAXIGP1ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARSIZE_ === 2'd0) ? 2'b0 : SAXIGP1ARSIZE;
wire [0:0] saxigp1arvalid = (_TECHMAP_CONSTMSK_SAXIGP1ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARVALID_ === 1'd0) ? 1'b0 : SAXIGP1ARVALID;
wire [31:0] saxigp1awaddr = (_TECHMAP_CONSTMSK_SAXIGP1AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWADDR_ === 32'd0) ? 32'b0 : SAXIGP1AWADDR;
wire [1:0] saxigp1awburst = (_TECHMAP_CONSTMSK_SAXIGP1AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWBURST_ === 2'd0) ? 2'b0 : SAXIGP1AWBURST;
wire [3:0] saxigp1awcache = (_TECHMAP_CONSTMSK_SAXIGP1AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWCACHE_ === 4'd0) ? 4'b0 : SAXIGP1AWCACHE;
wire [5:0] saxigp1awid = (_TECHMAP_CONSTMSK_SAXIGP1AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWID_ === 6'd0) ? 6'b0 : SAXIGP1AWID;
wire [3:0] saxigp1awlen = (_TECHMAP_CONSTMSK_SAXIGP1AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWLEN_ === 4'd0) ? 4'b0 : SAXIGP1AWLEN;
wire [1:0] saxigp1awlock = (_TECHMAP_CONSTMSK_SAXIGP1AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWLOCK_ === 2'd0) ? 2'b0 : SAXIGP1AWLOCK;
wire [2:0] saxigp1awprot = (_TECHMAP_CONSTMSK_SAXIGP1AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWPROT_ === 3'd0) ? 3'b0 : SAXIGP1AWPROT;
wire [3:0] saxigp1awqos = (_TECHMAP_CONSTMSK_SAXIGP1AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWQOS_ === 4'd0) ? 4'b0 : SAXIGP1AWQOS;
wire [1:0] saxigp1awsize = (_TECHMAP_CONSTMSK_SAXIGP1AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWSIZE_ === 2'd0) ? 2'b0 : SAXIGP1AWSIZE;
wire [0:0] saxigp1awvalid = (_TECHMAP_CONSTMSK_SAXIGP1AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWVALID_ === 1'd0) ? 1'b0 : SAXIGP1AWVALID;
wire [0:0] saxigp1bready = (_TECHMAP_CONSTMSK_SAXIGP1BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1BREADY_ === 1'd0) ? 1'b0 : SAXIGP1BREADY;
wire [0:0] saxigp1rready = (_TECHMAP_CONSTMSK_SAXIGP1RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1RREADY_ === 1'd0) ? 1'b0 : SAXIGP1RREADY;
wire [31:0] saxigp1wdata = (_TECHMAP_CONSTMSK_SAXIGP1WDATA_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP1WDATA_ === 32'd0) ? 32'b0 : SAXIGP1WDATA;
wire [5:0] saxigp1wid = (_TECHMAP_CONSTMSK_SAXIGP1WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP1WID_ === 6'd0) ? 6'b0 : SAXIGP1WID;
wire [0:0] saxigp1wlast = (_TECHMAP_CONSTMSK_SAXIGP1WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1WLAST_ === 1'd0) ? 1'b0 : SAXIGP1WLAST;
wire [3:0] saxigp1wstrb = (_TECHMAP_CONSTMSK_SAXIGP1WSTRB_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1WSTRB_ === 4'd0) ? 4'b0 : SAXIGP1WSTRB;
wire [0:0] saxigp1wvalid = (_TECHMAP_CONSTMSK_SAXIGP1WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1WVALID_ === 1'd0) ? 1'b0 : SAXIGP1WVALID;
wire [0:0] saxihp0aclk = (_TECHMAP_CONSTMSK_SAXIHP0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0ACLK_ === 1'd0) ? 1'b0 : SAXIHP0ACLK;
wire [31:0] saxihp0araddr = (_TECHMAP_CONSTMSK_SAXIHP0ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARADDR_ === 32'd0) ? 32'b0 : SAXIHP0ARADDR;
wire [1:0] saxihp0arburst = (_TECHMAP_CONSTMSK_SAXIHP0ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARBURST_ === 2'd0) ? 2'b0 : SAXIHP0ARBURST;
wire [3:0] saxihp0arcache = (_TECHMAP_CONSTMSK_SAXIHP0ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP0ARCACHE;
wire [5:0] saxihp0arid = (_TECHMAP_CONSTMSK_SAXIHP0ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARID_ === 6'd0) ? 6'b0 : SAXIHP0ARID;
wire [3:0] saxihp0arlen = (_TECHMAP_CONSTMSK_SAXIHP0ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARLEN_ === 4'd0) ? 4'b0 : SAXIHP0ARLEN;
wire [1:0] saxihp0arlock = (_TECHMAP_CONSTMSK_SAXIHP0ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP0ARLOCK;
wire [2:0] saxihp0arprot = (_TECHMAP_CONSTMSK_SAXIHP0ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARPROT_ === 3'd0) ? 3'b0 : SAXIHP0ARPROT;
wire [3:0] saxihp0arqos = (_TECHMAP_CONSTMSK_SAXIHP0ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARQOS_ === 4'd0) ? 4'b0 : SAXIHP0ARQOS;
wire [1:0] saxihp0arsize = (_TECHMAP_CONSTMSK_SAXIHP0ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP0ARSIZE;
wire [0:0] saxihp0arvalid = (_TECHMAP_CONSTMSK_SAXIHP0ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARVALID_ === 1'd0) ? 1'b0 : SAXIHP0ARVALID;
wire [31:0] saxihp0awaddr = (_TECHMAP_CONSTMSK_SAXIHP0AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWADDR_ === 32'd0) ? 32'b0 : SAXIHP0AWADDR;
wire [1:0] saxihp0awburst = (_TECHMAP_CONSTMSK_SAXIHP0AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWBURST_ === 2'd0) ? 2'b0 : SAXIHP0AWBURST;
wire [3:0] saxihp0awcache = (_TECHMAP_CONSTMSK_SAXIHP0AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP0AWCACHE;
wire [5:0] saxihp0awid = (_TECHMAP_CONSTMSK_SAXIHP0AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWID_ === 6'd0) ? 6'b0 : SAXIHP0AWID;
wire [3:0] saxihp0awlen = (_TECHMAP_CONSTMSK_SAXIHP0AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWLEN_ === 4'd0) ? 4'b0 : SAXIHP0AWLEN;
wire [1:0] saxihp0awlock = (_TECHMAP_CONSTMSK_SAXIHP0AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP0AWLOCK;
wire [2:0] saxihp0awprot = (_TECHMAP_CONSTMSK_SAXIHP0AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWPROT_ === 3'd0) ? 3'b0 : SAXIHP0AWPROT;
wire [3:0] saxihp0awqos = (_TECHMAP_CONSTMSK_SAXIHP0AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWQOS_ === 4'd0) ? 4'b0 : SAXIHP0AWQOS;
wire [1:0] saxihp0awsize = (_TECHMAP_CONSTMSK_SAXIHP0AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP0AWSIZE;
wire [0:0] saxihp0awvalid = (_TECHMAP_CONSTMSK_SAXIHP0AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWVALID_ === 1'd0) ? 1'b0 : SAXIHP0AWVALID;
wire [0:0] saxihp0bready = (_TECHMAP_CONSTMSK_SAXIHP0BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0BREADY_ === 1'd0) ? 1'b0 : SAXIHP0BREADY;
wire [0:0] saxihp0rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP0RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP0RDISSUECAP1EN;
wire [0:0] saxihp0rready = (_TECHMAP_CONSTMSK_SAXIHP0RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0RREADY_ === 1'd0) ? 1'b0 : SAXIHP0RREADY;
wire [63:0] saxihp0wdata = (_TECHMAP_CONSTMSK_SAXIHP0WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP0WDATA_ === 64'd0) ? 64'b0 : SAXIHP0WDATA;
wire [5:0] saxihp0wid = (_TECHMAP_CONSTMSK_SAXIHP0WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP0WID_ === 6'd0) ? 6'b0 : SAXIHP0WID;
wire [0:0] saxihp0wlast = (_TECHMAP_CONSTMSK_SAXIHP0WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0WLAST_ === 1'd0) ? 1'b0 : SAXIHP0WLAST;
wire [0:0] saxihp0wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP0WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP0WRISSUECAP1EN;
wire [7:0] saxihp0wstrb = (_TECHMAP_CONSTMSK_SAXIHP0WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP0WSTRB_ === 8'd0) ? 8'b0 : SAXIHP0WSTRB;
wire [0:0] saxihp0wvalid = (_TECHMAP_CONSTMSK_SAXIHP0WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0WVALID_ === 1'd0) ? 1'b0 : SAXIHP0WVALID;
wire [0:0] saxihp1aclk = (_TECHMAP_CONSTMSK_SAXIHP1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1ACLK_ === 1'd0) ? 1'b0 : SAXIHP1ACLK;
wire [31:0] saxihp1araddr = (_TECHMAP_CONSTMSK_SAXIHP1ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARADDR_ === 32'd0) ? 32'b0 : SAXIHP1ARADDR;
wire [1:0] saxihp1arburst = (_TECHMAP_CONSTMSK_SAXIHP1ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARBURST_ === 2'd0) ? 2'b0 : SAXIHP1ARBURST;
wire [3:0] saxihp1arcache = (_TECHMAP_CONSTMSK_SAXIHP1ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP1ARCACHE;
wire [5:0] saxihp1arid = (_TECHMAP_CONSTMSK_SAXIHP1ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARID_ === 6'd0) ? 6'b0 : SAXIHP1ARID;
wire [3:0] saxihp1arlen = (_TECHMAP_CONSTMSK_SAXIHP1ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARLEN_ === 4'd0) ? 4'b0 : SAXIHP1ARLEN;
wire [1:0] saxihp1arlock = (_TECHMAP_CONSTMSK_SAXIHP1ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP1ARLOCK;
wire [2:0] saxihp1arprot = (_TECHMAP_CONSTMSK_SAXIHP1ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARPROT_ === 3'd0) ? 3'b0 : SAXIHP1ARPROT;
wire [3:0] saxihp1arqos = (_TECHMAP_CONSTMSK_SAXIHP1ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARQOS_ === 4'd0) ? 4'b0 : SAXIHP1ARQOS;
wire [1:0] saxihp1arsize = (_TECHMAP_CONSTMSK_SAXIHP1ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP1ARSIZE;
wire [0:0] saxihp1arvalid = (_TECHMAP_CONSTMSK_SAXIHP1ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARVALID_ === 1'd0) ? 1'b0 : SAXIHP1ARVALID;
wire [31:0] saxihp1awaddr = (_TECHMAP_CONSTMSK_SAXIHP1AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWADDR_ === 32'd0) ? 32'b0 : SAXIHP1AWADDR;
wire [1:0] saxihp1awburst = (_TECHMAP_CONSTMSK_SAXIHP1AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWBURST_ === 2'd0) ? 2'b0 : SAXIHP1AWBURST;
wire [3:0] saxihp1awcache = (_TECHMAP_CONSTMSK_SAXIHP1AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP1AWCACHE;
wire [5:0] saxihp1awid = (_TECHMAP_CONSTMSK_SAXIHP1AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWID_ === 6'd0) ? 6'b0 : SAXIHP1AWID;
wire [3:0] saxihp1awlen = (_TECHMAP_CONSTMSK_SAXIHP1AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWLEN_ === 4'd0) ? 4'b0 : SAXIHP1AWLEN;
wire [1:0] saxihp1awlock = (_TECHMAP_CONSTMSK_SAXIHP1AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP1AWLOCK;
wire [2:0] saxihp1awprot = (_TECHMAP_CONSTMSK_SAXIHP1AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWPROT_ === 3'd0) ? 3'b0 : SAXIHP1AWPROT;
wire [3:0] saxihp1awqos = (_TECHMAP_CONSTMSK_SAXIHP1AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWQOS_ === 4'd0) ? 4'b0 : SAXIHP1AWQOS;
wire [1:0] saxihp1awsize = (_TECHMAP_CONSTMSK_SAXIHP1AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP1AWSIZE;
wire [0:0] saxihp1awvalid = (_TECHMAP_CONSTMSK_SAXIHP1AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWVALID_ === 1'd0) ? 1'b0 : SAXIHP1AWVALID;
wire [0:0] saxihp1bready = (_TECHMAP_CONSTMSK_SAXIHP1BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1BREADY_ === 1'd0) ? 1'b0 : SAXIHP1BREADY;
wire [0:0] saxihp1rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP1RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP1RDISSUECAP1EN;
wire [0:0] saxihp1rready = (_TECHMAP_CONSTMSK_SAXIHP1RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1RREADY_ === 1'd0) ? 1'b0 : SAXIHP1RREADY;
wire [63:0] saxihp1wdata = (_TECHMAP_CONSTMSK_SAXIHP1WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP1WDATA_ === 64'd0) ? 64'b0 : SAXIHP1WDATA;
wire [5:0] saxihp1wid = (_TECHMAP_CONSTMSK_SAXIHP1WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP1WID_ === 6'd0) ? 6'b0 : SAXIHP1WID;
wire [0:0] saxihp1wlast = (_TECHMAP_CONSTMSK_SAXIHP1WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1WLAST_ === 1'd0) ? 1'b0 : SAXIHP1WLAST;
wire [0:0] saxihp1wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP1WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP1WRISSUECAP1EN;
wire [7:0] saxihp1wstrb = (_TECHMAP_CONSTMSK_SAXIHP1WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP1WSTRB_ === 8'd0) ? 8'b0 : SAXIHP1WSTRB;
wire [0:0] saxihp1wvalid = (_TECHMAP_CONSTMSK_SAXIHP1WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1WVALID_ === 1'd0) ? 1'b0 : SAXIHP1WVALID;
wire [0:0] saxihp2aclk = (_TECHMAP_CONSTMSK_SAXIHP2ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2ACLK_ === 1'd0) ? 1'b0 : SAXIHP2ACLK;
wire [31:0] saxihp2araddr = (_TECHMAP_CONSTMSK_SAXIHP2ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARADDR_ === 32'd0) ? 32'b0 : SAXIHP2ARADDR;
wire [1:0] saxihp2arburst = (_TECHMAP_CONSTMSK_SAXIHP2ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARBURST_ === 2'd0) ? 2'b0 : SAXIHP2ARBURST;
wire [3:0] saxihp2arcache = (_TECHMAP_CONSTMSK_SAXIHP2ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP2ARCACHE;
wire [5:0] saxihp2arid = (_TECHMAP_CONSTMSK_SAXIHP2ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARID_ === 6'd0) ? 6'b0 : SAXIHP2ARID;
wire [3:0] saxihp2arlen = (_TECHMAP_CONSTMSK_SAXIHP2ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARLEN_ === 4'd0) ? 4'b0 : SAXIHP2ARLEN;
wire [1:0] saxihp2arlock = (_TECHMAP_CONSTMSK_SAXIHP2ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP2ARLOCK;
wire [2:0] saxihp2arprot = (_TECHMAP_CONSTMSK_SAXIHP2ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARPROT_ === 3'd0) ? 3'b0 : SAXIHP2ARPROT;
wire [3:0] saxihp2arqos = (_TECHMAP_CONSTMSK_SAXIHP2ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARQOS_ === 4'd0) ? 4'b0 : SAXIHP2ARQOS;
wire [1:0] saxihp2arsize = (_TECHMAP_CONSTMSK_SAXIHP2ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP2ARSIZE;
wire [0:0] saxihp2arvalid = (_TECHMAP_CONSTMSK_SAXIHP2ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARVALID_ === 1'd0) ? 1'b0 : SAXIHP2ARVALID;
wire [31:0] saxihp2awaddr = (_TECHMAP_CONSTMSK_SAXIHP2AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWADDR_ === 32'd0) ? 32'b0 : SAXIHP2AWADDR;
wire [1:0] saxihp2awburst = (_TECHMAP_CONSTMSK_SAXIHP2AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWBURST_ === 2'd0) ? 2'b0 : SAXIHP2AWBURST;
wire [3:0] saxihp2awcache = (_TECHMAP_CONSTMSK_SAXIHP2AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP2AWCACHE;
wire [5:0] saxihp2awid = (_TECHMAP_CONSTMSK_SAXIHP2AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWID_ === 6'd0) ? 6'b0 : SAXIHP2AWID;
wire [3:0] saxihp2awlen = (_TECHMAP_CONSTMSK_SAXIHP2AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWLEN_ === 4'd0) ? 4'b0 : SAXIHP2AWLEN;
wire [1:0] saxihp2awlock = (_TECHMAP_CONSTMSK_SAXIHP2AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP2AWLOCK;
wire [2:0] saxihp2awprot = (_TECHMAP_CONSTMSK_SAXIHP2AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWPROT_ === 3'd0) ? 3'b0 : SAXIHP2AWPROT;
wire [3:0] saxihp2awqos = (_TECHMAP_CONSTMSK_SAXIHP2AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWQOS_ === 4'd0) ? 4'b0 : SAXIHP2AWQOS;
wire [1:0] saxihp2awsize = (_TECHMAP_CONSTMSK_SAXIHP2AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP2AWSIZE;
wire [0:0] saxihp2awvalid = (_TECHMAP_CONSTMSK_SAXIHP2AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWVALID_ === 1'd0) ? 1'b0 : SAXIHP2AWVALID;
wire [0:0] saxihp2bready = (_TECHMAP_CONSTMSK_SAXIHP2BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2BREADY_ === 1'd0) ? 1'b0 : SAXIHP2BREADY;
wire [0:0] saxihp2rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP2RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP2RDISSUECAP1EN;
wire [0:0] saxihp2rready = (_TECHMAP_CONSTMSK_SAXIHP2RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2RREADY_ === 1'd0) ? 1'b0 : SAXIHP2RREADY;
wire [63:0] saxihp2wdata = (_TECHMAP_CONSTMSK_SAXIHP2WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP2WDATA_ === 64'd0) ? 64'b0 : SAXIHP2WDATA;
wire [5:0] saxihp2wid = (_TECHMAP_CONSTMSK_SAXIHP2WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP2WID_ === 6'd0) ? 6'b0 : SAXIHP2WID;
wire [0:0] saxihp2wlast = (_TECHMAP_CONSTMSK_SAXIHP2WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2WLAST_ === 1'd0) ? 1'b0 : SAXIHP2WLAST;
wire [0:0] saxihp2wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP2WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP2WRISSUECAP1EN;
wire [7:0] saxihp2wstrb = (_TECHMAP_CONSTMSK_SAXIHP2WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP2WSTRB_ === 8'd0) ? 8'b0 : SAXIHP2WSTRB;
wire [0:0] saxihp2wvalid = (_TECHMAP_CONSTMSK_SAXIHP2WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2WVALID_ === 1'd0) ? 1'b0 : SAXIHP2WVALID;
wire [0:0] saxihp3aclk = (_TECHMAP_CONSTMSK_SAXIHP3ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3ACLK_ === 1'd0) ? 1'b0 : SAXIHP3ACLK;
wire [31:0] saxihp3araddr = (_TECHMAP_CONSTMSK_SAXIHP3ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARADDR_ === 32'd0) ? 32'b0 : SAXIHP3ARADDR;
wire [1:0] saxihp3arburst = (_TECHMAP_CONSTMSK_SAXIHP3ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARBURST_ === 2'd0) ? 2'b0 : SAXIHP3ARBURST;
wire [3:0] saxihp3arcache = (_TECHMAP_CONSTMSK_SAXIHP3ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP3ARCACHE;
wire [5:0] saxihp3arid = (_TECHMAP_CONSTMSK_SAXIHP3ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARID_ === 6'd0) ? 6'b0 : SAXIHP3ARID;
wire [3:0] saxihp3arlen = (_TECHMAP_CONSTMSK_SAXIHP3ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARLEN_ === 4'd0) ? 4'b0 : SAXIHP3ARLEN;
wire [1:0] saxihp3arlock = (_TECHMAP_CONSTMSK_SAXIHP3ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP3ARLOCK;
wire [2:0] saxihp3arprot = (_TECHMAP_CONSTMSK_SAXIHP3ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARPROT_ === 3'd0) ? 3'b0 : SAXIHP3ARPROT;
wire [3:0] saxihp3arqos = (_TECHMAP_CONSTMSK_SAXIHP3ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARQOS_ === 4'd0) ? 4'b0 : SAXIHP3ARQOS;
wire [1:0] saxihp3arsize = (_TECHMAP_CONSTMSK_SAXIHP3ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP3ARSIZE;
wire [0:0] saxihp3arvalid = (_TECHMAP_CONSTMSK_SAXIHP3ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARVALID_ === 1'd0) ? 1'b0 : SAXIHP3ARVALID;
wire [31:0] saxihp3awaddr = (_TECHMAP_CONSTMSK_SAXIHP3AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWADDR_ === 32'd0) ? 32'b0 : SAXIHP3AWADDR;
wire [1:0] saxihp3awburst = (_TECHMAP_CONSTMSK_SAXIHP3AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWBURST_ === 2'd0) ? 2'b0 : SAXIHP3AWBURST;
wire [3:0] saxihp3awcache = (_TECHMAP_CONSTMSK_SAXIHP3AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP3AWCACHE;
wire [5:0] saxihp3awid = (_TECHMAP_CONSTMSK_SAXIHP3AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWID_ === 6'd0) ? 6'b0 : SAXIHP3AWID;
wire [3:0] saxihp3awlen = (_TECHMAP_CONSTMSK_SAXIHP3AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWLEN_ === 4'd0) ? 4'b0 : SAXIHP3AWLEN;
wire [1:0] saxihp3awlock = (_TECHMAP_CONSTMSK_SAXIHP3AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP3AWLOCK;
wire [2:0] saxihp3awprot = (_TECHMAP_CONSTMSK_SAXIHP3AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWPROT_ === 3'd0) ? 3'b0 : SAXIHP3AWPROT;
wire [3:0] saxihp3awqos = (_TECHMAP_CONSTMSK_SAXIHP3AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWQOS_ === 4'd0) ? 4'b0 : SAXIHP3AWQOS;
wire [1:0] saxihp3awsize = (_TECHMAP_CONSTMSK_SAXIHP3AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP3AWSIZE;
wire [0:0] saxihp3awvalid = (_TECHMAP_CONSTMSK_SAXIHP3AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWVALID_ === 1'd0) ? 1'b0 : SAXIHP3AWVALID;
wire [0:0] saxihp3bready = (_TECHMAP_CONSTMSK_SAXIHP3BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3BREADY_ === 1'd0) ? 1'b0 : SAXIHP3BREADY;
wire [0:0] saxihp3rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP3RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP3RDISSUECAP1EN;
wire [0:0] saxihp3rready = (_TECHMAP_CONSTMSK_SAXIHP3RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3RREADY_ === 1'd0) ? 1'b0 : SAXIHP3RREADY;
wire [63:0] saxihp3wdata = (_TECHMAP_CONSTMSK_SAXIHP3WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP3WDATA_ === 64'd0) ? 64'b0 : SAXIHP3WDATA;
wire [5:0] saxihp3wid = (_TECHMAP_CONSTMSK_SAXIHP3WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP3WID_ === 6'd0) ? 6'b0 : SAXIHP3WID;
wire [0:0] saxihp3wlast = (_TECHMAP_CONSTMSK_SAXIHP3WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3WLAST_ === 1'd0) ? 1'b0 : SAXIHP3WLAST;
wire [0:0] saxihp3wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP3WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP3WRISSUECAP1EN;
wire [7:0] saxihp3wstrb = (_TECHMAP_CONSTMSK_SAXIHP3WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP3WSTRB_ === 8'd0) ? 8'b0 : SAXIHP3WSTRB;
wire [0:0] saxihp3wvalid = (_TECHMAP_CONSTMSK_SAXIHP3WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3WVALID_ === 1'd0) ? 1'b0 : SAXIHP3WVALID;
// Replacement cell.
PS7_VPR _TECHMAP_REPLACE_ (
.DDRARB (ddrarb),
.DMA0ACLK (dma0aclk),
.DMA0DAREADY (dma0daready),
.DMA0DATYPE (DMA0DATYPE),
.DMA0DAVALID (DMA0DAVALID),
.DMA0DRLAST (dma0drlast),
.DMA0DRREADY (DMA0DRREADY),
.DMA0DRTYPE (dma0drtype),
.DMA0DRVALID (dma0drvalid),
.DMA0RSTN (DMA0RSTN),
.DMA1ACLK (dma1aclk),
.DMA1DAREADY (dma1daready),
.DMA1DATYPE (DMA1DATYPE),
.DMA1DAVALID (DMA1DAVALID),
.DMA1DRLAST (dma1drlast),
.DMA1DRREADY (DMA1DRREADY),
.DMA1DRTYPE (dma1drtype),
.DMA1DRVALID (dma1drvalid),
.DMA1RSTN (DMA1RSTN),
.DMA2ACLK (dma2aclk),
.DMA2DAREADY (dma2daready),
.DMA2DATYPE (DMA2DATYPE),
.DMA2DAVALID (DMA2DAVALID),
.DMA2DRLAST (dma2drlast),
.DMA2DRREADY (DMA2DRREADY),
.DMA2DRTYPE (dma2drtype),
.DMA2DRVALID (dma2drvalid),
.DMA2RSTN (DMA2RSTN),
.DMA3ACLK (dma3aclk),
.DMA3DAREADY (dma3daready),
.DMA3DATYPE (DMA3DATYPE),
.DMA3DAVALID (DMA3DAVALID),
.DMA3DRLAST (dma3drlast),
.DMA3DRREADY (DMA3DRREADY),
.DMA3DRTYPE (dma3drtype),
.DMA3DRVALID (dma3drvalid),
.DMA3RSTN (DMA3RSTN),
.EMIOCAN0PHYRX (emiocan0phyrx),
.EMIOCAN0PHYTX (EMIOCAN0PHYTX),
.EMIOCAN1PHYRX (emiocan1phyrx),
.EMIOCAN1PHYTX (EMIOCAN1PHYTX),
.EMIOENET0EXTINTIN (emioenet0extintin),
.EMIOENET0GMIICOL (emioenet0gmiicol),
.EMIOENET0GMIICRS (emioenet0gmiicrs),
.EMIOENET0GMIIRXCLK (emioenet0gmiirxclk),
.EMIOENET0GMIIRXD (emioenet0gmiirxd),
.EMIOENET0GMIIRXDV (emioenet0gmiirxdv),
.EMIOENET0GMIIRXER (emioenet0gmiirxer),
.EMIOENET0GMIITXCLK (emioenet0gmiitxclk),
.EMIOENET0GMIITXD (EMIOENET0GMIITXD),
.EMIOENET0GMIITXEN (EMIOENET0GMIITXEN),
.EMIOENET0GMIITXER (EMIOENET0GMIITXER),
.EMIOENET0MDIOI (emioenet0mdioi),
.EMIOENET0MDIOMDC (EMIOENET0MDIOMDC),
.EMIOENET0MDIOO (EMIOENET0MDIOO),
.EMIOENET0MDIOTN (EMIOENET0MDIOTN),
.EMIOENET0PTPDELAYREQRX (EMIOENET0PTPDELAYREQRX),
.EMIOENET0PTPDELAYREQTX (EMIOENET0PTPDELAYREQTX),
.EMIOENET0PTPPDELAYREQRX (EMIOENET0PTPPDELAYREQRX),
.EMIOENET0PTPPDELAYREQTX (EMIOENET0PTPPDELAYREQTX),
.EMIOENET0PTPPDELAYRESPRX (EMIOENET0PTPPDELAYRESPRX),
.EMIOENET0PTPPDELAYRESPTX (EMIOENET0PTPPDELAYRESPTX),
.EMIOENET0PTPSYNCFRAMERX (EMIOENET0PTPSYNCFRAMERX),
.EMIOENET0PTPSYNCFRAMETX (EMIOENET0PTPSYNCFRAMETX),
.EMIOENET0SOFRX (EMIOENET0SOFRX),
.EMIOENET0SOFTX (EMIOENET0SOFTX),
.EMIOENET1EXTINTIN (emioenet1extintin),
.EMIOENET1GMIICOL (emioenet1gmiicol),
.EMIOENET1GMIICRS (emioenet1gmiicrs),
.EMIOENET1GMIIRXCLK (emioenet1gmiirxclk),
.EMIOENET1GMIIRXD (emioenet1gmiirxd),
.EMIOENET1GMIIRXDV (emioenet1gmiirxdv),
.EMIOENET1GMIIRXER (emioenet1gmiirxer),
.EMIOENET1GMIITXCLK (emioenet1gmiitxclk),
.EMIOENET1GMIITXD (EMIOENET1GMIITXD),
.EMIOENET1GMIITXEN (EMIOENET1GMIITXEN),
.EMIOENET1GMIITXER (EMIOENET1GMIITXER),
.EMIOENET1MDIOI (emioenet1mdioi),
.EMIOENET1MDIOMDC (EMIOENET1MDIOMDC),
.EMIOENET1MDIOO (EMIOENET1MDIOO),
.EMIOENET1MDIOTN (EMIOENET1MDIOTN),
.EMIOENET1PTPDELAYREQRX (EMIOENET1PTPDELAYREQRX),
.EMIOENET1PTPDELAYREQTX (EMIOENET1PTPDELAYREQTX),
.EMIOENET1PTPPDELAYREQRX (EMIOENET1PTPPDELAYREQRX),
.EMIOENET1PTPPDELAYREQTX (EMIOENET1PTPPDELAYREQTX),
.EMIOENET1PTPPDELAYRESPRX (EMIOENET1PTPPDELAYRESPRX),
.EMIOENET1PTPPDELAYRESPTX (EMIOENET1PTPPDELAYRESPTX),
.EMIOENET1PTPSYNCFRAMERX (EMIOENET1PTPSYNCFRAMERX),
.EMIOENET1PTPSYNCFRAMETX (EMIOENET1PTPSYNCFRAMETX),
.EMIOENET1SOFRX (EMIOENET1SOFRX),
.EMIOENET1SOFTX (EMIOENET1SOFTX),
.EMIOGPIOI (emiogpioi),
.EMIOGPIOO (EMIOGPIOO),
.EMIOGPIOTN (EMIOGPIOTN),
.EMIOI2C0SCLI (emioi2c0scli),
.EMIOI2C0SCLO (EMIOI2C0SCLO),
.EMIOI2C0SCLTN (EMIOI2C0SCLTN),
.EMIOI2C0SDAI (emioi2c0sdai),
.EMIOI2C0SDAO (EMIOI2C0SDAO),
.EMIOI2C0SDATN (EMIOI2C0SDATN),
.EMIOI2C1SCLI (emioi2c1scli),
.EMIOI2C1SCLO (EMIOI2C1SCLO),
.EMIOI2C1SCLTN (EMIOI2C1SCLTN),
.EMIOI2C1SDAI (emioi2c1sdai),
.EMIOI2C1SDAO (EMIOI2C1SDAO),
.EMIOI2C1SDATN (EMIOI2C1SDATN),
.EMIOPJTAGTCK (emiopjtagtck),
.EMIOPJTAGTDI (emiopjtagtdi),
.EMIOPJTAGTDO (EMIOPJTAGTDO),
.EMIOPJTAGTDTN (EMIOPJTAGTDTN),
.EMIOPJTAGTMS (emiopjtagtms),
.EMIOSDIO0BUSPOW (EMIOSDIO0BUSPOW),
.EMIOSDIO0BUSVOLT (EMIOSDIO0BUSVOLT),
.EMIOSDIO0CDN (emiosdio0cdn),
.EMIOSDIO0CLK (EMIOSDIO0CLK),
.EMIOSDIO0CLKFB (emiosdio0clkfb),
.EMIOSDIO0CMDI (emiosdio0cmdi),
.EMIOSDIO0CMDO (EMIOSDIO0CMDO),
.EMIOSDIO0CMDTN (EMIOSDIO0CMDTN),
.EMIOSDIO0DATAI (emiosdio0datai),
.EMIOSDIO0DATAO (EMIOSDIO0DATAO),
.EMIOSDIO0DATATN (EMIOSDIO0DATATN),
.EMIOSDIO0LED (EMIOSDIO0LED),
.EMIOSDIO0WP (emiosdio0wp),
.EMIOSDIO1BUSPOW (EMIOSDIO1BUSPOW),
.EMIOSDIO1BUSVOLT (EMIOSDIO1BUSVOLT),
.EMIOSDIO1CDN (emiosdio1cdn),
.EMIOSDIO1CLK (EMIOSDIO1CLK),
.EMIOSDIO1CLKFB (emiosdio1clkfb),
.EMIOSDIO1CMDI (emiosdio1cmdi),
.EMIOSDIO1CMDO (EMIOSDIO1CMDO),
.EMIOSDIO1CMDTN (EMIOSDIO1CMDTN),
.EMIOSDIO1DATAI (emiosdio1datai),
.EMIOSDIO1DATAO (EMIOSDIO1DATAO),
.EMIOSDIO1DATATN (EMIOSDIO1DATATN),
.EMIOSDIO1LED (EMIOSDIO1LED),
.EMIOSDIO1WP (emiosdio1wp),
.EMIOSPI0MI (emiospi0mi),
.EMIOSPI0MO (EMIOSPI0MO),
.EMIOSPI0MOTN (EMIOSPI0MOTN),
.EMIOSPI0SCLKI (emiospi0sclki),
.EMIOSPI0SCLKO (EMIOSPI0SCLKO),
.EMIOSPI0SCLKTN (EMIOSPI0SCLKTN),
.EMIOSPI0SI (emiospi0si),
.EMIOSPI0SO (EMIOSPI0SO),
.EMIOSPI0SSIN (emiospi0ssin),
.EMIOSPI0SSNTN (EMIOSPI0SSNTN),
.EMIOSPI0SSON (EMIOSPI0SSON),
.EMIOSPI0STN (EMIOSPI0STN),
.EMIOSPI1MI (emiospi1mi),
.EMIOSPI1MO (EMIOSPI1MO),
.EMIOSPI1MOTN (EMIOSPI1MOTN),
.EMIOSPI1SCLKI (emiospi1sclki),
.EMIOSPI1SCLKO (EMIOSPI1SCLKO),
.EMIOSPI1SCLKTN (EMIOSPI1SCLKTN),
.EMIOSPI1SI (emiospi1si),
.EMIOSPI1SO (EMIOSPI1SO),
.EMIOSPI1SSIN (emiospi1ssin),
.EMIOSPI1SSNTN (EMIOSPI1SSNTN),
.EMIOSPI1SSON (EMIOSPI1SSON),
.EMIOSPI1STN (EMIOSPI1STN),
.EMIOSRAMINTIN (emiosramintin),
.EMIOTRACECLK (emiotraceclk),
.EMIOTRACECTL (EMIOTRACECTL),
.EMIOTRACEDATA (EMIOTRACEDATA),
.EMIOTTC0CLKI (emiottc0clki),
.EMIOTTC0WAVEO (EMIOTTC0WAVEO),
.EMIOTTC1CLKI (emiottc1clki),
.EMIOTTC1WAVEO (EMIOTTC1WAVEO),
.EMIOUART0CTSN (emiouart0ctsn),
.EMIOUART0DCDN (emiouart0dcdn),
.EMIOUART0DSRN (emiouart0dsrn),
.EMIOUART0DTRN (EMIOUART0DTRN),
.EMIOUART0RIN (emiouart0rin),
.EMIOUART0RTSN (EMIOUART0RTSN),
.EMIOUART0RX (emiouart0rx),
.EMIOUART0TX (EMIOUART0TX),
.EMIOUART1CTSN (emiouart1ctsn),
.EMIOUART1DCDN (emiouart1dcdn),
.EMIOUART1DSRN (emiouart1dsrn),
.EMIOUART1DTRN (EMIOUART1DTRN),
.EMIOUART1RIN (emiouart1rin),
.EMIOUART1RTSN (EMIOUART1RTSN),
.EMIOUART1RX (emiouart1rx),
.EMIOUART1TX (EMIOUART1TX),
.EMIOUSB0PORTINDCTL (EMIOUSB0PORTINDCTL),
.EMIOUSB0VBUSPWRFAULT (emiousb0vbuspwrfault),
.EMIOUSB0VBUSPWRSELECT (EMIOUSB0VBUSPWRSELECT),
.EMIOUSB1PORTINDCTL (EMIOUSB1PORTINDCTL),
.EMIOUSB1VBUSPWRFAULT (emiousb1vbuspwrfault),
.EMIOUSB1VBUSPWRSELECT (EMIOUSB1VBUSPWRSELECT),
.EMIOWDTCLKI (emiowdtclki),
.EMIOWDTRSTO (EMIOWDTRSTO),
.EVENTEVENTI (eventeventi),
.EVENTEVENTO (EVENTEVENTO),
.EVENTSTANDBYWFE (EVENTSTANDBYWFE),
.EVENTSTANDBYWFI (EVENTSTANDBYWFI),
.FCLKCLK (FCLKCLK),
.FCLKCLKTRIGN (fclkclktrign),
.FCLKRESETN (FCLKRESETN),
.FPGAIDLEN (fpgaidlen),
.FTMDTRACEINATID (ftmdtraceinatid),
.FTMDTRACEINCLOCK (ftmdtraceinclock),
.FTMDTRACEINDATA (ftmdtraceindata),
.FTMDTRACEINVALID (ftmdtraceinvalid),
.FTMTF2PDEBUG (ftmtf2pdebug),
.FTMTF2PTRIG (ftmtf2ptrig),
.FTMTF2PTRIGACK (FTMTF2PTRIGACK),
.FTMTP2FDEBUG (FTMTP2FDEBUG),
.FTMTP2FTRIG (FTMTP2FTRIG),
.FTMTP2FTRIGACK (ftmtp2ftrigack),
.IRQF2P (irqf2p),
.IRQP2F (IRQP2F),
.MAXIGP0ACLK (maxigp0aclk),
.MAXIGP0ARADDR (MAXIGP0ARADDR),
.MAXIGP0ARBURST (MAXIGP0ARBURST),
.MAXIGP0ARCACHE (MAXIGP0ARCACHE),
.MAXIGP0ARESETN (MAXIGP0ARESETN),
.MAXIGP0ARID (MAXIGP0ARID),
.MAXIGP0ARLEN (MAXIGP0ARLEN),
.MAXIGP0ARLOCK (MAXIGP0ARLOCK),
.MAXIGP0ARPROT (MAXIGP0ARPROT),
.MAXIGP0ARQOS (MAXIGP0ARQOS),
.MAXIGP0ARREADY (maxigp0arready),
.MAXIGP0ARSIZE (MAXIGP0ARSIZE),
.MAXIGP0ARVALID (MAXIGP0ARVALID),
.MAXIGP0AWADDR (MAXIGP0AWADDR),
.MAXIGP0AWBURST (MAXIGP0AWBURST),
.MAXIGP0AWCACHE (MAXIGP0AWCACHE),
.MAXIGP0AWID (MAXIGP0AWID),
.MAXIGP0AWLEN (MAXIGP0AWLEN),
.MAXIGP0AWLOCK (MAXIGP0AWLOCK),
.MAXIGP0AWPROT (MAXIGP0AWPROT),
.MAXIGP0AWQOS (MAXIGP0AWQOS),
.MAXIGP0AWREADY (maxigp0awready),
.MAXIGP0AWSIZE (MAXIGP0AWSIZE),
.MAXIGP0AWVALID (MAXIGP0AWVALID),
.MAXIGP0BID (maxigp0bid),
.MAXIGP0BREADY (MAXIGP0BREADY),
.MAXIGP0BRESP (maxigp0bresp),
.MAXIGP0BVALID (maxigp0bvalid),
.MAXIGP0RDATA (maxigp0rdata),
.MAXIGP0RID (maxigp0rid),
.MAXIGP0RLAST (maxigp0rlast),
.MAXIGP0RREADY (MAXIGP0RREADY),
.MAXIGP0RRESP (maxigp0rresp),
.MAXIGP0RVALID (maxigp0rvalid),
.MAXIGP0WDATA (MAXIGP0WDATA),
.MAXIGP0WID (MAXIGP0WID),
.MAXIGP0WLAST (MAXIGP0WLAST),
.MAXIGP0WREADY (maxigp0wready),
.MAXIGP0WSTRB (MAXIGP0WSTRB),
.MAXIGP0WVALID (MAXIGP0WVALID),
.MAXIGP1ACLK (maxigp1aclk),
.MAXIGP1ARADDR (MAXIGP1ARADDR),
.MAXIGP1ARBURST (MAXIGP1ARBURST),
.MAXIGP1ARCACHE (MAXIGP1ARCACHE),
.MAXIGP1ARESETN (MAXIGP1ARESETN),
.MAXIGP1ARID (MAXIGP1ARID),
.MAXIGP1ARLEN (MAXIGP1ARLEN),
.MAXIGP1ARLOCK (MAXIGP1ARLOCK),
.MAXIGP1ARPROT (MAXIGP1ARPROT),
.MAXIGP1ARQOS (MAXIGP1ARQOS),
.MAXIGP1ARREADY (maxigp1arready),
.MAXIGP1ARSIZE (MAXIGP1ARSIZE),
.MAXIGP1ARVALID (MAXIGP1ARVALID),
.MAXIGP1AWADDR (MAXIGP1AWADDR),
.MAXIGP1AWBURST (MAXIGP1AWBURST),
.MAXIGP1AWCACHE (MAXIGP1AWCACHE),
.MAXIGP1AWID (MAXIGP1AWID),
.MAXIGP1AWLEN (MAXIGP1AWLEN),
.MAXIGP1AWLOCK (MAXIGP1AWLOCK),
.MAXIGP1AWPROT (MAXIGP1AWPROT),
.MAXIGP1AWQOS (MAXIGP1AWQOS),
.MAXIGP1AWREADY (maxigp1awready),
.MAXIGP1AWSIZE (MAXIGP1AWSIZE),
.MAXIGP1AWVALID (MAXIGP1AWVALID),
.MAXIGP1BID (maxigp1bid),
.MAXIGP1BREADY (MAXIGP1BREADY),
.MAXIGP1BRESP (maxigp1bresp),
.MAXIGP1BVALID (maxigp1bvalid),
.MAXIGP1RDATA (maxigp1rdata),
.MAXIGP1RID (maxigp1rid),
.MAXIGP1RLAST (maxigp1rlast),
.MAXIGP1RREADY (MAXIGP1RREADY),
.MAXIGP1RRESP (maxigp1rresp),
.MAXIGP1RVALID (maxigp1rvalid),
.MAXIGP1WDATA (MAXIGP1WDATA),
.MAXIGP1WID (MAXIGP1WID),
.MAXIGP1WLAST (MAXIGP1WLAST),
.MAXIGP1WREADY (maxigp1wready),
.MAXIGP1WSTRB (MAXIGP1WSTRB),
.MAXIGP1WVALID (MAXIGP1WVALID),
.SAXIACPACLK (saxiacpaclk),
.SAXIACPARADDR (saxiacparaddr),
.SAXIACPARBURST (saxiacparburst),
.SAXIACPARCACHE (saxiacparcache),
.SAXIACPARESETN (SAXIACPARESETN),
.SAXIACPARID (saxiacparid),
.SAXIACPARLEN (saxiacparlen),
.SAXIACPARLOCK (saxiacparlock),
.SAXIACPARPROT (saxiacparprot),
.SAXIACPARQOS (saxiacparqos),
.SAXIACPARREADY (SAXIACPARREADY),
.SAXIACPARSIZE (saxiacparsize),
.SAXIACPARUSER (saxiacparuser),
.SAXIACPARVALID (saxiacparvalid),
.SAXIACPAWADDR (saxiacpawaddr),
.SAXIACPAWBURST (saxiacpawburst),
.SAXIACPAWCACHE (saxiacpawcache),
.SAXIACPAWID (saxiacpawid),
.SAXIACPAWLEN (saxiacpawlen),
.SAXIACPAWLOCK (saxiacpawlock),
.SAXIACPAWPROT (saxiacpawprot),
.SAXIACPAWQOS (saxiacpawqos),
.SAXIACPAWREADY (SAXIACPAWREADY),
.SAXIACPAWSIZE (saxiacpawsize),
.SAXIACPAWUSER (saxiacpawuser),
.SAXIACPAWVALID (saxiacpawvalid),
.SAXIACPBID (SAXIACPBID),
.SAXIACPBREADY (saxiacpbready),
.SAXIACPBRESP (SAXIACPBRESP),
.SAXIACPBVALID (SAXIACPBVALID),
.SAXIACPRDATA (SAXIACPRDATA),
.SAXIACPRID (SAXIACPRID),
.SAXIACPRLAST (SAXIACPRLAST),
.SAXIACPRREADY (saxiacprready),
.SAXIACPRRESP (SAXIACPRRESP),
.SAXIACPRVALID (SAXIACPRVALID),
.SAXIACPWDATA (saxiacpwdata),
.SAXIACPWID (saxiacpwid),
.SAXIACPWLAST (saxiacpwlast),
.SAXIACPWREADY (SAXIACPWREADY),
.SAXIACPWSTRB (saxiacpwstrb),
.SAXIACPWVALID (saxiacpwvalid),
.SAXIGP0ACLK (saxigp0aclk),
.SAXIGP0ARADDR (saxigp0araddr),
.SAXIGP0ARBURST (saxigp0arburst),
.SAXIGP0ARCACHE (saxigp0arcache),
.SAXIGP0ARESETN (SAXIGP0ARESETN),
.SAXIGP0ARID (saxigp0arid),
.SAXIGP0ARLEN (saxigp0arlen),
.SAXIGP0ARLOCK (saxigp0arlock),
.SAXIGP0ARPROT (saxigp0arprot),
.SAXIGP0ARQOS (saxigp0arqos),
.SAXIGP0ARREADY (SAXIGP0ARREADY),
.SAXIGP0ARSIZE (saxigp0arsize),
.SAXIGP0ARVALID (saxigp0arvalid),
.SAXIGP0AWADDR (saxigp0awaddr),
.SAXIGP0AWBURST (saxigp0awburst),
.SAXIGP0AWCACHE (saxigp0awcache),
.SAXIGP0AWID (saxigp0awid),
.SAXIGP0AWLEN (saxigp0awlen),
.SAXIGP0AWLOCK (saxigp0awlock),
.SAXIGP0AWPROT (saxigp0awprot),
.SAXIGP0AWQOS (saxigp0awqos),
.SAXIGP0AWREADY (SAXIGP0AWREADY),
.SAXIGP0AWSIZE (saxigp0awsize),
.SAXIGP0AWVALID (saxigp0awvalid),
.SAXIGP0BID (SAXIGP0BID),
.SAXIGP0BREADY (saxigp0bready),
.SAXIGP0BRESP (SAXIGP0BRESP),
.SAXIGP0BVALID (SAXIGP0BVALID),
.SAXIGP0RDATA (SAXIGP0RDATA),
.SAXIGP0RID (SAXIGP0RID),
.SAXIGP0RLAST (SAXIGP0RLAST),
.SAXIGP0RREADY (saxigp0rready),
.SAXIGP0RRESP (SAXIGP0RRESP),
.SAXIGP0RVALID (SAXIGP0RVALID),
.SAXIGP0WDATA (saxigp0wdata),
.SAXIGP0WID (saxigp0wid),
.SAXIGP0WLAST (saxigp0wlast),
.SAXIGP0WREADY (SAXIGP0WREADY),
.SAXIGP0WSTRB (saxigp0wstrb),
.SAXIGP0WVALID (saxigp0wvalid),
.SAXIGP1ACLK (saxigp1aclk),
.SAXIGP1ARADDR (saxigp1araddr),
.SAXIGP1ARBURST (saxigp1arburst),
.SAXIGP1ARCACHE (saxigp1arcache),
.SAXIGP1ARESETN (SAXIGP1ARESETN),
.SAXIGP1ARID (saxigp1arid),
.SAXIGP1ARLEN (saxigp1arlen),
.SAXIGP1ARLOCK (saxigp1arlock),
.SAXIGP1ARPROT (saxigp1arprot),
.SAXIGP1ARQOS (saxigp1arqos),
.SAXIGP1ARREADY (SAXIGP1ARREADY),
.SAXIGP1ARSIZE (saxigp1arsize),
.SAXIGP1ARVALID (saxigp1arvalid),
.SAXIGP1AWADDR (saxigp1awaddr),
.SAXIGP1AWBURST (saxigp1awburst),
.SAXIGP1AWCACHE (saxigp1awcache),
.SAXIGP1AWID (saxigp1awid),
.SAXIGP1AWLEN (saxigp1awlen),
.SAXIGP1AWLOCK (saxigp1awlock),
.SAXIGP1AWPROT (saxigp1awprot),
.SAXIGP1AWQOS (saxigp1awqos),
.SAXIGP1AWREADY (SAXIGP1AWREADY),
.SAXIGP1AWSIZE (saxigp1awsize),
.SAXIGP1AWVALID (saxigp1awvalid),
.SAXIGP1BID (SAXIGP1BID),
.SAXIGP1BREADY (saxigp1bready),
.SAXIGP1BRESP (SAXIGP1BRESP),
.SAXIGP1BVALID (SAXIGP1BVALID),
.SAXIGP1RDATA (SAXIGP1RDATA),
.SAXIGP1RID (SAXIGP1RID),
.SAXIGP1RLAST (SAXIGP1RLAST),
.SAXIGP1RREADY (saxigp1rready),
.SAXIGP1RRESP (SAXIGP1RRESP),
.SAXIGP1RVALID (SAXIGP1RVALID),
.SAXIGP1WDATA (saxigp1wdata),
.SAXIGP1WID (saxigp1wid),
.SAXIGP1WLAST (saxigp1wlast),
.SAXIGP1WREADY (SAXIGP1WREADY),
.SAXIGP1WSTRB (saxigp1wstrb),
.SAXIGP1WVALID (saxigp1wvalid),
.SAXIHP0ACLK (saxihp0aclk),
.SAXIHP0ARADDR (saxihp0araddr),
.SAXIHP0ARBURST (saxihp0arburst),
.SAXIHP0ARCACHE (saxihp0arcache),
.SAXIHP0ARESETN (SAXIHP0ARESETN),
.SAXIHP0ARID (saxihp0arid),
.SAXIHP0ARLEN (saxihp0arlen),
.SAXIHP0ARLOCK (saxihp0arlock),
.SAXIHP0ARPROT (saxihp0arprot),
.SAXIHP0ARQOS (saxihp0arqos),
.SAXIHP0ARREADY (SAXIHP0ARREADY),
.SAXIHP0ARSIZE (saxihp0arsize),
.SAXIHP0ARVALID (saxihp0arvalid),
.SAXIHP0AWADDR (saxihp0awaddr),
.SAXIHP0AWBURST (saxihp0awburst),
.SAXIHP0AWCACHE (saxihp0awcache),
.SAXIHP0AWID (saxihp0awid),
.SAXIHP0AWLEN (saxihp0awlen),
.SAXIHP0AWLOCK (saxihp0awlock),
.SAXIHP0AWPROT (saxihp0awprot),
.SAXIHP0AWQOS (saxihp0awqos),
.SAXIHP0AWREADY (SAXIHP0AWREADY),
.SAXIHP0AWSIZE (saxihp0awsize),
.SAXIHP0AWVALID (saxihp0awvalid),
.SAXIHP0BID (SAXIHP0BID),
.SAXIHP0BREADY (saxihp0bready),
.SAXIHP0BRESP (SAXIHP0BRESP),
.SAXIHP0BVALID (SAXIHP0BVALID),
.SAXIHP0RACOUNT (SAXIHP0RACOUNT),
.SAXIHP0RCOUNT (SAXIHP0RCOUNT),
.SAXIHP0RDATA (SAXIHP0RDATA),
.SAXIHP0RDISSUECAP1EN (saxihp0rdissuecap1en),
.SAXIHP0RID (SAXIHP0RID),
.SAXIHP0RLAST (SAXIHP0RLAST),
.SAXIHP0RREADY (saxihp0rready),
.SAXIHP0RRESP (SAXIHP0RRESP),
.SAXIHP0RVALID (SAXIHP0RVALID),
.SAXIHP0WACOUNT (SAXIHP0WACOUNT),
.SAXIHP0WCOUNT (SAXIHP0WCOUNT),
.SAXIHP0WDATA (saxihp0wdata),
.SAXIHP0WID (saxihp0wid),
.SAXIHP0WLAST (saxihp0wlast),
.SAXIHP0WREADY (SAXIHP0WREADY),
.SAXIHP0WRISSUECAP1EN (saxihp0wrissuecap1en),
.SAXIHP0WSTRB (saxihp0wstrb),
.SAXIHP0WVALID (saxihp0wvalid),
.SAXIHP1ACLK (saxihp1aclk),
.SAXIHP1ARADDR (saxihp1araddr),
.SAXIHP1ARBURST (saxihp1arburst),
.SAXIHP1ARCACHE (saxihp1arcache),
.SAXIHP1ARESETN (SAXIHP1ARESETN),
.SAXIHP1ARID (saxihp1arid),
.SAXIHP1ARLEN (saxihp1arlen),
.SAXIHP1ARLOCK (saxihp1arlock),
.SAXIHP1ARPROT (saxihp1arprot),
.SAXIHP1ARQOS (saxihp1arqos),
.SAXIHP1ARREADY (SAXIHP1ARREADY),
.SAXIHP1ARSIZE (saxihp1arsize),
.SAXIHP1ARVALID (saxihp1arvalid),
.SAXIHP1AWADDR (saxihp1awaddr),
.SAXIHP1AWBURST (saxihp1awburst),
.SAXIHP1AWCACHE (saxihp1awcache),
.SAXIHP1AWID (saxihp1awid),
.SAXIHP1AWLEN (saxihp1awlen),
.SAXIHP1AWLOCK (saxihp1awlock),
.SAXIHP1AWPROT (saxihp1awprot),
.SAXIHP1AWQOS (saxihp1awqos),
.SAXIHP1AWREADY (SAXIHP1AWREADY),
.SAXIHP1AWSIZE (saxihp1awsize),
.SAXIHP1AWVALID (saxihp1awvalid),
.SAXIHP1BID (SAXIHP1BID),
.SAXIHP1BREADY (saxihp1bready),
.SAXIHP1BRESP (SAXIHP1BRESP),
.SAXIHP1BVALID (SAXIHP1BVALID),
.SAXIHP1RACOUNT (SAXIHP1RACOUNT),
.SAXIHP1RCOUNT (SAXIHP1RCOUNT),
.SAXIHP1RDATA (SAXIHP1RDATA),
.SAXIHP1RDISSUECAP1EN (saxihp1rdissuecap1en),
.SAXIHP1RID (SAXIHP1RID),
.SAXIHP1RLAST (SAXIHP1RLAST),
.SAXIHP1RREADY (saxihp1rready),
.SAXIHP1RRESP (SAXIHP1RRESP),
.SAXIHP1RVALID (SAXIHP1RVALID),
.SAXIHP1WACOUNT (SAXIHP1WACOUNT),
.SAXIHP1WCOUNT (SAXIHP1WCOUNT),
.SAXIHP1WDATA (saxihp1wdata),
.SAXIHP1WID (saxihp1wid),
.SAXIHP1WLAST (saxihp1wlast),
.SAXIHP1WREADY (SAXIHP1WREADY),
.SAXIHP1WRISSUECAP1EN (saxihp1wrissuecap1en),
.SAXIHP1WSTRB (saxihp1wstrb),
.SAXIHP1WVALID (saxihp1wvalid),
.SAXIHP2ACLK (saxihp2aclk),
.SAXIHP2ARADDR (saxihp2araddr),
.SAXIHP2ARBURST (saxihp2arburst),
.SAXIHP2ARCACHE (saxihp2arcache),
.SAXIHP2ARESETN (SAXIHP2ARESETN),
.SAXIHP2ARID (saxihp2arid),
.SAXIHP2ARLEN (saxihp2arlen),
.SAXIHP2ARLOCK (saxihp2arlock),
.SAXIHP2ARPROT (saxihp2arprot),
.SAXIHP2ARQOS (saxihp2arqos),
.SAXIHP2ARREADY (SAXIHP2ARREADY),
.SAXIHP2ARSIZE (saxihp2arsize),
.SAXIHP2ARVALID (saxihp2arvalid),
.SAXIHP2AWADDR (saxihp2awaddr),
.SAXIHP2AWBURST (saxihp2awburst),
.SAXIHP2AWCACHE (saxihp2awcache),
.SAXIHP2AWID (saxihp2awid),
.SAXIHP2AWLEN (saxihp2awlen),
.SAXIHP2AWLOCK (saxihp2awlock),
.SAXIHP2AWPROT (saxihp2awprot),
.SAXIHP2AWQOS (saxihp2awqos),
.SAXIHP2AWREADY (SAXIHP2AWREADY),
.SAXIHP2AWSIZE (saxihp2awsize),
.SAXIHP2AWVALID (saxihp2awvalid),
.SAXIHP2BID (SAXIHP2BID),
.SAXIHP2BREADY (saxihp2bready),
.SAXIHP2BRESP (SAXIHP2BRESP),
.SAXIHP2BVALID (SAXIHP2BVALID),
.SAXIHP2RACOUNT (SAXIHP2RACOUNT),
.SAXIHP2RCOUNT (SAXIHP2RCOUNT),
.SAXIHP2RDATA (SAXIHP2RDATA),
.SAXIHP2RDISSUECAP1EN (saxihp2rdissuecap1en),
.SAXIHP2RID (SAXIHP2RID),
.SAXIHP2RLAST (SAXIHP2RLAST),
.SAXIHP2RREADY (saxihp2rready),
.SAXIHP2RRESP (SAXIHP2RRESP),
.SAXIHP2RVALID (SAXIHP2RVALID),
.SAXIHP2WACOUNT (SAXIHP2WACOUNT),
.SAXIHP2WCOUNT (SAXIHP2WCOUNT),
.SAXIHP2WDATA (saxihp2wdata),
.SAXIHP2WID (saxihp2wid),
.SAXIHP2WLAST (saxihp2wlast),
.SAXIHP2WREADY (SAXIHP2WREADY),
.SAXIHP2WRISSUECAP1EN (saxihp2wrissuecap1en),
.SAXIHP2WSTRB (saxihp2wstrb),
.SAXIHP2WVALID (saxihp2wvalid),
.SAXIHP3ACLK (saxihp3aclk),
.SAXIHP3ARADDR (saxihp3araddr),
.SAXIHP3ARBURST (saxihp3arburst),
.SAXIHP3ARCACHE (saxihp3arcache),
.SAXIHP3ARESETN (SAXIHP3ARESETN),
.SAXIHP3ARID (saxihp3arid),
.SAXIHP3ARLEN (saxihp3arlen),
.SAXIHP3ARLOCK (saxihp3arlock),
.SAXIHP3ARPROT (saxihp3arprot),
.SAXIHP3ARQOS (saxihp3arqos),
.SAXIHP3ARREADY (SAXIHP3ARREADY),
.SAXIHP3ARSIZE (saxihp3arsize),
.SAXIHP3ARVALID (saxihp3arvalid),
.SAXIHP3AWADDR (saxihp3awaddr),
.SAXIHP3AWBURST (saxihp3awburst),
.SAXIHP3AWCACHE (saxihp3awcache),
.SAXIHP3AWID (saxihp3awid),
.SAXIHP3AWLEN (saxihp3awlen),
.SAXIHP3AWLOCK (saxihp3awlock),
.SAXIHP3AWPROT (saxihp3awprot),
.SAXIHP3AWQOS (saxihp3awqos),
.SAXIHP3AWREADY (SAXIHP3AWREADY),
.SAXIHP3AWSIZE (saxihp3awsize),
.SAXIHP3AWVALID (saxihp3awvalid),
.SAXIHP3BID (SAXIHP3BID),
.SAXIHP3BREADY (saxihp3bready),
.SAXIHP3BRESP (SAXIHP3BRESP),
.SAXIHP3BVALID (SAXIHP3BVALID),
.SAXIHP3RACOUNT (SAXIHP3RACOUNT),
.SAXIHP3RCOUNT (SAXIHP3RCOUNT),
.SAXIHP3RDATA (SAXIHP3RDATA),
.SAXIHP3RDISSUECAP1EN (saxihp3rdissuecap1en),
.SAXIHP3RID (SAXIHP3RID),
.SAXIHP3RLAST (SAXIHP3RLAST),
.SAXIHP3RREADY (saxihp3rready),
.SAXIHP3RRESP (SAXIHP3RRESP),
.SAXIHP3RVALID (SAXIHP3RVALID),
.SAXIHP3WACOUNT (SAXIHP3WACOUNT),
.SAXIHP3WCOUNT (SAXIHP3WCOUNT),
.SAXIHP3WDATA (saxihp3wdata),
.SAXIHP3WID (saxihp3wid),
.SAXIHP3WLAST (saxihp3wlast),
.SAXIHP3WREADY (SAXIHP3WREADY),
.SAXIHP3WRISSUECAP1EN (saxihp3wrissuecap1en),
.SAXIHP3WSTRB (saxihp3wstrb),
.SAXIHP3WVALID (saxihp3wvalid)
);
endmodule
module CARRY4_FIX(output O0, O1, O2, O3, CO0, CO1, CO2, CO3, input CYINIT, CIN, DI0, DI1, DI2, DI3, S0, S1, S2, S3);
parameter CYINIT_AX = 1'b0;
parameter CYINIT_C0 = 1'b0;
parameter CYINIT_C1 = 1'b0;
if(CYINIT_AX) begin
CARRY4_VPR #(
.CYINIT_AX(1'b1),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO0),
.CO1(CO1),
.CO2(CO2),
.CO3(CO3),
.CYINIT(CYINIT),
.O0(O0),
.O1(O1),
.O2(O2),
.O3(O3),
.DI0(DI0),
.DI1(DI1),
.DI2(DI2),
.DI3(DI3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3)
);
end else if(CYINIT_C0 || CYINIT_C1) begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(CYINIT_C0),
.CYINIT_C1(CYINIT_C1)
) _TECHMAP_REPLACE_ (
.CO0(CO0),
.CO1(CO1),
.CO2(CO2),
.CO3(CO3),
.O0(O0),
.O1(O1),
.O2(O2),
.O3(O3),
.DI0(DI0),
.DI1(DI1),
.DI2(DI2),
.DI3(DI3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3)
);
end else begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO0),
.CO1(CO1),
.CO2(CO2),
.CO3(CO3),
.O0(O0),
.O1(O1),
.O2(O2),
.O3(O3),
.DI0(DI0),
.DI1(DI1),
.DI2(DI2),
.DI3(DI3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3),
.CIN(CIN)
);
end
endmodule
module IBUFDS_GTE2 (
output O,
output ODIV2,
input CEB,
input I,
input IB
);
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter [1:0] CLKSWING_CFG = 2'b11;
parameter IO_LOC_PAIRS = "NONE";
wire ipad_p_O, ipad_n_O;
IPAD_GTP_VPR IPAD_P (
.I(I),
.O(ipad_p_O)
);
IPAD_GTP_VPR IPAD_N (
.I(IB),
.O(ipad_n_O)
);
IBUFDS_GTE2_VPR #(
.CLKCM_CFG(CLKCM_CFG == "TRUE"),
.CLKRCV_TRST(CLKRCV_TRST == "TRUE"),
.CLKSWING_CFG(CLKSWING_CFG),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) IBUFDS_GTE2_INST (
.O(O),
.ODIV2(ODIV2),
.CEB(CEB),
.I(ipad_p_O),
.IB(ipad_n_O)
);
endmodule
module GTPE2_COMMON (
output DRPRDY,
output PLL0FBCLKLOST,
output PLL0LOCK,
output PLL0OUTCLK,
output PLL0OUTREFCLK,
output PLL0REFCLKLOST,
output PLL1FBCLKLOST,
output PLL1LOCK,
output PLL1OUTCLK,
output PLL1OUTREFCLK,
output PLL1REFCLKLOST,
output REFCLKOUTMONITOR0,
output REFCLKOUTMONITOR1,
output [15:0] DRPDO,
output [15:0] PMARSVDOUT,
output [7:0] DMONITOROUT,
input BGBYPASSB,
input BGMONITORENB,
input BGPDB,
input BGRCALOVRDENB,
input DRPCLK,
input DRPEN,
input DRPWE,
input GTREFCLK0,
input GTREFCLK1,
input GTGREFCLK0,
input GTGREFCLK1,
input PLL0LOCKDETCLK,
input PLL0LOCKEN,
input PLL0PD,
input PLL0RESET,
input PLL1LOCKDETCLK,
input PLL1LOCKEN,
input PLL1PD,
input PLL1RESET,
input RCALENB,
input [15:0] DRPDI,
input [2:0] PLL0REFCLKSEL,
input [2:0] PLL1REFCLKSEL,
input [4:0] BGRCALOVRD,
input [7:0] DRPADDR,
input [7:0] PMARSVD
);
parameter [63:0] BIAS_CFG = 64'h0000000000000000;
parameter [31:0] COMMON_CFG = 32'h00000000;
parameter [26:0] PLL0_CFG = 27'h01F03DC;
parameter [0:0] PLL0_DMON_CFG = 1'b0;
parameter [23:0] PLL0_INIT_CFG = 24'h00001E;
parameter [8:0] PLL0_LOCK_CFG = 9'h1E8;
parameter [26:0] PLL1_CFG = 27'h01F03DC;
parameter [0:0] PLL1_DMON_CFG = 1'b0;
parameter [23:0] PLL1_INIT_CFG = 24'h00001E;
parameter [8:0] PLL1_LOCK_CFG = 9'h1E8;
parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000;
parameter [15:0] RSVD_ATTR0 = 16'h0000;
parameter [15:0] RSVD_ATTR1 = 16'h0000;
parameter integer PLL0_REFCLK_DIV = 1;
parameter integer PLL0_FBDIV = 4;
parameter integer PLL0_FBDIV_45 = 5;
parameter integer PLL1_REFCLK_DIV = 1;
parameter integer PLL1_FBDIV = 4;
parameter integer PLL1_FBDIV_45 = 5;
localparam [4:0] PLL0_REFCLK_DIV_BIN = PLL0_REFCLK_DIV == 1 ? 5'b10000 : 5'b00000;
localparam [4:0] PLL1_REFCLK_DIV_BIN = PLL1_REFCLK_DIV == 1 ? 5'b10000 : 5'b00000;
localparam [5:0] PLL0_FBDIV_BIN = PLL0_FBDIV == 1 ? 6'b010000 :
PLL0_FBDIV == 2 ? 6'b000000 :
PLL0_FBDIV == 3 ? 6'b000001 :
PLL0_FBDIV == 4 ? 6'b000010 :
/*PLL0_FBDIV == 5*/ 6'b000011;
localparam [5:0] PLL1_FBDIV_BIN = PLL1_FBDIV == 1 ? 6'b010000 :
PLL1_FBDIV == 2 ? 6'b000000 :
PLL1_FBDIV == 3 ? 6'b000001 :
PLL1_FBDIV == 4 ? 6'b000010 :
/*PLL1_FBDIV == 5*/ 6'b000011;
localparam PLL0_FBDIV_45_BIN = PLL0_FBDIV_45 == 4 ? 1'b0 : 1'b1;
localparam PLL1_FBDIV_45_BIN = PLL1_FBDIV_45 == 4 ? 1'b0 : 1'b1;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_DRPCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DRPCLK_ = 0;
parameter _TECHMAP_CONSTMSK_PLL0LOCKDETCLK_ = 0;
parameter _TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ = 0;
parameter _TECHMAP_CONSTMSK_PLL1LOCKDETCLK_ = 0;
parameter _TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ = 0;
localparam [0:0] INV_DRPCLK = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? !_TECHMAP_CONSTVAL_DRPCLK_ ^ IS_DRPCLK_INVERTED :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? ~IS_DRPCLK_INVERTED : IS_DRPCLK_INVERTED;
wire drpclk = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? 1'b1 : DRPCLK;
localparam [0:0] INV_PLL0LOCKDETCLK = (_TECHMAP_CONSTMSK_PLL0LOCKDETCLK_ == 1) ? !_TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ ^ IS_PLL0LOCKDETCLK_INVERTED :
(_TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ == 0) ? ~IS_PLL0LOCKDETCLK_INVERTED : IS_PLL0LOCKDETCLK_INVERTED;
wire pll0lockdetclk = (_TECHMAP_CONSTMSK_PLL0LOCKDETCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ == 0) ? 1'b1 : PLL0LOCKDETCLK;
localparam [0:0] INV_PLL1LOCKDETCLK = (_TECHMAP_CONSTMSK_PLL1LOCKDETCLK_ == 1) ? !_TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ ^ IS_PLL1LOCKDETCLK_INVERTED :
(_TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ == 0) ? ~IS_PLL1LOCKDETCLK_INVERTED : IS_PLL1LOCKDETCLK_INVERTED;
wire pll1lockdetclk = (_TECHMAP_CONSTMSK_PLL1LOCKDETCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ == 0) ? 1'b1 : PLL1LOCKDETCLK;
parameter _TECHMAP_CONSTMSK_GTREFCLK0_ = 0;
parameter _TECHMAP_CONSTVAL_GTREFCLK0_ = 0;
parameter _TECHMAP_CONSTMSK_GTREFCLK1_ = 0;
parameter _TECHMAP_CONSTVAL_GTREFCLK1_ = 0;
localparam [0:0] GTREFCLK0_USED = (_TECHMAP_CONSTMSK_GTREFCLK0_ == 1) ? 1'b0 :
(_TECHMAP_CONSTVAL_GTREFCLK0_ === 0) ? 1'b0 : 1'b1;
localparam [0:0] GTREFCLK1_USED = (_TECHMAP_CONSTMSK_GTREFCLK1_ == 1) ? 1'b0 :
(_TECHMAP_CONSTVAL_GTREFCLK1_ === 0) ? 1'b0 : 1'b1;
localparam [0:0] BOTH_GTREFCLK_USED = GTREFCLK0_USED && GTREFCLK1_USED;
localparam [0:0] NONE_GTREFCLK_USED = !(GTREFCLK0_USED || GTREFCLK1_USED);
if (NONE_GTREFCLK_USED) begin
wire _TECHMAP_FAIL_ = 1'b1;
end
if (BOTH_GTREFCLK_USED) begin
GTPE2_COMMON_VPR #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV_BIN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_BIN),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_BIN),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV_BIN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_BIN),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_BIN),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.INV_DRPCLK (INV_DRPCLK),
.INV_PLL0LOCKDETCLK (INV_PLL0LOCKDETCLK),
.INV_PLL1LOCKDETCLK (INV_PLL1LOCKDETCLK),
.GTREFCLK0_USED (GTREFCLK0_USED == 1'b1),
.GTREFCLK1_USED (GTREFCLK1_USED == 1'b1),
.BOTH_GTREFCLK_USED (BOTH_GTREFCLK_USED),
.ENABLE_DRP (1'b1),
.IBUFDS_GTE2_CLKSWING_CFG (2'b11)
) _TECHMAP_REPLACE_ (
.DRPRDY (DRPRDY),
.PLL0FBCLKLOST (PLL0FBCLKLOST),
.PLL0LOCK (PLL0LOCK),
.PLL0OUTCLK (PLL0OUTCLK),
.PLL0OUTREFCLK (PLL0OUTREFCLK),
.PLL0REFCLKLOST (PLL0REFCLKLOST),
.PLL1FBCLKLOST (PLL1FBCLKLOST),
.PLL1LOCK (PLL1LOCK),
.PLL1OUTCLK (PLL1OUTCLK),
.PLL1OUTREFCLK (PLL1OUTREFCLK),
.PLL1REFCLKLOST (PLL1REFCLKLOST),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1),
.DRPDO (DRPDO),
.PMARSVDOUT (PMARSVDOUT),
.DMONITOROUT (DMONITOROUT),
.BGBYPASSB (BGBYPASSB),
.BGMONITORENB (BGMONITORENB),
.BGPDB (BGPDB),
.BGRCALOVRDENB (BGRCALOVRDENB),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.PLL0LOCKDETCLK (pll0lockdetclk),
.PLL0LOCKEN (PLL0LOCKEN),
.PLL0PD (PLL0PD),
.PLL0RESET (PLL0RESET),
.PLL1LOCKDETCLK (pll1lockdetclk),
.PLL1LOCKEN (PLL1LOCKEN),
.PLL1PD (PLL1PD),
.PLL1RESET (PLL1RESET),
.RCALENB (RCALENB),
.DRPDI (DRPDI),
.PLL0REFCLKSEL (PLL0REFCLKSEL),
.PLL1REFCLKSEL (PLL1REFCLKSEL),
.BGRCALOVRD (BGRCALOVRD),
.DRPADDR (DRPADDR),
.PMARSVD (PMARSVD)
);
end else if (GTREFCLK0_USED) begin
GTPE2_COMMON_VPR #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV_BIN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_BIN),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_BIN),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV_BIN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_BIN),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_BIN),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.INV_DRPCLK (INV_DRPCLK),
.INV_PLL0LOCKDETCLK (INV_PLL0LOCKDETCLK),
.INV_PLL1LOCKDETCLK (INV_PLL1LOCKDETCLK),
.GTREFCLK0_USED (GTREFCLK0_USED == 1'b1),
.GTREFCLK1_USED (GTREFCLK1_USED == 1'b1),
.BOTH_GTREFCLK_USED (BOTH_GTREFCLK_USED),
.ENABLE_DRP (1'b1),
.IBUFDS_GTE2_CLKSWING_CFG (2'b11)
) _TECHMAP_REPLACE_ (
.DRPRDY (DRPRDY),
.PLL0FBCLKLOST (PLL0FBCLKLOST),
.PLL0LOCK (PLL0LOCK),
.PLL0OUTCLK (PLL0OUTCLK),
.PLL0OUTREFCLK (PLL0OUTREFCLK),
.PLL0REFCLKLOST (PLL0REFCLKLOST),
.PLL1FBCLKLOST (PLL1FBCLKLOST),
.PLL1LOCK (PLL1LOCK),
.PLL1OUTCLK (PLL1OUTCLK),
.PLL1OUTREFCLK (PLL1OUTREFCLK),
.PLL1REFCLKLOST (PLL1REFCLKLOST),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1),
.DRPDO (DRPDO),
.PMARSVDOUT (PMARSVDOUT),
.DMONITOROUT (DMONITOROUT),
.BGBYPASSB (BGBYPASSB),
.BGMONITORENB (BGMONITORENB),
.BGPDB (BGPDB),
.BGRCALOVRDENB (BGRCALOVRDENB),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.GTREFCLK0 (GTREFCLK0),
.PLL0LOCKDETCLK (pll0lockdetclk),
.PLL0LOCKEN (PLL0LOCKEN),
.PLL0PD (PLL0PD),
.PLL0RESET (PLL0RESET),
.PLL1LOCKDETCLK (pll1lockdetclk),
.PLL1LOCKEN (PLL1LOCKEN),
.PLL1PD (PLL1PD),
.PLL1RESET (PLL1RESET),
.RCALENB (RCALENB),
.DRPDI (DRPDI),
.PLL0REFCLKSEL (PLL0REFCLKSEL),
.PLL1REFCLKSEL (PLL1REFCLKSEL),
.BGRCALOVRD (BGRCALOVRD),
.DRPADDR (DRPADDR),
.PMARSVD (PMARSVD)
);
end else begin
GTPE2_COMMON_VPR #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV_BIN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_BIN),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_BIN),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV_BIN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_BIN),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_BIN),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.INV_DRPCLK (INV_DRPCLK),
.INV_PLL0LOCKDETCLK (INV_PLL0LOCKDETCLK),
.INV_PLL1LOCKDETCLK (INV_PLL1LOCKDETCLK),
.GTREFCLK0_USED (GTREFCLK0_USED == 1'b1),
.GTREFCLK1_USED (GTREFCLK1_USED == 1'b1),
.BOTH_GTREFCLK_USED (BOTH_GTREFCLK_USED),
.ENABLE_DRP (1'b1),
.IBUFDS_GTE2_CLKSWING_CFG (2'b11)
) _TECHMAP_REPLACE_ (
.DRPRDY (DRPRDY),
.PLL0FBCLKLOST (PLL0FBCLKLOST),
.PLL0LOCK (PLL0LOCK),
.PLL0OUTCLK (PLL0OUTCLK),
.PLL0OUTREFCLK (PLL0OUTREFCLK),
.PLL0REFCLKLOST (PLL0REFCLKLOST),
.PLL1FBCLKLOST (PLL1FBCLKLOST),
.PLL1LOCK (PLL1LOCK),
.PLL1OUTCLK (PLL1OUTCLK),
.PLL1OUTREFCLK (PLL1OUTREFCLK),
.PLL1REFCLKLOST (PLL1REFCLKLOST),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1),
.DRPDO (DRPDO),
.PMARSVDOUT (PMARSVDOUT),
.DMONITOROUT (DMONITOROUT),
.BGBYPASSB (BGBYPASSB),
.BGMONITORENB (BGMONITORENB),
.BGPDB (BGPDB),
.BGRCALOVRDENB (BGRCALOVRDENB),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.GTREFCLK1 (GTREFCLK1),
.PLL0LOCKDETCLK (pll0lockdetclk),
.PLL0LOCKEN (PLL0LOCKEN),
.PLL0PD (PLL0PD),
.PLL0RESET (PLL0RESET),
.PLL1LOCKDETCLK (pll1lockdetclk),
.PLL1LOCKEN (PLL1LOCKEN),
.PLL1PD (PLL1PD),
.PLL1RESET (PLL1RESET),
.RCALENB (RCALENB),
.DRPDI (DRPDI),
.PLL0REFCLKSEL (PLL0REFCLKSEL),
.PLL1REFCLKSEL (PLL1REFCLKSEL),
.BGRCALOVRD (BGRCALOVRD),
.DRPADDR (DRPADDR),
.PMARSVD (PMARSVD)
);
end
endmodule
module GTPE2_CHANNEL (
output DRPRDY,
output EYESCANDATAERROR,
output GTPTXN,
output GTPTXP,
output PHYSTATUS,
output PMARSVDOUT0,
output PMARSVDOUT1,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output RXDLYSRESETDONE,
output RXELECIDLE,
output RXHEADERVALID,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPMARESETDONE,
output RXPRBSERR,
output RXRATEDONE,
output RXRESETDONE,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output TXCOMFINISH,
output TXDLYSRESETDONE,
output TXGEARBOXREADY,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
output [14:0] DMONITOROUT,
output [15:0] DRPDO,
output [15:0] PCSRSVDOUT,
output [1:0] RXCLKCORCNT,
output [1:0] RXDATAVALID,
output [1:0] RXSTARTOFSEQ,
output [1:0] TXBUFSTATUS,
output [2:0] RXBUFSTATUS,
output [2:0] RXHEADER,
output [2:0] RXSTATUS,
output [31:0] RXDATA,
output [3:0] RXCHARISCOMMA,
output [3:0] RXCHARISK,
output [3:0] RXCHBONDO,
output [3:0] RXDISPERR,
output [3:0] RXNOTINTABLE,
output [4:0] RXPHMONITOR,
output [4:0] RXPHSLIPMONITOR,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input DMONFIFORESET,
input DMONITORCLK,
input DRPCLK,
input DRPEN,
input DRPWE,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTPRXN,
input GTPRXP,
input GTRESETSEL,
input GTRXRESET,
input GTTXRESET,
input PLL0CLK,
input PLL0REFCLK,
input PLL1CLK,
input PLL1REFCLK,
input PMARSVDIN0,
input PMARSVDIN1,
input PMARSVDIN2,
input PMARSVDIN3,
input PMARSVDIN4,
input RESETOVRD,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCOMMADETEN,
input RXDDIEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input RXGEARBOXSLIP,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFOVRDEN,
input RXLPMOSINTNTRLEN,
input RXLPMRESET,
input RXMCOMMAALIGNEN,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTNTRLEN,
input RXOSINTOVRDEN,
input RXOSINTPD,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input RXRATEMODE,
input RXSLIDE,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input RXUSERRDY,
input RXUSRCLK2,
input RXUSRCLK,
input SETERRSTATUS,
input SIGVALIDCLK,
input TX8B10BEN,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input TXDEEMPH,
input TXDETECTRX,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input TXINHIBIT,
input TXPCSRESET,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input TXPISOPD,
input TXPMARESET,
input TXPOLARITY,
input TXPOSTCURSORINV,
input TXPRBSFORCEERR,
input TXPRECURSORINV,
input TXRATEMODE,
input TXSTARTSEQ,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input TXUSERRDY,
input TXUSRCLK2,
input TXUSRCLK,
input [13:0] RXADAPTSELTEST,
input [15:0] DRPDI,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [19:0] TSTIN,
input [1:0] RXELECIDLEMODE,
input [1:0] RXPD,
input [1:0] RXSYSCLKSEL,
input [1:0] TXPD,
input [1:0] TXSYSCLKSEL,
input [2:0] LOOPBACK,
input [2:0] RXCHBONDLEVEL,
input [2:0] RXOUTCLKSEL,
input [2:0] RXPRBSSEL,
input [2:0] RXRATE,
input [2:0] TXBUFDIFFCTRL,
input [2:0] TXHEADER,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input [2:0] TXPRBSSEL,
input [2:0] TXRATE,
input [31:0] TXDATA,
input [3:0] RXCHBONDI,
input [3:0] RXOSINTCFG,
input [3:0] RXOSINTID0,
input [3:0] TX8B10BBYPASS,
input [3:0] TXCHARDISPMODE,
input [3:0] TXCHARDISPVAL,
input [3:0] TXCHARISK,
input [3:0] TXDIFFCTRL,
input [4:0] TXPIPPMSTEPSIZE,
input [4:0] TXPOSTCURSOR,
input [4:0] TXPRECURSOR,
input [6:0] TXMAINCURSOR,
input [6:0] TXSEQUENCE,
input [8:0] DRPADDR
);
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
parameter [0:0] ACJTAG_MODE = 1'b0;
parameter [0:0] ACJTAG_RESET = 1'b0;
parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter [1:0] ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
parameter [6:0] CFOK_CFG2 = 7'b0100000;
parameter [6:0] CFOK_CFG3 = 7'b0100000;
parameter [0:0] CFOK_CFG4 = 1'b0;
parameter [1:0] CFOK_CFG5 = 2'b00;
parameter [3:0] CFOK_CFG6 = 4'b0000;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter [3:0] CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter [0:0] CLK_COMMON_SWING = 1'b0;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter [5:0] CLK_COR_MAX_LAT = 20;
parameter [5:0] CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter [4:0] CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "FALSE";
parameter [11:0] ES_HORZ_OFFSET = 12'h010;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] LOOPBACK_CFG = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
parameter [31:0] PMA_RSV = 32'h00000333;
parameter [31:0] PMA_RSV2 = 32'h00002050;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [3:0] PMA_RSV4 = 4'b0000;
parameter [0:0] PMA_RSV5 = 1'b0;
parameter [0:0] PMA_RSV6 = 1'b0;
parameter [0:0] PMA_RSV7 = 1'b0;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter [5:0] RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter [5:0] RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [15:0] RXDLY_CFG = 16'h0010;
parameter [8:0] RXDLY_LCFG = 9'h020;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
parameter [3:0] RXLPM_CFG = 4'b0110;
parameter [0:0] RXLPM_CFG1 = 1'b0;
parameter [0:0] RXLPM_CM_CFG = 1'b0;
parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
parameter [0:0] RXLPM_INCM_CFG = 1'b0;
parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter RXOOB_CLK_CFG = "PMA";
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084000;
parameter [23:0] RXPH_CFG = 24'hC00002;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [2:0] RXPI_CFG0 = 3'b000;
parameter [0:0] RXPI_CFG1 = 1'b0;
parameter [0:0] RXPI_CFG2 = 1'b0;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter [3:0] RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
parameter [0:0] RXSYNC_OVRD = 1'b0;
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_EN = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [3:0] RX_CM_TRIM = 4'b0100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter [6:0] SAS_MAX_COM = 64;
parameter [5:0] SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter [5:0] SATA_MAX_BURST = 8;
parameter [5:0] SATA_MAX_INIT = 21;
parameter [5:0] SATA_MAX_WAKE = 7;
parameter [5:0] SATA_MIN_BURST = 4;
parameter [5:0] SATA_MIN_INIT = 12;
parameter [5:0] SATA_MIN_WAKE = 4;
parameter SATA_PLL_CFG = "VCO_3000MHZ";
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h0010;
parameter [8:0] TXDLY_LCFG = 9'h020;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter [0:0] TXOOB_CFG = 1'b0;
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084000;
parameter [15:0] TXPH_CFG = 16'h0400;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] TXPI_CFG0 = 2'b00;
parameter [1:0] TXPI_CFG1 = 2'b00;
parameter [1:0] TXPI_CFG2 = 2'b00;
parameter [0:0] TXPI_CFG3 = 1'b0;
parameter [0:0] TXPI_CFG4 = 1'b0;
parameter [2:0] TXPI_CFG5 = 3'b000;
parameter [0:0] TXPI_GREY_SEL = 1'b0;
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
parameter [0:0] TXSYNC_OVRD = 1'b0;
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_EN = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [5:0] TX_DEEMPH0 = 6'b000000;
parameter [5:0] TX_DEEMPH1 = 6'b000000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
parameter IO_LOC_PAIRS = "NONE";
localparam [1:0] CHAN_BOND_SEQ_LEN_BIN = CHAN_BOND_SEQ_LEN - 1;
localparam [1:0] CLK_COR_SEQ_LEN_BIN = CLK_COR_SEQ_LEN - 1;
localparam [4:0] RX_CLK25_DIV_BIN = RX_CLK25_DIV - 1;
localparam [4:0] TX_CLK25_DIV_BIN = TX_CLK25_DIV - 1;
localparam [4:0] RX_SIG_VALID_DLY_BIN = RX_SIG_VALID_DLY - 1;
localparam [2:0] RX_DATA_WIDTH_BIN = RX_DATA_WIDTH == 16 ? 3'b010 :
RX_DATA_WIDTH == 20 ? 3'b011 :
RX_DATA_WIDTH == 32 ? 3'b100 :
/*RX_DATA_WIDTH == 40*/ 3'b101;
localparam [2:0] TX_DATA_WIDTH_BIN = TX_DATA_WIDTH == 16 ? 3'b010 :
TX_DATA_WIDTH == 20 ? 3'b011 :
TX_DATA_WIDTH == 32 ? 3'b100 :
/*TX_DATA_WIDTH == 40*/ 3'b101;
localparam [1:0] RXOUT_DIV_BIN = RXOUT_DIV == 1 ? 2'b00 :
RXOUT_DIV == 2 ? 2'b01 :
RXOUT_DIV == 4 ? 2'b10 :
/*RXOUT_DIV == 8*/ 2'b11;
localparam [1:0] TXOUT_DIV_BIN = TXOUT_DIV == 1 ? 2'b00 :
TXOUT_DIV == 2 ? 2'b01 :
TXOUT_DIV == 4 ? 2'b10 :
/*TXOUT_DIV == 8*/ 2'b11;
parameter _TECHMAP_CONSTMSK_TXUSRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_TXUSRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_TXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTVAL_TXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTMSK_TXPHDLYTSTCLK_ = 0;
parameter _TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ = 0;
parameter _TECHMAP_CONSTMSK_SIGVALIDCLK_ = 0;
parameter _TECHMAP_CONSTVAL_SIGVALIDCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RXUSRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_RXUSRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTVAL_RXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTVAL_DRPCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DRPCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMONITORCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMONITORCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKRSVD0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKRSVD0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKRSVD1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKRSVD1_ = 0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
localparam [0:0] INV_TXUSRCLK = (_TECHMAP_CONSTMSK_TXUSRCLK_ == 1) ? !_TECHMAP_CONSTVAL_TXUSRCLK_ ^ IS_TXUSRCLK_INVERTED :
(_TECHMAP_CONSTVAL_TXUSRCLK_ == 0) ? ~IS_TXUSRCLK_INVERTED : IS_TXUSRCLK_INVERTED;
wire txusrclk = (_TECHMAP_CONSTMSK_TXUSRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_TXUSRCLK_ == 0) ? 1'b1 : TXUSRCLK;
localparam [0:0] INV_TXUSRCLK2 = (_TECHMAP_CONSTMSK_TXUSRCLK2_ == 1) ? !_TECHMAP_CONSTVAL_TXUSRCLK2_ ^ IS_TXUSRCLK2_INVERTED :
(_TECHMAP_CONSTVAL_TXUSRCLK2_ == 0) ? ~IS_TXUSRCLK2_INVERTED : IS_TXUSRCLK2_INVERTED;
wire txusrclk2 = (_TECHMAP_CONSTMSK_TXUSRCLK2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_TXUSRCLK2_ == 0) ? 1'b1 : TXUSRCLK2;
localparam [0:0] INV_TXPHDLYTSTCLK = (_TECHMAP_CONSTMSK_TXPHDLYTSTCLK_ == 1) ? !_TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ ^ IS_TXPHDLYTSTCLK_INVERTED :
(_TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ == 0) ? ~IS_TXPHDLYTSTCLK_INVERTED : IS_TXPHDLYTSTCLK_INVERTED;
wire txphdlytstclk = (_TECHMAP_CONSTMSK_TXPHDLYTSTCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ == 0) ? 1'b1 : TXPHDLYTSTCLK;
localparam [0:0] INV_SIGVALIDCLK = (_TECHMAP_CONSTMSK_SIGVALIDCLK_ == 1) ? !_TECHMAP_CONSTVAL_SIGVALIDCLK_ ^ IS_SIGVALIDCLK_INVERTED :
(_TECHMAP_CONSTVAL_SIGVALIDCLK_ == 0) ? ~IS_SIGVALIDCLK_INVERTED : IS_SIGVALIDCLK_INVERTED;
wire sigvalidclk = (_TECHMAP_CONSTMSK_SIGVALIDCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_SIGVALIDCLK_ == 0) ? 1'b1 : SIGVALIDCLK;
localparam [0:0] INV_RXUSRCLK = (_TECHMAP_CONSTMSK_RXUSRCLK_ == 1) ? !_TECHMAP_CONSTVAL_RXUSRCLK_ ^ IS_RXUSRCLK_INVERTED :
(_TECHMAP_CONSTVAL_RXUSRCLK_ == 0) ? ~IS_RXUSRCLK_INVERTED : IS_RXUSRCLK_INVERTED;
wire rxusrclk = (_TECHMAP_CONSTMSK_RXUSRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RXUSRCLK_ == 0) ? 1'b1 : RXUSRCLK;
localparam [0:0] INV_RXUSRCLK2 = (_TECHMAP_CONSTMSK_RXUSRCLK2_ == 1) ? !_TECHMAP_CONSTVAL_RXUSRCLK2_ ^ IS_RXUSRCLK2_INVERTED :
(_TECHMAP_CONSTVAL_RXUSRCLK2_ == 0) ? ~IS_RXUSRCLK2_INVERTED : IS_RXUSRCLK2_INVERTED;
wire rxusrclk2 = (_TECHMAP_CONSTMSK_RXUSRCLK2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RXUSRCLK2_ == 0) ? 1'b1 : RXUSRCLK2;
localparam [0:0] INV_DRPCLK = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? !_TECHMAP_CONSTVAL_DRPCLK_ ^ IS_DRPCLK_INVERTED :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? ~IS_DRPCLK_INVERTED : IS_DRPCLK_INVERTED;
wire drpclk = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? 1'b1 : DRPCLK;
localparam [0:0] INV_DMONITORCLK = (_TECHMAP_CONSTMSK_DMONITORCLK_ == 1) ? !_TECHMAP_CONSTVAL_DMONITORCLK_ ^ IS_DMONITORCLK_INVERTED :
(_TECHMAP_CONSTVAL_DMONITORCLK_ == 0) ? ~IS_DMONITORCLK_INVERTED : IS_DMONITORCLK_INVERTED;
wire dmonitorclk = (_TECHMAP_CONSTMSK_DMONITORCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_DMONITORCLK_ == 0) ? 1'b1 : DMONITORCLK;
localparam [0:0] INV_CLKRSVD0 = (_TECHMAP_CONSTMSK_CLKRSVD0_ == 1) ? !_TECHMAP_CONSTVAL_CLKRSVD0_ ^ IS_CLKRSVD0_INVERTED :
(_TECHMAP_CONSTVAL_CLKRSVD0_ == 0) ? ~IS_CLKRSVD0_INVERTED : IS_CLKRSVD0_INVERTED;
wire clkrsvd0 = (_TECHMAP_CONSTMSK_CLKRSVD0_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKRSVD0_ == 0) ? 1'b1 : CLKRSVD0;
localparam [0:0] INV_CLKRSVD1 = (_TECHMAP_CONSTMSK_CLKRSVD1_ == 1) ? !_TECHMAP_CONSTVAL_CLKRSVD1_ ^ IS_CLKRSVD1_INVERTED :
(_TECHMAP_CONSTVAL_CLKRSVD1_ == 0) ? ~IS_CLKRSVD1_INVERTED : IS_CLKRSVD1_INVERTED;
wire clkrsvd1 = (_TECHMAP_CONSTMSK_CLKRSVD1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKRSVD1_ == 0) ? 1'b1 : CLKRSVD1;
parameter IN_USE = 1'b0;
wire gtprxn, gtprxp;
IPAD_GTP_VPR ibuf_rx_n (.I(GTPRXN), .O(gtprxn));
IPAD_GTP_VPR ibuf_rx_p (.I(GTPRXP), .O(gtprxp));
wire gtptxn, gtptxp;
OPAD_GTP_VPR obuf_tx_n (.I(gtptxn), .O(GTPTXN));
OPAD_GTP_VPR obuf_tx_p (.I(gtptxp), .O(GTPTXP));
GTPE2_CHANNEL_VPR #(
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE),
.ACJTAG_MODE (ACJTAG_MODE),
.ACJTAG_RESET (ACJTAG_RESET),
.ADAPT_CFG0 (ADAPT_CFG0),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE == "TRUE"),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET == "TRUE"),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET == "TRUE"),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.CBCC_DATA_SOURCE_SEL_DECODED (CBCC_DATA_SOURCE_SEL == "DECODED"),
.CFOK_CFG (CFOK_CFG),
.CFOK_CFG2 (CFOK_CFG2),
.CFOK_CFG3 (CFOK_CFG3),
.CFOK_CFG4 (CFOK_CFG4),
.CFOK_CFG5 (CFOK_CFG5),
.CFOK_CFG6 (CFOK_CFG6),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN == "TRUE"),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE == "TRUE"),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_BIN),
.CLK_COMMON_SWING (CLK_COMMON_SWING),
.CLK_CORRECT_USE (CLK_CORRECT_USE == "TRUE"),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE == "TRUE"),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE == "TRUE"),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE == "TRUE"),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_BIN),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT == "TRUE"),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT == "TRUE"),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY == "TRUE"),
.DMONITOR_CFG (DMONITOR_CFG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL),
.ES_CONTROL (ES_CONTROL),
.ES_ERRDET_EN (ES_ERRDET_EN == "TRUE"),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN == "TRUE"),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PMA_CFG (ES_PMA_CFG),
.ES_PRESCALE (ES_PRESCALE),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN == "TRUE"),
.GEARBOX_MODE (GEARBOX_MODE),
.LOOPBACK_CFG (LOOPBACK_CFG),
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
.PCS_PCIE_EN (PCS_PCIE_EN == "TRUE"),
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.PMA_LOOPBACK_CFG (PMA_LOOPBACK_CFG),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (PMA_RSV2),
.PMA_RSV3 (PMA_RSV3),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV5 (PMA_RSV5),
.PMA_RSV6 (PMA_RSV6),
.PMA_RSV7 (PMA_RSV7),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
.RXBUF_ADDR_MODE_FAST (RXBUF_ADDR_MODE == "FAST"),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_EN (RXBUF_EN == "TRUE"),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE == "TRUE"),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN == "TRUE"),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE == "TRUE"),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE == "TRUE"),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD == "TRUE"),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RXGEARBOX_EN (RXGEARBOX_EN == "TRUE"),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXLPMRESET_TIME (RXLPMRESET_TIME),
.RXLPM_BIAS_STARTUP_DISABLE (RXLPM_BIAS_STARTUP_DISABLE),
.RXLPM_CFG (RXLPM_CFG),
.RXLPM_CFG1 (RXLPM_CFG1),
.RXLPM_CM_CFG (RXLPM_CM_CFG),
.RXLPM_GC_CFG (RXLPM_GC_CFG),
.RXLPM_GC_CFG2 (RXLPM_GC_CFG2),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RXLPM_HF_CFG2 (RXLPM_HF_CFG2),
.RXLPM_HF_CFG3 (RXLPM_HF_CFG3),
.RXLPM_HOLD_DURING_EIDLE (RXLPM_HOLD_DURING_EIDLE),
.RXLPM_INCM_CFG (RXLPM_INCM_CFG),
.RXLPM_IPCM_CFG (RXLPM_IPCM_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXLPM_LF_CFG2 (RXLPM_LF_CFG2),
.RXLPM_OSINT_CFG (RXLPM_OSINT_CFG),
.RXOOB_CFG (RXOOB_CFG),
.RXOOB_CLK_CFG_FABRIC (RXOOB_CLK_CFG == "FABRIC"),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME),
.RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT),
.RXOUT_DIV (RXOUT_DIV_BIN),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_CFG2 (RXPI_CFG2),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RXSLIDE_MODE_AUTO (RXSLIDE_MODE == "AUTO"),
.RXSLIDE_MODE_PCS (RXSLIDE_MODE == "PCS"),
.RXSLIDE_MODE_PMA (RXSLIDE_MODE == "PMA"),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE),
.RXSYNC_OVRD (RXSYNC_OVRD),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_CLK25_DIV (RX_CLK25_DIV_BIN),
.RX_CLKMUX_EN (RX_CLKMUX_EN),
.RX_CM_SEL (RX_CM_SEL),
.RX_CM_TRIM (RX_CM_TRIM),
.RX_DATA_WIDTH (RX_DATA_WIDTH_BIN),
.RX_DDI_SEL (RX_DDI_SEL),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN == "TRUE"),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH == "TRUE"),
.RX_OS_CFG (RX_OS_CFG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_BIN),
.RX_XCLK_SEL_RXUSR (RX_XCLK_SEL == "RXUSR"),
.SAS_MAX_COM (SAS_MAX_COM),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SATA_PLL_CFG_VCO_1500MHZ (SATA_PLL_CFG == "VCO_1500MHZ"),
.SATA_PLL_CFG_VCO_750MHZ (SATA_PLL_CFG == "VCO_750MHZ"),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA == "TRUE"),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.TST_RSV (TST_RSV),
.TXBUF_EN (TXBUF_EN == "TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE == "TRUE"),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXGEARBOX_EN (TXGEARBOX_EN == "TRUE"),
.TXOOB_CFG (TXOOB_CFG),
.TXOUT_DIV (TXOUT_DIV_BIN),
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPI_CFG0 (TXPI_CFG0),
.TXPI_CFG1 (TXPI_CFG1),
.TXPI_CFG2 (TXPI_CFG2),
.TXPI_CFG3 (TXPI_CFG3),
.TXPI_CFG4 (TXPI_CFG4),
.TXPI_CFG5 (TXPI_CFG5),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_PPMCLK_SEL_TXUSRCLK2 (TXPI_PPMCLK_SEL == "TXUSRCLK2"),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_OVRD (TXSYNC_OVRD),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TX_CLK25_DIV (TX_CLK25_DIV_BIN),
.TX_CLKMUX_EN (TX_CLKMUX_EN),
.TX_DATA_WIDTH (TX_DATA_WIDTH_BIN),
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE_PIPE (TX_DRIVE_MODE == "PIPE"),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ == "TRUE"),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
.TX_XCLK_SEL_TXUSR (TX_XCLK_SEL == "TXUSR"),
.UCODEER_CLR (UCODEER_CLR),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL),
.INV_TXUSRCLK (INV_TXUSRCLK),
.INV_TXUSRCLK2 (INV_TXUSRCLK2),
.INV_TXPHDLYTSTCLK (INV_TXPHDLYTSTCLK),
.INV_SIGVALIDCLK (INV_SIGVALIDCLK),
.INV_RXUSRCLK (INV_RXUSRCLK),
.INV_RXUSRCLK2 (INV_RXUSRCLK2),
.INV_DRPCLK (INV_DRPCLK),
.INV_DMONITORCLK (INV_DMONITORCLK),
.INV_CLKRSVD0 (INV_CLKRSVD0),
.INV_CLKRSVD1 (INV_CLKRSVD1),
.IO_LOC_PAIRS (IO_LOC_PAIRS)
) gtp_channel (
.GTPRXN (gtprxn),
.GTPRXP (gtprxp),
.GTPTXN (gtptxn),
.GTPTXP (gtptxp),
.DRPRDY (DRPRDY),
.EYESCANDATAERROR (EYESCANDATAERROR),
.PHYSTATUS (PHYSTATUS),
.PMARSVDOUT0 (PMARSVDOUT0),
.PMARSVDOUT1 (PMARSVDOUT1),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCDRLOCK (RXCDRLOCK),
.RXCHANBONDSEQ (RXCHANBONDSEQ),
.RXCHANISALIGNED (RXCHANISALIGNED),
.RXCHANREALIGN (RXCHANREALIGN),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMMADET (RXCOMMADET),
.RXCOMSASDET (RXCOMSASDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXDLYSRESETDONE (RXDLYSRESETDONE),
.RXELECIDLE (RXELECIDLE),
.RXHEADERVALID (RXHEADERVALID),
.RXOSINTDONE (RXOSINTDONE),
.RXOSINTSTARTED (RXOSINTSTARTED),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXPHALIGNDONE (RXPHALIGNDONE),
.RXPMARESETDONE (RXPMARESETDONE),
.RXPRBSERR (RXPRBSERR),
.RXRATEDONE (RXRATEDONE),
.RXRESETDONE (RXRESETDONE),
.RXSYNCDONE (RXSYNCDONE),
.RXSYNCOUT (RXSYNCOUT),
.RXVALID (RXVALID),
.TXCOMFINISH (TXCOMFINISH),
.TXDLYSRESETDONE (TXDLYSRESETDONE),
.TXGEARBOXREADY (TXGEARBOXREADY),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXPHALIGNDONE (TXPHALIGNDONE),
.TXPHINITDONE (TXPHINITDONE),
.TXPMARESETDONE (TXPMARESETDONE),
.TXRATEDONE (TXRATEDONE),
.TXRESETDONE (TXRESETDONE),
.TXSYNCDONE (TXSYNCDONE),
.TXSYNCOUT (TXSYNCOUT),
.DMONITOROUT (DMONITOROUT),
.DRPDO (DRPDO),
.PCSRSVDOUT (PCSRSVDOUT),
.RXCLKCORCNT (RXCLKCORCNT),
.RXDATAVALID (RXDATAVALID),
.RXSTARTOFSEQ (RXSTARTOFSEQ),
.TXBUFSTATUS (TXBUFSTATUS),
.RXBUFSTATUS (RXBUFSTATUS),
.RXHEADER (RXHEADER),
.RXSTATUS (RXSTATUS),
.RXDATA (RXDATA),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXCHBONDO (RXCHBONDO),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.RXPHMONITOR (RXPHMONITOR),
.RXPHSLIPMONITOR (RXPHSLIPMONITOR),
.CFGRESET (CFGRESET),
.CLKRSVD0 (clkrsvd0),
.CLKRSVD1 (clkrsvd1),
.DMONFIFORESET (DMONFIFORESET),
.DMONITORCLK (dmonitorclk),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.EYESCANMODE (EYESCANMODE),
.EYESCANRESET (EYESCANRESET),
.EYESCANTRIGGER (EYESCANTRIGGER),
.GTRESETSEL (GTRESETSEL),
.GTRXRESET (GTRXRESET),
.GTTXRESET (GTTXRESET),
.PMARSVDIN0 (PMARSVDIN0),
.PMARSVDIN1 (PMARSVDIN1),
.PMARSVDIN2 (PMARSVDIN2),
.PMARSVDIN3 (PMARSVDIN3),
.PMARSVDIN4 (PMARSVDIN4),
.RESETOVRD (RESETOVRD),
.RX8B10BEN (RX8B10BEN),
.RXBUFRESET (RXBUFRESET),
.RXCDRFREQRESET (RXCDRFREQRESET),
.RXCDRHOLD (RXCDRHOLD),
.RXCDROVRDEN (RXCDROVRDEN),
.RXCDRRESET (RXCDRRESET),
.RXCDRRESETRSV (RXCDRRESETRSV),
.RXCHBONDEN (RXCHBONDEN),
.RXCHBONDMASTER (RXCHBONDMASTER),
.RXCHBONDSLAVE (RXCHBONDSLAVE),
.RXCOMMADETEN (RXCOMMADETEN),
.RXDDIEN (RXDDIEN),
.RXDFEXYDEN (RXDFEXYDEN),
.RXDLYBYPASS (RXDLYBYPASS),
.RXDLYEN (RXDLYEN),
.RXDLYOVRDEN (RXDLYOVRDEN),
.RXDLYSRESET (RXDLYSRESET),
.RXGEARBOXSLIP (RXGEARBOXSLIP),
.RXLPMHFHOLD (RXLPMHFHOLD),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN),
.RXLPMLFHOLD (RXLPMLFHOLD),
.RXLPMLFOVRDEN (RXLPMLFOVRDEN),
.RXLPMOSINTNTRLEN (RXLPMOSINTNTRLEN),
.RXLPMRESET (RXLPMRESET),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RXOOBRESET (RXOOBRESET),
.RXOSCALRESET (RXOSCALRESET),
.RXOSHOLD (RXOSHOLD),
.RXOSINTEN (RXOSINTEN),
.RXOSINTHOLD (RXOSINTHOLD),
.RXOSINTNTRLEN (RXOSINTNTRLEN),
.RXOSINTOVRDEN (RXOSINTOVRDEN),
.RXOSINTPD (RXOSINTPD),
.RXOSINTSTROBE (RXOSINTSTROBE),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN),
.RXOSOVRDEN (RXOSOVRDEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXPCSRESET (RXPCSRESET),
.RXPHALIGN (RXPHALIGN),
.RXPHALIGNEN (RXPHALIGNEN),
.RXPHDLYPD (RXPHDLYPD),
.RXPHDLYRESET (RXPHDLYRESET),
.RXPHOVRDEN (RXPHOVRDEN),
.RXPMARESET (RXPMARESET),
.RXPOLARITY (RXPOLARITY),
.RXPRBSCNTRESET (RXPRBSCNTRESET),
.RXRATEMODE (RXRATEMODE),
.RXSLIDE (RXSLIDE),
.RXSYNCALLIN (RXSYNCALLIN),
.RXSYNCIN (RXSYNCIN),
.RXSYNCMODE (RXSYNCMODE),
.RXUSERRDY (RXUSERRDY),
.RXUSRCLK2 (rxusrclk2),
.RXUSRCLK (rxusrclk),
.SETERRSTATUS (SETERRSTATUS),
.SIGVALIDCLK (sigvalidclk),
.TX8B10BEN (TX8B10BEN),
.TXCOMINIT (TXCOMINIT),
.TXCOMSAS (TXCOMSAS),
.TXCOMWAKE (TXCOMWAKE),
.TXDEEMPH (TXDEEMPH),
.TXDETECTRX (TXDETECTRX),
.TXDIFFPD (TXDIFFPD),
.TXDLYBYPASS (TXDLYBYPASS),
.TXDLYEN (TXDLYEN),
.TXDLYHOLD (TXDLYHOLD),
.TXDLYOVRDEN (TXDLYOVRDEN),
.TXDLYSRESET (TXDLYSRESET),
.TXDLYUPDOWN (TXDLYUPDOWN),
.TXELECIDLE (TXELECIDLE),
.TXINHIBIT (TXINHIBIT),
.TXPCSRESET (TXPCSRESET),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE),
.TXPHALIGN (TXPHALIGN),
.TXPHALIGNEN (TXPHALIGNEN),
.TXPHDLYPD (TXPHDLYPD),
.TXPHDLYRESET (TXPHDLYRESET),
.TXPHDLYTSTCLK (txphdlytstclk),
.TXPHINIT (TXPHINIT),
.TXPHOVRDEN (TXPHOVRDEN),
.TXPIPPMEN (TXPIPPMEN),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN),
.TXPIPPMPD (TXPIPPMPD),
.TXPIPPMSEL (TXPIPPMSEL),
.TXPISOPD (TXPISOPD),
.TXPMARESET (TXPMARESET),
.TXPOLARITY (TXPOLARITY),
.TXPOSTCURSORINV (TXPOSTCURSORINV),
.TXPRBSFORCEERR (TXPRBSFORCEERR),
.TXPRECURSORINV (TXPRECURSORINV),
.TXRATEMODE (TXRATEMODE),
.TXSTARTSEQ (TXSTARTSEQ),
.TXSWING (TXSWING),
.TXSYNCALLIN (TXSYNCALLIN),
.TXSYNCIN (TXSYNCIN),
.TXSYNCMODE (TXSYNCMODE),
.TXUSERRDY (TXUSERRDY),
.TXUSRCLK2 (txusrclk2),
.TXUSRCLK (txusrclk),
.RXADAPTSELTEST (RXADAPTSELTEST),
.DRPDI (DRPDI),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.TSTIN (TSTIN),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXPD (RXPD),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXPD (TXPD),
.TXSYSCLKSEL (TXSYSCLKSEL),
.LOOPBACK (LOOPBACK),
.RXCHBONDLEVEL (RXCHBONDLEVEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.RXPRBSSEL (RXPRBSSEL),
.RXRATE (RXRATE),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL),
.TXHEADER (TXHEADER),
.TXMARGIN (TXMARGIN),
.TXOUTCLKSEL (TXOUTCLKSEL),
.TXPRBSSEL (TXPRBSSEL),
.TXRATE (TXRATE),
.TXDATA (TXDATA),
.RXCHBONDI (RXCHBONDI),
.RXOSINTCFG (RXOSINTCFG),
.RXOSINTID0 (RXOSINTID0),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXDIFFCTRL (TXDIFFCTRL),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE),
.TXPOSTCURSOR (TXPOSTCURSOR),
.TXPRECURSOR (TXPRECURSOR),
.TXMAINCURSOR (TXMAINCURSOR),
.TXSEQUENCE (TXSEQUENCE),
.DRPADDR (DRPADDR)
);
endmodule
module PCIE_2_1 (
output CFGAERECRCCHECKEN,
output CFGAERECRCGENEN,
input [4:0] CFGAERINTERRUPTMSGNUM,
output CFGAERROOTERRCORRERRRECEIVED,
output CFGAERROOTERRCORRERRREPORTINGEN,
output CFGAERROOTERRFATALERRRECEIVED,
output CFGAERROOTERRFATALERRREPORTINGEN,
output CFGAERROOTERRNONFATALERRRECEIVED,
output CFGAERROOTERRNONFATALERRREPORTINGEN,
output CFGBRIDGESERREN,
output CFGCOMMANDBUSMASTERENABLE,
output CFGCOMMANDINTERRUPTDISABLE,
output CFGCOMMANDIOENABLE,
output CFGCOMMANDMEMENABLE,
output CFGCOMMANDSERREN,
output CFGDEVCONTROL2ARIFORWARDEN,
output CFGDEVCONTROL2ATOMICEGRESSBLOCK,
output CFGDEVCONTROL2ATOMICREQUESTEREN,
output CFGDEVCONTROL2CPLTIMEOUTDIS,
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL,
output CFGDEVCONTROL2IDOCPLEN,
output CFGDEVCONTROL2IDOREQEN,
output CFGDEVCONTROL2LTREN,
output CFGDEVCONTROL2TLPPREFIXBLOCK,
output CFGDEVCONTROLAUXPOWEREN,
output CFGDEVCONTROLCORRERRREPORTINGEN,
output CFGDEVCONTROLENABLERO,
output CFGDEVCONTROLEXTTAGEN,
output CFGDEVCONTROLFATALERRREPORTINGEN,
output [2:0] CFGDEVCONTROLMAXPAYLOAD,
output [2:0] CFGDEVCONTROLMAXREADREQ,
output CFGDEVCONTROLNONFATALREPORTINGEN,
output CFGDEVCONTROLNOSNOOPEN,
output CFGDEVCONTROLPHANTOMEN,
output CFGDEVCONTROLURERRREPORTINGEN,
input [15:0] CFGDEVID,
output CFGDEVSTATUSCORRERRDETECTED,
output CFGDEVSTATUSFATALERRDETECTED,
output CFGDEVSTATUSNONFATALERRDETECTED,
output CFGDEVSTATUSURDETECTED,
input [7:0] CFGDSBUSNUMBER,
input [4:0] CFGDSDEVICENUMBER,
input [2:0] CFGDSFUNCTIONNUMBER,
input [63:0] CFGDSN,
input CFGERRACSN,
input [127:0] CFGERRAERHEADERLOG,
output CFGERRAERHEADERLOGSETN,
input CFGERRATOMICEGRESSBLOCKEDN,
input CFGERRCORN,
input CFGERRCPLABORTN,
output CFGERRCPLRDYN,
input CFGERRCPLTIMEOUTN,
input CFGERRCPLUNEXPECTN,
input CFGERRECRCN,
input CFGERRINTERNALCORN,
input CFGERRINTERNALUNCORN,
input CFGERRLOCKEDN,
input CFGERRMALFORMEDN,
input CFGERRMCBLOCKEDN,
input CFGERRNORECOVERYN,
input CFGERRPOISONEDN,
input CFGERRPOSTEDN,
input [47:0] CFGERRTLPCPLHEADER,
input CFGERRURN,
input CFGFORCECOMMONCLOCKOFF,
input CFGFORCEEXTENDEDSYNCON,
input [2:0] CFGFORCEMPS,
input CFGINTERRUPTASSERTN,
input [7:0] CFGINTERRUPTDI,
output [7:0] CFGINTERRUPTDO,
output [2:0] CFGINTERRUPTMMENABLE,
output CFGINTERRUPTMSIENABLE,
output CFGINTERRUPTMSIXENABLE,
output CFGINTERRUPTMSIXFM,
input CFGINTERRUPTN,
output CFGINTERRUPTRDYN,
input CFGINTERRUPTSTATN,
output [1:0] CFGLINKCONTROLASPMCONTROL,
output CFGLINKCONTROLAUTOBANDWIDTHINTEN,
output CFGLINKCONTROLBANDWIDTHINTEN,
output CFGLINKCONTROLCLOCKPMEN,
output CFGLINKCONTROLCOMMONCLOCK,
output CFGLINKCONTROLEXTENDEDSYNC,
output CFGLINKCONTROLHWAUTOWIDTHDIS,
output CFGLINKCONTROLLINKDISABLE,
output CFGLINKCONTROLRCB,
output CFGLINKCONTROLRETRAINLINK,
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
output CFGLINKSTATUSBANDWIDTHSTATUS,
output [1:0] CFGLINKSTATUSCURRENTSPEED,
output CFGLINKSTATUSDLLACTIVE,
output CFGLINKSTATUSLINKTRAINING,
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH,
input [3:0] CFGMGMTBYTEENN,
input [31:0] CFGMGMTDI,
output [31:0] CFGMGMTDO,
input [9:0] CFGMGMTDWADDR,
input CFGMGMTRDENN,
output CFGMGMTRDWRDONEN,
input CFGMGMTWRENN,
input CFGMGMTWRREADONLYN,
input CFGMGMTWRRW1CASRWN,
output [15:0] CFGMSGDATA,
output CFGMSGRECEIVED,
output CFGMSGRECEIVEDASSERTINTA,
output CFGMSGRECEIVEDASSERTINTB,
output CFGMSGRECEIVEDASSERTINTC,
output CFGMSGRECEIVEDASSERTINTD,
output CFGMSGRECEIVEDDEASSERTINTA,
output CFGMSGRECEIVEDDEASSERTINTB,
output CFGMSGRECEIVEDDEASSERTINTC,
output CFGMSGRECEIVEDDEASSERTINTD,
output CFGMSGRECEIVEDERRCOR,
output CFGMSGRECEIVEDERRFATAL,
output CFGMSGRECEIVEDERRNONFATAL,
output CFGMSGRECEIVEDPMASNAK,
output CFGMSGRECEIVEDPMETO,
output CFGMSGRECEIVEDPMETOACK,
output CFGMSGRECEIVEDPMPME,
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
output CFGMSGRECEIVEDUNLOCK,
input [4:0] CFGPCIECAPINTERRUPTMSGNUM,
output [2:0] CFGPCIELINKSTATE,
output CFGPMCSRPMEEN,
output CFGPMCSRPMESTATUS,
output [1:0] CFGPMCSRPOWERSTATE,
input [1:0] CFGPMFORCESTATE,
input CFGPMFORCESTATEENN,
input CFGPMHALTASPML0SN,
input CFGPMHALTASPML1N,
output CFGPMRCVASREQL1N,
output CFGPMRCVENTERL1N,
output CFGPMRCVENTERL23N,
output CFGPMRCVREQACKN,
input CFGPMSENDPMETON,
input CFGPMTURNOFFOKN,
input CFGPMWAKEN,
input [7:0] CFGPORTNUMBER,
input [7:0] CFGREVID,
output CFGROOTCONTROLPMEINTEN,
output CFGROOTCONTROLSYSERRCORRERREN,
output CFGROOTCONTROLSYSERRFATALERREN,
output CFGROOTCONTROLSYSERRNONFATALERREN,
output CFGSLOTCONTROLELECTROMECHILCTLPULSE,
input [15:0] CFGSUBSYSID,
input [15:0] CFGSUBSYSVENDID,
output CFGTRANSACTION,
output [6:0] CFGTRANSACTIONADDR,
output CFGTRANSACTIONTYPE,
input CFGTRNPENDINGN,
output [6:0] CFGVCTCVCMAP,
input [15:0] CFGVENDID,
input CMRSTN,
input CMSTICKYRSTN,
input [1:0] DBGMODE,
output DBGSCLRA,
output DBGSCLRB,
output DBGSCLRC,
output DBGSCLRD,
output DBGSCLRE,
output DBGSCLRF,
output DBGSCLRG,
output DBGSCLRH,
output DBGSCLRI,
output DBGSCLRJ,
output DBGSCLRK,
input DBGSUBMODE,
output [63:0] DBGVECA,
output [63:0] DBGVECB,
output [11:0] DBGVECC,
input DLRSTN,
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
output [15:0] DRPDO,
input DRPEN,
output DRPRDY,
input DRPWE,
input FUNCLVLRSTN,
output LL2BADDLLPERR,
output LL2BADTLPERR,
output [4:0] LL2LINKSTATUS,
output LL2PROTOCOLERR,
output LL2RECEIVERERR,
output LL2REPLAYROERR,
output LL2REPLAYTOERR,
input LL2SENDASREQL1,
input LL2SENDENTERL1,
input LL2SENDENTERL23,
input LL2SENDPMACK,
input LL2SUSPENDNOW,
output LL2SUSPENDOK,
output LL2TFCINIT1SEQ,
output LL2TFCINIT2SEQ,
input LL2TLPRCV,
output LL2TXIDLE,
output LNKCLKEN,
output [12:0] MIMRXRADDR,
input [67:0] MIMRXRDATA,
output MIMRXREN,
output [12:0] MIMRXWADDR,
output [67:0] MIMRXWDATA,
output MIMRXWEN,
output [12:0] MIMTXRADDR,
input [68:0] MIMTXRDATA,
output MIMTXREN,
output [12:0] MIMTXWADDR,
output [68:0] MIMTXWDATA,
output MIMTXWEN,
input PIPECLK,
input PIPERX0CHANISALIGNED,
input [1:0] PIPERX0CHARISK,
input [15:0] PIPERX0DATA,
input PIPERX0ELECIDLE,
input PIPERX0PHYSTATUS,
output PIPERX0POLARITY,
input [2:0] PIPERX0STATUS,
input PIPERX0VALID,
input PIPERX1CHANISALIGNED,
input [1:0] PIPERX1CHARISK,
input [15:0] PIPERX1DATA,
input PIPERX1ELECIDLE,
input PIPERX1PHYSTATUS,
output PIPERX1POLARITY,
input [2:0] PIPERX1STATUS,
input PIPERX1VALID,
input PIPERX2CHANISALIGNED,
input [1:0] PIPERX2CHARISK,
input [15:0] PIPERX2DATA,
input PIPERX2ELECIDLE,
input PIPERX2PHYSTATUS,
output PIPERX2POLARITY,
input [2:0] PIPERX2STATUS,
input PIPERX2VALID,
input PIPERX3CHANISALIGNED,
input [1:0] PIPERX3CHARISK,
input [15:0] PIPERX3DATA,
input PIPERX3ELECIDLE,
input PIPERX3PHYSTATUS,
output PIPERX3POLARITY,
input [2:0] PIPERX3STATUS,
input PIPERX3VALID,
input PIPERX4CHANISALIGNED,
input [1:0] PIPERX4CHARISK,
input [15:0] PIPERX4DATA,
input PIPERX4ELECIDLE,
input PIPERX4PHYSTATUS,
output PIPERX4POLARITY,
input [2:0] PIPERX4STATUS,
input PIPERX4VALID,
input PIPERX5CHANISALIGNED,
input [1:0] PIPERX5CHARISK,
input [15:0] PIPERX5DATA,
input PIPERX5ELECIDLE,
input PIPERX5PHYSTATUS,
output PIPERX5POLARITY,
input [2:0] PIPERX5STATUS,
input PIPERX5VALID,
input PIPERX6CHANISALIGNED,
input [1:0] PIPERX6CHARISK,
input [15:0] PIPERX6DATA,
input PIPERX6ELECIDLE,
input PIPERX6PHYSTATUS,
output PIPERX6POLARITY,
input [2:0] PIPERX6STATUS,
input PIPERX6VALID,
input PIPERX7CHANISALIGNED,
input [1:0] PIPERX7CHARISK,
input [15:0] PIPERX7DATA,
input PIPERX7ELECIDLE,
input PIPERX7PHYSTATUS,
output PIPERX7POLARITY,
input [2:0] PIPERX7STATUS,
input PIPERX7VALID,
output [1:0] PIPETX0CHARISK,
output PIPETX0COMPLIANCE,
output [15:0] PIPETX0DATA,
output PIPETX0ELECIDLE,
output [1:0] PIPETX0POWERDOWN,
output [1:0] PIPETX1CHARISK,
output PIPETX1COMPLIANCE,
output [15:0] PIPETX1DATA,
output PIPETX1ELECIDLE,
output [1:0] PIPETX1POWERDOWN,
output [1:0] PIPETX2CHARISK,
output PIPETX2COMPLIANCE,
output [15:0] PIPETX2DATA,
output PIPETX2ELECIDLE,
output [1:0] PIPETX2POWERDOWN,
output [1:0] PIPETX3CHARISK,
output PIPETX3COMPLIANCE,
output [15:0] PIPETX3DATA,
output PIPETX3ELECIDLE,
output [1:0] PIPETX3POWERDOWN,
output [1:0] PIPETX4CHARISK,
output PIPETX4COMPLIANCE,
output [15:0] PIPETX4DATA,
output PIPETX4ELECIDLE,
output [1:0] PIPETX4POWERDOWN,
output [1:0] PIPETX5CHARISK,
output PIPETX5COMPLIANCE,
output [15:0] PIPETX5DATA,
output PIPETX5ELECIDLE,
output [1:0] PIPETX5POWERDOWN,
output [1:0] PIPETX6CHARISK,
output PIPETX6COMPLIANCE,
output [15:0] PIPETX6DATA,
output PIPETX6ELECIDLE,
output [1:0] PIPETX6POWERDOWN,
output [1:0] PIPETX7CHARISK,
output PIPETX7COMPLIANCE,
output [15:0] PIPETX7DATA,
output PIPETX7ELECIDLE,
output [1:0] PIPETX7POWERDOWN,
output PIPETXDEEMPH,
output [2:0] PIPETXMARGIN,
output PIPETXRATE,
output PIPETXRCVRDET,
output PIPETXRESET,
input [4:0] PL2DIRECTEDLSTATE,
output PL2L0REQ,
output PL2LINKUP,
output PL2RECEIVERERR,
output PL2RECOVERY,
output PL2RXELECIDLE,
output [1:0] PL2RXPMSTATE,
output PL2SUSPENDOK,
input [2:0] PLDBGMODE,
output [11:0] PLDBGVEC,
output PLDIRECTEDCHANGEDONE,
input PLDIRECTEDLINKAUTON,
input [1:0] PLDIRECTEDLINKCHANGE,
input PLDIRECTEDLINKSPEED,
input [1:0] PLDIRECTEDLINKWIDTH,
input [5:0] PLDIRECTEDLTSSMNEW,
input PLDIRECTEDLTSSMNEWVLD,
input PLDIRECTEDLTSSMSTALL,
input PLDOWNSTREAMDEEMPHSOURCE,
output [2:0] PLINITIALLINKWIDTH,
output [1:0] PLLANEREVERSALMODE,
output PLLINKGEN2CAP,
output PLLINKPARTNERGEN2SUPPORTED,
output PLLINKUPCFGCAP,
output [5:0] PLLTSSMSTATE,
output PLPHYLNKUPN,
output PLRECEIVEDHOTRST,
input PLRSTN,
output [1:0] PLRXPMSTATE,
output PLSELLNKRATE,
output [1:0] PLSELLNKWIDTH,
input PLTRANSMITHOTRST,
output [2:0] PLTXPMSTATE,
input PLUPSTREAMPREFERDEEMPH,
output RECEIVEDFUNCLVLRSTN,
input SYSRSTN,
input TL2ASPMSUSPENDCREDITCHECK,
output TL2ASPMSUSPENDCREDITCHECKOK,
output TL2ASPMSUSPENDREQ,
output TL2ERRFCPE,
output [63:0] TL2ERRHDR,
output TL2ERRMALFORMED,
output TL2ERRRXOVERFLOW,
output TL2PPMSUSPENDOK,
input TL2PPMSUSPENDREQ,
input TLRSTN,
output [11:0] TRNFCCPLD,
output [7:0] TRNFCCPLH,
output [11:0] TRNFCNPD,
output [7:0] TRNFCNPH,
output [11:0] TRNFCPD,
output [7:0] TRNFCPH,
input [2:0] TRNFCSEL,
output TRNLNKUP,
output [7:0] TRNRBARHIT,
output [127:0] TRNRD,
output [63:0] TRNRDLLPDATA,
output [1:0] TRNRDLLPSRCRDY,
input TRNRDSTRDY,
output TRNRECRCERR,
output TRNREOF,
output TRNRERRFWD,
input TRNRFCPRET,
input TRNRNPOK,
input TRNRNPREQ,
output [1:0] TRNRREM,
output TRNRSOF,
output TRNRSRCDSC,
output TRNRSRCRDY,
output [5:0] TRNTBUFAV,
input TRNTCFGGNT,
output TRNTCFGREQ,
input [127:0] TRNTD,
input [31:0] TRNTDLLPDATA,
output TRNTDLLPDSTRDY,
input TRNTDLLPSRCRDY,
output [3:0] TRNTDSTRDY,
input TRNTECRCGEN,
input TRNTEOF,
output TRNTERRDROP,
input TRNTERRFWD,
input [1:0] TRNTREM,
input TRNTSOF,
input TRNTSRCDSC,
input TRNTSRCRDY,
input TRNTSTR,
input USERCLK,
input USERCLK2,
output USERRSTN
);
parameter [11:0] AER_BASE_PTR = 12'd0;
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [15:0] AER_CAP_ID = 16'd0;
parameter AER_CAP_MULTIHEADER = "FALSE";
parameter [11:0] AER_CAP_NEXTPTR = 12'd0;
parameter AER_CAP_ON = "FALSE";
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'd0;
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE";
parameter [3:0] AER_CAP_VERSION = 4'd0;
parameter ALLOW_X8_GEN2 = "FALSE";
parameter [31:0] BAR0 = 32'd0;
parameter [31:0] BAR1 = 32'd0;
parameter [31:0] BAR2 = 32'd0;
parameter [31:0] BAR3 = 32'd0;
parameter [31:0] BAR4 = 32'd0;
parameter [31:0] BAR5 = 32'd0;
parameter [7:0] CAPABILITIES_PTR = 8'd0;
parameter [31:0] CARDBUS_CIS_POINTER = 32'd0;
parameter [23:0] CLASS_CODE = 24'd0;
parameter CMD_INTX_IMPLEMENTED = "FALSE";
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'd0;
parameter [6:0] CRM_MODULE_RSTS = 7'd0;
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'd0;
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'd0;
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "FALSE";
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "FALSE";
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE";
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
parameter [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED = 3'd0;
parameter DEV_CAP_ROLE_BASED_ERROR = "FALSE";
parameter [2:0] DEV_CAP_RSVD_14_12 = 3'd0;
parameter [1:0] DEV_CAP_RSVD_17_16 = 2'd0;
parameter [2:0] DEV_CAP_RSVD_31_29 = 3'd0;
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
parameter DISABLE_ASPM_L1_TIMER = "FALSE";
parameter DISABLE_BAR_FILTERING = "FALSE";
parameter DISABLE_ERR_MSG = "FALSE";
parameter DISABLE_ID_CHECK = "FALSE";
parameter DISABLE_LANE_REVERSAL = "FALSE";
parameter DISABLE_LOCKED_FILTER = "FALSE";
parameter DISABLE_PPM_FILTER = "FALSE";
parameter DISABLE_RX_POISONED_RESP = "FALSE";
parameter DISABLE_RX_TC_FILTER = "FALSE";
parameter DISABLE_SCRAMBLING = "FALSE";
parameter [7:0] DNSTREAM_LINK_NUM = 8'd0;
parameter [11:0] DSN_BASE_PTR = 12'd0;
parameter [15:0] DSN_CAP_ID = 16'd0;
parameter [11:0] DSN_CAP_NEXTPTR = 12'd0;
parameter DSN_CAP_ON = "FALSE";
parameter [3:0] DSN_CAP_VERSION = 4'd0;
parameter [10:0] ENABLE_MSG_ROUTE = 11'd0;
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
parameter ENTER_RVRY_EI_L0 = "FALSE";
parameter EXIT_LOOPBACK_ON_EI = "FALSE";
parameter [31:0] EXPANSION_ROM = 32'd0;
parameter [5:0] EXT_CFG_CAP_PTR = 6'd0;
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'd0;
parameter [7:0] HEADER_TYPE = 8'd0;
parameter [4:0] INFER_EI = 5'd0;
parameter [7:0] INTERRUPT_PIN = 8'd0;
parameter INTERRUPT_STAT_AUTO = "FALSE";
parameter IS_SWITCH = "FALSE";
parameter [9:0] LAST_CONFIG_DWORD = 10'd0;
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE";
parameter [1:0] LINK_CAP_ASPM_SUPPORT = 2'd0;
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'd0;
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'd0;
parameter [0:0] LINK_CAP_RSVD_23 = 1'd0;
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'd0;
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE";
parameter [14:0] LL_ACK_TIMEOUT = 15'd0;
parameter LL_ACK_TIMEOUT_EN = "FALSE";
parameter [1:0] LL_ACK_TIMEOUT_FUNC = 2'd0;
parameter [14:0] LL_REPLAY_TIMEOUT = 15'd0;
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
parameter [1:0] LL_REPLAY_TIMEOUT_FUNC = 2'd0;
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'd0;
parameter MPS_FORCE = "FALSE";
parameter [7:0] MSIX_BASE_PTR = 8'd0;
parameter [7:0] MSIX_CAP_ID = 8'd0;
parameter [7:0] MSIX_CAP_NEXTPTR = 8'd0;
parameter MSIX_CAP_ON = "FALSE";
parameter [2:0] MSIX_CAP_PBA_BIR = 3'd0;
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'd0;
parameter [2:0] MSIX_CAP_TABLE_BIR = 3'd0;
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'd0;
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'd0;
parameter [7:0] MSI_BASE_PTR = 8'd0;
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "FALSE";
parameter [7:0] MSI_CAP_ID = 8'd0;
parameter [2:0] MSI_CAP_MULTIMSGCAP = 3'd0;
parameter [7:0] MSI_CAP_NEXTPTR = 8'd0;
parameter MSI_CAP_ON = "FALSE";
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE";
parameter [7:0] N_FTS_COMCLK_GEN1 = 8'd255;
parameter [7:0] N_FTS_COMCLK_GEN2 = 8'd255;
parameter [7:0] N_FTS_GEN1 = 8'd255;
parameter [7:0] N_FTS_GEN2 = 8'd255;
parameter [7:0] PCIE_BASE_PTR = 8'd0;
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'd0;
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'd0;
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'd0;
parameter [7:0] PCIE_CAP_NEXTPTR = 8'd0;
parameter PCIE_CAP_ON = "FALSE";
parameter [1:0] PCIE_CAP_RSVD_15_14 = 2'd0;
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
parameter [3:0] PCIE_REVISION = 4'd2;
parameter PL_FAST_TRAIN = "FALSE";
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'd0;
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
parameter [1:0] PM_ASPML0S_TIMEOUT_FUNC = 2'd0;
parameter PM_ASPM_FASTEXIT = "FALSE";
parameter [7:0] PM_BASE_PTR = 8'd0;
parameter PM_CAP_D1SUPPORT = "FALSE";
parameter PM_CAP_D2SUPPORT = "FALSE";
parameter PM_CAP_DSI = "FALSE";
parameter [7:0] PM_CAP_ID = 8'd0;
parameter [7:0] PM_CAP_NEXTPTR = 8'd0;
parameter PM_CAP_ON = "FALSE";
parameter [4:0] PM_CAP_PMESUPPORT = 5'd0;
parameter PM_CAP_PME_CLOCK = "FALSE";
parameter [0:0] PM_CAP_RSVD_04 = 1'd0;
parameter [2:0] PM_CAP_VERSION = 3'd3;
parameter PM_CSR_B2B3 = "FALSE";
parameter PM_CSR_BPCCEN = "FALSE";
parameter PM_CSR_NOSOFTRST = "FALSE";
parameter [7:0] PM_DATA0 = 8'd0;
parameter [7:0] PM_DATA1 = 8'd0;
parameter [7:0] PM_DATA2 = 8'd0;
parameter [7:0] PM_DATA3 = 8'd0;
parameter [7:0] PM_DATA4 = 8'd0;
parameter [7:0] PM_DATA5 = 8'd0;
parameter [7:0] PM_DATA6 = 8'd0;
parameter [7:0] PM_DATA7 = 8'd0;
parameter [1:0] PM_DATA_SCALE0 = 2'd0;
parameter [1:0] PM_DATA_SCALE1 = 2'd0;
parameter [1:0] PM_DATA_SCALE2 = 2'd0;
parameter [1:0] PM_DATA_SCALE3 = 2'd0;
parameter [1:0] PM_DATA_SCALE4 = 2'd0;
parameter [1:0] PM_DATA_SCALE5 = 2'd0;
parameter [1:0] PM_DATA_SCALE6 = 2'd0;
parameter [1:0] PM_DATA_SCALE7 = 2'd0;
parameter PM_MF = "FALSE";
parameter [11:0] RBAR_BASE_PTR = 12'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'd0;
parameter [15:0] RBAR_CAP_ID = 16'd0;
parameter [2:0] RBAR_CAP_INDEX0 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX1 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX2 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX3 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX4 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX5 = 3'd0;
parameter [11:0] RBAR_CAP_NEXTPTR = 12'd0;
parameter RBAR_CAP_ON = "FALSE";
parameter [31:0] RBAR_CAP_SUP0 = 32'd0;
parameter [31:0] RBAR_CAP_SUP1 = 32'd0;
parameter [31:0] RBAR_CAP_SUP2 = 32'd0;
parameter [31:0] RBAR_CAP_SUP3 = 32'd0;
parameter [31:0] RBAR_CAP_SUP4 = 32'd0;
parameter [31:0] RBAR_CAP_SUP5 = 32'd0;
parameter [3:0] RBAR_CAP_VERSION = 4'd0;
parameter [2:0] RBAR_NUM = 3'd0;
parameter [1:0] RECRC_CHK = 2'd0;
parameter RECRC_CHK_TRIM = "FALSE";
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
parameter [1:0] RP_AUTO_SPD = 2'd0;
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'd0;
parameter SELECT_DLL_IF = "FALSE";
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'd0;
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'd0;
parameter [0:0] SPARE_BIT0 = 1'd0;
parameter [0:0] SPARE_BIT1 = 1'd0;
parameter [0:0] SPARE_BIT2 = 1'd0;
parameter [0:0] SPARE_BIT3 = 1'd0;
parameter [0:0] SPARE_BIT4 = 1'd0;
parameter [0:0] SPARE_BIT5 = 1'd0;
parameter [0:0] SPARE_BIT6 = 1'd0;
parameter [0:0] SPARE_BIT7 = 1'd0;
parameter [0:0] SPARE_BIT8 = 1'd0;
parameter [7:0] SPARE_BYTE0 = 8'd0;
parameter [7:0] SPARE_BYTE1 = 8'd0;
parameter [7:0] SPARE_BYTE2 = 8'd0;
parameter [7:0] SPARE_BYTE3 = 8'd0;
parameter [31:0] SPARE_WORD0 = 32'd0;
parameter [31:0] SPARE_WORD1 = 32'd0;
parameter [31:0] SPARE_WORD2 = 32'd0;
parameter [31:0] SPARE_WORD3 = 32'd0;
parameter SSL_MESSAGE_AUTO = "FALSE";
parameter TECRC_EP_INV = "FALSE";
parameter TL_RBYPASS = "FALSE";
parameter [1:0] TL_RX_RAM_RDATA_LATENCY = 2'd1;
parameter TL_TFC_DISABLE = "FALSE";
parameter TL_TX_CHECKS_DISABLE = "FALSE";
parameter [1:0] TL_TX_RAM_RDATA_LATENCY = 2'd1;
parameter TRN_DW = "FALSE";
parameter TRN_NP_FC = "FALSE";
parameter UPCONFIG_CAPABLE = "FALSE";
parameter UPSTREAM_FACING = "FALSE";
parameter UR_ATOMIC = "FALSE";
parameter UR_CFG1 = "FALSE";
parameter UR_INV_REQ = "FALSE";
parameter UR_PRS_RESPONSE = "FALSE";
parameter USER_CLK2_DIV2 = "FALSE";
parameter USE_RID_PINS = "FALSE";
parameter VC0_CPL_INFINITE = "FALSE";
parameter [12:0] VC0_RX_RAM_LIMIT = 13'd0;
parameter [6:0] VC0_TOTAL_CREDITS_CH = 7'd36;
parameter [6:0] VC0_TOTAL_CREDITS_NPH = 7'd12;
parameter [6:0] VC0_TOTAL_CREDITS_PH = 7'd32;
parameter [11:0] VC_BASE_PTR = 12'd0;
parameter [15:0] VC_CAP_ID = 16'd0;
parameter [11:0] VC_CAP_NEXTPTR = 12'd0;
parameter VC_CAP_ON = "FALSE";
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
parameter [3:0] VC_CAP_VERSION = 4'd0;
parameter [11:0] VSEC_BASE_PTR = 12'd0;
parameter [15:0] VSEC_CAP_HDR_ID = 16'd0;
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'd0;
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'd0;
parameter [15:0] VSEC_CAP_ID = 16'd0;
parameter VSEC_CAP_IS_LINK_VISIBLE = "FALSE";
parameter [11:0] VSEC_CAP_NEXTPTR = 12'd0;
parameter VSEC_CAP_ON = "FALSE";
parameter [3:0] VSEC_CAP_VERSION = 4'd0;
parameter [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY = 3'd0;
parameter [2:0] DEV_CAP_ENDPOINT_L1_LATENCY = 3'd0;
parameter [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 2'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 3'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN2 = 3'd0;
parameter [0:0] LINK_CONTROL_RCB = 1'd0;
parameter [0:0] MSI_CAP_MULTIMSG_EXTENSION = 1'd0;
parameter [2:0] PM_CAP_AUXCURRENT = 3'd0;
parameter [1:0] SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 2'd0;
parameter [2:0] USER_CLK_FREQ = 3'd0;
parameter [2:0] PL_AUTO_CONFIG = 3'd0;
parameter [0:0] TL_RX_RAM_RADDR_LATENCY = 1'd0;
parameter [0:0] TL_RX_RAM_WRITE_LATENCY = 1'd0;
parameter [0:0] TL_TX_RAM_RADDR_LATENCY = 1'd0;
parameter [0:0] TL_TX_RAM_WRITE_LATENCY = 1'd0;
parameter [10:0] VC0_TOTAL_CREDITS_CD = 11'd0;
parameter [10:0] VC0_TOTAL_CREDITS_NPD = 11'd0;
parameter [10:0] VC0_TOTAL_CREDITS_PD = 11'd0;
parameter [4:0] VC0_TX_LASTPACKET = 5'd0;
parameter [1:0] CFG_ECRC_ERR_CPLSTAT = 2'd0;
PCIE_2_1_VPR #(
.AER_BASE_PTR(AER_BASE_PTR),
.AER_CAP_ECRC_CHECK_CAPABLE(AER_CAP_ECRC_CHECK_CAPABLE == "TRUE"),
.AER_CAP_ECRC_GEN_CAPABLE(AER_CAP_ECRC_GEN_CAPABLE == "TRUE"),
.AER_CAP_ID(AER_CAP_ID),
.AER_CAP_MULTIHEADER(AER_CAP_MULTIHEADER == "TRUE"),
.AER_CAP_NEXTPTR(AER_CAP_NEXTPTR),
.AER_CAP_ON(AER_CAP_ON == "TRUE"),
.AER_CAP_OPTIONAL_ERR_SUPPORT(AER_CAP_OPTIONAL_ERR_SUPPORT),
.AER_CAP_PERMIT_ROOTERR_UPDATE(AER_CAP_PERMIT_ROOTERR_UPDATE == "TRUE"),
.AER_CAP_VERSION(AER_CAP_VERSION),
.ALLOW_X8_GEN2(ALLOW_X8_GEN2 == "TRUE"),
.BAR0(BAR0),
.BAR1(BAR1),
.BAR2(BAR2),
.BAR3(BAR3),
.BAR4(BAR4),
.BAR5(BAR5),
.CAPABILITIES_PTR(CAPABILITIES_PTR),
.CARDBUS_CIS_POINTER(CARDBUS_CIS_POINTER),
.CLASS_CODE(CLASS_CODE),
.CMD_INTX_IMPLEMENTED(CMD_INTX_IMPLEMENTED == "TRUE"),
.CPL_TIMEOUT_DISABLE_SUPPORTED(CPL_TIMEOUT_DISABLE_SUPPORTED == "TRUE"),
.CPL_TIMEOUT_RANGES_SUPPORTED(CPL_TIMEOUT_RANGES_SUPPORTED),
.CRM_MODULE_RSTS(CRM_MODULE_RSTS),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED == "TRUE"),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED(DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED == "TRUE"),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED(DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED == "TRUE"),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED(DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED == "TRUE"),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED(DEV_CAP2_CAS128_COMPLETER_SUPPORTED == "TRUE"),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED(DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED == "TRUE"),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED(DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED == "TRUE"),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED(DEV_CAP2_LTR_MECHANISM_SUPPORTED == "TRUE"),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING(DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING == "TRUE"),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED(DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE(DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE == "TRUE"),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE(DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE == "TRUE"),
.DEV_CAP_EXT_TAG_SUPPORTED(DEV_CAP_EXT_TAG_SUPPORTED == "TRUE"),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE(DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE == "TRUE"),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED),
.DEV_CAP_ROLE_BASED_ERROR(DEV_CAP_ROLE_BASED_ERROR == "TRUE"),
.DEV_CAP_RSVD_14_12(DEV_CAP_RSVD_14_12),
.DEV_CAP_RSVD_17_16(DEV_CAP_RSVD_17_16),
.DEV_CAP_RSVD_31_29(DEV_CAP_RSVD_31_29),
.DEV_CONTROL_AUX_POWER_SUPPORTED(DEV_CONTROL_AUX_POWER_SUPPORTED == "TRUE"),
.DEV_CONTROL_EXT_TAG_DEFAULT(DEV_CONTROL_EXT_TAG_DEFAULT == "TRUE"),
.DISABLE_ASPM_L1_TIMER(DISABLE_ASPM_L1_TIMER == "TRUE"),
.DISABLE_BAR_FILTERING(DISABLE_BAR_FILTERING == "TRUE"),
.DISABLE_ERR_MSG(DISABLE_ERR_MSG == "TRUE"),
.DISABLE_ID_CHECK(DISABLE_ID_CHECK == "TRUE"),
.DISABLE_LANE_REVERSAL(DISABLE_LANE_REVERSAL == "TRUE"),
.DISABLE_LOCKED_FILTER(DISABLE_LOCKED_FILTER == "TRUE"),
.DISABLE_PPM_FILTER(DISABLE_PPM_FILTER == "TRUE"),
.DISABLE_RX_POISONED_RESP(DISABLE_RX_POISONED_RESP == "TRUE"),
.DISABLE_RX_TC_FILTER(DISABLE_RX_TC_FILTER == "TRUE"),
.DISABLE_SCRAMBLING(DISABLE_SCRAMBLING == "TRUE"),
.DNSTREAM_LINK_NUM(DNSTREAM_LINK_NUM),
.DSN_BASE_PTR(DSN_BASE_PTR),
.DSN_CAP_ID(DSN_CAP_ID),
.DSN_CAP_NEXTPTR(DSN_CAP_NEXTPTR),
.DSN_CAP_ON(DSN_CAP_ON == "TRUE"),
.DSN_CAP_VERSION(DSN_CAP_VERSION),
.ENABLE_MSG_ROUTE(ENABLE_MSG_ROUTE),
.ENABLE_RX_TD_ECRC_TRIM(ENABLE_RX_TD_ECRC_TRIM == "TRUE"),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED(ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED == "TRUE"),
.ENTER_RVRY_EI_L0(ENTER_RVRY_EI_L0 == "TRUE"),
.EXIT_LOOPBACK_ON_EI(EXIT_LOOPBACK_ON_EI == "TRUE"),
.EXPANSION_ROM(EXPANSION_ROM),
.EXT_CFG_CAP_PTR(EXT_CFG_CAP_PTR),
.EXT_CFG_XP_CAP_PTR(EXT_CFG_XP_CAP_PTR),
.HEADER_TYPE(HEADER_TYPE),
.INFER_EI(INFER_EI),
.INTERRUPT_PIN(INTERRUPT_PIN),
.INTERRUPT_STAT_AUTO(INTERRUPT_STAT_AUTO == "TRUE"),
.IS_SWITCH(IS_SWITCH == "TRUE"),
.LAST_CONFIG_DWORD(LAST_CONFIG_DWORD),
.LINK_CAP_ASPM_OPTIONALITY(LINK_CAP_ASPM_OPTIONALITY == "TRUE"),
.LINK_CAP_ASPM_SUPPORT(LINK_CAP_ASPM_SUPPORT),
.LINK_CAP_CLOCK_POWER_MANAGEMENT(LINK_CAP_CLOCK_POWER_MANAGEMENT == "TRUE"),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP(LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP == "TRUE"),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP(LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP == "TRUE"),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_RSVD_23(LINK_CAP_RSVD_23),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE(LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE == "TRUE"),
.LINK_CTRL2_DEEMPHASIS(LINK_CTRL2_DEEMPHASIS == "TRUE"),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE(LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE == "TRUE"),
.LINK_CTRL2_TARGET_LINK_SPEED(LINK_CTRL2_TARGET_LINK_SPEED),
.LINK_STATUS_SLOT_CLOCK_CONFIG(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE"),
.LL_ACK_TIMEOUT(LL_ACK_TIMEOUT),
.LL_ACK_TIMEOUT_EN(LL_ACK_TIMEOUT_EN == "TRUE"),
.LL_ACK_TIMEOUT_FUNC(LL_ACK_TIMEOUT_FUNC),
.LL_REPLAY_TIMEOUT(LL_REPLAY_TIMEOUT),
.LL_REPLAY_TIMEOUT_EN(LL_REPLAY_TIMEOUT_EN == "TRUE"),
.LL_REPLAY_TIMEOUT_FUNC(LL_REPLAY_TIMEOUT_FUNC),
.LTSSM_MAX_LINK_WIDTH(LTSSM_MAX_LINK_WIDTH),
.MPS_FORCE(MPS_FORCE == "TRUE"),
.MSIX_BASE_PTR(MSIX_BASE_PTR),
.MSIX_CAP_ID(MSIX_CAP_ID),
.MSIX_CAP_NEXTPTR(MSIX_CAP_NEXTPTR),
.MSIX_CAP_ON(MSIX_CAP_ON == "TRUE"),
.MSIX_CAP_PBA_BIR(MSIX_CAP_PBA_BIR),
.MSIX_CAP_PBA_OFFSET(MSIX_CAP_PBA_OFFSET),
.MSIX_CAP_TABLE_BIR(MSIX_CAP_TABLE_BIR),
.MSIX_CAP_TABLE_OFFSET(MSIX_CAP_TABLE_OFFSET),
.MSIX_CAP_TABLE_SIZE(MSIX_CAP_TABLE_SIZE),
.MSI_BASE_PTR(MSI_BASE_PTR),
.MSI_CAP_64_BIT_ADDR_CAPABLE(MSI_CAP_64_BIT_ADDR_CAPABLE == "TRUE"),
.MSI_CAP_ID(MSI_CAP_ID),
.MSI_CAP_MULTIMSGCAP(MSI_CAP_MULTIMSGCAP),
.MSI_CAP_NEXTPTR(MSI_CAP_NEXTPTR),
.MSI_CAP_ON(MSI_CAP_ON == "TRUE"),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE(MSI_CAP_PER_VECTOR_MASKING_CAPABLE == "TRUE"),
.N_FTS_COMCLK_GEN1(N_FTS_COMCLK_GEN1),
.N_FTS_COMCLK_GEN2(N_FTS_COMCLK_GEN2),
.N_FTS_GEN1(N_FTS_GEN1),
.N_FTS_GEN2(N_FTS_GEN2),
.PCIE_BASE_PTR(PCIE_BASE_PTR),
.PCIE_CAP_CAPABILITY_ID(PCIE_CAP_CAPABILITY_ID),
.PCIE_CAP_CAPABILITY_VERSION(PCIE_CAP_CAPABILITY_VERSION),
.PCIE_CAP_DEVICE_PORT_TYPE(PCIE_CAP_DEVICE_PORT_TYPE),
.PCIE_CAP_NEXTPTR(PCIE_CAP_NEXTPTR),
.PCIE_CAP_ON(PCIE_CAP_ON == "TRUE"),
.PCIE_CAP_RSVD_15_14(PCIE_CAP_RSVD_15_14),
.PCIE_CAP_SLOT_IMPLEMENTED(PCIE_CAP_SLOT_IMPLEMENTED == "TRUE"),
.PCIE_REVISION(PCIE_REVISION),
.PL_FAST_TRAIN(PL_FAST_TRAIN == "TRUE"),
.PM_ASPML0S_TIMEOUT(PM_ASPML0S_TIMEOUT),
.PM_ASPML0S_TIMEOUT_EN(PM_ASPML0S_TIMEOUT_EN == "TRUE"),
.PM_ASPML0S_TIMEOUT_FUNC(PM_ASPML0S_TIMEOUT_FUNC),
.PM_ASPM_FASTEXIT(PM_ASPM_FASTEXIT == "TRUE"),
.PM_BASE_PTR(PM_BASE_PTR),
.PM_CAP_D1SUPPORT(PM_CAP_D1SUPPORT == "TRUE"),
.PM_CAP_D2SUPPORT(PM_CAP_D2SUPPORT == "TRUE"),
.PM_CAP_DSI(PM_CAP_DSI == "TRUE"),
.PM_CAP_ID(PM_CAP_ID),
.PM_CAP_NEXTPTR(PM_CAP_NEXTPTR),
.PM_CAP_ON(PM_CAP_ON == "TRUE"),
.PM_CAP_PMESUPPORT(PM_CAP_PMESUPPORT),
.PM_CAP_PME_CLOCK(PM_CAP_PME_CLOCK == "TRUE"),
.PM_CAP_RSVD_04(PM_CAP_RSVD_04),
.PM_CAP_VERSION(PM_CAP_VERSION),
.PM_CSR_B2B3(PM_CSR_B2B3 == "TRUE"),
.PM_CSR_BPCCEN(PM_CSR_BPCCEN == "TRUE"),
.PM_CSR_NOSOFTRST(PM_CSR_NOSOFTRST == "TRUE"),
.PM_DATA0(PM_DATA0),
.PM_DATA1(PM_DATA1),
.PM_DATA2(PM_DATA2),
.PM_DATA3(PM_DATA3),
.PM_DATA4(PM_DATA4),
.PM_DATA5(PM_DATA5),
.PM_DATA6(PM_DATA6),
.PM_DATA7(PM_DATA7),
.PM_DATA_SCALE0(PM_DATA_SCALE0),
.PM_DATA_SCALE1(PM_DATA_SCALE1),
.PM_DATA_SCALE2(PM_DATA_SCALE2),
.PM_DATA_SCALE3(PM_DATA_SCALE3),
.PM_DATA_SCALE4(PM_DATA_SCALE4),
.PM_DATA_SCALE5(PM_DATA_SCALE5),
.PM_DATA_SCALE6(PM_DATA_SCALE6),
.PM_DATA_SCALE7(PM_DATA_SCALE7),
.PM_MF(PM_MF == "TRUE"),
.RBAR_BASE_PTR(RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0(RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1(RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2(RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3(RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4(RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5(RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID(RBAR_CAP_ID),
.RBAR_CAP_INDEX0(RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1(RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2(RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3(RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4(RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5(RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR(RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON(RBAR_CAP_ON == "TRUE"),
.RBAR_CAP_SUP0(RBAR_CAP_SUP0),
.RBAR_CAP_SUP1(RBAR_CAP_SUP1),
.RBAR_CAP_SUP2(RBAR_CAP_SUP2),
.RBAR_CAP_SUP3(RBAR_CAP_SUP3),
.RBAR_CAP_SUP4(RBAR_CAP_SUP4),
.RBAR_CAP_SUP5(RBAR_CAP_SUP5),
.RBAR_CAP_VERSION(RBAR_CAP_VERSION),
.RBAR_NUM(RBAR_NUM),
.RECRC_CHK(RECRC_CHK),
.RECRC_CHK_TRIM(RECRC_CHK_TRIM == "TRUE"),
.ROOT_CAP_CRS_SW_VISIBILITY(ROOT_CAP_CRS_SW_VISIBILITY == "TRUE"),
.RP_AUTO_SPD(RP_AUTO_SPD),
.RP_AUTO_SPD_LOOPCNT(RP_AUTO_SPD_LOOPCNT),
.SELECT_DLL_IF(SELECT_DLL_IF == "TRUE"),
.SLOT_CAP_ATT_BUTTON_PRESENT(SLOT_CAP_ATT_BUTTON_PRESENT == "TRUE"),
.SLOT_CAP_ATT_INDICATOR_PRESENT(SLOT_CAP_ATT_INDICATOR_PRESENT == "TRUE"),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT(SLOT_CAP_ELEC_INTERLOCK_PRESENT == "TRUE"),
.SLOT_CAP_HOTPLUG_CAPABLE(SLOT_CAP_HOTPLUG_CAPABLE == "TRUE"),
.SLOT_CAP_HOTPLUG_SURPRISE(SLOT_CAP_HOTPLUG_SURPRISE == "TRUE"),
.SLOT_CAP_MRL_SENSOR_PRESENT(SLOT_CAP_MRL_SENSOR_PRESENT == "TRUE"),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT(SLOT_CAP_NO_CMD_COMPLETED_SUPPORT == "TRUE"),
.SLOT_CAP_PHYSICAL_SLOT_NUM(SLOT_CAP_PHYSICAL_SLOT_NUM),
.SLOT_CAP_POWER_CONTROLLER_PRESENT(SLOT_CAP_POWER_CONTROLLER_PRESENT == "TRUE"),
.SLOT_CAP_POWER_INDICATOR_PRESENT(SLOT_CAP_POWER_INDICATOR_PRESENT == "TRUE"),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE(SLOT_CAP_SLOT_POWER_LIMIT_VALUE),
.SPARE_BIT0(SPARE_BIT0),
.SPARE_BIT1(SPARE_BIT1),
.SPARE_BIT2(SPARE_BIT2),
.SPARE_BIT3(SPARE_BIT3),
.SPARE_BIT4(SPARE_BIT4),
.SPARE_BIT5(SPARE_BIT5),
.SPARE_BIT6(SPARE_BIT6),
.SPARE_BIT7(SPARE_BIT7),
.SPARE_BIT8(SPARE_BIT8),
.SPARE_BYTE0(SPARE_BYTE0),
.SPARE_BYTE1(SPARE_BYTE1),
.SPARE_BYTE2(SPARE_BYTE2),
.SPARE_BYTE3(SPARE_BYTE3),
.SPARE_WORD0(SPARE_WORD0),
.SPARE_WORD1(SPARE_WORD1),
.SPARE_WORD2(SPARE_WORD2),
.SPARE_WORD3(SPARE_WORD3),
.SSL_MESSAGE_AUTO(SSL_MESSAGE_AUTO == "TRUE"),
.TECRC_EP_INV(TECRC_EP_INV == "TRUE"),
.TL_RBYPASS(TL_RBYPASS == "TRUE"),
.TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.TL_TFC_DISABLE(TL_TFC_DISABLE == "TRUE"),
.TL_TX_CHECKS_DISABLE(TL_TX_CHECKS_DISABLE == "TRUE"),
.TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.TRN_DW(TRN_DW == "TRUE"),
.TRN_NP_FC(TRN_NP_FC == "TRUE"),
.UPCONFIG_CAPABLE(UPCONFIG_CAPABLE == "TRUE"),
.UPSTREAM_FACING(UPSTREAM_FACING == "TRUE"),
.UR_ATOMIC(UR_ATOMIC == "TRUE"),
.UR_CFG1(UR_CFG1 == "TRUE"),
.UR_INV_REQ(UR_INV_REQ == "TRUE"),
.UR_PRS_RESPONSE(UR_PRS_RESPONSE == "TRUE"),
.USER_CLK2_DIV2(USER_CLK2_DIV2 == "TRUE"),
.USE_RID_PINS(USE_RID_PINS == "TRUE"),
.VC0_CPL_INFINITE(VC0_CPL_INFINITE == "TRUE"),
.VC0_RX_RAM_LIMIT(VC0_RX_RAM_LIMIT),
.VC0_TOTAL_CREDITS_CH(VC0_TOTAL_CREDITS_CH),
.VC0_TOTAL_CREDITS_NPH(VC0_TOTAL_CREDITS_NPH),
.VC0_TOTAL_CREDITS_PH(VC0_TOTAL_CREDITS_PH),
.VC_BASE_PTR(VC_BASE_PTR),
.VC_CAP_ID(VC_CAP_ID),
.VC_CAP_NEXTPTR(VC_CAP_NEXTPTR),
.VC_CAP_ON(VC_CAP_ON == "TRUE"),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS(VC_CAP_REJECT_SNOOP_TRANSACTIONS == "TRUE"),
.VC_CAP_VERSION(VC_CAP_VERSION),
.VSEC_BASE_PTR(VSEC_BASE_PTR),
.VSEC_CAP_HDR_ID(VSEC_CAP_HDR_ID),
.VSEC_CAP_HDR_LENGTH(VSEC_CAP_HDR_LENGTH),
.VSEC_CAP_HDR_REVISION(VSEC_CAP_HDR_REVISION),
.VSEC_CAP_ID(VSEC_CAP_ID),
.VSEC_CAP_IS_LINK_VISIBLE(VSEC_CAP_IS_LINK_VISIBLE == "TRUE"),
.VSEC_CAP_NEXTPTR(VSEC_CAP_NEXTPTR),
.VSEC_CAP_ON(VSEC_CAP_ON == "TRUE"),
.VSEC_CAP_VERSION(VSEC_CAP_VERSION),
.DEV_CAP_ENDPOINT_L0S_LATENCY(DEV_CAP_ENDPOINT_L0S_LATENCY),
.DEV_CAP_ENDPOINT_L1_LATENCY(DEV_CAP_ENDPOINT_L1_LATENCY),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1(LINK_CAP_L0S_EXIT_LATENCY_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2(LINK_CAP_L0S_EXIT_LATENCY_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_GEN1(LINK_CAP_L1_EXIT_LATENCY_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_GEN2(LINK_CAP_L1_EXIT_LATENCY_GEN2),
.LINK_CONTROL_RCB(LINK_CONTROL_RCB),
.MSI_CAP_MULTIMSG_EXTENSION(MSI_CAP_MULTIMSG_EXTENSION),
.PM_CAP_AUXCURRENT(PM_CAP_AUXCURRENT),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE(SLOT_CAP_SLOT_POWER_LIMIT_SCALE),
.USER_CLK_FREQ(USER_CLK_FREQ),
.PL_AUTO_CONFIG(PL_AUTO_CONFIG),
.TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY),
.TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY),
.VC0_TOTAL_CREDITS_CD(VC0_TOTAL_CREDITS_CD),
.VC0_TOTAL_CREDITS_NPD(VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_PD(VC0_TOTAL_CREDITS_PD),
.VC0_TX_LASTPACKET(VC0_TX_LASTPACKET),
.CFG_ECRC_ERR_CPLSTAT(CFG_ECRC_ERR_CPLSTAT)
) _TECHMAP_REPLACE_ (
.CFGAERECRCCHECKEN(CFGAERECRCCHECKEN),
.CFGAERECRCGENEN(CFGAERECRCGENEN),
.CFGAERINTERRUPTMSGNUM(CFGAERINTERRUPTMSGNUM),
.CFGAERROOTERRCORRERRRECEIVED(CFGAERROOTERRCORRERRRECEIVED),
.CFGAERROOTERRCORRERRREPORTINGEN(CFGAERROOTERRCORRERRREPORTINGEN),
.CFGAERROOTERRFATALERRRECEIVED(CFGAERROOTERRFATALERRRECEIVED),
.CFGAERROOTERRFATALERRREPORTINGEN(CFGAERROOTERRFATALERRREPORTINGEN),
.CFGAERROOTERRNONFATALERRRECEIVED(CFGAERROOTERRNONFATALERRRECEIVED),
.CFGAERROOTERRNONFATALERRREPORTINGEN(CFGAERROOTERRNONFATALERRREPORTINGEN),
.CFGBRIDGESERREN(CFGBRIDGESERREN),
.CFGCOMMANDBUSMASTERENABLE(CFGCOMMANDBUSMASTERENABLE),
.CFGCOMMANDINTERRUPTDISABLE(CFGCOMMANDINTERRUPTDISABLE),
.CFGCOMMANDIOENABLE(CFGCOMMANDIOENABLE),
.CFGCOMMANDMEMENABLE(CFGCOMMANDMEMENABLE),
.CFGCOMMANDSERREN(CFGCOMMANDSERREN),
.CFGDEVCONTROL2ARIFORWARDEN(CFGDEVCONTROL2ARIFORWARDEN),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK(CFGDEVCONTROL2ATOMICEGRESSBLOCK),
.CFGDEVCONTROL2ATOMICREQUESTEREN(CFGDEVCONTROL2ATOMICREQUESTEREN),
.CFGDEVCONTROL2CPLTIMEOUTDIS(CFGDEVCONTROL2CPLTIMEOUTDIS),
.CFGDEVCONTROL2CPLTIMEOUTVAL(CFGDEVCONTROL2CPLTIMEOUTVAL),
.CFGDEVCONTROL2IDOCPLEN(CFGDEVCONTROL2IDOCPLEN),
.CFGDEVCONTROL2IDOREQEN(CFGDEVCONTROL2IDOREQEN),
.CFGDEVCONTROL2LTREN(CFGDEVCONTROL2LTREN),
.CFGDEVCONTROL2TLPPREFIXBLOCK(CFGDEVCONTROL2TLPPREFIXBLOCK),
.CFGDEVCONTROLAUXPOWEREN(CFGDEVCONTROLAUXPOWEREN),
.CFGDEVCONTROLCORRERRREPORTINGEN(CFGDEVCONTROLCORRERRREPORTINGEN),
.CFGDEVCONTROLENABLERO(CFGDEVCONTROLENABLERO),
.CFGDEVCONTROLEXTTAGEN(CFGDEVCONTROLEXTTAGEN),
.CFGDEVCONTROLFATALERRREPORTINGEN(CFGDEVCONTROLFATALERRREPORTINGEN),
.CFGDEVCONTROLMAXPAYLOAD(CFGDEVCONTROLMAXPAYLOAD),
.CFGDEVCONTROLMAXREADREQ(CFGDEVCONTROLMAXREADREQ),
.CFGDEVCONTROLNONFATALREPORTINGEN(CFGDEVCONTROLNONFATALREPORTINGEN),
.CFGDEVCONTROLNOSNOOPEN(CFGDEVCONTROLNOSNOOPEN),
.CFGDEVCONTROLPHANTOMEN(CFGDEVCONTROLPHANTOMEN),
.CFGDEVCONTROLURERRREPORTINGEN(CFGDEVCONTROLURERRREPORTINGEN),
.CFGDEVID(CFGDEVID),
.CFGDEVSTATUSCORRERRDETECTED(CFGDEVSTATUSCORRERRDETECTED),
.CFGDEVSTATUSFATALERRDETECTED(CFGDEVSTATUSFATALERRDETECTED),
.CFGDEVSTATUSNONFATALERRDETECTED(CFGDEVSTATUSNONFATALERRDETECTED),
.CFGDEVSTATUSURDETECTED(CFGDEVSTATUSURDETECTED),
.CFGDSBUSNUMBER(CFGDSBUSNUMBER),
.CFGDSDEVICENUMBER(CFGDSDEVICENUMBER),
.CFGDSFUNCTIONNUMBER(CFGDSFUNCTIONNUMBER),
.CFGDSN(CFGDSN),
.CFGERRACSN(CFGERRACSN),
.CFGERRAERHEADERLOG(CFGERRAERHEADERLOG),
.CFGERRAERHEADERLOGSETN(CFGERRAERHEADERLOGSETN),
.CFGERRATOMICEGRESSBLOCKEDN(CFGERRATOMICEGRESSBLOCKEDN),
.CFGERRCORN(CFGERRCORN),
.CFGERRCPLABORTN(CFGERRCPLABORTN),
.CFGERRCPLRDYN(CFGERRCPLRDYN),
.CFGERRCPLTIMEOUTN(CFGERRCPLTIMEOUTN),
.CFGERRCPLUNEXPECTN(CFGERRCPLUNEXPECTN),
.CFGERRECRCN(CFGERRECRCN),
.CFGERRINTERNALCORN(CFGERRINTERNALCORN),
.CFGERRINTERNALUNCORN(CFGERRINTERNALUNCORN),
.CFGERRLOCKEDN(CFGERRLOCKEDN),
.CFGERRMALFORMEDN(CFGERRMALFORMEDN),
.CFGERRMCBLOCKEDN(CFGERRMCBLOCKEDN),
.CFGERRNORECOVERYN(CFGERRNORECOVERYN),
.CFGERRPOISONEDN(CFGERRPOISONEDN),
.CFGERRPOSTEDN(CFGERRPOSTEDN),
.CFGERRTLPCPLHEADER(CFGERRTLPCPLHEADER),
.CFGERRURN(CFGERRURN),
.CFGFORCECOMMONCLOCKOFF(CFGFORCECOMMONCLOCKOFF),
.CFGFORCEEXTENDEDSYNCON(CFGFORCEEXTENDEDSYNCON),
.CFGFORCEMPS(CFGFORCEMPS),
.CFGINTERRUPTASSERTN(CFGINTERRUPTASSERTN),
.CFGINTERRUPTDI(CFGINTERRUPTDI),
.CFGINTERRUPTDO(CFGINTERRUPTDO),
.CFGINTERRUPTMMENABLE(CFGINTERRUPTMMENABLE),
.CFGINTERRUPTMSIENABLE(CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIXENABLE(CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFM(CFGINTERRUPTMSIXFM),
.CFGINTERRUPTN(CFGINTERRUPTN),
.CFGINTERRUPTRDYN(CFGINTERRUPTRDYN),
.CFGINTERRUPTSTATN(CFGINTERRUPTSTATN),
.CFGLINKCONTROLASPMCONTROL(CFGLINKCONTROLASPMCONTROL),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN(CFGLINKCONTROLAUTOBANDWIDTHINTEN),
.CFGLINKCONTROLBANDWIDTHINTEN(CFGLINKCONTROLBANDWIDTHINTEN),
.CFGLINKCONTROLCLOCKPMEN(CFGLINKCONTROLCLOCKPMEN),
.CFGLINKCONTROLCOMMONCLOCK(CFGLINKCONTROLCOMMONCLOCK),
.CFGLINKCONTROLEXTENDEDSYNC(CFGLINKCONTROLEXTENDEDSYNC),
.CFGLINKCONTROLHWAUTOWIDTHDIS(CFGLINKCONTROLHWAUTOWIDTHDIS),
.CFGLINKCONTROLLINKDISABLE(CFGLINKCONTROLLINKDISABLE),
.CFGLINKCONTROLRCB(CFGLINKCONTROLRCB),
.CFGLINKCONTROLRETRAINLINK(CFGLINKCONTROLRETRAINLINK),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS(CFGLINKSTATUSAUTOBANDWIDTHSTATUS),
.CFGLINKSTATUSBANDWIDTHSTATUS(CFGLINKSTATUSBANDWIDTHSTATUS),
.CFGLINKSTATUSCURRENTSPEED(CFGLINKSTATUSCURRENTSPEED),
.CFGLINKSTATUSDLLACTIVE(CFGLINKSTATUSDLLACTIVE),
.CFGLINKSTATUSLINKTRAINING(CFGLINKSTATUSLINKTRAINING),
.CFGLINKSTATUSNEGOTIATEDWIDTH(CFGLINKSTATUSNEGOTIATEDWIDTH),
.CFGMGMTBYTEENN(CFGMGMTBYTEENN),
.CFGMGMTDI(CFGMGMTDI),
.CFGMGMTDO(CFGMGMTDO),
.CFGMGMTDWADDR(CFGMGMTDWADDR),
.CFGMGMTRDENN(CFGMGMTRDENN),
.CFGMGMTRDWRDONEN(CFGMGMTRDWRDONEN),
.CFGMGMTWRENN(CFGMGMTWRENN),
.CFGMGMTWRREADONLYN(CFGMGMTWRREADONLYN),
.CFGMGMTWRRW1CASRWN(CFGMGMTWRRW1CASRWN),
.CFGMSGDATA(CFGMSGDATA),
.CFGMSGRECEIVED(CFGMSGRECEIVED),
.CFGMSGRECEIVEDASSERTINTA(CFGMSGRECEIVEDASSERTINTA),
.CFGMSGRECEIVEDASSERTINTB(CFGMSGRECEIVEDASSERTINTB),
.CFGMSGRECEIVEDASSERTINTC(CFGMSGRECEIVEDASSERTINTC),
.CFGMSGRECEIVEDASSERTINTD(CFGMSGRECEIVEDASSERTINTD),
.CFGMSGRECEIVEDDEASSERTINTA(CFGMSGRECEIVEDDEASSERTINTA),
.CFGMSGRECEIVEDDEASSERTINTB(CFGMSGRECEIVEDDEASSERTINTB),
.CFGMSGRECEIVEDDEASSERTINTC(CFGMSGRECEIVEDDEASSERTINTC),
.CFGMSGRECEIVEDDEASSERTINTD(CFGMSGRECEIVEDDEASSERTINTD),
.CFGMSGRECEIVEDERRCOR(CFGMSGRECEIVEDERRCOR),
.CFGMSGRECEIVEDERRFATAL(CFGMSGRECEIVEDERRFATAL),
.CFGMSGRECEIVEDERRNONFATAL(CFGMSGRECEIVEDERRNONFATAL),
.CFGMSGRECEIVEDPMASNAK(CFGMSGRECEIVEDPMASNAK),
.CFGMSGRECEIVEDPMETO(CFGMSGRECEIVEDPMETO),
.CFGMSGRECEIVEDPMETOACK(CFGMSGRECEIVEDPMETOACK),
.CFGMSGRECEIVEDPMPME(CFGMSGRECEIVEDPMPME),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT(CFGMSGRECEIVEDSETSLOTPOWERLIMIT),
.CFGMSGRECEIVEDUNLOCK(CFGMSGRECEIVEDUNLOCK),
.CFGPCIECAPINTERRUPTMSGNUM(CFGPCIECAPINTERRUPTMSGNUM),
.CFGPCIELINKSTATE(CFGPCIELINKSTATE),
.CFGPMCSRPMEEN(CFGPMCSRPMEEN),
.CFGPMCSRPMESTATUS(CFGPMCSRPMESTATUS),
.CFGPMCSRPOWERSTATE(CFGPMCSRPOWERSTATE),
.CFGPMFORCESTATE(CFGPMFORCESTATE),
.CFGPMFORCESTATEENN(CFGPMFORCESTATEENN),
.CFGPMHALTASPML0SN(CFGPMHALTASPML0SN),
.CFGPMHALTASPML1N(CFGPMHALTASPML1N),
.CFGPMRCVASREQL1N(CFGPMRCVASREQL1N),
.CFGPMRCVENTERL1N(CFGPMRCVENTERL1N),
.CFGPMRCVENTERL23N(CFGPMRCVENTERL23N),
.CFGPMRCVREQACKN(CFGPMRCVREQACKN),
.CFGPMSENDPMETON(CFGPMSENDPMETON),
.CFGPMTURNOFFOKN(CFGPMTURNOFFOKN),
.CFGPMWAKEN(CFGPMWAKEN),
.CFGPORTNUMBER(CFGPORTNUMBER),
.CFGREVID(CFGREVID),
.CFGROOTCONTROLPMEINTEN(CFGROOTCONTROLPMEINTEN),
.CFGROOTCONTROLSYSERRCORRERREN(CFGROOTCONTROLSYSERRCORRERREN),
.CFGROOTCONTROLSYSERRFATALERREN(CFGROOTCONTROLSYSERRFATALERREN),
.CFGROOTCONTROLSYSERRNONFATALERREN(CFGROOTCONTROLSYSERRNONFATALERREN),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE(CFGSLOTCONTROLELECTROMECHILCTLPULSE),
.CFGSUBSYSID(CFGSUBSYSID),
.CFGSUBSYSVENDID(CFGSUBSYSVENDID),
.CFGTRANSACTION(CFGTRANSACTION),
.CFGTRANSACTIONADDR(CFGTRANSACTIONADDR),
.CFGTRANSACTIONTYPE(CFGTRANSACTIONTYPE),
.CFGTRNPENDINGN(CFGTRNPENDINGN),
.CFGVCTCVCMAP(CFGVCTCVCMAP),
.CFGVENDID(CFGVENDID),
.CMRSTN(CMRSTN),
.CMSTICKYRSTN(CMSTICKYRSTN),
.DBGMODE(DBGMODE),
.DBGSCLRA(DBGSCLRA),
.DBGSCLRB(DBGSCLRB),
.DBGSCLRC(DBGSCLRC),
.DBGSCLRD(DBGSCLRD),
.DBGSCLRE(DBGSCLRE),
.DBGSCLRF(DBGSCLRF),
.DBGSCLRG(DBGSCLRG),
.DBGSCLRH(DBGSCLRH),
.DBGSCLRI(DBGSCLRI),
.DBGSCLRJ(DBGSCLRJ),
.DBGSCLRK(DBGSCLRK),
.DBGSUBMODE(DBGSUBMODE),
.DBGVECA(DBGVECA),
.DBGVECB(DBGVECB),
.DBGVECC(DBGVECC),
.DLRSTN(DLRSTN),
.DRPADDR(DRPADDR),
.DRPCLK(DRPCLK),
.DRPDI(DRPDI),
.DRPDO(DRPDO),
.DRPEN(DRPEN),
.DRPRDY(DRPRDY),
.DRPWE(DRPWE),
.FUNCLVLRSTN(FUNCLVLRSTN),
.LL2BADDLLPERR(LL2BADDLLPERR),
.LL2BADTLPERR(LL2BADTLPERR),
.LL2LINKSTATUS(LL2LINKSTATUS),
.LL2PROTOCOLERR(LL2PROTOCOLERR),
.LL2RECEIVERERR(LL2RECEIVERERR),
.LL2REPLAYROERR(LL2REPLAYROERR),
.LL2REPLAYTOERR(LL2REPLAYTOERR),
.LL2SENDASREQL1(LL2SENDASREQL1),
.LL2SENDENTERL1(LL2SENDENTERL1),
.LL2SENDENTERL23(LL2SENDENTERL23),
.LL2SENDPMACK(LL2SENDPMACK),
.LL2SUSPENDNOW(LL2SUSPENDNOW),
.LL2SUSPENDOK(LL2SUSPENDOK),
.LL2TFCINIT1SEQ(LL2TFCINIT1SEQ),
.LL2TFCINIT2SEQ(LL2TFCINIT2SEQ),
.LL2TLPRCV(LL2TLPRCV),
.LL2TXIDLE(LL2TXIDLE),
.LNKCLKEN(LNKCLKEN),
.MIMRXRADDR(MIMRXRADDR),
.MIMRXRDATA(MIMRXRDATA),
.MIMRXREN(MIMRXREN),
.MIMRXWADDR(MIMRXWADDR),
.MIMRXWDATA(MIMRXWDATA),
.MIMRXWEN(MIMRXWEN),
.MIMTXRADDR(MIMTXRADDR),
.MIMTXRDATA(MIMTXRDATA),
.MIMTXREN(MIMTXREN),
.MIMTXWADDR(MIMTXWADDR),
.MIMTXWDATA(MIMTXWDATA),
.MIMTXWEN(MIMTXWEN),
.PIPECLK(PIPECLK),
.PIPERX0CHANISALIGNED(PIPERX0CHANISALIGNED),
.PIPERX0CHARISK(PIPERX0CHARISK),
.PIPERX0DATA(PIPERX0DATA),
.PIPERX0ELECIDLE(PIPERX0ELECIDLE),
.PIPERX0PHYSTATUS(PIPERX0PHYSTATUS),
.PIPERX0POLARITY(PIPERX0POLARITY),
.PIPERX0STATUS(PIPERX0STATUS),
.PIPERX0VALID(PIPERX0VALID),
.PIPERX1CHANISALIGNED(PIPERX1CHANISALIGNED),
.PIPERX1CHARISK(PIPERX1CHARISK),
.PIPERX1DATA(PIPERX1DATA),
.PIPERX1ELECIDLE(PIPERX1ELECIDLE),
.PIPERX1PHYSTATUS(PIPERX1PHYSTATUS),
.PIPERX1POLARITY(PIPERX1POLARITY),
.PIPERX1STATUS(PIPERX1STATUS),
.PIPERX1VALID(PIPERX1VALID),
.PIPERX2CHANISALIGNED(PIPERX2CHANISALIGNED),
.PIPERX2CHARISK(PIPERX2CHARISK),
.PIPERX2DATA(PIPERX2DATA),
.PIPERX2ELECIDLE(PIPERX2ELECIDLE),
.PIPERX2PHYSTATUS(PIPERX2PHYSTATUS),
.PIPERX2POLARITY(PIPERX2POLARITY),
.PIPERX2STATUS(PIPERX2STATUS),
.PIPERX2VALID(PIPERX2VALID),
.PIPERX3CHANISALIGNED(PIPERX3CHANISALIGNED),
.PIPERX3CHARISK(PIPERX3CHARISK),
.PIPERX3DATA(PIPERX3DATA),
.PIPERX3ELECIDLE(PIPERX3ELECIDLE),
.PIPERX3PHYSTATUS(PIPERX3PHYSTATUS),
.PIPERX3POLARITY(PIPERX3POLARITY),
.PIPERX3STATUS(PIPERX3STATUS),
.PIPERX3VALID(PIPERX3VALID),
.PIPERX4CHANISALIGNED(PIPERX4CHANISALIGNED),
.PIPERX4CHARISK(PIPERX4CHARISK),
.PIPERX4DATA(PIPERX4DATA),
.PIPERX4ELECIDLE(PIPERX4ELECIDLE),
.PIPERX4PHYSTATUS(PIPERX4PHYSTATUS),
.PIPERX4POLARITY(PIPERX4POLARITY),
.PIPERX4STATUS(PIPERX4STATUS),
.PIPERX4VALID(PIPERX4VALID),
.PIPERX5CHANISALIGNED(PIPERX5CHANISALIGNED),
.PIPERX5CHARISK(PIPERX5CHARISK),
.PIPERX5DATA(PIPERX5DATA),
.PIPERX5ELECIDLE(PIPERX5ELECIDLE),
.PIPERX5PHYSTATUS(PIPERX5PHYSTATUS),
.PIPERX5POLARITY(PIPERX5POLARITY),
.PIPERX5STATUS(PIPERX5STATUS),
.PIPERX5VALID(PIPERX5VALID),
.PIPERX6CHANISALIGNED(PIPERX6CHANISALIGNED),
.PIPERX6CHARISK(PIPERX6CHARISK),
.PIPERX6DATA(PIPERX6DATA),
.PIPERX6ELECIDLE(PIPERX6ELECIDLE),
.PIPERX6PHYSTATUS(PIPERX6PHYSTATUS),
.PIPERX6POLARITY(PIPERX6POLARITY),
.PIPERX6STATUS(PIPERX6STATUS),
.PIPERX6VALID(PIPERX6VALID),
.PIPERX7CHANISALIGNED(PIPERX7CHANISALIGNED),
.PIPERX7CHARISK(PIPERX7CHARISK),
.PIPERX7DATA(PIPERX7DATA),
.PIPERX7ELECIDLE(PIPERX7ELECIDLE),
.PIPERX7PHYSTATUS(PIPERX7PHYSTATUS),
.PIPERX7POLARITY(PIPERX7POLARITY),
.PIPERX7STATUS(PIPERX7STATUS),
.PIPERX7VALID(PIPERX7VALID),
.PIPETX0CHARISK(PIPETX0CHARISK),
.PIPETX0COMPLIANCE(PIPETX0COMPLIANCE),
.PIPETX0DATA(PIPETX0DATA),
.PIPETX0ELECIDLE(PIPETX0ELECIDLE),
.PIPETX0POWERDOWN(PIPETX0POWERDOWN),
.PIPETX1CHARISK(PIPETX1CHARISK),
.PIPETX1COMPLIANCE(PIPETX1COMPLIANCE),
.PIPETX1DATA(PIPETX1DATA),
.PIPETX1ELECIDLE(PIPETX1ELECIDLE),
.PIPETX1POWERDOWN(PIPETX1POWERDOWN),
.PIPETX2CHARISK(PIPETX2CHARISK),
.PIPETX2COMPLIANCE(PIPETX2COMPLIANCE),
.PIPETX2DATA(PIPETX2DATA),
.PIPETX2ELECIDLE(PIPETX2ELECIDLE),
.PIPETX2POWERDOWN(PIPETX2POWERDOWN),
.PIPETX3CHARISK(PIPETX3CHARISK),
.PIPETX3COMPLIANCE(PIPETX3COMPLIANCE),
.PIPETX3DATA(PIPETX3DATA),
.PIPETX3ELECIDLE(PIPETX3ELECIDLE),
.PIPETX3POWERDOWN(PIPETX3POWERDOWN),
.PIPETX4CHARISK(PIPETX4CHARISK),
.PIPETX4COMPLIANCE(PIPETX4COMPLIANCE),
.PIPETX4DATA(PIPETX4DATA),
.PIPETX4ELECIDLE(PIPETX4ELECIDLE),
.PIPETX4POWERDOWN(PIPETX4POWERDOWN),
.PIPETX5CHARISK(PIPETX5CHARISK),
.PIPETX5COMPLIANCE(PIPETX5COMPLIANCE),
.PIPETX5DATA(PIPETX5DATA),
.PIPETX5ELECIDLE(PIPETX5ELECIDLE),
.PIPETX5POWERDOWN(PIPETX5POWERDOWN),
.PIPETX6CHARISK(PIPETX6CHARISK),
.PIPETX6COMPLIANCE(PIPETX6COMPLIANCE),
.PIPETX6DATA(PIPETX6DATA),
.PIPETX6ELECIDLE(PIPETX6ELECIDLE),
.PIPETX6POWERDOWN(PIPETX6POWERDOWN),
.PIPETX7CHARISK(PIPETX7CHARISK),
.PIPETX7COMPLIANCE(PIPETX7COMPLIANCE),
.PIPETX7DATA(PIPETX7DATA),
.PIPETX7ELECIDLE(PIPETX7ELECIDLE),
.PIPETX7POWERDOWN(PIPETX7POWERDOWN),
.PIPETXDEEMPH(PIPETXDEEMPH),
.PIPETXMARGIN(PIPETXMARGIN),
.PIPETXRATE(PIPETXRATE),
.PIPETXRCVRDET(PIPETXRCVRDET),
.PIPETXRESET(PIPETXRESET),
.PL2DIRECTEDLSTATE(PL2DIRECTEDLSTATE),
.PL2L0REQ(PL2L0REQ),
.PL2LINKUP(PL2LINKUP),
.PL2RECEIVERERR(PL2RECEIVERERR),
.PL2RECOVERY(PL2RECOVERY),
.PL2RXELECIDLE(PL2RXELECIDLE),
.PL2RXPMSTATE(PL2RXPMSTATE),
.PL2SUSPENDOK(PL2SUSPENDOK),
.PLDBGMODE(PLDBGMODE),
.PLDBGVEC(PLDBGVEC),
.PLDIRECTEDCHANGEDONE(PLDIRECTEDCHANGEDONE),
.PLDIRECTEDLINKAUTON(PLDIRECTEDLINKAUTON),
.PLDIRECTEDLINKCHANGE(PLDIRECTEDLINKCHANGE),
.PLDIRECTEDLINKSPEED(PLDIRECTEDLINKSPEED),
.PLDIRECTEDLINKWIDTH(PLDIRECTEDLINKWIDTH),
.PLDIRECTEDLTSSMNEW(PLDIRECTEDLTSSMNEW),
.PLDIRECTEDLTSSMNEWVLD(PLDIRECTEDLTSSMNEWVLD),
.PLDIRECTEDLTSSMSTALL(PLDIRECTEDLTSSMSTALL),
.PLDOWNSTREAMDEEMPHSOURCE(PLDOWNSTREAMDEEMPHSOURCE),
.PLINITIALLINKWIDTH(PLINITIALLINKWIDTH),
.PLLANEREVERSALMODE(PLLANEREVERSALMODE),
.PLLINKGEN2CAP(PLLINKGEN2CAP),
.PLLINKPARTNERGEN2SUPPORTED(PLLINKPARTNERGEN2SUPPORTED),
.PLLINKUPCFGCAP(PLLINKUPCFGCAP),
.PLLTSSMSTATE(PLLTSSMSTATE),
.PLPHYLNKUPN(PLPHYLNKUPN),
.PLRECEIVEDHOTRST(PLRECEIVEDHOTRST),
.PLRSTN(PLRSTN),
.PLRXPMSTATE(PLRXPMSTATE),
.PLSELLNKRATE(PLSELLNKRATE),
.PLSELLNKWIDTH(PLSELLNKWIDTH),
.PLTRANSMITHOTRST(PLTRANSMITHOTRST),
.PLTXPMSTATE(PLTXPMSTATE),
.PLUPSTREAMPREFERDEEMPH(PLUPSTREAMPREFERDEEMPH),
.RECEIVEDFUNCLVLRSTN(RECEIVEDFUNCLVLRSTN),
.SYSRSTN(SYSRSTN),
.TL2ASPMSUSPENDCREDITCHECK(TL2ASPMSUSPENDCREDITCHECK),
.TL2ASPMSUSPENDCREDITCHECKOK(TL2ASPMSUSPENDCREDITCHECKOK),
.TL2ASPMSUSPENDREQ(TL2ASPMSUSPENDREQ),
.TL2ERRFCPE(TL2ERRFCPE),
.TL2ERRHDR(TL2ERRHDR),
.TL2ERRMALFORMED(TL2ERRMALFORMED),
.TL2ERRRXOVERFLOW(TL2ERRRXOVERFLOW),
.TL2PPMSUSPENDOK(TL2PPMSUSPENDOK),
.TL2PPMSUSPENDREQ(TL2PPMSUSPENDREQ),
.TLRSTN(TLRSTN),
.TRNFCCPLD(TRNFCCPLD),
.TRNFCCPLH(TRNFCCPLH),
.TRNFCNPD(TRNFCNPD),
.TRNFCNPH(TRNFCNPH),
.TRNFCPD(TRNFCPD),
.TRNFCPH(TRNFCPH),
.TRNFCSEL(TRNFCSEL),
.TRNLNKUP(TRNLNKUP),
.TRNRBARHIT(TRNRBARHIT),
.TRNRD(TRNRD),
.TRNRDLLPDATA(TRNRDLLPDATA),
.TRNRDLLPSRCRDY(TRNRDLLPSRCRDY),
.TRNRDSTRDY(TRNRDSTRDY),
.TRNRECRCERR(TRNRECRCERR),
.TRNREOF(TRNREOF),
.TRNRERRFWD(TRNRERRFWD),
.TRNRFCPRET(TRNRFCPRET),
.TRNRNPOK(TRNRNPOK),
.TRNRNPREQ(TRNRNPREQ),
.TRNRREM(TRNRREM),
.TRNRSOF(TRNRSOF),
.TRNRSRCDSC(TRNRSRCDSC),
.TRNRSRCRDY(TRNRSRCRDY),
.TRNTBUFAV(TRNTBUFAV),
.TRNTCFGGNT(TRNTCFGGNT),
.TRNTCFGREQ(TRNTCFGREQ),
.TRNTD(TRNTD),
.TRNTDLLPDATA(TRNTDLLPDATA),
.TRNTDLLPDSTRDY(TRNTDLLPDSTRDY),
.TRNTDLLPSRCRDY(TRNTDLLPSRCRDY),
.TRNTDSTRDY(TRNTDSTRDY),
.TRNTECRCGEN(TRNTECRCGEN),
.TRNTEOF(TRNTEOF),
.TRNTERRDROP(TRNTERRDROP),
.TRNTERRFWD(TRNTERRFWD),
.TRNTREM(TRNTREM),
.TRNTSOF(TRNTSOF),
.TRNTSRCDSC(TRNTSRCDSC),
.TRNTSRCRDY(TRNTSRCRDY),
.TRNTSTR(TRNTSTR),
.USERCLK(USERCLK),
.USERCLK2(USERCLK2),
.USERRSTN(USERRSTN)
);
endmodule
|
module decoder ( cx, d );
input [18:0] cx;
output [5:0] d;
wire n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434,
n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530;
MUX2X1 U122 ( .B(n413), .A(n414), .S(cx[5]), .Y(d[5]) );
NOR2X1 U123 ( .A(n415), .B(n416), .Y(n414) );
MUX2X1 U124 ( .B(n417), .A(n418), .S(cx[4]), .Y(d[4]) );
NOR2X1 U125 ( .A(n419), .B(n416), .Y(n418) );
NAND2X1 U126 ( .A(n420), .B(n421), .Y(n416) );
MUX2X1 U127 ( .B(n422), .A(n421), .S(n423), .Y(d[3]) );
AND2X1 U128 ( .A(n420), .B(n424), .Y(n422) );
INVX1 U129 ( .A(n425), .Y(n420) );
NAND3X1 U130 ( .A(n426), .B(n427), .C(n428), .Y(n425) );
MUX2X1 U131 ( .B(n429), .A(n430), .S(cx[2]), .Y(d[2]) );
NOR2X1 U132 ( .A(n431), .B(n432), .Y(n430) );
INVX1 U133 ( .A(n433), .Y(n429) );
MUX2X1 U134 ( .B(n434), .A(n435), .S(n436), .Y(d[1]) );
NOR2X1 U135 ( .A(n433), .B(n432), .Y(n434) );
NAND2X1 U136 ( .A(n437), .B(n427), .Y(n432) );
MUX2X1 U137 ( .B(n427), .A(n438), .S(cx[0]), .Y(d[0]) );
AND2X1 U138 ( .A(n426), .B(n437), .Y(n438) );
INVX1 U139 ( .A(n439), .Y(n437) );
NAND3X1 U140 ( .A(n428), .B(n421), .C(n424), .Y(n439) );
NOR2X1 U141 ( .A(n415), .B(n419), .Y(n424) );
INVX1 U142 ( .A(n413), .Y(n419) );
NAND3X1 U143 ( .A(n440), .B(n441), .C(n442), .Y(n413) );
NOR2X1 U144 ( .A(n443), .B(n444), .Y(n442) );
NAND2X1 U145 ( .A(n445), .B(n446), .Y(n444) );
INVX1 U146 ( .A(n417), .Y(n415) );
NAND3X1 U147 ( .A(n447), .B(n448), .C(n449), .Y(n417) );
NOR2X1 U148 ( .A(n450), .B(n451), .Y(n449) );
NAND2X1 U149 ( .A(n446), .B(n452), .Y(n451) );
NAND3X1 U150 ( .A(n453), .B(n454), .C(n455), .Y(n450) );
NOR2X1 U151 ( .A(n456), .B(n457), .Y(n448) );
NOR2X1 U152 ( .A(n458), .B(n459), .Y(n447) );
NAND3X1 U153 ( .A(n460), .B(n461), .C(n462), .Y(n421) );
NOR2X1 U154 ( .A(n440), .B(n463), .Y(n462) );
INVX1 U155 ( .A(n464), .Y(n428) );
NAND3X1 U156 ( .A(n465), .B(n466), .C(n467), .Y(n464) );
NOR2X1 U157 ( .A(n468), .B(n469), .Y(n467) );
OAI21X1 U158 ( .A(n470), .B(n453), .C(n471), .Y(n469) );
OAI21X1 U159 ( .A(n452), .B(n472), .C(n473), .Y(n471) );
MUX2X1 U160 ( .B(n474), .A(n475), .S(n463), .Y(n472) );
NAND2X1 U161 ( .A(n476), .B(n453), .Y(n474) );
OAI21X1 U162 ( .A(n477), .B(n440), .C(n478), .Y(n468) );
NAND2X1 U163 ( .A(n479), .B(n480), .Y(n478) );
OAI21X1 U164 ( .A(n457), .B(n454), .C(n476), .Y(n480) );
INVX1 U165 ( .A(n481), .Y(n477) );
OAI22X1 U166 ( .A(n453), .B(n473), .C(n443), .D(n482), .Y(n481) );
MUX2X1 U167 ( .B(n483), .A(n456), .S(n484), .Y(n466) );
AND2X1 U168 ( .A(n485), .B(n486), .Y(n465) );
MUX2X1 U169 ( .B(n487), .A(n470), .S(n457), .Y(n486) );
NOR2X1 U170 ( .A(n452), .B(n456), .Y(n487) );
MUX2X1 U171 ( .B(n488), .A(n489), .S(n490), .Y(n485) );
NAND2X1 U172 ( .A(n491), .B(n492), .Y(n489) );
AOI22X1 U173 ( .A(n445), .B(n493), .C(n455), .D(n453), .Y(n492) );
AOI22X1 U174 ( .A(n482), .B(n475), .C(n440), .D(n494), .Y(n491) );
OAI21X1 U175 ( .A(n473), .B(n479), .C(n495), .Y(n488) );
INVX1 U176 ( .A(n459), .Y(n495) );
NAND3X1 U177 ( .A(n494), .B(n470), .C(n475), .Y(n459) );
NOR2X1 U178 ( .A(n431), .B(n433), .Y(n426) );
NOR2X1 U179 ( .A(n496), .B(n497), .Y(n433) );
NAND3X1 U180 ( .A(n463), .B(n440), .C(n498), .Y(n497) );
NAND3X1 U181 ( .A(n490), .B(n461), .C(n499), .Y(n496) );
NOR2X1 U182 ( .A(n473), .B(n500), .Y(n499) );
INVX1 U183 ( .A(n501), .Y(n461) );
NAND3X1 U184 ( .A(n484), .B(n483), .C(n502), .Y(n501) );
NOR2X1 U185 ( .A(n456), .B(n503), .Y(n502) );
NAND2X1 U186 ( .A(n443), .B(n445), .Y(n503) );
INVX1 U187 ( .A(n435), .Y(n431) );
NAND3X1 U188 ( .A(n490), .B(n441), .C(n504), .Y(n435) );
NOR2X1 U189 ( .A(n445), .B(n505), .Y(n504) );
NAND2X1 U190 ( .A(n443), .B(n454), .Y(n505) );
NOR2X1 U191 ( .A(n506), .B(n507), .Y(n441) );
NAND3X1 U192 ( .A(n500), .B(n473), .C(n498), .Y(n507) );
NOR3X1 U193 ( .A(n457), .B(n508), .C(n453), .Y(n498) );
NAND3X1 U194 ( .A(n456), .B(n494), .C(n509), .Y(n506) );
NOR2X1 U195 ( .A(n483), .B(n484), .Y(n509) );
INVX1 U196 ( .A(n476), .Y(n484) );
INVX1 U197 ( .A(n493), .Y(n483) );
OR2X1 U198 ( .A(n510), .B(n511), .Y(n427) );
NAND3X1 U199 ( .A(n463), .B(n460), .C(n440), .Y(n511) );
INVX1 U200 ( .A(n454), .Y(n440) );
XOR2X1 U201 ( .A(n512), .B(n513), .Y(n454) );
XOR2X1 U202 ( .A(cx[8]), .B(cx[5]), .Y(n513) );
NOR2X1 U203 ( .A(n514), .B(n515), .Y(n460) );
NAND3X1 U204 ( .A(n500), .B(n473), .C(n508), .Y(n515) );
INVX1 U205 ( .A(n470), .Y(n508) );
XOR2X1 U206 ( .A(cx[4]), .B(n516), .Y(n470) );
XOR2X1 U207 ( .A(cx[7]), .B(cx[5]), .Y(n516) );
INVX1 U208 ( .A(n455), .Y(n473) );
XNOR2X1 U209 ( .A(n517), .B(cx[13]), .Y(n455) );
INVX1 U210 ( .A(n452), .Y(n500) );
XNOR2X1 U211 ( .A(n518), .B(n519), .Y(n452) );
XNOR2X1 U212 ( .A(cx[4]), .B(cx[9]), .Y(n518) );
NAND3X1 U213 ( .A(n453), .B(n457), .C(n490), .Y(n514) );
INVX1 U214 ( .A(n446), .Y(n490) );
XNOR2X1 U215 ( .A(n520), .B(n521), .Y(n446) );
XOR2X1 U216 ( .A(cx[17]), .B(n522), .Y(n521) );
XNOR2X1 U217 ( .A(cx[2]), .B(cx[5]), .Y(n520) );
XNOR2X1 U218 ( .A(n523), .B(n524), .Y(n457) );
XOR2X1 U219 ( .A(cx[5]), .B(cx[10]), .Y(n524) );
XNOR2X1 U220 ( .A(n525), .B(cx[15]), .Y(n453) );
INVX1 U221 ( .A(n494), .Y(n463) );
XOR2X1 U222 ( .A(n519), .B(cx[14]), .Y(n494) );
XNOR2X1 U223 ( .A(cx[0]), .B(n423), .Y(n519) );
NAND3X1 U224 ( .A(n475), .B(n456), .C(n526), .Y(n510) );
INVX1 U225 ( .A(n458), .Y(n526) );
NAND3X1 U226 ( .A(n476), .B(n493), .C(n479), .Y(n458) );
INVX1 U227 ( .A(n445), .Y(n479) );
XNOR2X1 U228 ( .A(n523), .B(cx[16]), .Y(n445) );
XNOR2X1 U229 ( .A(cx[3]), .B(n522), .Y(n523) );
XNOR2X1 U230 ( .A(n525), .B(cx[11]), .Y(n493) );
XNOR2X1 U231 ( .A(cx[2]), .B(cx[4]), .Y(n525) );
XNOR2X1 U232 ( .A(n527), .B(n512), .Y(n476) );
XNOR2X1 U233 ( .A(cx[2]), .B(n423), .Y(n512) );
INVX1 U234 ( .A(cx[3]), .Y(n423) );
XNOR2X1 U235 ( .A(cx[1]), .B(cx[18]), .Y(n527) );
INVX1 U236 ( .A(n482), .Y(n456) );
XOR2X1 U237 ( .A(n528), .B(n529), .Y(n482) );
XNOR2X1 U238 ( .A(cx[5]), .B(n436), .Y(n529) );
XNOR2X1 U239 ( .A(cx[0]), .B(cx[12]), .Y(n528) );
INVX1 U240 ( .A(n443), .Y(n475) );
XNOR2X1 U241 ( .A(n517), .B(cx[6]), .Y(n443) );
XOR2X1 U242 ( .A(n530), .B(n522), .Y(n517) );
XNOR2X1 U243 ( .A(n436), .B(cx[4]), .Y(n522) );
INVX1 U244 ( .A(cx[1]), .Y(n436) );
XNOR2X1 U245 ( .A(cx[0]), .B(cx[5]), .Y(n530) );
endmodule
|
/***********************************************************************
Capsense system controller
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
Core used to periodically sample capsense buttons.
This version includes the frequency dividers and the toggle logic.
To Do:
-
Author:
- Salvador E. Tropea, salvador en inti.gob.ar
----------------------------------------------------------------------
Copyright (c) 2016 Salvador E. Tropea <salvador en inti.gob.ar>
Copyright (c) 2016 Instituto Nacional de Tecnología Industrial
This file can be distributed under the terms of the GPL 2.0 license
or newer.
----------------------------------------------------------------------
Design unit: CapSense_Sys
File name: capsense_sys.v
Note: None
Limitations: None known
Errors: None known
Library: None
Dependencies: None
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: iCEcube2 2016.02
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
************************************************************************/
/*module CapSense_Sys #(
parameter DIRECT=1, // Direct status, else: toggle
parameter FREQUENCY=24, // Clock in MHz
parameter N=4 // How many buttons
) (
input clk_i, // System clock
input rst_i, // System reset
input [N-1:0] capsense_i, // Buttons inputs
output oe, // Buttons OE
output [N-1:0] buttons_o, // Last sample result
output [N-1:0] debug_o // Used to measure the button timing
);*/
//localparam N=4;
localparam integer MOD_SAMP=FREQUENCY/1.5;
localparam integer MOD_BITS=$clog2(MOD_SAMP);
// FSM states
localparam IDLE=0, SAMPLING=1, DO_SAMPLE=2;
// Some constants
localparam ALL_1={N{1'b1}};
reg [1:0] state=IDLE;
reg [N-1:0] btns_r;
// CapSense sampling rate
wire clkSamp;
reg [MOD_BITS-1:0] cntSamp=0;
// CapSese polling rate
wire clkPoll;
reg [16:0] cntPoll=0;
// Buttons
wire [N-1:0] cur_btns;
reg [N-1:0] prev_btn_r=0;
reg [N-1:0] cur_btn_r=0;
// 1.5 MHz capacitors sample
always @(posedge clk_i)
if (cntSamp==MOD_SAMP-1)
cntSamp=0;
else
cntSamp=cntSamp+1;
assign clkSamp=!cntSamp ? 1 : 0;
// aprox. 87 ms
always @(posedge clk_i)
if (clkSamp)
cntPoll=cntPoll+1;
assign clkPoll=!cntPoll ? 1 : 0;
// Keep the capacitors discharged while we are idle
assign oe=state==IDLE ? 1 : 0;
always @(posedge clk_i)
begin : do_fsm
if (1'b0) // rst_i
begin
state=IDLE;
btns_r=0;
end
else
begin
case (state)
IDLE:
if (clkPoll)
state=SAMPLING;
SAMPLING:
// Sample the capacitors at the clkSamp rate
// If any of the capacitors is charged stop waiting
if (clkSamp && capsense_i)
state=DO_SAMPLE;
default: // DO_SAMPLE
// We wait 1 more cycle to mask small differences between
// buttons. Pressed buttons have big differeneces.
if (clkSamp) // For debug: && capsense_i==ALL_1
begin
// The "pressed" buttons are the ones that stay charging
btns_r=~capsense_i;
state=IDLE;
end
endcase
end
end
assign cur_btns=btns_r;
integer i;
always @(posedge clk_i)
begin
for (i=0; i<4; i=i+1)
if (!prev_btn_r[i] && cur_btns[i]) // pressed?
cur_btn_r[i]=~cur_btn_r[i]; // toggle
prev_btn_r=cur_btns;
end
assign buttons_o=DIRECT ? cur_btns : cur_btn_r;
//endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_16_V
`define SKY130_FD_SC_LP__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_16_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cyclone2_pmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cyclone2_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
// ----------------------------------------------------------------------
// Filename: Filename: tx_multiplexer_64.v
// Version: Version: 1.0
// Verilog Standard: Verilog-2005
// Description: the TX Multiplexer services read and write requests from
// RIFFA channels in round robin order.
// Author: Dustin Richmond (@darichmond)
// ----------------------------------------------------------------------
`define FMT_TXENGUPR64_WR32 7'b10_00000
`define FMT_TXENGUPR64_RD32 7'b00_00000
`define FMT_TXENGUPR64_WR64 7'b11_00000
`define FMT_TXENGUPR64_RD64 7'b01_00000
`define S_TXENGUPR64_MAIN_IDLE 4'b0001
`define S_TXENGUPR64_MAIN_RD 4'b0010
`define S_TXENGUPR64_MAIN_WR 4'b0100
`define S_TXENGUPR64_MAIN_WAIT 4'b1000
`define S_TXENGUPR64_CAP_RD_WR 4'b0001
`define S_TXENGUPR64_CAP_WR_RD 4'b0010
`define S_TXENGUPR64_CAP_CAP 4'b0100
`define S_TXENGUPR64_CAP_REL 4'b1000
`include "trellis.vh"
`timescale 1ns/1ns
module tx_multiplexer_64
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY);
localparam C_DATA_DELAY = 6'd6; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rMainState=`S_TXENGUPR64_MAIN_IDLE, _rMainState=`S_TXENGUPR64_MAIN_IDLE;
reg rCountIsWr=0, _rCountIsWr=0;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountValid=0,_rCountValid=0;
reg rCountStart=0, _rCountStart=0;
reg rCountOdd32=0, _rCountOdd32=0;
reg [9:0] rCountLen=0, _rCountLen=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR64_CAP_RD_WR, _rCapState=`S_TXENGUPR64_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [((C_DATA_DELAY+1)*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR64_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = (rCapAddr[61:30] != 0);
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR64_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = (wRdAck<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_WR_RD);
end
`S_TXENGUPR64_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_RD_WR);
end
`S_TXENGUPR64_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR64_CAP_REL;
end
`S_TXENGUPR64_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & rMainState[0]) // S_TXENGUPR64_MAIN_IDLE
_rCapState = (`S_TXENGUPR64_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR64_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR64_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR64_MAIN_IDLE : _rMainState);
rCountIsWr <= #1 _rCountIsWr;
rCountLen <= #1 _rCountLen;
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCountOdd32 <= #1 _rCountOdd32;
rWrDataRen <= #1 _rWrDataRen;
rCountValid <= #1 RST_IN ? 0 : _rCountValid;
end
always @ (*) begin
_rMainState = rMainState;
_rCountIsWr = rCountIsWr;
_rCount = rCount;
_rCountLen = rCountLen;
_rCountDone = rCountDone;
_rCountStart = rCountStart;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCountOdd32 = rCountOdd32;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
_rCountValid = rCountValid;
case (rMainState)
`S_TXENGUPR64_MAIN_IDLE : begin
_rCountIsWr = rCapIsWr;
_rCountLen = rCapLen;
_rCount = rCapLen;
_rCountDone = (rCapLen <= 2'd2);
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCountOdd32 = (rCapLen[0] & ((rCapAddr[61:30] == 0)));
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR64_CAP_REL
_rCountStart = (TXR_META_READY & rCapState[3]);
_rCountValid = TXR_META_READY & rCapState[3];
if (TXR_META_READY & rCapState[3]) // S_TXENGUPR64_CAP_REL
_rMainState = (`S_TXENGUPR64_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR64_MAIN_WR;
end
`S_TXENGUPR64_MAIN_RD : begin
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
`S_TXENGUPR64_MAIN_WR : begin
_rCount = rCount - 2'd2;
_rCountDone = (rCount <= 3'd4);
if (rCountDone) begin
_rWrDataRen = 0;
_rCountValid = 0;
_rMainState = (rCountOdd32 ? `S_TXENGUPR64_MAIN_IDLE : `S_TXENGUPR64_MAIN_WAIT);
end
end
`S_TXENGUPR64_MAIN_WAIT : begin // Signals request FIFO ren
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
default : begin
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
rValid <= #1 _rValid;
rDone <= #1 _rDone;
rStart <= #1 _rStart;
end
always @ (*) begin
_rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCapIsWr};
_rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCapAddr};
_rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
_rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
_rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
_rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr}; // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
_rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
_rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
end
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCapAddr,2'b00};
assign TXR_META_LENGTH = rCapLen;
assign TXR_META_LDWBE = 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 22:59:38 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul_16_32_stub.v
// Design : mul_16_32
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[15:0],B[31:0],P[47:0]" */;
input CLK;
input [15:0]A;
input [31:0]B;
output [47:0]P;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_4_V
`define SKY130_FD_SC_LP__A2BB2O_4_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_SYMBOL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eac_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eac_e.v,v 1.1 2006/04/10 15:42:08 wig Exp $
// $Date: 2006/04/10 15:42:08 $
// $Log: inst_eac_e.v,v $
// Revision 1.1 2006/04/10 15:42:08 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eac_e
//
// No user `defines in this module
module inst_eac_e
//
// Generated module inst_eac
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eac_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// based on http://cmosedu.com/jbaker/students/gerardo/Documents/UARTonFPGA.pdf
module uart_transmitter
(
input wire clk,
input wire rst,
input wire [7:0] data,
output reg nextch,
output reg txd
);
parameter CLK = 50_000_000;
parameter BAUD = 9600;
localparam RATE = CLK/BAUD;
localparam INIT = 0;
localparam TXD = 1;
reg state, next;
reg [31:0] cnt;
reg [4:0] bitcnt;
reg [9:0] rshift;
reg shift, load, clear, getch, gotch;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
state <= INIT;
cnt <= 0;
bitcnt <= 0;
gotch <= 0;
end
else begin
if (nextch) begin
nextch <= 0;
gotch <= 1;
end
else if (getch && !gotch)
nextch <= 1;
cnt <= cnt + 1;
if (cnt >= RATE) begin
state <= next;
cnt <= 0;
if (load)
rshift <= {1'b1, data[7:0], 1'b0};
if (clear) begin
bitcnt <= 0;
gotch <= 0;
end
if (shift) begin
rshift <= rshift >> 1;
bitcnt <= bitcnt + 1;
end
end
end
end
always @ (state or bitcnt or rshift) begin
load <= 0;
shift <= 0;
clear <= 0;
getch <= 0;
txd <= 1;
case (state)
INIT: begin
next <= TXD;
load <= 1;
shift <= 0;
clear <= 0;
end
TXD: begin
if (bitcnt >= 9) begin
next <= INIT;
clear <= 1;
getch <= 1;
end
else begin
next <= TXD;
shift <= 1;
txd <= rshift[0];
end
end
endcase
end
endmodule
|
//Listing 9.1
module ps2_rx
(
input wire clk, reset,
input wire ps2d, ps2c, rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule |
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
module robohand(reset, advance, ball_y, paddle_y);
// paddle Y location (0-480)
parameter PADDLESIZE = 10'd0;
parameter SCREENHEIGHT = 10'd0;
input reset;
input advance;
input [9:0] ball_y;
output reg[9:0] paddle_y;
// paddle move direction 0 = +, 1 = -
reg paddleDir;
reg [9:0] ptop;
reg [9:0] pbot;
reg [2:0] increment;
always @(negedge advance or posedge reset) begin
if (reset) begin
paddle_y <= SCREENHEIGHT/2;
end
else begin
if (ball_y < ptop || ball_y > pbot)
paddle_y <= paddlelimiter(paddleDir == 1'b0 ? paddle_y + 1'b1 : paddle_y - 1'b1);
end
end
always @(posedge advance) begin
ptop <= paddle_y - PADDLESIZE/2;
pbot <= paddle_y + PADDLESIZE/2;
paddleDir <= ball_y < paddle_y;
end
function [9:0] paddlelimiter;
input [9:0] py;
begin
if (py < PADDLESIZE/2)
paddlelimiter = PADDLESIZE/2;
else
if (py > SCREENHEIGHT-PADDLESIZE/2)
paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
else
paddlelimiter = py;
end
endfunction
endmodule
// $Id: robohand.v,v 1.4 2007/08/27 22:14:50 svo Exp $
|
module LCD_TEST ( // Host Side
iCLK,iRST_N,
// LCD Side
LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
// Host Side
input iCLK,iRST_N;
// LCD Side
output [7:0] LCD_DATA;
output LCD_RW,LCD_EN,LCD_RS;
// Internal Wires/Registers
reg [5:0] LUT_INDEX;
reg [8:0] LUT_DATA;
reg [5:0] mLCD_ST;
reg [17:0] mDLY;
reg mLCD_Start;
reg [7:0] mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;
parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE1+32+1;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA[7:0];
mLCD_RS <= LUT_DATA[8];
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY+1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
LUT_INDEX <= LUT_INDEX+1;
mLCD_ST <= 0;
end
endcase
end
end
end
always
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h120; // Welcome to the
LCD_LINE1+1: LUT_DATA <= 9'h157;
LCD_LINE1+2: LUT_DATA <= 9'h165;
LCD_LINE1+3: LUT_DATA <= 9'h16C;
LCD_LINE1+4: LUT_DATA <= 9'h163;
LCD_LINE1+5: LUT_DATA <= 9'h16F;
LCD_LINE1+6: LUT_DATA <= 9'h16D;
LCD_LINE1+7: LUT_DATA <= 9'h165;
LCD_LINE1+8: LUT_DATA <= 9'h120;
LCD_LINE1+9: LUT_DATA <= 9'h174;
LCD_LINE1+10: LUT_DATA <= 9'h16F;
LCD_LINE1+11: LUT_DATA <= 9'h120;
LCD_LINE1+12: LUT_DATA <= 9'h174;
LCD_LINE1+13: LUT_DATA <= 9'h168;
LCD_LINE1+14: LUT_DATA <= 9'h165;
LCD_LINE1+15: LUT_DATA <= 9'h120;
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
LCD_LINE2+0: LUT_DATA <= 9'h120; // Altera DE2-70
LCD_LINE2+1: LUT_DATA <= 9'h141;
LCD_LINE2+2: LUT_DATA <= 9'h16C;
LCD_LINE2+3: LUT_DATA <= 9'h174;
LCD_LINE2+4: LUT_DATA <= 9'h165;
LCD_LINE2+5: LUT_DATA <= 9'h172;
LCD_LINE2+6: LUT_DATA <= 9'h161;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h144;
LCD_LINE2+9: LUT_DATA <= 9'h145;
LCD_LINE2+10: LUT_DATA <= 9'h132;
LCD_LINE2+11: LUT_DATA <= 9'h1B0;
LCD_LINE2+12: LUT_DATA <= 9'h137;
LCD_LINE2+13: LUT_DATA <= 9'h130;
LCD_LINE2+14: LUT_DATA <= 9'h120;
LCD_LINE2+15: LUT_DATA <= 9'h120;
default: LUT_DATA <= 9'h120;
endcase
end
LCD_Controller u0 ( // Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS) );
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_BLACKBOX_V
`define SKY130_FD_SC_LS__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
`timescale 1ns/100ps
module ad_iqcor (
// data interface
clk,
valid,
data_i,
data_q,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled
parameter IQSEL = 0;
// data interface
input clk;
input valid;
input [15:0] data_i;
input [15:0] data_q;
output valid_out;
output [15:0] data_out;
// control interface
input iqcor_enable;
input [15:0] iqcor_coeff_1;
input [15:0] iqcor_coeff_2;
// internal registers
reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [33:0] p1_data_p_i_s;
wire p1_valid_s;
wire [15:0] p1_data_i_s;
wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s;
// scaling functions - i
ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
.clk (clk),
.data_a ({data_i[15], data_i}),
.data_b ({iqcor_coeff_1[15], iqcor_coeff_1}),
.data_p (p1_data_p_i_s),
.ddata_in ({valid, data_i}),
.ddata_out ({p1_valid_s, p1_data_i_s}));
// scaling functions - q
ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
.clk (clk),
.data_a ({data_q[15], data_q}),
.data_b ({iqcor_coeff_2[15], iqcor_coeff_2}),
.data_p (p1_data_p_q_s),
.ddata_in (data_q),
.ddata_out (p1_data_q_s));
// sum
always @(posedge clk) begin
p1_valid <= p1_valid_s;
p1_data_i <= p1_data_i_s;
p1_data_q <= p1_data_q_s;
p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
end
// output registers
always @(posedge clk) begin
valid_out <= p1_valid;
if (iqcor_enable == 1'b1) begin
data_out <= p1_data_p[29:14];
end else if (IQSEL == 1) begin
data_out <= p1_data_q;
end else begin
data_out <= p1_data_i;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module crc_ccitt
#(parameter INIT = 16'hffff)
(input clk, input rst, input [7:0] d, input dv, output [15:0] crc);
wire [15:0] next_crc;
wire [15:0] crc_d = (rst ? INIT : next_crc);
r #(16) crc_r(.c(clk), .rst(1'b0), .en(dv | rst), .d(crc_d), .q(crc));
assign next_crc[0] = crc[8] ^ crc[12] ^ d[0] ^ d[4];
assign next_crc[1] = crc[9] ^ crc[13] ^ d[1] ^ d[5];
assign next_crc[2] = crc[10] ^ crc[14] ^ d[2] ^ d[6];
assign next_crc[3] = crc[11] ^ crc[15] ^ d[3] ^ d[7];
assign next_crc[4] = crc[12] ^ d[4];
assign next_crc[5] = crc[8] ^ crc[12] ^ crc[13] ^ d[0] ^ d[4] ^ d[5];
assign next_crc[6] = crc[9] ^ crc[13] ^ crc[14] ^ d[1] ^ d[5] ^ d[6];
assign next_crc[7] = crc[10] ^ crc[14] ^ crc[15] ^ d[2] ^ d[6] ^ d[7];
assign next_crc[8] = crc[0] ^ crc[11] ^ crc[15] ^ d[3] ^ d[7];
assign next_crc[9] = crc[1] ^ crc[12] ^ d[4];
assign next_crc[10] = crc[2] ^ crc[13] ^ d[5];
assign next_crc[11] = crc[3] ^ crc[14] ^ d[6];
assign next_crc[12] = crc[4] ^ crc[8] ^ crc[12] ^ crc[15] ^ d[0] ^ d[4] ^ d[7];
assign next_crc[13] = crc[5] ^ crc[9] ^ crc[13] ^ d[1] ^ d[5];
assign next_crc[14] = crc[6] ^ crc[10] ^ crc[14] ^ d[2] ^ d[6];
assign next_crc[15] = crc[7] ^ crc[11] ^ crc[15] ^ d[3] ^ d[7];
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
(* FILL IN HERE *) admit.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb2: (nandb false false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb3: (nandb false true) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb4: (nandb true true) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
(* FILL IN HERE *) admit.
Example test_andb31: (andb3 true true true) = true.
(* FILL IN HERE *) Admitted.
Example test_andb32: (andb3 false true true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb33: (andb3 true false true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb34: (andb3 true true false) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
(* FILL IN HERE *) admit.
Example test_factorial1: (factorial 3) = 6.
(* FILL IN HERE *) Admitted.
Example test_factorial2: (factorial 5) = (mult 10 12).
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool := ble_nat (S n) m.
Example test_blt_nat1: (blt_nat 2 2) = false.
(* FILL IN HERE *) Admitted.
Example test_blt_nat2: (blt_nat 2 4) = true.
(* FILL IN HERE *) Admitted.
Example test_blt_nat3: (blt_nat 4 2) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [ | n' ].
reflexivity.
simpl. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f id b.
rewrite -> id.
rewrite -> id.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f.
intros nid.
intros b.
rewrite -> nid.
rewrite -> nid.
rewrite -> negb_involutive.
reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Lemma andb_true_id :
forall b : bool,
andb true b = b.
Proof. reflexivity. Qed.
Lemma orb_false_id : forall b : bool, orb false b = b.
Proof. reflexivity. Qed.
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
rewrite -> andb_true_id.
simpl. intros H. rewrite -> H. reflexivity.
simpl. intros H. rewrite -> H. reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive binary : Type :=
| OB : binary
| T : binary -> binary
| ST : binary -> binary.
Fixpoint incr (b : binary) : binary :=
match b with
| OB => ST OB
| T n => ST n
| ST n => T (incr n)
end.
Fixpoint to_nat (b : binary) : nat :=
match b with
| OB => 0
| T n => 2 * to_nat n
| ST n => 1 + 2 * to_nat n
end.
Fixpoint from_nat (b : nat) : binary :=
match b with
| 0 => OB
| S n => incr (from_nat n)
end.
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_iddr16 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT_Q0 = 1'b0,
parameter INIT_Q1 = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [15:0] Q0,
output [15:0] Q1,
input C0,
input C1,
input CE,
input [15:0] D,
input R,
input S
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr0 (
.Q0(Q0[0]),
.Q1(Q1[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[0]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr1 (
.Q0(Q0[1]),
.Q1(Q1[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[1]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr2 (
.Q0(Q0[2]),
.Q1(Q1[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[2]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr3 (
.Q0(Q0[3]),
.Q1(Q1[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[3]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr4 (
.Q0(Q0[4]),
.Q1(Q1[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[4]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr5 (
.Q0(Q0[5]),
.Q1(Q1[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[5]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr6 (
.Q0(Q0[6]),
.Q1(Q1[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[6]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr7 (
.Q0(Q0[7]),
.Q1(Q1[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[7]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr8 (
.Q0(Q0[8]),
.Q1(Q1[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[8]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr9 (
.Q0(Q0[9]),
.Q1(Q1[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[9]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr10 (
.Q0(Q0[10]),
.Q1(Q1[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[10]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr11 (
.Q0(Q0[11]),
.Q1(Q1[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[11]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr12 (
.Q0(Q0[12]),
.Q1(Q1[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[12]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr13 (
.Q0(Q0[13]),
.Q1(Q1[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[13]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr14 (
.Q0(Q0[14]),
.Q1(Q1[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[14]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr15 (
.Q0(Q0[15]),
.Q1(Q1[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[15]),
.R(R),
.S(S)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_1_V
`define SKY130_FD_SC_HS__A41O_1_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41o_1 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41o_1 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_SYMBOL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A221OI_PP_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a221oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_PP_SYMBOL_V
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
// BlockRAM
ram
#(
.block_count(128) // 1MB
)
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
// CPU
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE("ENABLED"),
.ENABLE_DCACHE("ENABLED"),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
.uart_tx_o(),
.uart_rx_i(1'b0),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRT Controller Registers
// File : crtregist.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the CRT Display controller Host accessible registers
// CRT Registers start at 0x0020 and end at 0x0063
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module crtregist
(
input hclock,
input hnreset,
input hwr,
input hncs,
input [3:0] hnben,
input [31:0] hdat_in,
input [7:2] haddr, // bit[2] used only in readback path
input ad_strst, /* synchronized reset for
* "display address updated" bit */
input vblnkst, // synchronized vertical blank status
input [11:0] lcounter_stat, // from line counter in TIMER (synch)
input dlp_wradd, // DLP write enable to display register
input [20:0] dlp_add, // display address from DLP
output reg [31:0] hdat_out,
output reg [7:0] vicount,
output reg [11:0] hicount,
output reg [13:0] hactive_o,
output reg [13:0] hblank_o,
output reg [13:0] hfporch_o,
output reg [13:0] hswidth_o,
output reg [11:0] vactive,
output reg [11:0] vblank,
output reg [11:0] vfporch,
output reg [11:0] vswidth,
output reg [3:0] dzoom,
output reg [15:4] db_pitch,
output reg [24:4] displ_start,
output reg [24:4] sec_start,
output reg poshs,
output reg posvs,
output reg compsync,
output reg crtintl,
output reg videnable,
output reg refresh_enable,
output reg ovignr,
output reg ovignr16l,
output reg [1:0] syncsenable,
output reg fdp_on, //1 - enables flat display mode
output reg addr_stat, // used as enble to synchr. with frame
output reg[9:0] pinl,
output reg ss_mode
);
parameter FRAME_COUNTorLINE_COUNT = 5'b0010_0,
DISP_STARTorDISP_PITCH = 5'b0010_1,
HACTIVEorHBLANK = 5'b0011_0,
HFPORCHorHSYNC = 5'b0011_1,
VACTIVEorVBLANK = 5'b0100_0,
VFPORCHorVSYNC = 5'b0100_1,
LCOUNTSorZOOM = 5'b0101_0,
SYNC_SELorMEM_CONFIG = 5'b0101_1 ,
SEC_STARTorRESERVED = 5'b0110_0 ;
reg [13:0] hactive, hblank, hfporch, hswidth;
reg [13:0] hactive_s, hblank_s, hfporch_s, hswidth_s;
reg [3:0] hshifter;
always @* hactive_o = {hactive_s[12:0], 1'b0};
always @* hblank_o = {hblank_s[12:0], 1'b0};
always @* hfporch_o = {hfporch_s[12:0], 1'b0};
always @* hswidth_o = {hswidth_s[12:0], 1'b0};
always @*
pinl[9:0] = (hactive_s[0]) ? (hactive_s[10:1]+1'b1) : hactive_s[10:1];
// shift /divide horizontal sync parameters
always @*
case (hshifter) // synopsys parallel_case full_case
4'b0,
4'b10,
4'b100,
4'b101,
4'b110,
4'b1000,
4'b1001,
4'b1010,
4'b1011,
4'b1100,
4'b1101,
4'b1110: begin
hactive_s[13:0]=hactive[13:0];
hblank_s[13:0]=hblank[13:0];
hfporch_s[13:0]=hfporch[13:0];
hswidth_s[13:0]=hswidth[13:0];
end // case: 4'b0,...
4'b1: begin
hactive_s[13:0]={1'b0,hactive[13:1]};
hblank_s[13:0]= {1'b0,hblank[13:1]};
hfporch_s[13:0]={1'b0,hfporch[13:1]};
hswidth_s[13:0]={1'b0,hswidth[13:1]};
end // case: 4'b1
4'b11: begin
hactive_s[13:0]={2'b0,hactive[13:2]};
hblank_s[13:0] ={2'b0,hblank[13:2]};
hfporch_s[13:0]={2'b0,hfporch[13:2]};
hswidth_s[13:0]={2'b0,hswidth[13:2]};
end // case: 4'b11
4'b111: begin
hactive_s[13:0]={3'b0,hactive[13:3]};
hblank_s[13:0]= {3'b0,hblank[13:3]};
hfporch_s[13:0]={3'b0,hfporch[13:3]};
hswidth_s[13:0]={3'b0,hswidth[13:3]};
end // case: 4'b111
4'b1111: begin
hactive_s[13:0]={4'b0,hactive[13:4]};
hblank_s[13:0]= {4'b0,hblank[13:4]};
hfporch_s[13:0]={4'b0,hfporch[13:4]};
hswidth_s[13:0]={4'b0,hswidth[13:4]};
end // case: 4'b1111
endcase
always @ (posedge hclock or negedge hnreset)
if(!hnreset) begin
syncsenable <= 2'b0;
videnable <= 1'b0;
refresh_enable <= 1'b0;
ovignr <= 1'b0;
ovignr16l <= 1'b0;
fdp_on <= 1'b1; // Now enable Flat panel on reset
ss_mode <= 1'b0;
end else if (hwr && !hncs) begin
case (haddr[7:2]) //
{SYNC_SELorMEM_CONFIG, 1'b0}: begin
if (!hnben[0]) videnable <= hdat_in[6];
if (!hnben[0]) syncsenable <= hdat_in[5:4];
if (!hnben[0]) {crtintl, compsync, posvs, poshs} <= hdat_in[3:0];
if (!hnben[1]) fdp_on <= hdat_in[8];
if (!hnben[3]) ss_mode <= hdat_in[30];
end
{SYNC_SELorMEM_CONFIG, 1'b1}: begin
if (!hnben[1]) refresh_enable <= hdat_in[8];
if (!hnben[1]) ovignr16l <= hdat_in[9];
if (!hnben[1]) ovignr <= hdat_in[10];
end
{FRAME_COUNTorLINE_COUNT, 1'b0}: begin
if (!hnben[0]) vicount[7:0] <= hdat_in[7:0];
end
{FRAME_COUNTorLINE_COUNT, 1'b1}: begin
if (!hnben[0]) hicount[7:0] <= {hdat_in[7:1], 1'b0};
if (!hnben[1]) hicount[11:8] <= hdat_in[11:8];
end
{DISP_STARTorDISP_PITCH, 1'b1}: begin
if (!hnben[0]) db_pitch[7:4] <= hdat_in[7:4];
if (!hnben[1]) db_pitch[15:8] <= hdat_in[15:8];
end
{HACTIVEorHBLANK, 1'b0}: begin
if (!hnben[0]) hactive[7:0] <= hdat_in[7:0];
if (!hnben[1]) hactive[13:8] <= hdat_in[13:8];
end
{HACTIVEorHBLANK, 1'b1}: begin
if (!hnben[0]) hblank[7:0] <= hdat_in[7:0];
if (!hnben[1]) hblank[13:8] <= hdat_in[13:8];
end
{HFPORCHorHSYNC, 1'b0}: begin
if (!hnben[0]) hfporch[7:0] <= hdat_in[7:0];
if (!hnben[1]) hfporch[13:8] <= hdat_in[13:8];
end
{HFPORCHorHSYNC, 1'b1}: begin
if (!hnben[0]) hswidth[7:0] <= hdat_in[7:0];
if (!hnben[1]) hswidth[13:8] <= hdat_in[13:8];
end
{VACTIVEorVBLANK, 1'b0}: begin
if (!hnben[0]) vactive[7:0] <= hdat_in[7:0];
if (!hnben[1]) vactive[11:8] <= hdat_in[11:8];
end
{VACTIVEorVBLANK, 1'b1}: begin
if (!hnben[0]) vblank[7:0] <= hdat_in[7:0];
if (!hnben[1]) vblank[11:8] <= hdat_in[11:8];
end
{VFPORCHorVSYNC, 1'b0}: begin
if (!hnben[0]) vfporch[7:0] <= hdat_in[7:0];
if (!hnben[1]) vfporch[11:8] <= hdat_in[11:8];
end
{VFPORCHorVSYNC, 1'b1}: begin
if (!hnben[0]) vswidth[7:0] <= hdat_in[7:0];
if (!hnben[1]) vswidth[11:8] <= hdat_in[11:8];
end
{LCOUNTSorZOOM, 1'b1}: begin
if (!hnben[0]) dzoom[3:0] <= hdat_in[3:0];
if (!hnben[2]) hshifter[3:0] <= hdat_in[19:16];
end
{SEC_STARTorRESERVED, 1'b0}: begin
if (!hnben[0]) sec_start[7:4] <= hdat_in[7:4];
if (!hnben[1]) sec_start[15:8] <= hdat_in[15:8];
if (!hnben[2]) sec_start[23:16] <= hdat_in[23:16];
if (!hnben[3]) sec_start[24] <= hdat_in[24];
end
endcase // case (haddr)
end // if (hwr && !hncs)
// displ_start register can be modyfied by host and DLP, DLP no byte writes
always @ (posedge hclock) begin
// host writes
if( hwr && !hncs && (haddr[7:2] == {DISP_STARTorDISP_PITCH, 1'b0}) ) begin
if (!hnben[0]) displ_start[7:4] <= hdat_in[7:4];
if (!hnben[1]) displ_start[15:8] <= hdat_in[15:8];
if (!hnben[2]) displ_start[23:16] <= hdat_in[23:16];
if (!hnben[3]) displ_start[24] <= hdat_in[24];
end else if (dlp_wradd) //DLP writes
displ_start[24:4] <= dlp_add;
end
// ad_strst is a one hclk active high signal
// generated after the display start address gets synchronized
// (once per frame)
// This is now a synchronous signal for synchronous clearing.
always @(posedge hclock or negedge hnreset) begin
if (!hnreset) addr_stat <= 1'b0;
else if (ad_strst) addr_stat <= 1'b0;
else if ((hwr && !hncs && !hnben[3]
&& (haddr[7:2] == {DISP_STARTorDISP_PITCH, 1'b0})
) || dlp_wradd)
addr_stat <= 1'b1;
end
/*********** output mux **************************************************/
// haddr[2] in this case statement got added for layout improvements
// (64->32 bus)
// Only to avoid redefinitions in case values bit[2] is treated seperately
// even if it looks strange
always @*
case (haddr[7:2]) //synopsys parallel_case
{FRAME_COUNTorLINE_COUNT, 1'b0}: hdat_out[31:0] = {24'b0, vicount[7:0]};
{FRAME_COUNTorLINE_COUNT, 1'b1}: hdat_out[31:0] = {20'b0, hicount[11:0]};
{DISP_STARTorDISP_PITCH, 1'b0}: hdat_out[31:0] = {addr_stat, 1'b0,
vblnkst, 4'b0,
displ_start[24:4],
4'b0};
{DISP_STARTorDISP_PITCH, 1'b1}: hdat_out[31:0] = {16'b0, db_pitch[15:4],
4'b0};
{HACTIVEorHBLANK, 1'b0}: hdat_out[31:0] = {18'b0, hactive[13:0]};
{HACTIVEorHBLANK, 1'b1}: hdat_out[31:0] = {18'b0, hblank[13:0]};
{HFPORCHorHSYNC, 1'b0}: hdat_out[31:0] = {18'b0, hfporch[13:0]};
{HFPORCHorHSYNC, 1'b1}: hdat_out[31:0] = {18'b0, hswidth[13:0]};
{VACTIVEorVBLANK, 1'b0}: hdat_out[31:0] = {20'b0, vactive[11:0]};
{VACTIVEorVBLANK, 1'b1}: hdat_out[31:0] = {20'b0, vblank[11:0]};
{VFPORCHorVSYNC, 1'b0}: hdat_out[31:0] = {20'b0, vfporch[11:0]};
{VFPORCHorVSYNC, 1'b1}: hdat_out[31:0] = {20'b0, vswidth[11:0]};
{LCOUNTSorZOOM, 1'b0}: hdat_out[31:0] = {20'b0,
lcounter_stat[11:0]};
{LCOUNTSorZOOM, 1'b1}: hdat_out[31:0] = {12'b0, hshifter[3:0],
12'b0, dzoom[3:0]};
{SYNC_SELorMEM_CONFIG, 1'b0}: hdat_out[31:0] = {1'b0, ss_mode,
1'b0, 13'b0,
7'b0, fdp_on,
1'b0, videnable,
syncsenable[1:0],
crtintl, compsync,
posvs, poshs };
{SYNC_SELorMEM_CONFIG, 1'b1}: hdat_out[31:0] = {8'b0, 8'b0, 5'b0,
ovignr, ovignr16l,
refresh_enable, 8'b0};
{SEC_STARTorRESERVED, 1'b0}: hdat_out[31:0] = {7'b0, sec_start[24:4],
4'b0};
{SEC_STARTorRESERVED, 1'b1}: hdat_out[31:0] = 32'b0;
default: hdat_out[31:0]= 32'b0; // why not?
endcase
endmodule
|
//b12015 Rohit Patiyal
`include "ALU/Logic/AND/AND_32bit.v"
`include "ALU/Logic/OR/OR_32bit.v"
`include "ALU/Logic/XOR/XOR_32bit.v" //`
`include "ALU/Logic/ASHIFTER/ASHIFTER_32bit.v"
`include "ALU/Logic/LSHIFTER/LSHIFTER_32bit.v"
module Logic(output [31:0] LogicAnswer, input [31:0] A,input [31:0] B, input [2:0] OpCode);
wire [31:0] ANDAns;
wire [31:0] ORAns;
wire [31:0] XORAns;
wire [31:0] LeftLSHIFTERAns;
wire [31:0] RightLSHIFTERAns;
wire [31:0] LeftASHIFTERAns;
wire [31:0] RightASHIFTERAns;
genvar i;
AND_32bit l1(ANDAns, A, B);
OR_32bit l2(ORAns, A, B);
XOR_32bit l3(XORAns, A, B);
LSHIFTER_32bit l4(LeftLSHIFTERAns, A, 1);
LSHIFTER_32bit l5(RightLSHIFTERAns, A, 0);
ASHIFTER_32bit l6(LeftASHIFTERAns, A, 1);
ASHIFTER_32bit l7(RightASHIFTERAns, A, 0);
generate for(i=0; i<32; i=i+1) begin: multiple2to1muxs
mux8to1 Mux1(LogicAnswer[i], ANDAns[i], ORAns[i], XORAns[i], LeftLSHIFTERAns[i], RightLSHIFTERAns[i], LeftASHIFTERAns[i], RightASHIFTERAns[i], 32'b0, OpCode); //'
end endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_1_V
`define SKY130_FD_SC_HDLL__MUX2I_1_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_1_V
`define SKY130_FD_SC_LP__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_1_V
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.05.08:40:39
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_ORI_BURST_SIZE_H (100),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (120),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_TRANS_LOCK (106),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_ORI_BURST_SIZE_H (136),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** This Verilog HDL file is used for simulation and synthesis in chained DMA design example
//* This file provides the top level wrapper file of the core and example applications
//*/
module pcie_hip_s4gx_gen2_x4_128_example_chaining_pipen1b (
// inputs:
free_100MHz,
local_rstn,
pcie_rstn,
pclk_in,
phystatus_ext,
pipe_mode,
pld_clk,
refclk,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
rxdata0_ext,
rxdata1_ext,
rxdata2_ext,
rxdata3_ext,
rxdatak0_ext,
rxdatak1_ext,
rxdatak2_ext,
rxdatak3_ext,
rxelecidle0_ext,
rxelecidle1_ext,
rxelecidle2_ext,
rxelecidle3_ext,
rxstatus0_ext,
rxstatus1_ext,
rxstatus2_ext,
rxstatus3_ext,
rxvalid0_ext,
rxvalid1_ext,
rxvalid2_ext,
rxvalid3_ext,
test_in,
// outputs:
clk250_out,
clk500_out,
core_clk_out,
gen2_speed,
lane_width_code,
pcie_reconfig_busy,
phy_sel_code,
powerdown_ext,
rate_ext,
rc_pll_locked,
ref_clk_sel_code,
rxpolarity0_ext,
rxpolarity1_ext,
rxpolarity2_ext,
rxpolarity3_ext,
test_out_icm,
tx_out0,
tx_out1,
tx_out2,
tx_out3,
txcompl0_ext,
txcompl1_ext,
txcompl2_ext,
txcompl3_ext,
txdata0_ext,
txdata1_ext,
txdata2_ext,
txdata3_ext,
txdatak0_ext,
txdatak1_ext,
txdatak2_ext,
txdatak3_ext,
txdetectrx_ext,
txelecidle0_ext,
txelecidle1_ext,
txelecidle2_ext,
txelecidle3_ext
)
;
output clk250_out;
output clk500_out;
output core_clk_out;
output gen2_speed;
output [ 3: 0] lane_width_code;
output pcie_reconfig_busy;
output [ 3: 0] phy_sel_code;
output [ 1: 0] powerdown_ext;
output rate_ext;
output rc_pll_locked;
output [ 3: 0] ref_clk_sel_code;
output rxpolarity0_ext;
output rxpolarity1_ext;
output rxpolarity2_ext;
output rxpolarity3_ext;
output [ 8: 0] test_out_icm;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
output txcompl0_ext;
output txcompl1_ext;
output txcompl2_ext;
output txcompl3_ext;
output [ 7: 0] txdata0_ext;
output [ 7: 0] txdata1_ext;
output [ 7: 0] txdata2_ext;
output [ 7: 0] txdata3_ext;
output txdatak0_ext;
output txdatak1_ext;
output txdatak2_ext;
output txdatak3_ext;
output txdetectrx_ext;
output txelecidle0_ext;
output txelecidle1_ext;
output txelecidle2_ext;
output txelecidle3_ext;
input free_100MHz;
input local_rstn;
input pcie_rstn;
input pclk_in;
input phystatus_ext;
input pipe_mode;
input pld_clk;
input refclk;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input [ 7: 0] rxdata0_ext;
input [ 7: 0] rxdata1_ext;
input [ 7: 0] rxdata2_ext;
input [ 7: 0] rxdata3_ext;
input rxdatak0_ext;
input rxdatak1_ext;
input rxdatak2_ext;
input rxdatak3_ext;
input rxelecidle0_ext;
input rxelecidle1_ext;
input rxelecidle2_ext;
input rxelecidle3_ext;
input [ 2: 0] rxstatus0_ext;
input [ 2: 0] rxstatus1_ext;
input [ 2: 0] rxstatus2_ext;
input [ 2: 0] rxstatus3_ext;
input rxvalid0_ext;
input rxvalid1_ext;
input rxvalid2_ext;
input rxvalid3_ext;
input [ 39: 0] test_in;
wire app_int_ack_icm;
wire app_int_sts_icm;
wire app_msi_ack;
wire [ 4: 0] app_msi_num;
wire app_msi_req;
wire [ 2: 0] app_msi_tc;
wire [ 12: 0] cfg_busdev_icm;
wire [ 31: 0] cfg_devcsr_icm;
wire [ 19: 0] cfg_io_bas;
wire [ 31: 0] cfg_linkcsr_icm;
wire [ 15: 0] cfg_msicsr;
wire [ 11: 0] cfg_np_bas;
wire [ 43: 0] cfg_pr_bas;
wire [ 31: 0] cfg_prmcsr_icm;
wire clk250_out;
wire clk500_out;
wire core_clk_out;
wire [ 6: 0] cpl_err_icm;
wire [ 6: 0] cpl_err_in;
wire cpl_pending_icm;
wire [ 4: 0] dl_ltssm;
wire [127: 0] err_desc;
wire fixedclk_serdes;
wire gen2_speed;
wire [ 23: 0] gnd_cfg_tcvcmap_icm;
wire gnd_msi_stream_ready0;
wire [ 9: 0] gnd_pm_data;
wire gnd_tx_stream_mask0;
wire [ 19: 0] ko_cpl_spc_vc0;
wire [ 3: 0] lane_act;
wire [ 3: 0] lane_width_code;
wire lmi_ack;
wire [ 11: 0] lmi_addr;
wire [ 31: 0] lmi_din;
wire [ 31: 0] lmi_dout;
wire lmi_rden;
wire lmi_wren;
wire [ 4: 0] open_aer_msi_num;
wire [ 23: 0] open_cfg_tcvcmap;
wire open_cplerr_lmi_busy;
wire [ 7: 0] open_msi_stream_data0;
wire open_msi_stream_valid0;
wire [ 9: 0] open_pm_data;
wire open_rx_st_err0;
wire otb0;
wire otb1;
wire pcie_reconfig_busy;
wire [ 4: 0] pex_msi_num_icm;
wire [ 3: 0] phy_sel_code;
wire pme_to_sr;
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire reconfig_clk;
wire reconfig_clk_locked;
wire [ 3: 0] ref_clk_sel_code;
wire rx_mask0;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [127: 0] rx_st_data0;
wire rx_st_empty0;
wire rx_st_eop0;
wire rx_st_sop0;
wire [ 81: 0] rx_stream_data0;
wire [ 81: 0] rx_stream_data0_1;
wire rx_stream_ready0;
wire rx_stream_valid0;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire srstn;
wire [ 8: 0] test_out_icm;
wire [ 8: 0] test_out_int;
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire tx_fifo_empty0;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire [127: 0] tx_st_data0;
wire tx_st_empty0;
wire tx_st_eop0;
wire tx_st_err0;
wire tx_st_sop0;
wire [ 35: 0] tx_stream_cred0;
wire [ 74: 0] tx_stream_data0;
wire [ 74: 0] tx_stream_data0_1;
wire tx_stream_ready0;
wire tx_stream_valid0;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
assign ref_clk_sel_code = 0;
assign lane_width_code = 2;
assign phy_sel_code = 6;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign gnd_pm_data = 0;
assign ko_cpl_spc_vc0[7 : 0] = 8'd112;
assign ko_cpl_spc_vc0[19 : 8] = 12'd448;
assign gnd_cfg_tcvcmap_icm = 0;
assign tx_st_sop0 = tx_stream_data0[73];
assign tx_st_err0 = tx_stream_data0[74];
assign rx_stream_data0 = {rx_st_be0[7 : 0], rx_st_sop0, rx_st_empty0, rx_st_bardec0, rx_st_data0[63 : 0]};
assign rx_stream_data0_1 = {rx_st_be0[15 : 8], rx_st_sop0, rx_st_eop0, rx_st_bardec0, rx_st_data0[127 : 64]};
assign tx_st_data0 = {tx_stream_data0_1[63 : 0],tx_stream_data0[63 : 0]};
assign tx_st_eop0 = tx_stream_data0_1[72];
assign tx_st_empty0 = tx_stream_data0[72];
assign test_out_icm = test_out_int;
assign pcie_reconfig_busy = 1'b1;
assign gen2_speed = cfg_linkcsr_icm[17];
assign gnd_tx_stream_mask0 = 1'b0;
assign gnd_msi_stream_ready0 = 1'b0;
pcie_hip_s4gx_gen2_x4_128_plus ep_plus
(
.app_int_ack (app_int_ack_icm),
.app_int_sts (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.clk250_out (clk250_out),
.clk500_out (clk500_out),
.core_clk_out (core_clk_out),
.cpl_err (cpl_err_icm),
.cpl_pending (cpl_pending_icm),
.fixedclk_serdes (fixedclk_serdes),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_dout (lmi_dout),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.local_rstn (local_rstn),
.ltssm (dl_ltssm),
.pcie_rstn (pcie_rstn),
.pclk_in (pclk_in),
.pex_msi_num (pex_msi_num_icm),
.phystatus_ext (phystatus_ext),
.pipe_mode (pipe_mode),
.pld_clk (pld_clk),
.pm_auxpwr (1'b0),
.pm_data (gnd_pm_data),
.pm_event (1'b0),
.pme_to_cr (pme_to_sr),
.pme_to_sr (pme_to_sr),
.powerdown_ext (powerdown_ext),
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.reconfig_clk (reconfig_clk),
.reconfig_clk_locked (reconfig_clk_locked),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0),
.rx_st_data0 (rx_st_data0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (open_rx_st_err0),
.rx_st_mask0 (rx_mask0),
.rx_st_ready0 (rx_stream_ready0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_stream_valid0),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.srstn (srstn),
.test_in (test_in),
.test_out (test_out_int),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.tx_cred0 (tx_stream_cred0),
.tx_fifo_empty0 (tx_fifo_empty0),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.tx_st_data0 (tx_st_data0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_stream_ready0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_stream_valid0),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext)
);
altpcierd_reconfig_clk_pll reconfig_pll
(
.c0 (reconfig_clk),
.c1 (fixedclk_serdes),
.inclk0 (free_100MHz),
.locked (reconfig_clk_locked)
);
altpcierd_tl_cfg_sample cfgbus
(
.cfg_busdev (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr_icm),
.cfg_io_bas (cfg_io_bas),
.cfg_linkcsr (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_np_bas (cfg_np_bas),
.cfg_pr_bas (cfg_pr_bas),
.cfg_prmcsr (cfg_prmcsr_icm),
.cfg_tcvcmap (open_cfg_tcvcmap),
.pld_clk (pld_clk),
.rstn (srstn),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr)
);
defparam cfgbus.HIP_SV = 0;
altpcierd_cplerr_lmi lmi_blk
(
.clk_in (pld_clk),
.cpl_err_in (cpl_err_in),
.cpl_err_out (cpl_err_icm),
.cplerr_lmi_busy (open_cplerr_lmi_busy),
.err_desc (err_desc),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.rstn (srstn)
);
altpcierd_example_app_chaining app
(
.aer_msi_num (open_aer_msi_num),
.app_int_ack (app_int_ack_icm),
.app_int_sts (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.cfg_busdev (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr_icm),
.cfg_linkcsr (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_prmcsr (cfg_prmcsr_icm),
.cfg_tcvcmap (gnd_cfg_tcvcmap_icm),
.clk_in (pld_clk),
.cpl_err (cpl_err_in),
.cpl_pending (cpl_pending_icm),
.err_desc (err_desc),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.msi_stream_data0 (open_msi_stream_data0),
.msi_stream_ready0 (gnd_msi_stream_ready0),
.msi_stream_valid0 (open_msi_stream_valid0),
.pex_msi_num (pex_msi_num_icm),
.pm_data (open_pm_data),
.rstn (srstn),
.rx_stream_data0_0 (rx_stream_data0),
.rx_stream_data0_1 (rx_stream_data0_1),
.rx_stream_mask0 (rx_mask0),
.rx_stream_ready0 (rx_stream_ready0),
.rx_stream_valid0 (rx_stream_valid0),
.test_sim (test_in[0]),
.tx_stream_cred0 (tx_stream_cred0),
.tx_stream_data0_0 (tx_stream_data0),
.tx_stream_data0_1 (tx_stream_data0_1),
.tx_stream_fifo_empty0 (tx_fifo_empty0),
.tx_stream_mask0 (gnd_tx_stream_mask0),
.tx_stream_ready0 (tx_stream_ready0),
.tx_stream_valid0 (tx_stream_valid0)
);
defparam app.AVALON_WADDR = 12,
app.CHECK_BUS_MASTER_ENA = 1,
app.CHECK_RX_BUFFER_CPL = 1,
app.CLK_250_APP = 0,
app.ECRC_FORWARD_CHECK = 0,
app.ECRC_FORWARD_GENER = 0,
app.MAX_NUMTAG = 32,
app.MAX_PAYLOAD_SIZE_BYTE = 256,
app.TL_SELECTION = 7,
app.TXCRED_WIDTH = 36;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_TB_V
`define SKY130_FD_SC_HD__O221AI_TB_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o221ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_TB_V
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 15:50:55 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_auto_pc_0_sim_netlist.v
// Design : gcd_block_design_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [22:0]Q;
wire \RD.ar_channel_0_n_0 ;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_16 ;
wire \RD.ar_channel_0_n_3 ;
wire \RD.ar_channel_0_n_4 ;
wire \RD.ar_channel_0_n_46 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_5 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_132;
wire SI_REG_n_133;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_149;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_155;
wire SI_REG_n_156;
wire SI_REG_n_157;
wire SI_REG_n_161;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_168;
wire SI_REG_n_169;
wire SI_REG_n_170;
wire SI_REG_n_171;
wire SI_REG_n_172;
wire SI_REG_n_173;
wire SI_REG_n_174;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_26;
wire SI_REG_n_64;
wire SI_REG_n_8;
wire SI_REG_n_82;
wire \WR.aw_channel_0_n_0 ;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_15 ;
wire \WR.aw_channel_0_n_3 ;
wire \WR.aw_channel_0_n_4 ;
wire \WR.aw_channel_0_n_47 ;
wire \WR.aw_channel_0_n_48 ;
wire \WR.aw_channel_0_n_49 ;
wire \WR.aw_channel_0_n_50 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire \ar.ar_pipe/m_valid_i0 ;
wire \ar.ar_pipe/p_1_in ;
wire \ar.ar_pipe/s_ready_i0 ;
wire [1:0]\ar_cmd_fsm_0/state ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire \aw.aw_pipe/p_1_in ;
wire [1:0]\aw_cmd_fsm_0/state ;
wire [11:0]axaddr_incr;
wire [11:0]b_awid;
wire [3:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:2]wrap_cnt;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel \RD.ar_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.E(\ar.ar_pipe/p_1_in ),
.O({SI_REG_n_140,SI_REG_n_141,SI_REG_n_142,SI_REG_n_143}),
.Q({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset [1:0]}),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [2]),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [1:0]}),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_161),
.\axaddr_offset_r_reg[3]_1 (SI_REG_n_165),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_4 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_5 ),
.\m_payload_i_reg[3] ({SI_REG_n_132,SI_REG_n_133,SI_REG_n_134,SI_REG_n_135}),
.\m_payload_i_reg[47] (SI_REG_n_64),
.\m_payload_i_reg[47]_0 (SI_REG_n_167),
.\m_payload_i_reg[5] (SI_REG_n_166),
.\m_payload_i_reg[6] ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\m_payload_i_reg[7] ({SI_REG_n_136,SI_REG_n_137,SI_REG_n_138,SI_REG_n_139}),
.m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_3 ),
.r_rlast(r_rlast),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
.s_ready_i_reg(s_axi_arready),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\ar_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_0 ),
.\wrap_cnt_r_reg[3] (\RD.ar_channel_0_n_10 ),
.\wrap_cnt_r_reg[3]_0 (\RD.ar_channel_0_n_11 ),
.\wrap_cnt_r_reg[3]_1 (\RD.ar_channel_0_n_16 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_156,SI_REG_n_157}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_168),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_3 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice SI_REG
(.D(wrap_cnt),
.E(\aw.aw_pipe/p_1_in ),
.O({SI_REG_n_140,SI_REG_n_141,SI_REG_n_142,SI_REG_n_143}),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_26,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[3] ({SI_REG_n_132,SI_REG_n_133,SI_REG_n_134,SI_REG_n_135}),
.\axaddr_incr_reg[7] ({SI_REG_n_136,SI_REG_n_137,SI_REG_n_138,SI_REG_n_139}),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [1:0]}),
.axaddr_offset_0({\cmd_translator_0/wrap_cmd_0/axaddr_offset [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset [1:0]}),
.\axaddr_offset_r_reg[2] (SI_REG_n_154),
.\axaddr_offset_r_reg[2]_0 (SI_REG_n_166),
.\axaddr_offset_r_reg[2]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2]),
.\axaddr_offset_r_reg[2]_2 (\WR.aw_channel_0_n_15 ),
.\axaddr_offset_r_reg[2]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [2]),
.\axaddr_offset_r_reg[2]_4 (\RD.ar_channel_0_n_16 ),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\WR.aw_channel_0_n_10 ),
.\axaddr_offset_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [1:0]}),
.\axaddr_offset_r_reg[3]_2 (\RD.ar_channel_0_n_11 ),
.\axlen_cnt_reg[3] (SI_REG_n_8),
.\axlen_cnt_reg[3]_0 (SI_REG_n_64),
.b_push(b_push),
.\cnt_read_reg[2]_rep__0 (SI_REG_n_168),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_0 ),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 }),
.m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
.m_valid_i_reg(\ar.ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_155),
.next_pending_r_reg_0(SI_REG_n_167),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_4 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_5 ),
.\state_reg[1] (\aw_cmd_fsm_0/state ),
.\state_reg[1]_0 (\ar_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_3 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_0 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_4 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\wrap_cnt_r_reg[2] (SI_REG_n_149),
.\wrap_cnt_r_reg[2]_0 (SI_REG_n_161),
.\wrap_cnt_r_reg[3] (SI_REG_n_153),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_156,SI_REG_n_157}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_165),
.\wrap_second_len_r_reg[1] (\WR.aw_channel_0_n_9 ),
.\wrap_second_len_r_reg[1]_0 (\RD.ar_channel_0_n_10 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ),
.\wrap_second_len_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel \WR.aw_channel_0
(.D(wrap_cnt),
.E(\aw.aw_pipe/p_1_in ),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_26,si_rs_awsize,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_incr(axaddr_incr),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [1:0]}),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2]),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [1:0]}),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_149),
.\axaddr_offset_r_reg[3]_1 (SI_REG_n_153),
.\axlen_cnt_reg[7] (\WR.aw_channel_0_n_3 ),
.\axlen_cnt_reg[7]_0 (\WR.aw_channel_0_n_4 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[47] (SI_REG_n_8),
.\m_payload_i_reg[47]_0 (SI_REG_n_155),
.\m_payload_i_reg[5] (SI_REG_n_154),
.\m_payload_i_reg[6] ({SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175}),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0]_rep (\aw_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_0 ),
.\wrap_cnt_r_reg[3] (\WR.aw_channel_0_n_9 ),
.\wrap_cnt_r_reg[3]_0 (\WR.aw_channel_0_n_10 ),
.\wrap_cnt_r_reg[3]_1 (\WR.aw_channel_0_n_15 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0]_rep ,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_1 ,
m_axi_arvalid,
m_valid_i0,
s_ready_i0,
E,
r_rlast,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
Q,
m_axi_arready,
si_rs_arvalid,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axaddr_offset_r_reg[3]_0 ,
axaddr_offset,
\axaddr_offset_r_reg[3]_1 ,
D,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[5] ,
s_axi_arvalid,
s_ready_i_reg,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0]_rep ;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_1 ;
output m_axi_arvalid;
output m_valid_i0;
output s_ready_i0;
output [0:0]E;
output r_rlast;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [31:0]Q;
input m_axi_arready;
input si_rs_arvalid;
input \cnt_read_reg[2]_rep__0 ;
input \m_payload_i_reg[47] ;
input \axaddr_offset_r_reg[3]_0 ;
input [2:0]axaddr_offset;
input \axaddr_offset_r_reg[3]_1 ;
input [2:0]D;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[5] ;
input s_axi_arvalid;
input s_ready_i_reg;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input [1:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6] ;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [31:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_10;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_6;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_3;
wire \cnt_read_reg[2]_rep__0 ;
wire \incr_cmd_0/sel_first ;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[5] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire m_valid_i0;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]\state_reg[0]_rep ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [2:2]\wrap_cmd_0/axaddr_offset_r ;
wire [0:0]\wrap_cmd_0/wrap_second_len ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [1:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_6),
.E(ar_cmd_fsm_0_n_8),
.Q(\state_reg[0]_rep ),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_16),
.axaddr_offset(axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[7]_0 (cmd_translator_0_n_3),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[46] (Q[18]),
.\m_payload_i_reg[5] (\m_payload_i_reg[5] ),
.m_valid_i0(m_valid_i0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq1_reg(cmd_translator_0_n_10),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i0(s_ready_i0),
.s_ready_i_reg(s_ready_i_reg),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_9),
.sel_first_reg_0(ar_cmd_fsm_0_n_10),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(cmd_translator_0_n_0),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\wrap_boundary_axaddr_r_reg[11] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.\wrap_second_len_r_reg[0] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[0]_0 (\wrap_second_len_r_reg[3] [0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 cmd_translator_0
(.D({axaddr_offset[2],\axaddr_offset_r_reg[2] ,axaddr_offset[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(Q[19:0]),
.S(S),
.aclk(aclk),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r ,\axaddr_offset_r_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[0] (cmd_translator_0_n_3),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_8),
.r_rlast(r_rlast),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_0),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(ar_cmd_fsm_0_n_10),
.sel_first_reg_3(ar_cmd_fsm_0_n_9),
.sel_first_reg_4(ar_cmd_fsm_0_n_16),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (cmd_translator_0_n_10),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0]_0 ),
.\state_reg[1] (\state_reg[0]_rep ),
.\state_reg[1]_0 (ar_cmd_fsm_0_n_0),
.\state_reg[1]_rep (r_push_r_reg),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 ({D,\wrap_cmd_0/wrap_second_len }),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 ,ar_cmd_fsm_0_n_6}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[31]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0]_rep ,
\axlen_cnt_reg[7] ,
\axlen_cnt_reg[7]_0 ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_1 ,
E,
b_push,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
Q,
si_rs_awvalid,
\cnt_read_reg[1]_rep__0 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
D,
\axaddr_offset_r_reg[3]_0 ,
axaddr_offset,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[47] ,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[5] ,
axaddr_incr,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0]_rep ;
output \axlen_cnt_reg[7] ;
output \axlen_cnt_reg[7]_0 ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_1 ;
output [0:0]E;
output b_push;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [15:0]in;
output [3:0]S;
input aclk;
input [31:0]Q;
input si_rs_awvalid;
input \cnt_read_reg[1]_rep__0 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [1:0]D;
input \axaddr_offset_r_reg[3]_0 ;
input [2:0]axaddr_offset;
input \axaddr_offset_r_reg[3]_1 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[47] ;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[5] ;
input [11:0]axaddr_incr;
input [6:0]\m_payload_i_reg[6] ;
wire [1:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_12;
wire aw_cmd_fsm_0_n_14;
wire aw_cmd_fsm_0_n_15;
wire aw_cmd_fsm_0_n_16;
wire aw_cmd_fsm_0_n_2;
wire aw_cmd_fsm_0_n_8;
wire aw_cmd_fsm_0_n_9;
wire [11:0]axaddr_incr;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[5] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire sel_first;
wire sel_first_i;
wire si_rs_awvalid;
wire [1:0]\state_reg[0]_rep ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [2:2]\wrap_cmd_0/axaddr_offset_r ;
wire [0:0]\wrap_cmd_0/wrap_second_len ;
wire [0:0]wrap_cnt;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(wrap_cnt),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(\state_reg[0]_rep ),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset(axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axaddr_wrap_reg[11] (aw_cmd_fsm_0_n_14),
.\axlen_cnt_reg[0] (aw_cmd_fsm_0_n_8),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (\axlen_cnt_reg[7] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7]_0 ),
.\axlen_cnt_reg[7]_1 (aw_cmd_fsm_0_n_2),
.\axlen_cnt_reg[7]_2 (cmd_translator_0_n_6),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[46] ({Q[18],Q[16:15]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[5] (\m_payload_i_reg[5] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_9),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_12),
.s_axburst_eq1_reg_0(cmd_translator_0_n_12),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_15),
.sel_first_reg_0(aw_cmd_fsm_0_n_16),
.sel_first_reg_1(cmd_translator_0_n_2),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[0] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[0]_0 (\wrap_second_len_r_reg[3] [0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator cmd_translator_0
(.D({axaddr_offset[2],\axaddr_offset_r_reg[2] ,axaddr_offset[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(cmd_translator_0_n_5),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r ,\axaddr_offset_r_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[2] (cmd_translator_0_n_6),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_9),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_12),
.\m_payload_i_reg[47] (Q[19:0]),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_1 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_16),
.sel_first_reg_2(aw_cmd_fsm_0_n_15),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (aw_cmd_fsm_0_n_14),
.\state_reg[0]_rep (aw_cmd_fsm_0_n_2),
.\state_reg[1] (\state_reg[0]_rep ),
.\state_reg[1]_0 (aw_cmd_fsm_0_n_8),
.\state_reg[1]_rep (cmd_translator_0_n_12),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 ({D,wrap_cnt}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 ,\wrap_cmd_0/wrap_second_len }));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(in[7]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(in[3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__0 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__0 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [15:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_6_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_3),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_5),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_6_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_6_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_6
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_6_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_3),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_5),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
sel_first_0,
sel_first,
Q,
\axlen_cnt_reg[2] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\state_reg[1]_rep ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
sel_first_reg_2,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_awvalid,
\axaddr_offset_r_reg[3]_0 ,
D,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[47]_1 ,
next,
axaddr_incr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0] ,
\state_reg[1]_0 ,
\state_reg[0]_rep ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output sel_first_0;
output sel_first;
output [0:0]Q;
output \axlen_cnt_reg[2] ;
output \wrap_cnt_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \state_reg[1]_rep ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input sel_first_reg_2;
input [0:0]E;
input [19:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_awvalid;
input \axaddr_offset_r_reg[3]_0 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[47]_1 ;
input next;
input [11:0]axaddr_incr;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1]_0 ;
input \state_reg[0]_rep ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[2] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [19:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[47]_1 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [0:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \wrap_cnt_r_reg[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd incr_cmd_0
(.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[0]_0 (sel_first_0),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[11] (incr_cmd_0_n_15),
.\m_axi_awaddr[5] (incr_cmd_0_n_16),
.\m_payload_i_reg[46] ({\m_payload_i_reg[47] [18:17],\m_payload_i_reg[47] [14:12],\m_payload_i_reg[47] [5],\m_payload_i_reg[47] [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[47] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[47] ({\m_payload_i_reg[47] [19:15],\m_payload_i_reg[47] [13:0]}),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_1 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.sel_first_reg_0(sel_first),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_15),
.sel_first_reg_3(incr_cmd_0_n_16),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_0 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_cmd_translator" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1
(sel_first_reg_0,
sel_first,
sel_first_reg_1,
\axlen_cnt_reg[0] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
S,
aclk,
sel_first_i,
sel_first_reg_2,
sel_first_reg_3,
E,
Q,
\state_reg[1] ,
si_rs_arvalid,
\m_payload_i_reg[47] ,
\axaddr_offset_r_reg[3]_0 ,
D,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\state_reg[0]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
m_valid_i_reg,
\state_reg[1]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
sel_first_reg_4,
m_axi_arready);
output sel_first_reg_0;
output sel_first;
output sel_first_reg_1;
output \axlen_cnt_reg[0] ;
output \wrap_cnt_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input sel_first_i;
input sel_first_reg_2;
input sel_first_reg_3;
input [0:0]E;
input [19:0]Q;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \m_payload_i_reg[47] ;
input \axaddr_offset_r_reg[3]_0 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[0]_rep_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input \state_reg[1]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [0:0]sel_first_reg_4;
input m_axi_arready;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [19:0]Q;
wire [3:0]S;
wire aclk;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[0] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire [0:0]sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire wrap_cmd_0_n_6;
wire wrap_cmd_0_n_7;
wire \wrap_cnt_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 incr_cmd_0
(.E(E),
.O(O),
.Q({Q[18:16],Q[14:12],Q[5],Q[3:0]}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[0]_0 (sel_first),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10}),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[11] (incr_cmd_0_n_11),
.\m_axi_araddr[1] (incr_cmd_0_n_15),
.\m_axi_araddr[2] (incr_cmd_0_n_14),
.\m_axi_araddr[3] (incr_cmd_0_n_13),
.\m_axi_araddr[5] (incr_cmd_0_n_12),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_4),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_0 (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(Q[15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_6),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_7),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 wrap_cmd_0
(.D(D),
.E(E),
.Q({Q[19:15],Q[13:0]}),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.s_axburst_eq0_reg(wrap_cmd_0_n_6),
.s_axburst_eq1_reg(wrap_cmd_0_n_7),
.sel_first_i(sel_first_i),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_11),
.sel_first_reg_3(incr_cmd_0_n_12),
.sel_first_reg_4(incr_cmd_0_n_13),
.sel_first_reg_5(incr_cmd_0_n_14),
.sel_first_reg_6(incr_cmd_0_n_15),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[0]_0 ,
Q,
\axlen_cnt_reg[2]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_awaddr[11] ,
\m_axi_awaddr[5] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
E,
\m_payload_i_reg[46] ,
\m_payload_i_reg[47] ,
next,
axaddr_incr,
\state_reg[0] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output \axaddr_incr_reg[0]_0 ;
output [0:0]Q;
output \axlen_cnt_reg[2]_0 ;
output [10:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_awaddr[11] ;
output \m_axi_awaddr[5] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [0:0]E;
input [9:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[47] ;
input next;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire \axaddr_incr[0]_i_1_n_0 ;
wire \axaddr_incr[10]_i_1_n_0 ;
wire \axaddr_incr[11]_i_1_n_0 ;
wire \axaddr_incr[11]_i_2_n_0 ;
wire \axaddr_incr[1]_i_1_n_0 ;
wire \axaddr_incr[2]_i_1_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1_n_0 ;
wire \axaddr_incr[4]_i_1_n_0 ;
wire \axaddr_incr[5]_i_1_n_0 ;
wire \axaddr_incr[6]_i_1_n_0 ;
wire \axaddr_incr[7]_i_1_n_0 ;
wire \axaddr_incr[8]_i_1_n_0 ;
wire \axaddr_incr[9]_i_1_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [10:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4_n_1 ;
wire \axaddr_incr_reg[11]_i_4_n_2 ;
wire \axaddr_incr_reg[11]_i_4_n_3 ;
wire \axaddr_incr_reg[11]_i_4_n_4 ;
wire \axaddr_incr_reg[11]_i_4_n_5 ;
wire \axaddr_incr_reg[11]_i_4_n_6 ;
wire \axaddr_incr_reg[11]_i_4_n_7 ;
wire \axaddr_incr_reg[3]_i_3_n_0 ;
wire \axaddr_incr_reg[3]_i_3_n_1 ;
wire \axaddr_incr_reg[3]_i_3_n_2 ;
wire \axaddr_incr_reg[3]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_3_n_4 ;
wire \axaddr_incr_reg[3]_i_3_n_5 ;
wire \axaddr_incr_reg[3]_i_3_n_6 ;
wire \axaddr_incr_reg[3]_i_3_n_7 ;
wire \axaddr_incr_reg[7]_i_3_n_0 ;
wire \axaddr_incr_reg[7]_i_3_n_1 ;
wire \axaddr_incr_reg[7]_i_3_n_2 ;
wire \axaddr_incr_reg[7]_i_3_n_3 ;
wire \axaddr_incr_reg[7]_i_3_n_4 ;
wire \axaddr_incr_reg[7]_i_3_n_5 ;
wire \axaddr_incr_reg[7]_i_3_n_6 ;
wire \axaddr_incr_reg[7]_i_3_n_7 ;
wire \axaddr_incr_reg_n_0_[5] ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_2_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[2]_0 ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[11] ;
wire \m_axi_awaddr[5] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire next;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire sel_first_reg_0;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire [0:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1
(.I0(axaddr_incr[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_7 ),
.O(\axaddr_incr[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1
(.I0(axaddr_incr[10]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_5 ),
.O(\axaddr_incr[10]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\axaddr_incr[11]_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(next),
.O(\axaddr_incr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2
(.I0(axaddr_incr[11]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_4 ),
.O(\axaddr_incr[11]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1
(.I0(axaddr_incr[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_6 ),
.O(\axaddr_incr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1
(.I0(axaddr_incr[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_5 ),
.O(\axaddr_incr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1
(.I0(axaddr_incr[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_4 ),
.O(\axaddr_incr[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0102))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg[11]_0 [3]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg[11]_0 [2]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[3]));
LUT4 #(
.INIT(16'h262A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[2]));
LUT4 #(
.INIT(16'h060A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.I3(next),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1
(.I0(axaddr_incr[4]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_7 ),
.O(\axaddr_incr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1
(.I0(axaddr_incr[5]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_6 ),
.O(\axaddr_incr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1
(.I0(axaddr_incr[6]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_5 ),
.O(\axaddr_incr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1
(.I0(axaddr_incr[7]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_4 ),
.O(\axaddr_incr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1
(.I0(axaddr_incr[8]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_7 ),
.O(\axaddr_incr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1
(.I0(axaddr_incr[9]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_6 ),
.O(\axaddr_incr[9]_i_1_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[0]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[10]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[11]_i_2_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [10]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4
(.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
.S(\axaddr_incr_reg[11]_0 [10:7]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[1]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[2]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[3]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(\axaddr_incr_reg[11]_0 [3:0]),
.O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[4]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[5]_i_1_n_0 ),
.Q(\axaddr_incr_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[6]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[7]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3
(.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
.S({\axaddr_incr_reg[11]_0 [6:5],\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg[11]_0 [4]}));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[8]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[9]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[2]_0 ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[2]_i_1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(Q),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg[2]_0 ),
.I4(E),
.I5(\m_payload_i_reg[46] [9]),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEBAAAAAAAA))
\axlen_cnt[3]_i_2
(.I0(\m_payload_i_reg[47] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(Q),
.I5(\axlen_cnt_reg[2]_0 ),
.O(\axlen_cnt[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(Q),
.O(\axlen_cnt[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\state_reg[1] ),
.Q(Q),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[0]_rep ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [7]),
.O(\m_axi_awaddr[11] ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[5] ),
.I2(\m_payload_i_reg[46] [7]),
.I3(\m_payload_i_reg[46] [4]),
.O(\m_axi_awaddr[5] ));
LUT5 #(
.INIT(32'h55545555))
next_pending_r_i_3__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.I4(next_pending_r_i_5_n_0),
.O(\axlen_cnt_reg[2]_0 ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_incr_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_araddr[11] ,
\m_axi_araddr[5] ,
\m_axi_araddr[3] ,
\m_axi_araddr[2] ,
\m_axi_araddr[1] ,
S,
aclk,
sel_first_reg_0,
E,
Q,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
\m_payload_i_reg[47]_0 ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep ,
m_valid_i_reg,
\state_reg[1] ,
sel_first_reg_1,
\state_reg[1]_0 ,
m_axi_arready);
output incr_next_pending;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [7:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_araddr[11] ;
output \m_axi_araddr[5] ;
output \m_axi_araddr[3] ;
output \m_axi_araddr[2] ;
output \m_axi_araddr[1] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input [0:0]E;
input [10:0]Q;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[47]_0 ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [0:0]sel_first_reg_1;
input [1:0]\state_reg[1]_0 ;
input m_axi_arready;
wire [0:0]E;
wire [3:0]O;
wire [10:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1__0_n_0 ;
wire \axaddr_incr[10]_i_1__0_n_0 ;
wire \axaddr_incr[11]_i_2__0_n_0 ;
wire \axaddr_incr[1]_i_1__0_n_0 ;
wire \axaddr_incr[2]_i_1__0_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1__0_n_0 ;
wire \axaddr_incr[4]_i_1__0_n_0 ;
wire \axaddr_incr[5]_i_1__0_n_0 ;
wire \axaddr_incr[6]_i_1__0_n_0 ;
wire \axaddr_incr[7]_i_1__0_n_0 ;
wire \axaddr_incr[8]_i_1__0_n_0 ;
wire \axaddr_incr[9]_i_1__0_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [7:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
wire \axaddr_incr_reg_n_0_[1] ;
wire \axaddr_incr_reg_n_0_[2] ;
wire \axaddr_incr_reg_n_0_[3] ;
wire \axaddr_incr_reg_n_0_[5] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__1_n_0 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2__0_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[11] ;
wire \m_axi_araddr[1] ;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[3] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__0_n_0;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire [0:0]sel_first_reg_1;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
.O(\axaddr_incr[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1__0
(.I0(O[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
.O(\axaddr_incr[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2__0
(.I0(O[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
.O(\axaddr_incr[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
.O(\axaddr_incr[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
.O(\axaddr_incr[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[3]_i_10
(.I0(Q[0]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg_n_0_[3] ),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg_n_0_[2] ),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg_n_0_[1] ),
.I1(Q[6]),
.I2(Q[5]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
.O(\axaddr_incr[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[3]_i_7
(.I0(Q[3]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[3]_i_8
(.I0(Q[2]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[3]_i_9
(.I0(Q[1]),
.I1(Q[5]),
.I2(Q[6]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1__0
(.I0(\m_payload_i_reg[7] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
.O(\axaddr_incr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1__0
(.I0(\m_payload_i_reg[7] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
.O(\axaddr_incr[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1__0
(.I0(\m_payload_i_reg[7] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
.O(\axaddr_incr[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1__0
(.I0(\m_payload_i_reg[7] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
.O(\axaddr_incr[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1__0
(.I0(O[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
.O(\axaddr_incr[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1__0
(.I0(O[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
.O(\axaddr_incr[9]_i_1__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[0]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[10]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[11]_i_2__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4__0
(.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
.S(\axaddr_incr_reg[11]_0 [7:4]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[1]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[2]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[3]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg_n_0_[1] ,\axaddr_incr_reg[11]_0 [0]}),
.O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[4]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[5]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[6]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[7]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3__0
(.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
.S({\axaddr_incr_reg[11]_0 [3:2],\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg[11]_0 [1]}));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[8]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[9]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1__2
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(Q[8]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(Q[9]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[2]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg[0]_0 ),
.I4(E),
.I5(Q[10]),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEBAAAAAAAA))
\axlen_cnt[3]_i_2__0
(.I0(\m_payload_i_reg[47] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h55545555))
\axlen_cnt[3]_i_4
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.I4(next_pending_r_i_4__0_n_0),
.O(\axlen_cnt_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(Q[7]),
.O(\m_axi_araddr[11] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[1] ),
.I2(Q[7]),
.I3(Q[1]),
.O(\m_axi_araddr[1] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[2] ),
.I2(Q[7]),
.I3(Q[2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[3]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[3] ),
.I2(Q[7]),
.I3(Q[3]),
.O(\m_axi_araddr[3] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[5] ),
.I2(Q[7]),
.I3(Q[4]),
.O(\m_axi_araddr[5] ));
LUT5 #(
.INIT(32'hFFFF505C))
next_pending_r_i_1__2
(.I0(next_pending_r_i_2__0_n_0),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(E),
.I4(\m_payload_i_reg[47]_0 ),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_2__0
(.I0(next_pending_r_i_4__0_n_0),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_2__0_n_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_4__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_1;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_4;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_2 (rd_data_fifo_0_n_2),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_4));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__3 (rd_data_fifo_0_n_2),
.\cnt_read_reg[0]_rep__3_0 (rd_data_fifo_0_n_4),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (rd_data_fifo_0_n_1),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm
(\axlen_cnt_reg[7] ,
Q,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
D,
\wrap_second_len_r_reg[0] ,
E,
sel_first_reg,
sel_first_reg_0,
sel_first_i,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[11] ,
\axaddr_incr_reg[0] ,
m_axi_arvalid,
m_valid_i0,
s_ready_i0,
\m_payload_i_reg[0]_1 ,
m_axi_arready,
si_rs_arvalid,
\axlen_cnt_reg[7]_0 ,
s_axburst_eq1_reg,
\cnt_read_reg[2]_rep__0 ,
\wrap_second_len_r_reg[0]_0 ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
sel_first_reg_1,
areset_d1,
sel_first,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[46] ,
\m_payload_i_reg[5] ,
s_axi_arvalid,
s_ready_i_reg,
aclk);
output \axlen_cnt_reg[7] ;
output [1:0]Q;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[0] ;
output [0:0]E;
output sel_first_reg;
output sel_first_reg_0;
output sel_first_i;
output \wrap_cnt_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_0 ;
output [0:0]\wrap_boundary_axaddr_r_reg[11] ;
output [0:0]\axaddr_incr_reg[0] ;
output m_axi_arvalid;
output m_valid_i0;
output s_ready_i0;
output [0:0]\m_payload_i_reg[0]_1 ;
input m_axi_arready;
input si_rs_arvalid;
input \axlen_cnt_reg[7]_0 ;
input s_axburst_eq1_reg;
input \cnt_read_reg[2]_rep__0 ;
input [0:0]\wrap_second_len_r_reg[0]_0 ;
input \axaddr_offset_r_reg[3] ;
input [0:0]axaddr_offset;
input sel_first_reg_1;
input areset_d1;
input sel_first;
input sel_first_reg_2;
input [1:0]\axaddr_offset_r_reg[3]_0 ;
input [0:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[5] ;
input s_axi_arvalid;
input s_ready_i_reg;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]\axaddr_incr_reg[0] ;
wire [0:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire \cnt_read_reg[2]_rep__0 ;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[5] ;
wire m_valid_i0;
wire [1:0]next_state__0;
wire r_push_r_reg;
wire s_axburst_eq1_reg;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg;
wire sel_first;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire [0:0]\wrap_boundary_axaddr_r_reg[11] ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]\wrap_second_len_r_reg[0] ;
wire [0:0]\wrap_second_len_r_reg[0]_0 ;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[11]_i_1__0
(.I0(sel_first),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[0] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[5] ),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[3]_i_1__2
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(Q[0]),
.I3(Q[1]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00005140))
\axlen_cnt[7]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(m_axi_arready),
.I3(si_rs_arvalid),
.I4(\axlen_cnt_reg[7]_0 ),
.O(\axlen_cnt_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(m_valid_i0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h8FFF8F8F))
s_ready_i_i_1__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(s_ready_i0));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__2
(.I0(m_axi_arready),
.I1(sel_first_reg_1),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first),
.I2(\m_payload_i_reg[0] ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0]_0 ),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__4
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_2),
.O(sel_first_i));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state__0[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state__0[1]));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state__0[0]),
.Q(Q[0]),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state__0[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state__0[1]),
.Q(Q[1]),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state__0[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(\wrap_boundary_axaddr_r_reg[11] ));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_4__0
(.I0(\axaddr_offset_r_reg[3]_0 [1]),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(\m_payload_i_reg[0] ),
.O(\wrap_cnt_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_6__0
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(\m_payload_i_reg[0] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(\wrap_second_len_r_reg[0] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__0_0 ,
SR,
D,
bresp_push,
bvalid_i_reg,
out,
b_push,
shandshake_r,
areset_d1,
Q,
\bresp_cnt_reg[7] ,
mhandshake_r,
si_rs_bready,
bvalid_i_reg_0,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output [0:0]SR;
output [0:0]D;
output bresp_push;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input [1:0]Q;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input si_rs_bready;
input bvalid_i_reg_0;
input [15:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire \bresp_cnt[7]_i_3_n_0 ;
wire \bresp_cnt[7]_i_4_n_0 ;
wire \bresp_cnt[7]_i_5_n_0 ;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [15:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire shandshake_r;
wire si_rs_bready;
LUT4 #(
.INIT(16'hABAA))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(\bresp_cnt[7]_i_4_n_0 ),
.I3(\bresp_cnt[7]_i_5_n_0 ),
.O(SR));
LUT6 #(
.INIT(64'hEEFEFFFFFFFFEEFE))
\bresp_cnt[7]_i_3
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\bresp_cnt_reg[7] [6]),
.I2(\bresp_cnt_reg[7] [0]),
.I3(\memory_reg[3][0]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFF6FFFF))
\bresp_cnt[7]_i_4
(.I0(\bresp_cnt_reg[7] [1]),
.I1(\memory_reg[3][1]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [4]),
.I3(\bresp_cnt_reg[7] [5]),
.I4(mhandshake_r),
.O(\bresp_cnt[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000D00DD00DD00D))
\bresp_cnt[7]_i_5
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\memory_reg[3][2]_srl4_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_0 ),
.I5(\cnt_read_reg[0]_rep__0_0 ),
.O(\bresp_cnt[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'h0444))
bvalid_i_i_1
(.I0(areset_d1),
.I1(bvalid_i_i_2_n_0),
.I2(si_rs_bready),
.I3(bvalid_i_reg_0),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(bresp_push),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000041004141))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\bresp_cnt_reg[7] [0]),
.I4(\memory_reg[3][0]_srl4_n_0 ),
.I5(\memory_reg[3][0]_srl4_i_3_n_0 ),
.O(bresp_push));
LUT2 #(
.INIT(4'h8))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFB))
\memory_reg[3][0]_srl4_i_3
(.I0(\bresp_cnt[7]_i_3_n_0 ),
.I1(mhandshake_r),
.I2(\bresp_cnt_reg[7] [5]),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(out[1]));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0
(Q,
mhandshake,
m_axi_bready,
\skid_buffer_reg[1] ,
shandshake_r,
sel,
m_axi_bvalid,
mhandshake_r,
in,
aclk,
areset_d1,
D);
output [1:0]Q;
output mhandshake;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input shandshake_r;
input sel;
input m_axi_bvalid;
input mhandshake_r;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(shandshake_r),
.I3(sel),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1
(\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
\cnt_read_reg[4]_rep__2_2 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
\cnt_read_reg[4]_rep__0_0 ,
si_rs_rready,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output \cnt_read_reg[4]_rep__2_2 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input \cnt_read_reg[4]_rep__0_0 ;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_5_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep__3_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep__2_2 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h9AA6))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hA9AAAA6A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[0]_rep__2_n_0 ),
.I3(\cnt_read[4]_i_5_n_0 ),
.I4(s_ready_i_reg),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAA6AA9AAAAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read[4]_i_5_n_0 ),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h99AA99AA99AA55A6))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_1 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_2 ),
.I3(\cnt_read[4]_i_3__0_n_0 ),
.I4(s_ready_i_reg),
.I5(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\cnt_read[4]_i_2__0
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_2 ));
LUT6 #(
.INIT(64'h0000000000100000))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read[4]_i_5_n_0 ),
.I3(\cnt_read_reg[4]_rep__0_0 ),
.I4(si_rs_rready),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h6000E000FFFFFFFF))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.I5(m_axi_rvalid),
.O(\cnt_read[4]_i_5_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__3
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__3_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_1 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h9FFF1FFF))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'h8AAA0AAA0AAAAAAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[0]_rep__3_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[4]_rep__2_1 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.I5(\cnt_read_reg[2]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h40C0C000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2
(m_valid_i_reg,
\state_reg[1]_rep ,
\skid_buffer_reg[46] ,
s_ready_i_reg,
r_push_r,
si_rs_rready,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[4]_rep__2 ,
\cnt_read_reg[0]_rep__3 ,
\cnt_read_reg[0]_rep__3_0 ,
in,
aclk,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output [12:0]\skid_buffer_reg[46] ;
input s_ready_i_reg;
input r_push_r;
input si_rs_rready;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[4]_rep__2 ;
input \cnt_read_reg[0]_rep__3 ;
input \cnt_read_reg[0]_rep__3_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__3 ;
wire \cnt_read_reg[0]_rep__3_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(r_push_r),
.I2(s_ready_i_reg),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hDB24))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFF7F0080FEFF0100))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h9A999AAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[3]_rep__0_n_0 ),
.I4(\cnt_read[4]_i_3_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h2AAAAAAA2AAA2AAA))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__1_n_0 ),
.I3(r_push_r),
.I4(m_valid_i_reg),
.I5(si_rs_rready),
.O(\cnt_read[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000004))
\cnt_read[4]_i_3
(.I0(r_push_r),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(\cnt_read_reg[0]_rep__1_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'h80808080FF808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(m_valid_i_i_3_n_0),
.I3(\cnt_read_reg[3]_rep__2 ),
.I4(\cnt_read_reg[4]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__3 ),
.O(m_valid_i_reg));
LUT3 #(
.INIT(8'h80))
m_valid_i_i_3
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__1_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.O(m_valid_i_i_3_n_0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBFEEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__3_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__1_n_0 ),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm
(\axlen_cnt_reg[7] ,
\axlen_cnt_reg[7]_0 ,
\axlen_cnt_reg[7]_1 ,
next,
Q,
D,
\wrap_second_len_r_reg[0] ,
\axlen_cnt_reg[0] ,
s_axburst_eq0_reg,
incr_next_pending,
sel_first_i,
s_axburst_eq1_reg,
E,
\axaddr_wrap_reg[11] ,
sel_first_reg,
sel_first_reg_0,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_0 ,
\m_payload_i_reg[0] ,
b_push,
m_axi_awvalid,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
si_rs_awvalid,
\axlen_cnt_reg[7]_2 ,
\wrap_second_len_r_reg[0]_0 ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[0]_0 ,
wrap_next_pending,
next_pending_r_reg,
\m_payload_i_reg[47] ,
sel_first,
areset_d1,
sel_first_0,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[5] ,
aclk);
output \axlen_cnt_reg[7] ;
output \axlen_cnt_reg[7]_0 ;
output \axlen_cnt_reg[7]_1 ;
output next;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[0] ;
output [0:0]\axlen_cnt_reg[0] ;
output s_axburst_eq0_reg;
output incr_next_pending;
output sel_first_i;
output s_axburst_eq1_reg;
output [0:0]E;
output [0:0]\axaddr_wrap_reg[11] ;
output sel_first_reg;
output sel_first_reg_0;
output \wrap_cnt_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_0 ;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
output m_axi_awvalid;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input si_rs_awvalid;
input \axlen_cnt_reg[7]_2 ;
input [0:0]\wrap_second_len_r_reg[0]_0 ;
input \axaddr_offset_r_reg[3] ;
input [0:0]axaddr_offset;
input [2:0]\m_payload_i_reg[46] ;
input [0:0]\axlen_cnt_reg[0]_0 ;
input wrap_next_pending;
input next_pending_r_reg;
input \m_payload_i_reg[47] ;
input sel_first;
input areset_d1;
input sel_first_0;
input sel_first_reg_1;
input [1:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[5] ;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire [0:0]\axlen_cnt_reg[0] ;
wire [0:0]\axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg[7]_1 ;
wire \axlen_cnt_reg[7]_2 ;
wire b_push;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire [2:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[5] ;
wire next;
wire next_pending_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_awvalid;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[0] ;
wire [0:0]\wrap_second_len_r_reg[0]_0 ;
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[46] [2]),
.I2(\axlen_cnt_reg[7]_0 ),
.I3(si_rs_awvalid),
.I4(\axlen_cnt_reg[7] ),
.I5(\m_payload_i_reg[5] ),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__0
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[46] [1]),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\axlen_cnt_reg[7]_2 ),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFF04))
\axlen_cnt[3]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(next),
.O(\axaddr_wrap_reg[11] ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT5 #(
.INIT(32'h0000FF04))
\axlen_cnt[7]_i_1__0
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7] ),
.I3(next),
.I4(\axlen_cnt_reg[7]_2 ),
.O(\axlen_cnt_reg[7]_1 ));
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(\axlen_cnt_reg[7] ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(\axlen_cnt_reg[7] ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(s_axburst_eq1_reg_0),
.O(b_push));
LUT5 #(
.INIT(32'hFFFFF404))
next_pending_r_i_1
(.I0(E),
.I1(next_pending_r_reg),
.I2(next),
.I3(\axlen_cnt_reg[7]_2 ),
.I4(\m_payload_i_reg[47] ),
.O(incr_next_pending));
LUT6 #(
.INIT(64'hF3F3FFFF51000000))
next_pending_r_i_2
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\axlen_cnt_reg[7]_0 ),
.I5(\axlen_cnt_reg[7] ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hBA8A))
s_axburst_eq0_i_1
(.I0(incr_next_pending),
.I1(sel_first_i),
.I2(\m_payload_i_reg[46] [0]),
.I3(wrap_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hFE02))
s_axburst_eq1_i_1
(.I0(incr_next_pending),
.I1(\m_payload_i_reg[46] [0]),
.I2(sel_first_i),
.I3(wrap_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1
(.I0(next),
.I1(sel_first),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1__0
(.I0(next),
.I1(sel_first_0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFF04FFFFFF04FF04))
sel_first_i_1__1
(.I0(\axlen_cnt_reg[7] ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7]_0 ),
.I3(areset_d1),
.I4(next),
.I5(sel_first_reg_1),
.O(sel_first_i));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hBBBA))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00F000F055750000))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\cnt_read_reg[1]_rep__0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\axlen_cnt_reg[7]_0 ),
.I5(\axlen_cnt_reg[7] ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\axlen_cnt_reg[7] ),
.I5(\axlen_cnt_reg[7]_0 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg[7]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg[7] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\axlen_cnt_reg[7] ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7]_0 ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_4
(.I0(\axaddr_offset_r_reg[3]_0 [1]),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(si_rs_awvalid),
.I3(\axlen_cnt_reg[7] ),
.O(\wrap_cnt_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_6
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(si_rs_awvalid),
.I3(\axlen_cnt_reg[7] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(\wrap_second_len_r_reg[0] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd
(wrap_next_pending,
sel_first_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_awvalid,
\axaddr_offset_r_reg[3]_1 ,
D,
\m_payload_i_reg[47]_0 ,
next,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output \wrap_cnt_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_awvalid;
input \axaddr_offset_r_reg[3]_1 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input next;
input sel_first_reg_2;
input [10:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input \axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire aclk;
wire [10:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire [18:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_i_2__1_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [11:0]wrap_boundary_axaddr_r;
wire [1:1]wrap_cnt;
wire [3:0]wrap_cnt_r;
wire \wrap_cnt_r_reg[3]_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(wrap_cnt_r[2]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S(axaddr_wrap[11:8]));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S(axaddr_wrap[7:4]));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1
(.I0(\m_payload_i_reg[47] [16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAACCCCCCC0))
\axlen_cnt[3]_i_1
(.I0(\m_payload_i_reg[47] [18]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(E),
.O(\axlen_cnt[3]_i_1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_awaddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[5]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_awaddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[47]_0 ),
.I1(next_pending_r_reg_n_0),
.I2(next),
.I3(next_pending_r_i_2__1_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__1
(.I0(\state_reg[1] [0]),
.I1(si_rs_awvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__1_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h3D310E02))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_2 ),
.I3(D[1]),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(wrap_cnt));
LUT6 #(
.INIT(64'h000CAAA8000C0000))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_second_len_r_reg[3]_0 [1]),
.I1(\axaddr_offset_r_reg[3]_1 ),
.I2(D[1]),
.I3(D[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [0]),
.O(\wrap_cnt_r_reg[3]_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(wrap_cnt),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_wrap_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3
(sel_first_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
s_axburst_eq0_reg,
s_axburst_eq1_reg,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
Q,
\state_reg[1] ,
si_rs_arvalid,
\axaddr_offset_r_reg[3]_1 ,
D,
sel_first_i,
incr_next_pending,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
sel_first_reg_4,
sel_first_reg_5,
sel_first_reg_6,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output sel_first_reg_0;
output \wrap_cnt_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output s_axburst_eq0_reg;
output s_axburst_eq1_reg;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]Q;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \axaddr_offset_r_reg[3]_1 ;
input [3:0]D;
input sel_first_i;
input incr_next_pending;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [7:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input sel_first_reg_4;
input sel_first_reg_5;
input sel_first_reg_6;
input \axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [18:0]Q;
wire aclk;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__2_n_0;
wire next_pending_r_reg_n_0;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire sel_first_reg_5;
wire sel_first_reg_6;
wire si_rs_arvalid;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[11] ,\axaddr_wrap_reg_n_0_[10] ,\axaddr_wrap_reg_n_0_[9] ,\axaddr_wrap_reg_n_0_[8] }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[7] ,\axaddr_wrap_reg_n_0_[6] ,\axaddr_wrap_reg_n_0_[5] ,\axaddr_wrap_reg_n_0_[4] }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__1
(.I0(Q[15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1__2
(.I0(Q[16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(Q[17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAACCCCCCC0))
\axlen_cnt[3]_i_1__1
(.I0(Q[18]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(E),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(Q[14]),
.I3(Q[0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(Q[14]),
.I3(Q[10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(Q[14]),
.I3(Q[11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_araddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[1]_INST_0
(.I0(Q[1]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[1] ),
.I3(Q[14]),
.I4(sel_first_reg_6),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(Q[2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(Q[14]),
.I4(sel_first_reg_5),
.O(m_axi_araddr[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[3]_INST_0
(.I0(Q[3]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[3] ),
.I3(Q[14]),
.I4(sel_first_reg_4),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(Q[14]),
.I3(Q[4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(Q[5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(Q[14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(Q[14]),
.I3(Q[6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(Q[14]),
.I3(Q[7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(Q[14]),
.I3(Q[8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(Q[14]),
.I3(Q[9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[47] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(next_pending_r_i_2__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__2
(.I0(\state_reg[1] [0]),
.I1(si_rs_arvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(Q[14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(Q[14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h3D310E02))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_2 ),
.I3(D[1]),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h000CAAA8000C0000))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [1]),
.I1(\axaddr_offset_r_reg[3]_1 ),
.I2(D[1]),
.I3(D[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [0]),
.O(\wrap_cnt_r_reg[3]_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1__0_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
\axlen_cnt_reg[3] ,
Q,
\axlen_cnt_reg[3]_0 ,
\s_arid_r_reg[11] ,
axaddr_incr,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[7] ,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
axaddr_offset,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[2]_0 ,
axaddr_offset_0,
\wrap_cnt_r_reg[3]_1 ,
\axaddr_offset_r_reg[2]_0 ,
next_pending_r_reg_0,
\cnt_read_reg[2]_rep__0 ,
\wrap_boundary_axaddr_r_reg[6] ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
s_ready_i0,
m_valid_i0,
aresetn,
\state_reg[1] ,
\state_reg[1]_0 ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_1 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[2]_2 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_awvalid,
b_push,
\wrap_second_len_r_reg[3]_2 ,
\state_reg[1]_rep_1 ,
\wrap_second_len_r_reg[1]_0 ,
\axaddr_offset_r_reg[2]_3 ,
\axaddr_offset_r_reg[3]_1 ,
\axaddr_offset_r_reg[3]_2 ,
\axaddr_offset_r_reg[2]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
si_rs_bvalid,
s_axi_bready,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output \axlen_cnt_reg[3]_0 ;
output [54:0]\s_arid_r_reg[11] ;
output [11:0]axaddr_incr;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output [2:0]axaddr_offset;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [1:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[2]_0 ;
output [2:0]axaddr_offset_0;
output \wrap_cnt_r_reg[3]_1 ;
output \axaddr_offset_r_reg[2]_0 ;
output next_pending_r_reg_0;
output \cnt_read_reg[2]_rep__0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input s_ready_i0;
input m_valid_i0;
input aresetn;
input [1:0]\state_reg[1] ;
input [1:0]\state_reg[1]_0 ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_1 ;
input [2:0]\axaddr_offset_r_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[2]_2 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_awvalid;
input b_push;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input \state_reg[1]_rep_1 ;
input \wrap_second_len_r_reg[1]_0 ;
input [0:0]\axaddr_offset_r_reg[2]_3 ;
input [2:0]\axaddr_offset_r_reg[3]_1 ;
input \axaddr_offset_r_reg[3]_2 ;
input \axaddr_offset_r_reg[2]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire \ar.ar_pipe_n_2 ;
wire aresetn;
wire \aw.aw_pipe_n_1 ;
wire \aw.aw_pipe_n_90 ;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[2]_0 ;
wire [0:0]\axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[2]_2 ;
wire [0:0]\axaddr_offset_r_reg[2]_3 ;
wire \axaddr_offset_r_reg[2]_4 ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [2:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[2]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire m_valid_i0;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [54:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[2]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [1:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire \wrap_second_len_r_reg[1] ;
wire \wrap_second_len_r_reg[1]_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice \ar.ar_pipe
(.O(O),
.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[0]_0 (\aw.aw_pipe_n_90 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.axaddr_offset_0(axaddr_offset_0[2:1]),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2]_0 ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_3 ),
.\axaddr_offset_r_reg[2]_1 (\axaddr_offset_r_reg[2]_4 ),
.\axaddr_offset_r_reg[3] (si_rs_arvalid),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i0(m_valid_i0),
.m_valid_i_reg_0(\ar.ar_pipe_n_2 ),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_ready_i0(s_ready_i0),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 \aw.aw_pipe
(.D(D),
.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (\aw.aw_pipe_n_90 ),
.\aresetn_d_reg[1]_inv_0 (\ar.ar_pipe_n_2 ),
.axaddr_incr(axaddr_incr),
.axaddr_offset(axaddr_offset[2:1]),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_1 ),
.\axaddr_offset_r_reg[2]_1 (\axaddr_offset_r_reg[2]_2 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(\aw.aw_pipe_n_1 ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1 \b.b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\ar.ar_pipe_n_2 ),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2 \r.r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\ar.ar_pipe_n_2 ),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice
(s_axi_arready,
\axaddr_offset_r_reg[3] ,
m_valid_i_reg_0,
\axlen_cnt_reg[3] ,
Q,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[7] ,
O,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
\axaddr_offset_r_reg[0] ,
axaddr_offset_0,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[0] ,
s_ready_i0,
aclk,
m_valid_i0,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_valid_i_reg_1);
output s_axi_arready;
output \axaddr_offset_r_reg[3] ;
output m_valid_i_reg_0;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output \axaddr_offset_r_reg[0] ;
output [1:0]axaddr_offset_0;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
input \aresetn_d_reg[0] ;
input s_ready_i0;
input aclk;
input m_valid_i0;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input \axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [0:0]m_valid_i_reg_1;
wire [3:0]O;
wire [54:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[3]_i_4__0_n_0 ;
wire \axaddr_incr[3]_i_5__0_n_0 ;
wire \axaddr_incr[3]_i_6__0_n_0 ;
wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
wire [1:0]axaddr_offset_0;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[3]_i_2__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[2] ;
wire [0:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[3] ;
wire [2:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[52]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_ready_i0;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_5__0_n_0 ;
wire \wrap_cnt_r_reg[2] ;
wire [1:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire \wrap_second_len_r[3]_i_3__0_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6__0_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3__0
(.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[7]_i_2__0
(.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[36]),
.I3(Q[1]),
.I4(Q[35]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I1(Q[40]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(axaddr_offset_0[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[36]),
.I3(Q[3]),
.I4(Q[35]),
.I5(Q[2]),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I1(Q[42]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(axaddr_offset_0[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[36]),
.I3(Q[4]),
.I4(Q[35]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\axlen_cnt[3]_i_3__0
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(\m_payload_i[52]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[52]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(\axaddr_offset_r_reg[3] ),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hFF0F553300000000))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[36]),
.I5(Q[2]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h503F5F3F00000000))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[36]),
.I3(Q[35]),
.I4(Q[42]),
.I5(Q[4]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(\wrap_cnt_r_reg[2] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(\wrap_cnt_r_reg[3] [0]));
LUT3 #(
.INIT(8'h6A))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAFFEA))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r_reg[3]_1 ),
.I1(\axlen_cnt_reg[3] ),
.I2(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\wrap_cnt_r[3]_i_5__0_n_0 ),
.I5(\axaddr_offset_r_reg[2]_1 ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT4 #(
.INIT(16'hFFDF))
\wrap_cnt_r[3]_i_5__0
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\state_reg[1]_rep_0 ),
.O(\wrap_cnt_r[3]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h0001000000010001))
\wrap_second_len_r[0]_i_2__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset_0[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hF00EFFFFF00E0000))
\wrap_second_len_r[1]_i_1__0
(.I0(axaddr_offset_0[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(axaddr_offset_0[0]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hCCC2FFFFCCC20000))
\wrap_second_len_r[2]_i_1__0
(.I0(axaddr_offset_0[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(axaddr_offset_0[0]),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\wrap_second_len_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset_0[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [3]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\wrap_second_len_r[3]_i_2__0
(.I0(\axlen_cnt_reg[3] ),
.I1(\wrap_second_len_r[3]_i_3__0_n_0 ),
.I2(Q[36]),
.I3(Q[5]),
.I4(Q[35]),
.I5(Q[6]),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[3]_i_3__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[3]),
.O(\wrap_second_len_r[3]_i_3__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_17_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
\axlen_cnt_reg[3] ,
Q,
axaddr_incr,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
\axaddr_offset_r_reg[0] ,
axaddr_offset,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[1] ,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_awvalid,
b_push,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output [11:0]axaddr_incr;
output [1:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output \axaddr_offset_r_reg[0] ;
output [1:0]axaddr_offset;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [1:0]\state_reg[1] ;
input [3:0]S;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_awvalid;
input b_push;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]E;
wire [1:0]D;
wire [0:0]E;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire [11:0]axaddr_incr;
wire \axaddr_incr[3]_i_4_n_0 ;
wire \axaddr_incr[3]_i_5_n_0 ;
wire \axaddr_incr[3]_i_6_n_0 ;
wire \axaddr_incr_reg[11]_i_3_n_1 ;
wire \axaddr_incr_reg[11]_i_3_n_2 ;
wire \axaddr_incr_reg[11]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_2_n_0 ;
wire \axaddr_incr_reg[3]_i_2_n_1 ;
wire \axaddr_incr_reg[3]_i_2_n_2 ;
wire \axaddr_incr_reg[3]_i_2_n_3 ;
wire \axaddr_incr_reg[7]_i_2_n_0 ;
wire \axaddr_incr_reg[7]_i_2_n_1 ;
wire \axaddr_incr_reg[7]_i_2_n_2 ;
wire \axaddr_incr_reg[7]_i_2_n_3 ;
wire [1:0]axaddr_offset;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[3]_i_2_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[2] ;
wire [0:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[2]_1 ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [61:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_5_n_0 ;
wire \wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire \wrap_second_len_r[3]_i_3_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3
(.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[11:8]),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }),
.O(axaddr_incr[3:0]),
.S(S));
CARRY4 \axaddr_incr_reg[7]_i_2
(.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[7:4]),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[36]),
.I3(Q[1]),
.I4(Q[35]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[1]_i_2_n_0 ),
.I1(Q[40]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[36]),
.I3(Q[3]),
.I4(Q[35]),
.I5(Q[2]),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r[3]_i_2_n_0 ),
.I1(Q[42]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [2]),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[36]),
.I3(Q[4]),
.I4(Q[35]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0020))
\axlen_cnt[3]_i_3
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_4
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hFF0F553300000000))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[36]),
.I5(Q[2]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h503F5F3F00000000))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[36]),
.I3(Q[35]),
.I4(Q[42]),
.I5(Q[4]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(\wrap_cnt_r_reg[2] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(D[0]));
LUT3 #(
.INIT(8'h6A))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_second_len_r_reg[3] [1]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAFFEA))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\axlen_cnt_reg[3] ),
.I2(\axaddr_offset_r[3]_i_2_n_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\wrap_cnt_r[3]_i_5_n_0 ),
.I5(\axaddr_offset_r_reg[2]_1 ),
.O(\wrap_cnt_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\wrap_cnt_r[3]_i_5
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\wrap_cnt_r[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0001000000010001))
\wrap_second_len_r[0]_i_2
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3] [2]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hF00EFFFFF00E0000))
\wrap_second_len_r[1]_i_1
(.I0(axaddr_offset[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(axaddr_offset[0]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hCCC2FFFFCCC20000))
\wrap_second_len_r[2]_i_1
(.I0(axaddr_offset[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(axaddr_offset[0]),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\wrap_second_len_r[3]_i_1
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [3]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\wrap_second_len_r[3]_i_2
(.I0(\axlen_cnt_reg[3] ),
.I1(\wrap_second_len_r[3]_i_3_n_0 ),
.I2(Q[36]),
.I3(Q[5]),
.I4(Q[35]),
.I5(Q[6]),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[3]_i_3
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[3]),
.O(\wrap_second_len_r[3]_i_3_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_17_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_17_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[2]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[2]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[2]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[4]_i_4
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[2]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "gcd_block_design_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module stage1 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/bachelors.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/bachelors.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/bachelors.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:33:56 03/10/2016
// Design Name: Top
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab6/test_isim_top.v
// Project Name: lab6
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_isim_top;
// Inputs
reg CLOCK_IN;
reg RESET;
reg [2:0] SWITCH;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.CLOCK_IN(CLOCK_IN),
.RESET(RESET),
.SW(SWITCH),
.LED(LED)
);
always #10 CLOCK_IN = ~CLOCK_IN;
initial begin
// Initialize Inputs
CLOCK_IN = 0;
RESET = 1;
SWITCH = 2'b001;
// Wait 100 ns for global reset to finish
#120;
// Add stimulus here
RESET = 0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_SYMBOL_V
`define SKY130_FD_SC_LP__NOR2_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_SYMBOL_V
`define SKY130_FD_SC_HD__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_SYMBOL_V
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "FIFO.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/FIFO.sdf",fifo_cb,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
// Push...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd231;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
// Pop
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd145;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd24; // Empty
// Pop more
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
// Push
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
// Push and Pop
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd1;
d_in=8'd201;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd72;
// DO NOT PUSH NOR POP
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd82;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd58;
#10 // FULL
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd238;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd125;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Simulated Memory */
`include "consts.vh"
module mem (
input clk,
input reset,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
);
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory [MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
initial begin
/* Loads by word addresses. Address 0x302c corresponds to 0x0c0b. */
$readmemh("mem.hex", memory);
end
always @ (*) begin
if (enable && cmd == `MEM_CMD_READ) begin
load_data = memory[word_addr];
valid = 1;
end else begin
load_data = 32'b0;
valid = 0;
end
end
wire [31:0] expanded_mask = {mask[3] ? 8'hFF : 8'h00,
mask[2] ? 8'hFF : 8'h00,
mask[1] ? 8'hFF : 8'h00,
mask[0] ? 8'hFF : 8'h00};
wire [31:0] to_be_written = (memory[word_addr] & ~expanded_mask) | (write_data & expanded_mask);
always @ (*) begin
if (enable && cmd == `MEM_CMD_WRITE) begin
memory[word_addr] = to_be_written;
end
end
endmodule
|
`include "system.v"
module hdmi_video (
input CLOCK_50_i,
input reset_i,
output hdmi_clk_o,
output hdmi_de_o,
output hdmi_vs_o,
output hdmi_hs_o,
output [23:0] hdmi_d_o,
output [15:0] a_o,
output vram_clk_o,
input [23:0] color_dat_i,
output [2:0] video_pixel_o,
output border_o,
input [15:0] video_offset_i
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire inDisplayArea;
reg [10:0] CounterX = 0;
reg [9:0] CounterY = 0;
// These are actual pixel cursors res 800x600
wire [9:0] cursorx;
wire [9:0] cursory;
wire [9:0] bitmapx;
wire [9:0] bitmapy;
wire inbitmap_area;
//=======================================================
// Combinational logic
//=======================================================
// if in bitmap area, show blue, if border area show green, else nothing
assign hdmi_d_o = { (inDisplayArea) ? color_dat_i : 24'd0 };
assign hdmi_de_o = inDisplayArea;
assign hdmi_hs_o = (CounterX >= 128) || (CounterY < 4) ; // change this value to move the display horizontally
assign hdmi_vs_o = (CounterY >= 4); // change this value to move the display vertically
assign inDisplayArea = (CounterX >= 216) && (CounterX < 1016) && (CounterY >= 27) && (CounterY < 627);
// These are actual pixel cursors res 800x600
assign cursorx = (inDisplayArea) ? CounterX - 10'd216 : 1'b0;
assign cursory = (inDisplayArea) ? CounterY - 10'd27 : 1'b0;
// Now work out if we're in the bitmapped area or border area
assign inbitmap_area = (cursorx >= 80) && (cursorx < 719) && (cursory >= 100) && (cursory < 500);
// What's our position in the bitmap area
assign bitmapx = (inbitmap_area) ? cursorx - 10'd80 : 10'd0;
assign bitmapy = (inbitmap_area) ? cursory - 10'd100 : 10'd0;
// Calculate our ram address
// Offset + (raster row offset 0-7 X h800) + line 0-200 * 80 + X (excluding bit positions)
wire [13:0] rastercalc = video_offset_i[10:0] + (bitmapy[3:1] << 11) + (bitmapy[9:4] * 7'd80) + bitmapx[9:3];
assign a_o = {video_offset_i[15:14], rastercalc};
// Send pixel number within video data byte
assign video_pixel_o = bitmapx[2:0];
// Send border signal
assign border_o = (inDisplayArea) && !(inbitmap_area);
//=======================================================
// Simulation control
//=======================================================
`ifndef SIMULATION
wire video_clock;
wire vram_clock;
// PLL - gives us various clocks from 50MHz
hdmi_clock video_clk(
.inclk0( CLOCK_50_i ),
.areset( reset_i ), // reset.reset
.c0(video_clock), // outclk0.clk
.c1(vram_clock) // outclk1.clk 4x video clock, so after 2 clocks data is available for strobe in
);
`else
// 40MHz clock
reg video_clock = 0;
reg vram_clock = 0;
always begin
#12 video_clock <= 1;
#24 video_clock <= 0;
end
// 120MHz clock
always begin
#4 vram_clock <= 1;
#4 vram_clock <= 0;
#4 vram_clock <= 1;
#5 vram_clock <= 0;
#4 vram_clock <= 1;
#4 vram_clock <= 0;
end
`endif
assign hdmi_clk_o = video_clock;
assign vram_clk_o = vram_clock;
//=======================================================
// Structural coding
//=======================================================
wire CounterXmaxed = (CounterX==11'd1055);
always @(posedge video_clock)
CounterX <= (CounterXmaxed) ? 11'd0 : CounterX + 1'b1;
always @(posedge video_clock)
if(CounterXmaxed) CounterY <= (CounterY == 627) ? 10'd0 : CounterY + 1'b1;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
//---------------------------------------------------------------------//
// Name: value_membank.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Memory bank for storing stock value. On pulse to start_init,
// the memory initializes to zero, sending a pulse on done_init when
// finished.
//---------------------------------------------------------------------//
module value_membank(
clk,
nrst,
wren,
rdaddr,
wraddr,
start_init,
done_init,
c0_in,
c1_in,
c2_in,
c3_in,
c0_out,
c1_out,
c2_out,
c3_out
);
input clk;
input nrst;
input wren;
input start_init; // Pulse
input [9:0] rdaddr;
input [9:0] wraddr;
input [63:0] c0_in;
input [63:0] c1_in;
input [63:0] c2_in;
input [63:0] c3_in;
output [63:0] c0_out;
output [63:0] c1_out;
output [63:0] c2_out;
output [63:0] c3_out;
output done_init; // Pulse
//---------------------------------------------------------------------//
// Wires and Regs
//---------------------------------------------------------------------//
reg [63:0] buffer0;
reg [63:0] buffer1;
reg [63:0] buffer2;
reg [63:0] buffer3;
reg [10:0] timer1;
reg [1:0] state;
wire t1_expire = timer1[10];
wire init = !t1_expire;
wire [9:0] mem_wraddr = init ? timer1[9:0] : wraddr;
wire mem_wren = init || wren;
wire done_init = state[1];
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
mem_1k c0_mem_1k(
.data(init ? 64'd0 : c0_in),
.rdaddress(rdaddr),
.rdclock(clk),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c0_out)
);
mem_1k c1_mem_1k(
.data(init ? 64'd0 : c1_in),
.rdaddress(rdaddr),
.rdclock(clk),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c1_out)
);
mem_1k c2_mem_1k(
.rdclock(clk),
.data(init ? 64'd0 : c2_in),
.rdaddress(rdaddr),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c2_out)
);
mem_1k c3_mem_1k(
.data(init ? 64'd0 : c3_in),
.rdaddress(rdaddr),
.rdclock(clk),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c3_out)
);
//---------------------------------------------------------------------//
// Control Logic
//---------------------------------------------------------------------//
// Timer T1
// - Count down from 1027 or other set value to -1.
// - Timer value is used as initialization address.
// - Loads on 'start_init' pulse.
// - Stops when reaches -1.
always@(posedge clk)
if(!nrst) timer1 <= -1;
else if(start_init) timer1 <= 11'b01111111111;
else if(!t1_expire) timer1 <= timer1 - 1;
// State machine to pulse 'done_init' when finished.
always@(posedge clk)
if(!nrst) state <= 2'b00;
else if(start_init) state <= 2'b01;
else if((state == 2'b01) && t1_expire) state <= 2'b10;
else if(state == 2'b10) state <= 2'b00;
endmodule |
module servo(clk, rst, rs232_in, rs232_in_stb, rs232_in_ack, rs232_out, servos, rs232_out_stb, servos_stb, rs232_out_ack, servos_ack);
input clk;
input rst;
input [15:0] rs232_in;
input rs232_in_stb;
output rs232_in_ack;
output [15:0] rs232_out;
output rs232_out_stb;
input rs232_out_ack;
output [15:0] servos;
output servos_stb;
input servos_ack;
wire [15:0] wire_140036826114168;
wire wire_140036826114168_stb;
wire wire_140036826114168_ack;
servo_ui servo_ui_32237832(
.clk(clk),
.rst(rst),
.input_rs232(rs232_in),
.input_rs232_stb(rs232_in_stb),
.input_rs232_ack(rs232_in_ack),
.output_control(wire_140036826114168),
.output_control_stb(wire_140036826114168_stb),
.output_control_ack(wire_140036826114168_ack),
.output_rs232(rs232_out),
.output_rs232_stb(rs232_out_stb),
.output_rs232_ack(rs232_out_ack));
servo_controller servo_controller_32246024(
.clk(clk),
.rst(rst),
.input_control(wire_140036826114168),
.input_control_stb(wire_140036826114168_stb),
.input_control_ack(wire_140036826114168_ack),
.output_servos(servos),
.output_servos_stb(servos_stb),
.output_servos_ack(servos_ack));
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_dataid_manager
# (
parameter
CFG_DATA_ID_WIDTH = 8,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 1,
CFG_TBP_NUM = 4,
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_BE_ALLLOW_RMW = 0
)
(
// clock & reset
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
// update cmd interface
update_cmd_if_ready,
update_cmd_if_valid,
update_cmd_if_data_id,
update_cmd_if_burstcount,
update_cmd_if_tbp_id,
// update data interface
update_data_if_valid,
update_data_if_data_id,
update_data_if_data_id_vector,
update_data_if_burstcount,
update_data_if_next_burstcount,
// notify burstcount consumed interface
notify_data_if_valid,
notify_data_if_burstcount,
// notify data ready interface (TBP)
notify_tbp_data_ready,
notify_tbp_data_partial_be,
// buffer write address generate interface
write_data_if_ready,
write_data_if_valid,
write_data_if_accepted,
write_data_if_address,
write_data_if_partial_be,
write_data_if_allzeros_be,
// buffer read addresss generate interface
read_data_if_valid,
read_data_if_data_id,
read_data_if_data_id_vector,
read_data_if_valid_first,
read_data_if_data_id_first,
read_data_if_data_id_vector_first,
read_data_if_valid_first_vector,
read_data_if_valid_last,
read_data_if_data_id_last,
read_data_if_data_id_vector_last,
read_data_if_address,
read_data_if_datavalid,
read_data_if_done
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
// clock & reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input cfg_enable_ecc;
input cfg_enable_auto_corr;
input cfg_enable_no_dm;
// update cmd interface
output update_cmd_if_ready;
input update_cmd_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
input [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
input [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
// update data interface
input update_data_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
input [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
output notify_data_if_valid;
output [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
// notify tbp interface
output [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
output notify_tbp_data_partial_be;
// buffer write address generate interface
output write_data_if_ready;
input write_data_if_valid;
output write_data_if_accepted;
output [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
input write_data_if_partial_be;
input write_data_if_allzeros_be;
// read data interface
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
input read_data_if_valid_first;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_first;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid_first_vector;
input read_data_if_valid_last;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_last;
output [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
output [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
output read_data_if_done;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_enable_no_dm;
// update cmd interface
wire update_cmd_if_ready;
wire update_cmd_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
wire [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
reg [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount_r;
wire [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address_r;
// update data interface
wire update_data_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
wire notify_data_if_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_notify_data_if_valid;
reg [CFG_INT_SIZE_WIDTH-1:0] mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
// dataid array
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0]; // mano - this should be CFG_INT_SIZE_WIDTH?
reg [CFG_TBP_NUM-1:0] dataid_array_tbp_id [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_dataid_array_done;
// notify tbp interface
wire [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
reg notify_tbp_data_partial_be;
reg [CFG_TBP_NUM-1:0] mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] tbp_data_ready_r;
// buffer write address generate interface
reg write_data_if_ready;
wire write_data_if_valid;
wire write_data_if_accepted;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_nextaddress;
wire write_data_if_partial_be;
wire write_data_if_allzeros_be;
// read data interface
wire [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
reg [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
wire [CFG_INT_SIZE_WIDTH-1:0] read_data_if_burstcount; // used in assertion check
reg [CFG_BUFFER_ADDR_WIDTH-1:0] mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
wire read_data_if_done;
reg write_data_if_address_blocked;
// -----------------------------
// signal declaration
// -----------------------------
reg cfg_enable_partial_be_notification;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount_2x;
wire update_cmd_if_accepted;
reg update_cmd_if_accepted_r;
wire update_cmd_if_address_blocked;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress_r;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextmaxaddress;
reg update_cmd_if_nextmaxaddress_wrapped; // nextmaxaddress has wrapped around buffer max address
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_unnotified_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_next_unnotified_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_write_data_if_address_blocked;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_update_cmd_if_address_blocked;
reg mux_update_cmd_if_address_blocked_q1;
reg mux_update_cmd_if_address_blocked_q2;
reg mux_update_cmd_if_address_blocked_q3;
reg mux_update_cmd_if_address_blocked_q4;
// error debug signals - used in assertions
reg err_dataid_array_overwritten;
reg err_dataid_array_invalidread;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter; // increments on data write, decrements on data read
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_cmd_unallocated_counter; // increments by cmd burstcount on update cmd, decrements on data read
reg buffer_valid_counter_full;
reg err_buffer_valid_counter_overflow;
reg err_buffer_cmd_unallocated_counter_overflow;
reg partial_be_detected;
reg partial_be_when_no_cmd_tracked;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_greatereq;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_same;
wire update_data_bc_gt_update_cmd_unnotified_bc;
wire burstcount_list_read;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_read_data;
wire burstcount_list_read_data_valid;
wire burstcount_list_write;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_write_data;
reg update_data_if_burstcount_greatereq_burstcount_list;
reg update_data_if_burstcount_same_burstcount_list;
integer k;
// -----------------------------
// module definition
// -----------------------------
always @ (*)
begin
cfg_enable_partial_be_notification = cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
always @ (*)
begin
cfg_max_cmd_burstcount = cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x = 2 * cfg_max_cmd_burstcount;
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
// Burst count list to keep track of burst count value,
// to be used for comparison with burst count value from burst tracking logic
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
// dataid_array management
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
// update cmd, update data & read data will not happen on same cycle
// update cmd interface
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
// update data interface
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
// read data interface
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
// mux to generate signals from output of dataid_array
// 1. notify TBP that data is ready to be read
// 2. notify other blocks burstcount consumed by dataid_array entry
// 3. generate read data address
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= mux_update_cmd_if_address_blocked_q1 | mux_update_cmd_if_address_blocked_q2 | mux_update_cmd_if_address_blocked_q3 | mux_update_cmd_if_address_blocked_q4;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
mux_update_cmd_if_address_blocked_q1 <= 0;
mux_update_cmd_if_address_blocked_q2 <= 0;
mux_update_cmd_if_address_blocked_q3 <= 0;
mux_update_cmd_if_address_blocked_q4 <= 0;
end
else
begin
mux_update_cmd_if_address_blocked_q1 <= |mux_update_cmd_if_address_blocked[(CFG_DATAID_ARRAY_DEPTH-1):(CFG_DATAID_ARRAY_DEPTH/4*3)];
mux_update_cmd_if_address_blocked_q2 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4*3)-1):(CFG_DATAID_ARRAY_DEPTH/2)];
mux_update_cmd_if_address_blocked_q3 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/2)-1):(CFG_DATAID_ARRAY_DEPTH/4)];
mux_update_cmd_if_address_blocked_q4 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4)-1):0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one afi_wlat group
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
// Read data address list, to keep track of read address to different write data buffer group
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
// address generation for data location in buffer
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_accepted_r <= 0;
update_cmd_if_address_r <= 0;
update_cmd_if_nextaddress_r <= 0;
end
else
begin
update_cmd_if_accepted_r <= update_cmd_if_accepted;
update_cmd_if_address_r <= update_cmd_if_address;
update_cmd_if_nextaddress_r <= update_cmd_if_nextaddress;
end
end
always @ (*)
begin
if (update_cmd_if_accepted_r)
begin
update_cmd_if_address = update_cmd_if_nextaddress_r;
end
else
begin
update_cmd_if_address = update_cmd_if_address_r;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
always @ (*)
begin
update_cmd_if_nextmaxaddress = update_cmd_if_address + cfg_max_cmd_burstcount_2x;
end
always @ (*)
begin
if (update_cmd_if_address > update_cmd_if_nextmaxaddress)
begin
update_cmd_if_nextmaxaddress_wrapped = 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped = 1'b0;
end
end
// un-notified burstcount counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_next_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_next_unnotified_burstcount <= update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_burstcount_r <= 0;
end
else
begin
update_cmd_if_burstcount_r <= update_cmd_if_burstcount;
end
end
always @ (*)
begin
if (update_cmd_if_accepted_r)
begin
update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount + update_cmd_if_burstcount_r;
end
else
begin
update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount;
end
end
// currently buffer_cmd_unallocated_counter only used for debug purposes
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
// write only
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
// read only
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
assign update_cmd_if_ready = ~update_cmd_if_address_blocked;
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
write_data_if_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
// if cfg_enable_partial_be_notification, de-assert write read if partial be detected, and we have no commands being tracked currently
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0}) // when valid counter is counting up to all_ones
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
// partial be generation logic
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
generate
if (CFG_ECC_BE_ALLLOW_RMW) begin
reg detect_all_zeros_be;
reg detect_all_ones_be;
reg detect_partial_write_be;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
detect_all_zeros_be <= 1'b0;
detect_partial_write_be <= 1'b0;
detect_all_ones_be <= 1'b0;
end
else begin
if (write_data_if_accepted & write_data_if_allzeros_be)
begin
detect_all_zeros_be <= 1'b1;
end
else if (write_data_if_accepted & ~write_data_if_partial_be & ~write_data_if_allzeros_be)
begin
detect_all_ones_be <= 1'b1;
end
else if (write_data_if_accepted & write_data_if_partial_be)
begin
detect_partial_write_be <= 1'b1;
end
else if (|update_data_if_burstcount_same)
begin
detect_all_zeros_be <= 1'b0;
detect_partial_write_be <= 1'b0;
detect_all_ones_be <= 1'b0;
end
end
end
always @ (*)
begin
if (|update_data_if_burstcount_same)
begin
if (detect_partial_write_be)
begin
partial_be_detected = 1'b1;
end
else if (detect_all_zeros_be & ~detect_all_ones_be)
begin
partial_be_detected = 1'b1;
end
else
begin
partial_be_detected = 1'b0;
end
end
else
begin
partial_be_detected = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
end
end
end
else begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
end
endgenerate
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
// Net declarations
wire dp;
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (we));
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
/*
defparam ram.INIT_00 = 256'h31303938373635343332313039383736_35343332313039383736353433323130;
defparam ram.INIT_01 = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_02 = 256'h3139383736353433323130393837363534;
defparam ram.INIT_03 = 256'h43000000;
defparam ram.INIT_05 = 256'h32;
defparam ram.INIT_07 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_0A = 256'h34;
defparam ram.INIT_0C = 256'h3500000000000000000000000000000000;
defparam ram.INIT_0F = 256'h36;
defparam ram.INIT_11 = 256'h3700000000000000000000000000000000;
defparam ram.INIT_14 = 256'h38;
defparam ram.INIT_16 = 256'h3900000000000000000000000000000000;
defparam ram.INIT_19 = 256'h30;
defparam ram.INIT_1B = 256'h3100000000000000000000000000000000;
defparam ram.INIT_1E = 256'h32;
defparam ram.INIT_20 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_23 = 256'h34;
defparam ram.INIT_25 = 256'h3500000000000000000000000000000000;
defparam ram.INIT_28 = 256'h36;
defparam ram.INIT_2A = 256'h3700000000000000000000000000000000;
defparam ram.INIT_2D = 256'h38;
defparam ram.INIT_2F = 256'h3900000000000000000000000000000000;
defparam ram.INIT_32 = 256'h30;
defparam ram.INIT_34 = 256'h3100000000000000000000000000000000;
defparam ram.INIT_37 = 256'h32;
defparam ram.INIT_39 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_3C = 256'h31303938373635343332313039383736_35343332313039383736353433323134;
defparam ram.INIT_3D = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_3E = 256'h35343332313039383736353433323130_39383736353433323130393837363534;
defparam ram.INIT_3F = 256'h37363534333231303938373635343332_31303938373635343332313039383736;
*/
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFRBP_PP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_BEHAVIORAL_PP_V |
// Texas A&M University //
// cpsc350 Computer Architecture //
//Alan Achtenberg??
//Project 2//
`define OPCODE_ADD 6'b000000
`define OPCODE_SUB 6'b000000
`define OPCODE_ADDU 6'b000000
`define OPCODE_SUBU 6'b000000
`define OPCODE_AND 6'b000000
`define OPCODE_OR 6'b000000
`define OPCODE_SLL 6'b000000
`define OPCODE_SRA 6'b000000
`define OPCODE_SRL 6'b000000
`define OPCODE_SLT 6'b000000
`define OPCODE_SLTU 6'b000000
`define OPCODE_XOR 6'b000000
`define OPCODE_JR 6'b000000
//I-Type (All opcodes except 000000, 00001x, and 0100xx)
`define OPCODE_ADDI 6'b001000
`define OPCODE_ADDIU 6'b001001
`define OPCODE_ANDI 6'b001100
`define OPCODE_BEQ 6'b000100
`define OPCODE_BNE 6'b000101
`define OPCODE_BLEZ 6'b000110
`define OPCODE_BLTZ 6'b000001
`define OPCODE_ORI 6'b001101
`define OPCODE_XORI 6'b001110
`define OPCODE_NOP 6'b110110
`define OPCODE_LUI 6'b001111
`define OPCODE_SLTI 6'b001010
`define OPCODE_SLTIU 6'b001011
`define OPCODE_LB 6'b100000
`define OPCODE_LW 6'b100011
`define OPCODE_SB 6'b101000
`define OPCODE_SW 6'b101011
// J-Type (Opcode 00001x)
`define OPCODE_J 6'b000010
`define OPCODE_JAL 6'b000011
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
// Top Level Architecture Model //
`include "Control.v"
`include "IdealMemory.v"
`include "PC.v"
`include "RegisterFile.v"
`include "mux.v"
`include "ALU_bhav.v"
`include "signextend.v"
`include "ALUControl.v"
/*-------------------------- CPU -------------------------------
* This module implements a single-cycle
* CPU similar to that described in the text book
* (for example, see Figure 5.19).
*
*/
//
// Input Ports
// -----------
// clock - the system clock (m555 timer).
//
// reset - when asserted by the test module, forces the processor to
// perform a "reset" operation. (note: to reset the processor
// the reset input must be held asserted across a
// negative clock edge).
//
// During a reset, the processor loads an externally supplied
// value into the program counter (see startPC below).
//
// startPC - during a reset, becomes the new contents of the program counter
// (starting address of test program).
//
// Output Port
// -----------
// dmemOut - contains the data word read out from data memory. This is used
// by the test module to verify the correctness of program
// execution.
//-------------------------------------------------------------------------
module SingleCycleProc(CLK, Reset_L, startPC, dmemOut);
input Reset_L, CLK;
input [31:0] startPC;
output [31:0] dmemOut;
wire [31:0] PC;
wire [31:0] Instr;
//
// INSERT YOUR CPU MODULES HERE
ProgramCounter PC1(PC, PC, Reset_L, startPC,CLK);
InstrMem IM1(PC, Instr);
wire RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend;
wire [3:0]ALUOp;
Control_Unit C1(RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend, ALUOp, Instr[31:26]);
wire [3:0] ALUctrl;
ALUControl AC1(ALUctrl, ALUOp,Instr[5:0]);
wire [4:0] Waddr;
MUX5_2to1 mux1(Instr[20:16], Instr[15:11], RegDst, Waddr );
wire [31:0]Read1, Read2, Writedata;
RegisterFile RF1(Read1, Read2, Writedata, Instr[25:21],Instr[20:16], Waddr, RegWrite, CLK, Reset_L);
wire [31:0]Immediate; //Sign extended value
SIGN_EXTEND SE1(Instr[15:0], Immediate);
wire [31:0] ALUin, Result; //
wire Zero;
MUX32_2to1 mux2(Read2, Immediate, ALUSrc, ALUin);
ALU_behav ALU1( Read1, ALUin, ALUctrl, Writedata, Overflow, 1'b0, Carry_out, Zero );
//
// Debugging
//
/*
always @(RegDst or Waddr)
begin
$display("RegDst %b Waddr %d" , RegDst, Waddr );
end
*/
//Monitor changes in the program counter
/* always @(PC)
begin
#10 $display($time," PC=%d Instr: op=%d rs=%d rt=%d rd=%d imm16=%d funct=%d",
PC,Instr[31:26],Instr[25:21],Instr[20:16],Instr[15:11],Instr[15:0],Instr[5:0]);
end
*/
/* Monitors memory writes
always @(MemWrite)
begin
#1 $display($time," MemWrite=%b clock=%d addr=%d data=%d",
MemWrite, clock, dmemaddr, rportb);
end
*/
/*always @(Instr)
begin
#10 $display($time,"OPCODE=%b, ALUctrl=%b , ALUOp=%b", Instr[31:26],ALUctrl, ALUOp);
end
*/
endmodule // CPU
module m555 (CLK);
parameter StartTime = 0, Ton = 50, Toff = 50, Tcc = Ton+Toff; //
output CLK;
reg CLK;
initial begin
#StartTime CLK = 0;
end
// The following is correct if clock starts at LOW level at StartTime //
always begin
#Toff CLK = ~CLK;
#Ton CLK = ~CLK;
end
endmodule
module testCPU(Reset_L, startPC, testData);
input [31:0] testData;
output Reset_L;
output [31:0] startPC;
reg Reset_L;
reg [31:0] startPC;
initial begin
// Your program 1
Reset_L = 0; startPC = 0 * 4;
#101 // insures reset is asserted across negative clock edge
Reset_L = 1;
#1000; // allow enough time for program 1 to run to completion
Reset_L = 0;
// #1 $display ("Program 1: Result: %d", testData);
// Your program 2
//startPC = 14 * 4;
//#101 Reset_L = 1;
//#10000;
//Reset_L = 0;
//#1 $display ("Program 2: Result: %d", testData);
// etc.
// Run other programs here
$finish;
end
endmodule // testCPU
module TopProcessor;
wire reset, CLK, Reset_L;
wire [31:0] startPC;
wire [31:0] testData;
m555 system_clock(CLK);
SingleCycleProc SSProc(CLK, Reset_L, startPC, testData);
testCPU tcpu(Reset_L, startPC, testData);
endmodule // TopProcessor |
module ARM_CU_ALU_TestBench5;
parameter sim_time = 750*2; // Num of Cycles * 2
reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;
//module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
#1 Reset = 0;
join
always@(posedge MFA)begin
$display("MEMADD = %d", MEMADD);
if(READ_WRITE == 1) begin
case(MEMADD)
8'h00:begin
#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h04:begin
#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h08:begin
#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h0C:begin
#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h10:begin
#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h14:begin
#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h18:begin
#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h1C:begin
#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h20:begin
#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h24:begin
#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h28:begin
#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h2C:begin
#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
default:begin
#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
endcase
#5 MFC = 1 ;#7 MFC = 0 ;
end
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench5.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench5);
//$display(" Test Results" );
//$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
//iverilog ARM_ALU.v ARM_CU_ALU.v BarrelShifter.v Buffer32_32.v controlunit6.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU_TestBench5.v |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fifo_async_103x32 (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input wire rst;
input wire wr_clk;
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [102 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [102 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire prog_full;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(103),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(103),
.C_ENABLE_RLOCS(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(16),
.C_PROG_FULL_THRESH_NEGATE_VAL(15),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(5'B0),
.prog_empty_thresh_assert(5'B0),
.prog_empty_thresh_negate(5'B0),
.prog_full_thresh(5'B0),
.prog_full_thresh_assert(5'B0),
.prog_full_thresh_negate(5'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(prog_full),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRTP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:30:25 05/05/2013
// Design Name:
// Module Name: multplr
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multplr(input [5:0]X,Y, output reg [11:0] prdct );
wire [5:0] p1,p2,p3,p4,p5,p6;
partialprdct ppdct(X,Y,p1,p2,p3,p4,p5,p6);
/////////////////L0ha1s(lavel zero half adder 1 sum)
reg L0ha1s,L0ha1c,L0fa1s,L0fa1c,L0fa2s,L0fa2c,L0fa3s,L0fa3c,L0fa4s,L0fa4c,L0ha2s,L0ha2c;
/////////////////L1ha1s(lavel 1 half adder 1 sum)
reg L1ha1s,L1ha1c,L1fa1s,L1fa1c,L1fa2s,L1fa2c,L1fa3s,L1fa3c,L1fa4s,L1fa4c,L1ha2s,L1ha2c;
/////////////////L2ha1s(lavel 2 half adder 1 sum)
reg L2ha1s,L2ha1c,L2fa1s,L2fa1c,L2fa2s,L2fa2c,L2fa3s,L2fa3c,L2fa4s,L2fa4c,L2fa5s,L2fa5c;
/////////////////L3ha1s(lavel 3 half adder 1 sum)
reg L3ha1s,L3ha1c,L3ha2s,L3ha2c,L3fa1s,L3fa1c,L3fa2s,L3fa2c,L3fa3s,L3fa3c,L3ha3s,L3ha3c,L3ha4s,L3ha4c,L3ha5s,L3ha5c;
////////////////////ripple carry signals//////////
reg c1,c2,c3,c4,c5,c6,c7,c8;
///////////////////////Half Adders and Full Adders Layers//////////////////////////
////////////////////LAYER 0 adders///////////////////
always @* begin
hfaddr(p1[1],p2[0],L0ha1s,L0ha1c);
fuladdr( p1[2],p2[1],p3[0],L0fa1s,L0fa1c);
fuladdr( p1[3],p2[2],p3[1],L0fa2s,L0fa2c);
fuladdr( p1[4],p2[3],p3[2],L0fa3s,L0fa3c);
fuladdr(p1[5],p2[4],p3[3],L0fa4s,L0fa4c);
hfaddr(p2[5],p3[4],L0ha2s,L0ha2c);
////////////////////LAYER 1 adders///////////////////
hfaddr(p4[1],p5[0], L1ha1s,L1ha1c);
fuladdr( p4[2],p5[1],p6[0],L1fa1s,L1fa1c);
fuladdr( p4[3],p5[2],p6[1],L1fa2s,L1fa2c);
fuladdr( p4[4],p5[3],p6[2],L1fa3s,L1fa3c);
fuladdr( p4[5],p5[4],p6[3],L1fa4s,L1fa4c);
hfaddr(p5[5],p6[4],L1ha2s,L1ha2c);
////////////////////LAYER 2 adders///////////////////
hfaddr(L0ha1c,L0fa1s, L2ha1s,L2ha1c);
fuladdr( L0fa1c,L0fa2s,p4[0],L2fa1s,L2fa1c);
fuladdr( L0fa2c,L1ha1s,L0fa3s,L2fa2s,L2fa2c);
fuladdr( L0fa3c,L1fa1s,L0fa4s,L2fa3s,L2fa3c);
fuladdr( L0fa4c,L1fa2s,L0ha2s,L2fa4s,L2fa4c);
fuladdr( L0ha2c,L1fa3s,p3[5],L2fa5s,L2fa5c);
////////////////////LAYER 3 adders///////////////////
hfaddr(L2ha1c,L2fa1s, L3ha1s,L3ha1c);
hfaddr(L2fa1c,L2fa2s, L3ha2s,L3ha2c);
fuladdr( L2fa2c,L1ha1c,L2fa3s,L3fa1s,L3fa1c);
fuladdr( L2fa3c,L1fa1c,L2fa4s,L3fa2s,L3fa2c);
fuladdr( L2fa4c,L1fa2c,L2fa5s,L3fa3s,L3fa3c);
hfaddr(L2fa5c,L1fa4s, L3ha3s,L3ha3c);
hfaddr(L1fa4c,L1ha2s, L3ha4s,L3ha4c);
hfaddr(L1ha2c,p6[5], L3ha5s,L3ha5c);
//////Finally Carry propagate Adder//////////////////
prdct[0] = p1[0];
prdct[1] = L0ha1s;
prdct[2] = L2ha1s;
prdct[3] = L3ha1s;
hfaddr(L3ha1c,L3ha2s,prdct[4],c1);
fuladdr( c1,L3ha2c,L3fa1s,prdct[5],c2);
fuladdr( c2,L3fa1c,L3fa2s,prdct[6],c3);
fuladdr( c3,L3fa2c,L3fa3s,prdct[7],c4);
fuladdr( c4,L3fa3c,L3ha3s,prdct[8],c5);
fuladdr( c5,L3ha3c,L3ha4s,prdct[9],c6);
fuladdr( c6,L3ha4c,L3ha5s,prdct[10],c7);
hfaddr( c7,L3ha5c,prdct[11],c8);
end
/////////////////////half adder task////////////////////////
task hfaddr(input a,b,output x,y);
begin
x=a^b;
y=a&b;
end
endtask
/////////////////////Full Adder adder task////////////////////////
task fuladdr(input a,b,c,output x,y);
reg w1;
begin
w1 =(a^b);
x = w1^c;
y =(w1&c)|(a&b);
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_PP_SYMBOL_V
`define SKY130_FD_SC_MS__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_PP_SYMBOL_V
|
/*
File: mux4.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module mux4(/*AUTOARG*/
// Outputs
out,
// Inputs
in0, in1, in2, in3, sel0, sel1, sel2, sel3
);
parameter DW=99;
//data inputs
input [DW-1:0] in0;
input [DW-1:0] in1;
input [DW-1:0] in2;
input [DW-1:0] in3;
//select inputs
input sel0;
input sel1;
input sel2;
input sel3;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0]);
endmodule // mux4
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`define CRC_COUNT 8
module sdio_data_phy (
input clk,
input rst,
input i_posedge_stb,
input i_interrupt,
//Configuration
input i_ddr_en,
input i_spi_phy,
input i_sd1_phy,
input i_sd4_phy,
//Data Interface
input i_activate,
output reg o_finished,
input i_write_flag,
input [12:0] i_data_count,
output reg o_data_wr_stb,
output [7:0] o_data_wr_data,
input i_data_rd_stb,
input [7:0] i_data_rd_data,
output reg o_data_hst_rdy, //Host May not be ready
input i_data_com_rdy,
output reg o_data_crc_good,
//FPGA Platform Interface
output reg o_sdio_data_dir,
input [7:0] i_sdio_data_in,
output reg [7:0] o_sdio_data_out
);
//local parameters
localparam IDLE = 4'h0;
localparam START = 4'h1;
localparam WRITE = 4'h2;
localparam READ = 4'h3;
localparam CRC = 4'h4;
localparam WRITE_CRC = 4'h5;
localparam FINISHED = 4'h6;
localparam PROCESS_CRC = 4'h1;
//registes/wires
reg [3:0] state;
reg [3:0] crc_state;
reg [12:0] data_count;
wire data_crc_good;
reg [3:0] crc_bit;
wire [15:0] crc_out [0:3];
reg crc_rst;
wire crc_main_rst;
wire crc_main_en;
reg [15:0] host_crc [0:3];
wire [15:0] host_crc0;
wire [15:0] host_crc1;
wire [15:0] host_crc2;
wire [15:0] host_crc3;
wire [15:0] crc_out0;
wire [15:0] crc_out1;
wire [15:0] crc_out2;
wire [15:0] crc_out3;
reg [7:0] read_data;
reg [7:0] crc_data;
wire sdio_data1;
wire sdio_data2;
wire sdio_data3;
reg capture_crc;
reg enable_crc;
reg prev_clk_edge;
wire posege_clk;
reg buffered_read_stb;
reg [7:0] buffered_read_data;
integer i;
//submodules
genvar g;
generate
for (g = 0; g < 4; g = g + 1) begin : data_crc
/*
crc16 crc (
.clk (clk_x2 ),
.rst (crc_main_rst ),
.en (crc_main_en ),
.bit (crc_data[g] ),
.crc (crc_out[g] )
);
*/
crc16_2bit crc(
.clk (clk ),
.rst (crc_main_rst ),
.en (crc_main_en ),
.bit1 (crc_data[g] ),
.bit0 (crc_data[g + 4] ),
.crc (crc_out[g] )
);
end
endgenerate
//asynchronous logic
assign crc_main_rst = i_data_rd_stb ? 1'b0 : crc_rst;
assign crc_main_en = i_data_rd_stb ? 1'b1 : enable_crc;
assign crc_out0 = crc_out[0];
assign crc_out1 = crc_out[1];
assign crc_out2 = crc_out[2];
assign crc_out3 = crc_out[3];
assign host_crc0 = host_crc[0];
assign host_crc1 = host_crc[1];
assign host_crc2 = host_crc[2];
assign host_crc3 = host_crc[3];
assign o_data_wr_data= o_sdio_data_dir ? 8'h00 : i_sdio_data_in;
assign data_crc_good = ( (host_crc[0] == crc_out[0]) &&
(host_crc[1] == crc_out[1]) &&
(host_crc[2] == crc_out[2]) &&
(host_crc[3] == crc_out[3]));
reg top_flag;
//CRC State Machine
always @ (posedge clk) begin
if (rst) begin
crc_rst <= 1;
crc_state <= IDLE;
enable_crc <= 0;
crc_data <= 0;
top_flag <= 0;
end
else begin
case (crc_state)
IDLE: begin
crc_rst <= 1;
crc_data <= 0;
if (capture_crc) begin
top_flag <= 1;
crc_rst <= 0;
crc_state <= PROCESS_CRC;
enable_crc <= 1;
end
end
PROCESS_CRC: begin
if (i_write_flag) begin
crc_data[0] <= i_sdio_data_in[4'h3];
crc_data[1] <= i_sdio_data_in[4'h2];
crc_data[2] <= i_sdio_data_in[4'h1];
crc_data[3] <= i_sdio_data_in[4'h0];
crc_data[4] <= i_sdio_data_in[4'h7];
crc_data[5] <= i_sdio_data_in[4'h6];
crc_data[6] <= i_sdio_data_in[4'h5];
crc_data[7] <= i_sdio_data_in[4'h4];
end
else begin
//Read Flag
crc_data[0] <= i_data_rd_data[4'h3];
crc_data[1] <= i_data_rd_data[4'h3];
crc_data[2] <= i_data_rd_data[4'h1];
crc_data[3] <= i_data_rd_data[4'h0];
crc_data[4] <= i_data_rd_data[4'h7];
crc_data[5] <= i_data_rd_data[4'h6];
crc_data[6] <= i_data_rd_data[4'h5];
crc_data[7] <= i_data_rd_data[4'h4];
end
if (!capture_crc) begin
crc_state <= FINISHED;
enable_crc <= 0;
end
end
FINISHED: begin
if (state == IDLE) begin
crc_state <= IDLE;
end
end
endcase
top_flag <= ~top_flag;
end
end
always @ (posedge clk)begin
if (rst) begin
buffered_read_stb <= 1'b0;
buffered_read_data <= 8'h00;
end
else begin
buffered_read_stb <= i_data_rd_stb;
buffered_read_data <= i_data_rd_data;
end
end
always @ (posedge clk) begin
if (rst) begin
o_sdio_data_out <= 8'hFF;
end
else begin
o_sdio_data_out <= read_data;
end
end
always @ (posedge clk) begin
o_data_wr_stb <= 0;
if (rst) begin
o_data_crc_good <= 0;
state <= IDLE;
o_data_hst_rdy <= 0;
data_count <= 0;
o_sdio_data_dir <= 0;
capture_crc <= 0;
read_data <= 0;
o_finished <= 0;
for (i = 0; i < 4; i = i + 1) begin
host_crc[i] <= 0;
end
end
else begin
read_data <= i_data_rd_data;
case (state)
IDLE: begin
o_finished <= 0;
data_count <= 0;
if (i_interrupt) begin
o_sdio_data_dir <= 1;
read_data <= 8'hFD;
end
else begin
o_sdio_data_dir <= 0;
read_data <= 8'hFF;
end
o_data_hst_rdy <= 0;
if (i_activate) begin
o_sdio_data_dir <= 0;
o_data_crc_good <= 0;
for (i = 0; i < 4; i = i + 1) begin
host_crc[i] <= 0;
end
state <= START;
end
end
START: begin
read_data <= 8'hFF;
//$display ("sdio_data_phy: SD4 Transaction Started!");
if (i_write_flag) begin
o_data_hst_rdy <= 1;
if (i_sdio_data_in[0] == 0) begin
capture_crc <= 1;
state <= WRITE;
end
else begin
end
end
else begin
if (i_sdio_data_in[2]) begin
o_data_hst_rdy <= 1;
if (i_data_com_rdy) begin
//Both the data bus is ready and the host has not issued the wait signal
o_sdio_data_dir <= 1;
state <= READ;
end
end
end
if (!i_activate) begin
state <= IDLE;
end
end
WRITE: begin
o_data_wr_stb <= 1;
if (data_count == i_data_count - 1) begin
//capture_crc <= 0;
end
if (data_count < i_data_count) begin
data_count <= data_count + 1;
end
else begin
o_data_wr_stb <= 0;
capture_crc <= 0;
state <= CRC;
data_count <= 0;
//data_count <= data_count + 1;
host_crc[0] <= {host_crc[0][13:0], i_sdio_data_in[7], i_sdio_data_in[3]};
host_crc[1] <= {host_crc[1][13:0], i_sdio_data_in[6], i_sdio_data_in[2]};
host_crc[2] <= {host_crc[2][13:0], i_sdio_data_in[5], i_sdio_data_in[1]};
host_crc[3] <= {host_crc[3][13:0], i_sdio_data_in[4], i_sdio_data_in[0]};
end
//Cancel a Transaction
if (!i_activate) begin
state <= IDLE;
end
end
READ: begin
//Cancel a Transaction
if (i_data_rd_stb) begin
host_crc[0] <= crc_out[0];
host_crc[1] <= crc_out[1];
host_crc[2] <= crc_out[2];
host_crc[3] <= crc_out[3];
end
if (!i_activate) begin
state <= IDLE;
end
if (data_count < i_data_count) begin
if (!buffered_read_stb) begin
read_data <= 8'hFF;
end
if (i_data_rd_stb && !buffered_read_stb) begin
read_data <= 8'h00;
end
//Is there a read strobe?
if (buffered_read_stb) begin
//It's okay if we start capturing the CRC when data is 0, it will not modify the outcome
//Is this the first byte?
read_data <= buffered_read_data;
data_count <= data_count + 1;
end
end
if (data_count >= i_data_count) begin
capture_crc <= 0;
state <= WRITE_CRC;
data_count <= 0;
//if (data_count >= (i_data_count - 1)) begin
read_data <= {host_crc0[15], host_crc1[15], host_crc2[15], host_crc3[15],
host_crc0[14], host_crc1[14], host_crc2[14], host_crc3[14]};
host_crc[0] <= {host_crc[0][13:0], 2'b00};
host_crc[1] <= {host_crc[1][13:0], 2'b00};
host_crc[2] <= {host_crc[2][13:0], 2'b00};
host_crc[3] <= {host_crc[3][13:0], 2'b00};
end
end
CRC: begin
if (data_count < (`CRC_COUNT - 1)) begin
data_count <= data_count + 1;
host_crc[0] <= {host_crc[0][13:0], i_sdio_data_in[7], i_sdio_data_in[3]};
host_crc[1] <= {host_crc[1][13:0], i_sdio_data_in[6], i_sdio_data_in[2]};
host_crc[2] <= {host_crc[2][13:0], i_sdio_data_in[5], i_sdio_data_in[1]};
host_crc[3] <= {host_crc[3][13:0], i_sdio_data_in[4], i_sdio_data_in[0]};
end
else begin
state <= FINISHED;
end
end
WRITE_CRC: begin
if (data_count < `CRC_COUNT) begin
data_count <= data_count + 1;
read_data <= {host_crc[0][15], host_crc[1][15], host_crc[2][15], host_crc[3][15],
host_crc[0][14], host_crc[1][14], host_crc[2][14], host_crc[3][14]};
host_crc[0] <= {host_crc[0][13:0], 2'b00};
host_crc[1] <= {host_crc[1][13:0], 2'b00};
host_crc[2] <= {host_crc[2][13:0], 2'b00};
host_crc[3] <= {host_crc[3][13:0], 2'b00};
end
else begin
read_data <= 8'hFF;
state <= FINISHED;
end
end
FINISHED: begin
o_finished <= 1;
o_data_hst_rdy <= 0;
read_data <= 8'hFF;
o_sdio_data_dir <= 0;
o_data_crc_good <= data_crc_good;
if (!i_activate) begin
state <= IDLE;
end
end
default: begin
if (!i_activate) begin
state <= IDLE;
end
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_rfifo.v,v $
// Revision 1.4 2003/07/11 18:20:26 gorban
// added clearing the receiver fifo statuses on resets
//
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= #1 0;
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_128_134.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_128_134 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [133:0] data;
input [6:0] rdaddress;
input rden;
input [6:0] wraddress;
input wren;
output [133:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [133:0] q = sub_wire0[133:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({134{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 134,
altsyncram_component.width_b = 134,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "17152"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "134"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "134"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "134"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "134"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "134"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "134"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL "wraddress[6..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q_b 0 0 134 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_134_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:51:35 06/09/2014
// Design Name:
// Module Name: GrayCounter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GrayCounter(
input clk,
input incdec,
input stop,
input rst,
output [7:0] gray,
output [7:0] normal
);
parameter CLK_DIV = 17_000_000;
reg [31:0] clkDiv = 32'd0;
reg [7:0] curGray = 8'b0;
reg [7:0] curNum = 8'b0;
assign gray = curGray;
assign normal = curNum;
always @(posedge clk)
begin
// increment the clock divider
clkDiv = clkDiv + 1;
// reset and run control
if (rst == 1) begin
clkDiv = 0;
curNum = 8'b0;
end else if (stop == 1)
clkDiv = clkDiv - 1;
else if (clkDiv == CLK_DIV)
begin
// first, reset the clock divider
clkDiv = 0;
// use the inc/dec input
if (incdec == 1)
curNum = curNum + 1;
else
curNum = curNum - 1;
end
curGray = curNum ^ (curNum >> 1);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HS__AND4BB_PP_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_PP_SYMBOL_V
|
module Mealy (
output out,
input in,
input clk,
input reset_n
);
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
reg state, nextState;
reg out;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
state <= 0;
end else begin
state <= nextState;
end
end
always @(*) begin
case(state)
S0: begin
if (in == 0) begin
nextState <= S0;
out <= 0;
end else if (in == 1) begin
nextState <= S1;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
S1: begin
if (in == 0) begin
nextState <= S1;
out <= 0;
end else if (in == 1) begin
nextState <= S2;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
S2: begin
if (in == 0) begin
nextState <= S2;
out <= 0;
end else if (in == 1) begin
nextState <= S3;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
S3: begin
if (in == 0) begin
nextState <= S3;
out <= 0;
end else if (in == 1) begin
nextState <= S0;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
endcase
end
endmodule
|
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