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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_1_V
`define SKY130_FD_SC_LS__NAND4_1_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A222O_FUNCTIONAL_PP_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire B2 and2_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X , and1_out, and0_out, and2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4BB_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_BLACKBOX_V
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* REMINDER: Please do not put solutions to the exercises in
publicly accessible places. Thank you!! *)
Require Export Lists.
(* ################################################################# *)
(** * Polymorphism *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data). We begin with polymorphism. *)
(* ================================================================= *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.)
What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** (Side note on notation: In .v files, the "forall" quantifier is
spelled out in letters. In the generated HTML files, [forall] is
usually typeset as the usual mathematical "upside down A," but
you'll see the spelled-out "forall" in a few places, as in the
above comments. This is just a quirk of typesetting: there is no
difference in meaning.) *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've written [nil] and [cons] explicitly here because we haven't
yet defined the [ [] ] and [::] notations for the new version of
lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic versions of all the
list-processing functions that we wrote before. Here is [repeat],
for example: *)
Fixpoint repeat (X : Type) (x : X) (count : nat) : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat X x count')
end.
(** As with [nil] and [cons], we can use [repeat] by applying it
first to a type and then to its list argument: *)
Example test_repeat1 :
repeat nat 4 2 = cons nat 4 (cons nat 4 (nil nat)).
Proof. reflexivity. Qed.
(** To use [repeat] to build other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_repeat2 :
repeat bool false 1 = cons bool false (nil bool).
Proof. reflexivity. Qed.
Module MumbleGrumble.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
*)
(** [] *)
(**Compute(d (b a 5)).**)
Compute (d mumble (b a 5)).
Compute (d bool (b a 5)).
Compute (e bool true).
Compute (e mumble(b c 0)).
(**Compute (e bool (b c 0)).**)
Compute (c).
End MumbleGrumble.
(* ----------------------------------------------------------------- *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [repeat] again, but this time we
won't specify the types of any of the arguments. Will Coq still
accept it? *)
Fixpoint repeat' X x count : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat' X x count')
end.
(** Indeed it will. Let's see what type Coq has assigned to [repeat']: *)
Check repeat'.
(* ===> forall X : Type, X -> nat -> list X *)
Check repeat.
(* ===> forall X : Type, X -> nat -> list X *)
(** It has exactly the same type type as [repeat]. Coq was able
to use _type inference_ to deduce what the types of [X], [x], and
[count] must be, based on how they are used. For example, since
[X] is used as an argument to [cons], it must be a [Type], since
[cons] expects a [Type] as its first argument; matching [count]
with [0] and [S] means it must be a [nat]; and so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks, so we will continue to use them most of the time. You
should try to find a balance in your own code between too many
type annotations (which can clutter and distract) and too
few (which forces readers to perform type inference in their heads
in order to understand your code). *)
(* ----------------------------------------------------------------- *)
(** *** Type Argument Synthesis *)
(** To we use a polymorphic function, we need to pass it one or
more types in addition to its other arguments. For example, the
recursive call in the body of the [repeat] function above must
pass along the type [X]. But since the second argument to
[repeat] is an element of [X], it seems entirely obvious that the
first argument can only be [X] -- why should we have to write it
explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please try to figure out for yourself
what belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- indeed, the
two procedures rely on the same underlying mechanisms. Instead of
simply omitting the types of some arguments to a function, like
repeat' X x count : list X :=
we can also replace the types with [_]
repeat' (X : _) (x : _) (count : _) : list X :=
to tell Coq to attempt to infer the missing information.
Using implicit arguments, the [count] function can be written
like this: *)
Fixpoint repeat'' X x count : list X :=
match count with
| 0 => nil _
| S count' => cons _ x (repeat'' _ x count')
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference in both keystrokes and
readability is nontrivial. For example, suppose we want to write
down a list containing the numbers [1], [2], and [3]. Instead of
writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' :=
cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ----------------------------------------------------------------- *)
(** *** Implicit Arguments *)
(** We can go further and even avoid writing [_]'s in most cases by
telling Coq _always_ to infer the type argument(s) of a given
function. The [Arguments] directive specifies the name of the
function (or constructor) and then lists its argument names, with
curly braces around any arguments to be treated as implicit. (If
some arguments of a definition don't have a name, as is often the
case for constructors, they can be marked with a wildcard pattern
[_].) *)
Arguments nil {X}.
Arguments cons {X} _ _.
Arguments repeat {X} x count.
(** Now, we don't have to supply type arguments at all: *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
(** Alternatively, we can declare an argument to be implicit
when defining the function itself, by surrounding it in curly
braces. For example: *)
Fixpoint repeat''' {X : Type} (x : X) (count : nat) : list X :=
match count with
| 0 => nil
| S count' => cons x (repeat''' x count')
end.
(** (Note that we didn't even have to provide a type argument to the
recursive call to [repeat''']; indeed, it would be invalid to
provide one!)
We will use the latter style whenever possible, but we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. The reason for this is that marking the
parameter of an inductive type as implicit causes it to become
implicit for the type itself, not just for its constructors. For
instance, consider the following alternative definition of the
[list] type: *)
Inductive list' {X:Type} : Type :=
| nil' : list'
| cons' : X -> list' -> list'.
(** Because [X] is declared as implicit for the _entire_ inductive
definition including [list'] itself, we now have to write just
[list'] whether we are talking about lists of numbers or booleans
or anything else, rather than [list' nat] or [list' bool] or
whatever; this is a step too far. *)
(** Let's finish by re-implementing a few other standard list
functions on our new polymorphic lists... *)
Fixpoint app {X : Type} (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons h (app t l2)
end.
Fixpoint rev {X:Type} (l:list X) : list X :=
match l with
| nil => nil
| cons h t => app (rev t) (cons h nil)
end.
Fixpoint length {X : Type} (l : list X) : nat :=
match l with
| nil => 0
| cons _ l' => S (length l')
end.
Example test_rev1 :
rev (cons 1 (cons 2 nil)) = (cons 2 (cons 1 nil)).
Proof. reflexivity. Qed.
Example test_rev2:
rev (cons true nil) = cons true nil.
Proof. reflexivity. Qed.
Example test_length1: length (cons 1 (cons 2 (cons 3 nil))) = 3.
Proof. reflexivity. Qed.
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly just this time. For
example, suppose we write this: *)
Fail Definition mynil := nil.
(** (The [Fail] qualifier that appears before [Definition] can be
used with _any_ command, and is used to ensure that that command
indeed fails when executed. If the command does fail, Coq prints
the corresponding error message, but continues processing the rest
of the file.)
Here, Coq gives us an error because it doesn't know what type
argument to supply to [nil]. We can help it by providing an
explicit type declaration (so that Coq has more information
available when it gets to the "application" of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Complete the proofs below. *)
Theorem app_nil_r : forall (X:Type), forall l:list X,
l ++ [] = l.
Proof.
intros. induction l.
- reflexivity.
- simpl. rewrite -> IHl. reflexivity.
Qed.
Theorem app_assoc : forall A (l m n:list A),
l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros. induction l.
- reflexivity.
- simpl. rewrite -> IHl. reflexivity.
Qed.
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
intros. induction l1.
- reflexivity.
- simpl. rewrite -> IHl1. reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (more_poly_exercises) *)
(** Here are some slightly more interesting ones... *)
Theorem rev_app_distr: forall X (l1 l2 : list X),
rev (l1 ++ l2) = rev l2 ++ rev l1.
Proof.
intros. induction l1.
- simpl. rewrite -> app_nil_r. reflexivity.
- simpl. rewrite -> IHl1. rewrite -> app_assoc. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros. induction l.
- reflexivity.
- simpl. rewrite -> rev_app_distr. rewrite -> IHl. reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_, often called _products_: *)
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for product _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should only be used when parsing types. This avoids a clash with
the multiplication symbol.) *)
(** It is easy at first to get [(x,y)] and [X*Y] confused.
Remember that [(x,y)] is a _value_ built from two other values,
while [X*Y] is a _type_ built from two other types. If [x] has
type [X] and [y] has type [Y], then [(x,y)] has type [X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with
| (x, y) => x
end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with
| (x, y) => y
end.
(** The following function takes two lists and combines them
into a list of pairs. In other functional languages, it is often
called [zip]; we call it [combine] for consistency with Coq's
standard library. *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx, ly with
| [], _ => []
| _, [] => []
| x :: tx, y :: ty => (x, y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Compute (combine [1;2] [false;false;true;true]).
print? [] *)
Compute (combine [1;2] [false;false;true;true]).
Check combine.
(** **** Exercise: 2 stars, recommended (split) *)
(** The function [split] is the right inverse of [combine]: it takes a
list of pairs and returns a pair of lists. In many functional
languages, it is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit test. *)
Fixpoint split {X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([],[])
| (x,y) :: t => (x :: fst( split t), y :: snd(split t))
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
simpl. reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_,
which generalize [natoption] from the previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** We can now rewrite the [nth_error] function so that it works
with any type of lists. *)
Fixpoint nth_error {X : Type} (l : list X) (n : nat)
: option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else nth_error l' (pred n)
end.
Example test_nth_error1 : nth_error [4;5;6;7] 0 = Some 4.
Proof. reflexivity. Qed.
Example test_nth_error2 : nth_error [[1];[2]] 1 = Some [2].
Proof. reflexivity. Qed.
Example test_nth_error3 : nth_error [true] 2 = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_error_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_error] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_error {X : Type} (l : list X) : option X
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_error.
Example test_hd_error1 : hd_error [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_error2 : hd_error [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Functions as Data *)
(** Like many other modern programming languages -- including
all functional languages (ML, Haskell, Scheme, Scala, Clojure,
etc.) -- Coq treats functions as first-class citizens, allowing
them to be passed as arguments to other functions, returned as
results, stored in data structures, etc.*)
(* ================================================================= *)
(** ** Higher-Order Functions *)
(** Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Filter *)
(** Here is a more useful higher-order function, taking a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filtering" the list, returning a new list containing just
those elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Anonymous Functions *)
(** It is arguably a little sad, in the example just above, to
be forced to define the function [length_is_1] and give it a name
just to be able to pass it as an argument to [filter], since we
will probably never use it again. Moreover, this is not an
isolated example: when using higher-order functions, we often want
to pass as arguments "one-off" functions that we will never use
again; having to give each of these functions a name would be
tedious.
Fortunately, there is a better way. We can construct a function
"on the fly" without declaring it at the top level or giving it a
name. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** The expression [(fun n => n * n)] can be read as "the function
that, given a number [n], yields [n * n]." *)
(** Here is the [filter] example, rewritten to use an anonymous
function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list. *)
Definition partition {X : Type}
(test : X -> bool)
(l : list X)
: list X * list X
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X) : (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (fun x => plus 3 x) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same, since [map] takes _two_ type arguments, [X] and [Y]; it
can thus be applied to a list of numbers and a function from
numbers to booleans to yield a list of booleans: *)
Example test_map2:
map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a _list of lists_ of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, recommended (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y)
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ================================================================= *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y)
: Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Some more examples: *)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 :
fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 :
fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 :
fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ================================================================= *)
(** ** Functions That Construct Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as arguments. Let's look at some examples that
involve _returning_ functions as the results of other functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. This operator is _right-associative_, so the type of
[plus] is really a shorthand for [nat -> (nat -> nat)] -- i.e., it
can be read as saying that "[plus] is a one-argument function that
takes a [nat] and returns a one-argument function that takes
another [nat] and returns a [nat]." In the examples above, we
have always applied [plus] to both of its arguments at once, but
if we like we can supply just the first. This is called _partial
application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ################################################################# *)
(** * Additional Exercises *)
Module Exercises.
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
(** As a trivial example of the usefulness of currying, we can use it
to shorten one of the examples that we saw above: *)
Example test_map2: map (fun x => plus 3 x) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** Thought exercise: before running the following commands, can you
calculate the types of [prod_curry] and [prod_uncurry]? *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type)
(f : X -> Y -> Z)
x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (nth_error_informal) *)
(** Recall the definition of the [nth_error] function:
Fixpoint nth_error {X : Type} (l : list X) (n : nat) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else nth_error l' (pred n)
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @nth_error X l n = None
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
(** This exercise explores an alternative way of defining natural
numbers, using the so-called _Church numerals_, named after
mathematician Alonzo Church. We can represent a natural number
[n] as a function that takes a function [f] as a parameter and
returns [f] iterated [n] times. *)
Module Church.
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Iterating
a function once should be the same as just applying it. Thus: *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** Similarly, [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** Defining [zero] is somewhat trickier: how can we "apply a function
zero times"? The answer is actually simple: just return the
argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] can be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in
particular how the [doit3times] function we've defined previously
is actually just the Church representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number: *)
Definition succ (n : nat) : nat
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example succ_1 : succ zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example succ_2 : succ one = two.
Proof. (* FILL IN HERE *) Admitted.
Example succ_3 : succ two = three.
Proof. (* FILL IN HERE *) Admitted.
(** Addition of two natural numbers: *)
Definition plus (n m : nat) : nat
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example plus_1 : plus zero one = one.
Proof. (* FILL IN HERE *) Admitted.
Example plus_2 : plus two three = plus three two.
Proof. (* FILL IN HERE *) Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. (* FILL IN HERE *) Admitted.
(** Multiplication: *)
Definition mult (n m : nat) : nat
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example mult_1 : mult one one = one.
Proof. (* FILL IN HERE *) Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. (* FILL IN HERE *) Admitted.
Example mult_3 : mult two three = plus three three.
Proof. (* FILL IN HERE *) Admitted.
(** Exponentiation: *)
(** (_Hint_: Polymorphism plays a crucial role here. However,
choosing the right type to iterate over can be tricky. If you hit
a "Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic.) *)
Definition exp (n m : nat) : nat
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
End Church.
(** [] *)
End Exercises.
(** $Date: 2016-07-11 21:31:32 -0400 (Mon, 11 Jul 2016) $ *)
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:28:39 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire d_ff1_operation_out, d_ff_Yn_31_, d_ff3_sign_out, n281, n640, n641,
n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652,
n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674,
n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696,
n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707,
n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718,
n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729,
n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740,
n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751,
n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762,
n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n773,
n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784,
n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795,
n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806,
n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817,
n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828,
n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839,
n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850,
n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861,
n862, n863, n864, n865, n866, n867, n868, n869, n870, n871, n872,
n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883,
n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894,
n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905,
n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916,
n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927,
n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, n938,
n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949,
n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960,
n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982,
n983, n984, n985, n986, n987, n988, n989, n990, intadd_365_B_1_,
intadd_365_CI, intadd_365_SUM_2_, intadd_365_SUM_1_,
intadd_365_SUM_0_, intadd_365_n3, intadd_365_n2, intadd_365_n1, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Zn;
wire [29:0] d_ff2_X;
wire [31:1] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
DFFRXLTS reg_operation_Q_reg_0_ ( .D(n984), .CK(clk), .RN(n1529), .Q(
d_ff1_operation_out), .QN(n1495) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(n983), .CK(clk), .RN(n1529), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1504) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n981), .CK(clk), .RN(n1529), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n980), .CK(clk), .RN(n1528), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n979), .CK(clk), .RN(n1527), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n978), .CK(clk), .RN(n1528), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n977), .CK(clk), .RN(n1532), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n976), .CK(clk), .RN(n1531), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n975), .CK(clk), .RN(n1527), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n974), .CK(clk), .RN(n1532), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n973), .CK(clk), .RN(n1531), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n972), .CK(clk), .RN(n1528), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n971), .CK(clk), .RN(n1528), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n970), .CK(clk), .RN(n1528), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n969), .CK(clk), .RN(n1529), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n968), .CK(clk), .RN(n1527), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n967), .CK(clk), .RN(n1532), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n966), .CK(clk), .RN(n1531), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n965), .CK(clk), .RN(n1526), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n964), .CK(clk), .RN(n1530), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n963), .CK(clk), .RN(n1525), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n962), .CK(clk), .RN(n1515), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n961), .CK(clk), .RN(n1518), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n960), .CK(clk), .RN(n1187), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n959), .CK(clk), .RN(n1188), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n958), .CK(clk), .RN(n1525), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n957), .CK(clk), .RN(n1510), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n956), .CK(clk), .RN(n1519), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n955), .CK(clk), .RN(n1190), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n954), .CK(clk), .RN(n1188), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n953), .CK(clk), .RN(n1525), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n952), .CK(clk), .RN(n1523), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n951), .CK(clk), .RN(n1531), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n950), .CK(clk), .RN(n1526), .Q(d_ff1_Z[31])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n949), .CK(clk), .RN(n1528), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n948), .CK(clk), .RN(n1530), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n947), .CK(clk), .RN(n1526), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n946), .CK(clk), .RN(n1527), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n945), .CK(clk), .RN(n1532), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n944), .CK(clk), .RN(n1531), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n943), .CK(clk), .RN(n1528), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n942), .CK(clk), .RN(n1526), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n941), .CK(clk), .RN(n1529), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n940), .CK(clk), .RN(n1530), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n939), .CK(clk), .RN(n1530), .Q(d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n938), .CK(clk), .RN(n1528), .Q(d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n937), .CK(clk), .RN(n1529), .Q(d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n936), .CK(clk), .RN(n1527), .Q(d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n935), .CK(clk), .RN(n1532), .Q(d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n934), .CK(clk), .RN(n1531), .Q(d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n933), .CK(clk), .RN(n1529), .Q(d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n932), .CK(clk), .RN(n1528), .Q(d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n931), .CK(clk), .RN(n1526), .Q(d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n930), .CK(clk), .RN(n1528), .Q(d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n929), .CK(clk), .RN(n1527), .Q(d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n928), .CK(clk), .RN(n1532), .Q(d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n927), .CK(clk), .RN(n1530), .Q(d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n926), .CK(clk), .RN(n1527), .Q(d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n925), .CK(clk), .RN(n1532), .Q(d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n924), .CK(clk), .RN(n1531), .Q(d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n923), .CK(clk), .RN(n1526), .Q(d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n922), .CK(clk), .RN(n1529), .Q(d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n921), .CK(clk), .RN(n1529), .Q(d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n920), .CK(clk), .RN(n1526), .Q(d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n919), .CK(clk), .RN(n1527), .Q(d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n918), .CK(clk), .RN(n1532), .Q(d_ff_Zn[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n917), .CK(clk), .RN(n1531), .QN(n1104) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n916), .CK(clk), .RN(n1530), .QN(n1089) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n915), .CK(clk), .RN(n1532), .QN(n1090) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1531), .QN(n1091) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n913), .CK(clk), .RN(n1529), .QN(n1092) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n912), .CK(clk), .RN(n1526), .QN(n1093) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n911), .CK(clk), .RN(n1526), .QN(n1094) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n910), .CK(clk), .RN(n1530), .QN(n1095) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n909), .CK(clk), .RN(n1530), .QN(n1096) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n908), .CK(clk), .RN(n1532), .QN(n1097) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n907), .CK(clk), .RN(n1531), .QN(n1098) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n906), .CK(clk), .RN(n1528), .QN(n1083) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n905), .CK(clk), .RN(n1530), .QN(n1062) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n904), .CK(clk), .RN(n1530), .QN(n1063) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n903), .CK(clk), .RN(n1188), .QN(n1064) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n902), .CK(clk), .RN(n1525), .QN(n1065) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n901), .CK(clk), .RN(n1189), .QN(n1066) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n900), .CK(clk), .RN(n1516), .QN(n1067) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n899), .CK(clk), .RN(n1531), .QN(n1068) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n898), .CK(clk), .RN(n1533), .QN(n1084) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n897), .CK(clk), .RN(n1510), .QN(n1085) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n896), .CK(clk), .RN(n1525), .QN(n1086) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n895), .CK(clk), .RN(n1529), .QN(n1087) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n894), .CK(clk), .RN(n1523), .QN(n1107) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n893), .CK(clk), .RN(n1511), .QN(n1088) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n892), .CK(clk), .RN(n1512), .QN(n1099) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n891), .CK(clk), .RN(n1530), .QN(n1100) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n890), .CK(clk), .RN(n1529), .QN(n1101) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n889), .CK(clk), .RN(n1526), .QN(n1108) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n888), .CK(clk), .RN(n1526), .QN(n1102) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n887), .CK(clk), .RN(n1527), .QN(n1103) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(n873), .CK(clk), .RN(n1530), .QN(n1109) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(n872), .CK(clk), .RN(n1522), .QN(n1110) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(n871), .CK(clk), .RN(n1527), .QN(n1111) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(n870), .CK(clk), .RN(n1521), .QN(n1105) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(n869), .CK(clk), .RN(n1514), .QN(n1112) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(n868), .CK(clk), .RN(n1515), .QN(n1113) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(n867), .CK(clk), .RN(n1517), .QN(n1106) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n821), .CK(clk), .RN(n1516), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1522), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n1515), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n1517), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n817), .CK(clk), .RN(n1524), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n815), .CK(clk), .RN(n1521), .Q(
d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n813), .CK(clk), .RN(n1187), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n812), .CK(clk), .RN(n1514), .QN(n1178) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n811), .CK(clk), .RN(n1187), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n810), .CK(clk), .RN(n1515), .QN(n1180) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n809), .CK(clk), .RN(n1517), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n806), .CK(clk), .RN(n1516), .QN(n1181) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1522), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1523), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1520), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1519), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n713), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n712), .CK(clk), .RN(n1190), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n711), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n710), .CK(clk), .RN(n1519), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1520), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n708), .CK(clk), .RN(n1516), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n707), .CK(clk), .RN(n1522), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n706), .CK(clk), .RN(n1523), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1520), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n1519), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n647), .CK(clk), .RN(n1188), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n646), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n645), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n644), .CK(clk), .RN(n1188), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n643), .CK(clk), .RN(n1516), .QN(n1179)
);
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n642), .CK(clk), .RN(n1522), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n799), .CK(clk), .RN(n1516), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n798), .CK(clk), .RN(n1522), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n797), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n796), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n795), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n794), .CK(clk), .RN(n1518), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n793), .CK(clk), .RN(n1188), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n792), .CK(clk), .RN(n1516), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n791), .CK(clk), .RN(n1522), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n790), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n789), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n788), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n781), .CK(clk), .RN(n1522), .Q(
d_ff2_Z[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n780), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n779), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n778), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n1518), .Q(
d_ff2_Z[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n775), .CK(clk), .RN(n1514), .Q(
d_ff2_Z[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n774), .CK(clk), .RN(n1515), .Q(
d_ff2_Z[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n773), .CK(clk), .RN(n1517), .Q(
d_ff2_Z[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n772), .CK(clk), .RN(n1524), .Q(
d_ff2_Z[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n771), .CK(clk), .RN(n1521), .Q(
d_ff2_Z[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n770), .CK(clk), .RN(n1514), .Q(
d_ff2_Z[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1515), .QN(
n1058) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1521), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1524), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n762), .CK(clk), .RN(n1519), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n760), .CK(clk), .RN(n1520), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n758), .CK(clk), .RN(n1523), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n756), .CK(clk), .RN(n1516), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(n755), .CK(clk), .RN(n1522), .QN(
n1059) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n754), .CK(clk), .RN(n1188), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n752), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(n751), .CK(clk), .RN(n1524), .QN(
n1060) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n750), .CK(clk), .RN(n1517), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n748), .CK(clk), .RN(n1515), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n746), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n744), .CK(clk), .RN(n1521), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n742), .CK(clk), .RN(n1524), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1517), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n738), .CK(clk), .RN(n1517), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n736), .CK(clk), .RN(n1515), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n734), .CK(clk), .RN(n1187), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(n733), .CK(clk), .RN(n1524),
.QN(n1073) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n732), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(n731), .CK(clk), .RN(n1521),
.QN(n1072) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n730), .CK(clk), .RN(n1187), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(n729), .CK(clk), .RN(n1514),
.QN(n1061) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n728), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n726), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n724), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n722), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n704), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n702), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n700), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n696), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(n695), .CK(clk), .RN(n1511), .QN(
n1077) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n694), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(n693), .CK(clk), .RN(n1533), .QN(
n1074) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n692), .CK(clk), .RN(n1533), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(n691), .CK(clk), .RN(n1509), .QN(
n1075) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n690), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(n689), .CK(clk), .RN(n1511), .QN(
n1076) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n688), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(n687), .CK(clk), .RN(n1533), .QN(
n1078) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n686), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(n685), .CK(clk), .RN(n1509), .QN(
n1079) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n684), .CK(clk), .RN(n1533), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n682), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n680), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n678), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n676), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n674), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1189), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n666), .CK(clk), .RN(n281), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n664), .CK(clk), .RN(n281), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n662), .CK(clk), .RN(n1189), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n660), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(n659), .CK(clk), .RN(n1511),
.QN(n1080) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n658), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(n657), .CK(clk), .RN(n1509),
.QN(n1069) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(n655), .CK(clk), .RN(n1511),
.QN(n1070) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_26_ ( .D(n654), .CK(clk), .RN(n1533),
.QN(n1071) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(n650), .CK(clk), .RN(n1533),
.QN(n1082) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(n641), .CK(clk), .RN(n1511),
.QN(n1081) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n640), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n716), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[28]), .QN(n1505) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n808), .CK(clk), .RN(n1187), .QN(n1503) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n721), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[23]), .QN(n1502) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n656), .CK(clk), .RN(n1511), .Q(
d_ff2_X[24]), .QN(n1500) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n988), .CK(clk), .RN(n1187), .Q(
cont_iter_out[1]), .QN(n1499) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1519), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1498) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(n986), .CK(clk), .RN(n1189), .Q(
cont_iter_out[3]), .QN(n1496) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n990), .CK(clk), .RN(n1520), .Q(
cont_var_out[1]), .QN(n1494) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n985), .CK(clk), .RN(n1532), .Q(
cont_var_out[0]), .QN(n1493) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n853), .CK(clk), .RN(n1531), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n852), .CK(clk), .RN(n1532), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n1530), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1516), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n849), .CK(clk), .RN(n1518), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n848), .CK(clk), .RN(n1525), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n847), .CK(clk), .RN(n1519), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n846), .CK(clk), .RN(n1513), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n845), .CK(clk), .RN(n1520), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n844), .CK(clk), .RN(n1189), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n843), .CK(clk), .RN(n1525), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n842), .CK(clk), .RN(n1189), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n841), .CK(clk), .RN(n1513), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n840), .CK(clk), .RN(n1516), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n839), .CK(clk), .RN(n1531), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n838), .CK(clk), .RN(n1524), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n837), .CK(clk), .RN(n1517), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1515), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n835), .CK(clk), .RN(n1514), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n834), .CK(clk), .RN(n1521), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n833), .CK(clk), .RN(n1524), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n832), .CK(clk), .RN(n1520), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n831), .CK(clk), .RN(n1522), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n830), .CK(clk), .RN(n1516), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n829), .CK(clk), .RN(n1523), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n828), .CK(clk), .RN(n1188), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n827), .CK(clk), .RN(n1188), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n826), .CK(clk), .RN(n1188), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n825), .CK(clk), .RN(n1518), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n824), .CK(clk), .RN(n1519), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n823), .CK(clk), .RN(n1522), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n822), .CK(clk), .RN(n1516), .Q(
data_output[31]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n768), .CK(clk), .RN(n1514), .Q(
d_ff3_sign_out) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n1189), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n1522), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n1508), .CK(clk), .RN(
n1531), .Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n1530), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n1522), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n1530), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n987), .CK(clk), .RN(n1525), .Q(n1506),
.QN(intadd_365_B_1_) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(n652), .CK(clk), .RN(n1533), .Q(
d_ff2_X[28]), .QN(n1501) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n717), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[27]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n653), .CK(clk), .RN(n1509), .Q(
d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n715), .CK(clk), .RN(n1510), .Q(
d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n651), .CK(clk), .RN(n1533), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n718), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n720), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n769), .CK(clk), .RN(n1521), .Q(
d_ff2_Z[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n714), .CK(clk), .RN(n1512), .Q(
d_ff2_Y[30]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1520), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n859), .CK(clk), .RN(n1518), .Q(d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n860), .CK(clk), .RN(n1519), .Q(d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n875), .CK(clk), .RN(n1523), .Q(d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n878), .CK(clk), .RN(n1518), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n879), .CK(clk), .RN(n1525), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n880), .CK(clk), .RN(n1189), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n882), .CK(clk), .RN(n1190), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n883), .CK(clk), .RN(n1527), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n884), .CK(clk), .RN(n1529), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n857), .CK(clk), .RN(n1516), .Q(d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n861), .CK(clk), .RN(n1520), .Q(d_ff_Xn[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n723), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n725), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n727), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n737), .CK(clk), .RN(n1524), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n753), .CK(clk), .RN(n1190), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n757), .CK(clk), .RN(n1518), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n759), .CK(clk), .RN(n1519), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n761), .CK(clk), .RN(n1520), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n763), .CK(clk), .RN(n1522), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1524), .Q(
d_ff2_Y[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n874), .CK(clk), .RN(n1189), .Q(d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n876), .CK(clk), .RN(n1187), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n877), .CK(clk), .RN(n1531), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n881), .CK(clk), .RN(n1520), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n885), .CK(clk), .RN(n1529), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n886), .CK(clk), .RN(n1529), .Q(d_ff_Yn_31_) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n854), .CK(clk), .RN(n1523), .Q(d_ff_Xn[31]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n814), .CK(clk), .RN(n1514), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n816), .CK(clk), .RN(n1521), .Q(
d_ff3_LUT_out[5]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n807), .CK(clk), .RN(n1523), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1509), .Q(
d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n669), .CK(clk), .RN(n1533), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n982), .CK(clk), .RN(n1532), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1497) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n866), .CK(clk), .RN(n1517), .Q(d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n865), .CK(clk), .RN(n1515), .Q(d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n858), .CK(clk), .RN(n1188), .Q(d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n856), .CK(clk), .RN(n1518), .Q(d_ff_Xn[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n749), .CK(clk), .RN(n1521), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n747), .CK(clk), .RN(n1524), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n745), .CK(clk), .RN(n1517), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n743), .CK(clk), .RN(n1515), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n741), .CK(clk), .RN(n1187), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1517), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n735), .CK(clk), .RN(n1515), .Q(
d_ff2_Y[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n864), .CK(clk), .RN(n1522), .Q(d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n863), .CK(clk), .RN(n1516), .Q(d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n862), .CK(clk), .RN(n1523), .Q(d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n855), .CK(clk), .RN(n1519), .Q(d_ff_Xn[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n705), .CK(clk), .RN(n1510), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n701), .CK(clk), .RN(n1512), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n699), .CK(clk), .RN(n1510), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n697), .CK(clk), .RN(n1512), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n683), .CK(clk), .RN(n1512), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n679), .CK(clk), .RN(n1510), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n677), .CK(clk), .RN(n1512), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1510), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n665), .CK(clk), .RN(n281), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n663), .CK(clk), .RN(n281), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n703), .CK(clk), .RN(n1510), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n681), .CK(clk), .RN(n1512), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1510), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n667), .CK(clk), .RN(n281), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n661), .CK(clk), .RN(n1189), .Q(
d_ff2_X[21]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n1525), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n783), .CK(clk), .RN(n1188), .Q(
d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n1190), .Q(
d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n787), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n786), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n785), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n784), .CK(clk), .RN(n1518), .Q(
d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n782), .CK(clk), .RN(n1516), .Q(
d_ff2_Z[18]) );
DFFRXLTS ITER_CONT_temp_reg_0_ ( .D(n989), .CK(clk), .RN(n1532), .Q(n1182),
.QN(n1507) );
ADDFX1TS intadd_365_U4 ( .A(d_ff2_Y[24]), .B(n1499), .CI(intadd_365_CI),
.CO(intadd_365_n3), .S(intadd_365_SUM_0_) );
CMPR32X2TS intadd_365_U3 ( .A(d_ff2_Y[25]), .B(intadd_365_B_1_), .C(
intadd_365_n3), .CO(intadd_365_n2), .S(intadd_365_SUM_1_) );
CMPR32X2TS intadd_365_U2 ( .A(d_ff2_Y[26]), .B(n1496), .C(intadd_365_n2),
.CO(intadd_365_n1), .S(intadd_365_SUM_2_) );
AOI222X1TS U705 ( .A0(n1313), .A1(d_ff2_Z[29]), .B0(n1317), .B1(d_ff1_Z[29]),
.C0(d_ff_Zn[29]), .C1(n1463), .Y(n1303) );
AOI222X1TS U706 ( .A0(n1318), .A1(d_ff2_Z[28]), .B0(n1317), .B1(d_ff1_Z[28]),
.C0(d_ff_Zn[28]), .C1(n1463), .Y(n1307) );
AOI222X1TS U707 ( .A0(n1318), .A1(d_ff2_Z[27]), .B0(n1317), .B1(d_ff1_Z[27]),
.C0(d_ff_Zn[27]), .C1(n1463), .Y(n1309) );
AOI222X1TS U708 ( .A0(n1467), .A1(d_ff2_Z[30]), .B0(n1315), .B1(d_ff1_Z[30]),
.C0(d_ff_Zn[30]), .C1(n1463), .Y(n1316) );
AOI222X1TS U709 ( .A0(n1318), .A1(d_ff2_Z[23]), .B0(n1315), .B1(d_ff1_Z[23]),
.C0(d_ff_Zn[23]), .C1(n1443), .Y(n1306) );
AOI211X1TS U710 ( .A0(d_ff3_LUT_out[6]), .A1(n1442), .B0(n1202), .C0(n1201),
.Y(n1203) );
AOI222X1TS U711 ( .A0(n1376), .A1(d_ff3_sh_x_out[10]), .B0(n1223), .B1(
d_ff3_sh_y_out[10]), .C0(n1263), .C1(d_ff3_LUT_out[10]), .Y(n1280) );
AOI222X1TS U712 ( .A0(n1376), .A1(d_ff3_sh_x_out[26]), .B0(n1223), .B1(
d_ff3_sh_y_out[26]), .C0(n1263), .C1(d_ff3_LUT_out[26]), .Y(n1279) );
AOI222X1TS U713 ( .A0(n1376), .A1(d_ff3_sh_x_out[23]), .B0(n1223), .B1(
d_ff3_sh_y_out[23]), .C0(n1263), .C1(d_ff3_LUT_out[23]), .Y(n1272) );
AOI222X1TS U714 ( .A0(n1390), .A1(n1169), .B0(n1408), .B1(n1158), .C0(
d_ff2_Z[6]), .C1(n1276), .Y(n1270) );
AOI222X1TS U715 ( .A0(n1390), .A1(d_ff2_Y[1]), .B0(n1408), .B1(d_ff2_X[1]),
.C0(d_ff2_Z[1]), .C1(n1276), .Y(n1267) );
AOI222X1TS U716 ( .A0(n1265), .A1(d_ff2_Y[2]), .B0(n1408), .B1(d_ff2_X[2]),
.C0(d_ff2_Z[2]), .C1(n1276), .Y(n1266) );
AOI222X1TS U717 ( .A0(n1265), .A1(d_ff2_Y[3]), .B0(n1408), .B1(d_ff2_X[3]),
.C0(d_ff2_Z[3]), .C1(n1276), .Y(n1252) );
AOI222X1TS U718 ( .A0(n1265), .A1(d_ff2_Y[7]), .B0(n1408), .B1(n1157), .C0(
d_ff2_Z[7]), .C1(n1276), .Y(n1260) );
AOI222X1TS U719 ( .A0(n1376), .A1(d_ff3_sh_x_out[25]), .B0(n1223), .B1(
d_ff3_sh_y_out[25]), .C0(d_ff3_LUT_out[25]), .C1(n1276), .Y(n1275) );
AOI222X1TS U720 ( .A0(n1376), .A1(d_ff3_sh_x_out[24]), .B0(n1223), .B1(
d_ff3_sh_y_out[24]), .C0(n1387), .C1(d_ff3_LUT_out[24]), .Y(n1278) );
AOI222X1TS U721 ( .A0(n1250), .A1(d_ff2_Y[22]), .B0(n1273), .B1(n1153), .C0(
d_ff2_Z[22]), .C1(n1115), .Y(n1249) );
AOI222X1TS U722 ( .A0(n1250), .A1(d_ff2_Y[20]), .B0(n1273), .B1(d_ff2_X[20]),
.C0(d_ff2_Z[20]), .C1(n1115), .Y(n1247) );
AOI222X1TS U723 ( .A0(n1376), .A1(d_ff3_sh_x_out[6]), .B0(n1273), .B1(
d_ff3_sh_y_out[6]), .C0(d_ff3_LUT_out[6]), .C1(n1116), .Y(n1271) );
AOI222X1TS U724 ( .A0(n1250), .A1(d_ff2_Y[25]), .B0(n1273), .B1(n1175), .C0(
d_ff2_Z[25]), .C1(n1116), .Y(n1244) );
AOI222X1TS U725 ( .A0(n1250), .A1(n1165), .B0(n1273), .B1(d_ff2_X[19]), .C0(
d_ff2_Z[19]), .C1(n1116), .Y(n1248) );
AOI222X1TS U726 ( .A0(n1250), .A1(d_ff3_sh_x_out[2]), .B0(n1273), .B1(
d_ff3_sh_y_out[2]), .C0(n1116), .C1(d_ff3_LUT_out[2]), .Y(n1245) );
AOI222X1TS U727 ( .A0(n1250), .A1(d_ff3_sh_x_out[0]), .B0(n1273), .B1(
d_ff3_sh_y_out[0]), .C0(n1116), .C1(d_ff3_LUT_out[0]), .Y(n1243) );
AOI222X1TS U728 ( .A0(n1376), .A1(d_ff3_sh_x_out[4]), .B0(n1273), .B1(
d_ff3_sh_y_out[4]), .C0(n1387), .C1(d_ff3_LUT_out[4]), .Y(n1274) );
AOI222X1TS U729 ( .A0(n1250), .A1(d_ff3_sh_x_out[1]), .B0(n1273), .B1(
d_ff3_sh_y_out[1]), .C0(n1387), .C1(d_ff3_LUT_out[1]), .Y(n1246) );
AOI222X1TS U730 ( .A0(n1250), .A1(d_ff2_Y[21]), .B0(n1273), .B1(d_ff2_X[21]),
.C0(d_ff2_Z[21]), .C1(n1387), .Y(n1251) );
AOI222X1TS U731 ( .A0(n1390), .A1(d_ff2_Y[26]), .B0(n1273), .B1(n1174), .C0(
d_ff2_Z[26]), .C1(n1387), .Y(n1241) );
AOI222X1TS U732 ( .A0(n1265), .A1(d_ff2_Y[12]), .B0(n1268), .B1(d_ff2_X[12]),
.C0(d_ff2_Z[12]), .C1(n1387), .Y(n1256) );
AOI222X1TS U733 ( .A0(n1265), .A1(n1168), .B0(n1268), .B1(n1155), .C0(
d_ff2_Z[8]), .C1(n1276), .Y(n1261) );
AOI222X1TS U734 ( .A0(n1390), .A1(d_ff2_Y[5]), .B0(n1268), .B1(n1159), .C0(
d_ff2_Z[5]), .C1(n1276), .Y(n1269) );
AOI222X1TS U735 ( .A0(n1265), .A1(d_ff2_Y[4]), .B0(n1268), .B1(n1156), .C0(
d_ff2_Z[4]), .C1(n1387), .Y(n1254) );
AOI222X1TS U736 ( .A0(n1265), .A1(d_ff2_Y[11]), .B0(n1268), .B1(d_ff2_X[11]),
.C0(d_ff2_Z[11]), .C1(n1115), .Y(n1262) );
AOI222X1TS U737 ( .A0(n1265), .A1(d_ff2_Y[10]), .B0(n1268), .B1(d_ff2_X[10]),
.C0(d_ff2_Z[10]), .C1(n1115), .Y(n1257) );
AOI222X1TS U738 ( .A0(n1265), .A1(d_ff2_Y[9]), .B0(n1268), .B1(n1154), .C0(
d_ff2_Z[9]), .C1(n1115), .Y(n1258) );
NAND2X4TS U739 ( .A(n1281), .B(n1508), .Y(n1194) );
NOR2X6TS U740 ( .A(ready_cordic), .B(n1322), .Y(n1323) );
CLKBUFX3TS U741 ( .A(n1057), .Y(n1412) );
CLKBUFX3TS U742 ( .A(n1056), .Y(n1402) );
AOI222X1TS U743 ( .A0(n1364), .A1(data_output[28]), .B0(n1363), .B1(n1119),
.C0(n1366), .C1(d_ff_Xn[28]), .Y(n1333) );
AOI222X1TS U744 ( .A0(n1364), .A1(data_output[21]), .B0(n1363), .B1(n1131),
.C0(n1366), .C1(d_ff_Xn[21]), .Y(n1339) );
AOI222X1TS U745 ( .A0(n1364), .A1(data_output[22]), .B0(n1363), .B1(n1130),
.C0(n1366), .C1(d_ff_Xn[22]), .Y(n1362) );
AOI222X1TS U746 ( .A0(n1364), .A1(data_output[26]), .B0(n1363), .B1(n1127),
.C0(n1366), .C1(d_ff_Xn[26]), .Y(n1365) );
AOI222X1TS U747 ( .A0(n1364), .A1(data_output[29]), .B0(n1363), .B1(n1125),
.C0(n1366), .C1(d_ff_Xn[29]), .Y(n1351) );
AOI222X1TS U748 ( .A0(n1364), .A1(data_output[24]), .B0(n1363), .B1(n1129),
.C0(n1366), .C1(d_ff_Xn[24]), .Y(n1344) );
AOI222X1TS U749 ( .A0(n1313), .A1(d_ff2_Z[31]), .B0(n1317), .B1(d_ff1_Z[31]),
.C0(d_ff_Zn[31]), .C1(n1463), .Y(n1310) );
NOR2BX2TS U750 ( .AN(n1325), .B(n1368), .Y(n1326) );
AOI222X1TS U751 ( .A0(n1313), .A1(d_ff2_Z[0]), .B0(n1444), .B1(d_ff_Zn[0]),
.C0(n1315), .C1(d_ff1_Z[0]), .Y(n1319) );
AOI222X1TS U752 ( .A0(n1313), .A1(d_ff2_Z[14]), .B0(n1315), .B1(d_ff1_Z[14]),
.C0(d_ff_Zn[14]), .C1(n1443), .Y(n1296) );
AOI222X1TS U753 ( .A0(n1467), .A1(d_ff2_Z[16]), .B0(n1315), .B1(d_ff1_Z[16]),
.C0(d_ff_Zn[16]), .C1(n1443), .Y(n1288) );
AOI222X1TS U754 ( .A0(n1318), .A1(d_ff2_Z[13]), .B0(n1315), .B1(d_ff1_Z[13]),
.C0(d_ff_Zn[13]), .C1(n1443), .Y(n1289) );
AOI222X1TS U755 ( .A0(n1313), .A1(d_ff2_Z[15]), .B0(n1315), .B1(d_ff1_Z[15]),
.C0(d_ff_Zn[15]), .C1(n1443), .Y(n1290) );
AOI222X1TS U756 ( .A0(n1467), .A1(d_ff2_Z[18]), .B0(n1315), .B1(d_ff1_Z[18]),
.C0(d_ff_Zn[18]), .C1(n1443), .Y(n1292) );
INVX3TS U757 ( .A(n1398), .Y(n1396) );
XOR2XLTS U758 ( .A(n1171), .B(n1487), .Y(n1489) );
INVX3TS U759 ( .A(n1398), .Y(n1399) );
XOR2XLTS U760 ( .A(d_ff2_Y[30]), .B(n1453), .Y(n1454) );
NOR2X1TS U761 ( .A(n1462), .B(n1281), .Y(n1282) );
INVX2TS U762 ( .A(n1194), .Y(n1466) );
AO22XLTS U763 ( .A0(n1176), .A1(n1155), .B0(n1491), .B1(d_ff3_sh_x_out[8]),
.Y(n686) );
AOI32X1TS U764 ( .A0(n1320), .A1(n1176), .A2(n1434), .B0(d_ff3_LUT_out[23]),
.B1(n1442), .Y(n1196) );
INVX4TS U765 ( .A(n1209), .Y(n1397) );
NOR2X1TS U766 ( .A(n1392), .B(n1374), .Y(n1322) );
CLKBUFX3TS U767 ( .A(n1508), .Y(n1464) );
AO22XLTS U768 ( .A0(n1486), .A1(intadd_365_B_1_), .B0(n1484), .B1(
d_ff3_LUT_out[8]), .Y(n813) );
INVX3TS U769 ( .A(n1484), .Y(n1456) );
INVX3TS U770 ( .A(n1455), .Y(n1195) );
AOI222X1TS U771 ( .A0(n1250), .A1(d_ff2_Y[31]), .B0(n1273), .B1(n1152), .C0(
d_ff2_Z[31]), .C1(n1116), .Y(n1240) );
BUFX3TS U772 ( .A(n1404), .Y(n1056) );
BUFX3TS U773 ( .A(n1410), .Y(n1057) );
CLKBUFX2TS U774 ( .A(n1371), .Y(n1118) );
AOI222X1TS U775 ( .A0(n1250), .A1(n1167), .B0(n1268), .B1(d_ff2_X[17]), .C0(
d_ff2_Z[17]), .C1(n1387), .Y(n1222) );
OAI211X2TS U776 ( .A0(n1506), .A1(n1320), .B0(n1216), .C0(n1432), .Y(n1425)
);
NAND3BX1TS U777 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n1184), .Y(n1183) );
BUFX3TS U778 ( .A(n1416), .Y(n1419) );
INVX3TS U779 ( .A(n1226), .Y(n1218) );
INVX3TS U780 ( .A(n1242), .Y(n1263) );
INVX3TS U781 ( .A(n1320), .Y(n1437) );
INVX3TS U782 ( .A(n1239), .Y(n1223) );
CLKBUFX2TS U783 ( .A(d_ff1_operation_out), .Y(n1172) );
CLKBUFX2TS U784 ( .A(d_ff1_shift_region_flag_out[0]), .Y(n1173) );
NAND4XLTS U785 ( .A(n1496), .B(intadd_365_B_1_), .C(n1437), .D(n1499), .Y(
n1281) );
NAND2BXLTS U786 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1207), .Y(n1208)
);
INVX2TS U787 ( .A(n1183), .Y(n1455) );
BUFX3TS U788 ( .A(n1300), .Y(n1315) );
INVX2TS U789 ( .A(d_ff3_LUT_out[3]), .Y(n1235) );
AO22XLTS U790 ( .A0(n1463), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n1313),
.Y(n661) );
AO22XLTS U791 ( .A0(n1463), .A1(n1121), .B0(d_ff2_X[18]), .B1(n1313), .Y(
n667) );
AO22XLTS U792 ( .A0(n1463), .A1(n1122), .B0(d_ff2_X[15]), .B1(n1318), .Y(
n673) );
AO22XLTS U793 ( .A0(n1463), .A1(d_ff_Xn[11]), .B0(d_ff2_X[11]), .B1(n1462),
.Y(n681) );
AO22XLTS U794 ( .A0(n1457), .A1(d_ff_Xn[0]), .B0(d_ff2_X[0]), .B1(n1318),
.Y(n703) );
AO22XLTS U795 ( .A0(n1457), .A1(d_ff_Yn_31_), .B0(d_ff2_Y[31]), .B1(n1467),
.Y(n705) );
AO22XLTS U796 ( .A0(n1420), .A1(result_add_subt[30]), .B0(n1416), .B1(
d_ff_Xn[30]), .Y(n855) );
AO22XLTS U797 ( .A0(n1418), .A1(result_add_subt[23]), .B0(n1419), .B1(
d_ff_Xn[23]), .Y(n862) );
AO22XLTS U798 ( .A0(n1418), .A1(result_add_subt[22]), .B0(n1417), .B1(
d_ff_Xn[22]), .Y(n863) );
AO22XLTS U799 ( .A0(n1418), .A1(result_add_subt[21]), .B0(n1417), .B1(
d_ff_Xn[21]), .Y(n864) );
AO22XLTS U800 ( .A0(n1446), .A1(n1136), .B0(d_ff2_Y[16]), .B1(n1195), .Y(
n735) );
AO22XLTS U801 ( .A0(n1446), .A1(n1138), .B0(d_ff2_Y[14]), .B1(n1195), .Y(
n739) );
AO22XLTS U802 ( .A0(n1446), .A1(n1139), .B0(d_ff2_Y[13]), .B1(n1195), .Y(
n741) );
AO22XLTS U803 ( .A0(n1446), .A1(n1140), .B0(d_ff2_Y[12]), .B1(n1195), .Y(
n743) );
AO22XLTS U804 ( .A0(n1446), .A1(n1141), .B0(d_ff2_Y[11]), .B1(n1195), .Y(
n745) );
AO22XLTS U805 ( .A0(n1446), .A1(n1142), .B0(d_ff2_Y[10]), .B1(n1445), .Y(
n747) );
AO22XLTS U806 ( .A0(n1444), .A1(n1143), .B0(d_ff2_Y[9]), .B1(n1445), .Y(n749) );
AO22XLTS U807 ( .A0(n1420), .A1(result_add_subt[29]), .B0(n1416), .B1(
d_ff_Xn[29]), .Y(n856) );
AO22XLTS U808 ( .A0(n1420), .A1(result_add_subt[27]), .B0(n1416), .B1(
d_ff_Xn[27]), .Y(n858) );
AO22XLTS U809 ( .A0(n1418), .A1(result_add_subt[20]), .B0(n1417), .B1(
d_ff_Xn[20]), .Y(n865) );
AO22XLTS U810 ( .A0(n1418), .A1(result_add_subt[19]), .B0(n1417), .B1(
d_ff_Xn[19]), .Y(n866) );
AO22XLTS U811 ( .A0(n1396), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1398),
.B1(shift_region_flag[1]), .Y(n982) );
AO22XLTS U812 ( .A0(n1477), .A1(n1434), .B0(n1458), .B1(d_ff3_LUT_out[19]),
.Y(n807) );
AO22XLTS U813 ( .A0(n1420), .A1(result_add_subt[31]), .B0(n1416), .B1(
d_ff_Xn[31]), .Y(n854) );
AO22XLTS U814 ( .A0(n1411), .A1(result_add_subt[31]), .B0(n1413), .B1(
d_ff_Yn_31_), .Y(n886) );
AO22XLTS U815 ( .A0(n1415), .A1(result_add_subt[0]), .B0(n1417), .B1(
d_ff_Xn[0]), .Y(n885) );
AO22XLTS U816 ( .A0(n1415), .A1(result_add_subt[4]), .B0(n1419), .B1(
d_ff_Xn[4]), .Y(n881) );
AO22XLTS U817 ( .A0(n1415), .A1(result_add_subt[8]), .B0(n1419), .B1(
d_ff_Xn[8]), .Y(n877) );
AO22XLTS U818 ( .A0(n1415), .A1(result_add_subt[9]), .B0(n1419), .B1(
d_ff_Xn[9]), .Y(n876) );
AO22XLTS U819 ( .A0(n1415), .A1(result_add_subt[11]), .B0(n1419), .B1(
d_ff_Xn[11]), .Y(n874) );
AO22XLTS U820 ( .A0(n1446), .A1(n1151), .B0(d_ff2_Y[1]), .B1(n1445), .Y(n765) );
AO22XLTS U821 ( .A0(n1466), .A1(n1150), .B0(d_ff2_Y[2]), .B1(n1445), .Y(n763) );
AO22XLTS U822 ( .A0(n1466), .A1(n1149), .B0(d_ff2_Y[3]), .B1(n1445), .Y(n761) );
AO22XLTS U823 ( .A0(n1466), .A1(n1148), .B0(d_ff2_Y[4]), .B1(n1445), .Y(n759) );
AO22XLTS U824 ( .A0(n1466), .A1(n1147), .B0(d_ff2_Y[5]), .B1(n1445), .Y(n757) );
AO22XLTS U825 ( .A0(n1444), .A1(n1145), .B0(d_ff2_Y[7]), .B1(n1445), .Y(n753) );
AO22XLTS U826 ( .A0(n1446), .A1(n1137), .B0(d_ff2_Y[15]), .B1(n1195), .Y(
n737) );
AO22XLTS U827 ( .A0(n1446), .A1(n1132), .B0(d_ff2_Y[20]), .B1(n1195), .Y(
n727) );
AO22XLTS U828 ( .A0(n1457), .A1(n1131), .B0(d_ff2_Y[21]), .B1(n1195), .Y(
n725) );
AO22XLTS U829 ( .A0(n1457), .A1(n1130), .B0(d_ff2_Y[22]), .B1(n1195), .Y(
n723) );
AO22XLTS U830 ( .A0(n1420), .A1(result_add_subt[24]), .B0(n1416), .B1(
d_ff_Xn[24]), .Y(n861) );
AO22XLTS U831 ( .A0(n1420), .A1(result_add_subt[28]), .B0(n1416), .B1(
d_ff_Xn[28]), .Y(n857) );
AO22XLTS U832 ( .A0(n1415), .A1(result_add_subt[1]), .B0(n1419), .B1(
d_ff_Xn[1]), .Y(n884) );
AO22XLTS U833 ( .A0(n1415), .A1(result_add_subt[2]), .B0(n1419), .B1(
d_ff_Xn[2]), .Y(n883) );
AO22XLTS U834 ( .A0(n1415), .A1(result_add_subt[3]), .B0(n1419), .B1(
d_ff_Xn[3]), .Y(n882) );
AO22XLTS U835 ( .A0(n1415), .A1(result_add_subt[5]), .B0(n1419), .B1(
d_ff_Xn[5]), .Y(n880) );
AO22XLTS U836 ( .A0(n1415), .A1(result_add_subt[6]), .B0(n1419), .B1(
d_ff_Xn[6]), .Y(n879) );
AO22XLTS U837 ( .A0(n1415), .A1(result_add_subt[7]), .B0(n1419), .B1(
d_ff_Xn[7]), .Y(n878) );
AO22XLTS U838 ( .A0(n1415), .A1(result_add_subt[10]), .B0(n1419), .B1(
d_ff_Xn[10]), .Y(n875) );
AO22XLTS U839 ( .A0(n1420), .A1(result_add_subt[25]), .B0(n1416), .B1(
d_ff_Xn[25]), .Y(n860) );
AO22XLTS U840 ( .A0(n1420), .A1(result_add_subt[26]), .B0(n1416), .B1(
d_ff_Xn[26]), .Y(n859) );
NAND2BXLTS U841 ( .AN(d_ff3_LUT_out[27]), .B(n1442), .Y(n801) );
AO22XLTS U842 ( .A0(n1457), .A1(n1124), .B0(d_ff2_Y[30]), .B1(n1462), .Y(
n714) );
AO22XLTS U843 ( .A0(n1457), .A1(n1129), .B0(d_ff2_Y[24]), .B1(n1195), .Y(
n720) );
AO22XLTS U844 ( .A0(n1457), .A1(n1128), .B0(d_ff2_Y[25]), .B1(n1462), .Y(
n719) );
AO22XLTS U845 ( .A0(n1457), .A1(n1127), .B0(d_ff2_Y[26]), .B1(n1462), .Y(
n718) );
AO22XLTS U846 ( .A0(n1457), .A1(n1125), .B0(d_ff2_Y[29]), .B1(n1462), .Y(
n715) );
AO22XLTS U847 ( .A0(n1457), .A1(n1126), .B0(d_ff2_Y[27]), .B1(n1462), .Y(
n717) );
AOI2BB2XLTS U848 ( .B0(n1506), .B1(n1393), .A0N(n1393), .A1N(n1506), .Y(n987) );
OAI21XLTS U849 ( .A0(beg_fsm_cordic), .A1(n1370), .B0(n1211), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AO22XLTS U850 ( .A0(n1481), .A1(d_ff3_sign_out), .B0(n1176), .B1(d_ff2_Z[31]), .Y(n768) );
OAI21XLTS U851 ( .A0(n1330), .A1(n1337), .B0(n1329), .Y(n822) );
AOI222X1TS U852 ( .A0(n1323), .A1(data_output[23]), .B0(n1363), .B1(n1120),
.C0(n1366), .C1(d_ff_Xn[23]), .Y(n1345) );
AOI222X1TS U853 ( .A0(n1364), .A1(data_output[19]), .B0(n1363), .B1(n1133),
.C0(n1366), .C1(d_ff_Xn[19]), .Y(n1336) );
AOI222X1TS U854 ( .A0(n1323), .A1(data_output[18]), .B0(n1367), .B1(n1134),
.C0(n1360), .C1(n1121), .Y(n1338) );
AOI222X1TS U855 ( .A0(n1323), .A1(data_output[17]), .B0(n1367), .B1(n1135),
.C0(n1360), .C1(n1160), .Y(n1346) );
AOI222X1TS U856 ( .A0(n1323), .A1(data_output[16]), .B0(n1367), .B1(n1136),
.C0(n1360), .C1(n1161), .Y(n1340) );
AOI222X1TS U857 ( .A0(n1323), .A1(data_output[15]), .B0(n1367), .B1(n1137),
.C0(n1360), .C1(n1122), .Y(n1341) );
AOI222X1TS U858 ( .A0(n1323), .A1(data_output[14]), .B0(n1367), .B1(n1138),
.C0(n1360), .C1(n1162), .Y(n1342) );
AOI222X1TS U859 ( .A0(n1323), .A1(data_output[13]), .B0(n1367), .B1(n1139),
.C0(n1360), .C1(n1163), .Y(n1359) );
AOI222X1TS U860 ( .A0(n1323), .A1(data_output[12]), .B0(n1367), .B1(n1140),
.C0(n1360), .C1(n1164), .Y(n1361) );
AOI222X1TS U861 ( .A0(n1323), .A1(data_output[11]), .B0(n1367), .B1(n1141),
.C0(n1360), .C1(d_ff_Xn[11]), .Y(n1358) );
AOI222X1TS U862 ( .A0(n1323), .A1(data_output[10]), .B0(n1367), .B1(n1142),
.C0(n1360), .C1(d_ff_Xn[10]), .Y(n1347) );
AOI222X1TS U863 ( .A0(n1368), .A1(data_output[9]), .B0(n1367), .B1(n1143),
.C0(n1360), .C1(d_ff_Xn[9]), .Y(n1348) );
AOI222X1TS U864 ( .A0(n1368), .A1(data_output[8]), .B0(n1367), .B1(n1144),
.C0(n1360), .C1(d_ff_Xn[8]), .Y(n1349) );
AOI222X1TS U865 ( .A0(n1368), .A1(data_output[7]), .B0(n1367), .B1(n1145),
.C0(n1360), .C1(d_ff_Xn[7]), .Y(n1350) );
AOI222X1TS U866 ( .A0(n1368), .A1(data_output[6]), .B0(n1367), .B1(n1146),
.C0(n1331), .C1(d_ff_Xn[6]), .Y(n1332) );
AOI222X1TS U867 ( .A0(n1368), .A1(data_output[5]), .B0(n1326), .B1(n1147),
.C0(n1360), .C1(d_ff_Xn[5]), .Y(n1352) );
AOI222X1TS U868 ( .A0(n1368), .A1(data_output[4]), .B0(n1326), .B1(n1148),
.C0(n1360), .C1(d_ff_Xn[4]), .Y(n1353) );
AOI222X1TS U869 ( .A0(n1368), .A1(data_output[3]), .B0(n1326), .B1(n1149),
.C0(n1360), .C1(d_ff_Xn[3]), .Y(n1354) );
AOI222X1TS U870 ( .A0(n1368), .A1(data_output[2]), .B0(n1367), .B1(n1150),
.C0(n1366), .C1(d_ff_Xn[2]), .Y(n1355) );
AOI222X1TS U871 ( .A0(n1368), .A1(data_output[1]), .B0(n1363), .B1(n1151),
.C0(n1366), .C1(d_ff_Xn[1]), .Y(n1356) );
AOI222X1TS U872 ( .A0(n1368), .A1(data_output[0]), .B0(n1123), .B1(n1363),
.C0(d_ff_Xn[0]), .C1(n1366), .Y(n1369) );
AOI2BB2XLTS U873 ( .B0(n1395), .B1(n1493), .A0N(n1493), .A1N(n1395), .Y(n985) );
OAI211XLTS U874 ( .A0(n1395), .A1(n1239), .B0(n1226), .C0(n1185), .Y(n990)
);
NOR2XLTS U875 ( .A(n1373), .B(n1402), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
AO22XLTS U876 ( .A0(d_ff2_Y[23]), .A1(n1318), .B0(n1466), .B1(n1120), .Y(
n721) );
OAI211XLTS U877 ( .A0(n1176), .A1(n1503), .B0(n1421), .C0(n1435), .Y(n808)
);
AO22XLTS U878 ( .A0(d_ff2_Y[28]), .A1(n1313), .B0(n1466), .B1(n1119), .Y(
n716) );
AO22XLTS U879 ( .A0(n1490), .A1(n1152), .B0(n1491), .B1(d_ff3_sh_x_out[31]),
.Y(n640) );
AO22XLTS U880 ( .A0(n1446), .A1(d_ff_Xn[31]), .B0(n1152), .B1(n1195), .Y(
n641) );
AO22XLTS U881 ( .A0(n1171), .A1(n1467), .B0(n1466), .B1(d_ff_Xn[30]), .Y(
n650) );
AO22XLTS U882 ( .A0(n1463), .A1(d_ff_Xn[23]), .B0(n1177), .B1(n1467), .Y(
n657) );
AO22XLTS U883 ( .A0(n1490), .A1(n1153), .B0(n1488), .B1(d_ff3_sh_x_out[22]),
.Y(n658) );
AO22XLTS U884 ( .A0(n1463), .A1(d_ff_Xn[22]), .B0(n1153), .B1(n1313), .Y(
n659) );
AO22XLTS U885 ( .A0(n1486), .A1(d_ff2_X[21]), .B0(n1481), .B1(
d_ff3_sh_x_out[21]), .Y(n660) );
AO22XLTS U886 ( .A0(n1490), .A1(d_ff2_X[20]), .B0(n1488), .B1(
d_ff3_sh_x_out[20]), .Y(n662) );
AO22XLTS U887 ( .A0(n1486), .A1(d_ff2_X[19]), .B0(n1461), .B1(
d_ff3_sh_x_out[19]), .Y(n664) );
AO22XLTS U888 ( .A0(n1176), .A1(d_ff2_X[18]), .B0(n1459), .B1(
d_ff3_sh_x_out[18]), .Y(n666) );
AO22XLTS U889 ( .A0(n1490), .A1(d_ff2_X[17]), .B0(n1488), .B1(
d_ff3_sh_x_out[17]), .Y(n668) );
AO22XLTS U890 ( .A0(n1460), .A1(d_ff2_X[16]), .B0(n1458), .B1(
d_ff3_sh_x_out[16]), .Y(n670) );
AO22XLTS U891 ( .A0(n1456), .A1(d_ff2_X[15]), .B0(n1491), .B1(
d_ff3_sh_x_out[15]), .Y(n672) );
AO22XLTS U892 ( .A0(n1492), .A1(d_ff2_X[14]), .B0(n1459), .B1(
d_ff3_sh_x_out[14]), .Y(n674) );
AO22XLTS U893 ( .A0(n1486), .A1(d_ff2_X[13]), .B0(n1488), .B1(
d_ff3_sh_x_out[13]), .Y(n676) );
AO22XLTS U894 ( .A0(n1492), .A1(d_ff2_X[12]), .B0(n1488), .B1(
d_ff3_sh_x_out[12]), .Y(n678) );
AO22XLTS U895 ( .A0(n1477), .A1(d_ff2_X[11]), .B0(n1491), .B1(
d_ff3_sh_x_out[11]), .Y(n680) );
AO22XLTS U896 ( .A0(n1456), .A1(d_ff2_X[10]), .B0(n1459), .B1(
d_ff3_sh_x_out[10]), .Y(n682) );
AO22XLTS U897 ( .A0(n1460), .A1(n1154), .B0(n1458), .B1(d_ff3_sh_x_out[9]),
.Y(n684) );
AO22XLTS U898 ( .A0(n1457), .A1(d_ff_Xn[9]), .B0(n1154), .B1(n1462), .Y(n685) );
AO22XLTS U899 ( .A0(n1457), .A1(d_ff_Xn[8]), .B0(n1155), .B1(n1467), .Y(n687) );
AO22XLTS U900 ( .A0(n1486), .A1(n1157), .B0(n1491), .B1(d_ff3_sh_x_out[7]),
.Y(n688) );
AO22XLTS U901 ( .A0(n1477), .A1(n1158), .B0(n1491), .B1(d_ff3_sh_x_out[6]),
.Y(n690) );
AO22XLTS U902 ( .A0(n1456), .A1(n1159), .B0(n1458), .B1(d_ff3_sh_x_out[5]),
.Y(n692) );
AO22XLTS U903 ( .A0(n1456), .A1(n1156), .B0(n1491), .B1(d_ff3_sh_x_out[4]),
.Y(n694) );
AO22XLTS U904 ( .A0(n1457), .A1(d_ff_Xn[4]), .B0(n1156), .B1(n1313), .Y(n695) );
AO22XLTS U905 ( .A0(n1490), .A1(d_ff2_X[3]), .B0(n1491), .B1(
d_ff3_sh_x_out[3]), .Y(n696) );
AO22XLTS U906 ( .A0(n1490), .A1(d_ff2_X[2]), .B0(n1491), .B1(
d_ff3_sh_x_out[2]), .Y(n698) );
AO22XLTS U907 ( .A0(n1490), .A1(d_ff2_X[1]), .B0(n1491), .B1(
d_ff3_sh_x_out[1]), .Y(n700) );
AO22XLTS U908 ( .A0(n1490), .A1(d_ff2_X[0]), .B0(n1491), .B1(
d_ff3_sh_x_out[0]), .Y(n702) );
AO22XLTS U909 ( .A0(n1492), .A1(d_ff2_Y[31]), .B0(n1491), .B1(
d_ff3_sh_y_out[31]), .Y(n704) );
AO22XLTS U910 ( .A0(n1490), .A1(d_ff2_Y[22]), .B0(n1459), .B1(
d_ff3_sh_y_out[22]), .Y(n722) );
AO22XLTS U911 ( .A0(n1460), .A1(d_ff2_Y[21]), .B0(n1459), .B1(
d_ff3_sh_y_out[21]), .Y(n724) );
AO22XLTS U912 ( .A0(n1456), .A1(d_ff2_Y[20]), .B0(n1459), .B1(
d_ff3_sh_y_out[20]), .Y(n726) );
AO22XLTS U913 ( .A0(n1456), .A1(n1165), .B0(n1459), .B1(d_ff3_sh_y_out[19]),
.Y(n728) );
AO22XLTS U914 ( .A0(n1446), .A1(n1133), .B0(n1165), .B1(n1195), .Y(n729) );
AO22XLTS U915 ( .A0(n1456), .A1(n1166), .B0(n1459), .B1(d_ff3_sh_y_out[18]),
.Y(n730) );
AO22XLTS U916 ( .A0(n1446), .A1(n1134), .B0(n1166), .B1(n1195), .Y(n731) );
AO22XLTS U917 ( .A0(n1486), .A1(n1167), .B0(n1459), .B1(d_ff3_sh_y_out[17]),
.Y(n732) );
AO22XLTS U918 ( .A0(n1446), .A1(n1135), .B0(n1167), .B1(n1195), .Y(n733) );
AO22XLTS U919 ( .A0(n1492), .A1(d_ff2_Y[16]), .B0(n1459), .B1(
d_ff3_sh_y_out[16]), .Y(n734) );
AO22XLTS U920 ( .A0(n1477), .A1(d_ff2_Y[15]), .B0(n1459), .B1(
d_ff3_sh_y_out[15]), .Y(n736) );
AO22XLTS U921 ( .A0(n1176), .A1(d_ff2_Y[14]), .B0(n1458), .B1(
d_ff3_sh_y_out[14]), .Y(n738) );
AO22XLTS U922 ( .A0(n1477), .A1(d_ff2_Y[13]), .B0(n1458), .B1(
d_ff3_sh_y_out[13]), .Y(n740) );
AO22XLTS U923 ( .A0(n1460), .A1(d_ff2_Y[12]), .B0(n1458), .B1(
d_ff3_sh_y_out[12]), .Y(n742) );
AO22XLTS U924 ( .A0(n1492), .A1(d_ff2_Y[11]), .B0(n1458), .B1(
d_ff3_sh_y_out[11]), .Y(n744) );
AO22XLTS U925 ( .A0(n1492), .A1(d_ff2_Y[10]), .B0(n1458), .B1(
d_ff3_sh_y_out[10]), .Y(n746) );
AO22XLTS U926 ( .A0(n1456), .A1(d_ff2_Y[9]), .B0(n1458), .B1(
d_ff3_sh_y_out[9]), .Y(n748) );
AO22XLTS U927 ( .A0(n1490), .A1(n1168), .B0(n1458), .B1(d_ff3_sh_y_out[8]),
.Y(n750) );
AO22XLTS U928 ( .A0(n1443), .A1(n1144), .B0(n1168), .B1(n1445), .Y(n751) );
AO22XLTS U929 ( .A0(n1456), .A1(d_ff2_Y[7]), .B0(n1458), .B1(
d_ff3_sh_y_out[7]), .Y(n752) );
AO22XLTS U930 ( .A0(n1486), .A1(n1169), .B0(n1458), .B1(d_ff3_sh_y_out[6]),
.Y(n754) );
AO22XLTS U931 ( .A0(n1443), .A1(n1146), .B0(n1169), .B1(n1445), .Y(n755) );
AO22XLTS U932 ( .A0(n1456), .A1(d_ff2_Y[5]), .B0(n1458), .B1(
d_ff3_sh_y_out[5]), .Y(n756) );
AO22XLTS U933 ( .A0(n1486), .A1(d_ff2_Y[4]), .B0(n1488), .B1(
d_ff3_sh_y_out[4]), .Y(n758) );
AO22XLTS U934 ( .A0(n1456), .A1(d_ff2_Y[3]), .B0(n1488), .B1(
d_ff3_sh_y_out[3]), .Y(n760) );
AO22XLTS U935 ( .A0(n1486), .A1(d_ff2_Y[2]), .B0(n1488), .B1(
d_ff3_sh_y_out[2]), .Y(n762) );
AO22XLTS U936 ( .A0(n1456), .A1(d_ff2_Y[1]), .B0(n1488), .B1(
d_ff3_sh_y_out[1]), .Y(n764) );
AO22XLTS U937 ( .A0(n1486), .A1(n1170), .B0(n1488), .B1(d_ff3_sh_y_out[0]),
.Y(n766) );
AO22XLTS U938 ( .A0(n1463), .A1(n1123), .B0(n1170), .B1(n1318), .Y(n767) );
AO22XLTS U939 ( .A0(n1486), .A1(n1489), .B0(n1488), .B1(d_ff3_sh_x_out[30]),
.Y(n642) );
AO22XLTS U940 ( .A0(n1486), .A1(n1482), .B0(n1481), .B1(d_ff3_sh_x_out[28]),
.Y(n644) );
OAI21XLTS U941 ( .A0(n1480), .A1(n1501), .B0(n1483), .Y(n1482) );
AOI2BB2XLTS U942 ( .B0(n1176), .B1(n1478), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1460), .Y(n645) );
AO22XLTS U943 ( .A0(n1486), .A1(n1475), .B0(n1488), .B1(d_ff3_sh_x_out[26]),
.Y(n646) );
AO22XLTS U944 ( .A0(n1486), .A1(n1473), .B0(n1488), .B1(d_ff3_sh_x_out[25]),
.Y(n647) );
AO21XLTS U945 ( .A0(d_ff3_sh_x_out[24]), .A1(n1488), .B0(n1471), .Y(n648) );
AO22XLTS U946 ( .A0(n1490), .A1(n1454), .B0(n1491), .B1(d_ff3_sh_y_out[30]),
.Y(n706) );
AOI2BB2XLTS U947 ( .B0(n1492), .B1(n1452), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1477), .Y(n707) );
AO22XLTS U948 ( .A0(n1490), .A1(n1450), .B0(n1491), .B1(d_ff3_sh_y_out[28]),
.Y(n708) );
OAI21XLTS U949 ( .A0(n1448), .A1(n1505), .B0(n1451), .Y(n1450) );
AOI2BB2XLTS U950 ( .B0(n1176), .B1(n1447), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1477), .Y(n709) );
AO22XLTS U951 ( .A0(n1490), .A1(intadd_365_SUM_2_), .B0(n1459), .B1(
d_ff3_sh_y_out[26]), .Y(n710) );
AO22XLTS U952 ( .A0(n1490), .A1(intadd_365_SUM_1_), .B0(n1459), .B1(
d_ff3_sh_y_out[25]), .Y(n711) );
AO22XLTS U953 ( .A0(n1477), .A1(intadd_365_SUM_0_), .B0(n1459), .B1(
d_ff3_sh_y_out[24]), .Y(n712) );
OAI21XLTS U954 ( .A0(n1442), .A1(intadd_365_CI), .B0(n1198), .Y(n713) );
OAI21XLTS U955 ( .A0(cont_iter_out[3]), .A1(n1469), .B0(n1199), .Y(n802) );
NOR2XLTS U956 ( .A(n1437), .B(n1470), .Y(n1438) );
OAI21XLTS U957 ( .A0(n1437), .A1(n1435), .B0(n1213), .Y(n804) );
OAI21XLTS U958 ( .A0(n1434), .A1(n1440), .B0(n1196), .Y(n805) );
NAND2BXLTS U959 ( .AN(n1430), .B(n1429), .Y(n811) );
OAI211XLTS U960 ( .A0(n1477), .A1(n1178), .B0(n1217), .C0(n1431), .Y(n812)
);
OAI21XLTS U961 ( .A0(n1506), .A1(n1470), .B0(n1215), .Y(n817) );
OAI211XLTS U962 ( .A0(n1460), .A1(n1235), .B0(n1421), .C0(n1217), .Y(n818)
);
OAI21XLTS U963 ( .A0(n1469), .A1(n1216), .B0(n1200), .Y(n819) );
AO22XLTS U964 ( .A0(n1418), .A1(result_add_subt[18]), .B0(n1417), .B1(n1121),
.Y(n867) );
AO22XLTS U965 ( .A0(n1418), .A1(result_add_subt[17]), .B0(n1417), .B1(n1160),
.Y(n868) );
AO22XLTS U966 ( .A0(n1418), .A1(result_add_subt[16]), .B0(n1417), .B1(n1161),
.Y(n869) );
AO22XLTS U967 ( .A0(n1418), .A1(result_add_subt[15]), .B0(n1417), .B1(n1122),
.Y(n870) );
AO22XLTS U968 ( .A0(n1418), .A1(result_add_subt[14]), .B0(n1417), .B1(n1162),
.Y(n871) );
AO22XLTS U969 ( .A0(n1418), .A1(result_add_subt[13]), .B0(n1417), .B1(n1163),
.Y(n872) );
AO22XLTS U970 ( .A0(n1418), .A1(result_add_subt[12]), .B0(n1417), .B1(n1164),
.Y(n873) );
AO22XLTS U971 ( .A0(n1411), .A1(result_add_subt[30]), .B0(n1413), .B1(n1124),
.Y(n887) );
AO22XLTS U972 ( .A0(n1411), .A1(result_add_subt[29]), .B0(n1413), .B1(n1125),
.Y(n888) );
AO22XLTS U973 ( .A0(n1414), .A1(result_add_subt[28]), .B0(n1413), .B1(n1119),
.Y(n889) );
AO22XLTS U974 ( .A0(n1414), .A1(result_add_subt[27]), .B0(n1413), .B1(n1126),
.Y(n890) );
AO22XLTS U975 ( .A0(n1411), .A1(result_add_subt[26]), .B0(n1413), .B1(n1127),
.Y(n891) );
AO22XLTS U976 ( .A0(n1411), .A1(result_add_subt[25]), .B0(n1413), .B1(n1128),
.Y(n892) );
AO22XLTS U977 ( .A0(n1414), .A1(result_add_subt[24]), .B0(n1413), .B1(n1129),
.Y(n893) );
AO22XLTS U978 ( .A0(n1411), .A1(result_add_subt[23]), .B0(n1413), .B1(n1120),
.Y(n894) );
AO22XLTS U979 ( .A0(n1414), .A1(result_add_subt[22]), .B0(n1413), .B1(n1130),
.Y(n895) );
AO22XLTS U980 ( .A0(n1411), .A1(result_add_subt[21]), .B0(n1057), .B1(n1131),
.Y(n896) );
AO22XLTS U981 ( .A0(n1411), .A1(result_add_subt[20]), .B0(n1057), .B1(n1132),
.Y(n897) );
AO22XLTS U982 ( .A0(n1414), .A1(result_add_subt[19]), .B0(n1057), .B1(n1133),
.Y(n898) );
AO22XLTS U983 ( .A0(n1411), .A1(result_add_subt[18]), .B0(n1057), .B1(n1134),
.Y(n899) );
AO22XLTS U984 ( .A0(n1411), .A1(result_add_subt[17]), .B0(n1057), .B1(n1135),
.Y(n900) );
AO22XLTS U985 ( .A0(n1414), .A1(result_add_subt[16]), .B0(n1057), .B1(n1136),
.Y(n901) );
AO22XLTS U986 ( .A0(n1414), .A1(result_add_subt[15]), .B0(n1410), .B1(n1137),
.Y(n902) );
AO22XLTS U987 ( .A0(n1411), .A1(result_add_subt[14]), .B0(n1410), .B1(n1138),
.Y(n903) );
AO22XLTS U988 ( .A0(n1411), .A1(result_add_subt[13]), .B0(n1413), .B1(n1139),
.Y(n904) );
AO22XLTS U989 ( .A0(n1411), .A1(result_add_subt[12]), .B0(n1413), .B1(n1140),
.Y(n905) );
AO22XLTS U990 ( .A0(n1411), .A1(result_add_subt[11]), .B0(n1412), .B1(n1141),
.Y(n906) );
AO22XLTS U991 ( .A0(n1414), .A1(result_add_subt[10]), .B0(n1057), .B1(n1142),
.Y(n907) );
AO22XLTS U992 ( .A0(n1411), .A1(result_add_subt[9]), .B0(n1057), .B1(n1143),
.Y(n908) );
AO22XLTS U993 ( .A0(n1409), .A1(result_add_subt[8]), .B0(n1057), .B1(n1144),
.Y(n909) );
AO22XLTS U994 ( .A0(n1409), .A1(result_add_subt[7]), .B0(n1057), .B1(n1145),
.Y(n910) );
AO22XLTS U995 ( .A0(n1409), .A1(result_add_subt[6]), .B0(n1057), .B1(n1146),
.Y(n911) );
AO22XLTS U996 ( .A0(n1409), .A1(result_add_subt[5]), .B0(n1057), .B1(n1147),
.Y(n912) );
AO22XLTS U997 ( .A0(n1409), .A1(result_add_subt[4]), .B0(n1412), .B1(n1148),
.Y(n913) );
AO22XLTS U998 ( .A0(n1409), .A1(result_add_subt[3]), .B0(n1412), .B1(n1149),
.Y(n914) );
AO22XLTS U999 ( .A0(n1409), .A1(result_add_subt[2]), .B0(n1412), .B1(n1150),
.Y(n915) );
AO22XLTS U1000 ( .A0(n1409), .A1(result_add_subt[1]), .B0(n1412), .B1(n1151),
.Y(n916) );
AO22XLTS U1001 ( .A0(n1409), .A1(result_add_subt[0]), .B0(n1412), .B1(n1123),
.Y(n917) );
AO22XLTS U1002 ( .A0(n1407), .A1(result_add_subt[31]), .B0(n1406), .B1(
d_ff_Zn[31]), .Y(n918) );
AO22XLTS U1003 ( .A0(n1407), .A1(result_add_subt[30]), .B0(n1056), .B1(
d_ff_Zn[30]), .Y(n919) );
AO22XLTS U1004 ( .A0(n1407), .A1(result_add_subt[29]), .B0(n1056), .B1(
d_ff_Zn[29]), .Y(n920) );
AO22XLTS U1005 ( .A0(n1403), .A1(result_add_subt[28]), .B0(n1056), .B1(
d_ff_Zn[28]), .Y(n921) );
AO22XLTS U1006 ( .A0(n1407), .A1(result_add_subt[27]), .B0(n1056), .B1(
d_ff_Zn[27]), .Y(n922) );
AO22XLTS U1007 ( .A0(n1407), .A1(result_add_subt[26]), .B0(n1056), .B1(
d_ff_Zn[26]), .Y(n923) );
AO22XLTS U1008 ( .A0(n1403), .A1(result_add_subt[25]), .B0(n1056), .B1(
d_ff_Zn[25]), .Y(n924) );
AO22XLTS U1009 ( .A0(n1407), .A1(result_add_subt[24]), .B0(n1406), .B1(
d_ff_Zn[24]), .Y(n925) );
AO22XLTS U1010 ( .A0(n1403), .A1(result_add_subt[23]), .B0(n1406), .B1(
d_ff_Zn[23]), .Y(n926) );
AO22XLTS U1011 ( .A0(n1405), .A1(result_add_subt[22]), .B0(n1404), .B1(
d_ff_Zn[22]), .Y(n927) );
AO22XLTS U1012 ( .A0(n1405), .A1(result_add_subt[21]), .B0(n1406), .B1(
d_ff_Zn[21]), .Y(n928) );
AO22XLTS U1013 ( .A0(n1403), .A1(result_add_subt[20]), .B0(n1406), .B1(
d_ff_Zn[20]), .Y(n929) );
AO22XLTS U1014 ( .A0(n1407), .A1(result_add_subt[19]), .B0(n1406), .B1(
d_ff_Zn[19]), .Y(n930) );
AO22XLTS U1015 ( .A0(n1403), .A1(result_add_subt[18]), .B0(n1406), .B1(
d_ff_Zn[18]), .Y(n931) );
AO22XLTS U1016 ( .A0(n1407), .A1(result_add_subt[17]), .B0(n1406), .B1(
d_ff_Zn[17]), .Y(n932) );
AO22XLTS U1017 ( .A0(n1407), .A1(result_add_subt[16]), .B0(n1406), .B1(
d_ff_Zn[16]), .Y(n933) );
AO22XLTS U1018 ( .A0(n1403), .A1(result_add_subt[15]), .B0(n1406), .B1(
d_ff_Zn[15]), .Y(n934) );
AO22XLTS U1019 ( .A0(n1407), .A1(result_add_subt[14]), .B0(n1406), .B1(
d_ff_Zn[14]), .Y(n935) );
AO22XLTS U1020 ( .A0(n1407), .A1(result_add_subt[13]), .B0(n1406), .B1(
d_ff_Zn[13]), .Y(n936) );
AO22XLTS U1021 ( .A0(n1403), .A1(result_add_subt[12]), .B0(n1406), .B1(
d_ff_Zn[12]), .Y(n937) );
AO22XLTS U1022 ( .A0(n1403), .A1(result_add_subt[11]), .B0(n1406), .B1(
d_ff_Zn[11]), .Y(n938) );
AO22XLTS U1023 ( .A0(n1407), .A1(result_add_subt[10]), .B0(n1402), .B1(
d_ff_Zn[10]), .Y(n939) );
AO22XLTS U1024 ( .A0(n1407), .A1(result_add_subt[9]), .B0(n1056), .B1(
d_ff_Zn[9]), .Y(n940) );
AO22XLTS U1025 ( .A0(n1403), .A1(result_add_subt[8]), .B0(n1056), .B1(
d_ff_Zn[8]), .Y(n941) );
AO22XLTS U1026 ( .A0(n1407), .A1(result_add_subt[7]), .B0(n1404), .B1(
d_ff_Zn[7]), .Y(n942) );
AO22XLTS U1027 ( .A0(n1405), .A1(result_add_subt[6]), .B0(n1056), .B1(
d_ff_Zn[6]), .Y(n943) );
AO22XLTS U1028 ( .A0(n1405), .A1(result_add_subt[5]), .B0(n1056), .B1(
d_ff_Zn[5]), .Y(n944) );
AO22XLTS U1029 ( .A0(n1405), .A1(result_add_subt[4]), .B0(n1056), .B1(
d_ff_Zn[4]), .Y(n945) );
AO22XLTS U1030 ( .A0(n1405), .A1(result_add_subt[3]), .B0(n1056), .B1(
d_ff_Zn[3]), .Y(n946) );
AO22XLTS U1031 ( .A0(n1405), .A1(result_add_subt[2]), .B0(n1402), .B1(
d_ff_Zn[2]), .Y(n947) );
AO22XLTS U1032 ( .A0(n1405), .A1(result_add_subt[1]), .B0(n1402), .B1(
d_ff_Zn[1]), .Y(n948) );
AO22XLTS U1033 ( .A0(n1405), .A1(result_add_subt[0]), .B0(n1402), .B1(
d_ff_Zn[0]), .Y(n949) );
AO22XLTS U1034 ( .A0(n1401), .A1(d_ff1_Z[31]), .B0(n1400), .B1(data_in[31]),
.Y(n950) );
AO22XLTS U1035 ( .A0(n1401), .A1(d_ff1_Z[30]), .B0(n1400), .B1(data_in[30]),
.Y(n951) );
AO22XLTS U1036 ( .A0(n1401), .A1(d_ff1_Z[29]), .B0(n1400), .B1(data_in[29]),
.Y(n952) );
AO22XLTS U1037 ( .A0(n1401), .A1(d_ff1_Z[28]), .B0(n1400), .B1(data_in[28]),
.Y(n953) );
AO22XLTS U1038 ( .A0(n1401), .A1(d_ff1_Z[27]), .B0(n1400), .B1(data_in[27]),
.Y(n954) );
AO22XLTS U1039 ( .A0(n1401), .A1(d_ff1_Z[26]), .B0(n1400), .B1(data_in[26]),
.Y(n955) );
AO22XLTS U1040 ( .A0(n1401), .A1(d_ff1_Z[25]), .B0(n1400), .B1(data_in[25]),
.Y(n956) );
AO22XLTS U1041 ( .A0(n1401), .A1(d_ff1_Z[24]), .B0(n1400), .B1(data_in[24]),
.Y(n957) );
AO22XLTS U1042 ( .A0(n1399), .A1(d_ff1_Z[23]), .B0(n1400), .B1(data_in[23]),
.Y(n958) );
AO22XLTS U1043 ( .A0(n1399), .A1(d_ff1_Z[22]), .B0(n1400), .B1(data_in[22]),
.Y(n959) );
AO22XLTS U1044 ( .A0(n1399), .A1(d_ff1_Z[21]), .B0(n1400), .B1(data_in[21]),
.Y(n960) );
AO22XLTS U1045 ( .A0(n1399), .A1(d_ff1_Z[20]), .B0(n1400), .B1(data_in[20]),
.Y(n961) );
AO22XLTS U1046 ( .A0(n1399), .A1(d_ff1_Z[19]), .B0(n1397), .B1(data_in[19]),
.Y(n962) );
AO22XLTS U1047 ( .A0(n1399), .A1(d_ff1_Z[18]), .B0(n1397), .B1(data_in[18]),
.Y(n963) );
AO22XLTS U1048 ( .A0(n1399), .A1(d_ff1_Z[17]), .B0(n1397), .B1(data_in[17]),
.Y(n964) );
AO22XLTS U1049 ( .A0(n1399), .A1(d_ff1_Z[16]), .B0(n1397), .B1(data_in[16]),
.Y(n965) );
AO22XLTS U1050 ( .A0(n1399), .A1(d_ff1_Z[15]), .B0(n1397), .B1(data_in[15]),
.Y(n966) );
AO22XLTS U1051 ( .A0(n1399), .A1(d_ff1_Z[14]), .B0(n1397), .B1(data_in[14]),
.Y(n967) );
AO22XLTS U1052 ( .A0(n1399), .A1(d_ff1_Z[13]), .B0(n1397), .B1(data_in[13]),
.Y(n968) );
AO22XLTS U1053 ( .A0(n1399), .A1(d_ff1_Z[12]), .B0(n1397), .B1(data_in[12]),
.Y(n969) );
AO22XLTS U1054 ( .A0(n1399), .A1(d_ff1_Z[11]), .B0(n1397), .B1(data_in[11]),
.Y(n970) );
AO22XLTS U1055 ( .A0(n1399), .A1(d_ff1_Z[10]), .B0(n1397), .B1(data_in[10]),
.Y(n971) );
AO22XLTS U1056 ( .A0(n1396), .A1(d_ff1_Z[9]), .B0(n1397), .B1(data_in[9]),
.Y(n972) );
AO22XLTS U1057 ( .A0(n1396), .A1(d_ff1_Z[8]), .B0(n1397), .B1(data_in[8]),
.Y(n973) );
AO22XLTS U1058 ( .A0(n1396), .A1(d_ff1_Z[7]), .B0(n1397), .B1(data_in[7]),
.Y(n974) );
AO22XLTS U1059 ( .A0(n1396), .A1(d_ff1_Z[6]), .B0(n1398), .B1(data_in[6]),
.Y(n975) );
AO22XLTS U1060 ( .A0(n1396), .A1(d_ff1_Z[5]), .B0(n1398), .B1(data_in[5]),
.Y(n976) );
AO22XLTS U1061 ( .A0(n1396), .A1(d_ff1_Z[4]), .B0(n1398), .B1(data_in[4]),
.Y(n977) );
AO22XLTS U1062 ( .A0(n1396), .A1(d_ff1_Z[3]), .B0(n1398), .B1(data_in[3]),
.Y(n978) );
AO22XLTS U1063 ( .A0(n1396), .A1(d_ff1_Z[2]), .B0(n1398), .B1(data_in[2]),
.Y(n979) );
AO22XLTS U1064 ( .A0(n1396), .A1(d_ff1_Z[1]), .B0(n1398), .B1(data_in[1]),
.Y(n980) );
AO22XLTS U1065 ( .A0(n1396), .A1(d_ff1_Z[0]), .B0(n1398), .B1(data_in[0]),
.Y(n981) );
AO22XLTS U1066 ( .A0(n1396), .A1(n1173), .B0(n1398), .B1(
shift_region_flag[0]), .Y(n983) );
AO22XLTS U1067 ( .A0(n1396), .A1(n1172), .B0(n1397), .B1(operation), .Y(n984) );
INVX2TS U1068 ( .A(n1263), .Y(n1114) );
CLKINVX3TS U1069 ( .A(n1114), .Y(n1115) );
INVX2TS U1070 ( .A(n1114), .Y(n1116) );
CLKBUFX2TS U1071 ( .A(n1194), .Y(n1117) );
AOI222X4TS U1072 ( .A0(n1313), .A1(d_ff2_Z[22]), .B0(n1315), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1443), .Y(n1308) );
AOI222X4TS U1073 ( .A0(n1467), .A1(d_ff2_Z[21]), .B0(n1315), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1443), .Y(n1314) );
AOI222X4TS U1074 ( .A0(n1467), .A1(d_ff2_Z[20]), .B0(n1315), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1443), .Y(n1305) );
AOI222X4TS U1075 ( .A0(n1318), .A1(d_ff2_Z[19]), .B0(n1315), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1443), .Y(n1301) );
AOI222X1TS U1076 ( .A0(n1250), .A1(n1166), .B0(n1268), .B1(d_ff2_X[18]),
.C0(d_ff2_Z[18]), .C1(n1115), .Y(n1220) );
AOI222X1TS U1077 ( .A0(n1265), .A1(d_ff2_Y[16]), .B0(n1268), .B1(d_ff2_X[16]), .C0(d_ff2_Z[16]), .C1(n1115), .Y(n1264) );
AOI222X1TS U1078 ( .A0(n1265), .A1(d_ff2_Y[15]), .B0(n1268), .B1(d_ff2_X[15]), .C0(d_ff2_Z[15]), .C1(n1115), .Y(n1253) );
AOI222X1TS U1079 ( .A0(n1265), .A1(d_ff2_Y[14]), .B0(n1268), .B1(d_ff2_X[14]), .C0(d_ff2_Z[14]), .C1(n1115), .Y(n1255) );
AOI222X1TS U1080 ( .A0(n1265), .A1(d_ff2_Y[13]), .B0(n1273), .B1(d_ff2_X[13]), .C0(d_ff2_Z[13]), .C1(n1387), .Y(n1259) );
AOI222X1TS U1081 ( .A0(n1250), .A1(n1170), .B0(n1268), .B1(d_ff2_X[0]), .C0(
d_ff2_Z[0]), .C1(n1115), .Y(n1221) );
NOR3X1TS U1082 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n1192) );
OAI21XLTS U1083 ( .A0(n1263), .A1(n1372), .B0(n1481), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
OAI32X1TS U1084 ( .A0(n1393), .A1(n1437), .A2(n1392), .B0(n1499), .B1(n1393),
.Y(n988) );
BUFX4TS U1085 ( .A(n1187), .Y(n1522) );
BUFX4TS U1086 ( .A(n1187), .Y(n1516) );
BUFX4TS U1087 ( .A(n281), .Y(n1188) );
BUFX3TS U1088 ( .A(n281), .Y(n1190) );
BUFX3TS U1089 ( .A(n1188), .Y(n1189) );
BUFX3TS U1090 ( .A(n1190), .Y(n1187) );
BUFX4TS U1091 ( .A(n1525), .Y(n1530) );
BUFX4TS U1092 ( .A(n1525), .Y(n1529) );
BUFX4TS U1093 ( .A(n1188), .Y(n1532) );
BUFX4TS U1094 ( .A(n1190), .Y(n1531) );
BUFX4TS U1095 ( .A(n1190), .Y(n1515) );
BUFX4TS U1096 ( .A(n1188), .Y(n1525) );
BUFX4TS U1097 ( .A(n1515), .Y(n1523) );
BUFX4TS U1098 ( .A(n1515), .Y(n1520) );
BUFX4TS U1099 ( .A(n1515), .Y(n1519) );
BUFX4TS U1100 ( .A(n1521), .Y(n1518) );
BUFX4TS U1101 ( .A(n1223), .Y(n1408) );
NOR2X2TS U1102 ( .A(n1496), .B(intadd_365_B_1_), .Y(n1321) );
BUFX4TS U1103 ( .A(n1300), .Y(n1317) );
INVX2TS U1104 ( .A(n1242), .Y(n1276) );
OR2X2TS U1105 ( .A(n1494), .B(n1493), .Y(n1242) );
NOR3X2TS U1106 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(inst_CORDIC_FSM_v3_state_reg[1]),
.Y(n1191) );
AOI211X1TS U1107 ( .A0(n1437), .A1(n1499), .B0(n1442), .C0(n1432), .Y(n1202)
);
NAND2X2TS U1108 ( .A(cont_iter_out[3]), .B(intadd_365_B_1_), .Y(n1432) );
INVX2TS U1109 ( .A(n1108), .Y(n1119) );
INVX2TS U1110 ( .A(n1107), .Y(n1120) );
INVX2TS U1111 ( .A(n1106), .Y(n1121) );
INVX2TS U1112 ( .A(n1105), .Y(n1122) );
INVX2TS U1113 ( .A(n1104), .Y(n1123) );
INVX2TS U1114 ( .A(n1103), .Y(n1124) );
INVX2TS U1115 ( .A(n1102), .Y(n1125) );
INVX2TS U1116 ( .A(n1101), .Y(n1126) );
INVX2TS U1117 ( .A(n1100), .Y(n1127) );
INVX2TS U1118 ( .A(n1099), .Y(n1128) );
INVX2TS U1119 ( .A(n1088), .Y(n1129) );
INVX2TS U1120 ( .A(n1087), .Y(n1130) );
INVX2TS U1121 ( .A(n1086), .Y(n1131) );
INVX2TS U1122 ( .A(n1085), .Y(n1132) );
INVX2TS U1123 ( .A(n1084), .Y(n1133) );
INVX2TS U1124 ( .A(n1068), .Y(n1134) );
INVX2TS U1125 ( .A(n1067), .Y(n1135) );
INVX2TS U1126 ( .A(n1066), .Y(n1136) );
INVX2TS U1127 ( .A(n1065), .Y(n1137) );
INVX2TS U1128 ( .A(n1064), .Y(n1138) );
INVX2TS U1129 ( .A(n1063), .Y(n1139) );
INVX2TS U1130 ( .A(n1062), .Y(n1140) );
INVX2TS U1131 ( .A(n1083), .Y(n1141) );
INVX2TS U1132 ( .A(n1098), .Y(n1142) );
INVX2TS U1133 ( .A(n1097), .Y(n1143) );
INVX2TS U1134 ( .A(n1096), .Y(n1144) );
INVX2TS U1135 ( .A(n1095), .Y(n1145) );
INVX2TS U1136 ( .A(n1094), .Y(n1146) );
INVX2TS U1137 ( .A(n1093), .Y(n1147) );
INVX2TS U1138 ( .A(n1092), .Y(n1148) );
INVX2TS U1139 ( .A(n1091), .Y(n1149) );
INVX2TS U1140 ( .A(n1090), .Y(n1150) );
INVX2TS U1141 ( .A(n1089), .Y(n1151) );
INVX2TS U1142 ( .A(n1081), .Y(n1152) );
INVX2TS U1143 ( .A(n1080), .Y(n1153) );
INVX2TS U1144 ( .A(n1079), .Y(n1154) );
INVX2TS U1145 ( .A(n1078), .Y(n1155) );
INVX2TS U1146 ( .A(n1077), .Y(n1156) );
INVX2TS U1147 ( .A(n1076), .Y(n1157) );
INVX2TS U1148 ( .A(n1075), .Y(n1158) );
INVX2TS U1149 ( .A(n1074), .Y(n1159) );
INVX2TS U1150 ( .A(n1113), .Y(n1160) );
INVX2TS U1151 ( .A(n1112), .Y(n1161) );
INVX2TS U1152 ( .A(n1111), .Y(n1162) );
INVX2TS U1153 ( .A(n1110), .Y(n1163) );
INVX2TS U1154 ( .A(n1109), .Y(n1164) );
INVX2TS U1155 ( .A(n1061), .Y(n1165) );
INVX2TS U1156 ( .A(n1072), .Y(n1166) );
INVX2TS U1157 ( .A(n1073), .Y(n1167) );
INVX2TS U1158 ( .A(n1060), .Y(n1168) );
INVX2TS U1159 ( .A(n1059), .Y(n1169) );
INVX2TS U1160 ( .A(n1058), .Y(n1170) );
INVX2TS U1161 ( .A(n1082), .Y(n1171) );
AOI222X4TS U1162 ( .A0(n1364), .A1(data_output[30]), .B0(n1363), .B1(n1124),
.C0(n1366), .C1(d_ff_Xn[30]), .Y(n1335) );
AOI222X4TS U1163 ( .A0(n1364), .A1(data_output[27]), .B0(n1363), .B1(n1126),
.C0(n1366), .C1(d_ff_Xn[27]), .Y(n1357) );
AOI222X4TS U1164 ( .A0(n1364), .A1(data_output[20]), .B0(n1363), .B1(n1132),
.C0(n1366), .C1(d_ff_Xn[20]), .Y(n1334) );
OAI33X4TS U1165 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(n1172), .A2(n1504), .B0(n1497), .B1(n1495), .B2(n1173), .Y(n1327) );
INVX2TS U1166 ( .A(n1071), .Y(n1174) );
INVX2TS U1167 ( .A(n1070), .Y(n1175) );
AOI222X4TS U1168 ( .A0(n1318), .A1(d_ff2_Z[4]), .B0(n1300), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n1444), .Y(n1286) );
AOI222X4TS U1169 ( .A0(n1313), .A1(d_ff2_Z[10]), .B0(n1317), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n1444), .Y(n1287) );
AOI222X4TS U1170 ( .A0(n1467), .A1(d_ff2_Z[9]), .B0(n1317), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1444), .Y(n1291) );
AOI222X4TS U1171 ( .A0(n1318), .A1(d_ff2_Z[12]), .B0(n1317), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1444), .Y(n1294) );
AOI222X4TS U1172 ( .A0(n1318), .A1(d_ff2_Z[11]), .B0(n1317), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n1444), .Y(n1295) );
BUFX4TS U1173 ( .A(n1463), .Y(n1444) );
BUFX4TS U1174 ( .A(n1449), .Y(n1442) );
CLKINVX3TS U1175 ( .A(n1416), .Y(n1415) );
NOR3X4TS U1176 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1498), .C(n1186),
.Y(enab_cont_iter) );
CLKINVX3TS U1177 ( .A(n1242), .Y(n1387) );
INVX2TS U1178 ( .A(n1484), .Y(n1176) );
CLKINVX3TS U1179 ( .A(n1484), .Y(n1477) );
INVX4TS U1180 ( .A(n1484), .Y(n1486) );
INVX2TS U1181 ( .A(n1069), .Y(n1177) );
AOI222X4TS U1182 ( .A0(n1318), .A1(d_ff2_Z[1]), .B0(n1317), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1444), .Y(n1304) );
AOI222X4TS U1183 ( .A0(n1313), .A1(d_ff2_Z[2]), .B0(n1300), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1444), .Y(n1283) );
AOI222X4TS U1184 ( .A0(n1467), .A1(d_ff2_Z[3]), .B0(n1300), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n1444), .Y(n1285) );
AOI222X4TS U1185 ( .A0(n1318), .A1(d_ff2_Z[5]), .B0(n1300), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n1444), .Y(n1284) );
AOI222X4TS U1186 ( .A0(n1318), .A1(d_ff2_Z[6]), .B0(n1317), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n1444), .Y(n1299) );
AOI222X4TS U1187 ( .A0(n1313), .A1(d_ff2_Z[7]), .B0(n1317), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1444), .Y(n1297) );
AOI222X4TS U1188 ( .A0(n1467), .A1(d_ff2_Z[8]), .B0(n1317), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1444), .Y(n1293) );
NOR2X2TS U1189 ( .A(n1439), .B(n1427), .Y(n1436) );
NOR2X2TS U1190 ( .A(cont_iter_out[3]), .B(intadd_365_B_1_), .Y(n1439) );
BUFX4TS U1191 ( .A(n1511), .Y(n1510) );
BUFX4TS U1192 ( .A(n1533), .Y(n1512) );
BUFX3TS U1193 ( .A(n1189), .Y(n1533) );
AOI222X4TS U1194 ( .A0(n1364), .A1(data_output[25]), .B0(n1363), .B1(n1128),
.C0(n1366), .C1(d_ff_Xn[25]), .Y(n1343) );
NOR4X2TS U1195 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.D(inst_CORDIC_FSM_v3_state_reg[0]), .Y(n1207) );
INVX4TS U1196 ( .A(n1412), .Y(n1411) );
CLKINVX3TS U1197 ( .A(n1416), .Y(n1418) );
NAND3X4TS U1198 ( .A(n1494), .B(n1493), .C(ready_add_subt), .Y(n1416) );
OAI21X2TS U1199 ( .A0(n1321), .A1(n1437), .B0(n1432), .Y(n1427) );
NOR3X4TS U1200 ( .A(n1392), .B(n1437), .C(n1499), .Y(n1393) );
BUFX4TS U1201 ( .A(n1463), .Y(n1443) );
BUFX4TS U1202 ( .A(n1466), .Y(n1463) );
BUFX4TS U1203 ( .A(n1326), .Y(n1363) );
BUFX4TS U1204 ( .A(n1326), .Y(n1367) );
BUFX4TS U1205 ( .A(n1218), .Y(n1265) );
BUFX4TS U1206 ( .A(n1218), .Y(n1390) );
AOI222X4TS U1207 ( .A0(n1467), .A1(d_ff2_Z[25]), .B0(n1317), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1443), .Y(n1311) );
AOI222X4TS U1208 ( .A0(n1467), .A1(d_ff2_Z[26]), .B0(n1317), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1463), .Y(n1312) );
INVX4TS U1209 ( .A(n1464), .Y(n1467) );
INVX4TS U1210 ( .A(n1402), .Y(n1407) );
INVX4TS U1211 ( .A(n1484), .Y(n1490) );
INVX2TS U1212 ( .A(d_ff3_LUT_out[13]), .Y(n1433) );
OAI21XLTS U1213 ( .A0(n1436), .A1(n1470), .B0(n1204), .Y(n821) );
OAI21XLTS U1214 ( .A0(n1114), .A1(n1178), .B0(n1231), .Y(add_subt_dataB[9])
);
OAI21XLTS U1215 ( .A0(n1242), .A1(n1503), .B0(n1228), .Y(add_subt_dataB[20])
);
OAI21XLTS U1216 ( .A0(n1226), .A1(n1502), .B0(n1225), .Y(add_subt_dataA[23])
);
NOR3BX1TS U1217 ( .AN(n1191), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1205) );
NAND2BX1TS U1218 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(n1205), .Y(n1186) );
NOR3BX1TS U1219 ( .AN(n1207), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[1]), .Y(n1184) );
BUFX3TS U1220 ( .A(n1455), .Y(n1508) );
NAND3X1TS U1221 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1207), .C(n1191),
.Y(n1375) );
INVX2TS U1222 ( .A(n1375), .Y(ready_cordic) );
NAND3BX1TS U1223 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(n1184), .Y(n1372) );
NOR3BX2TS U1224 ( .AN(n1372), .B(enab_cont_iter), .C(ready_add_subt), .Y(
n1395) );
NAND2X1TS U1225 ( .A(cont_var_out[0]), .B(n1494), .Y(n1239) );
NAND2X1TS U1226 ( .A(cont_var_out[1]), .B(n1493), .Y(n1226) );
NAND2X1TS U1227 ( .A(n1395), .B(cont_var_out[1]), .Y(n1185) );
INVX2TS U1228 ( .A(enab_cont_iter), .Y(n1392) );
INVX2TS U1229 ( .A(n1507), .Y(n1320) );
NAND3BX1TS U1230 ( .AN(n1186), .B(inst_CORDIC_FSM_v3_state_reg[5]), .C(n1498), .Y(n1373) );
NAND2X1TS U1231 ( .A(n1372), .B(n1373), .Y(beg_add_subt) );
INVX2TS U1232 ( .A(rst), .Y(n281) );
BUFX3TS U1233 ( .A(n1525), .Y(n1528) );
BUFX3TS U1234 ( .A(n1525), .Y(n1527) );
BUFX3TS U1235 ( .A(n1190), .Y(n1517) );
BUFX3TS U1236 ( .A(n1190), .Y(n1524) );
BUFX3TS U1237 ( .A(n1525), .Y(n1526) );
BUFX3TS U1238 ( .A(n1190), .Y(n1521) );
BUFX3TS U1239 ( .A(n1189), .Y(n1509) );
BUFX3TS U1240 ( .A(n1187), .Y(n1511) );
BUFX3TS U1241 ( .A(n1190), .Y(n1514) );
BUFX3TS U1242 ( .A(n1509), .Y(n1513) );
NAND4BX1TS U1243 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n1192), .D(n1191), .Y(n1461) );
CLKBUFX2TS U1244 ( .A(n1461), .Y(n1481) );
BUFX3TS U1245 ( .A(n1481), .Y(n1484) );
NOR2X2TS U1246 ( .A(n1177), .B(n1437), .Y(n1472) );
NAND2X1TS U1247 ( .A(n1490), .B(n1437), .Y(n1440) );
INVX2TS U1248 ( .A(n1440), .Y(n1197) );
CLKBUFX2TS U1249 ( .A(n1484), .Y(n1449) );
AOI22X1TS U1250 ( .A0(n1197), .A1(n1177), .B0(d_ff3_sh_x_out[23]), .B1(n1442), .Y(n1193) );
OAI2BB1X1TS U1251 ( .A0N(n1492), .A1N(n1472), .B0(n1193), .Y(n649) );
BUFX3TS U1252 ( .A(n1466), .Y(n1446) );
BUFX3TS U1253 ( .A(n1466), .Y(n1457) );
INVX2TS U1254 ( .A(n1321), .Y(n1434) );
NAND2X1TS U1255 ( .A(n1320), .B(n1502), .Y(intadd_365_CI) );
AOI22X1TS U1256 ( .A0(d_ff2_Y[23]), .A1(n1197), .B0(d_ff3_sh_y_out[23]),
.B1(n1442), .Y(n1198) );
NAND2X2TS U1257 ( .A(n1486), .B(n1499), .Y(n1469) );
AOI21X1TS U1258 ( .A0(n1506), .A1(n1320), .B0(cont_iter_out[3]), .Y(n1214)
);
AOI22X1TS U1259 ( .A0(n1460), .A1(n1214), .B0(d_ff3_LUT_out[26]), .B1(n1442),
.Y(n1199) );
INVX2TS U1260 ( .A(n1439), .Y(n1216) );
NAND2X2TS U1261 ( .A(n1456), .B(cont_iter_out[1]), .Y(n1470) );
NOR3X1TS U1262 ( .A(n1506), .B(n1437), .C(n1470), .Y(n1201) );
AOI21X1TS U1263 ( .A0(d_ff3_LUT_out[2]), .A1(n1442), .B0(n1201), .Y(n1200)
);
OAI31X1TS U1264 ( .A0(cont_iter_out[3]), .A1(n1320), .A2(n1469), .B0(n1203),
.Y(n815) );
BUFX3TS U1265 ( .A(n1218), .Y(n1376) );
NAND2X1TS U1266 ( .A(n1376), .B(ready_add_subt), .Y(n1404) );
AOI211X1TS U1267 ( .A0(n1320), .A1(n1496), .B0(n1506), .C0(n1469), .Y(n1430)
);
AOI21X1TS U1268 ( .A0(d_ff3_LUT_out[0]), .A1(n1484), .B0(n1430), .Y(n1204)
);
NOR2XLTS U1269 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1206) );
NAND3X1TS U1270 ( .A(n1206), .B(inst_CORDIC_FSM_v3_state_reg[0]), .C(n1205),
.Y(n1370) );
NOR4BX1TS U1271 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[4]),
.D(n1208), .Y(n1371) );
NOR2BX1TS U1272 ( .AN(n1370), .B(n1118), .Y(n1209) );
NOR4X1TS U1273 ( .A(enab_cont_iter), .B(n1477), .C(n1508), .D(beg_add_subt),
.Y(n1210) );
AOI32X1TS U1274 ( .A0(n1396), .A1(n1375), .A2(n1210), .B0(ready_cordic),
.B1(ack_cordic), .Y(n1211) );
OAI2BB1X1TS U1275 ( .A0N(n1432), .A1N(n1216), .B0(n1492), .Y(n1421) );
INVX2TS U1276 ( .A(n1470), .Y(n1428) );
NAND2X1TS U1277 ( .A(n1428), .B(n1434), .Y(n1435) );
INVX2TS U1278 ( .A(n1469), .Y(n1423) );
NAND2X1TS U1279 ( .A(n1320), .B(n1434), .Y(n1212) );
AOI22X1TS U1280 ( .A0(n1423), .A1(n1212), .B0(d_ff3_LUT_out[24]), .B1(n1442),
.Y(n1213) );
AOI22X1TS U1281 ( .A0(n1214), .A1(n1423), .B0(d_ff3_LUT_out[4]), .B1(n1442),
.Y(n1215) );
NAND2X1TS U1282 ( .A(n1423), .B(n1434), .Y(n1217) );
NAND2X1TS U1283 ( .A(n1428), .B(n1425), .Y(n1431) );
BUFX3TS U1284 ( .A(n1218), .Y(n1250) );
AOI22X1TS U1285 ( .A0(n1250), .A1(d_ff3_sh_x_out[16]), .B0(n1408), .B1(
d_ff3_sh_y_out[16]), .Y(n1219) );
OAI21XLTS U1286 ( .A0(n1242), .A1(n1235), .B0(n1219), .Y(add_subt_dataB[16])
);
BUFX3TS U1287 ( .A(n1223), .Y(n1268) );
INVX2TS U1288 ( .A(n1220), .Y(add_subt_dataA[18]) );
INVX2TS U1289 ( .A(n1221), .Y(add_subt_dataA[0]) );
INVX2TS U1290 ( .A(n1222), .Y(add_subt_dataA[17]) );
BUFX3TS U1291 ( .A(n1223), .Y(n1384) );
AOI22X1TS U1292 ( .A0(n1384), .A1(d_ff3_sh_y_out[29]), .B0(n1263), .B1(
d_ff3_LUT_out[27]), .Y(n1224) );
OAI21XLTS U1293 ( .A0(n1226), .A1(n1179), .B0(n1224), .Y(add_subt_dataB[29])
);
AOI22X1TS U1294 ( .A0(n1384), .A1(n1177), .B0(d_ff2_Z[23]), .B1(n1263), .Y(
n1225) );
AOI22X1TS U1295 ( .A0(n1265), .A1(d_ff3_sh_x_out[18]), .B0(n1384), .B1(
d_ff3_sh_y_out[18]), .Y(n1227) );
OAI21XLTS U1296 ( .A0(n1242), .A1(n1433), .B0(n1227), .Y(add_subt_dataB[18])
);
AOI22X1TS U1297 ( .A0(n1218), .A1(d_ff3_sh_x_out[20]), .B0(n1384), .B1(
d_ff3_sh_y_out[20]), .Y(n1228) );
AOI22X1TS U1298 ( .A0(n1265), .A1(d_ff3_sh_x_out[21]), .B0(n1384), .B1(
d_ff3_sh_y_out[21]), .Y(n1229) );
OAI21XLTS U1299 ( .A0(n1242), .A1(n1181), .B0(n1229), .Y(add_subt_dataB[21])
);
AOI22X1TS U1300 ( .A0(n1390), .A1(d_ff3_sh_x_out[15]), .B0(n1384), .B1(
d_ff3_sh_y_out[15]), .Y(n1230) );
OAI21XLTS U1301 ( .A0(n1242), .A1(n1503), .B0(n1230), .Y(add_subt_dataB[15])
);
AOI22X1TS U1302 ( .A0(n1390), .A1(d_ff3_sh_x_out[9]), .B0(n1384), .B1(
d_ff3_sh_y_out[9]), .Y(n1231) );
AOI22X1TS U1303 ( .A0(n1390), .A1(d_ff3_sh_x_out[12]), .B0(n1384), .B1(
d_ff3_sh_y_out[12]), .Y(n1232) );
OAI21XLTS U1304 ( .A0(n1114), .A1(n1180), .B0(n1232), .Y(add_subt_dataB[12])
);
AOI22X1TS U1305 ( .A0(n1390), .A1(d_ff3_sh_x_out[17]), .B0(n1408), .B1(
d_ff3_sh_y_out[17]), .Y(n1233) );
OAI21XLTS U1306 ( .A0(n1114), .A1(n1503), .B0(n1233), .Y(add_subt_dataB[17])
);
AOI22X1TS U1307 ( .A0(n1390), .A1(d_ff3_sh_x_out[3]), .B0(n1408), .B1(
d_ff3_sh_y_out[3]), .Y(n1234) );
OAI21XLTS U1308 ( .A0(n1114), .A1(n1235), .B0(n1234), .Y(add_subt_dataB[3])
);
AOI22X1TS U1309 ( .A0(n1390), .A1(d_ff3_sh_x_out[13]), .B0(n1408), .B1(
d_ff3_sh_y_out[13]), .Y(n1236) );
OAI21XLTS U1310 ( .A0(n1114), .A1(n1433), .B0(n1236), .Y(add_subt_dataB[13])
);
AOI22X1TS U1311 ( .A0(n1390), .A1(d_ff2_Y[24]), .B0(d_ff2_Z[24]), .B1(n1263),
.Y(n1237) );
OAI21XLTS U1312 ( .A0(n1239), .A1(n1500), .B0(n1237), .Y(add_subt_dataA[24])
);
AOI22X1TS U1313 ( .A0(n1390), .A1(d_ff2_Y[28]), .B0(d_ff2_Z[28]), .B1(n1263),
.Y(n1238) );
OAI21XLTS U1314 ( .A0(n1239), .A1(n1501), .B0(n1238), .Y(add_subt_dataA[28])
);
BUFX3TS U1315 ( .A(n1408), .Y(n1273) );
INVX2TS U1316 ( .A(n1240), .Y(add_subt_dataA[31]) );
INVX2TS U1317 ( .A(n1241), .Y(add_subt_dataA[26]) );
INVX2TS U1318 ( .A(n1243), .Y(add_subt_dataB[0]) );
INVX2TS U1319 ( .A(n1244), .Y(add_subt_dataA[25]) );
INVX2TS U1320 ( .A(n1245), .Y(add_subt_dataB[2]) );
INVX2TS U1321 ( .A(n1246), .Y(add_subt_dataB[1]) );
INVX2TS U1322 ( .A(n1247), .Y(add_subt_dataA[20]) );
INVX2TS U1323 ( .A(n1248), .Y(add_subt_dataA[19]) );
INVX2TS U1324 ( .A(n1249), .Y(add_subt_dataA[22]) );
INVX2TS U1325 ( .A(n1251), .Y(add_subt_dataA[21]) );
INVX2TS U1326 ( .A(n1252), .Y(add_subt_dataA[3]) );
INVX2TS U1327 ( .A(n1253), .Y(add_subt_dataA[15]) );
INVX2TS U1328 ( .A(n1254), .Y(add_subt_dataA[4]) );
INVX2TS U1329 ( .A(n1255), .Y(add_subt_dataA[14]) );
INVX2TS U1330 ( .A(n1256), .Y(add_subt_dataA[12]) );
INVX2TS U1331 ( .A(n1257), .Y(add_subt_dataA[10]) );
INVX2TS U1332 ( .A(n1258), .Y(add_subt_dataA[9]) );
INVX2TS U1333 ( .A(n1259), .Y(add_subt_dataA[13]) );
INVX2TS U1334 ( .A(n1260), .Y(add_subt_dataA[7]) );
INVX2TS U1335 ( .A(n1261), .Y(add_subt_dataA[8]) );
INVX2TS U1336 ( .A(n1262), .Y(add_subt_dataA[11]) );
INVX2TS U1337 ( .A(n1264), .Y(add_subt_dataA[16]) );
INVX2TS U1338 ( .A(n1266), .Y(add_subt_dataA[2]) );
INVX2TS U1339 ( .A(n1267), .Y(add_subt_dataA[1]) );
INVX2TS U1340 ( .A(n1269), .Y(add_subt_dataA[5]) );
INVX2TS U1341 ( .A(n1270), .Y(add_subt_dataA[6]) );
INVX2TS U1342 ( .A(n1271), .Y(add_subt_dataB[6]) );
INVX2TS U1343 ( .A(n1272), .Y(add_subt_dataB[23]) );
INVX2TS U1344 ( .A(n1274), .Y(add_subt_dataB[4]) );
INVX2TS U1345 ( .A(n1275), .Y(add_subt_dataB[25]) );
AOI222X1TS U1346 ( .A0(n1376), .A1(d_ff3_sh_x_out[8]), .B0(n1223), .B1(
d_ff3_sh_y_out[8]), .C0(n1276), .C1(d_ff3_LUT_out[8]), .Y(n1277) );
INVX2TS U1347 ( .A(n1277), .Y(add_subt_dataB[8]) );
INVX2TS U1348 ( .A(n1278), .Y(add_subt_dataB[24]) );
INVX2TS U1349 ( .A(n1279), .Y(add_subt_dataB[26]) );
INVX2TS U1350 ( .A(n1280), .Y(add_subt_dataB[10]) );
INVX4TS U1351 ( .A(n1464), .Y(n1318) );
CLKBUFX2TS U1352 ( .A(n1282), .Y(n1300) );
INVX2TS U1353 ( .A(n1283), .Y(n798) );
INVX2TS U1354 ( .A(n1284), .Y(n795) );
INVX2TS U1355 ( .A(n1285), .Y(n797) );
INVX2TS U1356 ( .A(n1286), .Y(n796) );
INVX2TS U1357 ( .A(n1287), .Y(n790) );
INVX4TS U1358 ( .A(n1464), .Y(n1313) );
INVX2TS U1359 ( .A(n1288), .Y(n784) );
INVX2TS U1360 ( .A(n1289), .Y(n787) );
INVX2TS U1361 ( .A(n1290), .Y(n785) );
INVX2TS U1362 ( .A(n1291), .Y(n791) );
INVX2TS U1363 ( .A(n1292), .Y(n782) );
INVX2TS U1364 ( .A(n1293), .Y(n792) );
INVX2TS U1365 ( .A(n1294), .Y(n788) );
INVX2TS U1366 ( .A(n1295), .Y(n789) );
INVX2TS U1367 ( .A(n1296), .Y(n786) );
INVX2TS U1368 ( .A(n1297), .Y(n793) );
AOI222X1TS U1369 ( .A0(n1467), .A1(d_ff2_Z[17]), .B0(n1317), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1443), .Y(n1298) );
INVX2TS U1370 ( .A(n1298), .Y(n783) );
INVX2TS U1371 ( .A(n1299), .Y(n794) );
INVX2TS U1372 ( .A(n1301), .Y(n781) );
AOI222X1TS U1373 ( .A0(n1313), .A1(d_ff2_Z[24]), .B0(n1315), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1443), .Y(n1302) );
INVX2TS U1374 ( .A(n1302), .Y(n776) );
INVX2TS U1375 ( .A(n1303), .Y(n771) );
INVX2TS U1376 ( .A(n1304), .Y(n799) );
INVX2TS U1377 ( .A(n1305), .Y(n780) );
INVX2TS U1378 ( .A(n1306), .Y(n777) );
INVX2TS U1379 ( .A(n1307), .Y(n772) );
INVX2TS U1380 ( .A(n1308), .Y(n778) );
INVX2TS U1381 ( .A(n1309), .Y(n773) );
INVX2TS U1382 ( .A(n1310), .Y(n769) );
INVX2TS U1383 ( .A(n1311), .Y(n775) );
INVX2TS U1384 ( .A(n1312), .Y(n774) );
INVX2TS U1385 ( .A(n1314), .Y(n779) );
INVX2TS U1386 ( .A(n1316), .Y(n770) );
INVX2TS U1387 ( .A(n1319), .Y(n800) );
XNOR2X1TS U1388 ( .A(n1327), .B(d_ff_Xn[31]), .Y(n1330) );
NAND3X1TS U1389 ( .A(n1321), .B(n1320), .C(cont_iter_out[1]), .Y(n1374) );
BUFX3TS U1390 ( .A(n1323), .Y(n1368) );
BUFX3TS U1391 ( .A(n1368), .Y(n1364) );
XNOR2X1TS U1392 ( .A(d_ff1_shift_region_flag_out[1]), .B(n1172), .Y(n1324)
);
XNOR2X1TS U1393 ( .A(n1173), .B(n1324), .Y(n1325) );
NOR2X1TS U1394 ( .A(n1364), .B(n1325), .Y(n1331) );
INVX2TS U1395 ( .A(n1331), .Y(n1337) );
XOR2XLTS U1396 ( .A(d_ff_Yn_31_), .B(n1327), .Y(n1328) );
AOI22X1TS U1397 ( .A0(n1364), .A1(data_output[31]), .B0(n1363), .B1(n1328),
.Y(n1329) );
INVX2TS U1398 ( .A(n1332), .Y(n847) );
INVX4TS U1399 ( .A(n1337), .Y(n1366) );
INVX2TS U1400 ( .A(n1333), .Y(n825) );
INVX2TS U1401 ( .A(n1334), .Y(n833) );
INVX2TS U1402 ( .A(n1335), .Y(n823) );
INVX2TS U1403 ( .A(n1336), .Y(n834) );
INVX4TS U1404 ( .A(n1337), .Y(n1360) );
INVX2TS U1405 ( .A(n1338), .Y(n835) );
INVX2TS U1406 ( .A(n1339), .Y(n832) );
INVX2TS U1407 ( .A(n1340), .Y(n837) );
INVX2TS U1408 ( .A(n1341), .Y(n838) );
INVX2TS U1409 ( .A(n1342), .Y(n839) );
INVX2TS U1410 ( .A(n1343), .Y(n828) );
INVX2TS U1411 ( .A(n1344), .Y(n829) );
INVX2TS U1412 ( .A(n1345), .Y(n830) );
INVX2TS U1413 ( .A(n1346), .Y(n836) );
INVX2TS U1414 ( .A(n1347), .Y(n843) );
INVX2TS U1415 ( .A(n1348), .Y(n844) );
INVX2TS U1416 ( .A(n1349), .Y(n845) );
INVX2TS U1417 ( .A(n1350), .Y(n846) );
INVX2TS U1418 ( .A(n1351), .Y(n824) );
INVX2TS U1419 ( .A(n1352), .Y(n848) );
INVX2TS U1420 ( .A(n1353), .Y(n849) );
INVX2TS U1421 ( .A(n1354), .Y(n850) );
INVX2TS U1422 ( .A(n1355), .Y(n851) );
INVX2TS U1423 ( .A(n1356), .Y(n852) );
INVX2TS U1424 ( .A(n1357), .Y(n826) );
INVX2TS U1425 ( .A(n1358), .Y(n842) );
INVX2TS U1426 ( .A(n1359), .Y(n840) );
INVX2TS U1427 ( .A(n1361), .Y(n841) );
INVX2TS U1428 ( .A(n1362), .Y(n831) );
INVX2TS U1429 ( .A(n1365), .Y(n827) );
INVX2TS U1430 ( .A(n1369), .Y(n853) );
NOR2BX1TS U1431 ( .AN(beg_fsm_cordic), .B(n1370), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U1432 ( .A0(enab_cont_iter), .A1(n1374), .B0(n1118), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U1433 ( .A0(n1407), .A1(n1373), .B0(n1372), .B1(n1114), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
OAI22X1TS U1434 ( .A0(ack_cordic), .A1(n1375), .B0(n1392), .B1(n1374), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
AOI2BB2XLTS U1435 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U1436 ( .A0(n1376), .A1(d_ff3_sh_x_out[31]), .B0(n1223), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1437 ( .A0(n1376), .A1(d_ff3_sh_x_out[30]), .B0(n1223), .B1(
d_ff3_sh_y_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U1438 ( .A0(n1218), .A1(d_ff3_sh_x_out[28]), .B0(n1384), .B1(
d_ff3_sh_y_out[28]), .Y(n1377) );
NAND2X1TS U1439 ( .A(n1263), .B(d_ff3_LUT_out[27]), .Y(n1378) );
NAND2X1TS U1440 ( .A(n1377), .B(n1378), .Y(add_subt_dataB[28]) );
AOI22X1TS U1441 ( .A0(n1218), .A1(d_ff3_sh_x_out[27]), .B0(n1384), .B1(
d_ff3_sh_y_out[27]), .Y(n1379) );
NAND2X1TS U1442 ( .A(n1379), .B(n1378), .Y(add_subt_dataB[27]) );
AOI22X1TS U1443 ( .A0(n1218), .A1(d_ff3_sh_x_out[22]), .B0(n1384), .B1(
d_ff3_sh_y_out[22]), .Y(n1380) );
OAI2BB1X1TS U1444 ( .A0N(n1387), .A1N(d_ff3_LUT_out[19]), .B0(n1380), .Y(
add_subt_dataB[22]) );
AOI22X1TS U1445 ( .A0(n1218), .A1(d_ff3_sh_x_out[19]), .B0(n1384), .B1(
d_ff3_sh_y_out[19]), .Y(n1381) );
OAI2BB1X1TS U1446 ( .A0N(n1116), .A1N(d_ff3_LUT_out[19]), .B0(n1381), .Y(
add_subt_dataB[19]) );
AOI22X1TS U1447 ( .A0(n1218), .A1(d_ff3_sh_x_out[14]), .B0(n1408), .B1(
d_ff3_sh_y_out[14]), .Y(n1382) );
OAI2BB1X1TS U1448 ( .A0N(n1116), .A1N(d_ff3_LUT_out[5]), .B0(n1382), .Y(
add_subt_dataB[14]) );
AOI22X1TS U1449 ( .A0(n1218), .A1(d_ff3_sh_x_out[11]), .B0(n1408), .B1(
d_ff3_sh_y_out[11]), .Y(n1383) );
OAI2BB1X1TS U1450 ( .A0N(n1387), .A1N(d_ff3_LUT_out[7]), .B0(n1383), .Y(
add_subt_dataB[11]) );
AOI22X1TS U1451 ( .A0(n1390), .A1(d_ff3_sh_x_out[7]), .B0(n1384), .B1(
d_ff3_sh_y_out[7]), .Y(n1385) );
OAI2BB1X1TS U1452 ( .A0N(n1116), .A1N(d_ff3_LUT_out[7]), .B0(n1385), .Y(
add_subt_dataB[7]) );
AOI22X1TS U1453 ( .A0(n1218), .A1(d_ff3_sh_x_out[5]), .B0(n1408), .B1(
d_ff3_sh_y_out[5]), .Y(n1386) );
OAI2BB1X1TS U1454 ( .A0N(n1116), .A1N(d_ff3_LUT_out[5]), .B0(n1386), .Y(
add_subt_dataB[5]) );
AOI22X1TS U1455 ( .A0(n1218), .A1(d_ff2_Y[30]), .B0(d_ff2_Z[30]), .B1(n1263),
.Y(n1388) );
OAI2BB1X1TS U1456 ( .A0N(n1223), .A1N(n1171), .B0(n1388), .Y(
add_subt_dataA[30]) );
AOI22X1TS U1457 ( .A0(n1390), .A1(d_ff2_Y[29]), .B0(d_ff2_Z[29]), .B1(n1263),
.Y(n1389) );
OAI2BB1X1TS U1458 ( .A0N(n1223), .A1N(d_ff2_X[29]), .B0(n1389), .Y(
add_subt_dataA[29]) );
AOI22X1TS U1459 ( .A0(n1390), .A1(d_ff2_Y[27]), .B0(d_ff2_Z[27]), .B1(n1263),
.Y(n1391) );
OAI2BB1X1TS U1460 ( .A0N(n1223), .A1N(d_ff2_X[27]), .B0(n1391), .Y(
add_subt_dataA[27]) );
AOI22X1TS U1461 ( .A0(enab_cont_iter), .A1(n1182), .B0(n1437), .B1(n1392),
.Y(n989) );
NAND2X1TS U1462 ( .A(n1506), .B(n1393), .Y(n1394) );
XNOR2X1TS U1463 ( .A(cont_iter_out[3]), .B(n1394), .Y(n986) );
BUFX3TS U1464 ( .A(n1397), .Y(n1398) );
BUFX3TS U1465 ( .A(n1398), .Y(n1400) );
INVX2TS U1466 ( .A(n1398), .Y(n1401) );
INVX2TS U1467 ( .A(n1402), .Y(n1405) );
INVX2TS U1468 ( .A(n1402), .Y(n1403) );
BUFX3TS U1469 ( .A(n1056), .Y(n1406) );
NAND2X1TS U1470 ( .A(n1408), .B(ready_add_subt), .Y(n1410) );
INVX2TS U1471 ( .A(n1412), .Y(n1409) );
BUFX3TS U1472 ( .A(n1057), .Y(n1413) );
INVX2TS U1473 ( .A(n1412), .Y(n1414) );
BUFX3TS U1474 ( .A(n1419), .Y(n1417) );
INVX2TS U1475 ( .A(n1419), .Y(n1420) );
AOI22X1TS U1476 ( .A0(n1423), .A1(n1425), .B0(d_ff3_LUT_out[1]), .B1(n1442),
.Y(n1422) );
NAND2X1TS U1477 ( .A(n1422), .B(n1421), .Y(n820) );
AOI22X1TS U1478 ( .A0(n1423), .A1(n1427), .B0(d_ff3_LUT_out[5]), .B1(n1449),
.Y(n1424) );
NAND2X1TS U1479 ( .A(n1424), .B(n1431), .Y(n816) );
AOI22X1TS U1480 ( .A0(n1460), .A1(n1425), .B0(d_ff3_LUT_out[7]), .B1(n1442),
.Y(n1426) );
NAND2X1TS U1481 ( .A(n1426), .B(n1435), .Y(n814) );
AOI22X1TS U1482 ( .A0(n1428), .A1(n1427), .B0(d_ff3_LUT_out[10]), .B1(n1449),
.Y(n1429) );
OAI221XLTS U1483 ( .A0(n1460), .A1(n1180), .B0(n1461), .B1(n1432), .C0(n1431), .Y(n810) );
AOI22X1TS U1484 ( .A0(n1176), .A1(n1436), .B0(n1433), .B1(n1442), .Y(n809)
);
BUFX3TS U1485 ( .A(n1449), .Y(n1458) );
OAI221XLTS U1486 ( .A0(n1477), .A1(n1181), .B0(n1481), .B1(n1436), .C0(n1435), .Y(n806) );
AOI22X1TS U1487 ( .A0(n1439), .A1(n1438), .B0(d_ff3_LUT_out[25]), .B1(n1442),
.Y(n1441) );
AOI32X1TS U1488 ( .A0(n1469), .A1(n1441), .A2(n1440), .B0(n1506), .B1(n1441),
.Y(n803) );
BUFX3TS U1489 ( .A(n1481), .Y(n1488) );
INVX2TS U1490 ( .A(n1455), .Y(n1445) );
INVX2TS U1491 ( .A(n1484), .Y(n1460) );
INVX2TS U1492 ( .A(n1484), .Y(n1492) );
BUFX3TS U1493 ( .A(n1449), .Y(n1459) );
INVX2TS U1494 ( .A(n1464), .Y(n1462) );
NOR2X1TS U1495 ( .A(d_ff2_Y[27]), .B(intadd_365_n1), .Y(n1448) );
AOI21X1TS U1496 ( .A0(intadd_365_n1), .A1(d_ff2_Y[27]), .B0(n1448), .Y(n1447) );
OR3X1TS U1497 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .C(intadd_365_n1), .Y(
n1451) );
BUFX3TS U1498 ( .A(n1449), .Y(n1491) );
NOR2X1TS U1499 ( .A(d_ff2_Y[29]), .B(n1451), .Y(n1453) );
AOI21X1TS U1500 ( .A0(d_ff2_Y[29]), .A1(n1451), .B0(n1453), .Y(n1452) );
OA22X1TS U1501 ( .A0(d_ff_Xn[1]), .A1(n1194), .B0(n1455), .B1(d_ff2_X[1]),
.Y(n701) );
OA22X1TS U1502 ( .A0(d_ff_Xn[2]), .A1(n1194), .B0(n1464), .B1(d_ff2_X[2]),
.Y(n699) );
OA22X1TS U1503 ( .A0(d_ff_Xn[3]), .A1(n1194), .B0(n1455), .B1(d_ff2_X[3]),
.Y(n697) );
OA22X1TS U1504 ( .A0(d_ff_Xn[5]), .A1(n1117), .B0(n1455), .B1(n1159), .Y(
n693) );
OA22X1TS U1505 ( .A0(d_ff_Xn[6]), .A1(n1117), .B0(n1508), .B1(n1158), .Y(
n691) );
OA22X1TS U1506 ( .A0(d_ff_Xn[7]), .A1(n1117), .B0(n1508), .B1(n1157), .Y(
n689) );
OA22X1TS U1507 ( .A0(d_ff_Xn[10]), .A1(n1194), .B0(n1508), .B1(d_ff2_X[10]),
.Y(n683) );
OA22X1TS U1508 ( .A0(n1164), .A1(n1194), .B0(n1508), .B1(d_ff2_X[12]), .Y(
n679) );
OA22X1TS U1509 ( .A0(n1163), .A1(n1194), .B0(n1508), .B1(d_ff2_X[13]), .Y(
n677) );
OA22X1TS U1510 ( .A0(n1162), .A1(n1194), .B0(n1508), .B1(d_ff2_X[14]), .Y(
n675) );
OA22X1TS U1511 ( .A0(n1161), .A1(n1194), .B0(n1508), .B1(d_ff2_X[16]), .Y(
n671) );
OA22X1TS U1512 ( .A0(n1160), .A1(n1194), .B0(n1464), .B1(d_ff2_X[17]), .Y(
n669) );
OA22X1TS U1513 ( .A0(d_ff_Xn[19]), .A1(n1117), .B0(n1464), .B1(d_ff2_X[19]),
.Y(n665) );
OA22X1TS U1514 ( .A0(d_ff_Xn[20]), .A1(n1117), .B0(n1464), .B1(d_ff2_X[20]),
.Y(n663) );
OA22X1TS U1515 ( .A0(n1508), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n1194),
.Y(n656) );
OA22X1TS U1516 ( .A0(d_ff_Xn[25]), .A1(n1117), .B0(n1455), .B1(n1175), .Y(
n655) );
OA22X1TS U1517 ( .A0(d_ff_Xn[26]), .A1(n1117), .B0(n1508), .B1(n1174), .Y(
n654) );
OA22X1TS U1518 ( .A0(n1508), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1194),
.Y(n653) );
OA22X1TS U1519 ( .A0(n1464), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1194),
.Y(n652) );
OA22X1TS U1520 ( .A0(n1455), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1194),
.Y(n651) );
XOR2X1TS U1521 ( .A(n1472), .B(d_ff2_X[24]), .Y(n1468) );
MXI2X1TS U1522 ( .A(n1470), .B(n1469), .S0(n1468), .Y(n1471) );
AOI222X1TS U1523 ( .A0(cont_iter_out[1]), .A1(n1472), .B0(cont_iter_out[1]),
.B1(n1500), .C0(n1472), .C1(n1500), .Y(n1474) );
CMPR32X2TS U1524 ( .A(intadd_365_B_1_), .B(n1175), .C(n1474), .CO(n1476),
.S(n1473) );
CMPR32X2TS U1525 ( .A(n1496), .B(n1174), .C(n1476), .CO(n1479), .S(n1475) );
NOR2X1TS U1526 ( .A(d_ff2_X[27]), .B(n1479), .Y(n1480) );
AOI21X1TS U1527 ( .A0(n1479), .A1(d_ff2_X[27]), .B0(n1480), .Y(n1478) );
OR3X1TS U1528 ( .A(n1479), .B(d_ff2_X[27]), .C(d_ff2_X[28]), .Y(n1483) );
NOR2X1TS U1529 ( .A(d_ff2_X[29]), .B(n1483), .Y(n1487) );
AOI21X1TS U1530 ( .A0(d_ff2_X[29]), .A1(n1483), .B0(n1487), .Y(n1485) );
AOI22X1TS U1531 ( .A0(n1492), .A1(n1485), .B0(n1179), .B1(n1484), .Y(n643)
);
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_syn.sdf");
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:29:57 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_util_vector_logic_0_0 -prefix
// system_util_vector_logic_0_0_ system_util_vector_logic_0_0_stub.v
// Design : system_util_vector_logic_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_vector_logic,Vivado 2016.4" *)
module system_util_vector_logic_0_0(Op1, Op2, Res)
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Base Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME4_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/22/2014 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME4_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output LOCKED,
input CLKFBIN,
input CLKIN1,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "MMCME4_BASE";
reg trig_attr = 1'b0;
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire CLKFBIN_in;
wire CLKIN1_in;
wire PWRDWN_in;
wire RST_in;
assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0
assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0
assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CLKIN1_INVERTED_REG !== 1'b0) && (IS_CLKIN1_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-143] IS_CLKIN1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN1_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifndef XIL_XECLIB
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
`endif
wire CDDCDONE;
wire DRDY;
wire PSDONE;
wire CLKFBSTOPPED;
wire CLKINSTOPPED;
wire [15:0] DO;
MMCME4_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CDDCDONE (CDDCDONE),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(CLKFBSTOPPED),
.CLKINSTOPPED(CLKINSTOPPED),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (DO),
.DRDY (DRDY),
.LOCKED (LOCKED),
.PSDONE(PSDONE),
.CDDCREQ (1'b0),
.CLKFBIN (CLKFBIN_in),
.CLKIN1 (CLKIN1_in),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN_in),
.RST (RST_in)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_hr_to_fr(
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk)
begin
q_h0 <= d_h0;
q_l0 <= d_l0;
q_h1 <= d_h1;
q_l1 <= d_l1;
end
always @(negedge clk)
begin
q_l0_neg <= q_l0;
q_l1_neg <= q_l1;
end
assign q0 = clk ? q_l0_neg : q_h0;
assign q1 = clk ? q_l1_neg : q_h1;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_9_top,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "dma_loopback_auto_us_1,axi_dwidth_converter_v2_1_9_top,{}" *)
(* CORE_GENERATION_INFO = "dma_loopback_auto_us_1,axi_dwidth_converter_v2_1_9_top,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16\
,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_auto_us_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_9_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
//======================================================================
//
// gcm.v
// -----
// Top level wrapper for the AES-GCM block cipher mode core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module gcm(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_DONE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam STATUS_CORRECT_ICV = 2;
localparam ADDR_CONFIG = 8'h0a;
localparam CONFIG_ENCDEC_BIT = 0;
localparam CONFIG_KEYLEN_BIT = 1;
localparam CONFIG_TAGLEN_START = 4;
localparam CONFIG_TAGLEN_END = 5;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam KEY_WORDS = 8;
localparam ADDR_BLOCK0 = 8'h20;
localparam ADDR_BLOCK3 = 8'h23;
localparam BLOCK_WORDS = 4;
localparam ADDR_NONCE0 = 8'h30;
localparam ADDR_NONCE3 = 8'h33;
localparam NONCE_WORDS = 4;
localparam ADDR_TAG0 = 8'h40;
localparam ADDR_TAG3 = 8'h43;
localparam TAG_WORDS = 4;
localparam WSIZE = 32;
localparam CORE_NAME0 = 32'h67636d2d; // "gcm-"
localparam CORE_NAME1 = 32'h61657320; // "aes "
localparam CORE_VERSION = 32'h302e3032; // "0.02"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg done_reg;
reg done_new;
reg encdec_reg;
reg encdec_new;
reg encdec_we;
reg valid_reg;
reg ready_reg;
reg tag_correct_reg;
reg [31 : 0] block_reg [0 : 3];
reg block_we;
reg [1 : 0] block_address;
reg keylen_reg;
reg keylen_new;
reg keylen_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [2 : 0] key_address;
reg [1 : 0] taglen_reg;
reg [1 : 0] taglen_new;
reg taglen_we;
reg [31 : 0] nonce_reg [0 : 3];
reg nonce_we;
reg [1 : 0] nonce_address;
reg [31 : 0] tag_reg [0 : 3];
reg tag_we;
reg [1 : 0] tag_address;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg core_encdec;
wire core_ready;
wire core_valid;
wire core_tag_correct;
wire [127 : 0] core_block_in;
wire [127 : 0] core_block_out;
wire [127 : 0] core_tag_in;
wire [127 : 0] core_tag_out;
wire [255 : 0] core_key;
wire [127 : 0] core_nonce;
wire core_keylen;
wire [127 : 0] core_result;
reg config_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_block_in = {block_reg[0], block_reg[1], block_reg[2], block_reg[3]};
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
//----------------------------------------------------------------
// GCM core instantiation.
//----------------------------------------------------------------
gcm_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.done(done_reg),
.enc_dec(encdec_reg),
.keylen(keylen_reg),
.taglen(taglen_reg),
.ready(core_ready),
.valid(core_valid),
.tag_correct(core_tag_correct),
.key(core_key),
.nonce(core_nonce),
.block_in(core_block_in),
.block_out(core_block_out),
.tag_in(core_tag_in),
.tag_out(core_tag_out)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 4 ; i = i + 1)
begin
block_reg[i] <= 32'h0;
nonce_reg[i] <= 32'h0;
tag_reg[i] <= 32'h0;
end
for (i = 0 ; i < 8 ; i = i + 1)
key_reg[i] <= 32'h0;
init_reg <= 0;
next_reg <= 0;
done_reg <= 0;
encdec_reg <= 0;
keylen_reg <= 0;
taglen_reg <= 2'h0;
valid_reg <= 0;
ready_reg <= 0;
end
else
begin
ready_reg <= core_ready;
valid_reg <= core_valid;
init_reg <= init_new;
next_reg <= next_new;
done_reg <= done_new;
if (config_we)
begin
encdec_reg <= write_data[CONFIG_ENCDEC_BIT];
keylen_reg <= write_data[CONFIG_KEYLEN_BIT];
taglen_reg <= write_data[CONFIG_TAGLEN_END : CONFIG_TAGLEN_START];
end
if (keylen_we)
keylen_reg <= keylen_new;
if (taglen_we)
taglen_reg <= taglen_new;
if (encdec_we)
encdec_reg <= encdec_new;
if (block_we)
block_reg[block_address] <= write_data;
if (key_we)
key_reg[key_address] <= write_data;
if (nonce_we)
key_reg[nonce_address] <= write_data;
if (tag_we)
key_reg[tag_address] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 0;
next_new = 0;
done_new = 0;
config_we = 0;
key_we = 0;
block_we = 0;
nonce_we = 0;
tag_we = 0;
keylen_new = 0;
keylen_we = 0;
taglen_new = 0;
taglen_we = 0;
encdec_new = 0;
encdec_we = 0;
tmp_read_data = 32'h0;
key_address = address[2 : 0];
block_address = address[1 : 0];
nonce_address = address[1 : 0];
tag_address = address[1 : 0];
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
done_new = write_data[CTRL_DONE_BIT];
end
if (address == ADDR_CONFIG)
config_we = 1;
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1;
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
block_we = 1;
if ((address >= ADDR_NONCE0) && (address <= ADDR_NONCE3))
nonce_we = 1;
if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
tag_we = 1;
end // if (we)
else
begin
if (address == ADDR_NAME0)
tmp_read_data = CORE_NAME0;
if (address == ADDR_NAME1)
tmp_read_data = CORE_NAME1;
if (address == ADDR_VERSION)
tmp_read_data = CORE_VERSION;
if (address == ADDR_CTRL)
tmp_read_data = {30'h0, next_reg, init_reg};
if (address == ADDR_STATUS)
tmp_read_data = {30'h0, valid_reg, ready_reg};
if (address == ADDR_CONFIG)
tmp_read_data = {30'h0, valid_reg, ready_reg};
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
tmp_read_data = key_reg[key_address];
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
tmp_read_data = block_reg[block_address];
if ((address >= ADDR_NONCE0) && (address <= ADDR_NONCE3))
tmp_read_data = block_reg[nonce_address];
if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
tmp_read_data = block_reg[tag_address];
end
end
end // addr_decoder
endmodule // aes
//======================================================================
// EOF aes.v
//======================================================================
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen ([email protected]) ////
//// - Tadej Markovic ([email protected]) ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A311O_FUNCTIONAL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_FUNCTIONAL_V |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: arria2gx_dmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module arria2gx_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria II GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_8_V
`define SKY130_FD_SC_HDLL__PROBE_P_8_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog wrapper for probe_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__probe_p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__probe_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__probe_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__probe_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_V |
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we take a more serious look at how to use Coq to
study other things. Our case study is a _simple imperative
programming language_ called Imp, embodying a tiny core fragment
of conventional mainstream languages such as C and Java. Here is
a familiar mathematical function written in Imp.
Z := X;
Y := 1;
while ~(Z = 0) do
Y := Y * Z;
Z := Z - 1
end
*)
(** We concentrate here on defining the _syntax_ and _semantics_ of
Imp; later chapters in _Programming Language Foundations_
(_Software Foundations_, volume 2) develop a theory of
_program equivalence_ and introduce _Hoare Logic_, a widely
used logic for reasoning about imperative programs. *)
Set Warnings "-notation-overridden,-parsing,-deprecated-hint-without-locality".
From Coq Require Import Bool.Bool.
From Coq Require Import Init.Nat.
From Coq Require Import Arith.Arith.
From Coq Require Import Arith.EqNat. Import Nat.
From Coq Require Import Lia.
From Coq Require Import Lists.List. Import ListNotations.
From Coq Require Import Strings.String.
From LF Require Import Maps.
(* ################################################################# *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ================================================================= *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
Inductive bexp : Type :=
| BTrue
| BFalse
| BEq (a1 a2 : aexp)
| BLe (a1 a2 : aexp)
| BNot (b : bexp)
| BAnd (b1 b2 : bexp).
(** In this chapter, we'll mostly elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1 + 2 * 3"] to the AST
APlus (ANum 1) (AMult (ANum 2) (ANum 3)).
The optional chapter [ImpParser] develops a simple lexical
analyzer and parser that can perform this translation. You do
_not_ need to understand that chapter to understand this one, but
if you haven't already taken a course where these techniques are
covered (e.g., a compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a := nat
| a + a
| a - a
| a * a
b := true
| false
| a = a
| a <= a
| ~ b
| b && b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written with an infix
[+]) while leaving other aspects of lexical analysis and
parsing (like the relative precedence of [+], [-], and
[*], the use of parens to group subexpressions, etc.)
unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition, e.g., for implementing a compiler.
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- Conversely, the BNF version is lighter and easier to read.
Its informality makes it flexible, a big advantage in
situations like discussions at the blackboard, where
conveying general ideas is more important than getting every
detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say
which kind of BNF they're using because there is no need to:
a rough-and-ready informal understanding is all that's
important.
It's good to be comfortable with both sorts of notations: informal
ones for communicating between humans and formal ones for carrying
out implementations and proofs. *)
(* ================================================================= *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval a1) =? (aeval a2)
| BLe a1 a2 => (aeval a1) <=? (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ================================================================= *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0 + e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n => ANum n
| APlus (ANum 0) e2 => optimize_0plus e2
| APlus e1 e2 => APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 => AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 => AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
- (* ANum *) reflexivity.
- (* APlus *) destruct a1 eqn:Ea1.
+ (* a1 = ANum n *) destruct n eqn:En.
* (* n = 0 *) simpl. apply IHa2.
* (* n <> 0 *) simpl. rewrite IHa2. reflexivity.
+ (* a1 = APlus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMinus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMult a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
- (* AMinus *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
- (* AMult *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ################################################################# *)
(** * Coq Automation *)
(** The amount of repetition in this last proof is a little
annoying. And if either the language of arithmetic expressions or
the optimization being proved sound were significantly more
complex, it would start to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ================================================================= *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ----------------------------------------------------------------- *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (rather than failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* This just does [reflexivity]. *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* Just [reflexivity] would have failed. *)
apply HP. (* We can still finish the proof in some other way. *)
Qed.
(** There is no real reason to use [try] in completely manual
proofs like these, but it is very useful for doing automated
proofs in conjunction with the [;] tactical, which we show
next. *)
(* ----------------------------------------------------------------- *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most common form, the [;] tactical takes two tactics as
arguments. The compound tactic [T;T'] first performs [T] and then
performs [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, 0 <=? n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
- (* n=0 *) simpl. reflexivity.
- (* n=Sn' *) simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, 0 <=? n = true.
Proof.
intros.
(* [destruct] the current goal *)
destruct n;
(* then [simpl] each resulting subgoal *)
simpl;
(* and do [reflexivity] on each resulting subgoal *)
reflexivity.
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH... *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* ... but the remaining cases -- ANum and APlus --
are different: *)
- (* ANum *) reflexivity.
- (* APlus *)
destruct a1 eqn:Ea1;
(* Again, most cases follow directly by the IH: *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...]
does nothing, is when [e1 = ANum n]. In this
case, we have to destruct [n] (to see whether
the optimization applies) and rewrite with the
induction hypothesis. *)
+ (* a1 = ANum n *) destruct n eqn:En;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs. For
example, here is an informal proof of the optimization theorem
that matches the structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. Most cases follow directly from the
IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We must
show
aeval (optimize_0plus (APlus a1 a2)) = aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n]. If
[n = 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** However, this proof can still be improved: the first case (for
[a = ANum n]) is very trivial -- even more trivial than the cases
that we said simply followed from the IH -- yet we have chosen to
write it out in full. It would be better and clearer to drop it
and just say, at the top, "Most cases are either immediate or
direct from the IH. The only interesting case is the one for
[APlus]..." We can make the same improvement in our formal proof
too. Here's how it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
- (* APlus *)
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical also has a more general form than the simple
[T;T'] we've seen above. If [T], [T1], ..., [Tn] are tactics,
then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e., [T;T'] is shorthand for:
T; [T' | T' | ... | T']
*)
(* ----------------------------------------------------------------- *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying this
tactic until it fails to make progress. Here is an example showing
that [10] is in a long list using [repeat]. *)
Theorem In10 : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat (try (left; reflexivity); right).
Qed.
(** The tactic [repeat T] never fails: if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (i.e., it repeats zero times). *)
Theorem In10' : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat simpl.
repeat (left; reflexivity).
repeat (right; try (left; reflexivity)).
Qed.
(** The tactic [repeat T] also does not have any upper bound on the
number of times it applies [T]. If [T] is a tactic that always
succeeds (and makes progress), then repeat [T] will loop forever. *)
Theorem repeat_loop : forall (m n : nat),
m + n = n + m.
Proof.
intros m n.
(* Uncomment the next line to see the infinite loop occur.
In Proof General, [C-c C-c] will break out of the loop. *)
(* repeat rewrite Nat.add_comm. *)
Admitted.
(** While evaluation in Coq's term language, Gallina, is guaranteed to
terminate, tactic evaluation is not! This does not affect Coq's
logical consistency, however, since the job of [repeat] and other
tactics is to guide Coq in constructing proofs; if the
construction process diverges (i.e., it does not terminate), this
simply means that we have failed to construct a proof, not that we
have constructed a wrong one. *)
(** **** Exercise: 3 stars, standard (optimize_0plus_b_sound)
Since the [optimize_0plus] transformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function that performs this transformation on [bexp]s and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard, optional (optimize)
_Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many possible
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct. (You will probably
find it easiest to start small -- add just a single, simple
optimization and its correctness proof -- and build up to
something more interesting incrementally.) *)
(* FILL IN HERE
[] *)
(* ================================================================= *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic
scripts.
- The [Tactic Notation] idiom illustrated below gives a handy way
to define "shorthand tactics" that bundle several tactics into a
single command.
- For more sophisticated programming, Coq offers a built-in
language called [Ltac] with primitives that can examine and
modify the proof state. The details are a bit too complicated
to get into here (and it is generally agreed that [Ltac] is not
the most beautiful part of Coq's design!), but they can be found
in the reference manual and other books on Coq, and there are
many examples of [Ltac] definitions in the Coq standard library
that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but this
is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips
with, and it offers plenty of power for many purposes. Here's an
example. *)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] that takes one
tactic [c] as an argument and is defined to be equivalent to the
tactic [simpl; try c]. Now writing "[simpl_and_try reflexivity.]"
in a proof will be the same as writing "[simpl; try reflexivity.]" *)
(* ================================================================= *)
(** ** The [lia] Tactic *)
(** The [lia] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and ordering ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [lia] will either solve the goal or fail, meaning
that the goal is actually false. (If the goal is _not_ of this
form, [lia] will also fail.) *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. lia.
Qed.
Example add_comm__lia : forall m n,
m + n = n + m.
Proof.
intros. lia.
Qed.
Example add_assoc__lia : forall m n p,
m + (n + p) = m + n + p.
Proof.
intros. lia.
Qed.
(** (Note the [From Coq Require Import Lia.] at the top of
the file.) *)
(* ================================================================= *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: For a variable [x], find an assumption [x = e] or
[e = x] in the context, replace [x] with [e] throughout the
context and current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x] (where [x] is a variable).
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, solve the goal.
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c].
We'll see examples of all of these as we go along. *)
(* ################################################################# *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoint]s. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
aevalR (ANum n) n
| E_APlus (e1 e2 : aexp) (n1 n2 : nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus (e1 e2 : aexp) (n1 n2 : nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult (e1 e2 : aexp) (n1 n2 : nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
Module HypothesisNames.
(** A small notational aside. We could also write the definition of
[aevalR] as follow, with explicit names for the hypotheses in each
case: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
aevalR (ANum n) n
| E_APlus (e1 e2 : aexp) (n1 n2 : nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus (e1 e2 : aexp) (n1 n2 : nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult (e1 e2 : aexp) (n1 n2 : nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (AMult e1 e2) (n1 * n2).
(** This style gives us more control over the names that Coq chooses
during proofs involving [aevalR], at the cost of making the
definition a little more verbose. *)
End HypothesisNames.
(** It will be convenient to have an infix notation for
[aevalR]. We'll write [e ==> n] to mean that arithmetic expression
[e] evaluates to value [n]. *)
Notation "e '==>' n"
:= (aevalR e n)
(at level 90, left associativity)
: type_scope.
End aevalR_first_try.
(** As we saw in [IndProp] in our case study of regular
expressions, Coq provides a way to use this notation in the
definition of [aevalR] itself. *)
Reserved Notation "e '==>' n" (at level 90, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
(ANum n) ==> n
| E_APlus (e1 e2 : aexp) (n1 n2 : nat) :
(e1 ==> n1) -> (e2 ==> n2) -> (APlus e1 e2) ==> (n1 + n2)
| E_AMinus (e1 e2 : aexp) (n1 n2 : nat) :
(e1 ==> n1) -> (e2 ==> n2) -> (AMinus e1 e2) ==> (n1 - n2)
| E_AMult (e1 e2 : aexp) (n1 n2 : nat) :
(e1 ==> n1) -> (e2 ==> n2) -> (AMult e1 e2) ==> (n1 * n2)
where "e '==>' n" := (aevalR e n) : type_scope.
(* ================================================================= *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules
for [aevalR] and similar relations in the more readable graphical
form of _inference rules_, where the premises above the line
justify the conclusion below the line (we have already seen them
in the [IndProp] chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2 : aexp) (n1 n2 : nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 ==> n1
e2 ==> n2
-------------------- (E_APlus)
APlus e1 e2 ==> n1+n2
*)
(** Formally, there is nothing deep about inference rules: they
are just implications. You can read the rule name on the right as
the name of the constructor and read each of the linebreaks
between the premises above the line (as well as the line itself)
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration. In informal prose, this is either elided or else
indicated by saying something like "Let [aevalR] be the smallest
relation closed under the following rules...". *)
(** For example, [==>] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n ==> n
e1 ==> n1
e2 ==> n2
-------------------- (E_APlus)
APlus e1 e2 ==> n1+n2
e1 ==> n1
e2 ==> n2
--------------------- (E_AMinus)
AMinus e1 e2 ==> n1-n2
e1 ==> n1
e2 ==> n2
-------------------- (E_AMult)
AMult e1 e2 ==> n1*n2
*)
(** **** Exercise: 1 star, standard, optional (beval_rules)
Here, again, is the Coq definition of the [beval] function:
Fixpoint beval (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval a1) =? (aeval a2)
| BLe a1 a2 => (aeval a1) <=? (aeval a2)
| BNot b => negb (beval b)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
Write out a corresponding definition of boolean evaluation as a
relation (in inference rule notation). *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_beval_rules : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree: *)
Theorem aeval_iff_aevalR : forall a n,
(a ==> n) <-> aeval a = n.
Proof.
split.
- (* -> *)
intros H.
induction H; simpl.
+ (* E_ANum *)
reflexivity.
+ (* E_APlus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMinus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMult *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
- (* <- *)
generalize dependent n.
induction a;
simpl; intros; subst.
+ (* ANum *)
apply E_ANum.
+ (* APlus *)
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMinus *)
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMult *)
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** We can make the proof quite a bit shorter by making more
use of tacticals. *)
Theorem aeval_iff_aevalR' : forall a n,
(a ==> n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
- (* -> *)
intros H; induction H; subst; reflexivity.
- (* <- *)
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars, standard (bevalR)
Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval]. *)
Reserved Notation "e '==>b' b" (at level 90, left associativity).
Inductive bevalR: bexp -> bool -> Prop :=
(* FILL IN HERE *)
where "e '==>b' b" := (bevalR e b) : type_scope
.
Lemma beval_iff_bevalR : forall b bv,
b ==>b bv <-> beval b = bv.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End AExp.
(* ================================================================= *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste: either way works.
However, there are circumstances where relational definitions of
evaluation work much better than functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations with division: *)
Inductive aexp : Type :=
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp)
| ADiv (a1 a2 : aexp). (* <--- NEW *)
(** Extending the definition of [aeval] to handle this new
operation would not be straightforward (what should we return as
the result of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR]
is very easy. *)
Reserved Notation "e '==>' n"
(at level 90, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
(ANum n) ==> n
| E_APlus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (APlus a1 a2) ==> (n1 + n2)
| E_AMinus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMinus a1 a2) ==> (n1 - n2)
| E_AMult (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMult a1 a2) ==> (n1 * n2)
| E_ADiv (a1 a2 : aexp) (n1 n2 n3 : nat) : (* <----- NEW *)
(a1 ==> n1) -> (a2 ==> n2) -> (n2 > 0) ->
(mult n2 n3 = n1) -> (ADiv a1 a2) ==> n3
where "a '==>' n" := (aevalR a n) : type_scope.
(** Notice that the evaluation relation has now become _partial_:
There are some inputs for which it simply does not specify an
output. *)
End aevalR_division.
Module aevalR_extended.
(** Or suppose that we want to extend the arithmetic operations
by a nondeterministic number generator [any] that, when evaluated,
may yield any number. Note that this is not the same as making a
_probabilistic_ choice among all possible numbers -- we're not
specifying any particular probability distribution for the
results, just saying what results are _possible_. *)
Reserved Notation "e '==>' n" (at level 90, left associativity).
Inductive aexp : Type :=
| AAny (* <--- NEW *)
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
(** Again, extending [aeval] would be tricky, since now
evaluation is _not_ a deterministic function from expressions to
numbers, but extending [aevalR] is no problem... *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any (n : nat) :
AAny ==> n (* <--- NEW *)
| E_ANum (n : nat) :
(ANum n) ==> n
| E_APlus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (APlus a1 a2) ==> (n1 + n2)
| E_AMinus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMinus a1 a2) ==> (n1 - n2)
| E_AMult (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMult a1 a2) ==> (n1 * n2)
where "a '==>' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** At this point you maybe wondering: which style should I use
by default? In the examples we've just seen, relational
definitions turned out to be more useful than functional ones.
For situations like these, where the thing being defined is not
easy to express as a function, or indeed where it is _not_ a
function, there is no real choice. But what about when both
styles are workable?
One point in favor of relational definitions is that they can be
more elegant and easier to understand.
Another is that Coq automatically generates nice inversion and
induction principles from [Inductive] definitions.
On the other hand, functional definitions can often be more
convenient:
- Functions are by definition deterministic and defined on all
arguments; for a relation we have to _prove_ these properties
explicitly if we need them.
- With functions we can also take advantage of Coq's computation
mechanism to simplify expressions during proofs.
Furthermore, functions can be directly "extracted" from Gallina to
executable code in OCaml or Haskell.
Ultimately, the choice often comes down to either the specifics of
a particular situation or simply a question of taste. Indeed, in
large Coq developments it is common to see a definition given in
_both_ functional and relational styles, plus a lemma stating that
the two coincide, allowing further proofs to switch from one point
of view to the other at will. *)
(* ################################################################# *)
(** * Expressions With Variables *)
(** Now we return to defining Imp. The next thing we need to do is to
enrich our arithmetic and boolean expressions with variables. To
keep things simple, we'll assume that all variables are global and
that they only hold numbers. *)
(* ================================================================= *)
(** ** States *)
(** Since we'll want to look variables up to find out their current
values, we'll reuse maps from the [Maps] chapter, and
[string]s will be used to represent variables in Imp.
A _machine state_ (or just _state_) represents the current values
of _all_ variables at some point in the execution of a program. *)
(** For simplicity, we assume that the state is defined for
_all_ variables, even though any given program is only going to
mention a finite number of them. The state captures all of the
information stored in memory. For Imp programs, because each
variable stores a natural number, we can represent the state as a
mapping from strings to [nat], and will use [0] as default value
in the store. For more complex programming languages, the state
might have more structure. *)
Definition state := total_map nat.
(* ================================================================= *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum (n : nat)
| AId (x : string) (* <--- NEW *)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition W : string := "W".
Definition X : string := "X".
Definition Y : string := "Y".
Definition Z : string := "Z".
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in the chapters
developed to Imp, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is unchanged (except that it now refers
to the new [aexp]s): *)
Inductive bexp : Type :=
| BTrue
| BFalse
| BEq (a1 a2 : aexp)
| BLe (a1 a2 : aexp)
| BNot (b : bexp)
| BAnd (b1 b2 : bexp).
(* ================================================================= *)
(** ** Notations *)
(** To make Imp programs easier to read and write, we introduce some
notations and implicit coercions. You do not need to understand
exactly what these declarations do. Briefly, though:
- The [Coercion] declaration stipulates that a function (or
constructor) can be implicitly used by the type system to
coerce a value of the input type to a value of the output
type. For instance, the coercion declaration for [AId]
allows us to use plain strings when an [aexp] is expected;
the string will implicitly be wrapped with [AId].
- [Declare Custom Entry com] tells Coq to create a new
"custom grammar" for parsing Imp expressions and
programs. The first notation declaration after this tells Coq
that anything between [<{] and [}>] should be parsed using
the Imp grammar. Again, it is not necessary to understand the
details, but it is important to recognize that we are
defining _new_ interpretations for some familiar operators
like [+], [-], [*], [=], [<=], etc., when they occur between
[<{] and [}>]. *)
Coercion AId : string >-> aexp.
Coercion ANum : nat >-> aexp.
Declare Custom Entry com.
Declare Scope com_scope.
Notation "<{ e }>" := e (at level 0, e custom com at level 99) : com_scope.
Notation "( x )" := x (in custom com, x at level 99) : com_scope.
Notation "x" := x (in custom com at level 0, x constr at level 0) : com_scope.
Notation "f x .. y" := (.. (f x) .. y)
(in custom com at level 0, only parsing,
f constr at level 0, x constr at level 9,
y constr at level 9) : com_scope.
Notation "x + y" := (APlus x y) (in custom com at level 50, left associativity).
Notation "x - y" := (AMinus x y) (in custom com at level 50, left associativity).
Notation "x * y" := (AMult x y) (in custom com at level 40, left associativity).
Notation "'true'" := true (at level 1).
Notation "'true'" := BTrue (in custom com at level 0).
Notation "'false'" := false (at level 1).
Notation "'false'" := BFalse (in custom com at level 0).
Notation "x <= y" := (BLe x y) (in custom com at level 70, no associativity).
Notation "x = y" := (BEq x y) (in custom com at level 70, no associativity).
Notation "x && y" := (BAnd x y) (in custom com at level 80, left associativity).
Notation "'~' b" := (BNot b) (in custom com at level 75, right associativity).
Open Scope com_scope.
(** We can now write [3 + (X * 2)] instead of [APlus 3 (AMult X 2)],
and [true && ~(X <= 4)] instead of [BAnd true (BNot (BLe X 4))]. *)
Definition example_aexp : aexp := <{ 3 + (X * 2) }>.
Definition example_bexp : bexp := <{ true && ~(X <= 4) }>.
(** One downside of these and notation tricks -- coercions in
particular -- is that they can make it a little harder for humans
to calculate the types of expressions. If you ever find yourself
confused, try doing [Set Printing Coercions] to see exactly what
is going on. *)
Print example_bexp.
(* ===> example_bexp = <{(true && ~ (X <= 4))}> *)
Set Printing Coercions.
Print example_bexp.
(* ===> example_bexp = <{(true && ~ (AId X <= ANum 4))}> *)
Unset Printing Coercions.
(* ================================================================= *)
(** ** Evaluation *)
(** The arith and boolean evaluators are extended to handle
variables in the obvious way, taking a state as an extra
argument: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <--- NEW *)
| <{a1 + a2}> => (aeval st a1) + (aeval st a2)
| <{a1 - a2}> => (aeval st a1) - (aeval st a2)
| <{a1 * a2}> => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| <{true}> => true
| <{false}> => false
| <{a1 = a2}> => (aeval st a1) =? (aeval st a2)
| <{a1 <= a2}> => (aeval st a1) <=? (aeval st a2)
| <{~ b1}> => negb (beval st b1)
| <{b1 && b2}> => andb (beval st b1) (beval st b2)
end.
(** We specialize our notation for total maps to the specific case of
states, i.e. using [(_ !-> 0)] as empty state. *)
Definition empty_st := (_ !-> 0).
(** Now we can add a notation for a "singleton state" with just one
variable bound to a value. *)
Notation "x '!->' v" := (x !-> v ; empty_st) (at level 100).
Example aexp1 :
aeval (X !-> 5) <{ 3 + (X * 2) }>
= 13.
Proof. reflexivity. Qed.
Example aexp2 :
aeval (X !-> 5 ; Y !-> 4) <{ Z + (X * Y) }>
= 20.
Proof. reflexivity. Qed.
Example bexp1 :
beval (X !-> 5) <{ true && ~(X <= 4) }>
= true.
Proof. reflexivity. Qed.
(* ################################################################# *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (sometimes called _statements_). *)
(* ================================================================= *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar.
c := skip | x := a | c ; c | if b then c else c end
| while b do c end
*)
(** Here is the formal definition of the abstract syntax of
commands: *)
Inductive com : Type :=
| CSkip
| CAsgn (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com).
(** As for expressions, we can use a few [Notation] declarations to
make reading and writing Imp programs more convenient. *)
Notation "'skip'" :=
CSkip (in custom com at level 0) : com_scope.
Notation "x := y" :=
(CAsgn x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity) : com_scope.
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity) : com_scope.
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99) : com_scope.
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99) : com_scope.
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
<{ Z := X;
Y := 1;
while ~(Z = 0) do
Y := Y * Z;
Z := Z - 1
end }>.
Print fact_in_coq.
(* ================================================================= *)
(** ** Desugaring notations *)
(** Coq offers a rich set of features to manage the increasing
complexity of the objects we work with, such as coercions
and notations. However, their heavy usage can make for quite
overwhelming syntax. It is often instructive to "turn off"
those features to get a more elementary picture of things,
using the following commands:
- [Unset Printing Notations] (undo with [Set Printing Notations])
- [Set Printing Coercions] (undo with [Unset Printing Coercions])
- [Set Printing All] (undo with [Unset Printing All])
These commands can also be used in the middle of a proof,
to elaborate the current goal and context.
*)
Unset Printing Notations.
Print fact_in_coq.
(* ===>
fact_in_coq =
CSeq (CAsgn Z X)
(CSeq (CAsgn Y (S O))
(CWhile (BNot (BEq Z O))
(CSeq (CAsgn Y (AMult Y Z))
(CAsgn Z (AMinus Z (S O))))))
: com *)
Set Printing Notations.
Set Printing Coercions.
Print fact_in_coq.
(* ===>
fact_in_coq =
<{ Z := (AId X);
Y := (ANum 1);
while ~ (AId Z) = (ANum 0) do
Y := (AId Y) * (AId Z);
Z := (AId Z) - (ANum 1)
end }>
: com *)
Unset Printing Coercions.
(* ================================================================= *)
(** ** The [Locate] command *)
(* ----------------------------------------------------------------- *)
(** *** Finding notations *)
(** When faced with unknown notation, use [Locate] with a _string_
containing one of its symbols to see its possible interpretations. *)
Locate "&&".
(* ===>
Notation
"x && y" := BAnd x y (default interpretation)
"x && y" := andb x y : bool_scope (default interpretation)
*)
Locate ";".
(* ===>
Notation
"x '|->' v ';' m" := update m x v (default interpretation)
"x ; y" := CSeq x y : com_scope (default interpretation)
"x '!->' v ';' m" := t_update m x v (default interpretation)
"[ x ; y ; .. ; z ]" := cons x (cons y .. (cons z nil) ..) : list_scope
(default interpretation) *)
Locate "while".
(* ===>
Notation
"'while' x 'do' y 'end'" := CWhile x y : com_scope (default interpretation)
"'_' '!->' v" := t_empty v (default interpretation)
*)
(* ----------------------------------------------------------------- *)
(** *** Finding identifiers *)
(** When used with an identifier, the command [Locate] prints
the full path to every value in scope with the same name.
This is useful to troubleshoot problems due to variable
shadowing. *)
Locate aexp.
(* ===>
Inductive LF.Imp.aexp
Inductive LF.Imp.AExp.aexp
(shorter name to refer to it in current context is AExp.aexp)
Inductive LF.Imp.aevalR_division.aexp
(shorter name to refer to it in current context is aevalR_division.aexp)
Inductive LF.Imp.aevalR_extended.aexp
(shorter name to refer to it in current context is aevalR_extended.aexp)
*)
(* ================================================================= *)
(** ** More Examples *)
(** Assignment: *)
Definition plus2 : com :=
<{ X := X + 2 }>.
Definition XtimesYinZ : com :=
<{ Z := X * Y }>.
Definition subtract_slowly_body : com :=
<{ Z := Z - 1 ;
X := X - 1 }>.
(* ----------------------------------------------------------------- *)
(** *** Loops *)
Definition subtract_slowly : com :=
<{ while ~(X = 0) do
subtract_slowly_body
end }>.
Definition subtract_3_from_5_slowly : com :=
<{ X := 3 ;
Z := 5 ;
subtract_slowly }>.
(* ----------------------------------------------------------------- *)
(** *** An infinite loop: *)
Definition loop : com :=
<{ while true do
skip
end }>.
(* ################################################################# *)
(** * Evaluating Commands *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [while] loops don't necessarily terminate makes
defining an evaluation function tricky... *)
(* ================================================================= *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [while] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| <{ skip }> =>
st
| <{ x := a }> =>
(x !-> (aeval st a) ; st)
| <{ c1 ; c2 }> =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| <{ if b then c1 else c2 end}> =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| <{ while b do c end }> =>
st (* bogus *)
end.
(** In a traditional functional programming language like OCaml or
Haskell we could add the [while] case as follows:
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| <{ while b do c end}> =>
if (beval st b)
then ceval_fun st <{c ; while b do c end}>
else st
end.
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it _doesn't_ always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming language
but also a consistent logic, any potentially non-terminating
function needs to be rejected. Here is an (invalid!) program
showing what would go wrong if Coq allowed non-terminating
recursive functions:
Fixpoint loop_false (n : nat) : False := loop_false n.
That is, propositions like [False] would become provable
([loop_false 0] would be a proof of [False]), which would be
a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, [ceval_fun]
cannot be written in Coq -- at least not without additional tricks
and workarounds (see chapter [ImpCEvalFun] if you're curious
about what those might be). *)
(* ================================================================= *)
(** ** Evaluation as a Relation *)
(** Here's a better way: define [ceval] as a _relation_ rather than a
_function_ -- i.e., define it in [Prop] instead of [Type], as we
did for [aevalR] above. *)
(** This is an important change. Besides freeing us from awkward
workarounds, it gives us a lot more flexibility in the definition.
For example, if we add nondeterministic features like [any] to the
language, we want the definition of evaluation to be
nondeterministic -- i.e., not only will it not be total, it will
not even be a function! *)
(** We'll use the notation [st =[ c ]=> st'] for the [ceval] relation:
[st =[ c ]=> st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']". *)
(* ----------------------------------------------------------------- *)
(** *** Operational Semantics *)
(** Here is an informal definition of evaluation, presented as inference
rules for readability:
----------------- (E_Skip)
st =[ skip ]=> st
aeval st a = n
------------------------------- (E_Asgn)
st =[ x := a ]=> (x !-> n ; st)
st =[ c1 ]=> st'
st' =[ c2 ]=> st''
--------------------- (E_Seq)
st =[ c1;c2 ]=> st''
beval st b = true
st =[ c1 ]=> st'
-------------------------------------- (E_IfTrue)
st =[ if b then c1 else c2 end ]=> st'
beval st b = false
st =[ c2 ]=> st'
-------------------------------------- (E_IfFalse)
st =[ if b then c1 else c2 end ]=> st'
beval st b = false
----------------------------- (E_WhileFalse)
st =[ while b do c end ]=> st
beval st b = true
st =[ c ]=> st'
st' =[ while b do c end ]=> st''
-------------------------------- (E_WhileTrue)
st =[ while b do c end ]=> st''
*)
(** Here is the formal definition. Make sure you understand
how it corresponds to the inference rules. *)
Reserved Notation
"st '=[' c ']=>' st'"
(at level 40, c custom com at level 99,
st constr, st' constr at next level).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
st =[ skip ]=> st
| E_Asgn : forall st a n x,
aeval st a = n ->
st =[ x := a ]=> (x !-> n ; st)
| E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ; c2 ]=> st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
st =[ c1 ]=> st' ->
st =[ if b then c1 else c2 end]=> st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
st =[ c2 ]=> st' ->
st =[ if b then c1 else c2 end]=> st'
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ while b do c end ]=> st
| E_WhileTrue : forall st st' st'' b c,
beval st b = true ->
st =[ c ]=> st' ->
st' =[ while b do c end ]=> st'' ->
st =[ while b do c end ]=> st''
where "st =[ c ]=> st'" := (ceval c st st').
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
empty_st =[
X := 2;
if (X <= 1)
then Y := 3
else Z := 4
end
]=> (Z !-> 4 ; X !-> 2).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (X !-> 2).
- (* assignment command *)
apply E_Asgn. reflexivity.
- (* if command *)
apply E_IfFalse.
reflexivity.
apply E_Asgn. reflexivity.
Qed.
(** **** Exercise: 2 stars, standard (ceval_example2) *)
Example ceval_example2:
empty_st =[
X := 0;
Y := 1;
Z := 2
]=> (Z !-> 2 ; Y !-> 1 ; X !-> 0).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Set Printing Implicit.
Check @ceval_example2.
(** **** Exercise: 3 stars, standard, optional (pup_to_n)
Write an Imp program that sums the numbers from [1] to [X]
(inclusive: [1 + 2 + ... + X]) in the variable [Y]. Your program
should update the state as shown in theorem [pup_to_2_ceval],
which you can reverse-engineer to discover the program you should
write. The proof of that theorem will be somewhat lengthy. *)
Definition pup_to_n : com
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem pup_to_2_ceval :
(X !-> 2) =[
pup_to_n
]=> (X !-> 0 ; Y !-> 3 ; X !-> 1 ; Y !-> 2 ; Y !-> 0 ; X !-> 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it frees us from the artificial
requirement that evaluation should be a total function. But it
also raises a question: Is the second definition of evaluation
really a partial _function_? Or is it possible that, beginning from
the same state [st], we could evaluate some command [c] in
different ways to reach two different output states [st'] and
[st'']?
In fact, this cannot happen: [ceval] _is_ a partial function: *)
Theorem ceval_deterministic: forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
induction E1; intros st2 E2; inversion E2; subst.
- (* E_Skip *) reflexivity.
- (* E_Asgn *) reflexivity.
- (* E_Seq *)
rewrite (IHE1_1 st'0 H1) in *.
apply IHE1_2. assumption.
- (* E_IfTrue, b evaluates to true *)
apply IHE1. assumption.
- (* E_IfTrue, b evaluates to false (contradiction) *)
rewrite H in H5. discriminate.
- (* E_IfFalse, b evaluates to true (contradiction) *)
rewrite H in H5. discriminate.
- (* E_IfFalse, b evaluates to false *)
apply IHE1. assumption.
- (* E_WhileFalse, b evaluates to false *)
reflexivity.
- (* E_WhileFalse, b evaluates to true (contradiction) *)
rewrite H in H2. discriminate.
- (* E_WhileTrue, b evaluates to false (contradiction) *)
rewrite H in H4. discriminate.
- (* E_WhileTrue, b evaluates to true *)
rewrite (IHE1_1 st'0 H3) in *.
apply IHE1_2. assumption. Qed.
(* ################################################################# *)
(** * Reasoning About Imp Programs *)
(** We'll get deeper into more systematic and powerful techniques for
reasoning about Imp programs in _Programming Language
Foundations_, but we can get some distance just working with the
bare definitions. This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
st =[ plus2 ]=> st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(** Inverting [Heval] essentially forces Coq to expand one step of
the [ceval] computation -- in this case revealing that [st']
must be [st] extended with the new value of [X], since [plus2]
is an assignment. *)
inversion Heval. subst. clear Heval. simpl.
apply t_update_eq. Qed.
(** **** Exercise: 3 stars, standard, optional (XtimesYinZ_spec)
State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_XtimesYinZ_spec : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, standard, especially useful (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(st =[ loop ]=> st').
Proof.
intros st st' contra. unfold loop in contra.
remember <{ while true do skip end }> as loopdef
eqn:Heqloopdef.
(** Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[discriminate]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (no_whiles_eqv)
Consider the following function: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| <{ skip }> =>
true
| <{ _ := _ }> =>
true
| <{ c1 ; c2 }> =>
andb (no_whiles c1) (no_whiles c2)
| <{ if _ then ct else cf end }> =>
andb (no_whiles ct) (no_whiles cf)
| <{ while _ do _ end }> =>
false
end.
(** This predicate yields [true] just on programs that have no while
loops. Using [Inductive], write a property [no_whilesR] such that
[no_whilesR c] is provable exactly when [c] is a program with no
while loops. Then prove its equivalence with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard (no_whiles_terminating)
Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this.
Use either [no_whiles] or [no_whilesR], as you prefer. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_no_whiles_terminating : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars, standard (stack_compiler)
Old HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a _stack_. For instance, the expression
(2*3)+(3*(4-2))
would be written as
2 3 * 3 4 2 - * +
and evaluated like this (where we show the program being evaluated
on the right and the contents of the stack on the left):
[ ] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
The goal of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract the first number from the second.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush (n : nat)
| SLoad (x : string)
| SPlus
| SMinus
| SMult.
(** Write a function to evaluate programs in the stack language. It
should take as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and it should return the
stack after executing the program. Test your function on the
examples below.
Note that it is unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
fewer than two elements. In a sense, it is immaterial what we do,
since a correct compiler will never emit such a malformed program.
But for sake of later exercises, it would be best to skip the
offending instruction and continue with the next one. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Check s_execute.
Example s_execute1 :
s_execute empty_st []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (X !-> 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function that compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile <{ X - (2 * Y) }>
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (execute_app) *)
(** Execution can be decomposed in the following sense: executing
stack program [p1 ++ p2] is the same as executing [p1], taking
the resulting stack, and executing [p2] from that stack. Prove
that fact. *)
Theorem execute_app : forall st p1 p2 stack,
s_execute st stack (p1 ++ p2) = s_execute st (s_execute st stack p1) p2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (stack_compiler_correct) *)
(** Now we'll prove the correctness of the compiler implemented in the
previous exercise. Begin by proving the following lemma. If it
becomes difficult, consider whether your implementation of
[s_execute] or [s_compile] could be simplified. *)
Lemma s_compile_correct_aux : forall st e stack,
s_execute st stack (s_compile e) = aeval st e :: stack.
Proof.
(* FILL IN HERE *) Admitted.
(** The main theorem should be a very easy corollary of that lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (short_circuit)
Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. (N.b. This is only true because expression
evaluation in Imp is rather simple. In a bigger language where
evaluating an expression might diverge, the short-circuiting [BAnd]
would _not_ be equivalent to the original, since it would make more
programs terminate.) *)
(* FILL IN HERE
[] *)
Module BreakImp.
(** **** Exercise: 4 stars, advanced (break_imp)
Imperative languages like C and Java often include a [break] or
similar statement for interrupting the execution of loops. In this
exercise we consider how to add [break] to Imp. First, we need to
enrich the language of commands with an additional case. *)
Inductive com : Type :=
| CSkip
| CBreak (* <--- NEW *)
| CAsgn (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com).
Notation "'break'" := CBreak (in custom com at level 0).
Notation "'skip'" :=
CSkip (in custom com at level 0) : com_scope.
Notation "x := y" :=
(CAsgn x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity) : com_scope.
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity) : com_scope.
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99) : com_scope.
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99) : com_scope.
(** Next, we need to define the behavior of [break]. Informally,
whenever [break] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop should terminate. (If there aren't any
enclosing loops, then the whole program simply terminates.) The
final state should be the same as the one in which the [break]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [break]. In those cases, [break] should only
terminate the _innermost_ loop. Thus, after executing the
following...
X := 0;
Y := 1;
while ~(0 = Y) do
while true do
break
end;
X := 1;
Y := Y - 1
end
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [break] statement: *)
Inductive result : Type :=
| SContinue
| SBreak.
Reserved Notation "st '=[' c ']=>' st' '/' s"
(at level 40, c custom com at level 99, st' constr at next level).
(** Intuitively, [st =[ c ]=> st' / s] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that the innermost surrounding loop (or the whole program) should
exit immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[st =[ c ]=> st' / s]" relation is very
similar to the one we gave above for the regular evaluation
relation ([st =[ c ]=> st']) -- we just need to handle the
termination signals appropriately:
- If the command is [skip], then the state doesn't change and
execution of any enclosing loop can continue normally.
- If the command is [break], the state stays unchanged but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [if b then c1 else c2 end], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state is the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal
generated there.
- Finally, for a loop of the form [while b do c end], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [break] only terminates the
innermost loop, [while] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> result -> state -> Prop :=
| E_Skip : forall st,
st =[ CSkip ]=> st / SContinue
(* FILL IN HERE *)
where "st '=[' c ']=>' st' '/' s" := (ceval c st s st').
(** Now prove the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
st =[ break; c ]=> st' / s ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
st =[ while b do c end ]=> st' / s ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
st =[ c ]=> st' / SBreak ->
st =[ while b do c end ]=> st' / SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem seq_continue : forall c1 c2 st st' st'',
st =[ c1 ]=> st' / SContinue ->
st' =[ c2 ]=> st'' / SContinue ->
st =[ c1 ; c2 ]=> st'' / SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem seq_stops_on_break : forall c1 c2 st st',
st =[ c1 ]=> st' / SBreak ->
st =[ c1 ; c2 ]=> st' / SBreak.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
st =[ while b do c end ]=> st' / SContinue ->
beval st' b = true ->
exists st'', st'' =[ c ]=> st' / SBreak.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
st =[ c ]=> st1 / s1 ->
st =[ c ]=> st2 / s2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End BreakImp.
(** **** Exercise: 4 stars, standard, optional (add_for_loop)
Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this
file are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE
[] *)
(* 2021-08-11 15:08 *)
|
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_std.v
// /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v1_8_ddr3_7Series, Coregen 14.4" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_8,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=2500, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=1.8V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8jtf12864hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *)
module mig_7series_v1_8_memc_ui_top_std #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter IODELAY_HP_MODE = "ON",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'hF,
parameter [3:0] BYTE_LANES_B1 = 4'hF,
parameter [3:0] BYTE_LANES_B2 = 4'hF,
parameter [3:0] BYTE_LANES_B3 = 4'hF,
parameter [3:0] BYTE_LANES_B4 = 4'hF,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
// Clock and reset ports
input clk,
input clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// temperature monitor ports
input [11:0] device_temp,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data
);
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
(* keep = "true", max_fanout = 30 *) reg reset;
//***************************************************************************
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v1_8_mem_intfc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT)
)
mem_intfc0
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
.device_temp (device_temp),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
);
mig_7series_v1_8_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
stream_in_TDATA,
stream_in_TVALID,
stream_in_TREADY,
stream_in_TKEEP,
stream_in_TSTRB,
stream_in_TUSER,
stream_in_TLAST,
stream_in_TID,
stream_in_TDEST,
img_rows_V_dout,
img_rows_V_empty_n,
img_rows_V_read,
img_cols_V_dout,
img_cols_V_empty_n,
img_cols_V_read,
img_data_stream_0_V_din,
img_data_stream_0_V_full_n,
img_data_stream_0_V_write,
img_data_stream_1_V_din,
img_data_stream_1_V_full_n,
img_data_stream_1_V_write,
img_data_stream_2_V_din,
img_data_stream_2_V_full_n,
img_data_stream_2_V_write,
img_rows_V_out_din,
img_rows_V_out_full_n,
img_rows_V_out_write,
img_cols_V_out_din,
img_cols_V_out_full_n,
img_cols_V_out_write
);
parameter ap_ST_fsm_state1 = 8'd1;
parameter ap_ST_fsm_state2 = 8'd2;
parameter ap_ST_fsm_state3 = 8'd4;
parameter ap_ST_fsm_state4 = 8'd8;
parameter ap_ST_fsm_pp1_stage0 = 8'd16;
parameter ap_ST_fsm_state7 = 8'd32;
parameter ap_ST_fsm_pp2_stage0 = 8'd64;
parameter ap_ST_fsm_state10 = 8'd128;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [23:0] stream_in_TDATA;
input stream_in_TVALID;
output stream_in_TREADY;
input [2:0] stream_in_TKEEP;
input [2:0] stream_in_TSTRB;
input [0:0] stream_in_TUSER;
input [0:0] stream_in_TLAST;
input [0:0] stream_in_TID;
input [0:0] stream_in_TDEST;
input [15:0] img_rows_V_dout;
input img_rows_V_empty_n;
output img_rows_V_read;
input [15:0] img_cols_V_dout;
input img_cols_V_empty_n;
output img_cols_V_read;
output [7:0] img_data_stream_0_V_din;
input img_data_stream_0_V_full_n;
output img_data_stream_0_V_write;
output [7:0] img_data_stream_1_V_din;
input img_data_stream_1_V_full_n;
output img_data_stream_1_V_write;
output [7:0] img_data_stream_2_V_din;
input img_data_stream_2_V_full_n;
output img_data_stream_2_V_write;
output [15:0] img_rows_V_out_din;
input img_rows_V_out_full_n;
output img_rows_V_out_write;
output [15:0] img_cols_V_out_din;
input img_cols_V_out_full_n;
output img_cols_V_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg img_rows_V_read;
reg img_cols_V_read;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg img_rows_V_out_write;
reg img_cols_V_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg [23:0] AXI_video_strm_V_data_V_0_data_out;
wire AXI_video_strm_V_data_V_0_vld_in;
wire AXI_video_strm_V_data_V_0_vld_out;
wire AXI_video_strm_V_data_V_0_ack_in;
reg AXI_video_strm_V_data_V_0_ack_out;
reg [23:0] AXI_video_strm_V_data_V_0_payload_A;
reg [23:0] AXI_video_strm_V_data_V_0_payload_B;
reg AXI_video_strm_V_data_V_0_sel_rd;
reg AXI_video_strm_V_data_V_0_sel_wr;
wire AXI_video_strm_V_data_V_0_sel;
wire AXI_video_strm_V_data_V_0_load_A;
wire AXI_video_strm_V_data_V_0_load_B;
reg [1:0] AXI_video_strm_V_data_V_0_state;
wire AXI_video_strm_V_data_V_0_state_cmp_full;
reg [0:0] AXI_video_strm_V_user_V_0_data_out;
wire AXI_video_strm_V_user_V_0_vld_in;
wire AXI_video_strm_V_user_V_0_vld_out;
wire AXI_video_strm_V_user_V_0_ack_in;
reg AXI_video_strm_V_user_V_0_ack_out;
reg [0:0] AXI_video_strm_V_user_V_0_payload_A;
reg [0:0] AXI_video_strm_V_user_V_0_payload_B;
reg AXI_video_strm_V_user_V_0_sel_rd;
reg AXI_video_strm_V_user_V_0_sel_wr;
wire AXI_video_strm_V_user_V_0_sel;
wire AXI_video_strm_V_user_V_0_load_A;
wire AXI_video_strm_V_user_V_0_load_B;
reg [1:0] AXI_video_strm_V_user_V_0_state;
wire AXI_video_strm_V_user_V_0_state_cmp_full;
reg [0:0] AXI_video_strm_V_last_V_0_data_out;
wire AXI_video_strm_V_last_V_0_vld_in;
wire AXI_video_strm_V_last_V_0_vld_out;
wire AXI_video_strm_V_last_V_0_ack_in;
reg AXI_video_strm_V_last_V_0_ack_out;
reg [0:0] AXI_video_strm_V_last_V_0_payload_A;
reg [0:0] AXI_video_strm_V_last_V_0_payload_B;
reg AXI_video_strm_V_last_V_0_sel_rd;
reg AXI_video_strm_V_last_V_0_sel_wr;
wire AXI_video_strm_V_last_V_0_sel;
wire AXI_video_strm_V_last_V_0_load_A;
wire AXI_video_strm_V_last_V_0_load_B;
reg [1:0] AXI_video_strm_V_last_V_0_state;
wire AXI_video_strm_V_last_V_0_state_cmp_full;
wire AXI_video_strm_V_dest_V_0_vld_in;
reg AXI_video_strm_V_dest_V_0_ack_out;
reg [1:0] AXI_video_strm_V_dest_V_0_state;
reg stream_in_TDATA_blk_n;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_pp1_stage0;
reg ap_enable_reg_pp1_iter1;
wire ap_block_pp1_stage0;
reg [0:0] exitcond_i_reg_442;
reg [0:0] brmerge_i_reg_451;
wire ap_CS_fsm_pp2_stage0;
reg ap_enable_reg_pp2_iter1;
wire ap_block_pp2_stage0;
reg [0:0] eol_2_i_reg_270;
reg img_rows_V_blk_n;
reg img_cols_V_blk_n;
reg img_data_stream_0_V_blk_n;
reg img_data_stream_1_V_blk_n;
reg img_data_stream_2_V_blk_n;
reg img_rows_V_out_blk_n;
reg img_cols_V_out_blk_n;
reg [10:0] t_V_2_reg_200;
reg [0:0] eol_i_reg_211;
reg [0:0] eol_reg_223;
reg [23:0] axi_data_V_1_i_reg_234;
reg [0:0] axi_last_V_3_i_reg_281;
reg [23:0] axi_data_V_3_i_reg_293;
wire [11:0] tmp_fu_315_p1;
reg [11:0] tmp_reg_403;
reg ap_block_state1;
wire [11:0] tmp_44_fu_319_p1;
reg [11:0] tmp_44_reg_408;
reg [23:0] tmp_data_V_reg_413;
reg [0:0] tmp_last_V_reg_421;
wire [0:0] exitcond2_i_fu_336_p2;
wire ap_CS_fsm_state4;
wire [10:0] i_V_fu_341_p2;
reg [10:0] i_V_reg_437;
wire [0:0] exitcond_i_fu_351_p2;
wire ap_block_state5_pp1_stage0_iter0;
reg ap_predicate_op75_read_state6;
reg ap_block_state6_pp1_stage0_iter1;
reg ap_block_pp1_stage0_11001;
wire [10:0] j_V_fu_356_p2;
reg ap_enable_reg_pp1_iter0;
wire [0:0] brmerge_i_fu_365_p2;
wire ap_block_state8_pp2_stage0_iter0;
reg ap_block_state9_pp2_stage0_iter1;
reg ap_block_pp2_stage0_11001;
reg ap_block_pp1_stage0_subdone;
reg ap_enable_reg_pp2_iter0;
wire ap_CS_fsm_state7;
reg ap_block_pp2_stage0_subdone;
reg [0:0] ap_phi_mux_eol_2_i_phi_fu_273_p4;
reg [0:0] axi_last_V1_i_reg_169;
wire ap_CS_fsm_state10;
wire ap_CS_fsm_state3;
reg [23:0] axi_data_V1_i_reg_179;
reg [10:0] t_V_reg_189;
reg [0:0] ap_phi_mux_eol_i_phi_fu_215_p4;
reg [0:0] ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
reg [23:0] ap_phi_mux_p_Val2_s_phi_fu_262_p4;
wire [0:0] ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
wire [23:0] ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
reg ap_block_pp1_stage0_01001;
reg [0:0] sof_1_i_fu_98;
wire [11:0] t_V_cast_i_fu_332_p1;
wire [11:0] t_V_3_cast_i_fu_347_p1;
wire [0:0] tmp_user_V_fu_323_p1;
reg [7:0] ap_NS_fsm;
reg ap_idle_pp1;
wire ap_enable_pp1;
reg ap_idle_pp2;
wire ap_enable_pp2;
reg ap_condition_529;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 8'd1;
#0 AXI_video_strm_V_data_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_data_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_data_V_0_state = 2'd0;
#0 AXI_video_strm_V_user_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_user_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_user_V_0_state = 2'd0;
#0 AXI_video_strm_V_last_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_last_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_last_V_0_state = 2'd0;
#0 AXI_video_strm_V_dest_V_0_state = 2'd0;
#0 ap_enable_reg_pp1_iter1 = 1'b0;
#0 ap_enable_reg_pp2_iter1 = 1'b0;
#0 ap_enable_reg_pp1_iter0 = 1'b0;
#0 ap_enable_reg_pp2_iter0 = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out))) begin
AXI_video_strm_V_data_V_0_sel_rd <= ~AXI_video_strm_V_data_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_data_V_0_ack_in) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in))) begin
AXI_video_strm_V_data_V_0_sel_wr <= ~AXI_video_strm_V_data_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_data_V_0_state)) | ((2'd1 == AXI_video_strm_V_data_V_0_state) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_data_V_0_state) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_data_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_dest_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_dest_V_0_state)) | ((2'd1 == AXI_video_strm_V_dest_V_0_state) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_dest_V_0_state) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_dest_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_out))) begin
AXI_video_strm_V_last_V_0_sel_rd <= ~AXI_video_strm_V_last_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_last_V_0_ack_in) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in))) begin
AXI_video_strm_V_last_V_0_sel_wr <= ~AXI_video_strm_V_last_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_last_V_0_state)) | ((2'd1 == AXI_video_strm_V_last_V_0_state) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_last_V_0_state) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_last_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_out))) begin
AXI_video_strm_V_user_V_0_sel_rd <= ~AXI_video_strm_V_user_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_user_V_0_ack_in) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in))) begin
AXI_video_strm_V_user_V_0_sel_wr <= ~AXI_video_strm_V_user_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_user_V_0_state)) | ((2'd1 == AXI_video_strm_V_user_V_0_state) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_user_V_0_state) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_user_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp1_iter0 <= 1'b0;
end else begin
if (((exitcond_i_fu_351_p2 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_enable_reg_pp1_iter0 <= 1'b0;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
ap_enable_reg_pp1_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp1_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
ap_enable_reg_pp1_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp2_iter0 <= 1'b0;
end else begin
if (((ap_phi_mux_eol_2_i_phi_fu_273_p4 == 1'd1) & (1'b0 == ap_block_pp2_stage0_subdone) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_enable_reg_pp2_iter0 <= 1'b0;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
ap_enable_reg_pp2_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp2_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
ap_enable_reg_pp2_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
axi_data_V1_i_reg_179 <= tmp_data_V_reg_413;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
axi_data_V1_i_reg_179 <= axi_data_V_3_i_reg_293;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
axi_data_V_1_i_reg_234 <= ap_phi_mux_p_Val2_s_phi_fu_262_p4;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
axi_data_V_1_i_reg_234 <= axi_data_V1_i_reg_179;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
axi_data_V_3_i_reg_293 <= axi_data_V_1_i_reg_234;
end else if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
axi_data_V_3_i_reg_293 <= AXI_video_strm_V_data_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
axi_last_V1_i_reg_169 <= tmp_last_V_reg_421;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
axi_last_V1_i_reg_169 <= axi_last_V_3_i_reg_281;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
axi_last_V_3_i_reg_281 <= eol_reg_223;
end else if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
axi_last_V_3_i_reg_281 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
eol_2_i_reg_270 <= eol_i_reg_211;
end else if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
eol_2_i_reg_270 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
eol_i_reg_211 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
eol_i_reg_211 <= 1'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
eol_reg_223 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
eol_reg_223 <= axi_last_V1_i_reg_169;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_fu_351_p2 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
sof_1_i_fu_98 <= 1'd0;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
sof_1_i_fu_98 <= 1'd1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_fu_351_p2 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
t_V_2_reg_200 <= j_V_fu_356_p2;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
t_V_2_reg_200 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
t_V_reg_189 <= 11'd0;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
t_V_reg_189 <= i_V_reg_437;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_load_A)) begin
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_load_B)) begin
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_load_A)) begin
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_load_B)) begin
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_load_A)) begin
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_load_B)) begin
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_fu_351_p2 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
brmerge_i_reg_451 <= brmerge_i_fu_365_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
exitcond_i_reg_442 <= exitcond_i_fu_351_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state4)) begin
i_V_reg_437 <= i_V_fu_341_p2;
end
end
always @ (posedge ap_clk) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
tmp_44_reg_408 <= tmp_44_fu_319_p1;
tmp_reg_403 <= tmp_fu_315_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
tmp_data_V_reg_413 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_421 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_data_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_data_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_sel)) begin
AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_B;
end else begin
AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_A;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_dest_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_dest_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_last_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_last_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_sel)) begin
AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_B;
end else begin
AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_A;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_user_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_user_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_sel)) begin
AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_B;
end else begin
AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_A;
end
end
always @ (*) begin
if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0))) begin
ap_idle_pp1 = 1'b1;
end else begin
ap_idle_pp1 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0))) begin
ap_idle_pp2 = 1'b1;
end else begin
ap_idle_pp2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_condition_529)) begin
if ((brmerge_i_reg_451 == 1'd1)) begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = eol_reg_223;
end else if ((brmerge_i_reg_451 == 1'd0)) begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = AXI_video_strm_V_last_V_0_data_out;
end else begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end
end else begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end
end
always @ (*) begin
if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_phi_mux_eol_2_i_phi_fu_273_p4 = AXI_video_strm_V_last_V_0_data_out;
end else begin
ap_phi_mux_eol_2_i_phi_fu_273_p4 = eol_2_i_reg_270;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_phi_mux_eol_i_phi_fu_215_p4 = ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
end else begin
ap_phi_mux_eol_i_phi_fu_215_p4 = eol_i_reg_211;
end
end
always @ (*) begin
if ((1'b1 == ap_condition_529)) begin
if ((brmerge_i_reg_451 == 1'd1)) begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = axi_data_V_1_i_reg_234;
end else if ((brmerge_i_reg_451 == 1'd0)) begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = AXI_video_strm_V_data_V_0_data_out;
end else begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end
end else begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_blk_n = img_cols_V_empty_n;
end else begin
img_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_out_blk_n = img_cols_V_out_full_n;
end else begin
img_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_out_write = 1'b1;
end else begin
img_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_read = 1'b1;
end else begin
img_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_0_V_blk_n = img_data_stream_0_V_full_n;
end else begin
img_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_0_V_write = 1'b1;
end else begin
img_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_1_V_blk_n = img_data_stream_1_V_full_n;
end else begin
img_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_1_V_write = 1'b1;
end else begin
img_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_2_V_blk_n = img_data_stream_2_V_full_n;
end else begin
img_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_2_V_write = 1'b1;
end else begin
img_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_blk_n = img_rows_V_empty_n;
end else begin
img_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_out_blk_n = img_rows_V_out_full_n;
end else begin
img_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_out_write = 1'b1;
end else begin
img_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_read = 1'b1;
end else begin
img_rows_V_read = 1'b0;
end
end
always @ (*) begin
if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) | ((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((brmerge_i_reg_451 == 1'd0) & (exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)))) begin
stream_in_TDATA_blk_n = AXI_video_strm_V_data_V_0_state[1'd0];
end else begin
stream_in_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((tmp_user_V_fu_323_p1 == 1'd0) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else if (((tmp_user_V_fu_323_p1 == 1'd1) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state3;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end
end
ap_ST_fsm_pp1_stage0 : begin
if (~((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end else if (((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_NS_fsm = ap_ST_fsm_state7;
end else begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end
ap_ST_fsm_pp2_stage0 : begin
if (~((1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end else if (((1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_NS_fsm = ap_ST_fsm_state10;
end else begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end
end
ap_ST_fsm_state10 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign AXI_video_strm_V_data_V_0_ack_in = AXI_video_strm_V_data_V_0_state[1'd1];
assign AXI_video_strm_V_data_V_0_load_A = (~AXI_video_strm_V_data_V_0_sel_wr & AXI_video_strm_V_data_V_0_state_cmp_full);
assign AXI_video_strm_V_data_V_0_load_B = (AXI_video_strm_V_data_V_0_state_cmp_full & AXI_video_strm_V_data_V_0_sel_wr);
assign AXI_video_strm_V_data_V_0_sel = AXI_video_strm_V_data_V_0_sel_rd;
assign AXI_video_strm_V_data_V_0_state_cmp_full = ((AXI_video_strm_V_data_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_data_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_data_V_0_vld_out = AXI_video_strm_V_data_V_0_state[1'd0];
assign AXI_video_strm_V_dest_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_last_V_0_ack_in = AXI_video_strm_V_last_V_0_state[1'd1];
assign AXI_video_strm_V_last_V_0_load_A = (~AXI_video_strm_V_last_V_0_sel_wr & AXI_video_strm_V_last_V_0_state_cmp_full);
assign AXI_video_strm_V_last_V_0_load_B = (AXI_video_strm_V_last_V_0_state_cmp_full & AXI_video_strm_V_last_V_0_sel_wr);
assign AXI_video_strm_V_last_V_0_sel = AXI_video_strm_V_last_V_0_sel_rd;
assign AXI_video_strm_V_last_V_0_state_cmp_full = ((AXI_video_strm_V_last_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_last_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_last_V_0_vld_out = AXI_video_strm_V_last_V_0_state[1'd0];
assign AXI_video_strm_V_user_V_0_ack_in = AXI_video_strm_V_user_V_0_state[1'd1];
assign AXI_video_strm_V_user_V_0_load_A = (~AXI_video_strm_V_user_V_0_sel_wr & AXI_video_strm_V_user_V_0_state_cmp_full);
assign AXI_video_strm_V_user_V_0_load_B = (AXI_video_strm_V_user_V_0_state_cmp_full & AXI_video_strm_V_user_V_0_sel_wr);
assign AXI_video_strm_V_user_V_0_sel = AXI_video_strm_V_user_V_0_sel_rd;
assign AXI_video_strm_V_user_V_0_state_cmp_full = ((AXI_video_strm_V_user_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_user_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_user_V_0_vld_out = AXI_video_strm_V_user_V_0_state[1'd0];
assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state10 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state7 = ap_CS_fsm[32'd5];
assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp1_stage0_01001 = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
always @ (*) begin
ap_block_pp1_stage0_11001 = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
always @ (*) begin
ap_block_pp1_stage0_subdone = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp2_stage0_11001 = ((eol_2_i_reg_270 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_enable_reg_pp2_iter1 == 1'b1));
end
always @ (*) begin
ap_block_pp2_stage0_subdone = ((eol_2_i_reg_270 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_enable_reg_pp2_iter1 == 1'b1));
end
always @ (*) begin
ap_block_state1 = ((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state5_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state6_pp1_stage0_iter1 = (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0)));
end
assign ap_block_state8_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state9_pp2_stage0_iter1 = ((eol_2_i_reg_270 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out));
end
always @ (*) begin
ap_condition_529 = ((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0));
end
assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
assign ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245 = 'bx;
assign ap_phi_reg_pp1_iter1_p_Val2_s_reg_258 = 'bx;
always @ (*) begin
ap_predicate_op75_read_state6 = ((brmerge_i_reg_451 == 1'd0) & (exitcond_i_reg_442 == 1'd0));
end
assign ap_ready = internal_ap_ready;
assign brmerge_i_fu_365_p2 = (sof_1_i_fu_98 | ap_phi_mux_eol_i_phi_fu_215_p4);
assign exitcond2_i_fu_336_p2 = ((t_V_cast_i_fu_332_p1 == tmp_reg_403) ? 1'b1 : 1'b0);
assign exitcond_i_fu_351_p2 = ((t_V_3_cast_i_fu_347_p1 == tmp_44_reg_408) ? 1'b1 : 1'b0);
assign i_V_fu_341_p2 = (t_V_reg_189 + 11'd1);
assign img_cols_V_out_din = img_cols_V_dout;
assign img_data_stream_0_V_din = ap_phi_mux_p_Val2_s_phi_fu_262_p4[7:0];
assign img_data_stream_1_V_din = {{ap_phi_mux_p_Val2_s_phi_fu_262_p4[15:8]}};
assign img_data_stream_2_V_din = {{ap_phi_mux_p_Val2_s_phi_fu_262_p4[23:16]}};
assign img_rows_V_out_din = img_rows_V_dout;
assign j_V_fu_356_p2 = (t_V_2_reg_200 + 11'd1);
assign start_out = real_start;
assign stream_in_TREADY = AXI_video_strm_V_dest_V_0_state[1'd1];
assign t_V_3_cast_i_fu_347_p1 = t_V_2_reg_200;
assign t_V_cast_i_fu_332_p1 = t_V_reg_189;
assign tmp_44_fu_319_p1 = img_cols_V_dout[11:0];
assign tmp_fu_315_p1 = img_rows_V_dout[11:0];
assign tmp_user_V_fu_323_p1 = AXI_video_strm_V_user_V_0_data_out;
endmodule //AXIvideo2Mat
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1
// RDY_server_reset_response_get O 1 reg
// imem_valid O 1
// imem_is_i32_not_i16 O 1 const
// imem_pc O 64 reg
// imem_instr O 32
// imem_exc O 1
// imem_exc_code O 4 reg
// imem_tval O 64 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 4 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 4 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// dmem_valid O 1
// dmem_word64 O 64
// dmem_st_amo_val O 64
// dmem_exc O 1
// dmem_exc_code O 4 reg
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// RDY_server_fence_i_request_put O 1
// RDY_server_fence_i_response_get O 1
// RDY_server_fence_request_put O 1 reg
// RDY_server_fence_response_get O 1
// RDY_sfence_vma_server_request_put O 1 reg
// RDY_sfence_vma_server_response_get O 1 reg
// dma_server_awready O 1 const
// dma_server_wready O 1 const
// dma_server_bvalid O 1 const
// dma_server_bid O 16 const
// dma_server_bresp O 2 const
// dma_server_arready O 1 const
// dma_server_rvalid O 1 const
// dma_server_rid O 16 const
// dma_server_rdata O 512 const
// dma_server_rresp O 2 const
// dma_server_rlast O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// imem_req_f3 I 3
// imem_req_addr I 64
// imem_req_priv I 2 reg
// imem_req_sstatus_SUM I 1 reg
// imem_req_mstatus_MXR I 1 reg
// imem_req_satp I 64 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 4 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 4 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// dmem_req_op I 2
// dmem_req_f3 I 3
// dmem_req_amo_funct7 I 7 reg
// dmem_req_addr I 64
// dmem_req_store_value I 64
// dmem_req_priv I 2 reg
// dmem_req_sstatus_SUM I 1 reg
// dmem_req_mstatus_MXR I 1 reg
// dmem_req_satp I 64 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// server_fence_request_put I 8 unused
// dma_server_awvalid I 1 unused
// dma_server_awid I 16 unused
// dma_server_awaddr I 64 unused
// dma_server_awlen I 8 unused
// dma_server_awsize I 3 unused
// dma_server_awburst I 2 unused
// dma_server_awlock I 1 unused
// dma_server_awcache I 4 unused
// dma_server_awprot I 3 unused
// dma_server_awqos I 4 unused
// dma_server_awregion I 4 unused
// dma_server_wvalid I 1 unused
// dma_server_wdata I 512 unused
// dma_server_wstrb I 64 unused
// dma_server_wlast I 1 unused
// dma_server_bready I 1 unused
// dma_server_arvalid I 1 unused
// dma_server_arid I 16 unused
// dma_server_araddr I 64 unused
// dma_server_arlen I 8 unused
// dma_server_arsize I 3 unused
// dma_server_arburst I 2 unused
// dma_server_arlock I 1 unused
// dma_server_arcache I 4 unused
// dma_server_arprot I 3 unused
// dma_server_arqos I 4 unused
// dma_server_arregion I 4 unused
// dma_server_rready I 1 unused
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_imem_req I 1
// EN_dmem_req I 1
// EN_server_fence_i_request_put I 1
// EN_server_fence_i_response_get I 1
// EN_server_fence_request_put I 1
// EN_server_fence_response_get I 1
// EN_sfence_vma_server_request_put I 1
// EN_sfence_vma_server_response_get I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkNear_Mem(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
imem_req_f3,
imem_req_addr,
imem_req_priv,
imem_req_sstatus_SUM,
imem_req_mstatus_MXR,
imem_req_satp,
EN_imem_req,
imem_valid,
imem_is_i32_not_i16,
imem_pc,
imem_instr,
imem_exc,
imem_exc_code,
imem_tval,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
dmem_req_op,
dmem_req_f3,
dmem_req_amo_funct7,
dmem_req_addr,
dmem_req_store_value,
dmem_req_priv,
dmem_req_sstatus_SUM,
dmem_req_mstatus_MXR,
dmem_req_satp,
EN_dmem_req,
dmem_valid,
dmem_word64,
dmem_st_amo_val,
dmem_exc,
dmem_exc_code,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
EN_server_fence_i_request_put,
RDY_server_fence_i_request_put,
EN_server_fence_i_response_get,
RDY_server_fence_i_response_get,
server_fence_request_put,
EN_server_fence_request_put,
RDY_server_fence_request_put,
EN_server_fence_response_get,
RDY_server_fence_response_get,
EN_sfence_vma_server_request_put,
RDY_sfence_vma_server_request_put,
EN_sfence_vma_server_response_get,
RDY_sfence_vma_server_response_get,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method imem_req
input [2 : 0] imem_req_f3;
input [63 : 0] imem_req_addr;
input [1 : 0] imem_req_priv;
input imem_req_sstatus_SUM;
input imem_req_mstatus_MXR;
input [63 : 0] imem_req_satp;
input EN_imem_req;
// value method imem_valid
output imem_valid;
// value method imem_is_i32_not_i16
output imem_is_i32_not_i16;
// value method imem_pc
output [63 : 0] imem_pc;
// value method imem_instr
output [31 : 0] imem_instr;
// value method imem_exc
output imem_exc;
// value method imem_exc_code
output [3 : 0] imem_exc_code;
// value method imem_tval
output [63 : 0] imem_tval;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [3 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [3 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [3 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [3 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// action method dmem_req
input [1 : 0] dmem_req_op;
input [2 : 0] dmem_req_f3;
input [6 : 0] dmem_req_amo_funct7;
input [63 : 0] dmem_req_addr;
input [63 : 0] dmem_req_store_value;
input [1 : 0] dmem_req_priv;
input dmem_req_sstatus_SUM;
input dmem_req_mstatus_MXR;
input [63 : 0] dmem_req_satp;
input EN_dmem_req;
// value method dmem_valid
output dmem_valid;
// value method dmem_word64
output [63 : 0] dmem_word64;
// value method dmem_st_amo_val
output [63 : 0] dmem_st_amo_val;
// value method dmem_exc
output dmem_exc;
// value method dmem_exc_code
output [3 : 0] dmem_exc_code;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method server_fence_i_request_put
input EN_server_fence_i_request_put;
output RDY_server_fence_i_request_put;
// action method server_fence_i_response_get
input EN_server_fence_i_response_get;
output RDY_server_fence_i_response_get;
// action method server_fence_request_put
input [7 : 0] server_fence_request_put;
input EN_server_fence_request_put;
output RDY_server_fence_request_put;
// action method server_fence_response_get
input EN_server_fence_response_get;
output RDY_server_fence_response_get;
// action method sfence_vma_server_request_put
input EN_sfence_vma_server_request_put;
output RDY_sfence_vma_server_request_put;
// action method sfence_vma_server_response_get
input EN_sfence_vma_server_response_get;
output RDY_sfence_vma_server_response_get;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [15 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [15 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [15 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [15 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] dmem_st_amo_val,
dmem_word64,
imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
imem_pc,
imem_tval,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [31 : 0] imem_instr;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] dmem_exc_code,
imem_exc_code,
imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_server_fence_i_request_put,
RDY_server_fence_i_response_get,
RDY_server_fence_request_put,
RDY_server_fence_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_watch_tohost,
RDY_sfence_vma_server_request_put,
RDY_sfence_vma_server_response_get,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
dmem_exc,
dmem_valid,
imem_exc,
imem_is_i32_not_i16,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
imem_valid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule dcache
wire [63 : 0] dcache$cword,
dcache$mem_master_araddr,
dcache$mem_master_awaddr,
dcache$mem_master_rdata,
dcache$mem_master_wdata,
dcache$mv_tohost_value,
dcache$req_addr,
dcache$req_satp,
dcache$req_st_value,
dcache$set_watch_tohost_tohost_addr,
dcache$st_amo_val;
wire [7 : 0] dcache$mem_master_arlen,
dcache$mem_master_awlen,
dcache$mem_master_wstrb,
dcache$mv_status;
wire [6 : 0] dcache$req_amo_funct7;
wire [3 : 0] dcache$exc_code,
dcache$mem_master_arcache,
dcache$mem_master_arid,
dcache$mem_master_arqos,
dcache$mem_master_arregion,
dcache$mem_master_awcache,
dcache$mem_master_awid,
dcache$mem_master_awqos,
dcache$mem_master_awregion,
dcache$mem_master_bid,
dcache$mem_master_rid,
dcache$set_verbosity_verbosity;
wire [2 : 0] dcache$mem_master_arprot,
dcache$mem_master_arsize,
dcache$mem_master_awprot,
dcache$mem_master_awsize,
dcache$req_f3;
wire [1 : 0] dcache$mem_master_arburst,
dcache$mem_master_awburst,
dcache$mem_master_bresp,
dcache$mem_master_rresp,
dcache$req_op,
dcache$req_priv;
wire dcache$EN_ma_ddr4_ready,
dcache$EN_req,
dcache$EN_server_flush_request_put,
dcache$EN_server_flush_response_get,
dcache$EN_server_reset_request_put,
dcache$EN_server_reset_response_get,
dcache$EN_set_verbosity,
dcache$EN_set_watch_tohost,
dcache$EN_tlb_flush,
dcache$RDY_server_flush_request_put,
dcache$RDY_server_flush_response_get,
dcache$RDY_server_reset_request_put,
dcache$RDY_server_reset_response_get,
dcache$exc,
dcache$mem_master_arlock,
dcache$mem_master_arready,
dcache$mem_master_arvalid,
dcache$mem_master_awlock,
dcache$mem_master_awready,
dcache$mem_master_awvalid,
dcache$mem_master_bready,
dcache$mem_master_bvalid,
dcache$mem_master_rlast,
dcache$mem_master_rready,
dcache$mem_master_rvalid,
dcache$mem_master_wlast,
dcache$mem_master_wready,
dcache$mem_master_wvalid,
dcache$req_mstatus_MXR,
dcache$req_sstatus_SUM,
dcache$set_watch_tohost_watch_tohost,
dcache$valid;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule f_sfence_vma_reqs
wire f_sfence_vma_reqs$CLR,
f_sfence_vma_reqs$DEQ,
f_sfence_vma_reqs$EMPTY_N,
f_sfence_vma_reqs$ENQ,
f_sfence_vma_reqs$FULL_N;
// ports of submodule f_sfence_vma_rsps
wire f_sfence_vma_rsps$CLR,
f_sfence_vma_rsps$DEQ,
f_sfence_vma_rsps$EMPTY_N,
f_sfence_vma_rsps$ENQ,
f_sfence_vma_rsps$FULL_N;
// ports of submodule icache
wire [63 : 0] icache$addr,
icache$cword,
icache$mem_master_araddr,
icache$mem_master_awaddr,
icache$mem_master_rdata,
icache$mem_master_wdata,
icache$req_addr,
icache$req_satp,
icache$req_st_value,
icache$set_watch_tohost_tohost_addr;
wire [7 : 0] icache$mem_master_arlen,
icache$mem_master_awlen,
icache$mem_master_wstrb;
wire [6 : 0] icache$req_amo_funct7;
wire [3 : 0] icache$exc_code,
icache$mem_master_arcache,
icache$mem_master_arid,
icache$mem_master_arqos,
icache$mem_master_arregion,
icache$mem_master_awcache,
icache$mem_master_awid,
icache$mem_master_awqos,
icache$mem_master_awregion,
icache$mem_master_bid,
icache$mem_master_rid,
icache$set_verbosity_verbosity;
wire [2 : 0] icache$mem_master_arprot,
icache$mem_master_arsize,
icache$mem_master_awprot,
icache$mem_master_awsize,
icache$req_f3;
wire [1 : 0] icache$mem_master_arburst,
icache$mem_master_awburst,
icache$mem_master_bresp,
icache$mem_master_rresp,
icache$req_op,
icache$req_priv;
wire icache$EN_ma_ddr4_ready,
icache$EN_req,
icache$EN_server_flush_request_put,
icache$EN_server_flush_response_get,
icache$EN_server_reset_request_put,
icache$EN_server_reset_response_get,
icache$EN_set_verbosity,
icache$EN_set_watch_tohost,
icache$EN_tlb_flush,
icache$RDY_server_flush_request_put,
icache$RDY_server_flush_response_get,
icache$RDY_server_reset_request_put,
icache$RDY_server_reset_response_get,
icache$exc,
icache$mem_master_arlock,
icache$mem_master_arready,
icache$mem_master_arvalid,
icache$mem_master_awlock,
icache$mem_master_awready,
icache$mem_master_awvalid,
icache$mem_master_bready,
icache$mem_master_bvalid,
icache$mem_master_rlast,
icache$mem_master_rready,
icache$mem_master_rvalid,
icache$mem_master_wlast,
icache$mem_master_wready,
icache$mem_master_wvalid,
icache$req_mstatus_MXR,
icache$req_sstatus_SUM,
icache$set_watch_tohost_watch_tohost,
icache$valid;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_sfence_vma,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_dmem_req,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_imem_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_server_fence_i_request_put,
CAN_FIRE_server_fence_i_response_get,
CAN_FIRE_server_fence_request_put,
CAN_FIRE_server_fence_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_sfence_vma_server_request_put,
CAN_FIRE_sfence_vma_server_response_get,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_sfence_vma,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_dmem_req,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_imem_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_server_fence_i_request_put,
WILL_FIRE_server_fence_i_response_get,
WILL_FIRE_server_fence_request_put,
WILL_FIRE_server_fence_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_sfence_vma_server_request_put,
WILL_FIRE_sfence_vma_server_response_get;
// inputs to muxes for submodule ports
wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1730;
reg [31 : 0] v__h1884;
reg [31 : 0] v__h1724;
reg [31 : 0] v__h1878;
// synopsys translate_on
// remaining internal signals
wire NOT_cfg_verbosity_read_ULE_1___d9;
// action method server_reset_request_put
assign RDY_server_reset_request_put = rg_state == 2'd2 ;
assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method imem_req
assign CAN_FIRE_imem_req = 1'd1 ;
assign WILL_FIRE_imem_req = EN_imem_req ;
// value method imem_valid
assign imem_valid = icache$valid ;
// value method imem_is_i32_not_i16
assign imem_is_i32_not_i16 = 1'd1 ;
// value method imem_pc
assign imem_pc = icache$addr ;
// value method imem_instr
assign imem_instr = icache$cword[31:0] ;
// value method imem_exc
assign imem_exc = icache$exc ;
// value method imem_exc_code
assign imem_exc_code = icache$exc_code ;
// value method imem_tval
assign imem_tval = icache$addr ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = icache$mem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = icache$mem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = icache$mem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = icache$mem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = icache$mem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = icache$mem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = icache$mem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = icache$mem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = icache$mem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = icache$mem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = icache$mem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = icache$mem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = icache$mem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = icache$mem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = icache$mem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = icache$mem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = icache$mem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = icache$mem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = icache$mem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = icache$mem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = icache$mem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = icache$mem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = icache$mem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = icache$mem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = icache$mem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = icache$mem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = icache$mem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = icache$mem_master_rready ;
// action method dmem_req
assign CAN_FIRE_dmem_req = 1'd1 ;
assign WILL_FIRE_dmem_req = EN_dmem_req ;
// value method dmem_valid
assign dmem_valid = dcache$valid ;
// value method dmem_word64
assign dmem_word64 = dcache$cword ;
// value method dmem_st_amo_val
assign dmem_st_amo_val = dcache$st_amo_val ;
// value method dmem_exc
assign dmem_exc = dcache$exc ;
// value method dmem_exc_code
assign dmem_exc_code = dcache$exc_code ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = dcache$mem_master_awvalid ;
// value method mem_master_m_awid
assign mem_master_awid = dcache$mem_master_awid ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = dcache$mem_master_awaddr ;
// value method mem_master_m_awlen
assign mem_master_awlen = dcache$mem_master_awlen ;
// value method mem_master_m_awsize
assign mem_master_awsize = dcache$mem_master_awsize ;
// value method mem_master_m_awburst
assign mem_master_awburst = dcache$mem_master_awburst ;
// value method mem_master_m_awlock
assign mem_master_awlock = dcache$mem_master_awlock ;
// value method mem_master_m_awcache
assign mem_master_awcache = dcache$mem_master_awcache ;
// value method mem_master_m_awprot
assign mem_master_awprot = dcache$mem_master_awprot ;
// value method mem_master_m_awqos
assign mem_master_awqos = dcache$mem_master_awqos ;
// value method mem_master_m_awregion
assign mem_master_awregion = dcache$mem_master_awregion ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = dcache$mem_master_wvalid ;
// value method mem_master_m_wdata
assign mem_master_wdata = dcache$mem_master_wdata ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = dcache$mem_master_wstrb ;
// value method mem_master_m_wlast
assign mem_master_wlast = dcache$mem_master_wlast ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = dcache$mem_master_bready ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = dcache$mem_master_arvalid ;
// value method mem_master_m_arid
assign mem_master_arid = dcache$mem_master_arid ;
// value method mem_master_m_araddr
assign mem_master_araddr = dcache$mem_master_araddr ;
// value method mem_master_m_arlen
assign mem_master_arlen = dcache$mem_master_arlen ;
// value method mem_master_m_arsize
assign mem_master_arsize = dcache$mem_master_arsize ;
// value method mem_master_m_arburst
assign mem_master_arburst = dcache$mem_master_arburst ;
// value method mem_master_m_arlock
assign mem_master_arlock = dcache$mem_master_arlock ;
// value method mem_master_m_arcache
assign mem_master_arcache = dcache$mem_master_arcache ;
// value method mem_master_m_arprot
assign mem_master_arprot = dcache$mem_master_arprot ;
// value method mem_master_m_arqos
assign mem_master_arqos = dcache$mem_master_arqos ;
// value method mem_master_m_arregion
assign mem_master_arregion = dcache$mem_master_arregion ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = dcache$mem_master_rready ;
// action method server_fence_i_request_put
assign RDY_server_fence_i_request_put =
dcache$RDY_server_flush_request_put &&
icache$RDY_server_flush_request_put ;
assign CAN_FIRE_server_fence_i_request_put =
dcache$RDY_server_flush_request_put &&
icache$RDY_server_flush_request_put ;
assign WILL_FIRE_server_fence_i_request_put =
EN_server_fence_i_request_put ;
// action method server_fence_i_response_get
assign RDY_server_fence_i_response_get =
dcache$RDY_server_flush_response_get &&
icache$RDY_server_flush_response_get ;
assign CAN_FIRE_server_fence_i_response_get =
dcache$RDY_server_flush_response_get &&
icache$RDY_server_flush_response_get ;
assign WILL_FIRE_server_fence_i_response_get =
EN_server_fence_i_response_get ;
// action method server_fence_request_put
assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ;
assign CAN_FIRE_server_fence_request_put =
dcache$RDY_server_flush_request_put ;
assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ;
// action method server_fence_response_get
assign RDY_server_fence_response_get =
dcache$RDY_server_flush_response_get ;
assign CAN_FIRE_server_fence_response_get =
dcache$RDY_server_flush_response_get ;
assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ;
// action method sfence_vma_server_request_put
assign RDY_sfence_vma_server_request_put = f_sfence_vma_reqs$FULL_N ;
assign CAN_FIRE_sfence_vma_server_request_put = f_sfence_vma_reqs$FULL_N ;
assign WILL_FIRE_sfence_vma_server_request_put =
EN_sfence_vma_server_request_put ;
// action method sfence_vma_server_response_get
assign RDY_sfence_vma_server_response_get = f_sfence_vma_rsps$EMPTY_N ;
assign CAN_FIRE_sfence_vma_server_response_get = f_sfence_vma_rsps$EMPTY_N ;
assign WILL_FIRE_sfence_vma_server_response_get =
EN_sfence_vma_server_response_get ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = 1'd0 ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = 1'd0 ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = 1'd0 ;
// value method dma_server_m_bid
assign dma_server_bid = 16'hAAAA ;
// value method dma_server_m_bresp
assign dma_server_bresp = 2'd0 ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = 1'd0 ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = 1'd0 ;
// value method dma_server_m_rid
assign dma_server_rid = 16'd0 ;
// value method dma_server_m_rdata
assign dma_server_rdata = 512'd0 ;
// value method dma_server_m_rresp
assign dma_server_rresp = 2'd0 ;
// value method dma_server_m_rlast
assign dma_server_rlast = 1'd1 ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = dcache$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = dcache$mv_status ;
// submodule dcache
mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(dcache$mem_master_arready),
.mem_master_awready(dcache$mem_master_awready),
.mem_master_bid(dcache$mem_master_bid),
.mem_master_bresp(dcache$mem_master_bresp),
.mem_master_bvalid(dcache$mem_master_bvalid),
.mem_master_rdata(dcache$mem_master_rdata),
.mem_master_rid(dcache$mem_master_rid),
.mem_master_rlast(dcache$mem_master_rlast),
.mem_master_rresp(dcache$mem_master_rresp),
.mem_master_rvalid(dcache$mem_master_rvalid),
.mem_master_wready(dcache$mem_master_wready),
.req_addr(dcache$req_addr),
.req_amo_funct7(dcache$req_amo_funct7),
.req_f3(dcache$req_f3),
.req_mstatus_MXR(dcache$req_mstatus_MXR),
.req_op(dcache$req_op),
.req_priv(dcache$req_priv),
.req_satp(dcache$req_satp),
.req_sstatus_SUM(dcache$req_sstatus_SUM),
.req_st_value(dcache$req_st_value),
.set_verbosity_verbosity(dcache$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(dcache$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(dcache$set_watch_tohost_watch_tohost),
.EN_set_verbosity(dcache$EN_set_verbosity),
.EN_server_reset_request_put(dcache$EN_server_reset_request_put),
.EN_server_reset_response_get(dcache$EN_server_reset_response_get),
.EN_req(dcache$EN_req),
.EN_server_flush_request_put(dcache$EN_server_flush_request_put),
.EN_server_flush_response_get(dcache$EN_server_flush_response_get),
.EN_tlb_flush(dcache$EN_tlb_flush),
.EN_set_watch_tohost(dcache$EN_set_watch_tohost),
.EN_ma_ddr4_ready(dcache$EN_ma_ddr4_ready),
.RDY_set_verbosity(),
.RDY_server_reset_request_put(dcache$RDY_server_reset_request_put),
.RDY_server_reset_response_get(dcache$RDY_server_reset_response_get),
.valid(dcache$valid),
.addr(),
.cword(dcache$cword),
.st_amo_val(dcache$st_amo_val),
.exc(dcache$exc),
.exc_code(dcache$exc_code),
.RDY_server_flush_request_put(dcache$RDY_server_flush_request_put),
.RDY_server_flush_response_get(dcache$RDY_server_flush_response_get),
.RDY_tlb_flush(),
.mem_master_awvalid(dcache$mem_master_awvalid),
.mem_master_awid(dcache$mem_master_awid),
.mem_master_awaddr(dcache$mem_master_awaddr),
.mem_master_awlen(dcache$mem_master_awlen),
.mem_master_awsize(dcache$mem_master_awsize),
.mem_master_awburst(dcache$mem_master_awburst),
.mem_master_awlock(dcache$mem_master_awlock),
.mem_master_awcache(dcache$mem_master_awcache),
.mem_master_awprot(dcache$mem_master_awprot),
.mem_master_awqos(dcache$mem_master_awqos),
.mem_master_awregion(dcache$mem_master_awregion),
.mem_master_wvalid(dcache$mem_master_wvalid),
.mem_master_wdata(dcache$mem_master_wdata),
.mem_master_wstrb(dcache$mem_master_wstrb),
.mem_master_wlast(dcache$mem_master_wlast),
.mem_master_bready(dcache$mem_master_bready),
.mem_master_arvalid(dcache$mem_master_arvalid),
.mem_master_arid(dcache$mem_master_arid),
.mem_master_araddr(dcache$mem_master_araddr),
.mem_master_arlen(dcache$mem_master_arlen),
.mem_master_arsize(dcache$mem_master_arsize),
.mem_master_arburst(dcache$mem_master_arburst),
.mem_master_arlock(dcache$mem_master_arlock),
.mem_master_arcache(dcache$mem_master_arcache),
.mem_master_arprot(dcache$mem_master_arprot),
.mem_master_arqos(dcache$mem_master_arqos),
.mem_master_arregion(dcache$mem_master_arregion),
.mem_master_rready(dcache$mem_master_rready),
.RDY_set_watch_tohost(),
.mv_tohost_value(dcache$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(dcache$mv_status));
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule f_sfence_vma_reqs
FIFO20 #(.guarded(1'd1)) f_sfence_vma_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(f_sfence_vma_reqs$ENQ),
.DEQ(f_sfence_vma_reqs$DEQ),
.CLR(f_sfence_vma_reqs$CLR),
.FULL_N(f_sfence_vma_reqs$FULL_N),
.EMPTY_N(f_sfence_vma_reqs$EMPTY_N));
// submodule f_sfence_vma_rsps
FIFO20 #(.guarded(1'd1)) f_sfence_vma_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_sfence_vma_rsps$ENQ),
.DEQ(f_sfence_vma_rsps$DEQ),
.CLR(f_sfence_vma_rsps$CLR),
.FULL_N(f_sfence_vma_rsps$FULL_N),
.EMPTY_N(f_sfence_vma_rsps$EMPTY_N));
// submodule icache
mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(icache$mem_master_arready),
.mem_master_awready(icache$mem_master_awready),
.mem_master_bid(icache$mem_master_bid),
.mem_master_bresp(icache$mem_master_bresp),
.mem_master_bvalid(icache$mem_master_bvalid),
.mem_master_rdata(icache$mem_master_rdata),
.mem_master_rid(icache$mem_master_rid),
.mem_master_rlast(icache$mem_master_rlast),
.mem_master_rresp(icache$mem_master_rresp),
.mem_master_rvalid(icache$mem_master_rvalid),
.mem_master_wready(icache$mem_master_wready),
.req_addr(icache$req_addr),
.req_amo_funct7(icache$req_amo_funct7),
.req_f3(icache$req_f3),
.req_mstatus_MXR(icache$req_mstatus_MXR),
.req_op(icache$req_op),
.req_priv(icache$req_priv),
.req_satp(icache$req_satp),
.req_sstatus_SUM(icache$req_sstatus_SUM),
.req_st_value(icache$req_st_value),
.set_verbosity_verbosity(icache$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(icache$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(icache$set_watch_tohost_watch_tohost),
.EN_set_verbosity(icache$EN_set_verbosity),
.EN_server_reset_request_put(icache$EN_server_reset_request_put),
.EN_server_reset_response_get(icache$EN_server_reset_response_get),
.EN_req(icache$EN_req),
.EN_server_flush_request_put(icache$EN_server_flush_request_put),
.EN_server_flush_response_get(icache$EN_server_flush_response_get),
.EN_tlb_flush(icache$EN_tlb_flush),
.EN_set_watch_tohost(icache$EN_set_watch_tohost),
.EN_ma_ddr4_ready(icache$EN_ma_ddr4_ready),
.RDY_set_verbosity(),
.RDY_server_reset_request_put(icache$RDY_server_reset_request_put),
.RDY_server_reset_response_get(icache$RDY_server_reset_response_get),
.valid(icache$valid),
.addr(icache$addr),
.cword(icache$cword),
.st_amo_val(),
.exc(icache$exc),
.exc_code(icache$exc_code),
.RDY_server_flush_request_put(icache$RDY_server_flush_request_put),
.RDY_server_flush_response_get(icache$RDY_server_flush_response_get),
.RDY_tlb_flush(),
.mem_master_awvalid(icache$mem_master_awvalid),
.mem_master_awid(icache$mem_master_awid),
.mem_master_awaddr(icache$mem_master_awaddr),
.mem_master_awlen(icache$mem_master_awlen),
.mem_master_awsize(icache$mem_master_awsize),
.mem_master_awburst(icache$mem_master_awburst),
.mem_master_awlock(icache$mem_master_awlock),
.mem_master_awcache(icache$mem_master_awcache),
.mem_master_awprot(icache$mem_master_awprot),
.mem_master_awqos(icache$mem_master_awqos),
.mem_master_awregion(icache$mem_master_awregion),
.mem_master_wvalid(icache$mem_master_wvalid),
.mem_master_wdata(icache$mem_master_wdata),
.mem_master_wstrb(icache$mem_master_wstrb),
.mem_master_wlast(icache$mem_master_wlast),
.mem_master_bready(icache$mem_master_bready),
.mem_master_arvalid(icache$mem_master_arvalid),
.mem_master_arid(icache$mem_master_arid),
.mem_master_araddr(icache$mem_master_araddr),
.mem_master_arlen(icache$mem_master_arlen),
.mem_master_arsize(icache$mem_master_arsize),
.mem_master_arburst(icache$mem_master_arburst),
.mem_master_arlock(icache$mem_master_arlock),
.mem_master_arcache(icache$mem_master_arcache),
.mem_master_arprot(icache$mem_master_arprot),
.mem_master_arqos(icache$mem_master_arqos),
.mem_master_arregion(icache$mem_master_arregion),
.mem_master_rready(icache$mem_master_rready),
.RDY_set_watch_tohost(),
.mv_tohost_value(),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status());
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
dcache$RDY_server_reset_request_put &&
icache$RDY_server_reset_request_put &&
rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_sfence_vma
assign CAN_FIRE_RL_rl_sfence_vma =
f_sfence_vma_reqs$EMPTY_N && f_sfence_vma_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_sfence_vma = CAN_FIRE_RL_rl_sfence_vma ;
// inputs to muxes for submodule ports
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put &&
!EN_server_fence_i_request_put ;
assign MUX_rg_state$write_1__SEL_3 =
dcache$RDY_server_reset_response_get &&
icache$RDY_server_reset_response_get &&
f_reset_rsps$FULL_N &&
rg_state == 2'd1 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete)
begin
case (1'b1) // synopsys parallel_case
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1;
WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset ||
WILL_FIRE_RL_rl_reset_complete ;
// submodule dcache
assign dcache$mem_master_arready = mem_master_arready ;
assign dcache$mem_master_awready = mem_master_awready ;
assign dcache$mem_master_bid = mem_master_bid ;
assign dcache$mem_master_bresp = mem_master_bresp ;
assign dcache$mem_master_bvalid = mem_master_bvalid ;
assign dcache$mem_master_rdata = mem_master_rdata ;
assign dcache$mem_master_rid = mem_master_rid ;
assign dcache$mem_master_rlast = mem_master_rlast ;
assign dcache$mem_master_rresp = mem_master_rresp ;
assign dcache$mem_master_rvalid = mem_master_rvalid ;
assign dcache$mem_master_wready = mem_master_wready ;
assign dcache$req_addr = dmem_req_addr ;
assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ;
assign dcache$req_f3 = dmem_req_f3 ;
assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ;
assign dcache$req_op = dmem_req_op ;
assign dcache$req_priv = dmem_req_priv ;
assign dcache$req_satp = dmem_req_satp ;
assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ;
assign dcache$req_st_value = dmem_req_store_value ;
assign dcache$set_verbosity_verbosity = 4'h0 ;
assign dcache$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign dcache$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign dcache$EN_set_verbosity = 1'b0 ;
assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ;
assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ;
assign dcache$EN_req = EN_dmem_req ;
assign dcache$EN_server_flush_request_put =
EN_server_fence_i_request_put || EN_server_fence_request_put ;
assign dcache$EN_server_flush_response_get =
EN_server_fence_i_response_get || EN_server_fence_response_get ;
assign dcache$EN_tlb_flush = CAN_FIRE_RL_rl_sfence_vma ;
assign dcache$EN_set_watch_tohost = EN_set_watch_tohost ;
assign dcache$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule f_sfence_vma_reqs
assign f_sfence_vma_reqs$ENQ = EN_sfence_vma_server_request_put ;
assign f_sfence_vma_reqs$DEQ = CAN_FIRE_RL_rl_sfence_vma ;
assign f_sfence_vma_reqs$CLR = 1'b0 ;
// submodule f_sfence_vma_rsps
assign f_sfence_vma_rsps$ENQ = CAN_FIRE_RL_rl_sfence_vma ;
assign f_sfence_vma_rsps$DEQ = EN_sfence_vma_server_response_get ;
assign f_sfence_vma_rsps$CLR = 1'b0 ;
// submodule icache
assign icache$mem_master_arready = imem_master_arready ;
assign icache$mem_master_awready = imem_master_awready ;
assign icache$mem_master_bid = imem_master_bid ;
assign icache$mem_master_bresp = imem_master_bresp ;
assign icache$mem_master_bvalid = imem_master_bvalid ;
assign icache$mem_master_rdata = imem_master_rdata ;
assign icache$mem_master_rid = imem_master_rid ;
assign icache$mem_master_rlast = imem_master_rlast ;
assign icache$mem_master_rresp = imem_master_rresp ;
assign icache$mem_master_rvalid = imem_master_rvalid ;
assign icache$mem_master_wready = imem_master_wready ;
assign icache$req_addr = imem_req_addr ;
assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ;
assign icache$req_f3 = imem_req_f3 ;
assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ;
assign icache$req_op = 2'd0 ;
assign icache$req_priv = imem_req_priv ;
assign icache$req_satp = imem_req_satp ;
assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ;
assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign icache$set_verbosity_verbosity = 4'h0 ;
assign icache$set_watch_tohost_tohost_addr = 64'h0 ;
assign icache$set_watch_tohost_watch_tohost = 1'b0 ;
assign icache$EN_set_verbosity = 1'b0 ;
assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ;
assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ;
assign icache$EN_req = EN_imem_req ;
assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ;
assign icache$EN_server_flush_response_get =
EN_server_fence_i_response_get ;
assign icache$EN_tlb_flush = CAN_FIRE_RL_rl_sfence_vma ;
assign icache$EN_set_watch_tohost = 1'b0 ;
assign icache$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9)
begin
v__h1730 = $stime;
#0;
end
v__h1724 = v__h1730 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9)
$display("%0d: Near_Mem.rl_reset", v__h1724);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9)
begin
v__h1884 = $stime;
#0;
end
v__h1878 = v__h1884 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9)
$display("%0d: Near_Mem.rl_reset_complete", v__h1878);
end
// synopsys translate_on
endmodule // mkNear_Mem
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hdll__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hdll__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_hdll__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hdll__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hdll__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_PP_V |
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy
* Description: High Speed Data Demo
* Demonstrate a source and sink interface for the DMA
*
* Changes:
*/
module hs_demo #(
parameter BUFFER_WIDTH = 10,
parameter FIFO_WIDTH = 10
)(
input clk,
input rst,
output o_idle,
//DEMO CODE START
input i_bram_wea,
input [BUFFER_WIDTH - 1:0] i_bram_addr,
input [31:0] i_bram_din,
output [31:0] o_bram_dout,
//DEMO CODE END
//Write Side
input i_write_enable,
input [63:0] i_write_addr,
input i_write_addr_inc,
input i_write_addr_dec,
output o_write_finished,
input [23:0] i_write_count,
input i_write_flush,
output [1:0] o_write_ready,
input [1:0] i_write_activate,
output [23:0] o_write_size,
input i_write_strobe,
input [31:0] i_write_data,
//Read Side
input i_read_enable,
input [63:0] i_read_addr,
input i_read_addr_inc,
input i_read_addr_dec,
output o_read_busy,
output o_read_error,
input [23:0] i_read_count,
input i_read_flush,
output o_read_ready,
input i_read_activate,
output [23:0] o_read_size,
output [31:0] o_read_data,
input i_read_strobe
);
//local parameters
localparam IDLE = 0;
localparam INGRESS_DMA_EN = 1;
localparam INGRESS_DMA_ACT = 2;
localparam INGRESS_DMA_FLUSH = 3;
localparam EGRESS_DMA_EN = 4;
localparam EGRESS_DMA_ACT = 5;
localparam EGRESS_DMA_FLUSH = 6;
//registes/wires
reg [23:0] r_count;
reg [3:0] state;
reg r_ingress_rd_stb;
wire w_ingress_rd_rdy;
reg r_ingress_rd_act;
wire [23:0] w_ingress_rd_size;
wire [31:0] w_ingress_rd_data;
wire [1:0] w_egress_wr_rdy;
reg [1:0] r_egress_wr_act;
wire [23:0] w_egress_wr_size;
reg r_egress_wr_stb;
//reg [31:0] w_egress_wr_data;
wire [31:0] w_egress_wr_data;
wire usr_clk;
reg [23:0] r_transfer_size;
//Demo Application Signals
reg r_wea_a;
reg [BUFFER_WIDTH - 1:0] r_addr_a;
//reg [31:0] w_din_a;
wire [31:0] w_din_a;
wire [31:0] w_dout_a;
//submodules
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (FIFO_WIDTH )
)ingress(
//universal input
.reset (rst ),
//write side
.write_clock (clk ),
.write_ready (o_write_ready ),
.write_activate (i_write_activate ),
.write_fifo_size(o_write_size ),
.write_strobe (i_write_strobe ),
.write_data (i_write_data ),
.starved ( ),
//read side
.read_clock (usr_clk ), //This does not have to be the same clock for write side
.read_strobe (r_ingress_rd_stb ),
.read_ready (w_ingress_rd_rdy ),
.read_activate (r_ingress_rd_act ),
.read_count (w_ingress_rd_size ),
.read_data (w_ingress_rd_data ),
.inactive ( )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (FIFO_WIDTH )
) egress (
//universal input
.reset (rst ),
//write side
.write_clock (usr_clk ), //This does not have to be the same clock for read side
.write_ready (w_egress_wr_rdy ),
.write_activate (r_egress_wr_act ),
.write_fifo_size(w_egress_wr_size ),
.write_strobe (r_egress_wr_stb ),
.write_data (w_egress_wr_data ),
.starved ( ),
//read side
.read_clock (clk ),
.read_strobe (i_read_strobe ),
.read_ready (o_read_ready ),
.read_activate (i_read_activate ),
.read_count (o_read_size ),
.read_data (o_read_data ),
.inactive ( )
);
/*
DEMO Application (Local Dual Port Buffer)
right now the dual port buffer is connected to both sides of the ping pong
FIFOs The output of the PPFIFOs can be used to attach to any interface such
as:
CSI Camera Reader
If this core were to control a CSI camera the output data would go into
the EGRESS PPFIFO
DSI Video Writer
If this core were to control a DSI display, the input would come from
the INGRESS PPFIFO
*/
//Read/Write Data to a local buffer
dpb #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (BUFFER_WIDTH )
) local_buffer (
.clka (usr_clk ),
.wea (r_wea_a ),
.addra (r_addr_a ),
.dina (w_din_a ),
.douta (w_dout_a ),
.clkb (clk ),
.web (i_bram_wea ),
.addrb (i_bram_addr ),
.dinb (i_bram_din ),
.doutb (o_bram_dout )
);
//asynchronous logic
assign usr_clk = clk; //The usr_clk does not need to be the same as the system clock
assign o_read_error = 1'b0;
assign w_din_a = w_ingress_rd_data;
assign w_egress_wr_data = w_dout_a;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
if (rst) begin
//State Machine
state <= IDLE;
//PPFIFO
r_ingress_rd_act <= 0;
r_egress_wr_act <= 0;
//w_egress_wr_data <= 0;
r_transfer_size <= 0;
//Demo Application Buffer
/* DEMO CODE START */
r_wea_a <= 0;
r_addr_a <= 0;
//w_din_a <= 0;
/* DEMO CODE END */
end
else begin
r_ingress_rd_stb <= 0;
r_egress_wr_stb <= 0;
case (state)
IDLE: begin
r_ingress_rd_act <= 0;
r_egress_wr_act <= 0;
//w_egress_wr_data <= 0;
r_count <= 0;
/* DEMO CODE START */
r_wea_a <= 0;
r_addr_a <= 0;
//w_din_a <= 0;
/* DEMO CODE END */
//if (i_write_enable || w_ingress_rd_rdy) begin
if (w_ingress_rd_rdy) begin
state <= INGRESS_DMA_EN;
r_addr_a <= i_write_addr;
r_transfer_size <= i_write_count;
end
else if (i_read_enable) begin
state <= EGRESS_DMA_EN;
r_addr_a <= i_read_addr;
r_transfer_size <= i_read_count;
end
end
//Incomming Data
INGRESS_DMA_EN: begin
if (w_ingress_rd_rdy && !r_ingress_rd_act) begin
//Activate a FIFO
r_ingress_rd_act <= 1;
r_count <= 0;
/* DEMO CODE START */
//r_wea_a <= 1;
//w_din_a <= 0;
/* DEMO CODE END */
state <= INGRESS_DMA_ACT;
end
if (i_write_flush) begin
state <= INGRESS_DMA_FLUSH;
end
//if (!i_write_enable && !w_ingress_rd_rdy) begin
if (!w_ingress_rd_rdy) begin
//This is the only place where we can return to IDLE state
state <= IDLE;
end
end
INGRESS_DMA_ACT: begin
//Read everything from the FIFO and put it into the dual port RAM
if (r_ingress_rd_stb) begin
if (i_write_addr_inc) begin
r_addr_a <= r_addr_a + 1;
end
else if (i_write_addr_dec) begin
r_addr_a <= r_addr_a - 1;
end
end
if (r_count < w_ingress_rd_size) begin
//w_din_a <= w_ingress_rd_data;
r_ingress_rd_stb <= 1;
r_wea_a <= 1;
r_count <= r_count + 1;
end
else begin
r_wea_a <= 0;
r_ingress_rd_act <= 0;
state <= INGRESS_DMA_EN;
end
end
INGRESS_DMA_FLUSH: begin
//Flush the ingress FIFO
if (w_ingress_rd_rdy && !r_ingress_rd_act) begin
//If there is a buffer available activate it
r_ingress_rd_act <= 1;
r_count <= 0;
end
else if(r_ingress_rd_act) begin
//Eat it all
if (r_count < w_ingress_rd_size) begin
r_ingress_rd_stb<= 1;
r_count <= r_count + 1;
end
else begin
//No more left
r_ingress_rd_act <= 0;
end
end
else begin
//Go back to wait for more instruction from the controller
state <= INGRESS_DMA_EN;
end
end
//Outgoing Data
EGRESS_DMA_EN: begin
//User wants to read data from the local buffer
if (i_read_enable) begin
if ((w_egress_wr_rdy > 0) && (r_egress_wr_act == 0)) begin
r_count <= 0;
if (w_egress_wr_rdy[0]) begin
r_egress_wr_act[0] <= 1;
end
else begin
r_egress_wr_act[1] <= 1;
end
state <= EGRESS_DMA_ACT;
end
end
else begin
state <= IDLE;
end
end
EGRESS_DMA_ACT: begin
if (r_egress_wr_act > 0) begin
if (r_count < w_egress_wr_size) begin
r_count <= r_count + 1;
r_egress_wr_stb <= 1;
//w_egress_wr_data <= w_dout_a;
if (i_read_addr_inc) begin
r_addr_a <= r_addr_a + 1;
end
else if (i_read_addr_dec) begin
r_addr_a <= r_addr_a - 1;
end
end
else begin
r_egress_wr_act <= 0;
end
end
else begin
state <= EGRESS_DMA_EN;
end
if (i_read_flush) begin
state <= EGRESS_DMA_FLUSH;
end
end
EGRESS_DMA_FLUSH: begin
if (r_egress_wr_act > 0) begin
if (r_count < w_egress_wr_size) begin
//w_egress_wr_data <= 32'h00000000;
r_count <= r_count + 1;
end
else begin
r_egress_wr_act <= 0;
end
end
else begin
state <= EGRESS_DMA_EN;
end
end
default: begin
end
endcase
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_de4.v
// Version: 1.00a
// Verilog Standard: Verilog-2001
// Description: Wrapper file for all riffa logic for Altera DE4 boards
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "altera.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_de4
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "ADE4")
(// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: Altera CLK/RESET
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
localparam C_VENDOR = "ALTERA";
localparam C_ALTERA_TX_READY_LATENCY = 2;
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = PLD_CLK;
assign rst_in = RESET_STATUS;
translation_altera
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
// Inputs
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
.APP_MSI_ACK (APP_MSI_ACK));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
module alu (
op,
a,
b,
y,
cin,
cout,
zout
);
input [3:0] op; // ALU Operation
input [7:0] a; // 8-bit Input a
input [7:0] b; // 8-bit Input b
output [7:0] y; // 8-bit Output
input cin;
output cout;
output zout;
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Reg declarations for outputs
reg cout;
reg zout;
reg [7:0] y;
// Internal declarations
reg addercout; // Carry out straight from the adder itself.
parameter [3:0] ALUOP_ADD = 4'b0000;
parameter [3:0] ALUOP_SUB = 4'b1000;
parameter [3:0] ALUOP_AND = 4'b0001;
parameter [3:0] ALUOP_OR = 4'b0010;
parameter [3:0] ALUOP_XOR = 4'b0011;
parameter [3:0] ALUOP_COM = 4'b0100;
parameter [3:0] ALUOP_ROR = 4'b0101;
parameter [3:0] ALUOP_ROL = 4'b0110;
parameter [3:0] ALUOP_SWAP = 4'b0111;
always @(a or b or cin or op) begin
case (op) // synopsys parallel_case
ALUOP_ADD: {addercout, y} = a + b;
ALUOP_SUB: {addercout, y} = a - b; // Carry out is really "borrow"
ALUOP_AND: {addercout, y} = {1'b0, a & b};
ALUOP_OR: {addercout, y} = {1'b0, a | b};
ALUOP_XOR: {addercout, y} = {1'b0, a ^ b};
ALUOP_COM: {addercout, y} = {1'b0, ~a};
ALUOP_ROR: {addercout, y} = {a[0], cin, a[7:1]};
ALUOP_ROL: {addercout, y} = {a[7], a[6:0], cin};
ALUOP_SWAP: {addercout, y} = {1'b0, a[3:0], a[7:4]};
default: {addercout, y} = {1'b0, 8'h00};
endcase
end
always @(y)
zout = (y == 8'h00);
always @(addercout or op)
if (op == ALUOP_SUB) cout = ~addercout; // Invert adder's carry to get borrow
else cout = addercout;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__FAHCIN_FUNCTIONAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_FUNCTIONAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Receive HDMI, hdmi embedded syncs data in, video dma data out.
module axi_hdmi_rx_es (
// hdmi interface
hdmi_clk,
hdmi_data,
hdmi_vs_de,
hdmi_hs_de,
hdmi_data_de);
// parameters
parameter DATA_WIDTH = 32;
localparam BYTE_WIDTH = DATA_WIDTH/8;
// hdmi interface
input hdmi_clk;
input [(DATA_WIDTH-1):0] hdmi_data;
// dma interface
output hdmi_vs_de;
output hdmi_hs_de;
output [(DATA_WIDTH-1):0] hdmi_data_de;
// internal registers
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
reg hdmi_hs_de_rcv_d = 'd0;
reg hdmi_vs_de_rcv_d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
reg hdmi_hs_de_rcv_2d = 'd0;
reg hdmi_vs_de_rcv_2d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
reg hdmi_hs_de_rcv_3d = 'd0;
reg hdmi_vs_de_rcv_3d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_rcv_4d = 'd0;
reg hdmi_vs_de_rcv_4d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_de = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 1:0] hdmi_preamble_cnt = 'd0;
reg hdmi_hs_de_rcv = 'd0;
reg hdmi_vs_de_rcv = 'd0;
// internal signals
wire [(DATA_WIDTH-1):0] hdmi_ff_s;
wire [(DATA_WIDTH-1):0] hdmi_00_s;
wire [(DATA_WIDTH-1):0] hdmi_b6_s;
wire [(DATA_WIDTH-1):0] hdmi_9d_s;
wire [(DATA_WIDTH-1):0] hdmi_ab_s;
wire [(DATA_WIDTH-1):0] hdmi_80_s;
// es constants
assign hdmi_ff_s = {BYTE_WIDTH{8'hff}};
assign hdmi_00_s = {BYTE_WIDTH{8'h00}};
assign hdmi_b6_s = {BYTE_WIDTH{8'hb6}};
assign hdmi_9d_s = {BYTE_WIDTH{8'h9d}};
assign hdmi_ab_s = {BYTE_WIDTH{8'hab}};
assign hdmi_80_s = {BYTE_WIDTH{8'h80}};
// delay to get rid of eav's 4 bytes
always @(posedge hdmi_clk) begin
hdmi_data_d <= hdmi_data;
hdmi_hs_de_rcv_d <= hdmi_hs_de_rcv;
hdmi_vs_de_rcv_d <= hdmi_vs_de_rcv;
hdmi_data_2d <= hdmi_data_d;
hdmi_hs_de_rcv_2d <= hdmi_hs_de_rcv_d;
hdmi_vs_de_rcv_2d <= hdmi_vs_de_rcv_d;
hdmi_data_3d <= hdmi_data_2d;
hdmi_hs_de_rcv_3d <= hdmi_hs_de_rcv_2d;
hdmi_vs_de_rcv_3d <= hdmi_vs_de_rcv_2d;
hdmi_data_4d <= hdmi_data_3d;
hdmi_hs_de_rcv_4d <= hdmi_hs_de_rcv_3d;
hdmi_vs_de_rcv_4d <= hdmi_vs_de_rcv_3d;
hdmi_data_de <= hdmi_data_4d;
hdmi_hs_de <= hdmi_hs_de_rcv & hdmi_hs_de_rcv_4d;
hdmi_vs_de <= hdmi_vs_de_rcv & hdmi_vs_de_rcv_4d;
end
// check for sav and eav and generate the corresponding enables
always @(posedge hdmi_clk) begin
if ((hdmi_data == hdmi_ff_s) || (hdmi_data == hdmi_00_s)) begin
hdmi_preamble_cnt <= hdmi_preamble_cnt + 1'b1;
end else begin
hdmi_preamble_cnt <= 'd0;
end
if (hdmi_preamble_cnt == 3'b11) begin
if ((hdmi_data == hdmi_b6_s) || (hdmi_data == hdmi_9d_s)) begin
hdmi_hs_de_rcv <= 1'b0;
end else if ((hdmi_data == hdmi_ab_s) || (hdmi_data == hdmi_80_s)) begin
hdmi_hs_de_rcv <= 1'b1;
end
if (hdmi_data == hdmi_b6_s) begin
hdmi_vs_de_rcv <= 1'b0;
end else if (hdmi_data == hdmi_9d_s) begin
hdmi_vs_de_rcv <= 1'b1;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:03:09 03/24/2015
// Design Name: clk_divider
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/clk_divider_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clk_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clk_divider_test;
// Inputs
reg rst;
reg clk;
// Outputs
wire div_clk_2, div_clk_3, div_clk_4;
// Instantiate the Unit Under Test (UUT)
clk_divider #(.DIV(2)) uut2 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_2)
);
clk_divider #(.DIV(3)) uut3 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_3)
);
clk_divider #(.DIV(500)) uut4 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_4)
);
reg [31:0] ctr_d, ctr_q;
always @(*) begin
ctr_d = ctr_q;
if(div_clk_4) begin
ctr_d = ctr_q + 1;
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 0;
end else begin
ctr_q <= ctr_d;
end
end
initial begin
// Initialize Inputs
clk = 0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
@(negedge rst); // wait for reset
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
$finish;
end
endmodule
|
// Test bench for the restricted 27x27 bit multiplier. (The
// restriction is that if the most significant bit of opa is set to
// one the three least significant bits of opa must be zero.) This
// enables us to design a 27x27 bit multiplier using only two DSP48E1
// multipliers and one LUT based adder outside the DSP blocks in the
// Xilinx 7-series of FPGAs.
`timescale 1ns / 1ps
module tb_mult_27x27;
parameter LATENCY = 4;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [53:0] res; // From dut of mult_27x27.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To dut of mult_27x27.v
reg [26:0] opa; // To dut of mult_27x27.v
reg [26:0] opb; // To dut of mult_27x27.v
// End of automatics
mult_27x27 #(.LATENCY(LATENCY))
dut(/*AUTOINST*/
// Outputs
.res (res[53:0]),
// Inputs
.clk (clk),
.opa (opa[26:0]),
.opb (opb[26:0]));
reg running = 1;
initial while(running) begin
clk = 0;
#10;
clk = 1;
#10;
end
reg [53:0] expected_res;
reg res_is_valid = 0;
always @(posedge clk) begin
expected_res <= repeat(LATENCY-1) @(posedge clk) $unsigned(opa)*$unsigned(opb);
end
integer state = 10; // FIXME: Remove the unused state variable
initial begin
opa = 0;
opb = 0;
expected_res = 0;
repeat(100) @(posedge clk);
repeat(10000) @(posedge clk) begin : FOO
reg [26:0] restricted_opa;
//
if(1 || !state) begin
restricted_opa = {$random,$random} ;
if(restricted_opa[26]) begin
restricted_opa[2:0] = 3'b000;
end
opa <= restricted_opa;
opb <= {$random,$random};
opb <= $random;
state = 10;
end else begin
state = state - 1;
end
if(expected_res !== res) begin
$display("expected_res !== res!");
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$stop;
// Note: We don't check the last few values, but it
// doesn't really matter as they are randomly generated
// anyway.
end
end
running = 0;
#10;
$display("");
$display("*** Multiplier test PASSED ***");
$display("");
end
initial begin
while(1) begin
$display(" opa opb res expected_res res^expected");
repeat(20) begin
@(posedge clk);
$display("%x %x %x %x %x ",opa,opb,res, expected_res, res^expected_res);
end
end
end
endmodule
|
module EX_MEM(input clk,
input reset,
input [1:0] WB_in,
input [1:0] M_in,
input [31:0] ALU_in,
input [4:0] instruction_mux_in,
input [31:0] RDdata2_in,
input hold_i,
output reg MemWrite,
output reg MemRead,
output reg[1:0] WB_out,
output reg[31:0] ALU_out,
output reg[4:0] instruction_mux_out,
output reg[31:0] RDdata2_out);
always@(posedge reset)begin
MemWrite = 0;
MemRead = 0;
WB_out = 0;
ALU_out = 0;
RDdata2_out = 0;
instruction_mux_out = 0;
end
always@(posedge clk)begin
if(hold_i)begin
WB_out <= WB_out;
MemWrite <= MemWrite;
MemRead <= MemRead;
ALU_out <= ALU_out;
RDdata2_out <= RDdata2_out;
instruction_mux_out <= instruction_mux_out;
end
else begin
WB_out <= WB_in;
MemWrite <= M_in[1];
MemRead <= M_in[0];
ALU_out <= ALU_in;
RDdata2_out <= RDdata2_in;
instruction_mux_out <= instruction_mux_in;
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 3;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.eqz1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.eqz1_tb.vcd");
$dumpvars(0, cpu_tb);
#18
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_1_V
`define SKY130_FD_SC_LS__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_1_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC
*/
module eth_mac_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
// bus width assertions
initial begin
if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
$error("Error: Interface width must be 32 or 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
generate
if (DATA_WIDTH == 64) begin
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
end else begin
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
assign rx_start_packet[1] = 1'b0;
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet[0])
);
assign tx_start_packet[1] = 1'b0;
end
endgenerate
endmodule
|
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module vgafb_graycounter
#(parameter COUNTER_WIDTH = 2)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06.03.2016 12:07:59
// Design Name:
// Module Name: FSM_C_CORDIC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_C_CORDIC(
//INPUTS
input wire CLK, //system clock
input wire RST_EX, //system reset
input wire ACK_ADD_SUBTX, //RECIBE SI LA SUMA EN FLOTANTE X SE EJECUTO
input wire ACK_ADD_SUBTY, //RECIBE SI LA SUMA EN FLOTANTE Y SE EJECUTO
input wire ACK_ADD_SUBTZ, //RECIBE SI LA SUMA EN FLOTANTE Z SE EJECUTO
input wire Begin_FSM_EX, //inicia la maquina de estados
input wire [4:0] CONT_ITER,//LLEVA LA CUENTA DE LA ITERACIONES
//OUTPUT SIGNALS
output reg RST, //REALIZA EL RESET DE LOS REGISTROS
output reg MS_1, //SELECCION DEL MUX 1
output reg EN_REG3, //ENABLE PARA EL REGISTRO 3 CON EL VALOR DEL EXP = COSH + SIN H
//output reg EN_REGMult, //ENABLE REG MULT
output reg ADD_SUBT, //SELECCION DE OPERACION PARA EL ADD/SUBT FLOTANTE
output reg Begin_SUMX, //INICIA ADD/SUM FLOTANTE X
output reg Begin_SUMY, //INICIA ADD/SUM FLOTANTE Y
output reg Begin_SUMZ, //INICIA ADD/SUM FLOTANTE Z
output reg EN_REG1X, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg EN_REG1Y, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg EN_REG1Z, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg MS_2, //SELECCION DEL MUX 2
output reg EN_REG2, //ENABLE PARA EL REGISTRO CON LOS VALORES DESPLAZADOS DE LA SEGUNDA ETAPA
output reg CLK_CDIR, //CLK PARA EL CONTADOR DE ITERACIONES
output reg EN_REG2XYZ, //ENABLE PARA EL VALOR ANTERIOR DE XYZ DE SEGUNDA ETAPA
output reg ACK_EX, //ACK PARA SABER SI LA OPERACION EX YA SE REALIZO
//registros de selectores
output reg EN_ADDSUBT,
output reg EN_MS1,
output reg EN_MS2
);
parameter [5:0]
//se definen los estados que se utilizaran en la maquina
a = 6'd0,
b = 6'd1,
c = 6'd2,
d = 6'd3,
e = 6'd4,
f = 6'd5,
g = 6'd6,
h = 6'd7,
i = 6'd8,
j = 6'd9,
k = 6'd10,
l = 6'd11,
m = 6'd12,
n = 6'd13,
o = 6'd14,
p = 6'd15,
q = 6'd16,
r = 6'd17,
s = 6'd18,
t = 6'd19;
reg [5:0] state_reg, state_next ; //state registers declaration
////
always @(posedge CLK, posedge RST_EX)
if (RST_EX) begin
state_reg <= a;
end
else begin
state_reg <= state_next;
end
//assign State = state_reg;
///
always @*
begin
state_next = state_reg;
EN_REG2 = 0;
EN_REG3 = 0;
//EN_REGMult = 0;
EN_REG1X = 0;
EN_REG1Y = 0;
EN_REG1Z = 0;
EN_REG2XYZ = 0;
Begin_SUMX = 0;
Begin_SUMY = 0;
Begin_SUMZ = 0;
ACK_EX = 0;
CLK_CDIR = 0;
RST = 0;
MS_1 = 0;
MS_2 = 0;
ADD_SUBT = 0;
EN_ADDSUBT = 0;
EN_MS1 = 0;
EN_MS2 = 0;
//nuevos estados
case(state_reg)
a:
begin
if(Begin_FSM_EX)
begin
RST = 1;
state_next = b;
end
else
state_next = a;
end
b:
begin
ADD_SUBT = 0;
EN_ADDSUBT = 1;
MS_1 = 1;
EN_MS1 = 1;
MS_2 = 1;
EN_MS2 = 1;
state_next = c;
end
c:
begin
EN_REG1X = 1;
EN_REG1Y = 1;
EN_REG1Z = 1;
MS_1 = 0;
EN_MS1= 1;
state_next = d;
end
d:
begin
state_next = e;
end
e:
begin
EN_REG2 = 1;
EN_REG2XYZ = 1;
state_next = f;
end
f:
begin
Begin_SUMX = 1;
Begin_SUMY = 1;
CLK_CDIR = 1;
state_next = g;
end
g:
begin
state_next = h;
end
h:
begin
Begin_SUMZ = 1;
if(ACK_ADD_SUBTX & ACK_ADD_SUBTY)
begin
EN_REG1X = 1;
EN_REG1Y = 1;
state_next = i;
end
else
state_next = h;
end
i:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG1Z = 1;
state_next = j;
end
else
state_next = i;
end
j:
begin
if(CONT_ITER == 5'b10001)//if(CONT_ITER == 5'b01111 ) //15 iteraciones
begin
MS_2 = 0;
EN_MS2 = 1;
ADD_SUBT = 0;
EN_ADDSUBT = 1;
state_next = k;
end
else
state_next = d;
end
k:
begin
Begin_SUMZ = 1;
state_next = l;
end
l:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG3 = 1;
state_next = m;
end
else
state_next = l;
end
m:
begin
ACK_EX = 1;
if(RST_EX)
begin
RST = 1;
state_next = a;
end
end
endcase
end
endmodule
//case(state_reg)
// a:
// begin
// if(Begin_FSM_EX)
// begin
// RST = 1;
// state_next = b;
// end
// else
// state_next = a;
// end
// b:
// begin
// ADD_SUBT = 0;
// EN_ADDSUBT = 1;
// MS_1 = 1;
// EN_MS1 = 1;
// MS_2 = 1;
// EN_MS2 = 1;
// state_next = c;
// end
// c:
// begin
// EN_REG1X = 1;
// EN_REG1Y = 1;
// EN_REG1Z = 1;
// MS_1 = 0;
// EN_MS1= 1;
// state_next = d;
// end
// /*d:
// begin
// MS_1 = 0;
// EN_MS1= 1;
// state_next = e;
// end*/
// d:
// begin
// CLK_CDIR = 1;
// state_next = e;
// end
// e:
// begin
// EN_REG2 = 1;
// state_next = f;
// end
// f:
// begin
// EN_REG2XYZ = 1;
// state_next = g;
// end
// g:
// begin
// Begin_SUMZ = 1;
// state_next = h;
// end
// h:
// begin
// Begin_SUMX = 1;
// Begin_SUMY = 1;
// if(ACK_ADD_SUBTZ)
// begin
// EN_REG1Z = 1;
// state_next = i;
// end
// else
// state_next = h;
// end
// i:
// begin
// //Begin_SUMZ = 1;
// if(ACK_ADD_SUBTX & ACK_ADD_SUBTY)
// begin
// EN_REG1X = 1;
// EN_REG1Y = 1;
// //Begin_SUMZ = 1;
// state_next = j;
// end
// else
// state_next = i;
// end
// /*k:
// begin
// state_next = l;
// end*/
// j:
// begin
// if(CONT_ITER == 5'b10001)//if(CONT_ITER == 5'b01111 ) //15 iteraciones
// begin
// MS_2 = 0;
// EN_MS2 = 1;
// ADD_SUBT = 0;
// EN_ADDSUBT = 1;
// state_next = k;
// end
// else
// state_next = d;
// end
// k:
// begin
// Begin_SUMZ = 1;
// state_next = l;
// end
// l:
// begin
// if(ACK_ADD_SUBTZ)
// begin
// EN_REG3 = 1;
// state_next = m;
// end
// else
// state_next = l;
// end
// m:
// begin
// ACK_EX = 1;
// if(RST_EX)
// begin
// RST = 1;
// state_next = a;
// end
// end
// endcase
// end
//endmodule |
//-----------------------------------------------------------------------------
// system_nfa_accept_samples_generic_hw_top_5_wrapper.v
//-----------------------------------------------------------------------------
module system_nfa_accept_samples_generic_hw_top_5_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD5000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD50000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_5 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:25 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_1_stub.v
// Design : zqynq_lab_1_design_xbar_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion,
m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast,
m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [7:0]m_axi_bresp;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/29 20:02:13
// Design Name:
// Module Name: _4bit_binary_counter_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _4bit_binary_counter_tb(
);
parameter COUNT = 85;
parameter DELAY = 10;
reg CP, M, LD_n, CLR_n;
reg [3:0] D;
wire [3:0] Q;
wire Qcc_n;
integer i;
_4bit_binary_counter DUT (.CP(CP), .M(M), .D(D), .LD_n(LD_n), .CLR_n(CLR_n), .Q(Q), .Qcc_n(Qcc_n));
initial begin
#(COUNT * DELAY) $finish;
end
initial begin
CP = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY CP = ~CP;
end
end
initial begin
M = 1;
#(COUNT*DELAY/2) M = 0;
end
initial begin
D = 4'b1111; LD_n = 1; CLR_n = 0;
#DELAY CLR_n = 1;
#(5*DELAY) CLR_n = 0;
#(3*DELAY) CLR_n = 1;
#(5*DELAY) LD_n = 0;
#(2*DELAY) D = 4'b0111;
#(4*DELAY) LD_n = 1;
end
endmodule
|
// megafunction wizard: %ALTERA_MULT_ADD v16.0%
// GENERATION: XML
// mult_add_fix8bx2.v
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module mult_add_fix8bx2 (
output wire [16:0] result, // result.result
input wire [7:0] dataa_0, // dataa_0.dataa_0
input wire [7:0] dataa_1, // dataa_1.dataa_1
input wire [7:0] datab_0, // datab_0.datab_0
input wire [7:0] datab_1, // datab_1.datab_1
input wire clock0 // clock0.clock0
);
mult_add_fix8bx2_0002 mult_add_fix8bx2_inst (
.result (result), // result.result
.dataa_0 (dataa_0), // dataa_0.dataa_0
.dataa_1 (dataa_1), // dataa_1.dataa_1
.datab_0 (datab_0), // datab_0.datab_0
.datab_1 (datab_1), // datab_1.datab_1
.clock0 (clock0) // clock0.clock0
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_mult_add" version="16.0" >
// Retrieval info: <generic name="number_of_multipliers" value="2" />
// Retrieval info: <generic name="width_a" value="8" />
// Retrieval info: <generic name="width_b" value="8" />
// Retrieval info: <generic name="width_result" value="17" />
// Retrieval info: <generic name="gui_4th_asynchronous_clear" value="false" />
// Retrieval info: <generic name="gui_associated_clock_enable" value="false" />
// Retrieval info: <generic name="gui_output_register" value="true" />
// Retrieval info: <generic name="gui_output_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_output_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_output_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier1_direction" value="ADD" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register1" value="false" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register1_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_addnsub_multiplier_aclr1" value="NONE" />
// Retrieval info: <generic name="gui_addnsub_multiplier_sclr1" value="NONE" />
// Retrieval info: <generic name="gui_multiplier3_direction" value="ADD" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register3" value="false" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register3_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_addnsub_multiplier_aclr3" value="NONE" />
// Retrieval info: <generic name="gui_addnsub_multiplier_sclr3" value="NONE" />
// Retrieval info: <generic name="gui_use_subnadd" value="false" />
// Retrieval info: <generic name="gui_representation_a" value="SIGNED" />
// Retrieval info: <generic name="gui_register_signa" value="false" />
// Retrieval info: <generic name="gui_register_signa_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_register_signa_aclr" value="NONE" />
// Retrieval info: <generic name="gui_register_signa_sclr" value="NONE" />
// Retrieval info: <generic name="gui_representation_b" value="SIGNED" />
// Retrieval info: <generic name="gui_register_signb" value="false" />
// Retrieval info: <generic name="gui_register_signb_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_register_signb_aclr" value="NONE" />
// Retrieval info: <generic name="gui_register_signb_sclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_a" value="true" />
// Retrieval info: <generic name="gui_input_register_a_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_register_a_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_a_sclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_b" value="true" />
// Retrieval info: <generic name="gui_input_register_b_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_register_b_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_b_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_a_input" value="Multiplier input" />
// Retrieval info: <generic name="gui_scanouta_register" value="false" />
// Retrieval info: <generic name="gui_scanouta_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_scanouta_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_scanouta_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_b_input" value="Multiplier input" />
// Retrieval info: <generic name="gui_multiplier_register" value="false" />
// Retrieval info: <generic name="gui_multiplier_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_multiplier_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_register_sclr" value="NONE" />
// Retrieval info: <generic name="preadder_mode" value="SIMPLE" />
// Retrieval info: <generic name="gui_preadder_direction" value="ADD" />
// Retrieval info: <generic name="width_c" value="16" />
// Retrieval info: <generic name="gui_datac_input_register" value="false" />
// Retrieval info: <generic name="gui_datac_input_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_datac_input_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_datac_input_register_sclr" value="NONE" />
// Retrieval info: <generic name="width_coef" value="18" />
// Retrieval info: <generic name="gui_coef_register" value="false" />
// Retrieval info: <generic name="gui_coef_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_coef_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_coef_register_sclr" value="NONE" />
// Retrieval info: <generic name="coef0_0" value="0" />
// Retrieval info: <generic name="coef0_1" value="0" />
// Retrieval info: <generic name="coef0_2" value="0" />
// Retrieval info: <generic name="coef0_3" value="0" />
// Retrieval info: <generic name="coef0_4" value="0" />
// Retrieval info: <generic name="coef0_5" value="0" />
// Retrieval info: <generic name="coef0_6" value="0" />
// Retrieval info: <generic name="coef0_7" value="0" />
// Retrieval info: <generic name="coef1_0" value="0" />
// Retrieval info: <generic name="coef1_1" value="0" />
// Retrieval info: <generic name="coef1_2" value="0" />
// Retrieval info: <generic name="coef1_3" value="0" />
// Retrieval info: <generic name="coef1_4" value="0" />
// Retrieval info: <generic name="coef1_5" value="0" />
// Retrieval info: <generic name="coef1_6" value="0" />
// Retrieval info: <generic name="coef1_7" value="0" />
// Retrieval info: <generic name="coef2_0" value="0" />
// Retrieval info: <generic name="coef2_1" value="0" />
// Retrieval info: <generic name="coef2_2" value="0" />
// Retrieval info: <generic name="coef2_3" value="0" />
// Retrieval info: <generic name="coef2_4" value="0" />
// Retrieval info: <generic name="coef2_5" value="0" />
// Retrieval info: <generic name="coef2_6" value="0" />
// Retrieval info: <generic name="coef2_7" value="0" />
// Retrieval info: <generic name="coef3_0" value="0" />
// Retrieval info: <generic name="coef3_1" value="0" />
// Retrieval info: <generic name="coef3_2" value="0" />
// Retrieval info: <generic name="coef3_3" value="0" />
// Retrieval info: <generic name="coef3_4" value="0" />
// Retrieval info: <generic name="coef3_5" value="0" />
// Retrieval info: <generic name="coef3_6" value="0" />
// Retrieval info: <generic name="coef3_7" value="0" />
// Retrieval info: <generic name="accumulator" value="NO" />
// Retrieval info: <generic name="accum_direction" value="ADD" />
// Retrieval info: <generic name="gui_ena_preload_const" value="false" />
// Retrieval info: <generic name="gui_accumulate_port_select" value="0" />
// Retrieval info: <generic name="loadconst_value" value="64" />
// Retrieval info: <generic name="gui_accum_sload_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_accum_sload_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_accum_sload_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_double_accum" value="false" />
// Retrieval info: <generic name="chainout_adder" value="NO" />
// Retrieval info: <generic name="chainout_adder_direction" value="ADD" />
// Retrieval info: <generic name="port_negate" value="PORT_UNUSED" />
// Retrieval info: <generic name="negate_register" value="UNREGISTERED" />
// Retrieval info: <generic name="negate_aclr" value="NONE" />
// Retrieval info: <generic name="negate_sclr" value="NONE" />
// Retrieval info: <generic name="gui_systolic_delay" value="false" />
// Retrieval info: <generic name="gui_systolic_delay_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_systolic_delay_aclr" value="NONE" />
// Retrieval info: <generic name="gui_systolic_delay_sclr" value="NONE" />
// Retrieval info: <generic name="gui_pipelining" value="0" />
// Retrieval info: <generic name="latency" value="0" />
// Retrieval info: <generic name="gui_input_latency_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_latency_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_latency_sclr" value="NONE" />
// Retrieval info: <generic name="selected_device_family" value="Stratix V" />
// Retrieval info: <generic name="reg_autovec_sim" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : mult_add_fix8bx2.vo
// RELATED_FILES: mult_add_fix8bx2.v, mult_add_fix8bx2_0002.v
|
`timescale 1ns / 100ps
module ee201_debouncer(CLK, RESET, PB, DPB, SCEN, MCEN, CCEN);
//inputs
input CLK, RESET;
input PB;
//outputs
output DPB;
output SCEN, MCEN, CCEN;
//parameters
parameter N_dc = 7;
(* fsm_encoding = "user" *)
reg [5:0] state;
// other items not controlledd by the special atribute
reg [N_dc-1:0] debounce_count;
reg [3:0] MCEN_count;
//concurrent signal assignment statements
// The following is possible because of the output coding used by us.
assign {DPB, SCEN, MCEN, CCEN} = state[5:2];
//constants used for state naming // the don't cares are replaced here with zeros
localparam
INI = 6'b000000,
W84 = 6'b000001,
SCEN_st = 6'b111100,
WS = 6'b100000,
MCEN_st = 6'b101100,
CCEN_st = 6'b100100,
MCEN_cont = 6'b101101,
CCR = 6'b100001,
WFCR = 6'b100010;
//logic
always @ (posedge CLK, posedge RESET)
begin : State_Machine
if (RESET)
begin
state <= INI;
debounce_count <= 'bx;
MCEN_count <= 4'bx;
end
else
begin
case (state)
INI: begin
debounce_count <= 0;
MCEN_count <= 0;
if (PB)
begin
state <= W84;
end
end
W84: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= INI;
end
else if (debounce_count[N_dc-5])// for N_dc of 28, it is debounce_count[23], i.e T = 0.084 sec for f = 100MHz
begin
state <= SCEN_st;
end
end
SCEN_st: begin
debounce_count <= 0;
MCEN_count <= MCEN_count + 1;
state <= WS;
end
WS: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= CCR;
end
else if (debounce_count[N_dc-1])// for N_dc of 28, it is debounce_count[27], i.e T = 1.342 sec for f = 100MHz
begin
state <= MCEN_st;
end
end
MCEN_st: begin
debounce_count <= 0;
MCEN_count <= MCEN_count + 1;
state <= CCEN_st;
end
CCEN_st: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= CCR;
end
else if (debounce_count[N_dc-1])// for N_dc of 28, it is debounce_count[27], i.e T = 1.342 sec for f = 100MHz
begin
if (MCEN_count == 4'b1000)
begin
state <= MCEN_cont;
end
else
begin
state <= MCEN_st;
end
end
end
MCEN_cont: begin
if (!PB)
begin
state <= CCR;
end
end
CCR: begin
debounce_count <= 0;
MCEN_count <= 0;
state <= WFCR;
end
WFCR: begin
debounce_count <= debounce_count + 1;
if (PB)
begin
state <= WS;
end
else if (debounce_count[N_dc-5])// for N_dc of 28, it is debounce_count[23], i.e T = 0.084 sec for f = 100MHz
begin
state <= INI;
end
end
endcase
end
end // State_Machine
endmodule // ee201_debouncer |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_CPU_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1P_LP_V
`define SKY130_FD_SC_LP__ISO1P_LP_V
/**
* iso1p: ????.
*
* Verilog wrapper for iso1p with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso1p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1p_lp (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1p_lp (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1P_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_TB_V
`define SKY130_FD_SC_HD__DFRBP_TB_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfrbp.v"
module top();
// Inputs are registered
reg D;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfrbp dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_tagdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Description:
// Final 4-1 mux for evicted address.
// lkup tag and wr data tag logic.
// diagnostic read pipe
// CTL logic for generating the
// Changes:
// - lkup_tag_c1[`TAG_WIDTH-1:6] replaces wrdata_tag_c1;
// - removed all bist related signals, since the bist mux has been moved inside
// the tag.
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
`include "iop.h"
`include "sctag.h"
module sctag_tagdp( /*AUTOARG*/
// Outputs
tagdp_evict_tag_c4, tagdp_diag_data_c7, tagdp_lkup_addr_c4,
lkup_row_addr_dcd_c3, lkup_row_addr_icd_c3, tagdp_lkup_addr11_c4,
mbdata_inst_tecc_c8, so, lkup_tag_c1, arbdp_tag_idx_px2_buf,
mbist_l2t_index_buf, arbctl_tag_way_px2_buf,
mbist_l2t_dec_way_buf, arbctl_tag_rd_px2_buf, mbist_l2t_read_buf,
arbctl_tag_wr_px2_buf, mbist_l2t_write_buf, tag_wrdata_px2_buf,
mbist_write_data_buf,
// Inputs
dir_cam_addr_c3, arbaddr_idx_c3, arbdp_tagdata_px2, tag_triad0_c3,
tag_triad1_c3, tag_triad2_c3, tag_triad3_c3, tag_quad_muxsel_c3,
arbdp_tag_idx_px2, mbist_l2t_index, arbctl_tag_way_px2,
mbist_l2t_dec_way, arbctl_tag_rd_px2, mbist_l2t_read,
arbctl_tag_wr_px2, mbist_l2t_write, tag_wrdata_px2,
mbist_write_data, arbctl_evict_c3, rclk, si, se, sehold
);
input [39:8] dir_cam_addr_c3; // from arbaddr
input [9:0] arbaddr_idx_c3; // from arbaddr
input [`TAG_WIDTH-1:6] arbdp_tagdata_px2 ; // write data for tag.
input [`TAG_WIDTH-1:0] tag_triad0_c3;
input [`TAG_WIDTH-1:0] tag_triad1_c3;
input [`TAG_WIDTH-1:0] tag_triad2_c3;
input [`TAG_WIDTH-1:0] tag_triad3_c3;
input [3:0] tag_quad_muxsel_c3 ; // to tagdp
output [`TAG_WIDTH-1:0] tagdp_evict_tag_c4; // to wbdata.
output [`TAG_WIDTH-1:0] tagdp_diag_data_c7; // to oqdp
output [39:10] tagdp_lkup_addr_c4; // to the directory
output [2:0] lkup_row_addr_dcd_c3, lkup_row_addr_icd_c3;
output tagdp_lkup_addr11_c4; // to dirrep. // NEW_PIN POST_4.2
output [5:0] mbdata_inst_tecc_c8; // to miss buffer data.
output so;
// lkup_tag_c1[`TAG_WIDTH-1:6] replaces wrdata_tag_c1;
output [`TAG_WIDTH-1:1] lkup_tag_c1; // to tag.
input [9:0] arbdp_tag_idx_px2;
input [9:0] mbist_l2t_index;
input [11:0] arbctl_tag_way_px2;
input [11:0] mbist_l2t_dec_way;
input arbctl_tag_rd_px2;
input mbist_l2t_read;
input arbctl_tag_wr_px2;
input mbist_l2t_write;
input [27:0] tag_wrdata_px2;
input [7:0] mbist_write_data;
output [9:0] arbdp_tag_idx_px2_buf;
output [9:0] mbist_l2t_index_buf;
output [11:0] arbctl_tag_way_px2_buf;
output [11:0] mbist_l2t_dec_way_buf;
output arbctl_tag_rd_px2_buf;
output mbist_l2t_read_buf;
output arbctl_tag_wr_px2_buf;
output mbist_l2t_write_buf;
output [27:0] tag_wrdata_px2_buf;
output [7:0] mbist_write_data_buf;
input arbctl_evict_c3;
input rclk;
input si,se;
input sehold; // POST_4.1
wire [29:6] tmp_lkup_tag_c1 ;
wire [5:0] parity_c1;
wire [5:0] tag_acc_ecc_c1, tag_acc_ecc_c2, tag_acc_ecc_c3;
wire [5:0] tag_acc_ecc_c4, tag_acc_ecc_c5, tag_acc_ecc_c6;
wire [5:0] tag_acc_ecc_c7;
wire [`TAG_WIDTH-1:0] tagdp_evict_tag_c3, tagdp_diag_data_c6; // to oqdp
wire [39:8] evict_addr_c3;
wire [39:8] lkup_addr_c3;
wire [39:10] tagdp_lkup_addr_c3;
wire [`TAG_WIDTH-1:6] wrdata_tag_c1;
// New functionality POST_4.1
// sehold will make ff_wrdata_tag_c1 non-transparent.
wire clk_1;
clken_buf clk_buf (.clk(clk_1), .rclk(rclk), .enb_l(sehold), .tmb_l(~se));
// reduced the width of this flop.
dff_s #(`TAG_WIDTH-6) ff_wrdata_tag_c1
(.din(arbdp_tagdata_px2[`TAG_WIDTH-1:6]), .clk(clk_1),
.q(wrdata_tag_c1[`TAG_WIDTH-1:6]), .se(se), .si(), .so());
zzecc_sctag_24b_gen tagecc0 (.din({2'b0,wrdata_tag_c1[`TAG_WIDTH-1:6]}),
.dout(tmp_lkup_tag_c1[29:6]),
.parity(parity_c1[5:0]));
assign tag_acc_ecc_c1 = { parity_c1[4:0], parity_c1[5] } ;
/////////////////////////////////////////////////////////
// To prevent the tag_acc_ecc_c1 bits from being
// part of the critical path in the tag compare operation,
// the overall parity bit P is not compared
//
// The check bits in tag_acc_ecc_c1 take 4 levels of XOR
// to compute whereas the overall parity P takes 5 levels.
//
// Not comparing P means that a hit could be signalled
// inspite of an error in the P bit. This requires the
// parity computation in C2 to account for this case
// and not cause any Miss Buffer insertions.
/////////////////////////////////////////////////////////
assign lkup_tag_c1[`TAG_WIDTH-1:6] = wrdata_tag_c1[`TAG_WIDTH-1:6] ;
assign lkup_tag_c1[5:1] = tag_acc_ecc_c1[5:1] ;
/////////////////////////////////////////////
// Directory lkup address
/////////////////////////////////////////////
assign evict_addr_c3[39:8] = { tagdp_evict_tag_c3[`TAG_WIDTH-1:6],
arbaddr_idx_c3[9:0] } ;
mux2ds #(32) mux_cam_addr_c3 ( .dout (lkup_addr_c3[39:8]),
.in0(dir_cam_addr_c3[39:8]), .in1(evict_addr_c3[39:8]),
.sel0(~arbctl_evict_c3), .sel1(arbctl_evict_c3));
assign tagdp_lkup_addr_c3[39:10] = lkup_addr_c3[39:10] ;
dff_s #(30) ff_tagdp_lkup_addr_c4 (.din(tagdp_lkup_addr_c3[39:10]), .clk(rclk),
.q(tagdp_lkup_addr_c4[39:10]), .se(se), .si(), .so());
/////////////////////////////////////////////
// LRU mux.
/////////////////////////////////////////////
mux4ds #(`TAG_WIDTH) mux_lru_tag (.dout (tagdp_evict_tag_c3[`TAG_WIDTH-1:0]),
.in0(tag_triad0_c3[`TAG_WIDTH-1:0]),
.in1(tag_triad1_c3[`TAG_WIDTH-1:0]),
.in2(tag_triad2_c3[`TAG_WIDTH-1:0]),
.in3(tag_triad3_c3[`TAG_WIDTH-1:0]),
.sel0(tag_quad_muxsel_c3[0]),
.sel1(tag_quad_muxsel_c3[1]),
.sel2(tag_quad_muxsel_c3[2]),
.sel3(tag_quad_muxsel_c3[3]));
//////////////////////////////////////////////////////////////////////////////////////////////
// Tag Diagnostic data pipeline
//------------------------------------------------------------------------------------------
// C1 C2 C3 C4 C5 C6 C7 C8 C9
//------------------------------------------------------------------------------------------
// diag px2 rd tag prepare mux flop flop mux data ret.
// decode idx mux way mux out tag with
// sels and flop other
// diag data
//------------------------------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////////////////
dff_s #(`TAG_WIDTH) ff_tagdp_evict_tag_c4 (.din(tagdp_evict_tag_c3[`TAG_WIDTH-1:0]), .clk(rclk),
.q(tagdp_evict_tag_c4[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
dff_s #(`TAG_WIDTH) ff_tagdp_diag_data_c6 (.din(tagdp_evict_tag_c4[`TAG_WIDTH-1:0]), .clk(rclk),
.q(tagdp_diag_data_c6[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
dff_s #(`TAG_WIDTH) ff_tagdp_diag_data_c7 (.din(tagdp_diag_data_c6[`TAG_WIDTH-1:0]), .clk(rclk),
.q(tagdp_diag_data_c7[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
/////////////////////////////////////////////
// DP is 32 bits wide. The following
// logic and flops are pushed to one side.
/////////////////////////////////////////////
dff_s #(6) ff_ecc_c2 (.din(tag_acc_ecc_c1[5:0]), .clk(rclk),
.q(tag_acc_ecc_c2[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c3 (.din(tag_acc_ecc_c2[5:0]), .clk(rclk),
.q(tag_acc_ecc_c3[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c4 (.din(tag_acc_ecc_c3[5:0]), .clk(rclk),
.q(tag_acc_ecc_c4[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c5 (.din(tag_acc_ecc_c4[5:0]), .clk(rclk),
.q(tag_acc_ecc_c5[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c6 (.din(tag_acc_ecc_c5[5:0]), .clk(rclk),
.q(tag_acc_ecc_c6[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c7 (.din(tag_acc_ecc_c6[5:0]), .clk(rclk),
.q(tag_acc_ecc_c7[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c8 (.din(tag_acc_ecc_c7[5:0]), .clk(rclk),
.q(mbdata_inst_tecc_c8[5:0]), .se(se), .si(), .so());
assign lkup_row_addr_dcd_c3[2:0] = lkup_addr_c3[10:8];
assign lkup_row_addr_icd_c3[2:0] = lkup_addr_c3[10:8];
dff_s #(1) ff_addr11_c4 (.din(lkup_addr_c3[11]), .clk(rclk),
.q(tagdp_lkup_addr11_c4), .se(se), .si(), .so());
////////////////////////////////////////////////////////////
// The following signals need to be bufferred before
// the tag.
// INput pins are arranged on the top.
// Try to align with the data path cell placement information
// provided below.
////////////////////////////////////////////////////////////
// repeater row1 ( 24 bits wide ) arranged as follows from left to right.
// index [0 ..... 9]
// way [11 .... 0 ]
// rd
// wr
assign arbdp_tag_idx_px2_buf[9:0] = arbdp_tag_idx_px2[9:0] ;
assign arbctl_tag_way_px2_buf[11:0] = arbctl_tag_way_px2[11:0] ;
assign arbctl_tag_rd_px2_buf = arbctl_tag_rd_px2;
assign arbctl_tag_wr_px2_buf = arbctl_tag_wr_px2;
// repeater row2 ( 24 bits wide ) arranged as follows from left to right.
// index [0 ..... 9]
// way [11 .... 0 ]
// rd
// wr
assign mbist_l2t_index_buf[9:0] = mbist_l2t_index[9:0] ;
assign mbist_l2t_dec_way_buf[11:0] = mbist_l2t_dec_way[11:0] ;
assign mbist_l2t_read_buf = mbist_l2t_read;
assign mbist_l2t_write_buf = mbist_l2t_write;
// repeater row 3 ( 28 bits wide ) arranged as follows from left to right.
// wr_data [0 .. 27]
assign tag_wrdata_px2_buf = tag_wrdata_px2 ;
// repeater row 4 ( 8 bits wide ) arranged as follows from left to right.
assign mbist_write_data_buf = mbist_write_data;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_FUNCTIONAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_FUNCTIONAL_PP_V |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_64.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
//synthesis_resources = lut 144
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_64_decode
//synthesis_resources = lut 144 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
parameter CFG_ECC_DECODER_REG = 0;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome_wire;
reg [7:0] syndrome;
reg [71:0] data_reg;
generate
if (CFG_ECC_DECODER_REG == 1)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
syndrome <= {8{1'b0}};
data_reg <= {72{1'b0}};
end else
begin
syndrome <= syndrome_wire;
data_reg <= data_wire;
end
end
end else
begin
always @ (*)
begin
syndrome = syndrome_wire;
data_reg = data_wire;
end
end
endgenerate
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_reg[0]) : data_reg[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_reg[1]) : data_reg[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_reg[10]) : data_reg[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_reg[11]) : data_reg[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_reg[12]) : data_reg[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_reg[13]) : data_reg[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_reg[14]) : data_reg[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_reg[15]) : data_reg[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_reg[16]) : data_reg[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_reg[17]) : data_reg[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_reg[18]) : data_reg[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_reg[19]) : data_reg[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_reg[2]) : data_reg[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_reg[20]) : data_reg[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_reg[21]) : data_reg[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_reg[22]) : data_reg[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_reg[23]) : data_reg[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_reg[24]) : data_reg[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_reg[25]) : data_reg[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_reg[26]) : data_reg[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_reg[27]) : data_reg[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_reg[28]) : data_reg[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_reg[29]) : data_reg[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_reg[3]) : data_reg[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_reg[30]) : data_reg[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_reg[31]) : data_reg[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_reg[32]) : data_reg[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_reg[33]) : data_reg[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_reg[34]) : data_reg[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_reg[35]) : data_reg[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_reg[36]) : data_reg[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_reg[37]) : data_reg[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_reg[38]) : data_reg[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_reg[39]) : data_reg[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_reg[4]) : data_reg[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_reg[40]) : data_reg[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_reg[41]) : data_reg[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_reg[42]) : data_reg[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_reg[43]) : data_reg[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_reg[44]) : data_reg[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_reg[45]) : data_reg[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_reg[46]) : data_reg[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_reg[47]) : data_reg[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_reg[48]) : data_reg[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_reg[49]) : data_reg[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_reg[5]) : data_reg[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_reg[50]) : data_reg[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_reg[51]) : data_reg[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_reg[52]) : data_reg[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_reg[53]) : data_reg[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_reg[54]) : data_reg[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_reg[55]) : data_reg[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_reg[56]) : data_reg[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_reg[57]) : data_reg[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_reg[58]) : data_reg[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_reg[59]) : data_reg[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_reg[6]) : data_reg[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_reg[60]) : data_reg[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_reg[61]) : data_reg[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_reg[62]) : data_reg[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_reg[63]) : data_reg[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_reg[7]) : data_reg[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_reg[8]) : data_reg[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_reg[9]) : data_reg[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome_wire = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64
#(
parameter
CFG_ECC_DECODER_REG = 1
)
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.clk (clk),
.reset_n (reset_n),
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_ecc_dec.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_ecc_dec
// Description: Decodes the result from the ecc checking block
// into a 64 bit value that is used to correct single bit errors.
// Correction is performed by e ^ data.
*/
module sparc_exu_ecc_dec (/*AUTOARG*/
// Outputs
e,
// Inputs
q
) ;
input [6:0] q;
output [63:0] e;
assign e[0] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[1] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[2] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[3] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[4] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[5] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[6] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[7] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[8] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[9] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[10] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & q[1] & q[0];
assign e[11] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[12] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[13] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[14] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[15] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[16] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[17] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[18] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[19] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[20] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[21] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[22] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[23] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[24] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[25] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & q[1] & q[0];
assign e[26] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[27] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[28] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[29] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[30] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[31] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[32] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[33] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[34] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[35] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[36] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[37] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[38] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[39] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[40] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & q[1] & q[0];
assign e[41] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[42] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[43] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[44] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[45] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[46] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[47] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[48] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[49] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[50] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[51] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[52] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[53] = ~q[6] & q[5] & q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[54] = ~q[6] & q[5] & q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[55] = ~q[6] & q[5] & q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[56] = ~q[6] & q[5] & q[4] & q[3] & q[2] & q[1] & q[0];
assign e[57] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[58] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[59] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[60] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[61] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[62] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[63] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
endmodule // sparc_exu_ecc_dec
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_BEHAVIORAL_V |
// ik_swift_master_0.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.05.05.12:48:22
`timescale 1 ps / 1 ps
module ik_swift_master_0 #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset) // resetrequest.reset
);
ik_swift_master_0_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // in.valid
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // .data
.out_valid (timing_adt_out_valid), // out.valid
.out_data (timing_adt_out_data), // .data
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
ik_swift_master_0_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (b2p_out_packets_stream_ready), // in.ready
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_data (b2p_out_packets_stream_data), // .data
.in_channel (b2p_out_packets_stream_channel), // .channel
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.out_ready (b2p_adapter_out_ready), // out.ready
.out_valid (b2p_adapter_out_valid), // .valid
.out_data (b2p_adapter_out_data), // .data
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
ik_swift_master_0_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (transacto_out_stream_ready), // in.ready
.in_valid (transacto_out_stream_valid), // .valid
.in_data (transacto_out_stream_data), // .data
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_ready (p2b_adapter_out_ready), // out.ready
.out_valid (p2b_adapter_out_valid), // .valid
.out_data (p2b_adapter_out_data), // .data
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
`define SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = 347.2222 and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart3_rx #(parameter real CLK_FREQ = 357e6, parameter real BAUD = 9600, parameter WIDTH = 8, parameter PARITY = 0, parameter STOP_BITS = 1) (
//input reset,
input clk,
input uld_rx_data,
output reg [WIDTH-1:0] rx_data = {WIDTH{1'b0}},
//input rx_enable,
input rx_in,
output reg byte_rdy = 1'b0
);
//Variable/custom Baud rate little-endian 8N1 UART-RX
`include "bits_to_fit.v"
//`ifdef ML505 localparam real CLK_FREQ = 100e6;
//`else localparam real CLK_FREQ = 40e6;
//`endif
localparam CLK16X_CNT_SIZE = bits_to_fit(CLK_FREQ/(16*BAUD));
localparam BIT_CNT_SIZE = bits_to_fit(WIDTH+PARITY+STOP_BITS+1);
localparam [CLK16X_CNT_SIZE-1:0] CLK16X_WIDTH = CLK_FREQ/(16*BAUD);
//localparam [BAUD_CNT_SIZE-1:0] FRAME_MIDPOINT = FRAME_WIDTH/2;
// Internal registers
reg [WIDTH-1:0] rx_reg = {WIDTH{1'b0}};
reg [CLK16X_CNT_SIZE-1:0] rx_sample_cnt = {CLK16X_CNT_SIZE{1'b0}};
reg [BIT_CNT_SIZE-1:0] rx_cnt = {BIT_CNT_SIZE{1'b0}};
reg [3:0] Baud_ctr = 4'd0;
(* ASYNC_REG = "true" *) reg rx_da = 1'b1, rx_db = 1'b1;
reg rx_busy = 1'b0;
// UART RX Logic - with 16X Baud Clock
always @ (posedge clk) begin
// Synchronize the asynch signal
rx_da <= rx_in;
rx_db <= rx_da;
// drive the ouptut register when requested
rx_data <= (uld_rx_data) ? rx_reg : rx_data;
/*if (reset) begin
rx_sample_cnt <= {BAUD_CNT_SIZE{1'b0}};
rx_cnt <= {BIT_CNT_SIZE{1'b0}};
byte_rdy <= 1'b0;
rx_busy <= 1'b0;
end else begin // if (~reset)*/
if (rx_busy) begin //drive logic, counters etc
if (rx_sample_cnt == CLK16X_WIDTH) begin
rx_sample_cnt <= {CLK16X_CNT_SIZE{1'b0}};
Baud_ctr <= Baud_ctr + 1'b1;
rx_cnt <= (Baud_ctr == 4'd15) ? rx_cnt + 1'b1 : rx_cnt;
if (Baud_ctr == 4'd7)
case(rx_cnt)
{BIT_CNT_SIZE{1'b0}}: begin
rx_busy <= ~rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
WIDTH+PARITY+STOP_BITS: begin
rx_busy <= 1'b0;
byte_rdy <= rx_db;
end
default: begin
rx_reg[rx_cnt - 1'b1] <= rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
endcase
else /*if (Baud_ctr!=7) */ byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end else begin // if (rx_sample_cnt != CLK16X_WIDTH)
rx_sample_cnt <= rx_sample_cnt + 1'b1;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
end else begin //if (~rx_busy)
rx_busy <= ~rx_db; //detect space on line as start of START bit
rx_sample_cnt <= {CLK16X_CNT_SIZE{1'b0}};
Baud_ctr <= 4'd0;
rx_cnt <= 1'b0;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end // if (~rx_busy)
//end //if (~reset)
end //always
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011-2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module embedded_sync_decoder(
input clk,
input [15:0] data_in,
output reg hs_de,
output reg vs_de,
output reg [15:0] data_out
);
reg [15:0] data_d = 'd0;
reg hs_de_rcv_d = 'd0;
reg vs_de_rcv_d = 'd0;
reg [15:0] data_2d = 'd0;
reg hs_de_rcv_2d = 'd0;
reg vs_de_rcv_2d = 'd0;
reg [15:0] data_3d = 'd0;
reg hs_de_rcv_3d = 'd0;
reg vs_de_rcv_3d = 'd0;
reg [15:0] data_4d = 'd0;
reg hs_de_rcv_4d = 'd0;
reg vs_de_rcv_4d = 'd0;
reg hs_de_rcv = 'd0;
reg vs_de_rcv = 'd0;
// delay to get rid of eav's 4 bytes
always @(posedge clk) begin
data_d <= data_in;
data_2d <= data_d;
data_3d <= data_2d;
data_4d <= data_3d;
data_out <= data_4d;
hs_de_rcv_d <= hs_de_rcv;
vs_de_rcv_d <= vs_de_rcv;
hs_de_rcv_2d <= hs_de_rcv_d;
vs_de_rcv_2d <= vs_de_rcv_d;
hs_de_rcv_3d <= hs_de_rcv_2d;
vs_de_rcv_3d <= vs_de_rcv_2d;
hs_de_rcv_4d <= hs_de_rcv_3d;
vs_de_rcv_4d <= vs_de_rcv_3d;
hs_de <= hs_de_rcv & hs_de_rcv_4d;
vs_de <= vs_de_rcv & vs_de_rcv_4d;
end
reg [1:0] preamble_cnt = 'd0;
// check for sav and eav and generate the corresponding enables
always @(posedge clk) begin
if ((data_in == 16'hffff) || (data_in == 16'h0000)) begin
preamble_cnt <= preamble_cnt + 1'b1;
end else begin
preamble_cnt <= 'd0;
end
if (preamble_cnt == 3'h3) begin
if ((data_in == 16'hb6b6) || (data_in == 16'h9d9d)) begin
hs_de_rcv <= 1'b0;
vs_de_rcv <= ~data_in[13];
end else if ((data_in == 16'habab) || (data_in == 16'h8080)) begin
hs_de_rcv <= 1'b1;
vs_de_rcv <= ~data_in[13];
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Transparent Data Latch with Asynchronous Clear and Gate Enable
// /___/ /\ Filename : LDCE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 11/01/11 - Disable timing check when set reset active (CR633224)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LDCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_G_INVERTED = 1'b0
)(
output Q,
input CLR,
input D,
input G,
input GE
);
wire [0:0] IS_CLR_INVERTED_BIN;
wire [0:0] IS_G_INVERTED_BIN;
reg Q_out = INIT;
wire CLR_in;
wire D_in;
wire GE_in;
wire G_in;
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED;
assign IS_G_INVERTED_BIN = IS_G_INVERTED;
`ifdef XIL_TIMING
wire CLR_dly;
wire D_dly;
wire GE_dly;
wire G_dly;
assign CLR_in = (CLR !== 1'bz) && (CLR_dly ^ IS_CLR_INVERTED_BIN); // rv 0
assign D_in = D_dly;
assign G_in = G_dly ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE_dly; // rv 1
`else
assign CLR_in = (CLR !== 1'bz) && (CLR ^ IS_CLR_INVERTED_BIN); // rv 0
assign D_in = D;
assign G_in = G ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE; // rv 1
`endif
assign Q = Q_out;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire o_out;
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nrst;
wire in_clk_enable, in_clk_enable_n, in_clk_enable_p;
wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p;
wire rst_clk_enable, rst_clk_enable1;
wire tl_enable, tl_enable_n, tl_enable_p;
wire clk_en_n, clk_en_p;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
not (nrst, CLR_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nrst, GE_in);
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, GE_in);
and (tl_enable, ngsr, nrst);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN;
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN;
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN;
assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN;
assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN;
assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or CLR_in) begin
if (GSR) begin
if (INIT) begin
rst_int = 1'b0;
set_int = 1'b1;
end
else begin
rst_int = 1'b1;
set_int = 1'b0;
end
end
else begin
rst_int = CLR_in;
set_int = 1'b0;
end
end
latchsre_ldce (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1);
always @(o_out)
Q_out = o_out;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(CLR => Q) = (0:0:0, 0:0:0);
(negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
$period (negedge G, 0:0:0, notifier);
$period (posedge G, 0:0:0, notifier);
$recrem (negedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly);
$recrem (negedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly);
$recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly);
$recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly);
$recrem (posedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly);
$recrem (posedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly);
$setuphold (negedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly);
$setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (negedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly);
$setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (posedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly);
$setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$setuphold (posedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly);
$setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$width (negedge CLR, 0:0:0, 0, notifier);
$width (negedge G, 0:0:0, 0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge G, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive latchsre_ldce (q, clk, d, set, rst, ge, notifier);
output q; reg q;
input clk, d, set, rst, ge, notifier;
table
// clk d set rst ge notifier q q+;
1 0 0 0 1 ? : ? : 0;
1 1 0 0 1 ? : ? : 1;
0 ? 0 0 ? ? : ? : -;
? ? 0 0 0 ? : ? : -;
? 0 0 ? ? ? : 0 : -;
? 1 ? 0 ? ? : 1 : -;
? ? 1 0 ? ? : ? : 1;
? ? ? 1 ? ? : ? : 0;
0 ? 0 x ? ? : 0 : 0;
? ? 0 x 0 ? : 0 : 0;
1 0 0 x 1 ? : ? : 0;
0 ? x 0 ? ? : 1 : 1;
? ? x 0 0 ? : 1 : 1;
1 1 x 0 1 ? : ? : 1;
? ? ? ? ? * : ? : x;
endtable
endprimitive
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_mem_backbone.v
//
// *Module Description:
// Memory interface backbone (decoder + arbiter)
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_mem_backbone (
// OUTPUTs
dbg_mem_din, // Debug unit Memory data input
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
eu_mdb_in, // Execution Unit Memory data bus input
fe_mdb_in, // Frontend Memory data bus input
fe_pmem_wait, // Frontend wait for Instruction fetch
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dmem_dout, // Data Memory data output
eu_mab, // Execution Unit Memory address bus
eu_mb_en, // Execution Unit Memory bus enable
eu_mb_wr, // Execution Unit Memory bus write transfer
eu_mdb_out, // Execution Unit Memory data bus output
fe_mab, // Frontend Memory address bus
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
puc // Main system reset
);
// OUTPUTs
//=========
output [15:0] dbg_mem_din; // Debug unit Memory data input
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
output [15:0] fe_mdb_in; // Frontend Memory data bus input
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_addr; // Debug address for rd/wr access
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_mem_en; // Debug unit memory enable
input [1:0] dbg_mem_wr; // Debug unit memory write
input [15:0] dmem_dout; // Data Memory data output
input [14:0] eu_mab; // Execution Unit Memory address bus
input eu_mb_en; // Execution Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
input [14:0] fe_mab; // Frontend Memory address bus
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input puc; // Main system reset
//=============================================================================
// 1) DECODER
//=============================================================================
// RAM Interface
//------------------
// Execution unit access
wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1);
// Debug interface access
wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1);
// RAM Interface
wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
wire [1:0] dmem_wen = ~(dbg_mem_wr | eu_mb_wr);
wire [15:0] dmem_din = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out;
// ROM Interface
//------------------
parameter PMEM_OFFSET = (16'hFFFF-`PMEM_SIZE+1);
// Execution unit access (only read access are accepted)
wire eu_pmem_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1)));
wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1);
// Front-end access
wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
// Debug interface access
wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1);
// ROM Interface (Execution unit has priority)
wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
wire pmem_cen = fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen;
wire [1:0] pmem_wen = ~dbg_mem_wr;
wire [15:0] pmem_din = dbg_mem_dout;
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
// Peripherals
//--------------------
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
reg [15:0] per_dout_val;
always @ (posedge mclk or posedge puc)
if (puc) per_dout_val <= 16'h0000;
else per_dout_val <= per_dout;
// Frontend data Mux
//---------------------------------
// Whenever the frontend doesn't access the ROM, backup the data
// Detect whenever the data should be backuped and restored
reg fe_pmem_cen_dly;
always @(posedge mclk or posedge puc)
if (puc) fe_pmem_cen_dly <= 1'b0;
else fe_pmem_cen_dly <= fe_pmem_cen;
wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
reg [15:0] pmem_dout_bckup;
always @(posedge mclk or posedge puc)
if (puc) pmem_dout_bckup <= 16'h0000;
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
// Mux between the ROM data and the backup
reg pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc)
if (puc) pmem_dout_bckup_sel <= 1'b0;
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
// Execution-Unit data Mux
//---------------------------------
// Select between peripherals, RAM and ROM
reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc)
if (puc) eu_mdb_in_sel <= 2'b00;
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
// Mux
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
// Debug interface data Mux
//---------------------------------
// Select between peripherals, RAM and ROM
reg [1:0] dbg_mem_din_sel;
always @(posedge mclk or posedge puc)
if (puc) dbg_mem_din_sel <= 2'b00;
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
// Mux
assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
endmodule // omsp_mem_backbone
`include "openMSP430_undefines.v"
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_V |
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* Mesh Network
*
*/
`include "types.v"
`include "parameters.v"
module LAG_mesh_network (din, dout,
input_full_flag,
cntrl_in,
clk, rst_n);
parameter XS=network_x;
parameter YS=network_y;
parameter NT=router_radix;
parameter NPL=router_num_pls;
// parameter channel_latency = 0; // number of registers in router to router link or channel
input clk, rst_n;
input [XS*YS*$bits(chan_cntrl_t) - 1 : 0] cntrl_in;
input [XS*YS*$bits(flit_t) - 1 : 0] din;
output [XS*YS*router_num_pls_on_exit*$bits(flit_t) - 1 : 0] dout;
output [XS*YS*router_num_pls_on_entry - 1 : 0] input_full_flag;
// network connections
flit_t i_flit_in [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_in_ [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_out [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_out_ [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t terminator [NPL-1:0];
chan_cntrl_t i_cntrl_in [XS-1:0][YS-1:0][NT-1:0];
chan_cntrl_t i_cntrl_out [XS-1:0][YS-1:0][NT-1:0];
reg clk_g [XS-1:0][YS-1:0];
genvar x,y,p,c;
// *********************************************************
// implement router-level clock gating if requested
// *********************************************************
//
generate
for (y=0; y<YS; y=y+1) begin:ycg
for (x=0; x<XS; x=x+1) begin:xcg
//
// no router level clock gating, router clock = global clock
//
always@(clk) begin
clk_g[x][y]<=clk;
end
end // block: xcg
end // block: ycg
endgenerate
// *********************************************************
generate
for (y=0; y<YS; y=y+1) begin:yl
for (x=0; x<XS; x=x+1) begin:xl
//
// make network connections
//
// tile port - external interface
always_comb
begin
i_flit_in[x][y][`TILE] = terminator;
i_flit_in[x][y][`TILE][0] = din[$bits(flit_t)*(x*YS + y + 1) - 1 : $bits(flit_t)*(x*YS + y)]; ;
end
assign i_cntrl_in[x][y][`TILE] = cntrl_in[$bits(chan_cntrl_t)*(x*YS + y + 1) - 1 : $bits(chan_cntrl_t)*(x*YS + y)];
for (c=0; c<router_num_pls_on_exit; c++) begin:network_out_to_sink
assign dout[$bits(flit_t)*(x*YS*router_num_pls_on_exit + y*router_num_pls_on_exit + c + 1) - 1 : $bits(flit_t)*(x*YS*router_num_pls_on_exit + y*router_num_pls_on_exit + c)] = i_flit_out[x][y][`TILE][c];
end
// north port
if (y==0) begin
assign i_flit_in[x][y][`NORTH] = terminator;
assign i_cntrl_in[x][y][`NORTH] = '0;
end else begin
assign i_flit_in[x][y][`NORTH] = i_flit_out[x][y-1][`SOUTH];
assign i_cntrl_in[x][y][`NORTH] = i_cntrl_out[x][y-1][`SOUTH];
end
// east port
if (x==XS-1) begin
assign i_flit_in[x][y][`EAST] = terminator;
assign i_cntrl_in[x][y][`EAST] = '0;
end else begin
assign i_flit_in[x][y][`EAST] = i_flit_out[x+1][y][`WEST];
assign i_cntrl_in[x][y][`EAST] = i_cntrl_out[x+1][y][`WEST];
end
// south port
if (y==YS-1) begin
assign i_flit_in[x][y][`SOUTH] = terminator;
assign i_cntrl_in[x][y][`SOUTH] = '0;
end else begin
assign i_flit_in[x][y][`SOUTH] = i_flit_out[x][y+1][`NORTH];
assign i_cntrl_in[x][y][`SOUTH] = i_cntrl_out[x][y+1][`NORTH];
end
// west port
if (x==0) begin
assign i_flit_in[x][y][`WEST] = terminator;
assign i_cntrl_in[x][y][`WEST] = '0;
end else begin
assign i_flit_in[x][y][`WEST] = i_flit_out[x-1][y][`EAST];
assign i_cntrl_in[x][y][`WEST] = i_cntrl_out[x-1][y][`EAST];
end
for (p=0; p<NT; p++) begin:prts
for (c=0; c<NPL; c++) begin:channels2
always_comb
begin
i_flit_in_[x][y][p][c] = i_flit_in[x][y][p][c];
end
end
end
// ###################################
// Channel (link) between routers - ** NOT FROM ROUTER TO TILE **
// ###################################
// i_flit_out_ -> CHANNEL -> i_flit_out
//
/*for (p=0; p<NT; p++) begin:prts2
assign i_flit_out[x][y][p]=i_flit_out_[x][y][p];
end*/
for (p=0; p<NT; p++) begin:prts2
if (p==`TILE) begin
// router to tile is a local connection
assign i_flit_out[x][y][p]=i_flit_out_[x][y][p];
end else begin
LAG_pipelined_channel #(.nPC(NPL), .stages(channel_latency)) channel
(.data_in(i_flit_out_[x][y][p]),
.data_out(i_flit_out[x][y][p]), .clk, .rst_n);
end
end
// ###################################
// Router
// ###################################
// # parameters for router are read from parameters.v
LAG_router #(
.buf_len(router_buf_len),
.network_x(network_x),
.network_y(network_y),
.NT(router_radix),
.NPL(router_num_pls),
.alloc_stages(router_alloc_stages),
.router_num_pls_on_entry(router_num_pls_on_entry),
.router_num_pls_on_exit(router_num_pls_on_exit)
) node
(i_flit_in_[x][y],
i_flit_out_[x][y],
i_cntrl_in[x][y],
i_cntrl_out[x][y],
input_full_flag[router_num_pls_on_entry*(x*YS + y + 1) - 1 : router_num_pls_on_entry*(x*YS + y)],
clk_g[x][y],
rst_n);
end //x
end //y
endgenerate
endmodule
|
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module mux16x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux2x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [1:0] out;
input [1:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x2(data0, data1, selectInput, out); // 2-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1;
input selectInput;
always@(data0 or data1 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
endcase
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IP demultiplexer
*/
module ip_demux #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [DATA_WIDTH-1:0] s_ip_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire [ID_WIDTH-1:0] s_ip_payload_axis_tid,
input wire [DEST_WIDTH-1:0] s_ip_payload_axis_tdest,
input wire [USER_WIDTH-1:0] s_ip_payload_axis_tuser,
/*
* IP frame outputs
*/
output wire [M_COUNT-1:0] m_ip_hdr_valid,
input wire [M_COUNT-1:0] m_ip_hdr_ready,
output wire [M_COUNT*48-1:0] m_eth_dest_mac,
output wire [M_COUNT*48-1:0] m_eth_src_mac,
output wire [M_COUNT*16-1:0] m_eth_type,
output wire [M_COUNT*4-1:0] m_ip_version,
output wire [M_COUNT*4-1:0] m_ip_ihl,
output wire [M_COUNT*6-1:0] m_ip_dscp,
output wire [M_COUNT*2-1:0] m_ip_ecn,
output wire [M_COUNT*16-1:0] m_ip_length,
output wire [M_COUNT*16-1:0] m_ip_identification,
output wire [M_COUNT*3-1:0] m_ip_flags,
output wire [M_COUNT*13-1:0] m_ip_fragment_offset,
output wire [M_COUNT*8-1:0] m_ip_ttl,
output wire [M_COUNT*8-1:0] m_ip_protocol,
output wire [M_COUNT*16-1:0] m_ip_header_checksum,
output wire [M_COUNT*32-1:0] m_ip_source_ip,
output wire [M_COUNT*32-1:0] m_ip_dest_ip,
output wire [M_COUNT*DATA_WIDTH-1:0] m_ip_payload_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep,
output wire [M_COUNT-1:0] m_ip_payload_axis_tvalid,
input wire [M_COUNT-1:0] m_ip_payload_axis_tready,
output wire [M_COUNT-1:0] m_ip_payload_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_ip_payload_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_ip_payload_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_ip_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg [M_COUNT-1:0] m_ip_hdr_valid_reg = 0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_int;
reg [M_COUNT-1:0] m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg && enable;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg && enable;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = {M_COUNT{m_eth_dest_mac_reg}};
assign m_eth_src_mac = {M_COUNT{m_eth_src_mac_reg}};
assign m_eth_type = {M_COUNT{m_eth_type_reg}};
assign m_ip_version = {M_COUNT{m_ip_version_reg}};
assign m_ip_ihl = {M_COUNT{m_ip_ihl_reg}};
assign m_ip_dscp = {M_COUNT{m_ip_dscp_reg}};
assign m_ip_ecn = {M_COUNT{m_ip_ecn_reg}};
assign m_ip_length = {M_COUNT{m_ip_length_reg}};
assign m_ip_identification = {M_COUNT{m_ip_identification_reg}};
assign m_ip_flags = {M_COUNT{m_ip_flags_reg}};
assign m_ip_fragment_offset = {M_COUNT{m_ip_fragment_offset_reg}};
assign m_ip_ttl = {M_COUNT{m_ip_ttl_reg}};
assign m_ip_protocol = {M_COUNT{m_ip_protocol_reg}};
assign m_ip_header_checksum = {M_COUNT{m_ip_header_checksum_reg}};
assign m_ip_source_ip = {M_COUNT{m_ip_source_ip_reg}};
assign m_ip_dest_ip = {M_COUNT{m_ip_dest_ip_reg}};
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg & ~m_ip_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
if (s_ip_payload_axis_tvalid && s_ip_payload_axis_tready) begin
// end of frame detection
if (s_ip_payload_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_ip_hdr_valid && s_ip_hdr_ready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = frame_ctl;
s_ip_hdr_ready_next = 1'b0;
m_ip_hdr_valid_next = (!drop_ctl) << select_ctl;
m_eth_dest_mac_next = s_eth_dest_mac;
m_eth_src_mac_next = s_eth_src_mac;
m_eth_type_next = s_eth_type;
m_ip_version_next = s_ip_version;
m_ip_ihl_next = s_ip_ihl;
m_ip_dscp_next = s_ip_dscp;
m_ip_ecn_next = s_ip_ecn;
m_ip_length_next = s_ip_length;
m_ip_identification_next = s_ip_identification;
m_ip_flags_next = s_ip_flags;
m_ip_fragment_offset_next = s_ip_fragment_offset;
m_ip_ttl_next = s_ip_ttl;
m_ip_protocol_next = s_ip_protocol;
m_ip_header_checksum_next = s_ip_header_checksum;
m_ip_source_ip_next = s_ip_source_ip;
m_ip_dest_ip_next = s_ip_dest_ip;
end
s_ip_hdr_ready_next = !frame_next && !m_ip_hdr_valid_next;
s_ip_payload_axis_tready_next = (m_ip_payload_axis_tready_int_early || drop_ctl) && frame_ctl;
m_ip_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = s_ip_payload_axis_tkeep;
m_ip_payload_axis_tvalid_int = (s_ip_payload_axis_tvalid && s_ip_payload_axis_tready && !drop_ctl) << select_ctl;
m_ip_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_ip_payload_axis_tid_int = s_ip_payload_axis_tid;
m_ip_payload_axis_tdest_int = s_ip_payload_axis_tdest;
m_ip_payload_axis_tuser_int = s_ip_payload_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_ip_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_ip_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = {M_COUNT{m_ip_payload_axis_tdata_reg}};
assign m_ip_payload_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_ip_payload_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = {M_COUNT{m_ip_payload_axis_tlast_reg}};
assign m_ip_payload_axis_tid = ID_ENABLE ? {M_COUNT{m_ip_payload_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_ip_payload_axis_tdest = DEST_ENABLE ? {M_COUNT{m_ip_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_ip_payload_axis_tuser = USER_ENABLE ? {M_COUNT{m_ip_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if ((m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || !m_ip_payload_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tid_reg <= temp_m_ip_payload_axis_tid_reg;
m_ip_payload_axis_tdest_reg <= temp_m_ip_payload_axis_tdest_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O31A_BEHAVIORAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__A22O_FUNCTIONAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_FUNCTIONAL_V |
module control_fsm
(
input clk, reset, run_n,
input [15:0] sram_d, regA, regB, alu_status, alu_out,
output reg sram_we_n, reg_we,
output reg [2:0] alu_op,
output reg [3:0] reg_addr_a, reg_addr_b, reg_addr_c,
output [15:0] alu_op_a, reg_data_c,
output reg [15:0] sram_addr, sram_q
);
// Define bit widths
`define alu_op_size 3
//===========================================================================
// Parameter Declarations
//===========================================================================
// Declare states
parameter ADD = 5'd0;
parameter ADDI = 5'd1;
parameter SUB = 5'd2;
parameter SUBI = 5'd3;
parameter MULT = 5'd4;
parameter SW = 5'd5;
parameter LW = 5'd6;
parameter LT = 5'd7;
parameter NAND = 4'd8;
parameter DIV = 5'd9;
parameter MOD = 5'd10;
parameter LTE = 5'd11;
parameter BLT = 5'd12;
parameter BLE = 5'd13;
parameter BEQ = 5'd14;
parameter JUMP = 5'd15;
parameter FETCH = 5'd16;
parameter BLT2 = 5'd17;
parameter BLE2 = 5'd18;
parameter BEQ2 = 5'd19;
parameter SW2 = 5'd20;
parameter DECODE = 5'd21;
parameter LW2 = 5'd22;
parameter LW3 = 5'd23;
parameter SW3 = 5'd24;
parameter SW4 = 5'd25;
parameter JUMP2 = 5'd26;
parameter BLE3 = 5'd27;
parameter BLT3 = 5'd28;
parameter BEQ3 = 5'd29;
reg im_en;
reg [4:0] state;
reg [15:0] instruction,pc, regC;
wire ram_to_reg;
wire [3:0] op_code, op1, op2, op3, im;
wire [11:0] jump;
//wire [15:0] alu_op_a;
// assign the different fields of the instruction
assign op_code = instruction[15:12];
assign op1 = instruction[3:0];
assign op2 = instruction[7:4];
assign op3 = instruction[11:8];
assign im = instruction[3:0];
assign jump = instruction[11:0];
assign alu_op_a = im_en ? {12'd0, im} : regA;
assign ram_to_reg = (state == LW) | (state == LW2) | (state == LW3);
assign reg_data_c = ram_to_reg ? sram_d : alu_out;
// Determine the next state synchronously, based on the
// current state and the input
always @ (posedge clk or negedge reset) begin
if (reset == 1'b0) begin
state <= FETCH;
end else if(!run_n)
case (state)
FETCH:
state <= DECODE;
DECODE:
state <= {1'b0, op_code};
ADD:
state <= FETCH;
ADDI:
state <= FETCH;
SUB:
state <= FETCH;
SUBI:
state <= FETCH;
MULT:
state <= FETCH;
SW:
state <= SW2;
SW2:
state <= SW3;
SW3:
state <= SW4;
SW4:
state <= FETCH;
LW:
state <= LW2;
LW2:
state <= LW3;
LW3:
state <= FETCH;
LT:
state <= FETCH;
NAND:
state <= FETCH;
DIV:
state <= FETCH;
MOD:
state <= FETCH;
LTE:
state <= FETCH;
BLT:
state <= BLT2;
BLE:
state <= BLE2;
BEQ:
state <= BEQ2;
JUMP:
state <= JUMP2;
JUMP2:
state <= FETCH;
BLT2:
state <= BLT3;
BLT3:
state <= FETCH;
BLE2:
state <= BLE3;
BLE3:
state <= FETCH;
BEQ2:
state <= BEQ3;
BEQ3:
state <= FETCH;
default:
state <= FETCH;
endcase
end
// Determine the output based only on the current state
// and the input (do not wait for a clock edge).
always @ (posedge clk or negedge reset) begin
if(reset == 1'b0) begin
pc <= 16'h0000;
instruction <= 16'hf000; // jump to 0
sram_addr <= 16'h0000;
sram_we_n <= 1'b1;
sram_q <= 16'h0000;
end else begin
case (state)
FETCH: begin
instruction <= sram_d;
sram_addr <= pc;
sram_we_n <= 1'b1;
pc <= pc;
sram_q <= 16'hffff;
end
DECODE: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
ADD: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
ADDI: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
SUB: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
SUBI: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
MULT: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
SW: begin
sram_we_n <= 1'b1;// should work
sram_q <= regA;// port A
sram_addr <= alu_out;
pc <= pc;
instruction <= instruction;
end
SW2: begin
sram_we_n <= 1'b0;
sram_q <= regA;// port A
sram_addr <= alu_out;
pc <= pc;
instruction <= instruction;
end
SW3: begin
sram_we_n <= 1'b1;
sram_q <= regA;// port A
sram_addr <= pc;// for fetch cycle
pc <= pc;
instruction <= instruction;
end
SW4: begin
sram_we_n <= 1'b1;
sram_q <= regA;// port A
sram_addr <= pc;// for fetch cycle
pc <= pc + 16'd1;
instruction <= instruction;
end
LW:begin
sram_we_n <= 1'b1;
sram_addr <= alu_out;
pc <= pc;
instruction <= instruction;
sram_q <= 16'hffff;
end
LW2:begin
sram_we_n <= 1'b1;
sram_addr <= pc;
pc <= pc;
instruction <= instruction;
sram_q <= 16'hffff;
end
LW3:begin
sram_we_n <= 1'b1;
sram_addr <= pc;
pc <= pc + 16'd1;
instruction <= instruction;
sram_q <= 16'hffff;
end
LT: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
NAND: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
DIV: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
MOD: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
LTE: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
BLT: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
BLE: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
BEQ: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
JUMP: begin
// move back 1 because previous instruction adds 1 to pc
// extend MSB beacuse jump is signed
pc <= pc + {jump[11],jump[11],jump[11],jump[11],jump} - 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
// shortcut to save a clock cycle, no need to wait for pc to update
sram_addr <= pc + {jump[11],jump[11],jump[11],jump[11],jump} - 16'd1;// extend MSB beacuse jump is signed
end
JUMP2: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
// pc should be updated now
sram_addr <= pc;
end
BLT2: begin
if(alu_status == 16'd1) begin
pc <= pc + {12'd0, im};
sram_addr <= pc + {12'd0, im};
end else begin
pc <= pc;
sram_addr <= sram_addr;
end
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
end
BLT3: begin
// made to look like BLE3
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;
end
BLE2: begin
if(alu_status == 16'd1) begin
pc <= pc + {12'd0, im};
sram_addr <= pc + {12'd0, im};
end else begin
pc <= pc; // + 16'd1;
sram_addr <= sram_addr;
end
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
end
BLE3: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;
end
BEQ2: begin
if(alu_status == 16'd0) begin
pc <= pc + {12'd0, im};
sram_addr <= pc + {12'd0, im};
end else begin
pc <= pc; // + 16'd1;
sram_addr <= sram_addr; //pc + 16'd1;
end
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
end
BEQ3: begin
// made to look like BLE3
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;
end
default: begin
pc <= 16'd0; // reset program
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
endcase
end
end
always@(*) begin
case (state)
FETCH: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
DECODE: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
ADD: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
ADDI: begin
reg_addr_a = 4'hx; // dont care
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
end
SUB: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h1;
im_en = 1'b0;
end
SUBI: begin
reg_addr_a = 4'hx; // dont care
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h1;
im_en = 1'b1;
end
MULT: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h2;
im_en = 1'b0;
end
SW: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
end
SW2: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
SW3: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
SW4: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
LW:begin
reg_addr_a = 4'hx; // dont care, the immed field is used
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = op3; // op3 is the register addr to load into
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
LW2:begin
reg_addr_a = 4'hx; // dont care, the immed field is used
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = op3; // op3 is the register addr to load into
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
LW3:begin
reg_addr_a = 4'hx; // dont care, the immed field is used
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = op3; // op3 is the register addr to load into
reg_we = 1'b1;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
end
LT: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h6;
im_en = 1'b0;
end
NAND: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h3;
im_en = 1'b0;
end
DIV: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h4;
im_en = 1'b0;
end
MOD: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h5;
im_en = 1'b0;
end
LTE: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h7;
im_en = 1'b0;
end
BLT: begin
reg_addr_a = op3;
reg_addr_b = op2;
reg_addr_c = 4'hx;
reg_we = 1'b0;
alu_op = `alu_op_size'h6;
im_en = 1'b0;
end
BLE: begin
reg_addr_a = op3;
reg_addr_b = op2;
reg_addr_c = 4'hx;
reg_we = 1'b0;
alu_op = `alu_op_size'h7;
im_en = 1'b0;
end
BEQ: begin
reg_addr_a = op3;
reg_addr_b = op2;
reg_addr_c = 4'hx;
reg_we = 1'b0;
alu_op = `alu_op_size'h1;
im_en = 1'b0;
end
JUMP: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
JUMP2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLT2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLE2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BEQ2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLT3: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLE3: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BEQ3: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
default: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module main(
input [7:0] pc,
output [7:0] pb,
output [7:0] pd,
input CS,
input CLK,
input RESET,
input RESET2,
input WR,
input RD,
input SLOWCLK,
input [1:0] fpgaID // Can be used to differentiate between FPGA's on single board
);
wire CLK1_internal;
wire CLK2_internal;
wire [7:0] pc_internal;
wire [7:0] pb_internal;
wire [7:0] pb_out;
wire [7:0] pd_internal;
wire [7:0] pb_out_delayed;
wire [7:0] pd_out;
wire input_full;
wire input_empty;
wire output_full;
wire output_empty;
wire locked;
wire input_empty_delay;
wire SLOW;
clock_generator clock_generator_instance
(// Clock in ports
.CLK_IN1(CLK), // IN
// Clock out ports
.CLK_OUT1(CLK1_internal), // OUT
.CLK_OUT2(CLK2_internal), // OUT
// Status and control signals
.RESET(RESET), // IN
.LOCKED(locked) // OUT
);
slower slower_instance
(
.CLK(CLK1_internal), //input CLK,
.SLOWCLK(SLOWCLK), //input SLOWCLK,
.RESET(RESET2), //input RESET,
.EN_OUT(SLOW) //output EN_OUT
);
io_queue input_queue (
.rst(RESET2), // input rst
.wr_clk(CLK1_internal), // input wr_clk
.rd_clk(CLK2_internal), // input rd_clk
.din(pc), // input [7 : 0] din
// .wr_en(CS && WR && SLOW), // input wr_en
.wr_en(WR && SLOW), // input wr_en
.rd_en(1'b1), // input rd_en
.dout(pc_internal), // output [7 : 0] dout
.full(input_full), // output full
.empty(input_empty) // output empty
);
wire [63:0] pc_internal_64;
wire [63:0] pb_internal_64;
wire [63:0] pb_internal_64_out;
wire srl_ready;
srl8_to_64 srl8_to_64_instance(
.clk(CLK2_internal), .enable(input_empty), .reset(RESET2), .dataIn(pc_internal), .ready(srl_ready), .result(pc_internal_64)
);
wire [67:0] Ktest;
descrypt_salt des_core(
.Din(64'h0),
.K(pc_internal_64 << 1),
.salt(12'b111001101111), // Static salt for now
.Kout(Ktest),
.CLK(CLK2_internal),
.L_out(pb_internal_64[63:32]),
.R_out(pb_internal_64[31:0])
);
wire converter_empty;
wire converter_empty_delay;
// For now tests only against non-zero key
// Exchanging pb_internal_64 and test value will create bruter
comparer comparer_instance(
//.Din({8'b0, Ktest[55:0]}),// input [width:0] Din,
//.test(pb_internal_64),
.Din(pb_internal_64),// input [width:0] Din,
.test({8'b0, Ktest[55:0]}),
.CLK(CLK2_internal),// input CLK,
.reset(RESET2),// input reset,
.Dout(pb_internal_64_out), // output [width:0] Dout,
.good(input_empty_delay)// output good
);
queue64_to_8 size_conversion (
.rst(RESET2), // input rst
.wr_clk(CLK2_internal), // input wr_clk
.rd_clk(CLK2_internal), // input rd_clk
.din(pb_internal_64_out), // input [63 : 0] din
.wr_en(~input_empty_delay), // input wr_en
.rd_en(1'b1), // input rd_en
.dout(pb_internal), // output [7 : 0] dout
.full(), // output full
.empty(converter_empty) // output empty
);
//srl Delay2_instance(
// CLK2_internal, 1'b1, input_empty, input_empty_delay, 4'b0001
// CLK2_internal, 1'b1, converter_empty, converter_empty_delay, 4'b0000
//);
io_queue output_queue (
.rst(RESET2), // input rst
.wr_clk(CLK2_internal), // input wr_clk
.rd_clk(CLK1_internal), // input rd_clk
.din(pb_internal), // input [7 : 0] din
.wr_en(~converter_empty), // input wr_en
.rd_en((CS && RD && SLOW)), // input rd_en
.dout(pb_out), // output [7 : 0] dout
.full(output_full), // output full
.empty(output_empty) // output empty
// .rd_data_count(pd_out)
);
///*
assign pd_out[7] = input_full;
assign pd_out[6] = input_empty;
assign pd_out[5] = output_full;
assign pd_out[4] = output_empty;
assign pd_out[3] = 1'b0;
assign pd_out[2] = 1'b0;
assign pd_out[1] = 1'b0;
assign pd_out[0] = locked;
//*/
assign pb = (CS==1) ? pb_out : 8'bZ;
assign pd = (CS==1) ? pd_out : 8'bZ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_BEHAVIORAL_V |
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:56 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 128 reg
// wsiM0_MByteEn O 16 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 128
// wsiS0_MByteEn I 16
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBiasWorker16B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [127 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [15 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [127 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [15 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [127 : 0] wsiM0_MData;
wire [31 : 0] wciS0_SData;
wire [15 : 0] wsiM0_MByteEn;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [168 : 0] wsiM_reqFifo_x_wire_wget, wsiS_wsiReq_wget;
wire [127 : 0] wsi_Es_mData_w_wget;
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] wci_wci_Es_mAddr_w_wget, wci_wci_Es_mData_w_wget;
wire [15 : 0] wsi_Es_mByteEn_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wsi_Es_mCmd_w_wget;
wire wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register biasValue
reg [31 : 0] biasValue;
wire [31 : 0] biasValue_D_IN;
wire biasValue_EN;
// register controlReg
reg [31 : 0] controlReg;
wire [31 : 0] controlReg_D_IN;
wire controlReg_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [168 : 0] wsiM_reqFifo_q_0;
reg [168 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [168 : 0] wsiM_reqFifo_q_1;
reg [168 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wsiS_reqFifo
wire [168 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [168 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_biasValue_write_1__SEL_1,
MUX_biasValue_write_1__SEL_2,
MUX_controlReg_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h11230, v__h11385, v__h3574, v__h3749, v__h3893;
reg [31 : 0] _theResult____h11369;
wire [127 : 0] x_data__h10099;
wire [31 : 0] rdat__h11459,
rdat__h11559,
rdat__h11573,
rdat__h11581,
rdat__h11587,
rdat__h11601,
rdat__h11609;
wire [15 : 0] x__h11463;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
wire _dfoo1, _dfoo3, _dfoo5, _dfoo7;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[168:166] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[165] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[164] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[163:152] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[151:24] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[23:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd169),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
!MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[168:166] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_biasValue_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ;
assign MUX_biasValue_write_1__SEL_2 =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
assign MUX_controlReg_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 =
{ 2'd1, _theResult____h11369 } ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
{ wsiS_reqFifo_D_OUT[168:152],
x_data__h10099,
wsiS_reqFifo_D_OUT[23:0] } ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
MUX_biasValue_write_1__SEL_2 ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register biasValue
assign biasValue_D_IN =
MUX_biasValue_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign biasValue_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ||
MUX_biasValue_write_1__SEL_2 ;
// register controlReg
assign controlReg_D_IN =
MUX_controlReg_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign controlReg_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ||
MUX_biasValue_write_1__SEL_2 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[165]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN =
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[165]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[165] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[165] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[165] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[165] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo7 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign rdat__h11459 = hasDebugLogic ? { 16'd0, x__h11463 } : 32'd0 ;
assign rdat__h11559 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11573 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11581 = hasDebugLogic ? wsiS_extStatusW_wget[31:0] : 32'd0 ;
assign rdat__h11587 = hasDebugLogic ? wsiM_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11601 = hasDebugLogic ? wsiM_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11609 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign x__h11463 = { wsiS_statusR, wsiM_statusR } ;
assign x_data__h10099 =
{ wsiS_reqFifo_D_OUT[151:120] + biasValue,
wsiS_reqFifo_D_OUT[119:88] + biasValue,
wsiS_reqFifo_D_OUT[87:56] + biasValue,
wsiS_reqFifo_D_OUT[55:24] + biasValue } ;
always@(wci_wslv_reqF_D_OUT or
biasValue or
controlReg or
rdat__h11459 or
rdat__h11559 or
rdat__h11573 or
rdat__h11581 or rdat__h11587 or rdat__h11601 or rdat__h11609)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0: _theResult____h11369 = biasValue;
8'h04: _theResult____h11369 = controlReg;
8'h20: _theResult____h11369 = rdat__h11459;
8'h24: _theResult____h11369 = rdat__h11559;
8'h28: _theResult____h11369 = rdat__h11573;
8'h2C: _theResult____h11369 = rdat__h11581;
8'h30: _theResult____h11369 = rdat__h11587;
8'h34: _theResult____h11369 = rdat__h11601;
8'h38: _theResult____h11369 = rdat__h11609;
default: _theResult____h11369 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (biasValue_EN) biasValue <= `BSV_ASSIGNMENT_DELAY biasValue_D_IN;
if (controlReg_EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
biasValue = 32'hAAAAAAAA;
controlReg = 32'hAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3574 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3574,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h11230 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h11230,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
wci_wslv_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3893 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3893,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3749 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3749,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h11385 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h11385,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
_theResult____h11369);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkBiasWorker16B
|
(* abc9_box, lib_whitebox *)
module \$__ICE40_CARRY_WRAPPER (
(* abc9_carry *)
output CO,
output O,
input A, B,
(* abc9_carry *)
input CI,
input I0, I3
);
parameter LUT = 0;
parameter I3_IS_CI = 0;
wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(LUT)
) adder (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3_OR_CI),
.O(O)
);
`ifdef ICE40_HX
specify
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
(CI => CO) = (126, 105);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
(I0 => O) = (449, 386);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
(A => CO) = (259, 245);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
(A => O) = (400, 379);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
(B => CO) = (231, 133);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
(B => O) = (379, 351);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
(I3 => O) = (316, 288);
(CI => O) = (316, 288);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
(CI => CO) = (186, 155);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
(I0 => O) = (662, 569);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
(A => CO) = (382, 362);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
(A => O) = (589, 558);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
(B => CO) = (341, 196);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
(B => O) = (558, 517);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
(I3 => O) = (465, 423);
(CI => O) = (465, 423);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
(CI => CO) = (278, 278);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
(I0 => O) = (1245, 1285);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
(A => CO) = (675, 662);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
(A => O) = (1179, 1232);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
(B => CO) = (609, 358);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
(B => O) = (1179, 1205);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
(I3 => O) = (861, 874);
(CI => O) = (861, 874);
endspecify
`endif
endmodule
|
//Listing 9.1
module ps2_rx
(
input wire clk, reset,
inout wire ps2d, ps2c,
input wire rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1'b1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule |
/*
* cpu. - five stage MIPS CPU.
*
* Many variables (wires) pass through several stages.
* The naming convention used for each stage is
* accomplished by appending the stage number (_s<num>).
* For example the variable named "data" which is
* in stage 2 and stage 3 would be named as follows.
*
* wire data_s2;
* wire data_s3;
*
* If the stage number is omitted it is assumed to
* be at the stage at which the variable is first
* established.
*/
`include "regr.v"
`include "im.v"
`include "regm.v"
`include "control.v"
`include "alu.v"
`include "alu_control.v"
`include "dm.v"
`ifndef DEBUG_CPU_STAGES
`define DEBUG_CPU_STAGES 0
`endif
module cpu(
input wire clk);
parameter NMEM = 20; // number in instruction memory
parameter IM_DATA = "im_data.txt";
wire regwrite_s5;
wire [4:0] wrreg_s5;
wire [31:0] wrdata_s5;
reg stall_s1_s2;
// {{{ diagnostic outputs
initial begin
if (`DEBUG_CPU_STAGES) begin
$display("if_pc, if_instr, id_regrs, id_regrt, ex_alua, ex_alub, ex_aluctl, mem_memdata, mem_memread, mem_memwrite, wb_regdata, wb_regwrite");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
pc, /* if_pc */
inst, /* if_instr */
data1, /* id_regrs */
data2, /* id_regrt */
data1_s3, /* data1_s3 */
alusrc_data2, /* alusrc_data2 */
aluctl, /* ex_aluctl */
data2_s4, /* mem_memdata */
memread_s4, /* mem_memread */
memwrite_s4, /* mem_memwrite */
wrdata_s5, /* wb_regdata */
regwrite_s5 /* wb_regwrite */
);
end
end
// }}}
// {{{ flush control
reg flush_s1, flush_s2, flush_s3;
always @(*) begin
flush_s1 <= 1'b0;
flush_s2 <= 1'b0;
flush_s3 <= 1'b0;
if (pcsrc | jump_s4) begin
flush_s1 <= 1'b1;
flush_s2 <= 1'b1;
flush_s3 <= 1'b1;
end
end
// }}}
// {{{ stage 1, IF (fetch)
reg [31:0] pc;
initial begin
pc <= 32'd0;
end
wire [31:0] pc4; // PC + 4
assign pc4 = pc + 4;
always @(posedge clk) begin
if (stall_s1_s2)
pc <= pc;
else if (pcsrc == 1'b1)
pc <= baddr_s4;
else if (jump_s4 == 1'b1)
pc <= jaddr_s4;
else
pc <= pc4;
end
// pass PC + 4 to stage 2
wire [31:0] pc4_s2;
regr #(.N(32)) regr_pc4_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(pc4), .out(pc4_s2));
// instruction memory
wire [31:0] inst;
wire [31:0] inst_s2;
im #(.NMEM(NMEM), .IM_DATA(IM_DATA))
im1(.clk(clk), .addr(pc), .data(inst));
regr #(.N(32)) regr_im_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(inst), .out(inst_s2));
// }}}
// {{{ stage 2, ID (decode)
// decode instruction
wire [5:0] opcode;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [15:0] imm;
wire [4:0] shamt;
wire [31:0] jaddr_s2;
wire [31:0] seimm; // sign extended immediate
//
assign opcode = inst_s2[31:26];
assign rs = inst_s2[25:21];
assign rt = inst_s2[20:16];
assign rd = inst_s2[15:11];
assign imm = inst_s2[15:0];
assign shamt = inst_s2[10:6];
assign jaddr_s2 = {pc[31:28], inst_s2[25:0], {2{1'b0}}};
assign seimm = {{16{inst_s2[15]}}, inst_s2[15:0]};
// register memory
wire [31:0] data1, data2;
regm regm1(.clk(clk), .read1(rs), .read2(rt),
.data1(data1), .data2(data2),
.regwrite(regwrite_s5), .wrreg(wrreg_s5),
.wrdata(wrdata_s5));
// pass rs to stage 3 (for forwarding)
wire [4:0] rs_s3;
regr #(.N(5)) regr_s2_rs(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(rs), .out(rs_s3));
// transfer register data to stage 3
wire [31:0] data1_s3, data2_s3;
regr #(.N(64)) reg_s2_mem(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({data1, data2}),
.out({data1_s3, data2_s3}));
// transfer seimm, rt, and rd to stage 3
wire [31:0] seimm_s3;
wire [4:0] rt_s3;
wire [4:0] rd_s3;
regr #(.N(32)) reg_s2_seimm(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in(seimm), .out(seimm_s3));
regr #(.N(10)) reg_s2_rt_rd(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({rt, rd}), .out({rt_s3, rd_s3}));
// transfer PC + 4 to stage 3
wire [31:0] pc4_s3;
regr #(.N(32)) reg_pc4_s2(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(pc4_s2), .out(pc4_s3));
// control (opcode -> ...)
wire regdst;
wire branch_eq_s2;
wire branch_ne_s2;
wire memread;
wire memwrite;
wire memtoreg;
wire [1:0] aluop;
wire regwrite;
wire alusrc;
wire jump_s2;
//
control ctl1(.opcode(opcode), .regdst(regdst),
.branch_eq(branch_eq_s2), .branch_ne(branch_ne_s2),
.memread(memread),
.memtoreg(memtoreg), .aluop(aluop),
.memwrite(memwrite), .alusrc(alusrc),
.regwrite(regwrite), .jump(jump_s2));
// shift left, seimm
wire [31:0] seimm_sl2;
assign seimm_sl2 = {seimm[29:0], 2'b0}; // shift left 2 bits
// branch address
wire [31:0] baddr_s2;
assign baddr_s2 = pc4_s2 + seimm_sl2;
// transfer the control signals to stage 3
wire regdst_s3;
wire memread_s3;
wire memwrite_s3;
wire memtoreg_s3;
wire [1:0] aluop_s3;
wire regwrite_s3;
wire alusrc_s3;
// A bubble is inserted by setting all the control signals
// to zero (stall_s1_s2).
regr #(.N(8)) reg_s2_control(.clk(clk), .clear(stall_s1_s2), .hold(1'b0),
.in({regdst, memread, memwrite,
memtoreg, aluop, regwrite, alusrc}),
.out({regdst_s3, memread_s3, memwrite_s3,
memtoreg_s3, aluop_s3, regwrite_s3, alusrc_s3}));
wire branch_eq_s3, branch_ne_s3;
regr #(.N(2)) branch_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in({branch_eq_s2, branch_ne_s2}),
.out({branch_eq_s3, branch_ne_s3}));
wire [31:0] baddr_s3;
regr #(.N(32)) baddr_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(baddr_s2), .out(baddr_s3));
wire jump_s3;
regr #(.N(1)) reg_jump_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(jump_s2),
.out(jump_s3));
wire [31:0] jaddr_s3;
regr #(.N(32)) reg_jaddr_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(jaddr_s2), .out(jaddr_s3));
// }}}
// {{{ stage 3, EX (execute)
// pass through some control signals to stage 4
wire regwrite_s4;
wire memtoreg_s4;
wire memread_s4;
wire memwrite_s4;
regr #(.N(4)) reg_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in({regwrite_s3, memtoreg_s3, memread_s3,
memwrite_s3}),
.out({regwrite_s4, memtoreg_s4, memread_s4,
memwrite_s4}));
// ALU
// second ALU input can come from an immediate value or data
wire [31:0] alusrc_data2;
assign alusrc_data2 = (alusrc_s3) ? seimm_s3 : fw_data2_s3;
// ALU control
wire [3:0] aluctl;
wire [5:0] funct;
assign funct = seimm_s3[5:0];
alu_control alu_ctl1(.funct(funct), .aluop(aluop_s3), .aluctl(aluctl));
// ALU
wire [31:0] alurslt;
reg [31:0] fw_data1_s3;
always @(*)
case (forward_a)
2'd1: fw_data1_s3 = alurslt_s4;
2'd2: fw_data1_s3 = wrdata_s5;
default: fw_data1_s3 = data1_s3;
endcase
wire zero_s3;
alu alu1(.ctl(aluctl), .a(fw_data1_s3), .b(alusrc_data2), .out(alurslt),
.zero(zero_s3));
wire zero_s4;
regr #(.N(1)) reg_zero_s3_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(zero_s3), .out(zero_s4));
// pass ALU result and zero to stage 4
wire [31:0] alurslt_s4;
regr #(.N(32)) reg_alurslt(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in({alurslt}),
.out({alurslt_s4}));
// pass data2 to stage 4
wire [31:0] data2_s4;
reg [31:0] fw_data2_s3;
always @(*)
case (forward_b)
2'd1: fw_data2_s3 = alurslt_s4;
2'd2: fw_data2_s3 = wrdata_s5;
default: fw_data2_s3 = data2_s3;
endcase
regr #(.N(32)) reg_data2_s3(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(fw_data2_s3), .out(data2_s4));
// write register
wire [4:0] wrreg;
wire [4:0] wrreg_s4;
assign wrreg = (regdst_s3) ? rd_s3 : rt_s3;
// pass to stage 4
regr #(.N(5)) reg_wrreg(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(wrreg), .out(wrreg_s4));
wire branch_eq_s4, branch_ne_s4;
regr #(.N(2)) branch_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in({branch_eq_s3, branch_ne_s3}),
.out({branch_eq_s4, branch_ne_s4}));
wire [31:0] baddr_s4;
regr #(.N(32)) baddr_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(baddr_s3), .out(baddr_s4));
wire jump_s4;
regr #(.N(1)) reg_jump_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(jump_s3),
.out(jump_s4));
wire [31:0] jaddr_s4;
regr #(.N(32)) reg_jaddr_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(jaddr_s3), .out(jaddr_s4));
// }}}
// {{{ stage 4, MEM (memory)
// pass regwrite and memtoreg to stage 5
wire memtoreg_s5;
regr #(.N(2)) reg_regwrite_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in({regwrite_s4, memtoreg_s4}),
.out({regwrite_s5, memtoreg_s5}));
// data memory
wire [31:0] rdata;
dm dm1(.clk(clk), .addr(alurslt_s4[8:2]), .rd(memread_s4), .wr(memwrite_s4),
.wdata(data2_s4), .rdata(rdata));
// pass read data to stage 5
wire [31:0] rdata_s5;
regr #(.N(32)) reg_rdata_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(rdata),
.out(rdata_s5));
// pass alurslt to stage 5
wire [31:0] alurslt_s5;
regr #(.N(32)) reg_alurslt_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(alurslt_s4),
.out(alurslt_s5));
// pass wrreg to stage 5
regr #(.N(5)) reg_wrreg_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(wrreg_s4),
.out(wrreg_s5));
// branch
reg pcsrc;
always @(*) begin
case (1'b1)
branch_eq_s4: pcsrc <= zero_s4;
branch_ne_s4: pcsrc <= ~(zero_s4);
default: pcsrc <= 1'b0;
endcase
end
// }}}
// {{{ stage 5, WB (write back)
assign wrdata_s5 = (memtoreg_s5 == 1'b1) ? rdata_s5 : alurslt_s5;
// }}}
// {{{ forwarding
// stage 3 (MEM) -> stage 2 (EX)
// stage 4 (WB) -> stage 2 (EX)
reg [1:0] forward_a;
reg [1:0] forward_b;
always @(*) begin
// If the previous instruction (stage 4) would write,
// and it is a value we want to read (stage 3), forward it.
// data1 input to ALU
if ((regwrite_s4 == 1'b1) && (wrreg_s4 == rs_s3)) begin
forward_a <= 2'd1; // stage 4
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rs_s3)) begin
forward_a <= 2'd2; // stage 5
end else
forward_a <= 2'd0; // no forwarding
// data2 input to ALU
if ((regwrite_s4 == 1'b1) & (wrreg_s4 == rt_s3)) begin
forward_b <= 2'd1; // stage 5
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rt_s3)) begin
forward_b <= 2'd2; // stage 5
end else
forward_b <= 2'd0; // no forwarding
end
// }}}
// {{{ load use data hazard detection, signal stall
/* If an operation in stage 4 (MEM) loads from memory (e.g. lw)
* and the operation in stage 3 (EX) depends on this value,
* a stall must be performed. The memory read cannot
* be forwarded because memory access is too slow. It can
* be forwarded from stage 5 (WB) after a stall.
*
* lw $1, 16($10) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $1, 32($12) ; I-type, rt_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $2, 32($1) ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* add $2, $1, $1 ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0
*/
always @(*) begin
if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin
stall_s1_s2 <= 1'b1; // perform a stall
end else
stall_s1_s2 <= 1'b0; // no stall
end
// }}}
endmodule
// vim:foldmethod=marker
|
//`define HIGH_BIOS 13'h0000
`define HIGH_BIOS 13'h00FF
module flash_dump (
input sys_clk_in,
output trx,
output [20:0] flash_addr,
input [15:0] flash_data,
output flash_we_n,
output flash_oe_n,
output flash_ce2
);
reg clk_9600;
reg [11:0] count_uart;
reg [ 6:0] dada_wr;
reg [ 7:0] estat;
reg [ 7:0] addr;
reg [ 2:0] espacios;
reg [ 6:0] char;
reg [ 3:0] nibble;
reg [ 7:0] col;
reg trx_req;
reg [ 7:0] adr0;
wire clk_60M;
wire rst, lock;
wire trx_ack;
wire [15:0] rd_data;
reg [15:0] ram[0:255];
reg [15:0] dades;
reg [ 3:0] count;
// Instanciacions de mòduls
clocks c0 (
.CLKIN_IN (sys_clk_in),
.CLKFX_OUT (clk_60M),
.LOCKED_OUT (lock)
);
uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx,
rst, clk_9600);
// Assignacions contínues
assign rst = ~lock;
assign flash_addr = { `HIGH_BIOS, adr0 };
assign rd_data = flash_data;
assign flash_we_n = 1'b1;
assign flash_oe_n = 1'b0;
assign flash_ce2 = 1'b1;
// Descripció del comportament
// count_uart
always @(posedge clk_60M)
if (rst) count_uart <= 12'h0;
else count_uart <= (count_uart==12'd3124) ?
12'd0 : count_uart + 12'd1;
// clk_9600
always @(posedge clk_60M)
if (rst) clk_9600 <= 1'b0;
else clk_9600 <= (count_uart==12'd0) ?
!clk_9600 : clk_9600;
// adr0
always @(posedge clk_60M)
if (rst) adr0 <= 8'h00;
else adr0 <= (adr0==8'hff || count!=4'hf) ? adr0
: (adr0 + 8'h01);
// count
always @(posedge clk_60M)
if (rst) count <= 4'h0;
else count <= count + 4'h1;
// ram
always @(posedge clk_60M) ram[adr0] <= rd_data;
// dades
always @(posedge clk_60M)
if (rst) dades <= 16'h0;
else dades <= ram[addr];
always @(posedge clk_60M)
if (adr0!=8'hff)
begin
dada_wr <= 7'h30;
trx_req <= 0;
estat <= 8'd0;
addr <= 8'h00;
espacios <= 3'd2;
char <= 7'd00;
nibble <= 4'd0;
col <= 8'd79;
end
else
case (estat)
8'd00: if (~trx_ack)
begin estat <= 8'd01;
if (espacios > 3'd0)
begin char <= 7'h20; espacios <= espacios - 3'd1; end
else
begin
char <= ascii(nibble); espacios <= 3'd4;
nibble <= nibble + 4'd1;
end
end
8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end
8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end
8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end
else estat <= 8'd04;
8'd04: if (~trx_ack) estat <= 8'd05;
8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end
8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end
8'd15: if (~trx_ack) estat <= 8'd20;
8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end
8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end
8'd30: if (~trx_ack) estat <= 8'd35;
8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end
8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end
8'd45: if (~trx_ack) estat <= 8'd50;
8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end
8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end
8'd60: if (~trx_ack) estat <= 8'd65;
8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end
8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end
8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90;
else if (~trx_ack) estat <= 8'd80;
8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end
8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end
8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end
else estat <= 8'd95;
8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15;
endcase
function [6:0] ascii(input [3:0] num);
if (num <= 4'd9) ascii = 7'h30 + num;
else ascii = 7'd87 + num;
endfunction
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "alu.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ppp; ctrl_ppp
reg [0:2] c_ppp;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// wrbyteen
reg [0:15] wbt;
// Dummy registers
//reg [0:15] a,b,c;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ppp,c_ww,a_op,res,wbt);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwadd AND aa AND w8
r_A=128'h0102030405060708090a0b0c0d0e0f10;
r_B=128'h01020304010203040507070809050607;
e_r=128'h0204060806080a0c0e11121416131517;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwadd;
wbt=16'd0;
#10
// aluwadd AND aa AND w8
r_A=128'hfffffffffffffffffffffffffffffff9;
r_B=128'h00000000000000000000000000000008;
e_r=128'hffffffffffffffffffffffffffffff01;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND aa AND w16
r_A=128'h00010002000300040005000600070008;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000300060009000c001100160019001c;
c_ppp=`aa;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND aa AND w32
r_A=128'h00000001000000020000000300000004;
r_B=128'h00000005000000060000000700000008;
e_r=128'h00000006000000080000000a0000000c;
c_ppp=`aa;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=40
// aluwadd AND uu AND w8
r_A=128'h0102030405060708090a0b0c0d0f1011;
r_B=128'h01010202030303030405060104050601;
e_r=128'h0203050608090a0b0d10130d11141612;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND uu AND w32
r_A=128'h00010002000300040005000600070008;
r_B=128'h00020002000300030001000100010003;
e_r=128'h0003000400060007000600070008000b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND uu AND w32
r_A=128'h00000001000000020000000300000004;
r_B=128'h00000005000000060000000700000008;
e_r=128'h00000006000000080000000100000002;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=70
// aluwadd AND dd AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'h0d10130d111416120203050608090a0b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND dd AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'h000600070008000b0003000400060007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND dd AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'h00000001000000020000000600000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=100
// aluwadd AND oo AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'hff0ffe0dfd14fc12fb03fa06f909f80b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND oo AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'he0010007e002000be0030004e0040007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND oo AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'hff0000f10000000cff0000f200000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=130
// aluwadd AND ee AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'h0dff11fe11fd16fc02fb05fa08f90afb;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND ee AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'h0006e0010008e0020003e0030006e004;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND ee AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'h0000000aff0000f100000006f200000d;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=160
// aluwadd AND mm AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'h0dff11ffdd004499bb7733ccdd221199;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND mm AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'h0006e00e0008e002e003e003e006e004;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND mm AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'h0000000aff0000f1ff000006ff00000d;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=190
// aluwadd AND ll AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'hcdff11ffdd004499bb7733ccdd22110b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ll;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND ll AND w32
r_A=128'h00050006000700080001000200000004;
r_B=128'h00010001000100030002000200000003;
e_r=128'hc006e00e0008e002e003e003e0000007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ll;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND ll AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'hc000000dff0000f1ff00000600000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ll;
c_ww=`w32;
a_op=`aluwadd;
/**
* ========================================
* ========================================
*
* AND INSTRUCTION
*
* ========================================
* ========================================
*/
#10 //TIME=220
// aluwand AND aa AND w8
r_A=128'h5b76abfdedbe9389ddcf35f657afebb6;
r_B=128'h9389ddcf35f65b76abfdedbe98dc3f39;
e_r=128'h130089cd25b6130089cd25b6108c2b30;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwand;
#10
// aluwand AND aa AND w16
r_A=128'h00050007000d000e001e00d600170018;
r_B=128'h0009000800050006001300f600180017;
e_r=128'h0001000000050006001200d600100010;
c_ppp=`aa;
c_ww=`w16;
a_op=`aluwand;
#10
// aluwand AND aa AND w32
r_A=128'h0000000f0000000e0000000b0000000a;
r_B=128'h0000000c000000030000000d0000000d;
e_r=128'h0000000c000000020000000900000008;
c_ppp=`aa;
c_ww=`w32;
a_op=`aluwand;
// ======================================
#10 //TIME=250
// aluwand AND uu AND w8
r_A=128'h0e0a0d0d0b0e0d0b090a0b0c0d0f1011;
r_B=128'h030d0f050f060b030405060104050601;
e_r=128'h02080d050b0609030d10130d11141612;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w8;
a_op=`aluwand;
#10
// aluwadd AND uu AND w32
r_A=128'h000d000d000e000b0006000f000a000d;
r_B=128'h000f00050006000f0009000c000d000b;
e_r=128'h000d00050006000b0000000c00080009;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w16;
a_op=`aluwand;
#10
// aluwadd AND uu AND w32
r_A=128'h00000001000000020000000300000004;
r_B=128'h00000005000000060000000700000008;
e_r=128'h00000001000000020000000100000002;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w32;
a_op=`aluwand;
// ======================================
#10 //TIME=280
// aluwand AND dd AND w8
r_A=128'h090a0b0c0d0f1011010e0b02050b070a;
r_B=128'h040506010405060101060d020d0d080d;
e_r=128'h0d10130d111416120106090205090008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w8;
a_op=`aluwand;
#10
// aluwand AND dd AND w32
r_A=128'h000500060007000800020002000e000d;
r_B=128'h0001000100010003000d000200030005;
e_r=128'h000600070008000b0000000200020005;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w16;
a_op=`aluwand;
#10
// aluwand AND dd AND w32
r_A=128'h00000003000000040000000b0000000e;
r_B=128'h00000007000000080000000f00000003;
e_r=128'h00000001000000020000000b00000002;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwand;
// ======================================
#10 //TIME=310
// aluwand AND oo AND w8
r_A=128'h090a0b0c0d0f1011010e030b05060708;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hff08fe0cfd0dfc11fb02fa09f906f800;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w8;
a_op=`aluwand;
/**
* Stop exhaustive testing of the ALU at
* AND, ppp==oo, and ww=w8
*/
// ======================================
#10 //TIME=320
// aluwnot AND aa AND w8
r_A=128'h090a0b0c0d0f1011010e030b05060708;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hf6f5f4f3f2f0efeefef1fcf4faf9f8f7;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwnot;
#10
// aluwnot AND ee AND w8
r_A=128'h44ff55ff22ff33ff66009900cc00bb00;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hbb00aa00dd00cc0099ff66ff33ff44ff;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w8;
a_op=`aluwnot;
#10
// aluwnot AND mm AND w32
r_A=128'hba98fedc0d0f1011010e030b05060708;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'h45670123f2f0efeefef1fcf4faf9f8f7;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w32;
a_op=`aluwnot;
#10
// aluwnot AND uu AND w16
r_A=128'h0123456789abcdeeffffffffffffffff;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hfedcba98765432110000000000000000;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w16;
a_op=`aluwnot;
// ======================================
#10 //TIME=360
// aluwor AND aa AND w8
r_A=128'h5b4924086211598192408624b5268261;
r_B=128'hac8241a24596a229241a2458ca442446;
e_r=128'hffcb65aa6797fba9b65aa67cff66a667;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwor;
#10
// aluwor AND oo AND w16
r_A=128'hffff0004ffff0000ffff0002ffff000b;
r_B=128'h33330001333300aa333300053333000c;
e_r=128'h44440005444400aa444400074444000f;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwor;
#10
// aluwor AND dd AND w32
r_A=128'h88888888888888880000000500000004;
r_B=128'h33333333333333330000000a00000008;
e_r=128'hcccccccccccccccc0000000f0000000c;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwor;
// ======================================
#10 //TIME=390
// aluwxor AND aa AND w8
r_A=128'h01409d09085ac63511c098c340900a6c;
r_B=128'h6820a4020741489211e6a7492020018e;
e_r=128'h6960390b0f1b8ea700263f8a60b00be2;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwxor;
#10
// aluwxor AND oo AND w16
r_A=128'hffff0009ffff000dffff000cffff0006;
r_B=128'heeee0002eeee0004eeee0004eeee0008;
e_r=128'haaaa000baaaa0009aaaa0008aaaa000e;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwxor;
#10
// aluwxor AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa000000030000000c;
r_B=128'hbbbbbbbbcccccccc0000000900000004;
e_r=128'hddddddddffffffff0000000a00000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwxor;
// ======================================
#10 //TIME=420
// aluwsub AND aa AND w8
r_A=128'h15141312111021222a2212b2a2941827;
r_B=128'h0102030405060708090a010202020516;
e_r=128'h1412100e0c0a1a1a211811b0a0921311;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsub;
#10
// aluwsub AND oo AND w16
r_A=128'hffff000dffff000effff000cffff0006;
r_B=128'heeee0004eeee0008eeee0004eeee0005;
e_r=128'haaaa0009aaaa0006aaaa0008aaaa0001;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsub;
#10
// aluwsub AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa0000000e0000000c;
r_B=128'hbbbbbbbbcccccccc0000000a00000005;
e_r=128'hddddddddffffffff0000000400000007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsub;
#20
/**
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
*/
//PRM TEST COMMANDS - Andrew
// aluwprm PRM aa
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h000102030405060708090a0b0c0d0e0f;
e_r=128'h0123456789abcdef0123456789abcdef;
c_ppp=`aa;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM aa
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23456789abcdef0123456789abcdef01;
c_ppp=`aa;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM uu
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23456789abcdef010000000000000000;
c_ppp=`uu;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM dd
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h000000000000000023456789abcdef01;
c_ppp=`dd;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM ee
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23006700ab00ef0023006700ab00ef00;
c_ppp=`ee;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM oo
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h0045008900cd00010045008900cd0001;
c_ppp=`oo;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM mm
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23000000000000000000000000000000;
c_ppp=`mm;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM ll
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h00000000000000000000000000000001;
c_ppp=`ll;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
/**
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
/**
a=16'd51267;
b=16'd11;
c=a>>b[11:15];
$display ("c ===========", c);
#10
a=16'd60123;
b=16'd5;
c=a>>b[11:15];
$display ("c ===========", c);
**/
//SLLI TEST COMMANDS - Andrew
// aluwslli SLLI aa
r_A=128'h11111111111111111111111111111111;
r_B=128'h00000000000000000000000000000000;//no shift
e_r=128'h11111111111111111111111111111111;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwslli;
#10;
// aluwslli SLLI aa
r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
r_B=128'h08000000000000000000000000000000;//shift 1 (00"001"000)
e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
c_ppp=`aa;
c_ww=`w8; // byte style
a_op=`aluwslli;
#10;
// aluwslli SLLI aa
r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
r_B=128'h08000000000000000000000000000000;//shift 1 (0"0001"000)
e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
c_ppp=`aa;
c_ww=`w16; // 2 byte style
a_op=`aluwslli;
#10;
// aluwslli SLLI aa
r_A=128'h000f000f000f000f000f000f000f000f;
r_B=128'h08000000000000000000000000000000;//shift 1 ("00001"000)
e_r=128'h001e001e001e001e001e001e001e001e;
c_ppp=`aa;
c_ww=`w32; // 2 byte style
a_op=`aluwslli;
#10;
// ======================================
#10 //TIME=420
// aluwsrl AND aa AND w8
r_A=128'h12345678941234567891234567891234;
r_B=128'h04040404040404040404040404040404;
e_r=128'h01030507090103050709020406080103;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsrl;
#10
// aluwsrl AND oo AND w16
r_A=128'hffff1234ffff5678ffff9abcffffdef0;
r_B=128'heeee0004eeee0008eeee0004eeee0008;
e_r=128'haaaa0123aaaa0056aaaa09abaaaa00de;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsrl;
#10
// aluwsrl AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa00001234006789ab;
r_B=128'hbbbbbbbbcccccccc0000000800000010;
e_r=128'hddddddddffffffff0000001200000067;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsrl;
// ======================================
#10 //TIME=420
// aluwsll AND aa AND w8
r_A=128'h12345678941234567891234567891234;
r_B=128'h04040404040404040404040404040404;
e_r=128'h20406080402040608010305070902040;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsll;
#10
// aluwsll AND oo AND w16
r_A=128'hffff1234ffff5678ffff9abcffffdefa;
r_B=128'heeee0004eeee0008eeee0004eeee0008;
e_r=128'haaaa2340aaaa7800aaaaabc0aaaafa00;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsll;
#10
// aluwsll AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa00001234006789ab;
r_B=128'hbbbbbbbbcccccccc0000000800000010;
e_r=128'hddddddddffffffff0012340089ab0000;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsll;
// =======================================
#10 //TIME=420
// aluwsra AND w8
r_A=128'h123456789abcdef89abcdef89abcdef8;
r_B=128'h04040404040404040404040404040404;
//e_r=128'hf1f3f5f7f9f1f3f5f7f9f2f4f6f8f1f3;
e_r=128'hf1f3f5f7f9f1f3f5f7f9f2f4f6f8f1f3;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsra;
#10
// aluwsra AND w16
r_A=128'hffff1234ffff5678ffff9abcffffdefa;
r_B=128'heeee0004eeee0008eeee0004eeee0008;
e_r=128'haaaa2340aaaa7800aaaaabc0aaaafa00;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsra;
#10
// aluwsra AND w32
r_A=128'heeeeeeeeaaaaaaaa00001234006789ab;
r_B=128'hbbbbbbbbcccccccc0000000800000010;
e_r=128'hddddddddffffffff0012340089ab0000;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsra;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_2_V
`define SKY130_FD_SC_HD__DLRBP_2_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_sim_netlist.v
// Design : pikachu_down_pixel
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "pikachu_down_pixel,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module pikachu_down_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [12:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [12:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [12:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "13" *)
(* C_ADDRB_WIDTH = "13" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.681258 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "pikachu_down_pixel.mem" *)
(* C_INIT_FILE_NAME = "pikachu_down_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "5589" *)
(* C_READ_DEPTH_B = "5589" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "5589" *)
(* C_WRITE_DEPTH_B = "5589" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
pikachu_down_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[12:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[12:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module pikachu_down_pixel_blk_mem_gen_generic_cstr
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [8:0]p_7_out;
wire [8:0]ram_douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_mux \has_mux_a.A
(.addra(addra[12:11]),
.clka(clka),
.douta(douta[8:0]),
.p_7_out(p_7_out),
.ram_douta(ram_douta));
pikachu_down_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.ram_douta(ram_douta),
.wea(wea));
pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.p_7_out(p_7_out),
.wea(wea));
pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:9]),
.douta(douta[11:9]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module pikachu_down_pixel_blk_mem_gen_mux
(douta,
addra,
clka,
p_7_out,
ram_douta);
output [8:0]douta;
input [1:0]addra;
input clka;
input [8:0]p_7_out;
input [8:0]ram_douta;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire [8:0]p_7_out;
wire [8:0]ram_douta;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT4 #(
.INIT(16'h2F20))
\douta[0]_INST_0
(.I0(p_7_out[0]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[0]),
.O(douta[0]));
LUT4 #(
.INIT(16'h2F20))
\douta[1]_INST_0
(.I0(p_7_out[1]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[1]),
.O(douta[1]));
LUT4 #(
.INIT(16'h2F20))
\douta[2]_INST_0
(.I0(p_7_out[2]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[2]),
.O(douta[2]));
LUT4 #(
.INIT(16'h2F20))
\douta[3]_INST_0
(.I0(p_7_out[3]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[3]),
.O(douta[3]));
LUT4 #(
.INIT(16'h2F20))
\douta[4]_INST_0
(.I0(p_7_out[4]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[4]),
.O(douta[4]));
LUT4 #(
.INIT(16'h2F20))
\douta[5]_INST_0
(.I0(p_7_out[5]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[5]),
.O(douta[5]));
LUT4 #(
.INIT(16'h2F20))
\douta[6]_INST_0
(.I0(p_7_out[6]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[6]),
.O(douta[6]));
LUT4 #(
.INIT(16'h2F20))
\douta[7]_INST_0
(.I0(p_7_out[7]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[7]),
.O(douta[7]));
LUT4 #(
.INIT(16'h2F20))
\douta[8]_INST_0
(.I0(p_7_out[8]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[8]),
.O(douta[8]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pikachu_down_pixel_blk_mem_gen_prim_width
(ram_douta,
clka,
addra,
dina,
wea);
output [8:0]ram_douta;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]ram_douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.ram_douta(ram_douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0
(p_7_out,
clka,
addra,
dina,
wea);
output [8:0]p_7_out;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]p_7_out;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.p_7_out(p_7_out),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1
(douta,
clka,
addra,
dina,
wea);
output [2:0]douta;
input clka;
input [12:0]addra;
input [2:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [2:0]dina;
wire [2:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init
(ram_douta,
clka,
addra,
dina,
wea);
output [8:0]ram_douta;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]ram_douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
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.INIT_6D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F090000000000000C0F0B0),
.INIT_6E(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0C000C0F0F0F0F0),
.INIT_6F(256'hF0F0F0F0F0E09000000010B0F0F0E0A0100000F0F0F0F0F000C0F0F0F0F0F0F0),
.INIT_70(256'hF0F0F0F0F0F0F0F0D000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_71(256'h00F0F0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_72(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070606080F0F0F0F0F020),
.INIT_73(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E06070B0F0F0F0F0F0),
.INIT_74(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0C01000F0F0F0F0F0F000C0F0F0F0F0F0F0F0F0),
.INIT_75(256'hF0F0F0F0F0F0F0F03080F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_76(256'hF0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_77(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B000F0F0F0),
.INIT_78(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_79(256'hF0F0F0F0F0F0F0F0F0902000F0F0F0F0F0F0F0F000C0F0F0F0F0F0F0F0F0F0F0),
.INIT_7A(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_7B(256'hF0F00000C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_7C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0904000F0F0F0F0F0F0),
.INIT_7D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_7E(256'hF0F0F0F0F0F02000F0F0F0F0F0F0F0F0F0F00060B0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_7F(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],ram_douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],ram_douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT1 #(
.INIT(2'h1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[12]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0
(p_7_out,
clka,
addra,
dina,
wea);
output [8:0]p_7_out;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]p_7_out;
wire [0:0]wea;
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'hFFFFFFFFFFFE80005FFFFFFFFFFFFFFF88003FFFFFFFFFFFFFFFF8001FFFFFFF),
.INITP_01(256'hFFFFFFFFF0FFFF8000013FFFFFFFFCFFFFE00000FFFFFFFFFBFFFFF800003FFF),
.INITP_02(256'h00001FFFFFFFFFBFE84000006FFFFFFFFF1FFD000000BFFFFFFFE1FFFE800001),
.INITP_03(256'h020000000FFFFF03FF4F3F0000001FFFFFFFFEA7FF8000001FFFFFFFFF0F8F80),
.INITP_04(256'h20E200000000001FFF902FF80000000001FFFFF81FE00000000008FFFF040FE0),
.INITP_05(256'h0000000000000000000000000000000000000000000001E40000000000100000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hF0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_01(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F02000F0F0F0F0F0F0F0F0F0),
.INIT_02(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_03(256'hF0A0202010F0F0F0F0F0F0F0F0F0F0F0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_04(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_05(256'hF01040F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_06(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F080300000F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_07(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_08(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00020F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_09(256'hF0F0F0F0F0C0B0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A02000),
.INIT_0A(256'h30F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0B(256'hF0F0F0F0F0F0F0F0F0F0F0C00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000),
.INIT_0C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F05030E0E0F0F0F0F0F0F0F0F0),
.INIT_0D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F00030E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0E(256'hF0F0F0F0A00000A0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A000F0F0F0F0F0),
.INIT_0F(256'h1090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_10(256'hF0F0F0F0F0F0F0801000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010),
.INIT_11(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0A0A0603050F0F0F0F0F0F0F0),
.INIT_12(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F000003080F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_13(256'hF0F0F0F0F09050508080C0F0F0F0F0F0F0F0F0F0F09060300000F0F0F0F0F0F0),
.INIT_14(256'h209090E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_15(256'hF0F0F0C010C0C0202010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000),
.INIT_16(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0101060D0D0F0F0F0F0),
.INIT_17(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F000000080D0D0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_18(256'hF0F0F0F0F0F0F0F0800000C0F0F0F0F0F0A000E0F0F0F0F03000F0F0F0F0F0F0),
.INIT_19(256'hF0000010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1A(256'h50D0F0F0F0F0F0D07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E09000102060F0F070),
.INIT_1C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000303090F0F0F0F0F0F0F0F0F0F0),
.INIT_1D(256'hF0F0F0F0F0F0F0F08070200070701010808070B0F0F0F09000F0F0F0F0F0F0F0),
.INIT_1E(256'hF0F000003090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080606060606090F0),
.INIT_1F(256'h000040C0C0C07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_20(256'hF0F0F0F0F0F0F050202020202050C0C0C0C0C0C0F0F0F0F0F090302000000000),
.INIT_21(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010C0C0C0D0F0F0F0F0F0F0F0),
.INIT_22(256'h000000B0F0F0F0F0F0F0F0200000F0F0F00000000000F0F0F0F0F0F0F0F0F0F0),
.INIT_23(256'hF0F0F0F000000030F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B0000000),
.INIT_24(256'hF0F0F00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_25(256'hF0F0F0F0F0F0F0F0F04020100000000000001080F0F0F0F0F0F0D0D090000000),
.INIT_26(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000002020202030F0F0F0F0),
.INIT_27(256'h0000306060606080F0F0F0C0000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_28(256'hF0F0F0F0F0F0000000000050606060606060606060606060000000F0F0F000F0),
.INIT_29(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2A(256'h00000000000000F00000F0F0F0F0F0F0F0000000000020B0B0B070000000F0F0),
.INIT_2B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000000000),
.INIT_2C(256'hF0F0F0F0F0000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2E(256'h0000000000000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra[10:0],1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],p_7_out[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],p_7_out[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1
(.I0(addra[12]),
.I1(addra[11]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1
(douta,
clka,
addra,
dina,
wea);
output [2:0]douta;
input clka;
input [12:0]addra;
input [2:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49 ;
wire [12:0]addra;
wire clka;
wire [2:0]dina;
wire [2:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2222222222222222222222222222222222200000222222222222222222222222),
.INIT_01(256'h2222222222222200004555102222222222222222222222222222222222222222),
.INIT_02(256'h3777510222222222222222222222222222222222222222222222222222222222),
.INIT_03(256'h2222222222222222222222222222222222222222222222222222222222220233),
.INIT_04(256'h2222222222222222222222222222222222222222220157777750222222222222),
.INIT_05(256'h2222222222222222222222220067777740222222222222222222222222222222),
.INIT_06(256'h2222222007777774022222222222222222222222222222222222222222222222),
.INIT_07(256'h2222222222222222222222222222222222222222222222222222222222222222),
.INIT_08(256'h2222222222222222222222222222222222222222222222222222201477777520),
.INIT_09(256'h2222222222222222222222222022222222001377777710222222222222222222),
.INIT_0A(256'h2222222002222222000477777772022222222222222222222222222222222222),
.INIT_0B(256'h6677777771022222222222222222222222222222222222222222222222222222),
.INIT_0C(256'h2222222222222222222222222222222222222222222222222222202600222201),
.INIT_0D(256'h2222222222222222222222222222222222203674100002577777776302222222),
.INIT_0E(256'h2222222222222222220577742222577777777502222222222222222222222222),
.INIT_0F(256'h2057777777777777777740222222222222222222222222222222222222222222),
.INIT_10(256'h7730222222222222222222222222222222222222222222222222222222222222),
.INIT_11(256'h2222222222222222222222222222222222222222222222006777777777777777),
.INIT_12(256'h2222222222222222222222222222000777777777777777777202222222222222),
.INIT_13(256'h2222222222000267777777777777777520222222222222222222222222222222),
.INIT_14(256'h7766666677776600222222222222222222222222222222222222222222222222),
.INIT_15(256'h2222222222222222222222222222222222222222222222222222222220015577),
.INIT_16(256'h2222222222222222222222222222222222222220025577770000000177300222),
.INIT_17(256'h2222222222222222222222034556321000055541100000222222222222222222),
.INIT_18(256'h2200004555400000147777333333100022222000000000022222222222222222),
.INIT_19(256'h6677777777731111000011111111110022222222222222222222222222222222),
.INIT_1A(256'h0004777777774000222222222222222222222222222222222000045542200013),
.INIT_1B(256'h0222222222222222222222222222222001444542220006400677777777777720),
.INIT_1C(256'h2222222222222203455100222200676614777777775000266677777777776610),
.INIT_1D(256'h4200020000015775347776222344467777777777777775430222222222222222),
.INIT_1E(256'h0555411147777777777777777777777202222222222222222222222222200245),
.INIT_1F(256'h7777777777777771022222222222222222222222200255420000000002135562),
.INIT_20(256'h0222222222222222222222220254520022000001774000000002777777777777),
.INIT_21(256'h0022222015510022222002777777777777777777777777777777777777777773),
.INIT_22(256'h0000037777777777777777777777777777777762267777302222222222222000),
.INIT_23(256'h7777777777777777777774024677752022222222220055554002202441000000),
.INIT_24(256'h7777407237777602222222220247777700201442211111002111147777777777),
.INIT_25(256'h2222222037777770000442176555512755540477777777777777777777777777),
.INIT_26(256'h0000377764444577544403777777777777777777777777777774006417775022),
.INIT_27(256'h4455327777777777777777777777777777400111777750002222200000002700),
.INIT_28(256'h7777777777777777763000177777432022220455555415555556777644445776),
.INIT_29(256'h7710017777777502220377777763777777777764444577544475247777777777),
.INIT_2A(256'h0277777777777777777776544567765447760677777777777777777777777777),
.INIT_2B(256'h7777774467777644776067777777777777777777777777777710177777775022),
.INIT_2C(256'h7606777777777777777777777777777776667777777502037777777777777777),
.INIT_2D(256'h7777777777777777777777777750047777777777777777777777744677776447),
.INIT_2E(256'h7777777775005777777777777777777777776467777766753477777777777777),
.INIT_2F(256'h6777777777777777777756777777773077777777777777777777777777777777),
.INIT_30(256'h7775677777777407777777777777777777777777777777777777777750057776),
.INIT_31(256'h7777777777777777777777777777777777777775005777137777777777777777),
.INIT_32(256'h7777777777777777777775202000057777777777777777777777777777774077),
.INIT_33(256'h7775102200006777777777777777777777777777777407777777777777777777),
.INIT_34(256'h7777777777777777777777777730777777777777777777777777777777777777),
.INIT_35(256'h7777777774177777777777777777777777777777777777777600022222067777),
.INIT_36(256'h7777777777777777777777777777777500002222206777777777777777777777),
.INIT_37(256'h7777777777777775000222220677777777777777777777777777777776067777),
.INIT_38(256'h0222222067777777777777777777777777777777606777777777777777777777),
.INIT_39(256'h7777777777777777777777773357777777777777777777777777777777777771),
.INIT_3A(256'h7777777714777777777777777777777777777777777776002222220677777777),
.INIT_3B(256'h7777777777777777777777777775022222222067777777777777777777777777),
.INIT_3C(256'h7777777774102222222206777777777777777777777777777777777777777777),
.INIT_3D(256'h2200677777777777777777777777777777777777777777777777777777777777),
.INIT_3E(256'h7777777777777777777777777777777777777777777777777777777420222222),
.INIT_3F(256'h7777777777777777777777777777777777777710222222222203577777777777),
.INIT_40(256'h7777777777777777777771022222222222037777777777777777777777777777),
.INIT_41(256'h7511022222222222203777777777777777777777777777777777777777777777),
.INIT_42(256'h2027777777777777777777777777777777777777777777777777777777777777),
.INIT_43(256'h7777777777777777777777777777777777777777777777741002222222222222),
.INIT_44(256'h7777765777777777777777777777751022222222222222220177777777777777),
.INIT_45(256'h7777777777760022222222222222222017777777777777777777777777777777),
.INIT_46(256'h2222222222222201777777777777777777777777777777777777217777777777),
.INIT_47(256'h0477777777777777777777777777777777775005777777777777777775022222),
.INIT_48(256'h7777777777777777777755312777777777777774002222222222222222222200),
.INIT_49(256'h7777742244677777777774310022222222222222222222001477777777777777),
.INIT_4A(256'h7776066110222222222222222222222014477777777777777777777777777777),
.INIT_4B(256'h2222222222222220004667777777777777777777777777777777777003667777),
.INIT_4C(256'h2000777777777777777777777777777777777777400677777507777710222222),
.INIT_4D(256'h7777777777777777777777774001377326777776302222222222222222222222),
.INIT_4E(256'h7777777743103300443577740222222222222222222222222001147777777777),
.INIT_4F(256'h0026663022222222222222222222222222001477777777777777777743333347),
.INIT_50(256'h2222222222222222222006666777777777777772111112666666777774110000),
.INIT_51(256'h2222000177777777777777777777500000057777777100222000002222222222),
.INIT_52(256'h7777777772100000000477777766400022200222222222222222222222222222),
.INIT_53(256'h0013333477760002222222222222222222222222222222222220000111117777),
.INIT_54(256'h2222222222222222222222222222222222222200000233333333333300022202),
.INIT_55(256'h2222222222222222222222222200000000000002112222222000001555300022),
.INIT_56(256'h2222222222222222222222222222222222222000000222222222222222222222),
.INIT_57(256'h0000000000000000000000000000000000000000000222222222222222222222),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:4],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49 ,douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module pikachu_down_pixel_blk_mem_gen_top
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "13" *) (* C_ADDRB_WIDTH = "13" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.681258 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "pikachu_down_pixel.mem" *)
(* C_INIT_FILE_NAME = "pikachu_down_pixel.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "5589" *) (* C_READ_DEPTH_B = "5589" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "5589" *) (* C_WRITE_DEPTH_B = "5589" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module pikachu_down_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [12:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [12:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [12:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [12:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
pikachu_down_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module pikachu_down_pixel_blk_mem_gen_v8_3_5_synth
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 05:22:50 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/sidxb/FPGA/ee2020/ee2020.runs/dds_compiler_0_synth_1/dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module dds_compiler_0(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
/*
* CameraOneFrame architecture
*
* Copyright (c) 2014,
* Luca Maggiani <[email protected]>,
* Scuola Superiore Sant'Anna (http://www.sssup.it) and
* Consorzio Nazionale Interuniversitario per le Telecomunicazioni
* (http://www.cnit.it).
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* gradient module
* Created by LMag 2013
*
* Spatial gradient extraction (on 8-derivatives)
* It uses 8 matrix with sin and cos values, normalized by 256 (N = 8)
*
* 14Feb13 v1.0 - first release
* 24Apr13 v1.1 - major revision, inserted into Camera_OneFrame v3.0 Architecture
* Now it has an Avalon-MM interface and
* 8Mag13 v2.0 - configurable resolution!from 64 to 320 pixel (at the moment)
* 13Dic13 v2.1 - image shift resolved, new FSM, modified registers addr_rel_i
* new registers for extended flexibility
*
* 5Jan15 v4.0 - major revision, flowvalid input and output added.
* Removed internal counter
* 4Feb15 v4.0 - token passing machine added!
* teastbench with image. Flow valid generation validated.
*
* TO DO:
* - generic kernel instatiations (realtointeger problem!!!)
*
*/
module gradient(
//input
clk_proc,
reset_n,
in_fv,
in_dv,
in_data,
//output
magnitude_fv,
magnitude_dv,
magnitude_data,
angle_fv,
angle_dv,
angle_data,
//Avalon-MM inputs
addr_rel_i,
wr_i,
datawr_i,
rd_i,
//Avalon-MM outputs
datard_o
);
/* Flows size */
parameter IN_SIZE = 8;
parameter MAGNITUDE_SIZE = 16;
parameter ANGLE_SIZE = 16;
/* Clock param */
parameter CLK_PROC_FREQ = 50000000;
/* Generic parameters */
parameter COEF_WIDTH = 9;
parameter NORM_FACTOR = 8;
parameter DEFAULT_SCR = 32'd41;
parameter DEFAULT_TH = 32'd50;
/* Internal parameters */
localparam TOKEN_SIZE = 9;
localparam N_KERNEL = 8;
input clk_proc;
input reset_n;
input in_fv;
input in_dv;
input addr_rel_i;
input [31:0] datawr_i;
input wr_i;
input rd_i;
input [IN_SIZE-1:0] in_data;
output [31:0] datard_o;
output [MAGNITUDE_SIZE-1:0] magnitude_data; //TODO: generic output flow width
output [ANGLE_SIZE-1:0] angle_data; //TODO: generic output flow width
output magnitude_fv;
output magnitude_dv;
output angle_fv;
output angle_dv;
/* Avalon-MM registers */
reg [31:0] datard_o, readdata_new;
reg [31:0] config_setup, config_setup_new;
reg [31:0] threshold, threshold_new;
/* Register definitions */
reg [(IN_SIZE-1):0] row1[2:0], row2[2:0], row3[2:0];
reg [TOKEN_SIZE-1:0] token_d;
reg [((COEF_WIDTH + IN_SIZE)+1):0] q1, q2, q3, q4, s1, s2, m_max;
reg [$clog2(N_KERNEL)-1:0] q1_dir, q2_dir, q3_dir, q4_dir, s1_dir, s2_dir, d_max;
reg [(COEF_WIDTH + IN_SIZE - NORM_FACTOR):0] data_d;
reg [$clog2(N_KERNEL)-1:0] dir_d;
/* Wire definitions */
wire [(IN_SIZE-1):0] row2_wire, row3_wire;
wire onoff_bit;
wire binarize_bit;
wire dv_s;
wire [((COEF_WIDTH + IN_SIZE)+1):0] matrix_out [N_KERNEL-1:0];
wire [TOKEN_SIZE-1:0] token_s;
wire signed [(COEF_WIDTH-1):0] sin_coef [N_KERNEL-1:0];
wire signed [(COEF_WIDTH-1):0] cos_coef [N_KERNEL-1:0];
/* Variable definitions */
integer i, j;
/* Parameters check */
generate
always@(*)
begin
if (MAGNITUDE_SIZE != 16)
$error("gradient.v: MAGNITUDE_SIZE different from 16 not supported yet!!!");
if (ANGLE_SIZE != 16)
$error("gradient.v: ANGLE_SIZE different from 16 not supported yet!!!");
if (IN_SIZE != 8)
$error("gradient.v: IN_SIZE different from 8 not supported yet!!!");
end
endgenerate
/* Internal signal alias */
assign onoff_bit = config_setup[0];
assign binarize_bit = config_setup[1];
/* Internal gathed data valid signal */
assign dv_s = in_dv & onoff_bit;
/* Token passing machine */
always@(posedge clk_proc or negedge reset_n)
begin
if (reset_n == 0)
token_d <= 0;
else
if (dv_s | ~in_fv)
begin
token_d[0] <= in_fv;
for(j=0; j<(TOKEN_SIZE-1); j=j+1)
token_d[j+1] <= token_d[j];
end
else
token_d <= token_d;
end
/* Token gathing for pipeline halt */
assign token_s = (dv_s | ~in_fv) ? token_d : 1'b0;
/* Line buffers (2 lines + 3x3 pixel matrix) */
always@(posedge clk_proc or negedge reset_n)
begin
if (reset_n == 0)
for(i=0; i<3;i=i+1)
begin
row1[i] <= {IN_SIZE{1'b0}};
row2[i] <= {IN_SIZE{1'b0}};
row3[i] <= {IN_SIZE{1'b0}};
end
else
if (token_s[0])
begin
for(i=1; i<3;i=i+1)
begin
row1[i] <= row1[i-1];
row2[i] <= row2[i-1];
row3[i] <= row3[i-1];
end
row1[0] <= in_data;
row2[0] <= row2_wire;
row3[0] <= row3_wire;
end
end
/* Enhanced shift register (configurable output shift position) */
eshift_reg eshift_reg_inst0(
.clk(clk_proc),
.clken(token_s[0]),
.shiftin(row1[2]),
.shiftout(row2_wire),
.taps(),
.aclr(),
.res_config(config_setup[10:3])
);
eshift_reg eshift_reg_inst1(
.clk(clk_proc),
.clken(token_s[0]),
.shiftin(row2[2]),
.shiftout(row3_wire),
.taps(),
.aclr(),
.res_config(config_setup[10:3])
);
/* Temporary sin and cos coefficient preload
* Smarter solution to be found! (realtointeger not synthesizable!)
*/
assign sin_coef[0] = 0;
assign sin_coef[1] = 97;
assign sin_coef[2] = 181;
assign sin_coef[3] = 236;
assign sin_coef[4] = 255;
assign sin_coef[5] = 236;
assign sin_coef[6] = 181;
assign sin_coef[7] = 97;
assign cos_coef[0] = 255;
assign cos_coef[1] = 236;
assign cos_coef[2] = 181;
assign cos_coef[3] = 97;
assign cos_coef[4] = 0;
assign cos_coef[5] = -97;
assign cos_coef[6] = -181;
assign cos_coef[7] = -236;
/* Generic Kernel loop instantiation - N_KERNEL
* NOTE: output data signal is already converted to unsigned!
*/
genvar index;
generate
for (index=0; index < N_KERNEL; index = index + 1)
begin: matrix_prod_gen
matrix_prod #(
.DATA_WIDTH(IN_SIZE),
.COEF_WIDTH(COEF_WIDTH)
) matrix_prod_inst(
.clk_i(clk_proc),
.reset_n_i(reset_n),
.dv0_i(token_s[1]),
.dv1_i(token_s[2]),
.dv2_i(token_s[3]),
.sclr_i(1'b0),
.pix01_i(row1[1]), //pix01_i
.pix10_i(row2[0]), //pix10_i
.pix12_i(row2[2]), //pix12_i
.pix21_i(row3[1]), //pix21_i
.sin_i(sin_coef[index]),
.cos_i(cos_coef[index]),
.data_o(matrix_out[index])
);
end
endgenerate
/* ###############################
* Pipelined ArgMax extractor
* ###############################*/
/* Quarter*/
always@(posedge clk_proc)
if(token_s[4])
begin
if (matrix_out[0] > matrix_out[1])
begin
q1 <= matrix_out[0];
q1_dir <= 0;
end
else
begin
q1 <= matrix_out[1];
q1_dir <= 1;
end
end
always@(posedge clk_proc)
if(token_s[4])
begin
if (matrix_out[2] > matrix_out[3])
begin
q2 <= matrix_out[2];
q2_dir<= 2;
end
else
begin
q2 <= matrix_out[3];
q2_dir <= 3;
end
end
always@(posedge clk_proc)
if(token_s[4])
begin
if (matrix_out[4] > matrix_out[5])
begin
q3 <= matrix_out[4];
q3_dir<= 4;
end
else
begin
q3 <= matrix_out[5];
q3_dir <= 5;
end
end
always@(posedge clk_proc)
if(token_s[4])
begin
if (matrix_out[6] > matrix_out[7])
begin
q4 <= matrix_out[6];
q4_dir<= 6;
end
else
begin
q4 <= matrix_out[7];
q4_dir <= 7;
end
end
/* Semi*/
always@(posedge clk_proc)
if (token_s[5])
begin
if (q1 > q2)
begin
s1 <= q1;
s1_dir<= q1_dir;
end
else
begin
s1 <= q2;
s1_dir <= q2_dir;
end
end
always@(posedge clk_proc)
if (token_s[5])
begin
if (q3 > q4)
begin
s2 <= q3;
s2_dir <= q3_dir;
end
else
begin
s2 <= q4;
s2_dir <= q4_dir;
end
end
/* Final */
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
begin
m_max <= 0;
d_max <= 0;
end
else
begin
if (token_s[6])
begin
if (s1 > s2)
begin
m_max <= s1;
d_max <= s1_dir;
end
else
begin
m_max <= s2;
d_max <= s2_dir;
end
end
end
/* Output module */
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
data_d <= 0;
else
begin
dir_d <= d_max;
if (token_s[7])
if (m_max[((COEF_WIDTH + IN_SIZE)+1):0] > threshold[((COEF_WIDTH + IN_SIZE)+1):0])
if(binarize_bit)
data_d <= {(COEF_WIDTH + IN_SIZE - NORM_FACTOR){1'b1}};
else
data_d <= m_max[(COEF_WIDTH + IN_SIZE):NORM_FACTOR-1];
else
if(binarize_bit)
data_d <= {(COEF_WIDTH + IN_SIZE - NORM_FACTOR){1'b0}};
else
data_d <= {(COEF_WIDTH + IN_SIZE - NORM_FACTOR){1'b0}};
end
assign magnitude_data = data_d;
assign angle_data = dir_d;
assign magnitude_dv = token_s[8];
assign angle_dv = token_s[8];
assign magnitude_fv = (token_d[8]) ? 1'b1 : 1'b0;
assign angle_fv = (token_d[8]) ? 1'b1 : 1'b0;
/* ######### Avalon-MM Slave Interface ##############
CONFIG_SETUP - R/W
THRESHOLD - R/W
*/
/* Write operation */
always @ (*)
if (wr_i)
case(addr_rel_i)
1'd0:
begin
config_setup_new = datawr_i;
threshold_new = threshold;
end
1'd1:
begin
config_setup_new = config_setup;
threshold_new = datawr_i;
end
default:
begin
config_setup_new = config_setup;
threshold_new = threshold;
end
endcase
else /* wr_i does not enabled */
begin
config_setup_new = config_setup;
threshold_new = threshold;
end
/* Read operation */
always @ (*)
if (rd_i)
case(addr_rel_i)
1'd0: readdata_new = config_setup;
1'd1: readdata_new = threshold;
default:
readdata_new = datard_o;
endcase
else
readdata_new = datard_o;
/* Internal register */
always @ (posedge clk_proc or negedge reset_n)
if (reset_n == 1'b0)
begin
config_setup <= DEFAULT_SCR;
threshold <= DEFAULT_TH;
datard_o <= 32'b0;
end
else
begin
config_setup <= config_setup_new;
threshold <= threshold_new;
datard_o <= readdata_new;
end
/* ##################################### */
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_ddr2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_ddr2(ddr2_dll_bypass_l ,ddr2_bypass_data ,clk_ddr2_cken ,
spare_ddr2_pin ,bscan_mode_ctl_in ,spare_ddr2_pad ,bscan_hiz_l_in ,
ddr_si ,tck ,pad_ddr2_sscan_out ,dram2_io_bank ,dram2_dq ,dram2_cb
,dram2_ba ,dram2_cas_l ,dram2_ras_l ,dram2_cke ,pad_ddr2_sscan_in
,ddr_testmode_l ,ctu_ddr2_dll_delayctr ,dram2_io_cs_l ,afo ,
bypass_enable ,bypass_enable_out ,bscan_shift_dr_out ,
bscan_clock_dr_out ,bscan_hiz_l_out ,ps_select_out ,
bscan_update_dr_out ,serial_out ,afi ,vdd18 ,ddr2_ctu_dll_overflow
,bscan_mode_ctl_out ,pad_ddr2_bsi ,dram_arst_l ,dram_grst_l ,
dram_gclk ,dram2_ck_p ,ctu_global_snap ,dram_gdbginit_l ,
ctu_ddr2_iodll_rst_l ,test_mode ,bscan_clock_dr_in ,serial_in ,
dram2_io_ptr_clk_inv ,ctu_io_sscan_update ,ctu_io_sscan_se ,
spare_ddr2_paddata ,dram23_p_ref_res ,ddr2_ddr3_cbd ,ddr_so ,
ps_select ,dram23_n_ref_res ,dram2_dqs ,pad_ddr2_bso ,ddr_se ,
dram2_addr ,dram2_we_l ,dram2_ck_n ,dram_adbginit_l
,ddr2_ddr3_cbu ,bscan_shift_dr_in ,ddr2_ctu_dll_lock ,
dram2_io_pad_enable ,bscan_update_dr_in ,dram2_io_drive_enable ,
dram2_io_write_en_l ,dram2_io_cas_l ,dram2_io_ras_l ,
dram2_io_clk_enable ,io_dram2_data_valid ,dram2_io_addr ,
io_dram2_data_in ,dram2_io_channel_disabled ,io_dram2_ecc_in ,
dram2_io_drive_data ,dram2_io_data_out ,dram2_io_cke ,
dram2_io_pad_clk_inv ,dram2_cs_l ,spare_ddr2_pindata, ddr2_lpf_code );
output [4:0] ddr2_lpf_code ;
output [2:0] dram2_ba ;
output [143:0] serial_out ;
output [143:0] afi ;
output [3:0] dram2_ck_p ;
output [8:1] ddr2_ddr3_cbd ;
output [14:0] dram2_addr ;
output [3:0] dram2_ck_n ;
output [8:1] ddr2_ddr3_cbu ;
output [255:0] io_dram2_data_in ;
output [31:0] io_dram2_ecc_in ;
output [3:0] dram2_cs_l ;
input [4:0] ddr2_bypass_data ;
input [2:0] dram2_io_bank ;
input [2:0] ctu_ddr2_dll_delayctr ;
input [3:0] dram2_io_cs_l ;
input [143:0] afo ;
input [1:0] dram_gclk ;
input [143:0] serial_in ;
input [4:0] dram2_io_ptr_clk_inv ;
input [6:0] spare_ddr2_paddata ;
input [14:0] dram2_io_addr ;
input [287:0] dram2_io_data_out ;
input [2:0] spare_ddr2_pindata ;
inout [2:0] spare_ddr2_pin ;
inout [6:0] spare_ddr2_pad ;
inout [127:0] dram2_dq ;
inout [15:0] dram2_cb ;
inout [35:0] dram2_dqs ;
output pad_ddr2_sscan_out ;
output dram2_cas_l ;
output dram2_ras_l ;
output dram2_cke ;
output bypass_enable_out ;
output bscan_shift_dr_out ;
output bscan_clock_dr_out ;
output bscan_hiz_l_out ;
output ps_select_out ;
output bscan_update_dr_out ;
output ddr2_ctu_dll_overflow ;
output bscan_mode_ctl_out ;
output ddr_so ;
output pad_ddr2_bso ;
output dram2_we_l ;
output ddr2_ctu_dll_lock ;
output io_dram2_data_valid ;
input ddr2_dll_bypass_l ;
input clk_ddr2_cken ;
input bscan_mode_ctl_in ;
input bscan_hiz_l_in ;
input ddr_si ;
input tck ;
input pad_ddr2_sscan_in ;
input ddr_testmode_l ;
input bypass_enable ;
input vdd18 ;
input pad_ddr2_bsi ;
input dram_arst_l ;
input dram_grst_l ;
input ctu_global_snap ;
input dram_gdbginit_l ;
input ctu_ddr2_iodll_rst_l ;
input test_mode ;
input bscan_clock_dr_in ;
input ctu_io_sscan_update ;
input ctu_io_sscan_se ;
input dram23_p_ref_res ;
input ps_select ;
input dram23_n_ref_res ;
input ddr_se ;
input dram_adbginit_l ;
input bscan_shift_dr_in ;
input dram2_io_pad_enable ;
input bscan_update_dr_in ;
input dram2_io_drive_enable ;
input dram2_io_write_en_l ;
input dram2_io_cas_l ;
input dram2_io_ras_l ;
input dram2_io_clk_enable ;
input dram2_io_channel_disabled ;
input dram2_io_drive_data ;
input dram2_io_cke ;
input dram2_io_pad_clk_inv ;
supply1 vdd ;
supply0 vss ;
wire [7:0] net227 ;
wire [7:0] net246 ;
wire net0204 ;
wire net196 ;
wire rst_l ;
wire sscan0 ;
wire net228 ;
wire scan0 ;
wire scan1 ;
wire scan2 ;
wire scan3 ;
wire clk_ddr2_cken_buf ;
wire net247 ;
wire ddr_se_buf ;
wire rclk ;
wire arst2_l ;
bw_io_ddr_impctl_pulldown ddr2_impctl_pulldown (
.z ({ddr2_ddr3_cbd } ),
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.to_csr ({net246[0] ,net246[1] ,net246[2] ,net246[3] ,
net246[4] ,net246[5] ,net246[6] ,net246[7] } ),
.tclk (tck ),
.ctu_global_snap (ctu_global_snap ),
.ctu_io_sscan_in (sscan0 ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.ctu_io_sscan_out (pad_ddr2_sscan_out ),
.rclk (rclk ),
.deltabit (net247 ),
.hard_reset_n (rst_l ),
.clk_dis_l (clk_ddr2_cken_buf ),
.we_csr (vss ),
.si (scan1 ),
.se (ddr_se_buf ),
.vdd18 (vdd18 ),
.pad (dram23_n_ref_res ),
.so (scan2 ) );
bw_io_ddr_impctl_pullup ddr2_impctl_pullup (
.z ({ddr2_ddr3_cbu } ),
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.to_csr ({net227[0] ,net227[1] ,net227[2] ,net227[3] ,
net227[4] ,net227[5] ,net227[6] ,net227[7] } ),
.rclk (rclk ),
.so (scan1 ),
.deltabit (net228 ),
.hard_reset_n (rst_l ),
.clk_dis_l (clk_ddr2_cken_buf ),
.we_csr (vss ),
.si (scan0 ),
.se (ddr_se_buf ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.vdd18 (vdd18 ),
.ctu_io_sscan_in (pad_ddr2_sscan_in ),
.ctu_io_sscan_out (sscan0 ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.pad (dram23_p_ref_res ),
.ctu_global_snap (ctu_global_snap ),
.tclk (tck ) );
// ECO 7016: added instance ddr2_iodll_code_adjust 10/11/04
// ECO 7016: Changed so, lpf_out connections on ddr2_master_dll
wire [4:0] ddr2_lpf_code_pre;
wire scan3_pre;
bw_iodll_code_adjust ddr2_iodll_code_adjust (
.bypass_data (ddr2_bypass_data[4:0]),
.ddr_clk_in (rclk),
.delay_ctrl (ctu_ddr2_dll_delayctr[2:0]),
.io_dll_bypass_l (ddr2_dll_bypass_l),
.iodll_reset_l (ctu_ddr2_iodll_rst_l),
.s_controller_out (ddr2_lpf_code_pre[4:0]),
.s_percent_ctrl_out (ddr2_lpf_code[4:0]),
.se (ddr_se_buf),
.si (scan3_pre),
.so (scan3));
bw_iodll ddr2_master_dll (
.ddr_testmode_l (ddr_testmode_l ),
.bypass_data ({ddr2_bypass_data } ),
.lpf_out (ddr2_lpf_code_pre ),
.delay_ctrl ({ctu_ddr2_dll_delayctr } ),
.so (scan3_pre ),
.io_dll_bypass_l (ddr2_dll_bypass_l ),
.io_dll_reset_l (ctu_ddr2_iodll_rst_l ),
.se (ddr_se_buf ),
.si (scan2 ),
.ddr_clk_in (rclk ),
.iodll_lock (ddr2_ctu_dll_lock ),
.overflow (ddr2_ctu_dll_overflow ),
.strobe (net0204 ) );
// End ECO 7016
bw_clk_cl_ddr_ddr pad_ddr2_header (
.gclk ({dram_gclk } ),
.ddr_rclk (rclk ),
.so (ddr_so_pre_latch ),
.si (scan3 ),
.gdbginit_l (dram_gdbginit_l ),
.grst_l (dram_grst_l ),
.cluster_grst_l (rst_l ),
.dbginit_l (net196 ),
.rclk (rclk ),
.se (ddr_se_buf ),
.adbginit_l (dram_adbginit_l ),
.arst2_l (arst2_l ),
.arst_l (dram_arst_l ),
.cluster_cken (clk_ddr2_cken_buf ) );
bw_u1_buf_40x I223 (
.z (ddr_se_buf ),
.a (ddr_se ) );
ddr_ch ddr2_ddr_ch (
.arst_l_out (arst2_l ),
.afo ({afo } ),
.serial_in ({serial_in } ),
.afi ({afi } ),
.serial_out ({serial_out } ),
.dram_io_data_out ({dram2_io_data_out } ),
.spare_ddr_pin ({spare_ddr2_pin[2] ,spare_ddr2_pad[6:0] ,
spare_ddr2_pin[1:0] } ),
.spare_ddr_data ({spare_ddr2_pindata[2] ,spare_ddr2_paddata[6:0] ,
spare_ddr2_pindata[1:0] } ),
.dram_io_ptr_clk_inv ({dram2_io_ptr_clk_inv } ),
.io_dram_data_in ({io_dram2_data_in } ),
.io_dram_ecc_in ({io_dram2_ecc_in } ),
.dram_io_addr ({dram2_io_addr } ),
.dram_io_bank ({dram2_io_bank } ),
.dram_io_cs_l ({dram2_io_cs_l } ),
.dram_dq ({dram2_dq } ),
.dram_addr ({dram2_addr } ),
.dram_cb ({dram2_cb } ),
.dram_dqs ({dram2_dqs } ),
.dram_ba ({dram2_ba } ),
.dram_ck_n ({dram2_ck_n } ),
.dram_ck_p ({dram2_ck_p } ),
.dram_cs_l ({dram2_cs_l } ),
.lpf_code (ddr2_lpf_code ),
.cbu ({ddr2_ddr3_cbu } ),
.cbd ({ddr2_ddr3_cbd } ),
.update_dr_in (bscan_update_dr_in ),
.mode_ctrl_in (bscan_mode_ctl_in ),
.shift_dr_in (bscan_shift_dr_in ),
.clock_dr_in (bscan_clock_dr_in ),
.hiz_n_in (bscan_hiz_l_in ),
.testmode_l (ddr_testmode_l ),
.test_mode (test_mode ),
.bypass_enable_out (bypass_enable_out ),
.ps_select_out (ps_select_out ),
.rclk (rclk ),
.se (ddr_se_buf ),
.pad_clk_so (scan0 ),
.pad_clk_si (ddr_si ),
.bso (pad_ddr2_bso ),
.bsi (pad_ddr2_bsi ),
.mode_ctrl_out (bscan_mode_ctl_out ),
.update_dr_out (bscan_update_dr_out ),
.shift_dr_out (bscan_shift_dr_out ),
.clock_dr_out (bscan_clock_dr_out ),
.hiz_n_out (bscan_hiz_l_out ),
.bypass_enable_in (bypass_enable ),
.ps_select_in (ps_select ),
.strobe (net0204 ),
.dram_io_clk_enable (dram2_io_clk_enable ),
.dram_io_cke (dram2_io_cke ),
.dram_io_ras_l (dram2_io_ras_l ),
.dram_io_write_en_l (dram2_io_write_en_l ),
.dram_io_cas_l (dram2_io_cas_l ),
.dram_cke (dram2_cke ),
.io_dram_data_valid (io_dram2_data_valid ),
.dram_ras_l (dram2_ras_l ),
.dram_we_l (dram2_we_l ),
.dram_cas_l (dram2_cas_l ),
.burst_length_four (vdd ),
.dram_io_pad_clk_inv (dram2_io_pad_clk_inv ),
.dram_io_pad_enable (dram2_io_pad_enable ),
.dram_io_drive_enable (dram2_io_drive_enable ),
.rst_l (rst_l ),
.dram_arst_l (dram_arst_l ),
.dram_io_channel_disabled (dram2_io_channel_disabled ),
.dram_io_drive_data (dram2_io_drive_data ),
.vdd_h (vdd18 ) );
bw_u1_buf_40x I225 (
.z (clk_ddr2_cken_buf ),
.a (clk_ddr2_cken ) );
bw_u1_scanl_2x lockup_latch(
.so(ddr_so),
.sd(ddr_so_pre_latch),
.ck(rclk));
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
// by: wig
// on: Mon Oct 23 16:54:16 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver2006.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.1 2006/10/30 15:38:11 wig Exp $
// $Date: 2006/10/30 15:38:11 $
// $Log: inst_b_e.v,v $
// Revision 1.1 2006/10/30 15:38:11 wig
// Updated testcase bitsplice/rfe20060904a and added some bug testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.96 2006/10/23 08:31:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_b_e
//
// No user `defines in this module
module inst_b_e
//
// Generated Module inst_b
//
(
only_low // Only ::low defined
);
// Generated Module Inputs:
input only_low;
// Generated Wires:
wire only_low;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_b_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_64_1.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 64,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_bb.v FALSE
|
// DE1-SOC Interface Specification
// KEY0= rising lock edge (When pressed)
// KEY1= Reset button
// LEDR[9:7]= status register output
// HEX3, HEX2, HEX1, HEX0= wired for LED display
module top(KEY, CLOCK_50, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);
input [1:0] KEY;
input CLOCK_50;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire [15:0] mdata, B, C, sximm5, sximm8, instruction;
wire write, loada, loadb, asel, bsel, loadc, loads, loadpc, msel, mwrite;
wire [2:0] readnum, writenum, opcode;
wire [1:0] shift, ALUop, op, vsel, nsel;
wire [7:0] address;
datapath datapathInstantiate(
.clk(~KEY[0]),
//register module
.readnum(readnum),
.vsel(vsel),
.loada(loada),
.loadb(loadb),
//computation + alu + shift modules
.shift(shift),
.asel(asel),
.bsel(bsel),
.ALUop(ALUop),
.loadc(loadc),
.loads(loads),
// write module
.writenum(writenum),
.write(write),
.mdata(mdata),
.sximm5(sximm5),
.sximm8(sximm8),
// outputs
.status(LEDR[9:7]),
.B(B),
.C(C)
);
decoder decoderInstantiate(
.instruction(instruction),
.nsel(nsel),
.opcode(opcode),
.readnum(readnum),
.writenum(writenum),
.ALUop(ALUop),
.op(op),
.shift(shift),
.sximm5(sximm5),
.sximm8(sximm8)
);
instructionReg instrRegInstantiate(
.clk(~KEY[0]),
.mdata(mdata),
.loadir(loadir),
.instruction(instruction)
);
RAM #(16,8,"data.txt") RAMInstantiate(
.clk(~KEY[0]),
.readAddress(address),
.writeAddress(address),
.mwrite(mwrite),
.in(B), //B is what is being written in
.out(mdata) //output is both instructions as well as values in the addresses
);
counter counterInstantiate(
.clk(~KEY[0]),
.reset(~KEY[1]),
.loadpc(loadpc),
.msel(msel),
.C(C),
.address(address) //output of counter is the read address
);
controller controllerInstantiate(
.clk(~KEY[0]),
.ALUop(ALUop),
.op(op),
.shift(shift),
.opcode(opcode),
.readnum(readnum),
.writenum(writenum),
.loada(loada),
.loadb(loadb),
.write(write),
.asel(asel),
.bsel(bsel),
.loadc(loadc),
.loads(loads),
.reset(~KEY[1]),
.loadpc(loadpc),
.msel(msel),
.mwrite(mwrite),
.loadir(loadir),
.nsel(nsel),
.vsel(vsel)
);
// assigned HEX display to datapath_out values
// HEXDisplay HEX0Instantiate(datapath_out[3:0], HEX0);
// HEXDisplay HEX1Instantiate(datapath_out[7:4], HEX1);
// HEXDisplay HEX2Instantiate(datapath_out[11:8], HEX2);
// HEXDisplay HEX3Instantiate(datapath_out[15:12], HEX3);
// assign HEX4 = 7'b1111111; // disabled
// assign HEX5 = 7'b1111111; // disabled
endmodule
|
Require Export Ch10_Smallstep.
Inductive Sec : Type :=
| L : Sec
| H : Sec.
Inductive Ty : Type :=
| an : RawTy -> Sec -> Ty
with RawTy : Type :=
| int : RawTy
| fn : Ty -> Sec -> Ty -> RawTy
| unit : RawTy
| ref : Ty -> RawTy.
Scheme Ty_mut := Induction for Ty Sort Prop
with RawTy_ := Induction for RawTy Sort Prop.
(*###subtyping###*)
Inductive subsum_r : Sec -> Sec -> Prop :=
| sub_refl: forall b : Sec,
subsum_r b b
| sub_LH: subsum_r L H
.
Lemma subsum_r_trans: forall a b c,
subsum_r a b ->
subsum_r b c ->
subsum_r a c.
Proof. intros. inversion H0. subst. inversion H1. subst.
apply sub_refl. apply sub_LH. destruct c. apply sub_refl.
apply sub_LH.
Qed.
Reserved Notation "T '<:' U" (at level 40).
Inductive subtyping : Ty -> Ty -> Prop :=
| subt_int: forall b b',
subsum_r b b' ->
(an int b) <: (an int b')
| subt_fn: forall b b' pc pc' T1 T1' T2 T2',
subsum_r b b' ->
subsum_r pc' pc ->
T1' <: T1 ->
T2 <: T2' ->
(an (fn T1 pc T2) b) <: (an (fn T1' pc' T2') b')
| subt_unit: forall b b',
subsum_r b b' ->
(an unit b) <: (an unit b')
| subt_ref: forall b b' T,
subsum_r b b' ->
(an (ref T) b) <: (an (ref T) b')
where "t1 '<:' t2" := (subtyping t1 t2).
Lemma subtyping_refl: forall T,
T <: T.
Proof. apply (Ty_mut (fun T => T <: T) (fun RT => forall b, (an RT b) <: (an RT b))).
intros. apply H0.
intros. apply subt_int. apply sub_refl.
intros. apply subt_fn. apply sub_refl. apply sub_refl. apply H0. apply H1.
intros. apply subt_unit. apply sub_refl.
intros. apply subt_ref. apply sub_refl.
Qed.
Lemma subtyping_trans: forall y z x z',
x <: y -> z <: x -> y <: z' -> z <: z'.
Proof. intros. generalize dependent z. generalize dependent z'. induction H0.
Case ("int").
intros. inversion H2. subst. inversion H1. subst. apply subt_int. apply subsum_r_trans with (a:=b0)(b:=b)(c:=b')in H6.
apply subsum_r_trans with (a:=b0)(b:=b')(c:=b'0) in H6. apply H6. apply H4. apply H0.
Case ("fn").
intros. inversion H2. subst. inversion H3. subst.
apply subt_fn. apply subsum_r_trans with (a:=b0)(b:=b)(c:=b') in H13.
apply subsum_r_trans with (a:=b0)(b:=b')(c:=b'0) in H13. apply H13. apply H8. apply H0.
apply subsum_r_trans with (a:=pc'0)(b:=pc')(c:=pc)in H10. apply subsum_r_trans with (a:=pc'0)(b:=pc)(c:=pc0)in H10.
apply H10. apply H14. apply H1.
apply IHsubtyping1. apply H15. apply H11.
apply IHsubtyping2. apply H12. apply H16.
Case ("unit").
intros. inversion H1. subst. inversion H2. subst. apply subt_unit.
apply subsum_r_trans with (a:=b0)(b:=b)(c:=b')in H5. apply subsum_r_trans with (a:=b0)(b:=b')(c:=b'0)in H5.
apply H5. apply H4. apply H0.
Case ("ref").
intros. inversion H2. inversion H1. subst. apply subt_ref.
apply subsum_r_trans with (a:=b1)(b:=b)(c:=b')in H9. apply subsum_r_trans with (a:=b1)(b:=b')(c:=b'0)in H9.
apply H9. apply H6. apply H0.
Qed.
(*variable environment*)
(*############typing context############*)
Definition context := id -> option Ty.
Definition empty_context : context :=
fun _ => None.
Definition Cupdate (St : context) (X:id) (T : option Ty) : context :=
fun X' => if beq_id X X' then T else St X'.
(*#######some useful theorems regarding [Cupdate]#########*)
Theorem Cupdate_eq : forall T X St,
(Cupdate St X T) X = T.
Proof.
intros. unfold Cupdate. rewrite<-beq_id_refl. reflexivity.
Qed.
Theorem Cupdate_neq : forall X2 X1 T St,
beq_id X2 X1 = false ->
(Cupdate St X2 T) X1 = (St X1).
Proof.
intros. unfold Cupdate. rewrite H0. reflexivity.
Qed.
Theorem Cupdate_shadow : forall T1 T2 X1 X2 (f : context),
(Cupdate (Cupdate f X2 T1) X2 T2) X1 = (Cupdate f X2 T2) X1.
Proof.
intros. unfold Cupdate. destruct (beq_id X2 X1). reflexivity.
reflexivity.
Qed.
Theorem Cupdate_same : forall T1 X1 X2 (f : context),
f X1 = T1 ->
(Cupdate f X1 T1) X2 = f X2.
Proof.
intros. unfold Cupdate. remember (beq_id X1 X2) as D. destruct D.
Case ("true"). apply beq_id_eq in HeqD. subst. reflexivity.
reflexivity.
Qed.
Theorem Cupdate_permute : forall T1 T2 X1 X2 X3 f,
beq_id X2 X1 = false ->
(Cupdate (Cupdate f X2 T1) X1 T2) X3 = (Cupdate (Cupdate f X1 T2) X2 T1) X3.
Proof.
intros. unfold Cupdate. remember (beq_id X1 X3) as D1. remember (beq_id X2 X3) as D2.
destruct D1.
Case ("D1=true"). destruct D2.
SCase ("D2=true"). apply beq_id_false_not_eq in H0. apply beq_id_eq in HeqD1.
apply beq_id_eq in HeqD2. rewrite<-HeqD2 in HeqD1.
unfold not in H0. symmetry in HeqD1. apply H0 in HeqD1.
inversion HeqD1.
SCase ("D2=false"). reflexivity.
Case ("D1=false"). destruct D2.
SCase ("D2=true"). reflexivity.
SCase ("D2=false"). reflexivity.
Qed.
(*end typing context*)
(*heap_Ty*)
Definition heap_Ty := list Ty.
Fixpoint heap_Tlookup (n:nat)(ht:heap_Ty): option Ty :=
match ht , n with
| nil , _ => None (*default return*)
| h::t , 0 => Some h
| h::t , S n' =>heap_Tlookup n' t
end.
(*end heap_Ty*)
(*functional extensionality*)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(*end*)
Module SecLang.
(*syntax*)
Inductive tm : Type :=
| tvar : id -> tm
| tprot : Sec -> tm -> tm
| tcon : nat -> Sec -> tm
| tabs : id -> Ty -> tm -> Sec -> tm
| tapp : tm -> tm -> tm
(*#####new terms######*)
| tunit : Sec -> tm
| tref : Ty -> tm -> Sec -> tm (*[Ty] as the initial type*)
| tderef : tm -> tm
| tloc : Ty -> option nat -> Sec -> tm(*[Ty] as the "access type"*)
(**
Note that regarding the type of the referred location in [tloc] we use
[option nat] instead of [nat]
*)
| tassign : tm -> tm -> tm.
(*values*)
(*###values###*)
Inductive value : tm -> Prop :=
| v_c : forall b n,
value (tcon n b)
| v_f : forall n T e b,
value (tabs (Id n) T e b)
| v_u : forall b,
value (tunit b)
| v_l : forall n T b,
value (tloc T (Some n) b).
(*###heaps###*)
Definition heap := list (tm*Ty).
Definition emp_hp:= @nil (tm*Ty).
(*###some useful functions###*)
(*###lookup function and some lemmas###*)
Fixpoint heap_lookup (n:nat)(st:heap):(option (tm*Ty)):=
match st , n with
| nil , _ =>None
| h::t , 0 => Some h
| h::t , S n' =>heap_lookup n' t
end.
(*extract the result of [heap_lookup]*)
Definition efst (p:option(tm*Ty)) : tm :=
match p with
| None => tvar (Id 100)
| Some (t , T) => t
end.
Definition esnd (p:option(tm*Ty)) : Ty :=
match p with
| None => an unit L
| Some (t, T) => T
end.
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
Lemma length_snoc:forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
intros. generalize dependent x. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x). rewrite->IHl.
reflexivity.
Qed.
Lemma lt_snoc_1 : forall n m,
S n <= S m -> n <= m.
Proof.
intros n m. generalize dependent n. induction m as [|m'].
Case ("m=0"). intros. destruct n as [|n'].
SCase ("n=0"). apply le_n.
SCase ("n=S n'"). inversion H0. inversion H2.
Case ("m=S m'"). intros. inversion H0. apply le_n. apply le_S.
apply IHm'. apply H2.
Qed.
Lemma lt_snoc: forall (l:heap) x (n:nat),
n < length l ->
heap_lookup n l = heap_lookup n (snoc l x).
Proof.
intros l. induction l.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. simpl. destruct n. reflexivity. simpl.
apply IHl. simpl in H0. apply lt_snoc_1 in H0.
apply H0.
Qed.
Lemma eq_snoc: forall (l:heap) x,
heap_lookup (length l) (snoc l x) = Some x.
Proof.
intros l. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x).
apply IHl.
Qed.
(*###replace function and some lemmas###*)
Fixpoint heap_replace n x (l:heap): heap :=
match l , n with
| nil , _ =>nil
| h::t , 0 => x::t
| h::t , S n' =>h :: (heap_replace n' x t)
end.
Lemma replace_nil: forall n x,
heap_replace n x nil = nil.
Proof.
intros. destruct n. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma length_replace: forall n x (l:heap),
length (heap_replace n x l) = length l.
Proof.
intros. generalize dependent n. generalize dependent x. induction l.
Case ("nil"). intros. simpl. rewrite->replace_nil. simpl. reflexivity.
Case ("h::t"). intros. simpl. destruct n. simpl. reflexivity.
simpl. specialize (IHl x n). rewrite->IHl. reflexivity.
Qed.
Lemma lookup_replace_eq: forall l t st,
l < length st ->
heap_lookup l (heap_replace l t st) = Some t.
Proof.
intros. generalize dependent l. generalize dependent t.
induction st.
Case ("nil"). intros. destruct l. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct l. simpl. reflexivity.
simpl. apply IHst. simpl in H0. unfold lt. unfold lt in H0.
apply lt_snoc_1 in H0. apply H0.
Qed.
Lemma lookup_replace_neq: forall l1 l2 t st,
l1 <> l2 ->
heap_lookup l1 (heap_replace l2 t st) = heap_lookup l1 st.
Proof.
intros. generalize dependent l1. generalize dependent l2. generalize dependent t.
induction st.
Case ("nil"). intros. rewrite->replace_nil. reflexivity.
Case ("h::t"). intros. destruct l2. destruct l1. simpl. assert (0=0). reflexivity.
apply H0 in H1. inversion H1. simpl. reflexivity. simpl.
destruct l1. reflexivity. apply IHst.
intros T. assert (l1 = l2 -> S l1 = S l2). intros. subst. reflexivity.
apply H1 in T. apply H0 in T. inversion T.
Qed.
(*###########*)
(*###end heap###*)
(*###substitution###*)
Fixpoint subst (x:id) (s:tm) (t:tm): tm :=
match t with
(*variables*)
| tvar x' =>
if beq_id x x' then s else t
(*protects*)
| tprot b t' =>
tprot b (subst x s t')
(*abstractions*)
| tabs x' T t1 b =>
tabs x' T (if beq_id x x' then t1 else (subst x s t1)) b
(*constants*)
| tcon n b => tcon n b
(*applications*)
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
(*units*)
| tunit b => tunit b
(*tref*)
| tref T t1 b => tref T (subst x s t1) b
(*tderef*)
| tderef t1 => tderef (subst x s t1)
(*tloc*)
| tloc T N b => tloc T N b
(*assignments*)
| tassign t1 t2 => tassign (subst x s t1)(subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(*###reduction relation###*)
(*###"join" functions###*)
Definition joins (b1:Sec) (b2:Sec): Sec :=
match b1 with
| L => b2
| H => H
end.
Fixpoint joinVS (T:tm) (b:Sec): option tm :=
match T , b with
| tvar x , _ => None
| tprot b e , _ => None
| tcon n b , L => Some (tcon n b)
| tcon n b , H => Some (tcon n H)
| tabs x T e b , L => Some (tabs x T e b)
| tabs x T e b , H => Some (tabs x T e H)
| tapp t1 t2 , _ => None
| tunit b , L => Some (tunit b)
| tunit b , H => Some (tunit H)
| tref T e b , _ => None
| tderef e , _ => None
| tloc T N b , L => Some (tloc T N b)
| tloc T N b , H => Some (tloc T N H)
| tassign t1 t2 , _ => None
end.
(*############*)
Definition extract (t:option Ty) : Ty :=
match t with
| Some T => T
| None => an unit L (*default type*)
end.
(*############*)
Definition extractT (t:option tm) : tm :=
match t with
| Some e => e
| None => tvar (Id 100)
end.
Definition joinvs (T:tm) (b:Sec): tm :=
extractT (joinVS T b).
Definition joinTs (T:Ty)(b:Sec) : Ty :=
match T , b with
| an rt s , L => an rt s
| an rt s , H => an rt H
end.
(*"get-label" functions*)
Fixpoint Label (t:tm) : option Sec :=
match t with
| tvar x => None
| tprot H t => Some H
| tprot L t => Label t
| tcon n b => Some b
| tabs x T e b => Some b
| tapp t1 t2 => None
| tunit b => Some b
| tref T e b => None
| tderef e => None
| tloc T N b => Some b
| tassign t1 t2 => None
end.
Definition eLabel (s:option Sec) : Sec :=
match s with
| Some s' => s'
| None => L
end.
Definition label (t:tm) : Sec :=
eLabel (Label t).
Definition labelT (T:Ty) : Sec:=
match T with
| an rt b => b
end.
(**
Now,we impose upon the language a relation which restricts the
form of expressions we are interested in when doing reduction.
Specifically we want to exclude from our consideration expression
which contains pointers whose referred location is out of range,
e.g. tapp t1 (tloc T n L) where n is equal or greater than the length
of the current heap
*)
(*well formed expressions*)
Inductive well_formed : tm -> nat -> Prop :=
| wf_tvar:forall (x:id)(hp:nat),
well_formed (tvar x) hp
| wf_tcon:forall (b:Sec)(n:nat)(hp:nat),
well_formed (tcon n b) hp
| wf_tunit:forall (b:Sec)(hp:nat),
well_formed (tunit b) hp
| wf_tloc:forall (T:Ty)(n:nat)(b:Sec)(hp:nat),
n < hp ->
well_formed (tloc T (Some n) b) hp
| wf_tprot:forall b t (hp:nat),
well_formed t hp ->
well_formed (tprot b t) hp
| wf_tabs:forall x T e b hp,
well_formed e hp ->
well_formed (tabs x T e b) hp
| wf_tapp:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tapp t1 t2) hp
| wf_tref:forall (T:Ty) (e:tm) (b:Sec) (hp:nat),
well_formed e hp ->
well_formed (tref T e b) hp
| wf_tderef:forall e hp,
well_formed e hp ->
well_formed (tderef e) hp
| wf_tassign:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tassign t1 t2) hp.
(*some examples of well-formed expressions*)
Example well_formed_1:
well_formed (tvar (Id 0)) 0.
Proof. apply wf_tvar.
Qed.
Example well_formed_2:
well_formed (tprot H (tloc (an int L) (Some 0) L)) 1.
Proof. apply wf_tprot. apply wf_tloc. apply le_n.
Qed.
Example well_formed_3:forall hp,
well_formed (tcon 0 H) hp.
Proof. intros. apply wf_tcon.
Qed.
Example well_formed_4:forall hp,
well_formed (tunit L) hp.
Proof. intros. apply wf_tunit.
Qed.
Example well_formed_5:
well_formed (tabs (Id 0)(an int L)(tderef (tloc (an int L) (Some 0) H)) L) 1.
Proof. apply wf_tabs. apply wf_tderef. apply wf_tloc. apply le_n.
Qed.
Example well_formed_6:forall hp,
well_formed (tref (an int L) (tcon 0 L) H) hp.
Proof. intros. apply wf_tref. apply wf_tcon.
Qed.
Example well_formed_7:
well_formed (tassign (tloc (an int L) (Some 0) L)(tcon 1 L)) 1.
Proof. apply wf_tassign. apply wf_tloc. apply le_n. apply wf_tcon.
Qed.
(*some examples of ill-formed expression*)
Example ill_formed_1:
~well_formed (tloc (an int L) (Some 0) L) 0.
Proof. intros contra. inversion contra. inversion H4.
Qed.
Example ill_formed_2:
~well_formed (tapp (tref (an int L) (tcon 1 L) L)(tloc (an int L) (Some 1) L)) 1.
Proof. intros contra. inversion contra. inversion H4. inversion H9. inversion H11.
Qed.
Example ill_formed_3:
~well_formed (tassign (tloc (an int L) (Some 1) L)(tapp (tabs (Id 0)(an int L)(tvar (Id 0)) L)(tcon 1 L))) 1.
Proof. intros contra. inversion contra. inversion H2. inversion H9. inversion H11.
Qed.
(*some lemmas regarding [well_formed]*)
Lemma well_formed_extend:forall t hp,
well_formed t hp ->
well_formed t (S hp).
Proof. intros t. induction t.
Case ("tvar"). intros. apply wf_tvar.
Case ("tprot"). intros. inversion H0. apply wf_tprot. apply IHt. apply H4.
Case ("tcon"). intros. apply wf_tcon.
Case ("tabs"). intros. inversion H0. apply wf_tabs. apply IHt. apply H6.
Case ("tapp"). intros. inversion H0. apply wf_tapp. apply IHt1. apply H3.
apply IHt2. apply H5.
Case ("tunit"). intros. apply wf_tunit.
Case ("tref"). intros. apply wf_tref. apply IHt. inversion H0. apply H5.
Case ("tderef"). intros. apply wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct o. apply wf_tloc. inversion H0.
apply le_S. apply H5. inversion H0.
Case ("tassign"). intros. apply wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Qed.
(**
Also,we restrict the heap at the beginning of our reduction such that
each and every element within the heap is well-foremed according to
the heap itself,
*)
(*heap well_formed*)
Inductive heap_well_formed : heap -> nat -> Prop :=
| nil_hwf:forall n,
heap_well_formed nil n
| one_hwf:forall t0 t T n,
heap_well_formed t n ->
well_formed t0 n ->
heap_well_formed ((t0,T) :: t) n.
(*some lemmas regarding [heap_well_formed]*)
Lemma heap_well_formed_extend'': forall n m,
n <= m -> S n <= S m.
Proof.
intros. induction H0. apply le_n. apply le_S. apply IHle.
Qed.
Lemma heap_well_formed_extend':forall (T:Type)(l:nat) (hp:list T),
l <= length hp ->
l <> length hp ->
l < length hp.
Proof. intros. unfold not in H1. unfold lt. inversion H0. apply H1 in H2. inversion H2.
apply heap_well_formed_extend'' in H3. apply H3. Qed.
Lemma heap_well_formed_extend:forall hp t T n,
heap_well_formed hp n->
well_formed t n ->
heap_well_formed (snoc hp (t,T)) (S n).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. apply one_hwf. apply nil_hwf. apply well_formed_extend. apply H1.
Case ("h::t"). intros. simpl. destruct a. apply one_hwf. apply IHhp. inversion H0. apply H6.
apply H1. inversion H0. subst. apply well_formed_extend. apply H7.
Qed.
Lemma heap_well_formed_shrink:forall hp a n,
heap_well_formed (a :: hp) n ->
heap_well_formed hp n.
Proof. intros. inversion H0. apply H3.
Qed.
Lemma lt_same_F' : forall n m,
S n <= S m -> n <= m.
Proof. intros. generalize dependent n. induction m.
intros. destruct n. apply le_n. inversion H0. inversion H2.
intros. inversion H0. apply le_n. apply le_S. apply IHm in H2.
apply H2. Qed.
Lemma lt_same_F:forall n,
n < n -> False.
Proof. intros. induction n. inversion H0. unfold lt in H0. unfold lt in IHn.
apply lt_same_F' in H0. apply IHn in H0. inversion H0. Qed.
Lemma heap_well_formed_replace:forall hp t T n n',
well_formed t n ->
heap_well_formed hp n ->
n' < length hp ->
heap_well_formed (heap_replace n' (t,T) hp) n.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl in H2. destruct n'. apply lt_same_F in H2. inversion H2. inversion H2.
Case ("h::t"). intros. destruct n'. simpl. apply one_hwf. inversion H1. apply H5. apply H0. simpl.
destruct a. apply one_hwf. apply IHhp. apply H0. inversion H1. apply H7. simpl in H2.
apply lt_same_F' in H2. apply H2. inversion H1. apply H8.
Qed.
(**
Note that the reason for having this additional restriction upon the heap is
that when the heap is extended we have to make sure that the projection of the
elements on the heap before the allocation is the same as that of those on the
heap after the allocation,
project_conf'_hp (project_hp heap)(project_hp heap)
=
project_conf'_hp (project_hp heap)(project_hp (snoc heap v)),
where [v] stands for a low value
*)
(**
Note regarding the reduction relation, there are few modifications made,
a. [st_refv]
1. the cell being written is guarded by both the security context and
the label of the allocation
2. moreover,we have to guarantee that the label of the cell being written
subsums that of its type
b. [st_assign]
1. the label of the resulting unit is the joint of PC and the label of the pointer
2. the label of the cell written to the heap has to be guarded by that of its type
3. the label of the cell on the heap being over-written equals the joint of the label
of the referred type and that of the replacing value
Note [a.2] and [b.2] together guarantee that for every pair in heap, the label of
the first element subsums that of the second one. This extra condition imposed upon
our typing system allows us to reintroduce "the condition" without sacrificing [progress]
c. [st_ref]
1. the security_context where the sub-term is reduced has to be guarded by
the label of the pointer for when we have a high pointer we have to make
sure that we also write high value to the heap so that our projection function
can successfully handle this case in the sense that the resulting reduction
is allowed in [LowLang]
Note that there are two types of over-writing we care for in the system,
1. a low cell being over-written by a low value
tassign (tloc (an int L) 0 L)(tcon 1 L) / ((tcon 0 L,an int L) :: nil)
==L=>
tunit L / ((tcon 1 L,an int L) :: nil)
2. a high cell being over-written by a high value
tassign (tloc (an int L) 0 L)(tcon 1 H) / ((tcon 0 H,an int L) :: nil)
==L=>
tunit L / ((tcon 1 H,an int L) :: nil)
##########################################################################
the remaining two cases are left out currently,
3. a high cell being over-written by a low value
tassign (tloc (an int L) 0 L)(tcon 1 L) / ((tcon 0 H,an int L) :: nil)
==L=>
tunit L / ((tcon 1 L,an int L) :: nil)
4. a low cell being over-written by a high value
tassign (tloc (an int L) 0 L)(tcon 1 H) / ((tcon 0 L,an int L) :: nil)
==L=>
tunit L / ((tcon 1 H,an int L) :: nil)
##########################################################################
*)
(**
Now in addition to the above analysis,we also require that the expression we
are concerned with before reduction is well-formed. This is already adequate for
us to exclude from consideration all expression involved in the reduction process
which are ill-formed for the heap can only be extended in the process.
*)
(*##########*)
Reserved Notation "t1 '/' hp '==' PC '=>' t2 '/' hp'"
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
Inductive step : tm * heap -> Sec -> tm * heap -> Prop :=
| st_prot: forall b PC t t' hp hp',
heap_well_formed hp (length hp)-> (*additional requirement*)
well_formed t (length hp) -> (*additional requirement*)
t / hp == (joins PC b) => t' / hp' ->
tprot b t / hp == PC => tprot b t' / hp'
| st_protv: forall b v hp PC,
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
value v ->
tprot b v / hp == PC => joinvs v b / hp
| st_appabs: forall x T e b PC hp v,
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
well_formed e (length hp) -> (*additional requirement*)
value v ->
tapp (tabs x T e b) v / hp == PC => tprot b ([x := v]e) / hp
| st_app1: forall t1 t1' t2 PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
t1 / hp == PC => t1' / hp' ->
tapp t1 t2 / hp == PC => tapp t1' t2 / hp'
| st_app2: forall v1 t2 t2' PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
value v1 ->
t2 / hp == PC => t2' / hp' ->
tapp v1 t2 / hp == PC => tapp v1 t2' / hp'
| st_refv: forall T v v' b b' b'' b''' PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
value v ->
b' = labelT T ->
b'' = joins b PC -> (*join PC with label of the pointer*)
b''' =joins b' b'' ->(*then join with the label of the type of the pointer*)
v' = joinvs v b''' ->
hp' = snoc hp (v',T) ->
tref T v b / hp == PC => tloc T (Some (length hp)) b / hp'
| st_ref: forall T t t' b PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t (length hp) -> (*additional requirement*)
t / hp == (joins PC b) => t' / hp' ->
tref T t b / hp == PC => tref T t' b / hp'
| st_derefloc: forall T n b PC hp t,
heap_well_formed hp (length hp) -> (*additional requirement*)
n < length hp ->
t = efst (heap_lookup n hp) ->
tderef (tloc T (Some n) b) / hp == PC => tprot b t / hp
| st_deref: forall t t' hp hp' PC,
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t (length hp) -> (*additional requirement*)
t / hp == PC => t' / hp' ->
tderef t / hp == PC => tderef t' / hp'
| st_assign: forall v v' T T' b b' b'' b''' l n PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
n < length hp -> (* heap_lookup n hp = some e'*)
value v ->
l = label v ->
b' = labelT T ->
b'' = joins PC b ->
joins l b' = label (efst (heap_lookup n hp)) ->
subsum_r b'' (label (efst (heap_lookup n hp))) ->
b'''= joins b' b'' ->
T' = joinTs T b'' ->
v' = joinvs v b''' ->
hp' = heap_replace n (v',T') hp ->
tassign (tloc T (Some n) b) v / hp == PC => tunit b'' / hp'
| st_assign1: forall t1 t1' t2 PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
t1 / hp == PC => t1' / hp' ->
tassign t1 t2 / hp == PC => tassign t1' t2 / hp'
| st_assign2: forall v1 t2 t2' PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
value v1 ->
t2 / hp == PC => t2' / hp' ->
tassign v1 t2 / hp == PC => tassign v1 t2' / hp'
where "t1 '/' hp '==' PC '=>' t2 '/' hp'" := (step (t1,hp) PC (t2,hp')).
(*###multi-step reduction###*)
Definition Relation (X: Type) := X->Sec->X->Prop.
Inductive Multi {X:Type} (R: Relation X) : Relation X :=
| Multi_refl : forall (x : X)(b : Sec), Multi R x b x
| Multi_step : forall (x y z : X)(b : Sec),
R x b y ->
Multi R y b z ->
Multi R x b z.
Definition Multistep := (Multi step).
Notation "t1 '/' hp '==' PC '=>*' t2 '/' hp'" := (Multistep (t1,hp) PC (t2,hp'))
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
Definition stuck_term (s:tm) (hp:heap) (PC:Sec) : Prop :=
(~exists e', step (s,hp) PC e') /\ (~value s).
(*Some reduction examples*)
Example test_step_1:
tref (an int L)(tcon 0 L) L / emp_hp
==L=>
tloc (an int L) (Some 0) L / ((tcon 0 L,an int L) :: emp_hp).
Proof. apply st_refv with (v':=tcon 0 L)(b':=L)(b'':=L)(b''':=L).
apply nil_hwf.
apply wf_tcon. apply v_c. reflexivity.
reflexivity. reflexivity. reflexivity. reflexivity. Qed.
Example test_step_2:forall hp,
heap_well_formed hp (length hp) ->
tref (an int L)(tcon 0 L) H / hp
==L=>
tloc (an int L) (Some (length hp)) H / snoc hp (tcon 0 H,an int L).
Proof. intros. apply st_refv with (v':=tcon 0 H)(b':=L)(b'':=H)(b''':=H).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
Example test_step_3:forall hp,
heap_well_formed hp (length hp) ->
tref (an int H)(tcon 0 L) L / hp
==L=>
tloc (an int H) (Some (length hp)) L / snoc hp (tcon 0 H,an int H).
Proof. intros. apply st_refv with (v':=tcon 0 H)(b':=H)(b'':=L)(b''':=H).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
Example test_step_4:forall hp,
heap_well_formed hp (length hp) ->
tref (an int L)(tcon 0 H) L / hp
==L=>
tloc (an int L) (Some (length hp)) L / snoc hp (tcon 0 H,an int L).
Proof. intros. apply st_refv with (v':=tcon 0 H)(b':=L)(b'':=L)(b''':=L).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
Lemma test_step_5'': forall n m,
n <= m -> S n <= S m.
Proof.
intros. induction H0. apply le_n. apply le_S. apply IHle.
Qed.
Lemma test_step_5':forall (T:Type)(l:nat) (hp:list T),
l <= length hp ->
l <> length hp ->
l < length hp.
Proof. intros. unfold not in H1. unfold lt. inversion H0. apply H1 in H2. inversion H2.
apply test_step_5'' in H3. apply H3. Qed.
Example test_step_5:forall hp,
heap_well_formed hp (length hp) ->
tprot H (tref (an int H)(tcon 0 L) L) / hp
==L=>*
tloc (an int H) (Some (length hp)) H / snoc hp (tcon 0 H,an int H).
Proof. intros. apply Multi_step with (y:=(tprot H (tloc (an int H)(Some (length hp)) L),(snoc hp (tcon 0 H,an int H)))).
apply st_prot.
apply H0.
apply wf_tref. apply wf_tcon.
apply st_refv with (v':=tcon 0 H)(b':=H)(b'':=H)(b''':=H).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity.
reflexivity. reflexivity.
apply Multi_step with (y:=(tloc (an int H) (Some (length hp)) H,(snoc hp (tcon 0 H,an int H)))). apply st_protv.
rewrite->length_snoc.
apply heap_well_formed_extend. apply H0. apply wf_tcon.
apply wf_tloc. rewrite->length_snoc. apply le_n. apply v_l.
apply Multi_refl. Qed.
Example test_step_6:forall hp,
heap_well_formed hp (length hp) ->
tprot L (tref (an int H)(tcon 0 L)L) / hp
==L=>*
tloc (an int H) (Some (length hp)) L / snoc hp (tcon 0 H,an int H).
Proof. intros. apply Multi_step with (y:=(tprot L (tloc (an int H) (Some (length hp)) L),(snoc hp (tcon 0 H,an int H)))).
apply st_prot. apply H0. apply wf_tref. apply wf_tcon.
apply st_refv with (v':=tcon 0 H)(b':=H)(b'':=L)(b''':=H). apply H0. apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity.
reflexivity. reflexivity.
apply Multi_step with (y:=(tloc (an int H) (Some (length hp)) L,(snoc hp (tcon 0 H,an int H)))). apply st_protv. rewrite->length_snoc.
apply heap_well_formed_extend.
apply H0. apply wf_tcon.
apply wf_tloc. rewrite->length_snoc. apply le_n.
apply v_l. apply Multi_refl. Qed.
(*a low cell is being over-written by a low value*)
Example test_step_7:
tassign (tloc (an int L) (Some 0) L)(tcon 1 L) / ((tcon 0 L,an int L) :: emp_hp)
==L=>
tunit L / ((tcon 1 L,an int L) :: emp_hp).
Proof. apply st_assign with (v':=tcon 1 L)(T':=an int L)(b':=L)(b''':=L)(l:=L).
assert (snoc emp_hp (tcon 0 L,an int L)=((tcon 0 L,an int L) :: emp_hp)). reflexivity. rewrite<-H0.
rewrite->length_snoc.
apply heap_well_formed_extend. apply nil_hwf. apply wf_tcon.
apply wf_tcon.
apply le_n. apply v_c. reflexivity. reflexivity.
reflexivity. reflexivity. apply sub_refl. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
(*high cell being over-written by a high value*)
Example test_step_8:
tassign (tloc (an int H) (Some 0) L)(tcon 1 H) / ((tcon 0 H,an int H) :: emp_hp)
==L=>
tunit L / ((tcon 1 H,an int H) :: emp_hp).
Proof. apply st_assign with (v':=tcon 1 H)(T':=an int H)(b':=H)(b''':=H)(l:=H).
assert ((tcon 0 H,an int H) :: emp_hp = snoc emp_hp (tcon 0 H,an int H)). reflexivity.
rewrite->H0. rewrite->length_snoc. apply heap_well_formed_extend. apply nil_hwf. apply wf_tcon.
apply wf_tcon.
apply le_n. apply v_c.
reflexivity. reflexivity. reflexivity. reflexivity. apply sub_LH. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
(*high cell being over-written by a low value*)
Example test_step_9:
stuck_term (tassign (tloc (an int L) (Some 0) L)(tcon 1 L)) ((tcon 0 H,an int L) :: emp_hp) L.
Proof. split. intros contra. inversion contra. inversion H0. subst.
simpl in H13. inversion H13.
inversion H9. inversion H10. intros contra. inversion contra.
Qed.
(*low cell being over-written by high value
*)
Example test_step_9':
stuck_term (tassign (tloc (an int L) (Some 0) L)(tcon 1 H)) ((tcon 0 L,an int L) :: emp_hp) L.
Proof. split. intros contra. inversion contra. inversion H0. subst. inversion H13. inversion H9.
inversion H10. intros contra. inversion contra.
Qed.
Example test_step_10:
stuck_term (tassign (tloc (an int L) (Some 0) H)(tcon 1 L)) ((tcon 0 L,an int H) :: emp_hp) L.
Proof. split. intros contra. inversion contra. inversion H0. subst. inversion H14. inversion H9. inversion H10.
intros contra. inversion contra.
Qed.
Example test_step_11:
stuck_term (tassign (tloc (an int L) (Some 0) L)(tcon 1 L)) ((tcon 0 L,an int L) :: emp_hp) H.
Proof. split. intros contra. inversion contra. inversion H0. subst. simpl in H14. inversion H14. inversion H9.
inversion H10. intros contra. inversion contra.
Qed.
Example test_step_12:
stuck_term (tassign (tloc (an int L) (Some 0) H)(tcon 1 L))((tcon 0 L,an int L) :: emp_hp) H.
Proof. split. intros contra. inversion contra. inversion H0. subst. simpl in H14. inversion H14. inversion H9. inversion H10.
intros contra. inversion contra.
Qed.
Example test_step_13:
tref (an (ref (an int L)) L) (tref (an int L)(tcon 0 L) L) H / nil
==L=>
tref (an (ref (an int L)) L) (tloc (an int L) (Some 0) L) H / ((tcon 0 H,an int L) :: nil).
Proof. apply st_ref. apply nil_hwf. apply wf_tref. apply wf_tcon.
apply st_refv with (v':=tcon 0 H)(b':=L)(b'':=H)(b''':=H). apply nil_hwf. apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity.
reflexivity.
Qed.
(**
Note that it is clear from the above examples that when a cell is being written the label
of the cell subsums that of its type. This is necessary for us to restore the restriction
for security upgrading without sacrificing [progress]
*)
(**
Note that by including extra condition in [st_assign], we can
no longer have the following property,
forall PC PC' t hp,
exists c,t / hp ==PC=> c -> exists c', t / hp ==PC'=> c'.
Consider the following configuration,
tassign (tloc (an int L) 0 L)(tcon 1 L) / ((tcon 0 L,an int L) :: emp_hp)
it is reducible under [L] while it is not under [H].
Actually,we can only argue that if a configuration is reducible under [H] then
it is also under [L]. See the following lemma.
*)
Lemma HL_scontext:forall s hp,
(exists e',step (s,hp) H e') ->
exists e',step (s,hp) L e'.
Proof.
intros s. induction s.
Case ("tvar"). intros. inversion H0. inversion H1.
Case ("tprot"). intros. inversion H0. inversion H1. subst. destruct s.
simpl in H9. assert (exists e',step (s0,hp) H e'). exists (t',hp').
apply H9. apply IHs in H2. inversion H2. destruct x. exists (tprot L t,h).
apply st_prot. apply H5. apply H8. simpl. apply H3. simpl in H9. exists (tprot H t',hp').
apply st_prot. apply H5. apply H8. simpl. apply H9. subst. exists (joinvs s0 s,hp). apply st_protv.
apply H5. apply H8.
apply H9.
Case ("tcon"). intros. inversion H0. inversion H1.
Case ("tabs"). intros. inversion H0. inversion H1.
Case ("tapp"). intros. inversion H0. inversion H1.
subst. exists (tprot b ([x0:=s2]e),hp). apply st_appabs. apply H5. apply H6. apply H9.
apply H10.
subst. assert (exists e',step (s1,hp) H e'). exists (t1',hp').
apply H10. apply IHs1 in H2. inversion H2. destruct x.
exists (tapp t s2,h). apply st_app1. apply H5. apply H6. apply H9. apply H3.
subst.
assert (exists e',step (s2,hp) H e'). exists (t2',hp'). apply H11.
apply IHs2 in H2. inversion H2. destruct x. exists (tapp s1 t,h).
apply st_app2. apply H5. apply H6. apply H7. apply H10. apply H3.
Case ("tunit"). intros. inversion H0. inversion H1.
Case ("tref"). intros. inversion H0. inversion H1. subst.
exists (tloc t (Some (length hp)) s0,snoc hp (joinvs s (joins (labelT t)(joins s0 L)),t)). apply st_refv with (v':=joinvs s (joins (labelT t)(joins s0 L)))(b':=labelT t)(b'':=joins s0 L)(b''':=joins (labelT t)(joins s0 L)).
apply H6.
apply H7. apply H8.
reflexivity. reflexivity. reflexivity. reflexivity. reflexivity. subst. destruct s0. simpl in H10.
assert (exists e',step (s,hp) H e'). exists (t',hp'). apply H10. apply IHs in H2. inversion H2.
destruct x. exists (tref t t0 L,h). apply st_ref. apply H8. apply H9. simpl. apply H3. simpl in H10. exists (tref t t' H,hp').
apply st_ref. apply H8. apply H9. simpl. apply H10.
Case ("tderef"). intros. inversion H0. inversion H1. subst. exists (tprot b (efst (heap_lookup n hp)),hp).
apply st_derefloc. apply H4. apply H5. reflexivity. subst. assert (exists e',step (s,hp) H e'). exists (t',hp').
apply H8. apply IHs in H2. inversion H2. destruct x. exists (tderef t,h). apply st_deref. apply H4. apply H5. apply H3.
Case ("tloc"). intros. inversion H0. inversion H1.
Case ("tassign"). intros. inversion H0. inversion H1. subst. exists (tunit (joins L b),heap_replace n (joinvs s2 (joins (labelT T)(joins L b)), joinTs T (joins L b)) hp).
apply st_assign with (v':=joinvs s2 (joins (labelT T)(joins L b)))(T':=joinTs T (joins L b))(b':=labelT T)(b''':=joins (labelT T)(joins L b))(l:=label s2). apply H5. apply H6. apply H7. apply H8. reflexivity. reflexivity. reflexivity.
apply H12. simpl.
apply subsum_r_trans with (a:= b)(b:= H)(c:=label (efst (heap_lookup n hp))). destruct b. apply sub_LH. apply sub_refl. simpl in H13. apply H13. reflexivity. reflexivity. reflexivity. reflexivity.
assert (exists e',step (s1,hp) H e'). exists (t1',hp'). apply H10. apply IHs1 in H11. inversion H11.
destruct x0. exists (tassign t s2,h ). apply st_assign1. apply H5. apply H6. apply H9. apply H12. subst. assert (exists e',step (s2,hp) H e'). exists (t2',hp').
apply H11. apply IHs2 in H2. inversion H2. destruct x. exists (tassign s1 t,h). apply st_assign2. apply H5. apply H6. apply H7. apply H10. apply H3.
Qed.
(*generalization of the above lemma*)
Lemma prot_scontext:forall s hp PC b,
(exists e', step (s,hp) (joins PC b) e') ->
exists e',step (s,hp) PC e'.
Proof.
intros. destruct PC. destruct b. simpl in H0. apply H0.
simpl in H0. apply HL_scontext. apply H0. simpl in H0.
apply H0.
Qed.
(*typing rule*)
(*typing relation*)
(**
Note that we make one change above in [st_ref] so that the evaluation of
the subterm in allocation is under the security context guarded by the label
of the allocation,
[st_ref]:forall T t t' b PC hp hp',
t / hp == (joins PC b) => t' / hp' ->
tref T t b / hp == PC => tref T t' b / hp'
this is some what similar to the reduction rule of protection when the
protected subterm is not a value.
Now we show that we have to modify [t_ref] as well in the following typing rule
so as to make the whole system sound. For without it [preservation breaks down],
[t_ref]: forall pc Gamma HT t T b b',
has_type (joins pc b) Gamma HT t T ->
b' = joins pc b ->
subsum_r b' (labelT T) ->
has_type pc Gamma HT (tref T t b) (an (ref T) b)
To see why we have to modify our typing rule consider the following legit reduction
sequence,
tref (an (ref (an int L)) L) (tref (an int L)(tcon 0 L) L) H / nil
==L=>
tref (an (ref (an int L)) L) (tloc (an int L) 0 L) H / ((tcon 0 H,an int L) :: nil),
according to [t_ref] we know that
has_type L empty_context []
(tref (an int L)(tcon 0 L) L)
(an (ref (an int L)) L)
which implies that
has_type L empty_context []
(tref (an (ref (an int L)) L) (tref (an int L)(tcon 0 L) L) H)
(an (ref (an (ref (an int L)) L)) H)
now we reduce it according to [st_ref] we have,
tref (an (ref (an int L)) L) (tloc (an int L) 0 L) H / ((tcon 0 H,an int L) :: nil)
and given the new heap_typing,HT',as [an int L] we again have the resulting term as
well-typed,
has_type L empty_context [an int L]
(tref (an (ref (an int L)) L) (tloc (an int L) 0 L) H)
(an (ref (an (ref (an int L)) L)) H)
however the [heap_well_typed] breaks down,
~has_typed pc empty_context HT
(tcon 0 H)
(an int L).
One way to fix it is to have the following typing rule,
[t_ref]: forall pc Gamma HT t T b b',
has_type (joins pc b) Gamma HT t T ->
b' = joins pc b ->
subsum_r b' (labelT T) ->
has_type pc Gamma HT (tref T t b) (an (ref T) b)
which renders the term before reduction ill-typed.
Qed.
*)
Inductive has_type : Sec -> context -> heap_Ty -> tm -> Ty -> Prop :=
| t_var : forall pc Gamma HT x T,
Gamma x = Some T ->
has_type pc Gamma HT (tvar x) T
| t_con : forall pc Gamma HT n b,
has_type pc Gamma HT (tcon n b) (an int b)
| t_unit: forall pc Gamma HT b,
has_type pc Gamma HT (tunit b) (an unit b)
| t_loc: forall pc Gamma HT T n b,
heap_Tlookup n HT = Some T ->
has_type pc Gamma HT (tloc T (Some n) b) (an (ref T) b)
| t_abs: forall pc pc' Gamma HT x T e b T',
has_type pc' (Cupdate Gamma x (Some T)) HT e T' ->
has_type pc Gamma HT (tabs x T e b) (an (fn T pc' T') b)
| t_prot: forall pc Gamma HT t b T T',
has_type (joins pc b) Gamma HT t T ->
T' = joinTs T b ->
has_type pc Gamma HT (tprot b t) T'
| t_app: forall pc Gamma HT T1 T2 T2' b t1 t2,
has_type pc Gamma HT t1 (an (fn T1 (joins pc b) T2) b) ->
has_type pc Gamma HT t2 T1 ->
joinTs T2 b = T2' ->
has_type pc Gamma HT (tapp t1 t2) T2'
| t_ref: forall pc Gamma HT t T b b',
has_type (joins pc b) Gamma HT t T ->
b' = joins pc b ->
subsum_r b' (labelT T)->
has_type pc Gamma HT (tref T t b) (an (ref T) b)
| t_deref: forall pc Gamma HT t T T' b,
has_type pc Gamma HT t (an (ref T) b) ->
T' = joinTs T b ->
has_type pc Gamma HT (tderef t) T'
| t_assign: forall pc Gamma HT t1 t2 b b' T,
b' = labelT T ->
subsum_r (joins pc b) b' ->
has_type pc Gamma HT t1 (an (ref T) b) ->
has_type pc Gamma HT t2 T ->
has_type pc Gamma HT (tassign t1 t2) (an unit b')
| t_sub: forall pc pc' Gamma HT t T T',
has_type pc Gamma HT t T ->
subsum_r pc' pc ->
T <: T' ->
has_type pc' Gamma HT t T'
.
(*###inversion of [has_type]###*)
(*inversion of [has_type pc Gamma HT (tvar x) T]*)
Lemma inversion_tvar: forall pc Gamma HT x T,
has_type pc Gamma HT (tvar x) T ->
exists T0, (Gamma x = Some T0)/\(T0 <: T).
Proof. intros. remember (tvar x) as t. induction H0.
inversion Heqt. subst. exists T. split. apply H0. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x0. split. inversion H3.
apply H4. inversion H3. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tabs x T1 e b) T]*)
Lemma inversion_tabs: forall pc Gamma HT x T1 T e b,
has_type pc Gamma HT (tabs x T1 e b) T ->
exists T1', exists T2, exists T2', exists pc', exists pc'', exists pc''', exists b',
(has_type pc' Gamma HT (tabs x T1 e b) (an (fn T1 pc'' T2) b)) /\
(has_type pc'' (Cupdate Gamma x (Some T1)) HT e T2) /\(subsum_r pc''' pc'')/\(subsum_r pc pc')/\
(T1'<:T1)/\(T2<:T2')/\(subsum_r b b')/\((an (fn T1' pc''' T2') b') <: T).
Proof. intros. remember (tabs x T1 e b) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. subst. exists T1. exists T'. exists T'. exists pc. exists pc'. exists pc'. exists b.
split. apply t_abs with (b:=b)(pc:=pc) in H0. apply H0.
split. apply H0. split. apply sub_refl. split. apply sub_refl. split. apply subtyping_refl. split. apply subtyping_refl. split. apply sub_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x0. inversion H3. exists x1. inversion H4. exists x2.
inversion H5. exists x3. inversion H6. exists x4. inversion H7. exists x5. inversion H8. exists x6. split. apply H9. split. apply H9. split. apply H9. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x3).
apply H1. apply H9. split. apply H9. split. apply H9. split. apply H9.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H9. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tcon n b) T]*)
Lemma inversion_tcon: forall pc Gamma HT T n b,
has_type pc Gamma HT (tcon n b) T ->
exists T', exists T'', exists b',
(T' = an int b)/\(T'' = an int b')/\(subsum_r b b')/\(T'' <: T).
Proof.
intros. remember (tcon n b) as t. induction H0.
inversion Heqt. inversion Heqt. subst. exists (an int b). exists (an int b).
exists b. split. reflexivity. split. reflexivity. split. apply sub_refl.
apply subt_int. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1.
inversion H5. split. apply H6. inversion H7. split. apply H8. inversion H9. split. apply H10.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H11. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tunit b) T]*)
Lemma inversion_tunit:forall pc Gamma HT T b,
has_type pc Gamma HT (tunit b) T ->
exists T', exists T'', exists b',
(T'=an unit b)/\(T''=an unit b')/\(subsum_r b b')/\(T''<:T).
Proof. intros. remember (tunit b) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
subst. exists (an unit b). exists (an unit b). exists b. split. reflexivity. split. reflexivity. split.
apply sub_refl. apply subt_unit. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H5. apply H2. Qed.
(*inversion of [has_type pc Gamma HT (tloc T N b)(an (ref T) b)]*)
Lemma inversion_tloc:forall pc Gamma HT N T1 b T,
has_type pc Gamma HT (tloc T1 N b) T ->
exists n, exists T', exists T'', exists b',
(N = Some n)/\
(heap_Tlookup n HT = Some T1)/\(T'=an (ref T1) b)/\(T''=an (ref T1) b')/\(subsum_r b b')/\(T''<:T).
Proof. intros. remember (tloc T1 N b) as t. induction H0. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. subst. exists n. exists (an (ref T1) b). exists (an (ref T1) b).
exists b. split. reflexivity. split. apply H0. split. reflexivity. split. reflexivity. split. apply sub_refl. apply subtyping_refl. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3. exists x0.
inversion H4. exists x1. inversion H5. exists x2. split. apply H6. split. apply H6. split. apply H6. split. apply H6. split. apply H6. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H6. apply H2. Qed.
(*inversion of [has_type pc Gamma HT (tprot b t) T]*)
Lemma inversion_tprot:forall pc Gamma HT t T b,
has_type pc Gamma HT (tprot b t) T ->
exists T', exists T'', exists pc',
((joinTs T' b) <: T) /\(has_type pc' Gamma HT t T'')/\(subsum_r (joins pc b) pc')/\(T'' <: T').
Proof. intros. remember (tprot b t) as e. induction H0. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst.
exists T. exists T. exists (joins pc b). split. apply subtyping_refl. split. apply H0.
split. apply sub_refl. apply subtyping_refl.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4.
exists x1. split. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H5.
apply H2. split. apply H5. split. destruct pc. destruct pc'. simpl. simpl in H5. apply H5.
inversion H1. simpl in H5. destruct pc'. simpl. destruct b. apply subsum_r_trans with (a:=L)(b:=H)(c:=x1).
apply sub_LH. apply H5. apply H5. simpl. apply H5. apply H5.
Qed.
(*inversion of [has_type pc Gamma HT (tapp t1 t2) T]*)
Lemma inversion_tapp: forall pc Gamma HT t1 t2 T2,
has_type pc Gamma HT (tapp t1 t2) T2 ->
exists T1', exists T2', exists b', exists T1'', exists T1''', exists T2'', exists b'', exists pc', exists sp', exists sp'',
(sp'=joins pc' b')/\has_type pc' Gamma HT t1 (an (fn T1' sp' T2') b')/\((an (fn T1' sp' T2') b')<:(an (fn T1'' sp'' T2'') b''))/\
(has_type pc' Gamma HT t2 T1''')/\(T1''' <: T1'')/\(subsum_r pc pc')/\
((joinTs T2'' b'')<:T2).
Proof. intros. remember (tapp t1 t2) as t. induction H0.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
subst. exists T1. exists T2. exists b. exists T1. exists T1. exists T2. exists b. exists pc. exists (joins pc b). exists (joins pc b). split. reflexivity.
split. apply H0_. split. apply subtyping_refl. split. apply H0_0. split. apply subtyping_refl. split. destruct b. destruct pc. simpl.
apply sub_refl. simpl. apply sub_refl. destruct pc. simpl. apply sub_refl. apply sub_refl. apply subtyping_refl. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. inversion H5. exists x2. inversion H6. exists x3. inversion H7. exists x4.
inversion H8. exists x5. inversion H9. exists x6. inversion H10. exists x7. inversion H11. exists x8. split. apply H12.
split. apply H12. split. apply H12. split. apply H12. split. apply H12. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x6).
apply H1. apply H12. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H12. apply H2. Qed.
(*inversion of [has_type pc Gamma HT (tref T1 t b) T]*)
Lemma inversion_tref:forall pc Gamma HT T1 T t b,
has_type pc Gamma HT (tref T1 t b) T ->
exists pc', exists pc'', exists T1', exists T1'', exists b',
(has_type pc'' Gamma HT (tref T1 t b)(an (ref T1) b))/\
(subsum_r b b')/\(subsum_r pc pc'')/\
((an (ref T1) b')<:T)/\
(has_type pc' Gamma HT t T1')/\(T1' <: T1'')/\(T1''<:T1)/\
(subsum_r (joins pc'' b) pc')/\
(subsum_r (joins pc'' b) (labelT T1')).
Proof. intros. remember (tref T1 t b) as e. induction H0. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. subst. exists (joins pc b). exists pc. exists T1. exists T1.
exists b. split. apply t_ref with (b':=joins pc b). apply H0. reflexivity. apply H2. split. apply sub_refl. split. apply sub_refl.
split. apply subtyping_refl. split. apply H0. split. apply subtyping_refl. split. apply subtyping_refl. split. apply sub_refl. apply H2.
inversion Heqe. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2. inversion H6. exists x3.
split. apply H7. split. apply H7. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x0). apply H1. apply H7. split. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H7. apply H2. apply H7.
Qed.
(*inversion of [has_type pc Gamma HT (tderef t) T]*)
Lemma inversion_tderef:forall pc Gamma HT t T,
has_type pc Gamma HT (tderef t) T ->
exists pc', exists T1, exists b', exists b'',
has_type pc' Gamma HT t (an (ref T1) b')/\(subsum_r b' b'')/\
((joinTs T1 b'')<:T)/\(subsum_r pc pc').
Proof. intros. remember (tderef t) as e. induction H0. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst. exists pc. exists T. exists b. exists b. split. apply H0. split.
apply sub_refl. split. apply subtyping_refl. apply sub_refl. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4. exists x1.
inversion H5. exists x2. split. apply H6. split. apply H6. split. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H6. apply H2. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6. Qed.
(*inversion of [has_type pc Gamma HT (tassign t1 t2) T]*)
Lemma inversion_tassign:forall pc Gamma HT t1 t2 T,
has_type pc Gamma HT (tassign t1 t2) T ->
exists pc',exists T1, exists T1', exists b,
has_type pc' Gamma HT (tassign t1 t2)(an unit (labelT T1))/\
has_type pc' Gamma HT t1 (an (ref T1) b)/\
has_type pc' Gamma HT t2 T1'/\
(T1'<:T1)/\(subsum_r pc pc')/\(subsum_r (joins pc' b)(labelT T1))/\
((an unit (labelT T1))<:T).
Proof. intros. remember (tassign t1 t2) as t. induction H0. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. subst. exists pc.
exists T. exists T. exists b. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1.
apply H0_. apply H0_0. split. apply H0_. split. apply H0_0. split. apply subtyping_refl. split.
apply sub_refl. split. apply H1. apply subtyping_refl. apply IHhas_type in Heqt.
inversion Heqt. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2.
split. apply H6. split. apply H6. split. apply H6. split. apply H6. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6. split. apply H6. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H6. apply H2. Qed.
(*#############################*)
(*######Properties########*)
(**
There are two important type safety properties we want to investigate,
a.Progress
forall Gamma T t t' st,
has_type Gamma t T ->
value t \/ exists t', t / st ==> t' / st
That is well-typed terms never get stuck
b. type preservation
forall Gamma t t' st T,
has_type Gamma t T ->
t / st ==> t' / st ->
has_type Gamma t' T
*)
(*############type preserversion############*)
(*#################auxiliary theorems##########*)
(*##########s_p_t_1##############*)
(*Firstly we use the following proposition to describe free variables*)
Inductive free_var : id -> tm -> Prop :=
| e_tvar : forall x,
free_var x (tvar x)
| e_tprot : forall x b t,
free_var x t ->
free_var x (tprot b t)
| e_tapp1 : forall x e1 e2,
free_var x e1 ->
free_var x (tapp e1 e2)
| e_tapp2 : forall x e1 e2,
free_var x e2 ->
free_var x (tapp e1 e2)
| e_tabs : forall x y e T b,
y <> x ->
free_var x e ->
free_var x (tabs y T e b)
| e_tref :forall x T t b,
free_var x t ->
free_var x (tref T t b)
| e_tderef:forall x t,
free_var x t ->
free_var x (tderef t)
| e_tassign1:forall x t1 t2,
free_var x t1 ->
free_var x (tassign t1 t2)
| e_tassign2:forall x t1 t2,
free_var x t2 ->
free_var x (tassign t1 t2)
.
(*some auxiliary lemmas*)
Theorem beq_id_eq : forall i1 i2,
true = beq_id i1 i2 -> i1 = i2.
Proof.
intros. unfold beq_id in H0. destruct i1. destruct i2. symmetry in H0.
apply beq_nat_true in H0. subst. reflexivity.
Qed.
Theorem not_eq_beq_id_false : forall i1 i2,
i1 <> i2 -> beq_id i1 i2 = false.
Proof.
intros. unfold beq_id. destruct i1. destruct i2. apply beq_nat_false_iff.
intros C. apply H0. subst. reflexivity.
Qed.
Theorem beq_id_refl : forall X,
true = beq_id X X.
Proof.
intros. destruct X.
apply beq_nat_refl. Qed.
(*end*)
(*####any_term_typable_under_empty context is closed####*)
Lemma term_typable_empty_closed_1:forall pc Gamma HT x t T,
free_var x t ->
has_type pc Gamma HT t T ->
exists T',Gamma x = Some T'.
Proof. intros. generalize dependent T. generalize dependent Gamma.
generalize dependent HT. generalize dependent pc.
induction H0.
Case ("tvar").
intros. apply inversion_tvar in H1. inversion H1. inversion H0.
exists x0. apply H2.
Case ("tprot").
intros. apply inversion_tprot in H1. inversion H1. inversion H2.
inversion H3. inversion H4. inversion H6.
apply IHfree_var in H7. inversion H7. exists x3. apply H9.
Case ("tapp1").
intros. apply inversion_tapp in H1. inversion H1. inversion H2.
inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H10. inversion H11. inversion H13.
apply IHfree_var in H14. inversion H14. exists x10.
apply H16.
Case ("tapp2").
intros. apply inversion_tapp in H1. inversion H1. inversion H2.
inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H10. inversion H11. inversion H13.
inversion H15. inversion H17.
apply IHfree_var in H18. inversion H18. exists x10. apply H20.
Case ("tabs").
intros. apply inversion_tabs in H2. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11.
apply IHfree_var in H12. inversion H12.
apply not_eq_beq_id_false in H0. apply Cupdate_neq with (T:=Some T)(St:=Gamma)in H0.
rewrite->H0 in H14. exists x7. apply H14.
Case ("tref").
intros. apply inversion_tref in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H8. inversion H10. inversion H12. inversion H14.
apply IHfree_var in H15. apply H15.
Case ("tderef").
intros. apply inversion_tderef in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. apply IHfree_var in H6. inversion H6. exists x4. apply H8.
Case ("tassign1").
intros. apply inversion_tassign in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H7. apply IHfree_var in H8. inversion H8. exists x4. apply H10.
Case ("tassign2").
intros. apply inversion_tassign in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H7. inversion H9. apply IHfree_var in H10. inversion H10. exists x4.
apply H12.
Qed.
Corollary term_typable_empty_closed: forall t pc HT T,
has_type pc empty_context HT t T ->
forall x, ~free_var x t.
Proof. intros t. induction t.
Case ("tvar").
intros. apply inversion_tvar in H0. inversion H0. inversion H1.
inversion H2.
Case ("tprot").
intros. apply inversion_tprot in H0. inversion H0. inversion H1. inversion H2.
inversion H3. inversion H5. apply IHt with (x:=x)in H6.
intros contra. inversion contra. subst. apply H6 in H10. inversion H10.
Case ("tcon").
intros. intros contra. inversion contra.
Case ("tabs").
intros. apply inversion_tabs in H0. inversion H0. inversion H1. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H6. inversion H7. inversion H9.
intros contra. inversion contra. subst.
apply term_typable_empty_closed_1 with (T:=x1)(Gamma:=Cupdate empty_context i (Some t))(pc:=x4)(HT:=HT)in H18.
inversion H18. apply not_eq_beq_id_false in H15. apply Cupdate_neq with (T:=Some t)(St:=empty_context)in H15.
rewrite->H15 in H12. inversion H12. apply H10.
Case ("tapp").
intros. apply inversion_tapp in H0. inversion H0. inversion H1. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H6. inversion H7. inversion H8. inversion H9.
inversion H10. inversion H12. inversion H14. inversion H16.
apply IHt1 with (x:=x)in H13. apply IHt2 with(x:=x) in H17. intros contra. inversion contra.
subst. apply H13 in H21. inversion H21. apply H17 in H21. inversion H21.
Case ("tunit").
intros. intros contra. inversion contra.
Case ("tref").
intros. apply inversion_tref in H0. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. inversion H11. inversion H13. apply IHt with (x:=x)in H14. intros contra. inversion contra. apply H14 in H18.
inversion H18.
Case ("tderef").
intros. apply inversion_tderef in H0. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. apply IHt with(x:=x) in H5.
intros contra. inversion contra. apply H5 in H9. inversion H9.
Case ("tloc").
intros. intros contra. inversion contra.
Case ("tassign").
intros. apply inversion_tassign in H0. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6. inversion H8.
apply IHt1 with (x:=x) in H7. apply IHt2 with (x:=x) in H9. intros contra. inversion contra. subst. apply H7 in H13. inversion H13.
apply H9 in H13. inversion H13.
Qed.
Corollary change_context: forall pc Gamma Gamma' HT t T,
has_type pc Gamma HT t T ->
(forall x, free_var x t -> Gamma x = Gamma' x) ->
has_type pc Gamma' HT t T.
Proof.
intros. generalize dependent Gamma'. induction H0.
Case ("t_var").
intros. apply t_var. rewrite<-H0. symmetry. apply H1.
apply e_tvar.
Case ("t_con").
intros. apply t_con.
Case ("tunit").
intros. apply t_unit.
Case ("tloc").
intros. apply t_loc. apply H0.
Case ("t_abs").
intros. apply t_abs. apply IHhas_type. intros. remember (beq_id x x0) as BB.
destruct BB. apply beq_id_eq in HeqBB. rewrite->HeqBB. rewrite->Cupdate_eq.
rewrite->Cupdate_eq. reflexivity. inversion HeqBB. symmetry in H4.
apply Cupdate_neq with (T:=Some T)(St:=Gamma) in H4. rewrite->H4.
inversion HeqBB. symmetry in H5. apply Cupdate_neq with (T:=Some T)(St:=Gamma') in H5.
rewrite->H5. clear H4. clear H5. apply H1. apply e_tabs. intros contra. rewrite->contra in HeqBB.
rewrite<-beq_id_refl in HeqBB. inversion HeqBB. apply H2.
Case ("t_prot").
intros. apply t_prot with (T:=T). apply IHhas_type. intros. apply H2.
apply e_tprot. apply H3. apply H1.
Case ("t_app").
intros. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply IHhas_type1. intros. apply H1. apply e_tapp1.
apply H2. apply IHhas_type2. intros. apply H1. apply e_tapp2. apply H2.
apply H0.
Case ("t_tref").
intros. apply t_ref with (b':=joins pc b). apply IHhas_type. intros. apply H3. apply e_tref. apply H4. reflexivity. subst.
apply H2.
Case ("t_deref").
intros. apply t_deref with (T:=T)(b:=b). apply IHhas_type. intros. apply H2. apply e_tderef. apply H3.
apply H1.
Case ("t_assign").
intros. apply t_assign with (b:=b)(T:=T). apply H0. apply H1. apply IHhas_type1. intros. apply H2.
apply e_tassign1. apply H3. apply IHhas_type2. intros. apply H2. apply e_tassign2. apply H3.
Case ("t_sub").
intros. apply t_sub with(pc:=pc) (T:=T). apply IHhas_type. apply H3. apply H1.
apply H2.
Qed.
Theorem s_p_t_1: forall t pc Gamma HT T,
has_type pc empty_context HT t T ->
has_type pc Gamma HT t T.
Proof. intros. apply change_context with (Gamma':=Gamma)in H0.
apply H0. intros. apply term_typable_empty_closed with (x:=x)in H0.
apply H0 in H1. inversion H1.
Qed.
(*################s_p_t_1################*)
(**
Recall that in [step], we specify that substitution can only take place if
the second argument of the application is reduced to be a value which is
closed and typable under both high and low security context.
In the following Theorem, we assume that the term used to replace bounded
variables is value.
*)
Lemma value_pc:forall pc pc' Gamma HT v T,
value v ->
has_type pc Gamma HT v T ->
has_type pc' Gamma HT v T.
Proof. intros. generalize dependent pc'. induction H1.
Case("tvar").
inversion H0.
Case("tcon").
intros. apply t_con.
Case("tunit").
intros. apply t_unit.
Case("tloc").
intros. apply t_loc. apply H1.
Case("tabs").
intros. apply t_abs. apply H1.
Case("tprot").
inversion H0.
Case("tapp").
inversion H0.
Case("tref").
inversion H0.
Case("tderef").
inversion H0.
Case("tassign").
inversion H0.
Case("sub").
intros. apply t_sub with (pc:=pc'0)(T:=T). apply IHhas_type. apply H0.
apply sub_refl. apply H3.
Qed.
Theorem substitution_preserves_typing: forall pc Gamma HT x v2 T1 T2 e,
value v2 ->
has_type pc empty_context HT v2 T1 ->
has_type pc (Cupdate Gamma x (Some T1)) HT e T2 ->
has_type pc Gamma HT ([x := v2]e) T2.
Proof. intros. generalize dependent pc. generalize dependent HT.
generalize dependent Gamma. generalize dependent x.
generalize dependent v2. generalize dependent T1. generalize dependent
T2. induction e.
Case ("tvar").
intros. apply inversion_tvar in H2. inversion H2. inversion H3.
remember (beq_id x i) as BB.
destruct BB. apply beq_id_eq in HeqBB. rewrite->HeqBB in H4.
rewrite->Cupdate_eq in H4. inversion H4. subst. simpl. rewrite<-beq_id_refl.
apply s_p_t_1. apply t_sub with (pc:=pc)(T:=x0). apply H1. apply sub_refl. apply H5.
symmetry in HeqBB. simpl. rewrite->HeqBB. destruct i. apply t_sub with (pc:=pc)(T:=x0).
apply t_var. apply Cupdate_neq with (T:=Some T1)(St:=Gamma)in HeqBB.
rewrite->HeqBB in H4. apply H4. apply sub_refl. apply H5.
Case ("tprot").
intros. simpl. apply inversion_tprot in H2. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H7. apply t_sub with (pc:=pc)(T:=joinTs x0 s). apply t_prot with (T:=x0) . apply IHe with (T1:=T1).
apply H0. apply value_pc with (pc:=pc). apply H0. apply H1.
subst. apply t_sub with (pc:=x2)(T:=x1). apply H8. apply H9. apply H9. reflexivity. apply sub_refl. apply H6.
Case ("tcon").
intros. simpl. apply inversion_tcon in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. subst. destruct T2. destruct r. inversion H11. subst. apply t_sub with (pc:=pc)(T:=an int s). apply t_con.
apply sub_refl. apply subt_int. apply subsum_r_trans with (a:=s)(b:=x2)(c:=s0). apply H10. apply H12. inversion H11.
inversion H11. inversion H11.
Case ("tabs").
intros. simpl. remember (beq_id x i) as BB. destruct BB. apply inversion_tabs in H2.
inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H11. inversion H13. inversion H15. inversion H17.
inversion H19. inversion H21. destruct T2. destruct r. inversion H23. apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) x6).
apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) s). apply t_sub with (pc:=pc)(T:=an (fn x0 s1 t1) s). apply t_sub with (pc:=pc)(T:=an (fn t s1 t1) s).
apply t_sub with (pc:=pc)(T:=an (fn t x5 t1) s). apply t_sub with (pc:=pc)(T:=an (fn t x4 t1) s).
apply t_abs. apply t_sub with (pc:=x4)(T:=x2). apply t_sub with (pc:=x4)(T:=x1). apply beq_id_eq in HeqBB. rewrite->HeqBB in H12.
assert (Cupdate Gamma i (Some t) = Cupdate (Cupdate Gamma i (Some T1)) i (Some t)).
apply functional_extensionality. intros. remember (beq_id i x7) as CC. destruct CC.
apply beq_id_eq in HeqCC. rewrite->HeqCC. rewrite->Cupdate_eq.
rewrite->Cupdate_eq. reflexivity. symmetry in HeqCC. inversion HeqCC. inversion HeqCC.
apply Cupdate_neq with (T:= Some t)(St:=Gamma ) in HeqCC. rewrite->HeqCC.
apply Cupdate_neq with (T:= Some t)(St:=Cupdate Gamma i (Some T1)) in H25.
rewrite->H25. apply Cupdate_neq with (T:=Some T1)(St:=Gamma) in H26. rewrite->H26.
reflexivity. rewrite->H24. apply H12. apply sub_refl. apply H20. apply sub_refl. inversion H23. apply H35.
apply sub_refl. apply subt_fn. apply sub_refl. apply H14. apply subtyping_refl. apply subtyping_refl.
apply sub_refl. apply subt_fn. apply sub_refl. inversion H23. apply H33. apply subtyping_refl. apply subtyping_refl.
apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply H18. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply sub_refl. apply sub_refl. inversion H23. apply H34. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply H22. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn.
inversion H23. apply H29. apply sub_refl. apply subtyping_refl. apply subtyping_refl. inversion H23. inversion H23.
apply inversion_tabs in H2. inversion H2. inversion H3. inversion H4. inversion H5.
inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. inversion H13. inversion H15.
inversion H17. inversion H19. inversion H21. destruct T2. destruct r. inversion H23.
apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) x6). apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) s).
apply t_sub with (pc:=pc)(T:=an (fn x0 s1 t1) s). apply t_sub with (pc:=pc)(T:=an (fn t s1 t1) s).
apply t_abs. apply IHe with (T1:=T1). apply H0. apply value_pc with (pc:=pc). apply H0. apply H1.
apply t_sub with (pc:=s1)(T:=x2). apply t_sub with (pc:=s1)(T:=x1). apply t_sub with (pc:=x5)(T:=x1).
apply t_sub with (pc:=x4)(T:=x1).
assert (Cupdate (Cupdate Gamma x (Some T1)) i (Some t) = Cupdate (Cupdate Gamma i (Some t)) x (Some T1)).
apply functional_extensionality. intros. remember (beq_id x x7) as AA.
remember (beq_id i x7) as BB. destruct AA. destruct BB. apply beq_id_eq in HeqAA.
apply beq_id_eq in HeqBB0. rewrite->HeqAA in HeqBB. rewrite->HeqBB0 in HeqBB.
rewrite<-beq_id_refl in HeqBB. inversion HeqBB. apply beq_id_eq in HeqAA. rewrite->HeqAA.
rewrite->Cupdate_eq. rewrite->HeqAA in HeqBB. symmetry in HeqBB. apply Cupdate_permute with (T1:=Some T1)(T2:=Some t)(X3:=x7)(f:=Gamma) in HeqBB.
rewrite->HeqBB. rewrite->Cupdate_eq. reflexivity. destruct BB. apply beq_id_eq in HeqBB0. rewrite->HeqBB0. rewrite->Cupdate_eq.
symmetry in HeqAA. apply Cupdate_permute with (T1:=Some T1)(T2:=Some t)(X3:=x7)(f:=Gamma) in HeqAA.
rewrite<-HeqAA. rewrite->Cupdate_eq. reflexivity. symmetry in HeqBB0. inversion HeqBB0.
apply Cupdate_neq with (T:=Some t)(St:=Cupdate Gamma x (Some T1))in HeqBB0.
rewrite->HeqBB0. symmetry in HeqAA. inversion HeqAA.
apply Cupdate_neq with (T:=Some T1)(St:=Gamma) in HeqAA.
rewrite->HeqAA. apply Cupdate_neq with (T:=Some T1)(St:=Cupdate Gamma i (Some t)) in H26.
rewrite->H26. apply Cupdate_neq with (T:=Some t)(St:=Gamma) in H25. rewrite->H25. reflexivity.
rewrite<-H24. apply H12.
apply H14. apply subtyping_refl. inversion H23. inversion H33. apply sub_refl. apply sub_LH.
apply subtyping_refl. apply sub_refl. apply H20. apply sub_refl. inversion H23. apply H35.
apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
apply H18. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
inversion H23. apply H34. apply subtyping_refl. apply sub_refl. apply subt_fn. apply H22. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn. inversion H23. apply H29. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. inversion H23. inversion H23.
Case ("tapp").
intros. simpl. apply inversion_tapp in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6.
inversion H7. inversion H8. inversion H9. inversion H10. inversion H11. inversion H12. inversion H14. inversion H16.
inversion H18.
apply t_sub with (pc:=pc)(T:=joinTs x5 x2).
apply t_app with (T1:=x4)(T2:=x5)(b:=x2).
apply IHe1 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x7)(T:= an (fn x4 (joins pc x2) x5) x2).
apply t_sub with (pc:=x7)(T:=an (fn x3 (joins pc x2) x5) x2). apply t_sub with (pc:=x7)(T:=an (fn x0(joins pc x2)x5)x2).
apply t_sub with (pc:=x7)(T:=an (fn x0 x8 x5) x2). apply t_sub with (pc:=x7)(T:=an (fn x0 x8 x1) x2).
apply H15. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply subtyping_refl. inversion H17. apply H32.
apply sub_refl. apply subt_fn. apply sub_refl. assert (subsum_r (joins pc x2) x8). rewrite->H13. destruct pc. destruct x7.
simpl. apply sub_refl. simpl. destruct x2. apply sub_LH. apply sub_refl. destruct x7. inversion H20. inversion H22. inversion H23.
simpl. apply sub_refl. apply H21. apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
inversion H17. apply H31. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply H20. apply subtyping_refl.
apply H20. apply subtyping_refl.
apply IHe2 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x7)(T:=x4). apply H19. inversion H20. apply H22.
apply subtyping_refl. reflexivity. apply sub_refl. assert (joinTs x5 x2 <: T2). apply subtyping_trans with (x:=joinTs x5 x6)(y:=joinTs x5 x6).
apply subtyping_refl. destruct x2. destruct x6. apply subtyping_refl. destruct x5. simpl. destruct r. apply subt_int. destruct s. apply sub_LH.
apply sub_refl. apply subt_fn. destruct s. apply sub_LH. apply sub_refl. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply subt_unit.
destruct s. apply sub_LH. apply sub_refl. apply subt_ref. destruct s. apply sub_LH. apply sub_refl. destruct x6. inversion H17. inversion H26. apply subtyping_refl.
apply H20. apply H21.
Case ("tunit").
intros. simpl. apply inversion_tunit in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. subst. destruct T2. destruct r. inversion H11. inversion H11. apply t_sub with (pc:=pc)(T:=an unit x2).
apply t_sub with (pc:=pc)(T:=an unit s). apply t_unit. apply sub_refl. apply subt_unit. apply H9. apply sub_refl. apply H11. inversion H11.
Case ("tref").
intros. simpl. apply inversion_tref in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H9. inversion H11. inversion H13. destruct T2. destruct r. inversion H14. inversion H14. inversion H14. apply t_sub with (pc:=pc)(T:=an (ref t0) x4).
apply t_sub with (pc:=pc)(T:=an (ref t0) s). inversion H14. subst. apply t_ref with (b':=joins pc s). apply IHe with (T1:=T1).
apply H0. apply value_pc with (pc:=pc). apply H0. apply H1. apply t_sub with (pc:=joins x1 s)(T:=x3). apply t_sub with (pc:=x0)(T:=x2). apply H15. apply H13.
apply H15. destruct pc. destruct x1. destruct s. apply sub_refl. apply sub_refl. destruct s. apply sub_LH. apply sub_refl. destruct x1. inversion H12. apply sub_refl.
apply H15. reflexivity. apply subsum_r_trans with (a:=joins pc s)(b:=joins x1 s)(c:=labelT t0). destruct pc. destruct x1. destruct s. apply sub_refl. apply sub_refl.
destruct s. apply sub_LH. apply sub_refl. destruct x1. inversion H12. apply sub_refl. apply subsum_r_trans with (a:=joins x1 s)(b:=labelT x2)(c:=labelT t0).
apply H15. apply subsum_r_trans with (a:=labelT x2)(b:=labelT x3)(c:=labelT t0). inversion H15. inversion H18. destruct x2. destruct x3. inversion H19. simpl. apply H22.
simpl. apply H25. simpl. apply H22. simpl. apply H22. inversion H15. inversion H18. inversion H20. destruct x3. destruct t0. inversion H21. simpl. apply H24. simpl. apply H27.
simpl. apply H24. simpl. apply H24. apply sub_refl. apply subt_ref. apply H10. apply sub_refl. apply subt_ref. inversion H14. apply H17.
Case ("tderef").
intros. simpl. apply inversion_tderef in H2. inversion H2. inversion H3. inversion H4. inversion H5.
apply t_sub with (pc:=pc)(T:=joinTs x1 x3).
apply t_deref with (T:=x1)(b:=x3). apply IHe with (T1:=T1).
apply H0. apply H1. apply t_sub with (pc:=x0)(T:=an (ref x1) x3). apply t_sub with (pc:=x0)(T:=an (ref x1) x2).
apply H6. apply sub_refl. apply subt_ref. apply H6. apply H6. apply subtyping_refl. reflexivity. apply sub_refl.
apply H6.
Case ("tloc").
intros. simpl. destruct o. apply inversion_tloc in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6.
inversion H8. inversion H10. inversion H12. inversion H14. subst. apply t_sub with (pc:=pc)(T:=an (ref t) x3). apply t_sub with (pc:=pc)(T:=an (ref t) s).
apply t_loc. inversion H7. subst. apply H6. apply sub_refl. apply subt_ref. apply H15. apply sub_refl. apply H6. apply inversion_tloc in H2. inversion H2.
inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
Case ("tassign").
intros. simpl. apply inversion_tassign in H2. inversion H2. inversion H3. inversion H4. inversion H5. apply t_sub with (pc:=pc)(T:=an unit (labelT x1)).
apply t_assign with (b:=x3)(T:=x1). reflexivity. apply subsum_r_trans with (a:=joins pc x3)(b:=joins x0 x3)(c:=labelT x1). destruct pc. destruct x0.
simpl. apply sub_refl. simpl. destruct x3. apply sub_LH. apply sub_refl. destruct x0. inversion H6. inversion H8. inversion H10. inversion H12. inversion H14.
inversion H15. simpl. apply sub_refl. apply H6. apply IHe1 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x0)(T:=an (ref x1) x3). apply H6.
apply H6. apply subtyping_refl. apply IHe2 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x0)(T:=x2). apply H6. apply H6. apply H6. apply sub_refl.
apply H6.
Qed.
(*heap_well_typed*)
Definition heap_well_typed (HT:heap_Ty) (hp:heap) :=
length HT = length hp /\
(*every value on the heap must be well-formed*)
(heap_well_formed hp (length hp))/\
(forall pc l, l < length hp ->
(*two additional constraints*)
(value (efst (heap_lookup l hp)))/\
extract (heap_Tlookup l HT) <: esnd (heap_lookup l hp) /\
subsum_r (labelT (esnd (heap_lookup l hp))) (label(efst (heap_lookup l hp))) /\
has_type pc empty_context HT (efst(heap_lookup l hp)) (extract (heap_Tlookup l HT))).
(**
Note the reason for having the additional constraint which requires for a well_typed a heap
typing is that the type on the heap subsums the corresponding typing in the heap typing.
Consider the following example which illustrates a well-typed stuck configuration,
has_type H empty_context [an int H] (tassign (tloc (an int H) 0 L)(tcon 1 L)) (an unit H)
with [(tcon 0 L,an int L)] as hp we have,
heap_well_typed [an int H] [(tcon 0 L,an int L)] for
a. has_type pc empty_context [an int H] (tcon 0 L)(an int H)
b. the label of the type on the heap is guarded by that of its type
c. they have the same length
Now,according to [progress] and set [PC=H] we should have,
exists p, tassign (tloc (an int H) 0 L)(tcon 1 L) / (tcon 0 L,an int L)
==H=> p
and according to [st_assign],we acctually have,
stuck_term (tassign (tloc (an int H) 0 L)(tcon 1 L)) [(tcon 0 L,an int L)] H.
Qed.
*)
(*Some instances of consistent heap typing [HT] w.r.t. some heap [hp]*)
Example test_heap_well_typed_1:
heap_well_typed (an int L :: an unit H :: an (fn (an int L) H (an int L)) L :: an (ref (an int L)) H :: nil)
((tcon 0 L,an int L) :: (tunit H,an unit H) :: (tabs (Id 0)(an int L)(tcon 0 L) L,an (fn (an int L) H (an int L)) L) :: (tloc (an int L) (Some 0) H,an (ref (an int L)) H) :: nil).
Proof. split. simpl. reflexivity. split. apply one_hwf. apply one_hwf. apply one_hwf. apply one_hwf. apply nil_hwf.
simpl. apply wf_tloc. apply le_S. apply le_S. apply le_S. apply le_n.
simpl. apply wf_tabs. apply wf_tcon. simpl. apply wf_tunit. simpl. apply wf_tcon.
split.
simpl in H0. inversion H0. simpl. apply v_l. inversion H2. simpl. apply v_f. inversion H4. simpl. apply v_u. inversion H6. simpl. apply v_c. inversion H8.
split. simpl in H0. inversion H0. simpl. apply subtyping_refl. inversion H2. simpl. apply subtyping_refl. inversion H4. simpl. apply subtyping_refl.
inversion H6. simpl. apply subtyping_refl. inversion H8.
split. simpl in H0. inversion H0. simpl. apply sub_refl. inversion H2. simpl. apply sub_refl. inversion H4. simpl. apply sub_refl.
inversion H6. simpl. apply sub_refl. inversion H8.
simpl in H0. inversion H0. simpl. apply t_loc. simpl. reflexivity. inversion H2. simpl. apply t_abs. apply t_con. inversion H4. simpl. apply t_unit. inversion H6. simpl.
apply t_con. inversion H8.
Qed.
Example test_heap_well_typed_2:
~heap_well_typed (an int L :: an unit H :: an (ref (an int L)) L :: nil)
((tcon 1 L,an int L) :: (tunit H,an unit H) :: nil).
Proof. intros contra. inversion contra. inversion H0. Qed.
Example test_heap_well_typed_3:
~heap_well_typed (an int L :: nil)
((tcon 0 H,an int H) :: nil).
Proof. intros contra. inversion contra. inversion H1. specialize (H3 H 0). simpl in H3.
assert (0 < 1). apply le_n. apply H3 in H4. inversion H4. inversion H6. inversion H8.
apply inversion_tcon in H10.
inversion H10. inversion H11. inversion H12. inversion H13. inversion H15.
inversion H17. subst. destruct x1. inversion H18. inversion H19. inversion H20.
Qed.
(*continue from here*)
Example test_heap_well_typed_4:
~heap_well_typed (an int L :: an unit H :: (an (ref (an int L)) L) :: nil)
((tcon 1 L,an int L) :: (tunit L,an unit H) :: (tloc (an int L) (Some 0) L,an (ref (an int L)) L) :: nil).
Proof. intros contra. inversion contra. inversion H1. specialize (H3 L 1). simpl in H3. assert (1<3). apply le_S. apply le_n. apply H3 in H4.
inversion H4. inversion H6. inversion H8. inversion H9.
Qed.
Example test_heap_well_typed_5:
~heap_well_typed ((an int H) :: nil)((tcon 0 L,an int L) :: nil).
Proof. intros contra. inversion contra. inversion H1. specialize (H3 L 0). simpl in H3. assert (0<1). apply le_n. apply H3 in H4.
inversion H4. inversion H6. inversion H7. inversion H11.
Qed.
(*heap extends*)
Inductive extends : heap_Ty -> heap_Ty -> Prop :=
| extends_nil : forall HT',
extends HT' nil
| extends_cons : forall x HT' HT,
extends HT' HT ->
extends (x::HT') (x::HT).
(*lemmas about extended contexts*)
Lemma zero_n:forall n,
0<=n.
Proof. intros. induction n. apply le_n. apply le_S.
apply IHn. Qed.
Lemma n_iff_Sn_left: forall n m,
n <= m -> S n <= S m.
Proof.
intros. induction H0. apply le_n. apply le_S. apply IHle.
Qed.
Lemma n_iff_Sn_right : forall n m,
S n <= S m -> n <= m.
Proof. intros. generalize dependent n. induction m.
intros. destruct n. apply le_n. inversion H0. inversion H2.
intros. inversion H0. apply le_n. apply le_S. apply IHm in H2.
apply H2. Qed.
Theorem n_iff_Sn : forall n m,
n <= m <-> S n <= S m.
Proof.
intros. split.
Case ("->"). apply n_iff_Sn_left.
Case ("<-"). apply n_iff_Sn_right.
Qed.
Lemma extends_lookup_last:forall hp p,
heap_lookup (length hp)(snoc hp p) = Some p.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("hd::t"). intros. simpl. apply IHhp.
Qed.
Lemma extends_Tlookup_last:forall HT T,
heap_Tlookup (length HT)(snoc HT T) = Some T.
Proof. intros HT. induction HT.
Case ("nil"). intros. simpl. reflexivity.
Case ("hd::t"). intros. simpl. apply IHHT.
Qed.
Lemma extends_lookup:forall l hp p,
l < length hp ->
heap_lookup l hp = heap_lookup l (snoc hp p).
Proof.
intros. generalize dependent hp. generalize dependent p. induction l.
intros. destruct hp. simpl in H0. inversion H0. simpl. reflexivity.
intros. destruct hp. simpl in H0. inversion H0. simpl in H0. unfold lt in H0.
apply n_iff_Sn_right in H0. simpl. apply IHl. unfold lt. apply H0. Qed.
Lemma extends_Tlookup:forall l HT HT',
l < length HT ->
extends HT' HT ->
heap_Tlookup l HT' = heap_Tlookup l HT.
Proof.
intros. generalize dependent l. induction H1.
Case ("extends_nil"). intros. destruct l. simpl in H0. inversion H0. simpl in H0.
inversion H0.
Case ("extends_cons"). intros. destruct l. reflexivity. apply IHextends. simpl in H0.
unfold lt in H0. unfold lt. apply n_iff_Sn in H0.
apply H0.
Qed.
Lemma length_extends:forall l HT HT',
l < length HT ->
extends HT' HT ->
l < length HT'.
Proof.
intros. generalize dependent l. induction H1.
intros. destruct l. unfold lt in H0. inversion H0. inversion H0.
intros. destruct l. admit. unfold lt. simpl. apply n_iff_Sn_left.
apply IHextends. simpl in H0. apply n_iff_Sn_right in H0. apply H0.
Qed.
Lemma extends_snoc: forall HT T,
extends (snoc HT T) HT.
Proof.
intros. generalize dependent T. induction HT.
intros. simpl. apply extends_nil.
intros. simpl. apply extends_cons. specialize (IHHT T). apply IHHT.
Qed.
Lemma extends_refl: forall HT,
extends HT HT.
Proof.
intros. induction HT. apply extends_nil. apply extends_cons.
apply IHHT. Qed.
Lemma extends_trans:forall HT HT' HT'',
extends HT' HT ->
extends HT'' HT' ->
extends HT'' HT.
Proof. intros. generalize dependent HT''. induction H0.
Case ("extends_nil"). intros. apply extends_nil.
Case ("extends_cons"). intros. destruct HT''. inversion H1. inversion H1.
apply extends_cons. apply IHextends. apply H3.
Qed.
Lemma change_HT':forall HT n T,
heap_Tlookup n HT = Some T ->
n < length HT.
Proof. intros. generalize dependent HT. generalize dependent T.
induction n. intros. destruct HT. simpl in H0. inversion H0. simpl.
apply n_iff_Sn_left. apply zero_n.
intros. destruct HT. simpl in H0. inversion H0. simpl in H0. apply IHn in H0.
unfold lt in H0. unfold lt. simpl. apply n_iff_Sn_left. apply H0. Qed.
Lemma change_HT: forall HT HT' pc Gamma t T,
extends HT' HT ->
has_type pc Gamma HT t T ->
has_type pc Gamma HT' t T.
Proof. intros. generalize dependent HT'. induction H1.
Case ("t_var"). intros. apply t_var. apply H0.
Case ("t_con"). intros. apply t_con.
Case ("t_unit"). intros. apply t_unit.
Case ("t_loc"). intros. apply t_loc. rewrite<-H0. apply extends_Tlookup.
apply change_HT' with (T:=T). apply H0. apply H1.
Case ("t_tabs"). intros. apply t_abs. apply IHhas_type. apply H0.
Case ("t_prot"). intros. subst. apply t_prot with (T:=T). apply IHhas_type. apply H2.
reflexivity.
Case ("t_app"). intros. subst. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply IHhas_type1. apply H1.
apply IHhas_type2. apply H1. reflexivity.
Case ("t_ref"). intros. apply t_ref with(b':=joins pc b). apply IHhas_type. apply H3. reflexivity. subst. apply H2.
Case ("t_deref"). intros. subst. apply t_deref with (T:=T)(b:=b). apply IHhas_type. apply H2. reflexivity.
Case ("t_assign"). intros. apply t_assign with (b:=b)(T:=T). apply H0. apply H1. apply IHhas_type1. apply H2.
apply IHhas_type2. apply H2.
Case ("t_sub"). intros. apply IHhas_type in H3. apply t_sub with (pc:=pc)(T:=T). apply H3. apply H0. apply H2.
Qed.
(*#######################end###################*)
(*preservation*)
(*some auxiliary lemmas*)
Lemma joins_refl:forall a b,
joins a b = joins b a.
Proof. intros. destruct a. destruct b. reflexivity.
reflexivity. destruct b. reflexivity. reflexivity.
Qed.
Lemma joins_subsum:forall a b,
subsum_r a b ->
joins a b = b.
Proof. intros. destruct a. destruct b. reflexivity. reflexivity.
destruct b. inversion H0. reflexivity.
Qed.
Lemma subsum_guard:forall a b,
subsum_r a (joins a b).
Proof. destruct a. destruct b. apply sub_refl. apply sub_LH. destruct b.
apply sub_refl. apply sub_refl. Qed.
Lemma joins_b:forall s1 s2 b,
subsum_r s1 s2 ->
subsum_r (joins s1 b)(joins s2 b).
Proof. intros. destruct s1. destruct s2. destruct b.
simpl. apply sub_refl. simpl. apply sub_refl. destruct b. simpl. apply sub_LH.
simpl. apply sub_refl. destruct b. destruct s2. inversion H0. simpl. apply H0.
destruct s2. inversion H0. simpl. apply sub_refl. Qed.
Lemma subsum_joins:forall a b c,
subsum_r a c ->
subsum_r b c ->
subsum_r (joins a b) c.
Proof. intros. destruct a. destruct b. destruct c.
simpl. apply sub_refl. simpl. apply sub_LH. destruct c. inversion H1. simpl. apply sub_refl.
destruct c. inversion H0. destruct b. simpl. apply sub_refl. simpl. apply sub_refl.
Qed.
Lemma subsum_equal:forall a b,
subsum_r a b ->
subsum_r b a ->
a = b.
Proof. intros. destruct a. destruct b. reflexivity. inversion H1. destruct b. inversion H0. reflexivity.
Qed.
Lemma subsum_low:forall a,
subsum_r a L ->
a = L.
Proof. intros. destruct a. reflexivity. inversion H0.
Qed.
Lemma joinTs_b:forall r s b,
joinTs (an r s) b = an r (joins s b).
Proof. intros. destruct s. destruct b. simpl. reflexivity.
simpl. reflexivity. simpl. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tcon_b:forall n s b,
joinvs (tcon n s) b = tcon n (joins s b).
Proof. intros. destruct b. destruct s. simpl. reflexivity. simpl. reflexivity.
destruct s. simpl. reflexivity. simpl. reflexivity.
Qed.
Lemma join_tabs_b:forall n T e s b,
joinvs (tabs (Id n) T e s) b = tabs (Id n) T e (joins s b).
Proof. destruct s. destruct b. simpl. reflexivity. simpl. reflexivity.
intros. destruct b. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma join_tunit_b:forall s b,
joinvs (tunit s) b = tunit (joins s b).
Proof. intros. destruct s. destruct b. simpl. reflexivity. simpl. reflexivity.
destruct b. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma join_tloc_b:forall T N s b,
joinvs (tloc T N s) b = tloc T N (joins s b).
Proof. intros. destruct s. destruct b. simpl. reflexivity. simpl. reflexivity.
destruct b. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma join_tcon_H:forall n b,
joinvs (tcon n H) b = tcon n H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tabs_H:forall x T e b,
joinvs (tabs x T e H) b = tabs x T e H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tunit_H:forall b,
joinvs (tunit H) b = tunit H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tloc_H:forall T N b,
joinvs (tloc T N H) b = tloc T N H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma label_joinvs:forall t a,
value t ->
label (joinvs t a) = joins (label t) a.
Proof. intros. inversion H0. rewrite->join_tcon_b. reflexivity. rewrite->join_tabs_b. simpl.
reflexivity. rewrite->join_tunit_b. reflexivity. rewrite->join_tloc_b. reflexivity.
Qed.
Lemma joinTs_same:forall T,
joinTs T (labelT T) = T.
Proof. intros. destruct T. simpl. destruct s. reflexivity. reflexivity.
Qed.
Lemma sub_T_b:forall a b r,
subsum_r a b ->
an r a <: an r b.
Proof. intros. destruct r. apply subt_int. apply H0. apply subt_fn. apply H0. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. apply subt_unit. apply H0. apply subt_ref. apply H0.
Qed.
Lemma joinTs_subtyping_s:forall T b' b,
subsum_r b' b ->
joinTs T b' <: joinTs T b.
Proof. intros. inversion H0. apply subtyping_refl. destruct T. simpl.
destruct r. destruct s. apply subt_int. apply sub_LH. apply subtyping_refl.
destruct s. apply subt_fn. apply sub_LH. apply sub_refl. apply subtyping_refl.
apply subtyping_refl. apply subtyping_refl. apply subt_unit. destruct s. apply sub_LH.
apply sub_refl. apply subt_ref. destruct s. apply sub_LH. apply sub_refl.
Qed.
Lemma joinTs_subtyping_T:forall T1 T2 b,
T1 <: T2 ->
joinTs T1 b <: joinTs T2 b.
Proof. intros. destruct T1. destruct T2. rewrite->joinTs_b. rewrite->joinTs_b.
inversion H0. subst. apply subt_int. apply joins_b. apply H2. subst. apply subt_fn.
apply joins_b. apply H5. apply H6. apply H7. apply H8. subst. apply subt_unit.
apply joins_b. apply H2. subst. apply subt_ref. apply joins_b. apply H2. Qed.
Lemma subtyping_subsum:forall T1 T2,
T1 <: T2 ->
subsum_r (labelT T1)(labelT T2).
Proof. intros. inversion H0. subst. simpl. apply H1. subst. simpl. apply H1.
subst. simpl. apply H1. subst. simpl. apply H1.
Qed.
Lemma joins_subtyping_1:forall s1 s1' s2,
subsum_r s1 s1' ->
subsum_r (joins s1 s2)(joins s1' s2).
Proof. intros. destruct s1. destruct s1'. destruct s2. simpl. apply sub_refl.
simpl. apply sub_refl. simpl. destruct s2. apply sub_LH. apply sub_refl. destruct s1'.
inversion H0. simpl. apply sub_refl. Qed.
Lemma joins_subtyping_2:forall s1 s2 s2',
subsum_r s2 s2' ->
subsum_r (joins s1 s2)(joins s1 s2').
Proof. intros. destruct s1. destruct s2. destruct s2'. simpl. apply sub_refl. simpl. apply sub_LH.
destruct s2'. inversion H0. simpl. apply sub_refl. simpl. apply sub_refl. Qed.
Lemma value_b:forall t b,
value t ->
value (joinvs t b).
Proof. intros. inversion H0. rewrite->join_tcon_b. apply v_c. rewrite->join_tabs_b. apply v_f.
rewrite->join_tunit_b. apply v_u. rewrite->join_tloc_b. apply v_l. Qed.
Lemma has_type_value_joinvs:forall pc b Gamma HT t T,
value t ->
subsum_r pc b ->
subsum_r b (labelT T) ->
has_type pc Gamma HT t T ->
has_type pc Gamma HT (joinvs t b) T.
Proof. intros. inversion H0.
Case ("tcon").
intros. rewrite->join_tcon_b. subst. apply inversion_tcon in H3. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H8. inversion H10. subst. destruct T. destruct r.
simpl in H2. apply t_sub with (pc:=pc)(T:=an int (joins b0 b)). apply t_con. apply sub_refl.
apply subt_int. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s). apply H6.
inversion H12. apply H13. apply H2. inversion H12.
inversion H12. inversion H12.
Case ("tabs").
intros. rewrite->join_tabs_b. subst. apply inversion_tabs in H3. inversion H3. inversion H4. inversion H5.
inversion H6. inversion H7. inversion H8. inversion H9. inversion H10. inversion H12. inversion H14.
inversion H16. inversion H18. inversion H20. inversion H22. destruct T. destruct r. inversion H24.
simpl in H2. apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) (joins b0 b)). apply t_sub with (pc:=pc)(T:=an (fn x s0 t0)(joins b0 b)).
apply t_sub with (pc:=pc)(T:=an (fn T0 s0 t0) (joins b0 b)). apply t_abs. apply t_sub with (pc:=x4)(T:=x1). apply t_sub with (pc:=x3)(T:=x0).
apply H13. apply H15. apply H21. inversion H24. apply H34. inversion H24. apply H36. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
apply H19. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. inversion H24. apply H35. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x5)(c:=s). apply H23. inversion H24. apply H30. apply H2. apply sub_refl. apply subtyping_refl.
apply subtyping_refl. inversion H24. inversion H24.
Case ("tunit").
intros. rewrite->join_tunit_b. subst. apply inversion_tunit in H3. inversion H3. inversion H4. inversion H5. inversion H6. inversion H8. inversion H10.
subst. destruct T. destruct r. inversion H12. inversion H12. apply t_sub with (pc:=pc)(T:=an unit (joins b0 b)).
apply t_unit. apply sub_refl. apply subt_unit. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s). apply H6. inversion H12. apply H13.
simpl in H2. apply H2. inversion H12.
Case ("tloc").
intros. rewrite->join_tloc_b. subst. apply inversion_tloc in H3. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7. inversion H9. inversion H11. inversion H13. inversion H15. subst.
destruct T. destruct r. inversion H17. inversion H17. inversion H17. inversion H17. subst. simpl in H2. apply t_sub with (pc:=pc)(T:=an (ref t) (joins b0 b)). apply t_loc. inversion H8. subst.
apply H7. apply sub_refl. apply subt_ref. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=s). apply H11. inversion H17. apply H18. apply H2.
Qed.
Lemma has_type_joinvs_sub:forall pc b b' Gamma HT t T,
value t ->
subsum_r b b' ->
has_type pc Gamma HT (joinvs t b') T ->
has_type pc Gamma HT (joinvs t b) T.
Proof. intros. inversion H0.
Case ("tcon").
rewrite->join_tcon_b. subst. rewrite->join_tcon_b in H2. apply inversion_tcon in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. subst. destruct T. destruct r. apply t_sub with (pc:=pc)(T:=an int x1). apply t_sub with (pc:=pc)(T:=an int (joins b0 b')).
apply t_sub with (pc:=pc)(T:=an int (joins b0 b)). apply t_con. apply sub_refl. apply subt_int. apply joins_subtyping_2. apply H1. apply sub_refl. apply subt_int.
apply H5. apply sub_refl. apply H11. inversion H11. inversion H11. inversion H11.
Case ("tabs").
rewrite->join_tabs_b. subst. rewrite->join_tabs_b in H2. apply inversion_tabs in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H11. inversion H13. inversion H15. inversion H17. inversion H19. inversion H21. destruct T. destruct r. inversion H23. apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) x5).
apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) (joins b0 b')). apply t_sub with (pc:=pc)(T:=an (fn t s0 t0)(joins b0 b)). apply t_sub with (pc:=pc)(T:=an (fn x s0 t0)(joins b0 b)).
apply t_sub with (pc:=pc)(T:=an (fn T0 s0 t0)(joins b0 b)). apply t_abs. apply t_sub with (pc:=x4)(T:=x1). apply t_sub with (pc:=x3)(T:=x0). apply H12. apply H14. apply H20. inversion H23. apply H33.
inversion H23. apply H35. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply H18. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. inversion H23. inversion H34. subst.
apply H34. subst. apply H34. subst. apply H34. subst. apply H34. apply subtyping_refl. apply sub_refl. apply subt_fn. apply joins_subtyping_2. apply H1. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply H22. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn. inversion H23. apply H29. apply sub_refl. apply subtyping_refl. apply subtyping_refl. inversion H23. inversion H23.
Case ("tunit").
rewrite->join_tunit_b. subst. rewrite->join_tunit_b in H2. apply inversion_tunit in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7. inversion H9. subst. destruct T. destruct r. inversion H11. inversion H11.
apply t_sub with (pc:=pc)(T:=an unit x1). apply t_sub with (pc:=pc)(T:=an unit (joins b0 b')). apply t_sub with (pc:=pc)(T:=an unit (joins b0 b)). apply t_unit. apply sub_refl. apply subt_unit. apply joins_subtyping_2. apply H1. apply sub_refl.
apply subt_unit. apply H5. apply sub_refl. apply H11. inversion H11.
Case ("tloc").
rewrite->join_tloc_b. subst. rewrite->join_tloc_b in H2. apply inversion_tloc in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H8. inversion H10. inversion H12. inversion H14. subst. destruct T. destruct r. inversion H16. inversion H16. inversion H16.
inversion H16. subst. apply t_sub with (pc:=pc)(T:=an (ref t) x2). apply t_sub with (pc:=pc)(T:=an (ref t) (joins b0 b')).
apply t_sub with (pc:=pc)(T:=an (ref t) (joins b0 b)). apply t_loc. inversion H7. subst. apply H6. apply sub_refl. apply subt_ref. apply joins_subtyping_2. apply H1. apply sub_refl. apply subt_ref. apply H10. apply sub_refl. apply subt_ref. inversion H16. apply H17.
Qed.
Lemma has_type_joinvs_b:forall pc HT t T b,
value t ->
has_type pc empty_context HT t T ->
has_type pc empty_context HT (joinvs t b) (joinTs T b).
Proof.
intros. inversion H0.
Case ("tcon").
intros. rewrite->join_tcon_b. subst. apply inversion_tcon in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6.
inversion H8. subst. destruct T. destruct r. rewrite->joinTs_b. apply t_sub with (pc:=pc)(T:=an int (joins b0 b)). apply t_con. apply sub_refl.
apply subt_int. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s). apply H9. inversion H10. apply H11. inversion H10.
inversion H10. inversion H10.
Case ("tabs").
intros. rewrite->join_tabs_b. subst. apply inversion_tabs in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6.
inversion H7. inversion H8. inversion H10. inversion H12. inversion H14. inversion H16. inversion H18. inversion H20. destruct T. destruct r. inversion H22.
rewrite->joinTs_b. apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) (joins b0 b)). apply t_sub with (pc:=pc)(T:=an (fn x s0 t0) (joins b0 b)).
apply t_sub with (pc:=pc)(T:=an (fn T0 s0 t0)(joins b0 b)). apply t_abs. apply t_sub with (pc:=x4)(T:=x1). apply t_sub with (pc:=x3)(T:=x0).
apply H11. inversion H13. apply sub_refl. apply sub_LH. apply H19. inversion H22. apply H32. inversion H22. apply H34. apply sub_refl. apply subt_fn. apply sub_refl.
apply sub_refl. apply H17. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. inversion H22. apply H33. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x5)(c:=s). apply H21. inversion H22. apply H28. apply sub_refl. apply subtyping_refl. apply subtyping_refl.
inversion H22. inversion H22.
Case ("tunit").
intros. rewrite->join_tunit_b. subst. apply inversion_tunit in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6. inversion H8. subst. destruct T. destruct r. inversion H10.
inversion H10. rewrite->joinTs_b. apply t_sub with (pc:=pc)(T:=an unit (joins b0 b)). apply t_unit. apply sub_refl. apply subt_unit. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s).
apply H9. inversion H10. apply H11. inversion H10.
Case ("tloc").
intros. rewrite->join_tloc_b. subst. apply inversion_tloc in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7. inversion H9.
inversion H11. inversion H13. subst. destruct T. destruct r. inversion H15. inversion H15. inversion H15. rewrite->joinTs_b. inversion H15. subst. apply t_sub with (pc:=pc)(T:=an (ref t)(joins b0 b)).
apply t_loc. inversion H6. subst. apply H5. apply sub_refl. apply subt_ref. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=s). apply H9. inversion H15. apply H16.
Qed.
Lemma l_lt_hp:forall (T:Type)(l:nat) (hp:list T),
l <= length hp ->
l <> length hp ->
l < length hp.
Proof. intros. unfold not in H1. unfold lt. inversion H0. apply H1 in H2. inversion H2.
apply n_iff_Sn_left. apply H3. Qed.
Lemma labelT_subsum_labelt:forall pc HT t T,
value t ->
has_type pc empty_context HT t T ->
subsum_r (label t)(labelT T).
Proof. intros. inversion H0.
Case ("tcon"). subst. apply inversion_tcon in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H6. inversion H8. subst. apply subtyping_subsum in H10. simpl in H10. apply subsum_r_trans with (a:=label (tcon n b))(b:=x1)(c:=labelT T).
compute. apply H9. apply H10.
Case ("tabs"). subst. apply inversion_tabs in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7. inversion H8.
inversion H10. inversion H12. inversion H14. inversion H16. inversion H18. inversion H20. apply subtyping_subsum in H22. simpl in H22. compute. destruct T. simpl in H22.
apply subsum_r_trans with (a:=b)(b:=x5)(c:=s). apply H21. apply H22.
Case ("tunit"). subst. apply inversion_tunit in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6. inversion H8. subst. apply subtyping_subsum in H10. simpl in H10.
apply subsum_r_trans with (a:=label (tunit b))(b:=x1)(c:=labelT T). compute. apply H9. apply H10.
Case ("tloc"). subst. apply inversion_tloc in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7. inversion H9. inversion H11. inversion H13. subst. apply subtyping_subsum in H15. simpl in H15.
apply subsum_r_trans with (a:=label (tloc T0 (Some n) b))(b:=x2)(c:=labelT T). compute. apply H9. apply H15.
Qed.
(**
Lemma well_formed_heap_extend:forall t hp C,
well_formed t hp ->
well_formed t (snoc hp C).
Proof. intros t. induction t.
Case ("tvar"). intros. apply wf_tvar.
Case ("tprot"). intros. apply wf_tprot. apply IHt. inversion H0. apply H4.
Case ("tcon"). intros. apply wf_tcon.
Case ("tabs"). intros. apply wf_tabs. apply IHt. inversion H0. apply H6.
Case ("tapp"). intros. apply wf_tapp. apply IHt1. inversion H0. apply H3.
apply IHt2. inversion H0. apply H5.
Case ("tunit"). intros. apply wf_tunit.
Case ("tref"). intros. apply wf_tref. apply IHt. inversion H0. apply H5.
Case ("tderef"). intros. apply wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct o. apply wf_tloc. rewrite->length_snoc. apply le_S. inversion H0. apply H5.
inversion H0.
Case ("tassign"). intros. apply wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Qed.
*)
(**
Lemma well_formed_heap_replace:forall t hp C x,
well_formed t hp ->
well_formed t (heap_replace x C hp).
Proof. intros t. induction t.
Case ("tvar"). intros. apply wf_tvar.
Case ("tprot"). intros. apply wf_tprot. apply IHt. inversion H0. apply H4.
Case ("tcon"). intros. apply wf_tcon.
Case ("tabs"). intros. apply wf_tabs. apply IHt. inversion H0. apply H6.
Case ("tapp"). intros. apply wf_tapp. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Case ("tunit"). intros. apply wf_tunit.
Case ("tref"). intros. apply wf_tref. apply IHt. inversion H0. apply H5.
Case ("tderef"). intros. apply wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct o. apply wf_tloc. rewrite->length_replace. inversion H0.
apply H5. inversion H0.
Case ("tassign"). intros. apply wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Qed.
*)
(**
Lemma well_formed_joinvs_b:forall t hp b C,
value t ->
well_formed t hp ->
well_formed (joinvs t b) (snoc hp C).
Proof. intros. inversion H0.
Case ("tcon"). subst. rewrite->join_tcon_b. apply wf_tcon.
Case ("tabs"). subst. rewrite->join_tabs_b. apply wf_tabs. inversion H1. subst. apply well_formed_heap_extend.
apply H7.
Case ("tunit"). rewrite->join_tunit_b. apply wf_tunit.
Case ("tloc"). rewrite->join_tloc_b. apply wf_tloc. subst. inversion H1. subst. rewrite->length_snoc. apply le_S.
apply H6.
Qed.
*)
Lemma well_formed_b:forall t hp b,
value t ->
well_formed t hp ->
well_formed (joinvs t b) hp.
Proof. intros. inversion H0.
Case ("tcon"). subst. rewrite->join_tcon_b. apply wf_tcon.
Case ("tabs"). subst. rewrite->join_tabs_b. apply wf_tabs.
inversion H1. apply H7.
Case ("tunit"). subst. rewrite->join_tunit_b. apply wf_tunit.
Case ("tloc"). subst. rewrite->join_tloc_b. apply wf_tloc. inversion H1.
apply H6.
Qed.
(*type preservation*)
Theorem preservation:forall pc PC HT t t' T hp hp',
has_type pc empty_context HT t T ->
heap_well_typed HT hp ->
t / hp ==PC=> t' / hp' ->
subsum_r PC pc ->
exists HT',
(extends HT' HT /\
has_type pc empty_context HT' t' T /\
heap_well_typed HT' hp').
Proof.
intros. remember (@empty_context) as context. generalize dependent hp.
generalize dependent hp'. generalize dependent t'. generalize dependent PC.
induction H0.
Case ("t_var").
intros. inversion H2.
Case ("t_con").
intros. inversion H2.
Case ("t_unit").
intros. inversion H2.
Case ("t_loc").
intros. inversion H2.
Case ("t_abs").
intros. inversion H2.
Case ("t_prot").
intros. inversion H4. subst. apply IHhas_type in H13. inversion H13. exists x.
split. apply H1. split. apply t_prot with (T:=T). apply H1. reflexivity. apply H1.
reflexivity. apply joins_subtyping_1. apply H3. apply H2.
subst. exists HT. split. apply extends_refl. split. apply value_pc with (pc:=joins pc b).
apply value_b. apply H13. apply has_type_joinvs_b. apply H13. apply H0. apply H2.
Case ("t_app").
intros. inversion H2. subst. exists HT. split. apply extends_refl. split. apply inversion_tabs in H0_. inversion H0_. inversion H0. inversion H4. inversion H5. inversion H6. inversion H7. inversion H8.
inversion H9. inversion H15. inversion H17. inversion H19. inversion H21. inversion H23. inversion H25.
apply t_sub with (pc:=pc)(T:=joinTs T2 x6). apply t_sub with (pc:=pc)(T:=joinTs T2 b0). apply t_prot with (T:=T2).
apply t_sub with (pc:=x5)(T:=T2). apply t_sub with (pc:=x4)(T:=T2). apply t_sub with (pc:=x4)(T:=x2). apply t_sub with (pc:=x4)(T:=x1). apply value_pc with (pc':=x4) in H0_0.
apply t_sub with (pc':=x4)(T':=x0)in H0_0. apply t_sub with (pc':=x4)(T':=T) in H0_0. apply substitution_preserves_typing with (T1:=T). apply H13. apply H0_0. apply H16. apply sub_refl.
apply H22. apply sub_refl. inversion H27. apply H38. apply H13. apply sub_refl. apply H24. apply sub_refl.
inversion H27. apply H39. apply H18. apply subtyping_refl. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=x5). apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc x6)(c:=joins pc b).
apply joins_subtyping_2. apply H26. apply joins_subtyping_2. inversion H27. apply H33. inversion H27. apply H37. apply subtyping_refl. reflexivity. apply sub_refl. apply joinTs_subtyping_s. apply H26. apply sub_refl.
apply joinTs_subtyping_s. inversion H27. apply H33. apply H1. subst.
apply IHhas_type1 in H13. inversion H13. exists x. split. apply H0. split. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply H0. apply change_HT with (HT:=HT). apply H0. apply H0_0. reflexivity. apply H0. reflexivity. apply H3. apply H1.
subst. apply IHhas_type2 in H14. inversion H14. exists x. split. apply H0. split. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply change_HT with (HT:=HT). apply H0. apply H0_. apply H0. reflexivity. apply H0. reflexivity. apply H3.
apply H1.
Case ("t_ref").
intros. inversion H5. subst. exists (snoc HT T). split. apply extends_snoc. split. apply t_loc. inversion H4.
rewrite<-H1. rewrite->extends_Tlookup_last. reflexivity. split.
rewrite->length_snoc. rewrite->length_snoc. inversion H4. rewrite->H1. reflexivity.
inversion H4. split. rewrite->length_snoc. apply heap_well_formed_extend. apply H6. apply well_formed_b. apply H14. apply H13.
(*continue from here*)
intros. remember (beq_nat l (length hp)) as CC. destruct CC. apply beq_nat_eq in HeqCC. rewrite->HeqCC. assert (heap_Tlookup (length hp)(snoc HT T) = heap_Tlookup (length HT)(snoc HT T)).
rewrite<-H1. reflexivity. rewrite->H8. rewrite->extends_Tlookup_last. simpl. rewrite->extends_lookup_last. simpl. split. apply value_b. apply H14. split. apply subtyping_refl. split.
rewrite->joins_refl.
assert (subsum_r (joins PC b)(labelT T)). apply subsum_r_trans with (a:=joins PC b)(b:=joins pc b)(c:=labelT T). apply joins_subtyping_1. apply H3. apply H2.
apply joins_subsum in H9. assert (joins PC b = joins b PC). rewrite->joins_refl. reflexivity. rewrite->H10 in H9. rewrite->H9. inversion H14. subst. rewrite->join_tcon_b. assert (label (tcon n (joins b0 (labelT T)))=joins b0 (labelT T)). reflexivity.
rewrite->joins_refl. compute. apply subsum_guard. rewrite->join_tabs_b. rewrite->joins_refl. compute. apply subsum_guard. rewrite->join_tunit_b. rewrite->joins_refl. compute. apply subsum_guard. rewrite->join_tloc_b. rewrite->joins_refl. compute. apply subsum_guard.
apply change_HT with (HT:=HT). apply extends_snoc. apply value_pc with (pc:=joins pc b). apply value_b. apply H14. apply t_sub with (pc:=joins pc b)(T:=joinTs T (joins (labelT T)(joins b PC))).
apply has_type_joinvs_b. apply H14. apply H0. apply sub_refl. assert (subsum_r (joins b PC)(labelT T)). apply subsum_r_trans with (a:=joins b PC)(b:=joins b pc)(c:=labelT T). apply joins_subtyping_2. apply H3. rewrite->joins_refl.
apply H2. apply joins_subsum in H9. rewrite->joins_refl. rewrite->H9. destruct T. simpl. destruct s. apply subtyping_refl. apply subtyping_refl.
symmetry in HeqCC. apply beq_nat_false in HeqCC. unfold lt in H7. rewrite ->length_snoc in H7. apply n_iff_Sn_right in H7. assert (l < length hp). apply l_lt_hp. apply H7. apply HeqCC. clear H7. clear HeqCC. assert (l <length hp). apply H8. assert (l <length hp).
apply H8. rewrite<-H1 in H8. apply extends_lookup with (p:=(joinvs t (joins (labelT T)(joins b PC)),T))in H7. rewrite<-H7. apply extends_Tlookup with (HT':=snoc HT T) in H8. rewrite->H8. split. inversion H6. specialize (H11 pc0 l). apply H11 in H9. apply H9. split.
inversion H6. specialize (H11 pc0 l). apply H11 in H9. apply H9. split.
inversion H6. specialize (H11 pc0 l). apply H11 in H9. apply H9.
inversion H6. specialize (H11 pc0 l). apply H11 in H9.
apply change_HT with (HT:=HT). apply extends_snoc. apply H9.
apply extends_snoc. subst. destruct b. rewrite->joins_refl in H15. simpl in H15.
apply IHhas_type in H15. inversion H15. exists x. split. apply H1. split. apply t_ref with (b':=joins pc L). apply H1. reflexivity. apply H2. apply H1. reflexivity. rewrite->joins_refl. simpl. apply H3. apply H4. rewrite->joins_refl in H15. simpl in H15.
apply IHhas_type in H15. inversion H15. exists x. split. apply H1. split. apply t_ref with (b':=joins pc H). apply H1. reflexivity. apply H2. apply H1. reflexivity. rewrite->joins_refl. simpl. apply sub_refl. apply H4.
Case ("t_deref").
intros. inversion H4. subst. exists HT. split. apply extends_refl. split. apply inversion_tloc in H0. inversion H0. inversion H1. inversion H5. inversion H6. inversion H7. inversion H9. inversion H13. inversion H15. inversion H17.
subst. apply t_sub with (pc:=pc)(T:=joinTs T x2). apply t_sub with (pc:=pc)(T:=joinTs T b0). apply t_prot with (T:=T). inversion H19. subst. inversion H2. inversion H20. apply H22 with (pc:=joins pc b0)in H11. inversion H7. inversion H23. subst. rewrite->H12 in H11. simpl in H11.
inversion H11. inversion H26. inversion H28. apply H30.
reflexivity. apply sub_refl. apply joinTs_subtyping_s. apply H13. apply sub_refl. apply joinTs_subtyping_s. inversion H19. apply H16. apply H2. subst.
apply IHhas_type in H12. inversion H12. exists x. split. apply H1. split. apply t_deref with (T:=T)(b:=b). apply H1. reflexivity. apply H1. reflexivity. apply H3. apply H2.
Case ("t_assign").
intros. inversion H4. subst. exists HT. split. apply extends_refl. split. apply t_sub with (pc:=pc)(T:=an unit (joins pc b)).
apply t_sub with (pc:=pc)(T:=an unit (joins PC b)). apply t_sub with (pc:=pc)(T:=an unit (joins PC b0)). apply t_unit. apply sub_refl. apply subt_unit. apply joins_subtyping_2. apply inversion_tloc in H0_. inversion H0_. inversion H0. inversion H5. inversion H6. inversion H7. inversion H9. inversion H15. inversion H19. inversion H21. subst. inversion H23. subst.
apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H15. inversion H23. apply H24. apply sub_refl. apply subt_unit. apply joins_subtyping_1. apply H3. apply sub_refl. apply subt_unit. apply H1. split. inversion H2.
rewrite->H0. rewrite->length_replace. reflexivity. split. rewrite->length_replace.
apply heap_well_formed_replace. apply well_formed_b. apply H13. apply H11. apply H10. apply H12.
intros. remember (beq_nat l n) as CC. destruct CC.
apply beq_nat_eq in HeqCC. subst. apply lookup_replace_eq with (t:=(joinvs t2 (joins (labelT T0) (joins PC b0)),joinTs T0 (joins PC b0)))in H12. rewrite->H12. simpl. apply inversion_tloc in H0_. inversion H0_. inversion H5. inversion H6.
inversion H7. inversion H8. inversion H14. inversion H16. inversion H20. inversion H22. subst. inversion H9. subst. rewrite->H15. simpl. split.
apply value_b. apply H13.
split.
assert(subsum_r (joins PC b0)(labelT T0)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T0). apply joins_subtyping_1. apply H3. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T0).
apply joins_subtyping_2. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H8. inversion H24. apply H21. inversion H24. apply H1. apply joins_subsum in H19. assert (joins (labelT T0)(joins PC b0) = joins (joins PC b0)(labelT T0)). rewrite->joins_refl. reflexivity. destruct T0. rewrite->joinTs_b. simpl in H19. rewrite->joins_refl in H19. rewrite->H19. apply subtyping_refl.
split.
assert(subsum_r (joins PC b0)(labelT T0)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T0). apply joins_subtyping_1. apply H3. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T0).
apply joins_subtyping_2. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H8. inversion H24. apply H21. inversion H24. apply H1. apply joins_subsum in H19. destruct T0. rewrite->joinTs_b. simpl in H19. rewrite->joins_refl in H19. rewrite->H19. simpl. rewrite->H19.
inversion H13.
rewrite->join_tcon_b. assert (label (tcon n (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25. rewrite->joins_refl. apply subsum_guard. rewrite->join_tabs_b. assert (label (tabs (Id n) T0 e (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25.
rewrite->joins_refl. apply subsum_guard. rewrite->join_tunit_b. assert (label (tunit (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25. rewrite->joins_refl. apply subsum_guard.
rewrite->join_tloc_b. assert (label (tloc T0 (Some n) (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25. rewrite->joins_refl. apply subsum_guard.
apply value_pc with (pc:=pc). apply value_b. apply H13. apply t_sub with (pc:=pc)(T:=joinTs T0 (joins (labelT T0)(joins PC b0))).
apply has_type_joinvs_b. apply H13. inversion H24. apply H0_0. apply sub_refl. assert (subsum_r (joins PC b0)(labelT T0)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b)(c:=labelT T0). apply subsum_r_trans with (a:=joins PC b0)(b:=joins PC b)(c:=joins pc b). apply joins_subtyping_2. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H8. inversion H24. apply H21. apply joins_subtyping_1.
apply H3. inversion H24. subst. apply H1. apply joins_subsum in H19. rewrite->joins_refl in H19. rewrite->H19. rewrite->joinTs_same. apply subtyping_refl. subst.
symmetry in HeqCC. apply beq_nat_false in HeqCC. rewrite->length_replace in H0. apply lookup_replace_neq with (t:=(joinvs t2 (joins (labelT T0)(joins PC b0)),joinTs T0 (joins PC b0)))(st:=hp) in HeqCC. rewrite->HeqCC. split. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0.
split. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0. split. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0.
subst.
apply IHhas_type1 in H14. inversion H14. exists x. split. apply H0. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1. apply H0. apply change_HT with (HT:=HT). apply H0. apply H0_0. apply H0. reflexivity. apply H3. apply H2. subst.
apply IHhas_type2 in H15. inversion H15. exists x. split. apply H0. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1. apply change_HT with (HT:=HT). apply H0. apply H0_. apply H0. apply H0. reflexivity. apply H3. apply H2.
Case ("t_sub").
intros. apply IHhas_type in H5. inversion H5. exists x. split. apply H6. split. apply t_sub with (pc:=pc)(T:=T). apply H6. apply H1. apply H2. apply H6. apply Heqcontext. apply subsum_r_trans with (a:=PC)(b:=pc')(c:=pc). apply H3. apply H1. apply H4.
Qed.
(*generalization of preservation*)
Theorem type_uniqueness:forall x z PC pc HT T,
has_type pc empty_context HT (fst x) T ->
heap_well_typed HT (snd x) ->
subsum_r PC pc ->
Multistep x PC z ->
(exists HT',
extends HT' HT /\
heap_well_typed HT' (snd z) /\
has_type pc empty_context HT'(fst z) T).
Proof. intros. generalize dependent pc. generalize dependent HT. induction H3.
Case ("multi_refl"). intros. exists HT. admit.
Case ("multi_step"). intros. apply preservation with (PC:=b)(t':=fst y)(hp:=snd x)(hp':=snd y)in H2.
inversion H2. inversion H5. inversion H7. apply IHMulti with (pc:=pc)in H9.
inversion H9. exists x1. split. apply extends_trans with (HT':=x0). apply H6.
apply H10. apply H10. apply H8. apply H4. apply H1. destruct x. destruct y. apply H0.
apply H4.
Qed.
(*progress*)
(*one auxiliary lemma*)
Lemma well_typed_well_formed:forall pc HT hp t T,
has_type pc empty_context HT t T ->
heap_well_typed HT hp ->
well_formed t (length hp).
Proof. intros. generalize dependent hp. induction H0.
Case ("t_var"). intros. apply wf_tvar.
Case ("t_con"). intros. apply wf_tcon.
Case ("t_unit"). intros. apply wf_tunit.
Case ("t_loc"). intros. apply wf_tloc. inversion H1. rewrite<-H2. apply change_HT' with (T:=T).
apply H0.
Case ("t_abs"). intros. apply wf_tabs. apply IHhas_type. apply H1.
Case ("t_prot"). intros. apply wf_tprot. apply IHhas_type. apply H2.
Case ("t_app"). intros. apply wf_tapp. apply IHhas_type1. apply H1. apply IHhas_type2.
apply H1.
Case ("t_ref"). intros. apply wf_tref. apply IHhas_type. apply H3.
Case ("t_deref"). intros. apply wf_tderef. apply IHhas_type. apply H2.
Case ("t_assign"). intros. apply wf_tassign. apply IHhas_type1. apply H2.
apply IHhas_type2. apply H2.
Case ("t_sub"). intros. apply IHhas_type. apply H3.
Qed.
Theorem progress: forall t T pc PC HT hp,
has_type pc empty_context HT t T ->
heap_well_typed HT hp ->
subsum_r PC pc ->
value t \/ (exists p, step (t,hp) PC p).
Proof. intros. remember (@empty_context) as context. generalize dependent hp.
generalize dependent PC. induction H0.
Case ("t_var").
intros. subst. inversion H0.
Case ("t_con").
intros. subst. left. apply v_c.
Case ("t_unit").
intros. subst. left. apply v_u.
Case ("t_loc").
intros. subst. left. apply v_l.
Case ("t_abs").
intros. subst. left. destruct x. apply v_f.
Case ("t_prot").
intros. subst. right. assert (heap_well_typed HT hp). apply H3. apply IHhas_type with (PC:=joins PC b)in H1.
inversion H1. exists (joinvs t b,hp). apply st_protv. inversion H3. apply H6.
apply well_typed_well_formed with (hp:=hp)in H0. apply H0. apply H3.
apply H4. inversion H4. destruct x. exists (tprot b t0,h).
apply st_prot. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H3.
apply H5. reflexivity. apply joins_subtyping_1. apply H2.
Case ("t_app").
intros. subst. right. assert (heap_well_typed HT hp). apply H1.
assert (heap_well_typed HT hp). apply H1.
apply IHhas_type1 with (PC:=PC) in H1.
apply IHhas_type2 with (PC:=PC) in H0. inversion H1. inversion H0. inversion H4. subst. apply inversion_tcon in H0_.
inversion H0_. inversion H6. inversion H7. inversion H8. inversion H10. inversion H12. subst. inversion H14.
subst. exists (tprot b0 ([(Id n ) := t2]e),hp). apply st_appabs. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp)in H0_0. apply H0_0. apply H3. apply well_typed_well_formed with (hp:=hp)in H0_.
inversion H0_. apply H11. apply H3.
apply H5. subst. apply inversion_tunit in H0_.
inversion H0_. inversion H6. inversion H7. inversion H8. inversion H10. inversion H12. subst. inversion H14.
subst. apply inversion_tloc in H0_. inversion H0_. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. inversion H13.
inversion H15. inversion H17. subst. inversion H19. inversion H5. destruct x. exists (tapp t1 t,h). apply st_app2. inversion H3. apply H8.
apply well_typed_well_formed with (hp:=hp) in H0_.
apply H0_. apply H3. apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H4. apply H6.
inversion H4. destruct x. exists (tapp t t2,h). apply st_app1. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0_.
apply H0_. apply H3.
apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H5. reflexivity. apply H2. reflexivity. apply H2.
Case ("t_ref").
intros. subst. right. assert (heap_well_typed HT hp). apply H4. apply IHhas_type with (PC:=PC)in H1. inversion H1.
exists (tloc T (Some (length hp)) b,snoc hp (joinvs t (joins (labelT T)(joins b PC)),T)). apply st_refv with (v':=joinvs t (joins (labelT T)(joins b PC)))(b':=labelT T)(b'':=joins b PC)(b''':= joins (labelT T)(joins b PC)).
inversion H4. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
apply H5. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity. destruct b. inversion H5. destruct x. exists (tref T t0 L,h).
apply st_ref. inversion H4. apply H8.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
rewrite->joins_refl. simpl. apply H6. assert (empty_context=empty_context). reflexivity. apply IHhas_type with (PC:=H)(hp:=hp) in H6. inversion H6.
exists (tloc T (Some (length hp)) H,snoc hp (joinvs t H,T)). apply st_refv with (v':=joinvs t H)(b':=labelT T)(b'':=H)(b''':=H).
inversion H4. apply H9.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
apply H7. reflexivity. reflexivity. rewrite->joins_refl. reflexivity. reflexivity. reflexivity.
inversion H7. destruct x. exists (tref T t0 H,h). apply st_ref.
inversion H4. apply H10.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
rewrite->joins_refl. simpl. apply H8. rewrite->joins_refl. simpl. apply sub_refl. apply H4. reflexivity. apply subsum_r_trans with (a:=PC)(b:=pc)(c:=joins pc b).
apply H3. apply subsum_guard.
Case ("t_deref").
intros. subst. right. assert (heap_well_typed HT hp). apply H3. apply IHhas_type with (PC:=PC)in H1. inversion H1.
inversion H4. subst. apply inversion_tcon in H0. inversion H0. inversion H5. inversion H6.
inversion H7. inversion H9. inversion H11. subst. inversion H13. subst. apply inversion_tabs in H0. inversion H0. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H10. inversion H11. inversion H13. inversion H15. inversion H17. inversion H19. inversion H21. inversion H23. inversion H25.
subst. apply inversion_tunit in H0. inversion H0. inversion H5. inversion H6. inversion H7. inversion H9. inversion H11. subst. inversion H13. subst. apply inversion_tloc in H0.
inversion H0. inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H10. apply change_HT' in H11. exists (tprot b0 (efst (heap_lookup x hp)),hp). apply st_derefloc. inversion H3.
apply H15. inversion H3. rewrite->H14 in H11. apply H11. reflexivity.
inversion H4. destruct x. exists (tderef t0,h). apply st_deref. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H3.
apply H5. reflexivity. apply H2.
Case ("t_assign").
intros. subst. right. assert (heap_well_typed HT hp). apply H3. assert (heap_well_typed HT hp). apply H3.
apply IHhas_type1 with (PC:=PC)in H0. apply IHhas_type2 with (PC:=PC)in H4. inversion H0. inversion H4. inversion H5. subst. apply inversion_tcon in H0_. inversion H0_. inversion H7. inversion H8.
inversion H9. inversion H11. inversion H13. subst. inversion H15. subst. apply inversion_tabs in H0_. inversion H0_. inversion H7. inversion H8. inversion H9. inversion H10.
inversion H11. inversion H12. inversion H13. inversion H15. inversion H17. inversion H19. inversion H21. inversion H23. inversion H25. inversion H27. subst. apply inversion_tunit in H0_. inversion H0_.
inversion H7. inversion H8. inversion H9. inversion H11. inversion H13. subst. inversion H15. subst. apply inversion_tloc in H0_. inversion H0_. inversion H7. inversion H8. inversion H9. inversion H10. inversion H11. subst. inversion H12. apply change_HT' in H13.
exists (tunit (joins PC b0),heap_replace x (joinvs t2 (joins (labelT T0)(joins PC b0)),joinTs T0 (joins PC b0)) hp). apply st_assign with (v':=joinvs t2 (joins(labelT T0)(joins PC b0)))(T':=joinTs T0 (joins PC b0))(b':=labelT T0)(b''':=joins (labelT T0)(joins PC b0))(l:=label t2). inversion H3.
apply H16.
apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3. inversion H3.
rewrite<-H15. apply H13. apply H6.
reflexivity. reflexivity. reflexivity. inversion H3.
assert (value t2). apply H6. apply labelT_subsum_labelt with (pc:=pc)(HT:=HT)(T:=T) in H17. inversion H14. inversion H19. inversion H21. subst. inversion H23. subst. apply joins_subsum in H17. rewrite->H17. inversion H16. specialize (H24 pc x). rewrite->H15 in H13. apply H24 in H13. inversion H10. inversion H26. rewrite->H27 in H13. simpl in H13. inversion H13. inversion H30. inversion H32.
apply subtyping_subsum in H31. inversion H32. assert (subsum_r (labelT T)(label (efst (heap_lookup x hp)))). apply subsum_r_trans with (a:=labelT T)(b:=labelT (esnd (heap_lookup x hp)))(c:=label (efst (heap_lookup x hp))). apply H31. apply H33. inversion H32. assert (subsum_r (label (efst (heap_lookup x hp)))(labelT T)). apply labelT_subsum_labelt with (pc:=pc)(HT:=HT).
apply H29. apply H36. apply subsum_equal. apply H37. apply H40. apply H0_0.
inversion H3. inversion H12. inversion H16. specialize (H20 L x). rewrite->H17 in H20. rewrite->H15 in H13. apply H20 in H13. inversion H13. simpl in H22. inversion H18. inversion H24. inversion H26. subst. inversion H28. subst.
apply subsum_r_trans with (a:=joins PC b0)(b:=labelT T)(c:=label (efst (heap_lookup x hp))). assert (subsum_r (joins PC b0)(labelT T)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T). apply joins_subtyping_1. apply H2. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T). apply joins_subtyping_2.
apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H18. inversion H28. apply H29. apply H1. apply H23.
apply subsum_r_trans with (a:=labelT T)(b:=labelT (esnd (heap_lookup x hp)))(c:=label (efst (heap_lookup x hp))). inversion H22. inversion H29. apply subtyping_subsum in H23. apply H23. apply H13. reflexivity. reflexivity. reflexivity. reflexivity.
(**
inversion H30. rewrite->H32. apply labelT_subsum_labelt with (pc:=pc)(HT:=HT)(T:=T) in H27. rewrite<-H32 in H27. rewrite<-H32. apply subsum_low in H27. symmetry. apply H27. apply H34. apply H0_0.
inversion H3. inversion H12. specialize (H16 L x). rewrite->H17 in H16. rewrite->H15 in H13. apply H16 in H13. inversion H13. simpl in H19. inversion H18. inversion H22. inversion H24. subst. inversion H26. subst.
apply subsum_r_trans with (a:=joins PC b0)(b:=labelT T)(c:=label (efst (heap_lookup x hp))). assert (subsum_r (joins PC b0)(labelT T)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T). apply joins_subtyping_1. apply H2. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T). apply joins_subtyping_2.
apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H14. inversion H20. apply H23. apply H1. apply H21.
apply subsum_r_trans with (a:=labelT T)(b:=labelT (esnd (heap_lookup x hp)))(c:=label (efst (heap_lookup x hp))). inversion H20. simpl in H21. apply subtyping_subsum in H21. apply H21. apply H13. reflexivity. reflexivity. reflexivity. reflexivity.
*)
inversion H6. destruct x. exists (tassign t1 t,h). apply st_assign2.
inversion H3. apply H9.
apply well_typed_well_formed with (hp:=hp) in H0_. apply H0_. apply H3. apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H5. apply H7. inversion H5. destruct x.
exists (tassign t t2,h). apply st_assign1.
inversion H3. apply H8.
apply well_typed_well_formed with (hp:=hp) in H0_. apply H0_. apply H3. apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H6. reflexivity. apply H2. reflexivity. apply H2.
Case ("t_sub").
intros. assert (subsum_r PC pc). apply subsum_r_trans with (a:=PC)(b:=pc')(c:=pc). apply H3. apply H1.
apply IHhas_type with (PC:=PC)in H4. apply H4. apply Heqcontext. apply H5.
Qed.
(*##########determinism#########*)
Theorem determinism: forall t t' t'' hp hp' hp'' PC,
t / hp ==PC=> t' / hp' ->
t / hp ==PC=> t'' / hp'' ->
(t' = t''/\hp' = hp'').
Proof. intros t. induction t.
Case ("tvar").
intros. inversion H0.
Case ("tprot").
intros. inversion H0. subst. inversion H1. subst.
apply IHt with (t':=t'0)(t'':=t')(hp'':=hp'')in H10. inversion H10. subst.
split. reflexivity. reflexivity. apply H13. subst. inversion H13. subst. inversion H10.
subst. inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H1. subst.
inversion H10. subst. inversion H13. subst. inversion H13. subst. inversion H13. subst. inversion H13.
subst. split. reflexivity. reflexivity.
Case ("tcon").
intros. inversion H0.
Case ("tabs").
intros. inversion H0.
Case ("tapp").
intros. inversion H0. inversion H1. subst. inversion H12. subst. split.
reflexivity. reflexivity. subst. inversion H21. subst. inversion H11. subst. inversion H22.
subst. inversion H22. subst. inversion H22. subst. inversion H22. subst. inversion H1. subst.
inversion H11. subst.
apply IHt1 with (t':=t1')(t'':=t1'0)(hp'':=hp'') in H11. inversion H11. subst. split. reflexivity.
reflexivity. apply H15. subst. inversion H15. subst. inversion H11. subst. inversion H11. subst. inversion H11.
subst. inversion H11. subst. inversion H1. subst. inversion H16. subst. inversion H12. subst. inversion H12.
subst. inversion H12. subst. inversion H12. subst. inversion H11. subst. inversion H16. subst. inversion H16.
subst. inversion H16. subst. inversion H16. subst.
apply IHt2 with (t':=t2')(t'':=t2'0)(hp'':=hp'')in H12. inversion H12. subst. split. reflexivity. reflexivity.
apply H17.
Case ("tunit").
intros. inversion H0.
Case ("tref").
intros. inversion H0. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H10. subst.
inversion H14. subst. inversion H14. subst. inversion H14. subst. inversion H14. subst. inversion H1. subst. inversion H13. subst.
inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. specialize (IHt t'0 t' hp hp' hp''). apply IHt in H14.
inversion H14. subst. split. reflexivity. reflexivity. apply H11.
Case ("tderef").
intros. inversion H0. inversion H1. subst. inversion H10. subst. split. reflexivity. reflexivity. subst. inversion H17. subst. inversion H1. subst.
inversion H9. subst. apply IHt with (t':=t'0)(t'':=t')(hp'':=hp'') in H9. inversion H9. subst. split. reflexivity. reflexivity. apply H12.
Case ("tloc").
intros. inversion H0.
Case ("tassign").
intros. inversion H0. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H17. subst. inversion H10. subst. inversion H18. subst. inversion H18.
subst. inversion H18. subst. inversion H18. subst. inversion H1. subst. inversion H11. subst.
specialize (IHt1 t1' t1'0 hp hp' hp'' PC). apply IHt1 in H11. inversion H11. subst.
split. reflexivity. reflexivity. apply H15. subst. inversion H15. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H1. subst.
inversion H15. subst. inversion H12. subst. inversion H12. subst. inversion H12. subst. inversion H12. subst. inversion H11. subst. inversion H16. subst. inversion H16. subst. inversion H16.
subst. inversion H14. subst. inversion H16. subst. specialize (IHt2 t2' t2'0 hp hp' hp'' PC). apply IHt2 in H12. inversion H12. subst. split. reflexivity. reflexivity. apply H17.
Qed.
(*############soundness############*)
Corollary soundness : forall pc PC HT p p' T,
has_type pc empty_context HT (fst p) T ->
heap_well_typed HT (snd p) ->
Multistep p PC p' ->
subsum_r PC pc ->
~((~exists p'', step p' PC p'')/\(~ value (fst p'))).
Proof.
intros. remember (@empty_context) as context. generalize dependent pc. generalize dependent HT.
generalize dependent T. induction H2.
Case ("multi_refl").
intros. subst. intros contra. inversion contra.
apply progress with (PC:=b)(hp:=snd x) in H0. inversion H0.
SCase ("left"). apply H4 in H5. inversion H5.
SCase ("right"). destruct x. apply H2 in H5. inversion H5. apply H1. apply H3.
Case ("multi_step"). subst. intros. apply preservation with (PC:=b)(t':=fst y)(hp:=snd x)(hp':=snd y)in H3.
inversion H3. inversion H5. inversion H7. apply IHMulti with (T:=T)(pc:=pc) in H9. apply H9. apply H8.
apply H4. apply H1. destruct x. destruct y. apply H0. apply H4.
Qed.
End SecLang.
Module LowLang.
(*syntax*)
Inductive tm : Type :=
| tvar : id -> tm
(*| tprot : Sec -> tm -> tm*)
| tcon : nat -> tm
| tabs : id -> Ty -> tm -> tm
| tapp : tm -> tm -> tm
(*#####new terms######*)
| tunit : tm
| tref : Ty -> tm -> tm (*[Ty] as the initial type*)
| tderef : tm -> tm
| tloc : Ty -> option nat -> tm(*[Ty] as the "access type"*)
| tassign : tm -> tm -> tm
(*####one additional terms meant to be typed with high security####*)
| tH : tm.
(**
Note that there is no [tprot] in [LowLang]. For the projection of a
term protected by [H] is always [tH] while the projection of terms
protected by [L] is just that of themselves
*)
(**
Also note that the referred location in [tloc] is typed as [option nat] where
we use [None] indicating a pointer to a high value on the heap in [SecLang] while
[Some n] indicating a pointer to a low value on the projected heap given that [n]
is smaller than the length of the projected heap
*)
(*well-formed term in [LowLang]*)
(*well formed expressions*)
(**
Here,a term is well-formed given a natural number which stands for
the length of the heap in [SecLang]
*)
Inductive well_formed : tm -> nat -> Prop :=
| wf_tvar:forall (x:id)(hp:nat),
well_formed (tvar x) hp
| wf_tcon:forall (n:nat)(hp:nat),
well_formed (tcon n) hp
| wf_tunit:forall (hp:nat),
well_formed tunit hp
| wf_tloc:forall (T:Ty)(n:nat)(hp:nat),
n < hp ->
well_formed (tloc T (Some n)) hp
| wf_tabs:forall x T e hp,
well_formed e hp ->
well_formed (tabs x T e) hp
| wf_tapp:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tapp t1 t2) hp
| wf_tref:forall (T:Ty) (e:tm) (hp:nat),
well_formed e hp ->
well_formed (tref T e) hp
| wf_tderef:forall e hp,
well_formed e hp ->
well_formed (tderef e) hp
| wf_tassign:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tassign t1 t2) hp
| wf_tH:forall hp,
well_formed tH hp.
(*value*)
Inductive value : tm -> Prop :=
| v_c : forall n,
value (tcon n)
| v_f : forall n T e,
value (tabs (Id n) T e)
| v_u : value tunit
| v_l : forall N T,
value (tloc T N)
| v_H : value tH
.
(*heap*)
Definition heap := list (tm*Ty).
Definition emp_hp:= @nil (tm*Ty).
(*some useful functions*)
(*###lookup function and some lemmas###*)
Fixpoint heap_lookup (n:nat)(st:heap):(option (tm*Ty)):=
match st , n with
| nil , _ =>None
| h::t , 0 => Some h
| h::t , S n' =>heap_lookup n' t
end.
(*extract the result of [heap_lookup]*)
Definition efst (p:option(tm*Ty)) : tm :=
match p with
| None => tvar (Id 100)
| Some (t , T) => t
end.
Definition esnd (p:option(tm*Ty)) : Ty :=
match p with
| None => an unit L
| Some (t, T) => T
end.
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
Lemma length_snoc:forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
intros. generalize dependent x. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x). rewrite->IHl.
reflexivity.
Qed.
Lemma lt_snoc_1 : forall n m,
S n <= S m -> n <= m.
Proof.
intros n m. generalize dependent n. induction m as [|m'].
Case ("m=0"). intros. destruct n as [|n'].
SCase ("n=0"). apply le_n.
SCase ("n=S n'"). inversion H0. inversion H2.
Case ("m=S m'"). intros. inversion H0. apply le_n. apply le_S.
apply IHm'. apply H2.
Qed.
Lemma lt_snoc: forall (l:heap) x (n:nat),
n < length l ->
heap_lookup n l = heap_lookup n (snoc l x).
Proof.
intros l. induction l.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. simpl. destruct n. reflexivity. simpl.
apply IHl. simpl in H0. apply lt_snoc_1 in H0.
apply H0.
Qed.
Lemma eq_snoc: forall (l:heap) x,
heap_lookup (length l) (snoc l x) = Some x.
Proof.
intros l. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x).
apply IHl.
Qed.
(*###replace function and some lemmas###*)
Fixpoint heap_replace n x (l:heap): heap :=
match l , n with
| nil , _ =>nil
| h::t , 0 => x::t
| h::t , S n' =>h :: (heap_replace n' x t)
end.
Lemma replace_nil: forall n x,
heap_replace n x nil = nil.
Proof.
intros. destruct n. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma length_replace: forall n x (l:heap),
length (heap_replace n x l) = length l.
Proof.
intros. generalize dependent n. generalize dependent x. induction l.
Case ("nil"). intros. simpl. rewrite->replace_nil. simpl. reflexivity.
Case ("h::t"). intros. simpl. destruct n. simpl. reflexivity.
simpl. specialize (IHl x n). rewrite->IHl. reflexivity.
Qed.
Lemma lookup_replace_eq: forall l t st,
l < length st ->
heap_lookup l (heap_replace l t st) = Some t.
Proof.
intros. generalize dependent l. generalize dependent t.
induction st.
Case ("nil"). intros. destruct l. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct l. simpl. reflexivity.
simpl. apply IHst. simpl in H0. unfold lt. unfold lt in H0.
apply lt_snoc_1 in H0. apply H0.
Qed.
Lemma lookup_replace_neq: forall l1 l2 t st,
l1 <> l2 ->
heap_lookup l1 (heap_replace l2 t st) = heap_lookup l1 st.
Proof.
intros. generalize dependent l1. generalize dependent l2. generalize dependent t.
induction st.
Case ("nil"). intros. rewrite->replace_nil. reflexivity.
Case ("h::t"). intros. destruct l2. destruct l1. simpl. assert (0=0). reflexivity.
apply H0 in H1. inversion H1. simpl. reflexivity. simpl.
destruct l1. reflexivity. apply IHst.
intros T. assert (l1 = l2 -> S l1 = S l2). intros. subst. reflexivity.
apply H1 in T. apply H0 in T. inversion T.
Qed.
(*substitution*)
Fixpoint subst (x:id) (s:tm) (t:tm): tm :=
match t with
(*variables*)
| tvar x' =>
if beq_id x x' then s else t
(*abstractions*)
| tabs x' T t1 =>
tabs x' T (if beq_id x x' then t1 else (subst x s t1))
(*constants*)
| tcon n => tcon n
(*applications*)
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
(*units*)
| tunit => tunit
(*tref*)
| tref T t1 => tref T (subst x s t1)
(*tderef*)
| tderef t1 => tderef (subst x s t1)
(*tloc*)
| tloc T N => tloc T N
(*assignments*)
| tassign t1 t2 => tassign (subst x s t1)(subst x s t2)
(*high value*)
| tH => tH
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
Definition labelT (T:Ty) : Sec:=
match T with
| an rt b => b
end.
Reserved Notation "t1 '/' hp '==' PC '=>' t2 '/' hp'"
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
(**
Note currently all terms are without any security labels and as will be
specified below in the type relation all terms except [tH] can be typed
as low and high while [tH] can only be typed as low.
*)
(**
Regarding the reduction relation,
a. application
In [LowLang], we preserve both [st_app1] [st_app2] and [st_appabs] to deal with
cases where either of the subterms of the application are reducible or the first
term of the application which is a low abstraction is applied to a value. In addition,
we have [st_apptH] to deal with cases where a high abstraction is being applied to
a value. In such cases,since the result is always being protected by [H] we should
have it as follows,
[st_apptH]:forall v PC hp,
value v ->
tapp tH v / hp ==PC=> tH / hp
b. reference
in [LowLang], we preserve both [st_ref] and [st_refv] to deal with cases where either the
subterm is reducible or the subterm is a low value and both the label of the referred
tpye and PC have to be low for the new cell being written onto the heap is being
protected by both [labelT T] and [PC] and after reduction the heap is extended by
the pair of the guarded low value and the referred type. In addtion we also have
to deal with cases where a high value actually gets written onto the heap either
because the value itself is [tH] or the join of [PC] and [labelT T] is [H]. In such
cases, the heaps before and after the reduction are the same while we replace the
referred location to [None] to signal the fact that in [LowLang],all
high values in a heap are referred to via [None] which is the default value of the referred
location.
[st_reftH]:forall v PC T hp,
value v ->
v = tH \/ PC = H \/ LabelT T = H ->
tref T v / hp ==PC=> tloc T None / hp
Note that we only consider three cases of assignment in [LowLang],
1. a high cell is being over-written by a high value
2. a low cell is being over-written by a low value
It should be noted that we do not deal with cases where a high cell is being over-written
by a low value and a low cell is being over-written by a high value. Such cases are ruled out by explicitly prohibiting any upgrading
and downgrading in [SecLang]
c. dereference
as illustrated in [b.],the ways how we write a low value and a high value are
different in that the low cell being written onto the heap is always referred
to via a location which is within range while all high values are actually not
being written onto the heap for in [LowLang] we want to abstract away all high
level side-effect. Instead, we rewrite the referred location as [None] so as to
signal cases where high value is being written onto the heap.
Hence we should have the following reduction rules besides [st_deref] where the
subterm is reducible,
[st_derefloc]:forall n hp T hp PC,
n < length hp ->
v = efst (heap_lookup n hp) ->
tderef (tloc T (Some n)) / hp ==PC=> v / hp
[st_derefloctH]:
tderef (tloc T None) / hp ==PC=> tH / hp
the case where the subterm is [tH] is simple for it must
correspond to the dereference of a high location in [SecLang] where the
result of the reduction is protected by [H] the projection of which is [tH],
[st_dereftH]:
tderef tH / hp ==PC=> tH / hp
d. assignment
the reduction rule in cases where each of its subterms is reducible is not different
from [st_assign1] and [st_assign2] in [SecLang]. Now in regard with cases where
a cell on the heap is being over-written by some value it is not necessary for us
to deal with cases where either a high cell is being over-written by a low value or
a low cell is being over-written by a high value. They are ruled out by prohibiting any
upgrading and downgrading in [SecLang].
Now in [LowLang],we only need to consider two cases of assignment,
a. a low cell is being over-written by a low value
[st_assign]:forall n hp v T PC
n < length hp ->
value v ->
v <> tH ->
PC = labelT T = L ->
hp'=heap_replace n (v,T) hp ->
tassign ((tloc T )(Some n)) v / hp ==PC=>tunit / hp'
b. a high cell is being over-written by a high value
when security context is low
[st_assigntH_L]:forall hp v T PC hp,
value v ->
v = tH \/ labelT T = H ->
PC = L ->
tassign (tloc T None) v / hp ==PC=> tunit / hp
c. a high cell is being over-written by a high value
when security context is high
[st_assigntH_H]:forall n hp v PC T hp,
n = length hp ->
value v ->
PC = H ->
tassign (tloc T None) v / hp ==PC=> tH / hp
the case where the pointer through which heap cell is updated is high would
mean either over-writing a low cell with a high value or a high cell with a
high value where the former case bring us difficulty for the projection of
a high pointer according to our projection function destroys all info. regarding
the location of the relevent low cell which we would like to get rid of through
projection. Yet,we need not consider this case for condition that the cell being
over-written must be guarded by the joint of [PC] and the label of the pointer for
the reduction to proceed. Then we have,
[st_assignHP]:forall
value v ->
tassign tH v / hp ==PC=> tH / hp
*)
Inductive step : tm * heap -> Sec -> tm * heap -> Prop :=
| st_appabs: forall x T e PC hp v,
value v ->
tapp (tabs x T e) v / hp == PC => [x := v]e / hp
| st_app1: forall t1 t1' t2 PC hp hp',
t1 / hp == PC => t1' / hp' ->
tapp t1 t2 / hp == PC => tapp t1' t2 / hp'
| st_app2: forall v1 t2 t2' PC hp hp',
value v1 ->
t2 / hp == PC => t2' / hp' ->
tapp v1 t2 / hp == PC => tapp v1 t2' / hp'
(*application were a high abstraction is being applied*)
| st_apptH:forall v hp PC,
value v ->
tapp tH v / hp ==PC=> tH / hp
(*writing a new low cell*)
| st_refv: forall T v PC hp hp',
value v ->
v <> tH ->
labelT T = L ->
PC = L ->
hp' = snoc hp (v,T) ->
tref T v / hp == PC => tloc T (Some (length hp)) / hp'
(*writing a new high cell*)
| st_reftH:forall v PC T hp,
value v ->
v = tH \/ PC = H \/ labelT T = H ->
tref T v / hp ==PC=> tloc T None / hp
| st_ref: forall T t t' PC hp hp',
t / hp == PC => t' / hp' ->
tref T t / hp == PC => tref T t' / hp'
(*dereferencing a low cell on the heap*)
| st_derefloc: forall T n PC hp v,
n < length hp ->
v = efst (heap_lookup n hp) ->
tderef (tloc T (Some n)) / hp == PC => v / hp
(*dereferencing a high cell on the heap*)
| st_derefloctH:forall hp T PC,
tderef (tloc T None) / hp == PC => tH / hp
| st_deref: forall t t' hp hp' PC,
t / hp == PC => t' / hp' ->
tderef t / hp == PC => tderef t' / hp'
(*dereferencing a high loction*)
| st_dereftH:forall hp PC,
tderef tH / hp ==PC=> tH / hp
(*low cell is being over-written by a low value*)
| st_assign: forall v T n PC hp hp',
n < length hp -> (* heap_lookup n hp = some e'*)
value v ->
v <> tH ->
PC = L /\ labelT T = L ->
hp' = heap_replace n (v,T) hp ->
tassign (tloc T (Some n)) v / hp == PC => tunit / hp'
(*high cell is being over-written by a high value when [PC] is L*)
| st_assigntH_L:forall hp v PC T,
value v ->
PC = L ->
v = tH \/ labelT T = H ->
tassign (tloc T None) v / hp ==PC=> tunit / hp
(*high cell is being over-written by a high value when [PC] is H*)
| st_assigntH_H:forall hp v PC T,
value v ->
PC = H ->
tassign (tloc T None) v / hp ==PC=> tH / hp
(*a high pointer*)
| st_assignHP:forall v hp PC,
value v ->
tassign tH v / hp ==PC=> tH / hp
| st_assign1: forall t1 t1' t2 PC hp hp',
t1 / hp == PC => t1' / hp' ->
tassign t1 t2 / hp == PC => tassign t1' t2 / hp'
| st_assign2: forall v1 t2 t2' PC hp hp',
value v1 ->
t2 / hp == PC => t2' / hp' ->
tassign v1 t2 / hp == PC => tassign v1 t2' / hp'
where "t1 '/' hp '==' PC '=>' t2 '/' hp'" := (step (t1,hp) PC (t2,hp')).
(*###multi-step reduction###*)
Definition Relation (X: Type) := X->Sec->X->Prop.
Inductive Multi {X:Type} (R: Relation X) : Relation X :=
| Multi_refl : forall (x : X)(b : Sec), Multi R x b x
| Multi_step : forall (x y z : X)(b : Sec),
R x b y ->
Multi R y b z ->
Multi R x b z.
Definition Multistep := (Multi step).
Notation "t1 '/' hp '==' PC '=>*' t2 '/' hp'" := (Multistep (t1,hp) PC (t2,hp'))
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
Theorem multi_trans:forall t t' t'' hp hp' hp'' pc,
Multistep (t,hp) pc (t',hp') ->
Multistep (t',hp') pc (t'',hp'') ->
Multistep (t,hp) pc (t'',hp'').
Proof.
intros. induction H0. apply H1. apply IHMulti in H1.
apply Multi_step with y. apply H0. apply H1.
Qed.
(*some reduction samples*)
Example test_step_1:forall hp PC,
tapp tH (tcon 0) / hp ==PC=> tH / hp.
Proof. intros. apply st_apptH. apply v_c. Qed.
Example test_step_2:forall PC hp,
tref (an int L) tH / hp ==PC=>tloc (an int L) None / hp.
Proof. intros. apply st_reftH. apply v_H. left. reflexivity. Qed.
Example test_step_3:forall hp,
tref (an int L)(tcon 0) / hp ==L=> tloc (an int L) (Some (length hp)) / snoc hp (tcon 0,an int L).
Proof. intros. apply st_refv. apply v_c. intros contra. inversion contra. reflexivity. reflexivity.
reflexivity. Qed.
Example test_step_4:forall PC,
tderef (tloc (an int H) (Some 0)) / ((tcon 0,an int H) :: nil)
==PC=>
tcon 0 / ((tcon 0,an int H) :: nil).
Proof. intros. apply st_derefloc. apply le_n. reflexivity. Qed.
Example test_step_5:forall hp PC,
tderef (tloc (an int H) None) / hp
==PC=>
tH / hp.
Proof. intros. apply st_derefloctH. Qed.
Example test_step_6:forall hp PC,
tderef tH / hp ==PC=> tH / hp.
Proof. apply st_dereftH. Qed.
Example test_step_7:
tassign (tloc (an int L) (Some 0))(tcon 1) / ((tcon 0,an int L) :: nil)
==L=>
tunit / ((tcon 1,an int L) :: nil).
Proof. apply st_assign. apply le_n. apply v_c. intros contra. inversion contra.
split. reflexivity. reflexivity. reflexivity. Qed.
Example test_step_8:forall hp,
tassign (tloc (an int L) None) tH / hp
==L=>
tunit / hp.
Proof. intros. apply st_assigntH_L. apply v_H. reflexivity. left.
reflexivity. Qed.
Example test_step_9:forall hp,
tassign (tloc (an int H) None) (tcon 1) / hp
==L=>
tunit / hp.
Proof. intros. apply st_assigntH_L. apply v_c. reflexivity. right.
reflexivity. Qed.
Example test_step_10:forall hp,
tassign (tloc (an int L) None)(tcon 1) / hp
==H=>
tH / hp.
Proof. intros. apply st_assigntH_H. apply v_c. reflexivity. Qed.
Example test_step_11:forall hp PC,
tassign tH (tcon 1) / hp ==PC=> tH / hp.
Proof. intros. apply st_assignHP. apply v_c. Qed.
Example test_step_12:forall hp,
tapp (tassign (tloc (an int L) None)(tcon 1))(tderef (tloc (an int H) None)) / hp
==H=>*
tH / hp.
Proof. intros.
apply Multi_step with (y:=(tapp tH (tderef (tloc (an int H) None)),hp)).
apply st_app1. apply st_assigntH_H. apply v_c. reflexivity.
apply Multi_step with (y:=(tapp tH tH,hp)).
apply st_app2. apply v_H. apply st_derefloctH.
apply Multi_step with (y:=(tH,hp)).
apply st_apptH. apply v_H.
apply Multi_refl.
Qed.
Example test_step_13:forall PC hp,
tref (an int H)(tapp tH (tcon 0)) / hp
==PC=>*
tloc (an int H) None / hp.
Proof. intros.
apply Multi_step with (y:=(tref (an int H)(tH),hp)).
apply st_ref. apply st_apptH. apply v_c.
apply Multi_step with (y:=(tloc (an int H) None,hp)).
apply st_reftH. apply v_H. left. reflexivity.
apply Multi_refl.
Qed.
Example test_step_14:forall hp,
tderef (tref (an int L)(tcon 0)) / hp
==H=>*
tH / hp.
Proof. intros.
apply Multi_step with (y:=(tderef (tloc (an int L) None),hp)).
apply st_deref. apply st_reftH. apply v_c. right. left. reflexivity.
apply Multi_step with (y:=(tH,hp)).
apply st_derefloctH. apply Multi_refl.
Qed.
Example test_step_15:forall hp,
tassign (tref (an int L) tH)(tapp tH (tcon 0)) / hp
==L=>*
tunit / hp.
Proof. intros.
apply Multi_step with (y:=(tassign(tloc (an int L) None)(tapp tH (tcon 0)),hp)).
apply st_assign1. apply st_reftH. apply v_H. left. reflexivity.
apply Multi_step with (y:=(tassign (tloc (an int L) None) tH,hp)).
apply st_assign2. apply v_l. apply st_apptH. apply v_c.
apply Multi_step with (y:=(tunit,hp)).
apply st_assigntH_L. apply v_H. reflexivity. left. reflexivity.
apply Multi_refl.
Qed.
(**
Note we might thought that in [LowLang],the securtiy context can be freely modified
if we know that some configuration is reducible under some security context.
This is,however,not the case. Consider the following reduction under high
security context where a high cell is being over-written by a high value,
tassign (tloc (an int L) None)(tcon 1) / hp
==H=>
tH / hp.
If we change the security context to low, we suddenly have a stuck configuration,
tassign (tloc (an int L) None)(tcon 1) / hp ==L=> ?.
Now how about the other way round, can we argue that if a configuration is reducible
under low security context is also reducible under high security context?
The answer is still no.
Consider the following example where a low cell is being over-written by a low value,
tassign (tloc (an int L) (Some n))(tcon 1)
==L=>
tunit / heap_replace n (tcon 1,an int L) hp,where n < length hp.
Now if we change the security context to H then we get a stuck term,
tassign (tloc (an int L) (Some n))(tcon 1)
==H=>?.
In conclusion, since in [LowLang] we donot care for the cases where either a low
cell is being over-written by a high value or a high cell is being written by a
low value,the security context is not allowed to be changed at all even though we
have on our hands a reducible configuration under some security context.
*)
(*some stuck terms in [LowLang]*)
Definition stuck_term (s:tm) (hp:heap) (PC:Sec) : Prop :=
(~exists e', step (s,hp) PC e') /\ (~value s).
Lemma lt_same_F' : forall n m,
S n <= S m -> n <= m.
Proof. intros. generalize dependent n. induction m.
intros. destruct n. apply le_n. inversion H0. inversion H2.
intros. inversion H0. apply le_n. apply le_S. apply IHm in H2.
apply H2. Qed.
Lemma lt_same_F:forall n,
n < n -> False.
Proof. intros. induction n. inversion H0. unfold lt in H0. unfold lt in IHn.
apply lt_same_F' in H0. apply IHn in H0. inversion H0. Qed.
Example test_stuck_term_1:forall hp,
stuck_term (tassign (tloc (an int L) None)(tcon 1)) hp L.
Proof. intros. split. intros contra. inversion contra. inversion H0.
subst. inversion H0. subst. inversion H10. inversion H1. inversion H1.
subst. inversion H7. inversion H6. inversion H7. intros contra. inversion contra.
Qed.
Lemma test_stuck_term_2':forall {A:Type} (hp:list A),
hp <> hp -> False.
Proof. intros. apply H0. reflexivity.
Qed.
Example test_stuck_term_2:forall hp,
hp <> nil ->
stuck_term (tassign (tloc (an int L) (Some 0))(tcon 1)) hp H.
Proof. intros. split. intros contra. inversion contra. inversion H1.
inversion H11. inversion H13. inversion H7. inversion H8.
intros contra. inversion contra.
Qed.
Lemma not_equal_nat:forall (n:nat),
n <> n -> False.
Proof. intros. assert (n=n). reflexivity. apply H0 in H1.
inversion H1.
Qed.
(*typing rule*)
(*some auxiliary functions*)
Definition joinTs (T:Ty)(b:Sec) : Ty :=
match T , b with
| an rt s , L => an rt s
| an rt s , H => an rt H
end.
Definition joins (b1:Sec) (b2:Sec): Sec :=
match b1 with
| L => b2
| H => H
end.
(*typing relation*)
(**
Regarding the typing relation in [LowLang],all terms except for [tH] can be
typed with both low and high security level while [tH] can only be typed with
high security level. The typing relation itself is similar to that in [SecLang]
which consists of the programme counter,pc,the tying context,Gamma,the heap typing
,HT,the term,and the related type.
There are three cases needed discussion,
a. [t_H]
[tH] can be typed under all [pc],[Gamma],[HT],and [rt] as follows,
has_type pc Gamma HT tH (an rt H)
b. [t_loc]
Recall that in [LowLang] we only store low terms in the heap,hp,whose address,n,
satisfies that [n < length hp] while all high terms in the heap are indicated via
their address as [None]. Since the heap_typing,HT,should correspond to
the heap,hp,in a consistent way,when we type location,[tloc T N],we should consider
both reference to low terms where the referred loction is smaller than the length
of the heap_typing and high terms where the referred location is simply [None],
b.1. [t_loc_L]:forall n HT T pc Gamma,
n < length HT ->
heap_Tlookup n HT = Some T ->
has_type pc Gamma HT (tloc T (Some n))(an (ref T) L)
b.2. [t_loc_H]:forall pc Gamma HT rt,
has_type pc Gamma HT (tloc (an rt H) None)(an (ref (an rt H)) L)
c. [t_ref]
Recall the typing rule for allocation in [SecLang],the label of the allocation joined
with the programme counter must be smaller than the label of the referred type.
Such restriction still applies when we try to type allocation in [LowLang],
where the label of the allocation joined by [pc] has to be smaller than the label of
the referred type,
forall pc Gamma HT t T,
has_type pc Gamma HT t T ->
subsum_r pc (labelT T) ->
has_type pc Gamma HT (tref T t)(an (ref T) L)
*)
Inductive has_type : Sec -> context -> heap_Ty -> tm -> Ty -> Prop :=
| t_var : forall pc Gamma HT x T,
Gamma x = Some T ->
has_type pc Gamma HT (tvar x) T
| t_con : forall pc Gamma HT n,
has_type pc Gamma HT (tcon n) (an int L)
| t_unit: forall pc Gamma HT,
has_type pc Gamma HT tunit (an unit L)
(*special case*)
| t_H:forall pc Gamma HT rt,
has_type pc Gamma HT tH (an rt H)
(*special case*)
| t_loc_L:forall n HT T pc Gamma,
heap_Tlookup n HT = Some T ->
has_type pc Gamma HT (tloc T (Some n))(an (ref T) L)
| t_loc_H:forall pc Gamma HT rt,
has_type pc Gamma HT (tloc (an rt H) None) (an (ref (an rt H)) L)
| t_abs: forall pc pc' Gamma HT x T e T',
has_type pc' (Cupdate Gamma x (Some T)) HT e T' ->
has_type pc Gamma HT (tabs x T e) (an (fn T pc' T') L)
| t_app: forall pc Gamma HT T1 T2 T2' b t1 t2,
has_type pc Gamma HT t1 (an (fn T1 (joins pc b) T2) b) ->
has_type pc Gamma HT t2 T1 ->
joinTs T2 b = T2' ->
has_type pc Gamma HT (tapp t1 t2) T2'
(*special case*)
| t_ref: forall pc Gamma HT t T,
has_type pc Gamma HT t T ->
subsum_r pc (labelT T) ->
has_type pc Gamma HT (tref T t) (an (ref T) L)
| t_deref: forall pc Gamma HT t T T' b,
has_type pc Gamma HT t (an (ref T) b) ->
T' = joinTs T b ->
has_type pc Gamma HT (tderef t) T'
| t_assign: forall pc Gamma HT t1 t2 b b' T,
b' = labelT T ->
subsum_r (joins pc b) b' ->
has_type pc Gamma HT t1 (an (ref T) b) ->
has_type pc Gamma HT t2 T ->
has_type pc Gamma HT (tassign t1 t2) (an unit b')
| t_sub: forall pc pc' Gamma HT t T T',
has_type pc Gamma HT t T ->
subsum_r pc' pc ->
T <: T' ->
has_type pc' Gamma HT t T'
.
(*some examples*)
Example has_type_1:forall pc Gamma HT,
has_type pc Gamma HT tH (an int H).
Proof. intros. apply t_H. Qed.
Example has_type_2:forall pc Gamma HT,
has_type pc Gamma HT tH (an unit H).
Proof. intros. apply t_H. Qed.
Example has_type_3:forall pc Gamma HT,
has_type pc Gamma HT tH (an (ref (an int L)) H).
Proof. intros. apply t_H. Qed.
Example has_type_4:forall pc Gamma HT,
has_type pc Gamma HT tH (an (fn (an int L) L (an unit H)) H).
Proof. intros. apply t_H. Qed.
Example has_type_5:forall pc HT,
has_type pc (Cupdate empty_context (Id 0) (Some(an int H))) HT
(tvar (Id 0))
(an int H).
Proof. intros. apply t_var. rewrite->Cupdate_eq. reflexivity. Qed.
Example has_type_6:forall pc Gamma HT n,
has_type pc Gamma HT (tcon n) (an int H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an int L). apply t_con.
apply sub_refl. apply subt_int. apply sub_LH. Qed.
Example has_type_7:forall pc Gamma HT,
has_type pc Gamma HT tunit (an unit H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an unit L). apply t_unit.
apply sub_refl. apply subt_unit. apply sub_LH. Qed.
Example has_type_8:forall pc Gamma,
has_type pc Gamma [an int L]
(tloc (an int L) (Some 0))
(an (ref (an int L)) H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an (ref (an int L)) L). apply t_loc_L.
reflexivity. apply sub_refl. apply subt_ref. apply sub_LH. Qed.
Example has_type_9:forall pc Gamma rt,
has_type pc Gamma []
(tloc (an rt H) None)
(an (ref (an rt H)) H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an (ref (an rt H)) L). apply t_loc_H.
apply sub_refl. apply subt_ref. apply sub_LH. Qed.
Example has_type_10:forall Gamma HT,
has_type L Gamma HT
(tref (an int H) (tcon 0))
(an (ref (an int H)) H).
Proof. intros. apply t_sub with (pc:=L)(T:=an (ref (an int H)) L). apply t_ref.
apply t_sub with (pc:=L)(T:=an int L). apply t_con. apply sub_refl. apply subt_int. apply sub_LH.
apply sub_LH. apply sub_refl. apply subt_ref. apply sub_LH.
Qed.
Example has_type_10':forall Gamma HT,
has_type H Gamma HT
(tref (an int H) tH)
(an (ref (an int H)) H).
Proof. intros. apply t_sub with (pc:=H)(T:=an (ref (an int H)) L). apply t_ref. apply t_H. apply sub_refl.
apply sub_refl. apply subt_ref. apply sub_LH.
Qed.
Example has_type_11:forall Gamma HT,
has_type L Gamma HT
(tref (an int L)(tcon 0))
(an (ref (an int L)) L).
Proof. intros. apply t_ref. apply t_con. apply sub_refl.
Qed.
Example has_type_12:forall Gamma HT,
has_type L Gamma HT
(tref (an int L)(tcon 0))
(an (ref (an int L)) H).
Proof. intros. apply t_sub with (pc:=L)(T:=an (ref (an int L)) L). apply t_ref. apply t_con.
apply sub_refl. apply sub_refl. apply subt_ref. apply sub_LH.
Qed.
Example has_type_13:forall Gamma HT pc,
has_type pc Gamma HT
(tabs (Id 0)(an unit H)(tref (an int H)(tcon 0)))
(an (fn (an unit H) H (an (ref (an int H)) L)) H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an (fn (an unit H) H (an (ref (an int H)) L)) L).
apply t_abs. apply t_ref. apply t_sub with (pc:=H)(T:=an int L). apply t_con.
apply sub_refl. apply subt_int. apply sub_LH. apply sub_refl. apply sub_refl.
apply subt_fn. apply sub_LH. apply sub_refl. apply subt_unit. apply sub_refl.
apply subt_ref. apply sub_refl. Qed.
Example has_type_14:forall Gamma HT,
has_type L Gamma HT
(tapp (tabs (Id 0)(an int H)(tvar (Id 0)))(tcon 0))
(an int H).
Proof. intros. apply t_app with (T1:=an int H)(T2:=an int H)(b:=H).
simpl. apply t_sub with (pc:=L)(T:=an (fn (an int H) H (an int H)) L).
apply t_abs. apply t_var. rewrite->Cupdate_eq. reflexivity. apply sub_refl.
apply subt_fn. apply sub_LH. apply sub_refl. apply subt_int. apply sub_refl.
apply subt_int. apply sub_refl. apply t_sub with (pc:=L)(T:=an int L). apply t_con.
apply sub_refl. apply subt_int. apply sub_LH. reflexivity. Qed.
Example has_type_15:forall Gamma HT,
has_type L Gamma HT
(tapp (tabs (Id 0)(an int H)(tvar (Id 0)))(tcon 0))
(an int H).
Proof. intros. apply t_app with (T1:=an int H)(T2:=an int H)(b:=L).
apply t_abs. apply t_var. rewrite->Cupdate_eq. reflexivity. apply t_sub with (pc:=L)(T:=an int L).
apply t_con. apply sub_refl. apply subt_int. apply sub_LH. reflexivity. Qed.
Example has_type_15':forall Gamma HT,
has_type L Gamma HT
(tapp tH (tcon 0))
(an int H).
Proof. intros. apply t_app with (T1:=an int L)(T2:=an int L)(b:=H). apply t_H. apply t_con.
reflexivity.
Qed.
Example has_type_16:forall pc Gamma,
has_type pc Gamma [an int L]
(tderef (tloc (an int L) (Some 0)))
(an int H).
Proof. intros. apply t_deref with (T:=an int L)(b:=H). apply t_sub with (pc:=pc)(T:=an (ref (an int L)) L).
apply t_loc_L. reflexivity. apply sub_refl. apply subt_ref. apply sub_LH. reflexivity.
Qed.
Example has_type_17:forall pc Gamma,
has_type pc Gamma [an int L]
(tderef (tloc (an int L) (Some 0)))
(an int L).
Proof. intros. apply t_deref with (T:=an int L)(b:=L). apply t_loc_L. reflexivity. reflexivity.
Qed.
Example has_type_18:forall pc Gamma rt,
has_type pc Gamma []
(tderef (tloc (an rt H) None))
(an rt H).
Proof. intros. apply t_deref with (T:=an rt H)(b:=L). apply t_loc_H. reflexivity.
Qed.
Example has_type_19:forall pc Gamma rt,
has_type pc Gamma []
(tderef (tloc (an rt H) None))
(an rt H).
Proof. intros. apply t_deref with (T:=an rt H)(b:=H). apply t_sub with (pc:=pc)(T:=an (ref (an rt H)) L).
apply t_loc_H. apply sub_refl. apply subt_ref. apply sub_LH. reflexivity.
Qed.
Example has_type_19':forall pc Gamma rt,
has_type pc Gamma []
(tderef tH)
(an rt H).
Proof. intros. apply t_deref with (T:=an rt L)(b:=H). apply t_H. reflexivity.
Qed.
Example has_type_20:forall Gamma HT,
has_type H Gamma HT
(tassign (tref (an int H)(tcon 0))(tcon 1))
(an unit H).
Proof. intros. apply t_assign with (b:=L)(T:=an int H). reflexivity. apply sub_refl.
apply t_ref. apply t_sub with (pc:=H)(T:=an int L). apply t_con. apply sub_refl.
apply subt_int. apply sub_LH. apply sub_refl. apply t_sub with (pc:=H)(T:=an int L).
apply t_con. apply sub_refl. apply subt_int. apply sub_LH. Qed.
Example has_type_21:forall Gamma HT,
has_type L Gamma HT
(tassign (tref (an int L)(tcon 0))(tcon 1))
(an unit L).
Proof. intros. apply t_assign with (b:=L)(T:=an int L). reflexivity. apply sub_refl.
apply t_ref. apply t_con. apply sub_refl. apply t_con.
Qed.
Example has_type_21':forall Gamma HT,
has_type L Gamma HT
(tassign tH (tcon 1))
(an unit H).
Proof. intros. apply t_assign with (b:=H)(T:=an int H). reflexivity. apply sub_refl. apply t_H.
apply t_sub with (pc:=L)(T:=an int L). apply t_con. apply sub_refl. apply subt_int. apply sub_LH.
Qed.
(*###inversion of [has_type]###*)
(*inversion of [has_type pc Gamma HT tH T]*)
Lemma inversion_tH:forall pc Gamma HT T,
has_type pc Gamma HT tH T ->
exists rt,
(an rt H) <: T.
Proof. intros. remember tH as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
exists rt. destruct rt. apply subt_int. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. apply subt_unit. apply sub_refl. apply subt_ref. apply sub_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H3. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tvar x) T]*)
Lemma inversion_tvar: forall pc Gamma HT x T,
has_type pc Gamma HT (tvar x) T ->
exists T0, (Gamma x = Some T0)/\(T0 <: T).
Proof. intros. remember (tvar x) as t. induction H0.
inversion Heqt. subst. exists T. split. apply H0. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x0. split. inversion H3.
apply H4. inversion H3. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tabs x T1 e b) T]*)
Lemma inversion_tabs: forall pc Gamma HT x T1 T e,
has_type pc Gamma HT (tabs x T1 e) T ->
exists T1', exists T2, exists T2', exists pc', exists pc'', exists pc''', exists b,
(has_type pc' Gamma HT (tabs x T1 e) (an (fn T1 pc'' T2) L)) /\
(has_type pc'' (Cupdate Gamma x (Some T1)) HT e T2) /\(subsum_r pc''' pc'')/\(subsum_r pc pc')/\
(T1'<:T1)/\(T2<:T2')/\(subsum_r L b)/\((an (fn T1' pc''' T2') b) <: T).
Proof. intros. remember (tabs x T1 e) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. subst.
exists T1. exists T'. exists T'. exists pc. exists pc'. exists pc'. exists L. split. apply t_abs. apply H0.
split. apply H0. split. apply sub_refl. split. apply sub_refl. split. apply subtyping_refl. split. apply subtyping_refl.
split. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply subtyping_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x0.
inversion H4. exists x1. inversion H5. exists x2. inversion H6. exists x3. inversion H7. exists x4. inversion H8. exists x5. inversion H9.
exists x6. split. apply t_abs. apply H10. split. apply H10. split. apply H10. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x3).
apply H1. apply H10. split. apply H10. split. apply H10. split. apply H10. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H10. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tcon n b) T]*)
Lemma inversion_tcon: forall pc Gamma HT T n,
has_type pc Gamma HT (tcon n) T ->
exists T', exists T'', exists b,
(T' = an int L)/\(T'' = an int b)/\(subsum_r L b)/\(T'' <: T).
Proof.
intros. remember (tcon n) as t. induction H0.
inversion Heqt. inversion Heqt. subst. exists (an int L). exists (an int L).
exists L. split. reflexivity. split. reflexivity. split. apply sub_refl.
apply subt_int. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tunit b) T]*)
Lemma inversion_tunit:forall pc Gamma HT T,
has_type pc Gamma HT tunit T ->
exists T', exists T'', exists b,
(T'=an unit L)/\(T''=an unit b)/\(subsum_r L b)/\(T''<:T).
Proof. intros. remember tunit as t. induction H0. inversion Heqt. inversion Heqt.
exists (an unit L). exists (an unit L). exists L. split. reflexivity. split. reflexivity. split.
apply sub_refl. apply subt_unit. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H5. apply H2.
Qed.
(**
inversion of [has_type pc Gamma HT (tloc T (Some n)) T']
where n <= length HT
*)
Lemma inversion_tloc_L:forall pc Gamma HT n T1 T,
has_type pc Gamma HT (tloc T1 (Some n)) T ->
exists T', exists T'', exists b,
(heap_Tlookup n HT = Some T1)/\(T'=an (ref T1) L)/\(T''=an (ref T1) b)/\(subsum_r L b)/\(T''<:T).
Proof. intros. remember (tloc T1 (Some n)) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. subst. exists (an (ref T1) L). exists (an (ref T1) L). exists L. split.
apply H0. split. reflexivity. split. reflexivity. split. apply sub_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt.
exists x. inversion H3. exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5. split. apply H5.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tloc T None) T']*)
Lemma inversion_tloc_H:forall pc Gamma HT T1 T,
has_type pc Gamma HT (tloc T1 None) T ->
exists T', exists T'', exists b, exists rt,
(T1=an rt H)/\
(T'=an (ref (an rt H)) L)/\(T''=an (ref (an rt H)) b)/\(subsum_r L b)/\(T''<:T).
Proof. intros. remember (tloc T1 None) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. subst. exists (an (ref (an rt H)) L). exists (an (ref (an rt H)) L). exists L. exists rt. split. reflexivity. split. reflexivity. split. reflexivity.
split. apply sub_refl. apply subtyping_refl. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x.
inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2. split. apply H6. split. apply H6. split. apply H6. split. apply H6.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H6. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tapp t1 t2) T]*)
Lemma inversion_tapp: forall pc Gamma HT t1 t2 T2,
has_type pc Gamma HT (tapp t1 t2) T2 ->
exists T1', exists T2', exists b', exists T1'', exists T1''', exists T2'', exists b'', exists pc', exists sp', exists sp'',
(sp'=joins pc' b')/\has_type pc' Gamma HT t1 (an (fn T1' sp' T2') b')/\((an (fn T1' sp' T2') b')<:(an (fn T1'' sp'' T2'') b''))/\
(has_type pc' Gamma HT t2 T1''')/\(T1''' <: T1'')/\(subsum_r pc pc')/\
((joinTs T2'' b'')<:T2).
Proof. intros. remember (tapp t1 t2) as t. induction H0.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
subst. exists T1. exists T2. exists b. exists T1. exists T1. exists T2. exists b. exists pc. exists (joins pc b). exists (joins pc b). split. reflexivity.
split. apply H0_. split. apply subtyping_refl. split. apply H0_0. split. apply subtyping_refl. split. apply sub_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2.
inversion H6. exists x3. inversion H7. exists x4. inversion H8. exists x5. inversion H9. exists x6. inversion H10. exists x7. inversion H11. exists x8.
split. apply H12. split. apply H12. split. apply H12. split. apply H12. split. apply H12. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x6). apply H1. apply H12. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H12. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tref T1 t b) T]*)
Lemma inversion_tref:forall pc Gamma HT T1 T t,
has_type pc Gamma HT (tref T1 t) T ->
exists pc', exists T1', exists T1'', exists b,
(subsum_r L b)/\
((an (ref T1) b)<:T)/\
(has_type pc' Gamma HT t T1')/\(T1' <: T1'')/\(subsum_r pc pc')/\(T1''<:T1)/\
(subsum_r pc' (labelT T1')).
Proof. intros. remember (tref T1 t) as e. induction H0. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst.
exists pc. exists T1. exists T1. exists L. split. apply sub_refl. split. apply subtyping_refl.
split. apply H0. split. apply subtyping_refl. split. apply sub_refl. split. apply subtyping_refl. apply H1.
inversion Heqe. inversion Heqe. apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0.
inversion H4. exists x1. inversion H5. exists x2. split. apply H6. split.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H6. apply H2. split. apply H6.
split. apply H6. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x). apply H1. apply H6. split. apply H6.
apply H6.
Qed.
(*inversion of [has_type pc Gamma HT (tderef t) T]*)
Lemma inversion_tderef:forall pc Gamma HT t T,
has_type pc Gamma HT (tderef t) T ->
exists pc', exists T1, exists b', exists b'',
has_type pc' Gamma HT t (an (ref T1) b')/\(subsum_r b' b'')/\
((joinTs T1 b'')<:T)/\(subsum_r pc pc').
Proof. intros. remember (tderef t) as e. induction H0. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst. exists pc. exists T. exists b. exists b. split. apply H0. split.
apply sub_refl. split. apply subtyping_refl. apply sub_refl. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4. exists x1.
inversion H5. exists x2. split. apply H6. split. apply H6. split. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H6. apply H2. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6.
Qed.
(*inversion of [has_type pc Gamma HT (tassign t1 t2) T]*)
Lemma inversion_tassign:forall pc Gamma HT t1 t2 T,
has_type pc Gamma HT (tassign t1 t2) T ->
exists pc',exists T1, exists T1', exists b,
has_type pc' Gamma HT (tassign t1 t2)(an unit (labelT T1))/\
has_type pc' Gamma HT t1 (an (ref T1) b)/\
has_type pc' Gamma HT t2 T1'/\
(T1'<:T1)/\(subsum_r pc pc')/\(subsum_r (joins pc' b)(labelT T1))/\
((an unit (labelT T1))<:T).
Proof. intros. remember (tassign t1 t2) as t. induction H0. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. subst. exists pc.
exists T. exists T. exists b. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1.
apply H0_. apply H0_0. split. apply H0_. split. apply H0_0. split. apply subtyping_refl. split.
apply sub_refl. split. apply H1. apply subtyping_refl. apply IHhas_type in Heqt.
inversion Heqt. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2.
split. apply H6. split. apply H6. split. apply H6. split. apply H6. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6. split. apply H6. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H6. apply H2.
Qed.
(*#############################*)
(*some examples of ill-typed terms*)
Example ill_typed_1:forall pc HT,
~has_type pc empty_context HT
(tvar (Id 0))
(an int L).
Proof. intros. intros contra. apply inversion_tvar in contra. inversion contra. inversion H0.
inversion H1.
Qed.
Example ill_typed_2:forall pc Gamma HT,
~has_type pc Gamma HT
(tcon 0)
(an unit H).
Proof. intros. intros contra. apply inversion_tcon in contra. inversion contra. inversion H0. inversion H1.
inversion H2. inversion H4. inversion H6. subst. inversion H8.
Qed.
Example ill_typed_3:forall pc Gamma HT,
~has_type pc Gamma HT
tunit
(an int L).
Proof. intros. intros contra. apply inversion_tunit in contra. inversion contra. inversion H0. inversion H1.
inversion H2. inversion H4. inversion H6. subst. inversion H8.
Qed.
Example ill_typed_4:forall pc Gamma HT rt,
~has_type pc Gamma HT
tH
(an rt L).
Proof. intros. intros contra. apply inversion_tH in contra. inversion contra. inversion H0. inversion H2.
inversion H5. inversion H2. inversion H2.
Qed.
Example ill_typed_5:forall pc Gamma,
~has_type pc Gamma [an int L]
(tloc (an int L) (Some 1))
(an (ref (an int L)) H).
Proof. intros. intros contra. apply inversion_tloc_L in contra. inversion contra.
inversion H0. inversion H1. inversion H2. simpl in H3. inversion H3.
Qed.
Example ill_typed_6:forall pc Gamma,
~has_type pc Gamma [an int L]
(tloc (an int H) (Some 0))
(an (ref (an int L)) H).
Proof. intros. intros contra. apply inversion_tloc_L in contra. inversion contra.
inversion H0. inversion H1. inversion H2. simpl in H3. inversion H3.
Qed.
Example ill_typed_7:forall pc Gamma HT,
~has_type pc Gamma HT
(tabs (Id 0)(an int L)(tvar (Id 0)))
(an int L).
Proof. intros. intros contra. apply inversion_tabs in contra. inversion contra.
inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5.
inversion H6. inversion H8. inversion H10. inversion H12. inversion H14. inversion H16.
inversion H18. inversion H20.
Qed.
Example ill_typed_8:forall pc Gamma HT,
~has_type pc Gamma HT
(tabs (Id 0)(an int H)(tref (an int L)(tcon 0)))
(an (fn (an int H) H (an (ref (an int L)) H)) H).
Proof. intros. intros contra. apply inversion_tabs in contra. inversion contra. inversion H0.
inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H8.
inversion H10. inversion H12. inversion H14. inversion H16. inversion H18. inversion H20. subst. destruct x4.
inversion H30. destruct x3. inversion H11. apply inversion_tref in H9. inversion H9. inversion H21. inversion H22.
inversion H23. inversion H24. inversion H27. inversion H29. inversion H34. inversion H36. inversion H38.
apply inversion_tcon in H33. inversion H33. inversion H41. inversion H42. inversion H43. inversion H45. inversion H47.
rewrite->H46 in H49. destruct x4. destruct r. destruct x3. inversion H37. destruct s. inversion H40. destruct x6. destruct r.
destruct s. inversion H35. inversion H52. inversion H39. inversion H52. inversion H39. inversion H39. inversion H39. inversion H49.
inversion H49. inversion H49.
Qed.
Example ill_typed_9:forall pc Gamma HT,
~has_type pc Gamma HT
(tapp (tcon 0)(tcon 1))
(an int L).
Proof. intros. intros contra. apply inversion_tapp in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. apply inversion_tcon in H12. inversion H12.
inversion H14. inversion H15. inversion H16. inversion H18. inversion H20. subst. inversion H22.
Qed.
Example ill_typed_10:forall Gamma HT,
~has_type H Gamma HT
(tapp (tabs (Id 0)(an int L)(tref (an int L)(tcon 0)))(tcon 1))
(an (ref (an int L)) L).
Proof. intros. intros contra. apply inversion_tapp in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. inversion H13. inversion H15. inversion H17. inversion H19.
destruct x6. inversion H0. inversion H20. simpl in H10. subst. apply inversion_tabs in H12. inversion H12. inversion H10. inversion H22. inversion H23.
inversion H24. inversion H25. inversion H26. inversion H27. inversion H29. inversion H31. inversion H33. destruct x10. inversion H34. inversion H35.
inversion H37. inversion H39. inversion H41. destruct x12. inversion H51. destruct x11. inversion H32. apply inversion_tref in H30. inversion H30. inversion H54.
inversion H55. inversion H56. inversion H57. inversion H59. inversion H61. inversion H63. inversion H65. inversion H67. destruct x12. destruct r. destruct s.
destruct x11. destruct r. destruct s. destruct x10. inversion H66. inversion H69. inversion H64. inversion H72. inversion H64. inversion H64. inversion H64.
inversion H68. inversion H72. inversion H68. inversion H68. inversion H68.
Qed.
Example ill_typed_11:forall Gamma HT,
~has_type H Gamma HT
(tref (an int L)(tcon 0))
(an (ref (an int L)) H).
Proof. intros. intros contra. apply inversion_tref in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H5. inversion H7.
inversion H9. inversion H11. inversion H13. destruct x1. destruct r. destruct s. destruct x0. destruct r. destruct s. destruct x. inversion H12. inversion H15.
inversion H10. inversion H18. inversion H10. inversion H10. inversion H10. inversion H14. inversion H18. inversion H14. inversion H14. inversion H14.
Qed.
Example ill_typed_12:forall pc Gamma,
~has_type pc Gamma []
(tderef (tloc (an int L) None))
(an int H).
Proof. intros. intros contra. apply inversion_tderef in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3.
apply inversion_tloc_H in H4. inversion H4. inversion H6. inversion H7. inversion H8. inversion H9. inversion H10.
Qed.
Example ill_typed_13:forall pc Gamma HT,
~has_type pc Gamma HT
(tassign (tcon 0)(tcon 1))
(an unit L).
Proof. intros. intros contra. apply inversion_tassign in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H5.
apply inversion_tcon in H6. inversion H6. inversion H8. inversion H9. inversion H10. inversion H12. inversion H14. subst. inversion H16.
Qed.
Example ill_typed_14:forall Gamma HT n,
~has_type H Gamma HT
(tassign (tloc (an int L) (Some n))(tcon 1))
(an unit H).
Proof. intros. intros contra. apply inversion_tassign in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H5.
inversion H7. inversion H9. inversion H11. destruct x. inversion H12. apply inversion_tloc_L in H6. inversion H6. inversion H14. inversion H15. inversion H16.
inversion H18. inversion H20. inversion H22. subst. inversion H24. subst. inversion H13. simpl in H19. inversion H19.
Qed.
(**
Properties of [LowLang],
a. Determinism
b. ...
*)
(*Determinism*)
Theorem determinism: forall t t' t'' hp hp' hp'' PC,
t / hp ==PC=> t' / hp' ->
t / hp ==PC=> t'' / hp'' ->
(t' = t''/\hp' = hp'').
Proof. intros t. induction t.
Case ("tvar").
intros. inversion H0.
Case ("tcon").
intros. inversion H0.
Case ("tabs").
intros. inversion H0.
Case ("tapp").
intros. inversion H0. inversion H1. subst. inversion H9. subst. split.
reflexivity. reflexivity. subst. inversion H13. subst. inversion H6. subst.
inversion H16. subst. inversion H16. subst. inversion H16. subst. inversion H16. subst. inversion H16. subst.
inversion H9. subst.
inversion H1. subst. inversion H6. subst.
apply IHt1 with (t':=t1')(t'':=t1'0)(hp'':=hp'') in H6. inversion H6. subst. split. reflexivity.
reflexivity. apply H7. subst. inversion H7. subst. inversion H6. subst. inversion H6. subst. inversion H6.
subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H1. subst. inversion H7.
subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9.
subst. inversion H6. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H7. subst.
apply IHt2 with (t':=t2')(t'':=t2'0)(hp'':=hp'')in H9. inversion H9. subst. split. reflexivity. reflexivity.
apply H11. subst. inversion H7. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst.
inversion H9. subst. inversion H1. subst. inversion H7. subst. inversion H6. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst.
inversion H10. subst. inversion H10. subst. split. reflexivity. reflexivity.
Case ("tunit").
intros. inversion H0.
Case ("tref").
intros. inversion H0. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H20.
apply H9 in H2. inversion H2. inversion H2. inversion H3. rewrite->H10 in H3. inversion H3. subst.
inversion H7. subst.
inversion H17. subst. inversion H17. subst. inversion H17. subst. inversion H17. subst. inversion H17. subst.
inversion H1. subst. inversion H9. apply H11 in H2. inversion H2. inversion H2. inversion H3. rewrite->H12 in H3. inversion H3.
split. reflexivity. reflexivity. subst. inversion H6. subst.
inversion H9. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H1. subst. inversion H8. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst.
inversion H6. subst. inversion H7. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst.
inversion H6. subst.
specialize (IHt t'0 t' hp hp' hp''). apply IHt in H6.
inversion H6. subst. split. reflexivity. reflexivity. apply H7.
Case ("tderef").
intros. inversion H0. inversion H1. subst. inversion H9. subst. split. reflexivity. reflexivity. subst. inversion H10. subst. inversion H12. subst.
inversion H10. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H5. subst. inversion H1. subst. inversion H5. subst.
inversion H5. subst.
apply IHt with (t':=t'0)(t'':=t')(hp'':=hp'') in H5. inversion H5. subst. split. reflexivity. reflexivity. apply H6. subst. inversion H5. subst.
inversion H1. subst. inversion H5. split. reflexivity. reflexivity.
Case ("tloc").
intros. inversion H0.
Case ("tassign").
intros. inversion H0. inversion H1. subst. inversion H13. subst. split. reflexivity. reflexivity. subst. inversion H13. subst. inversion H11. inversion H2.
subst. inversion H13. subst. inversion H17. subst. inversion H9. subst.
inversion H20. subst. inversion H20. subst. inversion H20. subst. inversion H20.
subst. inversion H20. subst. inversion H1. subst. split. reflexivity. reflexivity.
subst. inversion H11. subst. inversion H6. subst. inversion H7. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11.
subst. inversion H1. subst. inversion H10. subst. split. reflexivity. reflexivity. subst. inversion H7. subst. inversion H6. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst.
inversion H10. subst. inversion H10. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H7. subst. inversion H6. subst.
inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H1. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6.
subst.
specialize (IHt1 t1' t1'0 hp hp' hp'' PC). apply IHt1 in H6. inversion H6. subst.
split. reflexivity. reflexivity. apply H7. subst. inversion H7. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst.
inversion H1. subst.
inversion H11. subst. inversion H0. inversion H7. subst. inversion H15. subst. inversion H0. inversion H7. subst. inversion H15. subst. inversion H0. inversion H7. subst. inversion H15. subst.
inversion H0. inversion H7. subst. inversion H15. subst. inversion H0. inversion H7. subst. inversion H15. subst. inversion H8. subst.
inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H7. subst. inversion H9.
subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H0. subst. inversion H8. subst. inversion H7. subst.
inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H6. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H7. subst.
specialize (IHt2 t2' t2'0 hp hp' hp'' PC). apply IHt2 in H9. inversion H9. subst. split. reflexivity. reflexivity. apply H11.
Case ("tH").
intros. inversion H0.
Qed.
Theorem determinism_extended:forall x y z PC,
value (fst y) ->
value (fst z) ->
Multistep x PC y ->
Multistep x PC z ->
fst y = fst z.
Proof. intros. generalize dependent z. induction H2.
intros. inversion H0. inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst.
inversion H2. inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
intros. apply IHMulti. apply H0. apply H3. inversion H4. subst. inversion H3. subst.
destruct z0. simpl in H6. subst. inversion H1. destruct z0. simpl in H6. subst. inversion H1. destruct z0. simpl in H6. subst. inversion H1.
destruct z0. simpl in H6. subst. inversion H1. destruct z0. simpl in H6. subst. inversion H1.
subst. destruct x. destruct y. destruct y0. apply determinism with (t':=t0)(hp':=h0)(t'':=t1)(hp'':=h1)in H1. inversion H1. subst.
apply H6. apply H5.
Qed.
End LowLang.
Module Correspondence.
(*Projection function*)
(*a. projection of term*)
Fixpoint project_e (e : SecLang.tm) : LowLang.tm :=
match e with
(*variables*)
| SecLang.tvar x => LowLang.tvar x
(*constants*)
| SecLang.tcon n L => LowLang.tcon n
| SecLang.tcon n H => LowLang.tH
(*protects*)
| SecLang.tprot L e' => project_e e'
| SecLang.tprot H e' => LowLang.tH
(*abstractions*)
| SecLang.tabs x T e L => LowLang.tabs x T (project_e e)
| SecLang.tabs x T e H => LowLang.tH
(*applications*)
| SecLang.tapp t1 t2 => LowLang.tapp (project_e t1)(project_e t2)
(*unit*)
| SecLang.tunit L => LowLang.tunit
| SecLang.tunit H => LowLang.tH
(*allocation*)
| SecLang.tref T t L => LowLang.tref T (project_e t)
| SecLang.tref T t H => LowLang.tH
(*deallocation*)
| SecLang.tderef t => LowLang.tderef (project_e t)
(*location*)
| SecLang.tloc T N L => LowLang.tloc T N
| SecLang.tloc T N H => LowLang.tH
(*assignment*)
| SecLang.tassign t1 t2 => LowLang.tassign (project_e t1)(project_e t2)
end.
(*some lemma regarding [project_e]*)
Lemma project_e_subst:forall x v e,
SecLang.value v ->
project_e (SecLang.subst x v e) = LowLang.subst x (project_e v)(project_e e).
Proof. intros. generalize dependent x. generalize dependent v. induction e.
Case ("tvar"). intros. simpl. remember (beq_id x i) as CC. destruct CC. reflexivity.
reflexivity.
Case ("tprot"). intros. simpl. destruct s. apply IHe. apply H0. reflexivity.
Case ("tcon"). intros. simpl. destruct s. reflexivity. reflexivity.
Case ("tabs"). intros. simpl. destruct s. simpl. remember (beq_id x i) as CC. destruct CC.
reflexivity. apply IHe with(x:=x)in H0. rewrite<-H0. reflexivity.
reflexivity.
Case ("tapp"). intros. simpl. assert (SecLang.value v). apply H0. apply IHe1 with(x:=x)in H0.
apply IHe2 with(x:=x)in H1. rewrite->H0. rewrite->H1. reflexivity.
Case ("tunit"). intros. simpl. destruct s. reflexivity. reflexivity.
Case ("tref"). intros. simpl. destruct s. apply IHe with(x:=x)in H0. rewrite->H0. reflexivity.
reflexivity.
Case ("tderef"). intros. simpl. apply IHe with(x:=x)in H0. rewrite->H0. reflexivity.
Case ("tloc"). intros. simpl. destruct s. reflexivity. reflexivity.
Case ("tassign"). intros. simpl. assert (SecLang.value v). apply H0. apply IHe1 with(x:=x)in H0.
apply IHe2 with(x:=x)in H1. rewrite->H0. rewrite->H1. reflexivity.
Qed.
(*marked heap*)
Definition heap := list ((LowLang.tm*Ty)*(nat*nat)).
Definition emp_hp:= @nil ((LowLang.tm*Ty)*(nat*nat)).
(**
Note the marked heap is the projection of the heap in [SecLang] to a heap where
each of its member is marked with a pair of numbers indication the change of its
location in the heap
*)
(*Some examples*)
Check (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
(**
Note the above marked heap indicates that,
a. a Low constant in [SecLang] whose position on the heap is [0] before the
projection and [0] after the projection
b. another constant in [SecLang] whose position on the heap is [2] before the
projection and [1] after the projection
*)
(*heap_projection*)
(*firstly we generate a heap where every cell is marked according to its location on the heap*)
Fixpoint marked_heap' (hp:SecLang.heap)(n:nat) : list ((SecLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , 0 =>match h with
|(e,T)=>((e,T),(0,0)) :: (marked_heap' t 1)
end
| h :: t , n =>match h with
|(e,T)=>((e,T),(n,n)) :: (marked_heap' t (S n))
end
| nil , _ => nil
end.
(*some tests*)
Example test_marked_heap'_1:
marked_heap' ((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil) 0
= ((SecLang.tcon 6 L,an int L),(0,0)) :: ((SecLang.tcon 6 H,an int H),(1,1)) :: ((SecLang.tcon 5 L,an int L),(2,2)) :: nil.
Proof. simpl. reflexivity. Qed.
Example test_marked_heap'_2:
marked_heap' ((SecLang.tcon 0 L,an int L) :: (SecLang.tcon 1 L,an int L) :: nil) 0
= ((SecLang.tcon 0 L,an int L),(0,0)) :: ((SecLang.tcon 1 L,an int L),(1,1)) :: nil.
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [marked_heap']*)
Lemma n_plus_1:forall n,
n + 1 = S n.
Proof. intros n. induction n. reflexivity. rewrite->plus_Sn_m. rewrite->IHn.
reflexivity.
Qed.
Lemma marked_heap'_hd:forall h t n,
marked_heap' (h :: t) n = (h,(n,n)) :: (marked_heap' t (n+1)).
Proof. intros. generalize dependent h. generalize dependent t. induction n.
intros. simpl. destruct h. reflexivity.
intros. simpl. destruct h. rewrite->n_plus_1. reflexivity.
Qed.
(* then we get the marked heap with only low cells on it*)
Fixpoint marked_heap (hp:list ((SecLang.tm*Ty)*(nat*nat))) (n:nat): list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
|(a,b)=>match a with
| (e,T)=>match SecLang.label e with
| H =>marked_heap t (S n)
| L =>match b with
|(n1,n2)=>match a with
|(e,T)=>((project_e e,T),(n1,n2-n)) :: (marked_heap t n)
end
end
end
end
end
| nil => nil
end.
(*some test*)
Example test_marked_heap_1:
marked_heap (((SecLang.tcon 1 L,an int L),(0,0)) :: ((SecLang.tcon 2 H,an int H),(1,1)) :: ((SecLang.tcon 3 L,an int L),(2,2)) :: ((SecLang.tcon 4 H,an int H),(3,3)) :: ((SecLang.tcon 5 L,an int L),(4,4)) :: nil) 0
= (((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 3,an int L),(2,1)) :: ((LowLang.tcon 5,an int L),(4,2)) :: nil).
Proof. simpl. reflexivity.
Qed.
(*some lemmas regarding [marked_heap]*)
Lemma marked_heap_L:forall e T n1 n2 t n,
SecLang.label e = L ->
marked_heap (((e,T),(n1,n2)) :: t) n = ((project_e e,T),(n1,n2-n)) :: (marked_heap t n).
Proof. intros. simpl. rewrite->H0. reflexivity.
Qed.
Lemma marked_heap_mark_length:forall hp n1 n2 n3 n4,
length (marked_heap(marked_heap' hp n1)n2) = length (marked_heap(marked_heap' hp n3)n4).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. destruct n3. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. specialize (IHhp 1 n2 1 n4). rewrite->IHhp. reflexivity.
specialize (IHhp 1 (S n2) 1 (S n4)). rewrite->IHhp. reflexivity. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. specialize (IHhp 1 n2 (S (S n3)) n4). rewrite<-IHhp. reflexivity.
specialize (IHhp 1 (S n2)(S (S n3)) (S n4)). rewrite<-IHhp. reflexivity. destruct n3. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. specialize (IHhp (S (S n1)) n2 1 n4).
rewrite<-IHhp. reflexivity. specialize (IHhp (S (S n1)) (S n2) 1 (S n4)). rewrite<-IHhp.
reflexivity. simpl. remember (SecLang.label t) as BB. destruct BB. simpl. specialize (IHhp (S (S n1)) n2 (S (S n3)) n4).
rewrite<-IHhp. reflexivity. specialize (IHhp (S (S n1)) (S n2) (S (S n3)) (S n4)). rewrite<-IHhp.
reflexivity.
Qed.
(*look-up function regarding the marked heap*)
(**
Note: in the current segment, heaps are all marked and there are two ways of looking up
a value stored on a heap,
a. looking up via matching up query with some mark,[marked_heap_lookup]
b. looking up via the query indicating the position of some value stored on the heap
[].
*)
(*a*)
(**
The search is being done via looking for a match between a target and the first number
of some mark of the marked heap
*)
Fixpoint marked_heap_lookup (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))):(option (LowLang.tm*Ty)):=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) =>if beq_nat n1 n
then Some fst
else marked_heap_lookup n t
end
end
| nil => None
end.
(*extract the result of [marked_heap_lookup]*)
Definition marked_efst (p:option(LowLang.tm*Ty)) : option (LowLang.tm) :=
match p with
| None => None
| Some (t , T) => Some t
end.
(*b*)
(*heap_lookup*)
Fixpoint heap_lookup (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))):(option ((LowLang.tm*Ty)*(nat*nat))):=
match hp , n with
| nil , _ =>None
| h::t , 0 => Some h
| h::t , S n' =>heap_lookup n' t
end.
(*extract the result of [heap_lookup]*)
Definition efst (p:option((LowLang.tm*Ty)*(nat*nat))) : option (LowLang.tm) :=
match p with
| None => None
| Some ((t,T),N) => Some t
end.
(*the following block is regarding the "replace" function w.r.t. marked heap*)
(*#########################*)
(**
note that similar to the "lookup" functions defines in the current block,there are
two ways to replace a value on the marked heap,
a. we can either query for the first element of the mark attached to the value like
[return_smallest_match] to locate the value and then replace it
b. we can also firstly get the second value of the mark and then search for the value
on the indicated location directly essentially ignoring the marks on the heap
*)
(**
"a. marked_heap_replace"
*)
Fixpoint marked_heap_replace n (x:(LowLang.tm)*Ty) (hp:list ((LowLang.tm*Ty)*(nat*nat))): list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) =>if beq_nat n1 n
then (x,snd)::t
else h::(marked_heap_replace n x t)
end
end
| nil => nil
end.
(*some examples*)
Example test_marked_heap_replace_1:
marked_heap_replace 3 (LowLang.tcon 1,an int L) (((LowLang.tcon 0,an int L),(0,0)):: ((LowLang.tcon 2,an int L),(3,1)) :: ((LowLang.tunit,an unit L),(4,2)) :: nil)
= (((LowLang.tcon 0,an int L),(0,0)) :: ((LowLang.tcon 1,an int L),(3,1)) :: ((LowLang.tunit,an unit L),(4,2)) :: nil).
Proof. simpl. reflexivity.
Qed.
Example test_marked_heap_replace_2:
marked_heap_replace 2 (LowLang.tcon 2,an int L) (((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 1,an int L),(6,1))::nil)
= (((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 1,an int L),(6,1))::nil).
Proof. simpl. reflexivity.
Qed.
(*########*)
(*backhere*)
(*########*)
(*some lemmas related to [marked_heap_replace]*)
Lemma marked_heap_replace_same:forall hp n n1 n2 p,
n < n1 ->
marked_heap_replace n p (marked_heap(marked_heap' hp n1)n2)
=(marked_heap(marked_heap' hp n1)n2).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. destruct n.
apply LowLang.lt_same_F in H0. inversion H0. inversion H0.
simpl. remember (SecLang.label t) as BB. destruct BB. destruct n2.
simpl. destruct n. specialize (IHhp 0 (S (S n1)) 0 p). apply le_S in H0.
apply IHhp in H0. rewrite->H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC.
apply beq_nat_eq in HeqCC. subst. apply LowLang.lt_same_F in H0. inversion H0.
specialize (IHhp (S n) (S (S n1)) 0 p). apply le_S in H0. apply IHhp in H0. rewrite->H0.
reflexivity. simpl. destruct n. specialize (IHhp 0 (S (S n1)) (S n2) p). apply le_S in H0.
apply IHhp in H0. rewrite->H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC.
apply beq_nat_eq in HeqCC. rewrite->HeqCC in H0. apply LowLang.lt_same_F in H0. inversion H0.
specialize (IHhp (S n) (S (S n1)) (S n2) p). apply le_S in H0. apply IHhp in H0. rewrite->H0.
reflexivity. specialize (IHhp n (S (S n1)) (S n2) p). apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity.
Qed.
(**
"b. heap_replace"
*)
Fixpoint heap_replace n (x:(LowLang.tm)*Ty) (hp:list ((LowLang.tm*Ty)*(nat*nat))): list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| nil , _ =>nil
| h::t , 0 => match h with
|(fst,snd)=>(x,snd)::t
end
| h::t , S n' =>h :: (heap_replace n' x t)
end.
(*some examples*)
Example test_heap_replace_1:
heap_replace 2 (LowLang.tcon 1,an int L)(((LowLang.tcon 0,an int L),(7,0))::((LowLang.tcon 2,an int L),(8,1))::((LowLang.tcon 3,an int L),(9,2))::nil)
= (((LowLang.tcon 0,an int L),(7,0))::((LowLang.tcon 2,an int L),(8,1))::((LowLang.tcon 1,an int L),(9,2))::nil).
Proof. simpl. reflexivity.
Qed.
Example test_heap_replace_2:
heap_replace 3 (LowLang.tcon 1,an int L)(((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 2,an int L),(5,1))::((LowLang.tcon 3,an int L),(6,2))::nil)
= (((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 2,an int L),(5,1))::((LowLang.tcon 3,an int L),(6,2))::nil).
Proof. simpl. reflexivity.
Qed.
(*#########################*)
(*marked heap well-formed*)
(**
the property [marked_heap_well_formed] states that for each term on the marked heap
,it is well_formed given some natural number corresponding to the length of the
original heap in [SecLang]
*)
(*marked_heap well_formed*)
Inductive marked_heap_well_formed : list ((LowLang.tm*Ty)*(nat*nat)) -> nat -> Prop :=
| nil_mhwf:forall n,
marked_heap_well_formed nil n
| one_mhwf:forall t0 T p t n,
marked_heap_well_formed t n ->
LowLang.well_formed t0 n ->
marked_heap_well_formed (((t0,T),p) :: t) n.
(*some lemmas regarding [marked_heap_well_formed]*)
Lemma marked_heap_well_formed_shrink:forall hp a n,
marked_heap_well_formed (a :: hp) n ->
marked_heap_well_formed hp n.
Proof. intros. inversion H0. apply H3.
Qed.
(*finally we put [marked_hp'] and [marked_hp] together to get [project_hp]*)
Definition project_hp (hp:SecLang.heap) : list ((LowLang.tm*Ty)*(nat*nat)) :=
marked_heap (marked_heap' hp 0) 0.
(*some examples*)
Example test_project_hp_1:
project_hp ((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. compute. reflexivity. Qed.
(**
Note the following function decides whether or not two marked heaps have the same
marks. It will be useful later on for proving "Lemma two" in Lu's paper
*)
Fixpoint same_mark (hp1:list ((LowLang.tm*Ty)*(nat*nat)))(hp2:list ((LowLang.tm*Ty)*(nat*nat))) : bool :=
match hp1 , hp2 with
| (L1,(n1,m1)) :: t1 , (L2,(n2,m2)) :: t2 =>match beq_nat n1 n2 with
| true =>match beq_nat m1 m2 with
| true =>same_mark t1 t2
| false =>false
end
| false =>false
end
| nil , h :: t =>false
| h :: t , nil =>false
| nil , nil =>true
end.
(**
There is only one case where two marked heaps are considered to have the same marks,
a. each of their corresponding marks are the same
b. these two heaps involved have the same length
See the following examples
*)
Example test_same_mark_1:
same_mark (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(2,1)) :: ((LowLang.tcon 8,an int L),(5,2)) :: nil)(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(2,1)) :: ((LowLang.tcon 3,an int L),(5,2)) :: nil)
= true.
Proof. simpl. reflexivity.
Qed.
Example test_same_mark_2:
same_mark (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(2,1)) :: nil)(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(2,1)) :: ((LowLang.tcon 3,an int L),(5,2)) :: nil)
= false.
Proof. simpl. reflexivity.
Qed.
Example test_same_mark_3:
same_mark (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(2,1)) :: ((LowLang.tcon 8,an int L),(5,2)) :: nil)(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(2,1)) :: nil)
= false.
Proof. simpl. reflexivity.
Qed.
(*some lemmas regarding [same_mark]*)
Lemma same_mark_length:forall hp hp',
same_mark hp hp' = true ->
length hp = length hp'.
Proof. intros hp. induction hp.
intros. destruct hp'. reflexivity. simpl in H0. inversion H0. intros. destruct hp'.
destruct a. destruct p0. simpl in H0. inversion H0. destruct a. destruct p1. destruct p.
destruct p1. simpl. simpl in H0. remember (beq_nat n n1) as BB. destruct BB. remember (beq_nat n0 n2) as CC.
destruct CC. apply IHhp in H0. rewrite->H0. reflexivity. inversion H0. inversion H0.
Qed.
Lemma same_mark_refl:forall hp,
same_mark hp hp = true.
Proof. intros. induction hp. reflexivity. destruct a. destruct p0. simpl.
rewrite<-beq_nat_refl. rewrite<-beq_nat_refl. apply IHhp.
Qed.
Lemma same_mark_sym:forall hp1 hp2,
same_mark hp1 hp2 = true ->
same_mark hp2 hp1 = true.
Proof. intros. generalize dependent hp2. induction hp1.
intros. destruct hp2. reflexivity. simpl. destruct p. destruct p0. simpl in H0. inversion H0.
intros. destruct hp2. simpl. simpl in H0. destruct a. destruct p0. inversion H0.
simpl. destruct p. destruct p0. destruct a. destruct p1. remember (beq_nat n n1) as BB.
remember (beq_nat n0 n2) as CC. destruct BB. destruct CC. apply IHhp1. simpl in H0. rewrite->beq_nat_sym in HeqBB. rewrite->beq_nat_sym in HeqCC.
rewrite<-HeqBB in H0. rewrite<-HeqCC in H0. apply H0. simpl in H0. rewrite->beq_nat_sym in HeqBB. rewrite->beq_nat_sym in HeqCC. rewrite<-HeqBB in H0. rewrite<-HeqCC in H0.
inversion H0. simpl in H0. rewrite->beq_nat_sym in HeqBB. rewrite<-HeqBB in H0. inversion H0.
Qed.
Lemma same_mark_replace:forall hp1 hp2 hp3,
same_mark hp1 hp2 = true ->
same_mark hp1 hp3 = true ->
same_mark hp3 hp2 = true.
Proof. intros. generalize dependent hp2. generalize dependent hp3. induction hp1.
Case ("nil"). intros. destruct hp2. destruct hp3. reflexivity. simpl in H1. inversion H1. destruct hp3. simpl in H0. inversion H0.
simpl in H0. inversion H0.
Case ("h::t"). intros. destruct hp3. simpl in H1. inversion H1. destruct hp2. simpl in H0. destruct a. destruct p0. inversion H0.
destruct a. destruct p1. inversion H1. destruct hp2. simpl in H0. inversion H0. simpl. destruct p. destruct p0. destruct a. destruct p1. reflexivity.
simpl. destruct p. destruct p1. destruct p0. destruct p1. remember (beq_nat n n1) as BB. remember (beq_nat n0 n2) as CC. destruct BB. destruct CC.
destruct a. destruct p2. apply IHhp1. inversion H1. remember (beq_nat n3 n) as DD. destruct DD. remember (beq_nat n4 n0) as EE. destruct EE.
reflexivity. inversion H3. inversion H3.
inversion H0. remember (beq_nat n3 n1) as DD. destruct DD. remember (beq_nat n4 n2) as EE. destruct EE. reflexivity. inversion H3. inversion H3.
destruct a. destruct p2. simpl in H1. remember (beq_nat n3 n) as DD. destruct DD. remember (beq_nat n4 n0) as EE. destruct EE. apply beq_nat_eq in HeqEE.
simpl in H0. remember (beq_nat n3 n1) as FF. destruct FF. remember (beq_nat n4 n2) as GG. destruct GG. apply beq_nat_eq in HeqGG. rewrite->HeqEE in HeqGG. rewrite->HeqGG in HeqCC.
symmetry in HeqCC. apply beq_nat_false in HeqCC. assert (n2=n2). reflexivity. apply HeqCC in H2. inversion H2. inversion H0. inversion H0. inversion H1. inversion H1.
destruct a. destruct p2. simpl in H1. remember (beq_nat n3 n) as DD. destruct DD. apply beq_nat_eq in HeqDD. simpl in H0. remember (beq_nat n3 n1) as EE. destruct EE. apply beq_nat_eq in HeqEE.
rewrite->HeqDD in HeqEE. rewrite->HeqEE in HeqBB. symmetry in HeqBB. apply beq_nat_false in HeqBB. assert (n1=n1). reflexivity. apply HeqBB in H2. inversion H2.
inversion H0. inversion H1.
Qed.
(*#######try#########*)
Lemma same_mark_empty:forall hp n,
same_mark (marked_heap (marked_heap' hp n) n) [] = true ->
same_mark (marked_heap (marked_heap' hp (S n)) (S n)) [] = true.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. simpl in H0. destruct n. simpl in H0. remember (SecLang.label t) as BB. destruct BB.
inversion H0. simpl. rewrite<-HeqBB. apply IHhp in H0. apply H0. simpl. simpl in H0. remember (SecLang.label t) as BB.
destruct BB. inversion H0. apply IHhp in H0. apply H0.
Qed.
(*###################*)
(*some lemmas regarding [project_hp]*)
(**
Recall the way how we get our marked heap,
firstly we have a heap from [SecLang] and we mark each cell on the heap according
to its location on the heap;then for each cell we calculate the number of high cells
on its left and then subtract it from its mark giving us the location of the cell
after we discard the high cells;lastly we apply [project_e] to all the terms on
the marked heap.
*)
(**
Consider the following example,
suppose we have
hp = [L(1),H(2),L(3),H(4),L(5)] and hp' = [L(1),H(7),L(3),H(8),L(5)]
according to [project_hp] we have,
project_hp hp = [ 1, 3, 5] = project_hp hp'
0->0 2->1 4->2
Now,we prefix both hp and hp' by (L(8)) and as a result we have,
project_hp hp = [ 8, 1, 3, 5] = project_hp hp'
0->0 1->1 3->2 5->3
while if we prefix by (H(8)) we get,
project_hp hp = [ 1, 3, 5] = project_hp hp'
1->0 3->1 4->2
.
Note how the marks of the extended heap depends upon the label of the new cell.
If it is [L] then the marks of the rest of the heap is equal to the original
ones added by one or if [H] the marks of the original one is increased only in
their first element.
Sppose we define the following two functions,
[add_both_mark] which add every mark on the heap by one
and [add_fst_mark] which add the first element of every mark on the heap by one
then we have,
a.
project_hp (a::hp) = (a,(0,0)) :: add_both_mark (project_hp hp)
when the label of is [L];
b.
project_hp (a::hp) = add_fst_mark (project_hp hp)
when the label of hp is [H].
In what follows we firstly define [add_both_mark] and [add_fst_mark] and then prove the above
two equalities.
*)
(*###########*)
(*add_both_mark*)
Fixpoint add_both_mark (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
| (a , b) =>match b with
|(n1,n2) =>(a,(n1+1,n2+1)) :: (add_both_mark t)
end
end
| nil =>nil
end.
(*some example*)
Example test_add_both_mark_1:
add_both_mark (((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 3,an int L),(2,1)) :: ((LowLang.tcon 5,an int L),(4,2)) :: nil)
= (((LowLang.tcon 1,an int L),(1,1)) :: ((LowLang.tcon 3,an int L),(3,2)) :: ((LowLang.tcon 5,an int L),(5,3)) :: nil).
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [add_both_mark]*)
Lemma add_both_mark_hd:forall a n1 n2 t,
add_both_mark ((a,(n1,n2)) :: t) = (a,(n1+1,n2+1)) :: (add_both_mark t).
Proof. intros. simpl. reflexivity.
Qed.
Lemma Sn_n_plus_one:forall n,
S n = n + 1.
Proof. intros. induction n.
reflexivity. rewrite->plus_Sn_m. rewrite<-IHn.
reflexivity.
Qed.
Lemma n_minus_m_plus_one:forall n m,
m <= n ->
n - m + 1 = 1 + n - m.
Proof. intros. generalize dependent m. induction n.
Case ("nil"). intros. destruct m. reflexivity. inversion H0.
Case ("h::t"). intros. simpl. destruct m. rewrite<-Sn_n_plus_one.
reflexivity. destruct m. rewrite<-minus_n_O.
rewrite<-Sn_n_plus_one. reflexivity. apply LowLang.lt_snoc_1 in H0.
apply IHn in H0. rewrite->H0. rewrite->plus_comm. rewrite<-Sn_n_plus_one.
simpl. reflexivity.
Qed.
Lemma marked_heap_add_both_mark:forall hp n n',
n' <= n ->
add_both_mark (marked_heap (marked_heap' hp n) n')
=marked_heap (marked_heap' hp (n+1)) n'.
Proof. intros. generalize dependent n. generalize dependent n'. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
destruct a. remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl. specialize (IHhp n' (n+1)).
assert (n'<=n). apply H0. apply le_S in H0. rewrite->Sn_n_plus_one in H0. apply IHhp in H0. rewrite->H0.
rewrite->n_minus_m_plus_one. rewrite plus_comm. reflexivity. apply H1.
simpl. rewrite<-HeqBB. specialize (IHhp (S n') (n+1)). apply IHhp. apply SecLang.n_iff_Sn_left in H0.
rewrite<-Sn_n_plus_one. apply H0.
Qed.
Lemma marked_heap_add_both_mark_snoc:forall hp n1 n2 n3 n4 V T,
n2 <= n1 ->
add_both_mark (LowLang.snoc (marked_heap (marked_heap' hp n1)n2)((V,T),(n3,n4)))
=LowLang.snoc (marked_heap (marked_heap' hp (n1+1)) n2)((V,T),(S n3,S n4)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl. reflexivity.
Case ("h::t"). intros. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
destruct a. remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl.
assert (n1+1-n2=1+n1-n2). rewrite->plus_comm. reflexivity. rewrite->H1. clear H1.
assert (n2<=n1). apply H0. apply n_minus_m_plus_one in H0. rewrite->H0. specialize (IHhp (n1+1) n2 n3 n4 V T).
apply le_S in H1. rewrite->plus_comm in IHhp. simpl in IHhp. apply IHhp in H1.
rewrite->plus_comm. simpl. rewrite<-H1. reflexivity.
simpl. rewrite<-HeqBB. specialize (IHhp (n1+1) (S n2) n3 n4 V T). rewrite->plus_comm in IHhp. simpl in IHhp.
apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. rewrite->plus_comm. simpl. apply H0.
Qed.
Lemma add_both_mark_same_mark':forall hp hp',
same_mark hp hp' = true ->
same_mark (add_both_mark hp)(add_both_mark hp') = true.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct hp'. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct a. destruct p0. destruct hp'. inversion H0.
destruct p0. destruct p1. simpl. simpl in H0. remember (beq_nat n n1) as BB.
destruct BB. apply beq_nat_eq in HeqBB. rewrite->HeqBB. rewrite<-beq_nat_refl.
remember (beq_nat n0 n2) as CC. destruct CC. apply beq_nat_eq in HeqCC. rewrite->HeqCC.
rewrite<-beq_nat_refl. apply IHhp. apply H0. inversion H0. inversion H0.
Qed.
Lemma add_both_mark_same_mark:forall hp hp',
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (add_both_mark (project_hp hp))(add_both_mark (project_hp hp')) = true.
Proof. intros. apply add_both_mark_same_mark'. apply H0.
Qed.
(*add_fst_mark*)
Fixpoint add_fst_mark (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
| (a , b) =>match b with
|(n1,n2) =>(a,(n1+1,n2)) :: (add_fst_mark t)
end
end
| nil =>nil
end.
(*some example*)
Example test_add_fst_mark_1:
add_fst_mark (((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 3,an int L),(2,1)) :: ((LowLang.tcon 5,an int L),(4,2)) :: nil)
= (((LowLang.tcon 1,an int L),(1,0)) :: ((LowLang.tcon 3,an int L),(3,1)) :: ((LowLang.tcon 5,an int L),(5,2)) :: nil).
Proof. simpl. reflexivity. Qed.
Lemma marked_heap_add_fst_mark:forall hp n m,
m <= n ->
add_fst_mark (marked_heap (marked_heap' hp n) m)
=marked_heap (marked_heap' hp (n+1)) (m+1).
Proof. intros. generalize dependent n. generalize dependent m. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl. apply le_S in H0.
apply IHhp in H0. rewrite->Sn_n_plus_one in H0. assert (n+1-(m+1)=S n - S m). rewrite<-Sn_n_plus_one.
rewrite<-Sn_n_plus_one. reflexivity. rewrite->H1. simpl. rewrite->H0. reflexivity.
simpl. rewrite<-HeqBB. apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. rewrite->Sn_n_plus_one in H0.
rewrite->plus_Sn_m in H0. apply H0.
Qed.
Lemma marked_heap_add_fst_mark_snoc:forall hp n1 n2 n3 n4 V T,
n2 <= n1 ->
add_fst_mark (LowLang.snoc (marked_heap (marked_heap' hp n1)n2)((V,T),(n3,n4)))
=LowLang.snoc (marked_heap (marked_heap' hp (n1+1))(n2+1))((V,T),(S n3,n4)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. rewrite->plus_comm. simpl. reflexivity.
Case ("h::t"). intros. destruct a. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl. specialize (IHhp (n1+1) n2 n3 n4 V T).
rewrite->plus_comm in IHhp. simpl in IHhp. apply le_S in H0. apply IHhp in H0. rewrite->plus_comm. assert (1+n1+1=S (n1+1)). reflexivity.
rewrite->H1. clear H1. assert (1+n1=S n1). reflexivity. rewrite->H1. clear H1. rewrite<-H0.
assert (n2+1=S n2). rewrite->plus_comm. reflexivity. rewrite->H1. clear H1. simpl. reflexivity.
specialize (IHhp (n1+1) (n2+1) n3 n4 V T). apply SecLang.n_iff_Sn_left in H0.
assert (n1+1=S n1). rewrite->plus_comm. reflexivity. rewrite<-H1 in H0. clear H1.
assert (n2+1=S n2). rewrite->plus_comm. reflexivity. rewrite<-H1 in H0. clear H1. apply IHhp in H0.
simpl. rewrite<-HeqBB. rewrite->plus_comm in H0. simpl in H0. rewrite->plus_comm in H0. simpl in H0.
rewrite->plus_comm. simpl. apply H0.
Qed.
Lemma add_fst_mark_same_mark':forall hp hp',
same_mark hp hp' = true ->
same_mark (add_fst_mark hp)(add_fst_mark hp') = true.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct hp'. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct hp'. destruct a. destruct p0. inversion H0.
destruct a. destruct p. destruct p1. destruct p2. simpl. simpl in H0.
remember (beq_nat n n1) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB. rewrite<-beq_nat_refl. remember (beq_nat n0 n2) as CC. destruct CC.
apply IHhp. apply H0. inversion H0. inversion H0.
Qed.
Lemma add_fst_mark_same_mark:forall hp hp',
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (add_fst_mark (project_hp hp))(add_fst_mark (project_hp hp')) = true.
Proof. intros. apply add_fst_mark_same_mark'. apply H0.
Qed.
(*minus_snd_mark*)
Fixpoint minus_snd_mark (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
| (a , b) =>match b with
|(n1,n2) =>(a,(n1,n2-1)) :: (minus_snd_mark t)
end
end
| nil =>nil
end.
(*some example*)
Example test_minus_snd_mark_1:
minus_snd_mark (((LowLang.tcon 1,an int L),(0,0))::((LowLang.tcon 4,an int L),(3,1))::((LowLang.tcon 5,an int L),(4,2))::nil) =
(((LowLang.tcon 1,an int L),(0,0))::((LowLang.tcon 4,an int L),(3,0))::((LowLang.tcon 5,an int L),(4,1))::nil).
Proof. simpl. reflexivity.
Qed.
Lemma marked_heap_minus_snd_mark_1:forall n n',
n - (n' + 1) = n -n' -1.
Proof. intros n. induction n.
Case ("n=0"). reflexivity.
Case ("n=Sn''"). intros. destruct n'. simpl. reflexivity. simpl.
apply IHn.
Qed.
Lemma marked_heap_minus_snd_mark:forall hp n1 n2,
minus_snd_mark (marked_heap(marked_heap' hp n1) n2)
= (marked_heap(marked_heap' hp n1)(S n2)).
Proof. intro hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl.
remember (SecLang.label t) as BB. destruct BB.
simpl. specialize (IHhp 1 n2). rewrite->IHhp. reflexivity.
specialize (IHhp 1 (S n2)). rewrite->IHhp. reflexivity.
simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. simpl. specialize (IHhp (S (S n1)) 0). rewrite->IHhp.
reflexivity. simpl. specialize (IHhp (S (S n1)) (S n2)). rewrite->IHhp.
SearchAbout minus. assert (S n2 = n2 + 1). rewrite->plus_comm. reflexivity.
rewrite->H0. clear H0. rewrite->marked_heap_minus_snd_mark_1. reflexivity.
specialize (IHhp (S (S n1)) (S n2)). rewrite->IHhp. reflexivity.
Qed.
Lemma minus_snd_mark_same_mark:forall hp hp',
same_mark hp hp' = true ->
same_mark (minus_snd_mark hp)(minus_snd_mark hp') = true.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct hp'. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct hp'. destruct a. destruct p0. inversion H0.
destruct a. destruct p. destruct p1. destruct p2. simpl. simpl in H0.
remember (beq_nat n n1) as BB. destruct BB. remember (beq_nat n0 n2) as CC. destruct CC.
apply beq_nat_eq in HeqCC. rewrite->HeqCC. rewrite<-beq_nat_refl. apply IHhp. apply H0.
inversion H0. inversion H0.
Qed.
(*Lemma add_both_mark_L*)
Lemma add_both_mark_L:forall e T hp,
SecLang.label e = L ->
project_hp ((e,T) :: hp) = ((project_e e,T),(0,0)) :: (add_both_mark (project_hp hp)).
Proof. intros. generalize dependent e. generalize dependent T. induction hp.
intros. simpl. unfold project_hp. unfold marked_heap'. unfold marked_heap. rewrite->H0. reflexivity.
intros. unfold project_hp. rewrite->marked_heap'_hd. simpl. rewrite->H0. destruct a. remember (SecLang.label t) as BB.
destruct BB. rewrite->marked_heap_L. simpl. rewrite<-HeqBB. rewrite->add_both_mark_hd. simpl. assert (0<=1). apply le_S.
apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1. simpl in H1. rewrite->H1. reflexivity. symmetry. apply HeqBB.
simpl. rewrite<-HeqBB. assert (1<=1). apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1.
rewrite->H1. reflexivity.
Qed.
(*#######################################################*)
Lemma same_mark_marked_heap:forall hp hp',
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (marked_heap (marked_heap' hp 1) 1)(marked_heap (marked_heap' hp' 1) 1) = true.
Proof. intros. assert (marked_heap (marked_heap' hp 1) 1 = add_fst_mark (project_hp hp)).
unfold project_hp. symmetry. apply marked_heap_add_fst_mark. apply le_n. rewrite->H1. clear H1.
assert (add_fst_mark (project_hp hp') = marked_heap (marked_heap' hp' 1) 1). unfold project_hp.
apply marked_heap_add_fst_mark. apply le_n. rewrite<-H1. clear H1.
apply add_fst_mark_same_mark. apply H0.
Qed.
(**
Lemma same_mark_marked_heap_generalize_1:forall n hp hp',
same_mark (marked_heap(marked_heap' hp 0)0)(marked_heap(marked_heap' hp' 0)0) = true ->
same_mark (marked_heap (marked_heap' hp 0) n)(marked_heap (marked_heap' hp' 0) n) = true.
Proof. intros n. induction n.
Case ("n=0"). intros. apply H0.
Case ("n=S n'"). intros. rewrite<-marked_heap_minus_snd_mark. rewrite<-marked_heap_minus_snd_mark.
apply minus_snd_mark_same_mark. apply IHn. apply H0.
Qed.
*)
Lemma same_mark_marked_heap_generalize:forall hp hp' n1 n2,
n2<=n1 ->
same_mark (marked_heap(marked_heap' hp 0)0)(marked_heap(marked_heap' hp' 0)0) = true ->
same_mark (marked_heap (marked_heap' hp n1) n2)(marked_heap (marked_heap' hp' n1) n2) = true.
Proof. intros. generalize dependent n2. generalize dependent hp. generalize dependent hp'.
induction n1.
Case ("n1=0"). intros. destruct n2. apply H1. inversion H0.
Case ("n1=S n"). intros. destruct n2. assert (0<=n1). apply SecLang.zero_n.
assert (S n1 = n1 +1). rewrite->plus_comm. reflexivity. rewrite->H3.
clear H3. assert (0<=n1). apply H2. apply marked_heap_add_both_mark with (hp:=hp)in H2.
rewrite<-H2. clear H2. apply marked_heap_add_both_mark with (hp:=hp') in H3. rewrite<-H3.
clear H3. apply IHn1 with (n2:=0)in H1. apply add_both_mark_same_mark'.
apply H1. apply SecLang.zero_n. apply SecLang.lt_snoc_1 in H0. assert (n2<=n1). apply H0. assert (n2<=n1). apply H0.
apply marked_heap_add_fst_mark with(hp:=hp)in H0. apply marked_heap_add_fst_mark with(hp:=hp')in H2.
assert (S n1 = n1 + 1). rewrite->plus_comm. reflexivity. rewrite->H4. clear H4. assert (S n2 = n2 + 1).
rewrite->plus_comm. reflexivity. rewrite->H4. clear H4. rewrite<-H0. clear H0. rewrite<-H2. clear H2.
apply IHn1 with (n2:=n2)in H1. apply add_fst_mark_same_mark'. apply H1. apply H3.
Qed.
(*########################################################*)
Lemma same_mark_Sameext:forall hp hp' a,
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (project_hp (a :: hp))(project_hp (a :: hp')) = true.
Proof. intros. destruct a. remember (SecLang.label t) as BB. destruct BB.
symmetry in HeqBB. assert (SecLang.label t = L). apply HeqBB.
apply add_both_mark_L with (T:=t0)(hp:=hp)in HeqBB. rewrite->HeqBB.
apply add_both_mark_L with (T:=t0)(hp:=hp')in H1. rewrite->H1.
simpl. apply add_both_mark_same_mark. apply H0. unfold project_hp.
simpl. rewrite<-HeqBB.
assert (add_fst_mark (project_hp hp) = marked_heap (marked_heap' hp 1) 1).
unfold project_hp. apply marked_heap_add_fst_mark. apply le_n. rewrite<-H1. clear H1.
assert (add_fst_mark (project_hp hp') = marked_heap (marked_heap' hp' 1) 1).
unfold project_hp. apply marked_heap_add_fst_mark. apply le_n. rewrite<-H1.
apply add_fst_mark_same_mark. apply H0.
Qed.
(*###########*)
Lemma project_hp_Sameext:forall hp hp' a,
project_hp hp = project_hp hp' ->
project_hp (a::hp) = project_hp (a::hp').
Proof. intros. destruct a. remember (SecLang.label t) as BB. destruct BB. unfold project_hp.
rewrite->marked_heap'_hd. rewrite->marked_heap'_hd. simpl. rewrite<-HeqBB. unfold project_hp in H0.
assert (0<=0). apply le_n. assert (0<=0). apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1.
apply marked_heap_add_both_mark with (hp:=hp') in H2. simpl in H1. simpl in H2. rewrite<-H1. rewrite<-H2.
rewrite->H0. reflexivity. unfold project_hp. simpl. rewrite<-HeqBB. unfold project_hp in H0. assert (0<=0). apply le_n.
assert (0<=0). apply le_n. apply marked_heap_add_fst_mark with (hp:=hp) in H1. apply marked_heap_add_fst_mark with (hp:=hp') in H2.
simpl in H1. simpl in H2. rewrite<-H1. rewrite<-H2. rewrite->H0. reflexivity.
Qed.
(*the projection of a heap equals that of the heap itself*)
Lemma project_hp_Hextend:forall v hp T,
SecLang.value v ->
project_hp hp = project_hp (SecLang.snoc hp (SecLang.joinvs v H,T)).
Proof. intros. generalize dependent T. generalize dependent v. induction hp.
Case ("nil"). intros. simpl. inversion H0. subst. rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity. subst. rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity. subst. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity. subst. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity.
Case ("h::t"). intros. simpl. apply project_hp_Sameext. apply IHhp. apply H0.
Qed.
Lemma project_hp_Lextend:forall v hp T,
SecLang.value v ->
SecLang.label v = L ->
project_hp (SecLang.snoc hp (v,T)) = LowLang.snoc (project_hp hp) ((project_e v,T),(length hp,length (project_hp hp))).
Proof. intros. generalize dependent v. generalize dependent T. induction hp.
Case ("nil"). intros. unfold project_hp. simpl. rewrite->H1. reflexivity.
Case ("h::t"). intros. simpl. unfold project_hp. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
simpl. assert (0<=0). apply le_n. apply marked_heap_add_both_mark with(hp:=SecLang.snoc hp (v,T))in H2.
simpl in H2. rewrite<-H2. clear H2. assert (0<=0). apply le_n.
apply marked_heap_add_both_mark_snoc with(hp:=hp)(n3:=length hp)(n4:=length (marked_heap(marked_heap' hp 1)0))(V:=project_e v)(T:=T)in H2.
simpl in H2. rewrite<-H2. clear H2. rewrite->marked_heap_mark_length with(n3:=0)(n4:=0). apply IHhp with(T:=T)in H0. unfold project_hp in H0.
rewrite<-H0. reflexivity. apply H1.
assert (0<=0). apply le_n. apply marked_heap_add_fst_mark with(hp:=SecLang.snoc hp (v,T))in H2.
simpl in H2. rewrite<-H2. clear H2. assert (0<=0). apply le_n.
apply marked_heap_add_fst_mark_snoc with(hp:=hp)(n3:=length hp)(n4:=length(marked_heap(marked_heap' hp 1)1))(V:=project_e v)(T:=T)in H2.
simpl in H2. rewrite<-H2. clear H2.
rewrite->marked_heap_mark_length with(n3:=0)(n4:=0). unfold project_hp in IHhp. apply IHhp with(T:=T)in H0. rewrite<-H0. reflexivity.
apply H1.
Qed.
(**
the projection of a heap equals that of the heap with some of its high cell
being over-written by a high value
*)
Lemma project_hp_Hoverwrite:forall n hp t T,
n < length hp ->
SecLang.value t ->
subsum_r H (SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))) ->
project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t H,T) hp).
Proof. intros. generalize dependent n. generalize dependent t. generalize dependent T. induction hp.
Case ("nil"). intros. simpl. destruct n. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct n. simpl. simpl in H2. destruct a. unfold project_hp. rewrite->marked_heap'_hd.
rewrite->marked_heap'_hd. simpl. inversion H2. subst. inversion H1. rewrite->SecLang.join_tcon_b.
rewrite->SecLang.joins_refl. simpl. reflexivity. rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl.
simpl. reflexivity. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl. reflexivity. simpl. apply project_hp_Sameext.
apply IHhp. apply H1. simpl in H0. apply LowLang.lt_snoc_1 in H0. apply H0. simpl in H2. apply H2.
Qed.
Lemma lt_S_n:forall n n',
S n < S n' ->
n < n'.
Proof. intros. apply LowLang.lt_snoc_1 in H0. apply H0.
Qed.
Lemma project_hp_Loverwrite:forall n hp t T,
n < length hp ->
SecLang.value t ->
SecLang.label t = L ->
SecLang.label (SecLang.efst (SecLang.heap_lookup n hp)) = L ->
same_mark (project_hp hp)(project_hp (SecLang.heap_replace n (t,T) hp)) = true.
Proof. intros. generalize dependent n. generalize dependent t. generalize dependent T.
induction hp.
Case ("nil"). intros. destruct n. simpl in H0. apply LowLang.lt_same_F in H0. inversion H0. inversion H0.
Case ("h::t"). intros. destruct n. simpl. simpl in H3. destruct a. apply add_both_mark_L with (T:=t1)(hp:=hp) in H3.
rewrite->H3. apply add_both_mark_L with (T:=T)(hp:=hp) in H2. rewrite->H2. simpl. apply same_mark_refl.
simpl. apply same_mark_Sameext. apply IHhp. apply H1. apply H2. simpl in H0.
apply lt_S_n. apply H0. simpl in H3. apply H3.
Qed.
(**
Now how about the projection of a heap versus that of the heap with some of its
low cell being over-written by
the projection of a heap equals that of the heap with some of its high cell
being over-written by a low value
Lemma project_hp_LHoverwrite:forall n hp t T,
n < length hp ->
SecLang.value t ->
subsum_r H (SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))) ->
project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t H,T) hp).
*)
(**
Note that with the help of [project_e] and [project_hp], the configuration in [SecLang] can be
converted to a term in [LowLang] and a marked heap with mark indicating the positions
of each cell both before and after the projection of the heap.
Now we finish up our job by further project the configuration,rewriting the locations in the term,
and then erasing all the marks on the heap.
Keep in mind that regarding the rewriting of referred location we have the following
two cases to consider,
a. high cell being over-written by high value
b. low cell being over-written by low value
This,as is discussed later,implies that our further projection w.r.t. the marked
heap simply erases the marks on the heap
*)
(**
Note regarding the further projection of the configuration of term and heap,let us
consider the following cases:
suppose our unprojected heap in [SecLang] as follows,
[3 L,4 H,5 H,6 L]
a. high cell being over-written by a low value
tassign (tloc (an int L) 2) 7 / [(3,(0->0)),(6,(3->1))]
"proj",
tassign (tloc (an int L) 1) 7 / [(3,(0->0)),(#,(2->1)),(6,(3->2))]
Note that if the type of the pointer is [L] and the location in [tloc] does not
match up with the first element of all markers,the rules for the game as follows,
firstly find the element whose first number is the lowest number which is bigger
than that in [tloc];then insert some arbitrary element together with its mark
to the heap;finally replace the location in [tloc] with the location of the inserted
cell on the heap
Note that we can actually use a much simply fix,
we can replace the low value with [tH],treating it as a high value and then
change the referred location to be the length of the heap,transforming the case
to the case where a high cell is being over-written by a high value
Note: for now this case is excluded from our consideration
b. high cell being over-written by a high value
tassign (tloc (an int H) 2) 7 / [(3,0->0),(6,3->1)]
"proj",
tassign (tloc (an int H) 2) 7 / [(3,0->0),(6,3->1)]
Recall [st_assign] that the value being written onto the heap is guarded also by
the label of the referred type which is [H] in this case. It follows that whatever
gets written onto the heap, it must have high label and therefore must not appear
in the projected heap. Therefore in the current case we need not further project
the configuration to change the location in [tloc] and the corresponding heap in case
where the number in [tloc] does not match up with all the marks
c. low cell being over-written by a low value
tassign (tloc (an int L) 3) 7 / [(3,0->0),(6,3->1)]
"proj"
tassign (tloc (an int L) 1) 7 / [(3,0->0),(6,3->1)]
Note that in case the number in [tloc] matches up with some mark in the heap,
we simply replace that number by the second number in the mark while leaving
the heap unchanged. By doing so we can then specify reduction rules in [LowLang]
which over-writes the corresponding cell on the heap.
In conclusion, the only case where both the marked heap and the location in [tloc]
need to be modified is that both the referred type of the pointer and the value being
written have low security.
*)
(*
Note we proceed as follows,
1. we specify some list functions to help us to manipulate our marked heap
so that we can insert cell in the heap then mark that cell with
the right mark and after that replace the location in [tloc] correctly
2. combine the projections together
*)
(*some useful list operations*)
(**
a. given a number and a marked heap return the location of the cell
whose first number is the smallest one among all that are bigger
than that number;if there is a match,however,the second number of the
mark of the matched cell is returned
the function relies upon the assumption that the input heap is such that
the first numbers of the marker are in ascending order from left to right
moreover the second number of the marker corresponds to the location of
that cell on the heap
*)
Fixpoint return_smallest_match (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : bool*(nat*nat) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) =>if beq_nat n1 n
then (false,(n,n2))
else return_smallest_match n t
end
end
| nil => (true,(n,n))
end.
(*some examples*)
Example test_return_smallest_match_1:
return_smallest_match 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil)
= (true,(1,1)).
Proof. simpl. reflexivity. Qed.
(**
Note in [test_return_smallest_match_1],no match and the position of the cell the
first number of whose marker is bigger is one,hence returning [(true,1)]
*)
Example test_return_smallest_match_2:
return_smallest_match 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (false,(2,1)).
Proof. simpl. reflexivity. Qed.
(**
Note in [test_return_smallest_match_2], a match is obtained and the second number
of the marker is returned
*)
Example test_return_smallest_match_3:
return_smallest_match 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (true,(100,100)).
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [return_smallest_match]*)
Lemma return_smallest_match_true'':forall n n',
beq_nat n (n' + (S n)) = false.
Proof. intros. generalize dependent n'. induction n.
intros. rewrite->plus_comm. simpl. reflexivity. intros.
rewrite<-plus_n_Sm. simpl. apply IHn.
Qed.
Lemma return_smallest_match_true':forall hp n1 n2,
return_smallest_match ((length hp)+n1)(marked_heap(marked_heap' hp n1)n2)
=(true,(length hp + n1,length hp + n1)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. specialize (IHhp 1 n2). rewrite->plus_comm in IHhp. simpl in IHhp.
rewrite->plus_comm. simpl. apply IHhp. specialize (IHhp 1 (S n2)). rewrite->plus_comm in IHhp.
simpl in IHhp. rewrite->plus_comm. simpl. apply IHhp. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n2. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp (S (S n1)) 0). apply IHhp. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp (S (S n1)) (S n2)). apply IHhp. rewrite->plus_n_Sm. specialize (IHhp (S (S n1))(S n2)).
apply IHhp.
Qed.
Lemma return_smallest_match_true:forall hp,
return_smallest_match (length hp)(project_hp hp) = (true,(length hp,length hp)).
Proof. unfold project_hp. intros.
assert ((length hp) + 0 = length hp). rewrite->plus_comm. reflexivity.
rewrite<-H0. clear H0. apply return_smallest_match_true'.
Qed.
Lemma Hlabel_tH:forall t,
SecLang.label t = H ->
project_e t = LowLang.tH.
Proof. intros t. induction t.
Case ("tvar"). intros. inversion H0.
Case ("tprot"). intros. destruct s. simpl. assert (SecLang.label (SecLang.tprot L t) = SecLang.label t). reflexivity. rewrite->H1 in H0.
apply IHt. apply H0. simpl. reflexivity.
Case ("tcon"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tabs"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tapp"). intros. inversion H0.
Case ("tunit"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tref"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tderef"). intros. inversion H0.
Case ("tloc"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tassign"). intros. inversion H0.
Qed.
Lemma return_smallest_match_Sn_n:forall n n0 n1 n2 hp,
fst (return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0)) n1))
= fst (return_smallest_match n (marked_heap (marked_heap' hp n0) n2)).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n1. destruct n0. simpl.
destruct n. rewrite<-HeqBB. simpl. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp n2 0 1 (S n)). apply IHhp.
simpl. rewrite<-HeqBB. destruct n. destruct n2. simpl. specialize (IHhp 0 0 (S (S n0)) 0). apply IHhp. simpl.
specialize (IHhp (S n2) 0 (S (S n0)) 0). apply IHhp. destruct n2. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp 0 0 (S (S n0)) (S n)). apply IHhp. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp (S n2) 0 (S (S n0)) (S n)). apply IHhp. simpl. destruct n0. simpl. rewrite<-HeqBB. simpl.
destruct n. reflexivity. specialize (IHhp n2 (S n1) 1 (S n)). apply IHhp. simpl. rewrite<-HeqBB. destruct n2. simpl. destruct n.
specialize (IHhp 0 (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp 0 (S n1) (S (S n0)) (S n)). apply IHhp.
simpl. destruct n. specialize (IHhp (S n2) (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp (S n2) (S n1) (S (S n0)) (S n)). apply IHhp.
destruct n0. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) 1 n). apply IHhp. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) (S (S n0)) n). apply IHhp.
Qed.
Lemma return_smallest_match_Sn_Sn:forall n n0 n1 n2 hp,
fst (return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0))(S n1)))
= fst (return_smallest_match n (marked_heap (marked_heap' hp n0) n2)).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n0. simpl. destruct n.
rewrite<-HeqBB. simpl. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp n2 n1 1 (S n)). apply IHhp.
simpl. rewrite<-HeqBB. destruct n. destruct n2. simpl. specialize (IHhp 0 n1 (S (S n0)) 0). apply IHhp. simpl.
specialize (IHhp (S n2) n1 (S (S n0)) 0). apply IHhp. destruct n2. simpl. remember (beq_nat n0 n) as CC. destruct CC.
destruct n1. reflexivity. reflexivity.
specialize (IHhp 0 n1 (S (S n0)) (S n)). apply IHhp. simpl. remember (beq_nat n0 n) as CC. destruct CC. destruct n1. reflexivity.
reflexivity. specialize (IHhp (S n2) n1 (S (S n0)) (S n)). apply IHhp. destruct n0. simpl. rewrite<-HeqBB. simpl.
specialize (IHhp (S n2) (S n1) 1 n). apply IHhp. simpl. rewrite<-HeqBB. specialize (IHhp (S n2)(S n1)(S (S n0)) n). apply IHhp.
Qed.
Lemma return_smallest_match_snd_Sn_Sn:forall n n0 n1 hp,
fst (return_smallest_match n (marked_heap (marked_heap' hp n0) n1)) = false ->
snd(snd(return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0))(S n1))))
=snd(snd(return_smallest_match n (marked_heap (marked_heap' hp n0) n1))).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1.
induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n0. simpl. rewrite<-HeqBB. destruct n. simpl. reflexivity. simpl.
apply IHhp. simpl in H0. rewrite<-HeqBB in H0. simpl in H0. apply H0.
simpl. rewrite<-HeqBB. destruct n1. destruct n. apply IHhp. simpl in H0. rewrite<-HeqBB in H0.
simpl in H0. apply H0. remember (beq_nat n0 n) as CC. destruct CC. simpl. rewrite<-HeqCC. simpl.
reflexivity. simpl. rewrite<-HeqCC. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. simpl in H0.
rewrite<-HeqCC in H0. apply H0. destruct n. simpl. apply IHhp. simpl in H0. rewrite<-HeqBB in H0.
apply H0. remember (beq_nat n0 n) as CC. destruct CC. simpl. rewrite<-HeqCC. simpl. reflexivity.
simpl. rewrite<-HeqCC. apply IHhp. simpl in H0. rewrite<-H0. rewrite<-HeqBB. simpl. rewrite<-HeqCC.
reflexivity. destruct n0. simpl. rewrite<-HeqBB. apply IHhp. simpl in H0. rewrite<-HeqBB in H0.
apply H0. simpl. rewrite<-HeqBB. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
Qed.
Lemma return_smallest_match_snd_Sn_n:forall hp n n0 n1,
n1 <= n0 ->
snd (snd (return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0)) n1)))
=S (snd (snd (return_smallest_match n (marked_heap (marked_heap' hp n0) n1)))).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n1. destruct n0. simpl. rewrite<-HeqBB. simpl. destruct n. reflexivity.
specialize (IHhp (S n) 1 0). apply IHhp. apply le_S. apply le_n. simpl. rewrite<-HeqBB. simpl. destruct n.
specialize (IHhp 0 (S (S n0)) 0). apply IHhp. apply le_S. apply H0. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp (S n) (S (S n0)) 0). apply IHhp. apply le_S. apply H0. simpl.
destruct n0. simpl. rewrite<-HeqBB. simpl. destruct n. inversion H0. specialize (IHhp (S n) 1 (S n1)). apply IHhp. inversion H0.
simpl. rewrite<-HeqBB. simpl. destruct n. specialize (IHhp 0 (S (S n0)) (S n1)). apply IHhp. apply le_S. apply H0.
remember (beq_nat n0 n) as CC. destruct CC. destruct n1. rewrite<-minus_n_O. reflexivity.
simpl. rewrite->minus_Sn_m. reflexivity. apply LowLang.lt_same_F'. apply H0.
specialize (IHhp (S n) (S (S n0)) (S n1)). apply IHhp. apply le_S. apply H0. destruct n0. simpl. rewrite<-HeqBB.
specialize (IHhp n 1 (S n1)). apply IHhp. apply SecLang.n_iff_Sn_left in H0. apply H0.
simpl. rewrite<-HeqBB. specialize (IHhp n (S (S n0)) (S n1)). apply IHhp. apply SecLang.n_iff_Sn_left in H0. apply H0.
Qed.
Lemma n_le_minus_n':forall n n',
n - n' <= n.
Proof. intros. generalize dependent n'. induction n.
Case ("nil"). intros. simpl. apply le_n.
Case ("h::t"). intros. destruct n'. simpl. apply le_n. simpl. apply le_S.
apply IHn.
Qed.
Lemma return_smallest_match_fst_snd':forall n n1 n2 hp,
snd(snd(return_smallest_match n (marked_heap(marked_heap' hp n1)n2))) <= n.
Proof. intros. generalize dependent n. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. simpl. apply le_n.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. destruct n. simpl. apply le_n. specialize (IHhp n2 1 (S n)).
apply IHhp. specialize (IHhp (S n2) 1 n). apply IHhp. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n2. simpl. destruct n. specialize (IHhp 0 (S (S n1)) 0). apply IHhp.
remember (beq_nat n1 n) as CC. destruct CC. simpl. apply beq_nat_eq in HeqCC.
subst. apply le_n. specialize (IHhp 0 (S (S n1)) (S n)). apply IHhp. simpl. destruct n.
specialize (IHhp (S n2)(S (S n1)) 0). apply IHhp. remember (beq_nat n1 n) as CC. destruct CC.
simpl. apply beq_nat_eq in HeqCC. subst. apply le_S. apply n_le_minus_n'.
specialize (IHhp (S n2) (S (S n1)) (S n)). apply IHhp. specialize (IHhp (S n2)(S (S n1)) n). apply IHhp.
Qed.
Lemma return_smallest_match_fst_snd:forall n hp,
snd(snd(return_smallest_match n (project_hp hp))) <= n.
Proof. unfold project_hp. intros. apply return_smallest_match_fst_snd'.
Qed.
Lemma project_hp_le_length:forall hp,
length (project_hp hp) <= length hp.
Proof. intros hp. induction hp.
Case ("nil"). simpl. apply le_n.
Case ("h::t"). unfold project_hp. destruct a. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. apply SecLang.n_iff_Sn_left. rewrite->marked_heap_mark_length with (n3:=0)(n4:=0).
apply IHhp. apply le_S. rewrite->marked_heap_mark_length with (n3:=0)(n4:=0).
apply IHhp.
Qed.
Lemma return_smallest_match_project_e_true:forall n hp,
n < length hp ->
fst(return_smallest_match n (project_hp hp)) = true ->
project_e (SecLang.efst (SecLang.heap_lookup n hp)) = LowLang.tH.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl in H0. destruct n. apply LowLang.lt_same_F in H0. inversion H0.
inversion H0.
Case ("h::t"). intros. destruct n. destruct a. simpl. unfold project_hp in H1. simpl in H1. remember (SecLang.label t) as BB. destruct BB.
simpl in H1. inversion H1. apply Hlabel_tH. symmetry. apply HeqBB. simpl. apply IHhp. simpl in H0. apply lt_S_n in H0. apply H0.
unfold project_hp. unfold project_hp in H1. destruct a. simpl in H1. remember (SecLang.label t) as BB. destruct BB. simpl in H1.
assert (fst (return_smallest_match (S n)(marked_heap (marked_heap' hp 1) 0)) = fst (return_smallest_match n (marked_heap (marked_heap' hp 0) 0))).
apply return_smallest_match_Sn_n. rewrite<-H2. apply H1.
assert (fst (return_smallest_match (S n)(marked_heap (marked_heap' hp 1) 1)) = fst (return_smallest_match n (marked_heap (marked_heap' hp 0) 0))).
apply return_smallest_match_Sn_n. rewrite<-H2. apply H1.
Qed.
(*###################*)
Lemma return_smallest_match_hit'':forall n m,
ble_nat n m = ble_nat (S n)(S m).
Proof. intros n. induction n. intros. simpl. reflexivity.
intros. simpl. destruct m. reflexivity. reflexivity.
Qed.
Lemma return_smallest_match_hit':forall n,
ble_nat (S n) n = false.
Proof. intros. induction n. simpl. reflexivity. simpl. destruct n. reflexivity.
rewrite->return_smallest_match_hit''. apply IHn.
Qed.
(*####################*)
Lemma return_true_marked_heap:forall hp n n1 n2,
n < n1 ->
true = fst (return_smallest_match n (marked_heap (marked_heap' hp n1) n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct n. destruct a. simpl. destruct n1. apply LowLang.lt_same_F in H0.
inversion H0. simpl. destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0.
apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0. apply H0.
apply IHhp. apply le_S in H0. apply H0. destruct a. simpl. destruct n1. inversion H0. simpl.
destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl.
assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
Qed.
Lemma return_smallest_match_hit:forall n n' L hp,
return_smallest_match n ((L,(n,n')) :: hp) = (false,(n,n')).
Proof. intros. simpl. destruct n. reflexivity. rewrite<-beq_nat_refl.
reflexivity.
Qed.
Lemma return_smallest_match_hit_snoc':forall n n1 n2 L hp,
return_smallest_match ((length hp)+n1) (LowLang.snoc (marked_heap(marked_heap' hp n1)n2) (L,((length hp)+n1,n))) =(false,((length hp)+n1,n)).
Proof. intros. generalize dependent n. generalize dependent n1. generalize dependent n2. generalize dependent L0.
induction hp.
Case ("nil"). intros. simpl. rewrite<-beq_nat_refl. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl. remember (SecLang.label t) as BB. destruct BB.
simpl. rewrite->plus_comm. simpl. specialize (IHhp L0 n2 1 n). rewrite->plus_comm in IHhp. simpl in IHhp.
apply IHhp. rewrite->plus_comm. simpl. specialize (IHhp L0 (S n2) 1 n). rewrite->plus_comm in IHhp. simpl in IHhp.
apply IHhp. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n2. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp L0 0 (S (S n1)) n). apply IHhp. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp L0 (S n2)(S (S n1)) n). apply IHhp. rewrite->plus_n_Sm. specialize (IHhp L0 (S n2)(S (S n1)) n).
apply IHhp.
Qed.
Lemma return_smallest_match_hit_snoc:forall n L hp,
return_smallest_match (length hp)(LowLang.snoc (project_hp hp)(L,(length hp,n)))
=(false,(length hp,n)).
Proof. intros. unfold project_hp. assert (length hp = (length hp) + 0). rewrite->plus_comm. reflexivity.
rewrite->H0. clear H0. apply return_smallest_match_hit_snoc'.
Qed.
Lemma return_smallest_match_project_hp_hit:forall n hp,
n < length hp ->
SecLang.label (SecLang.efst (SecLang.heap_lookup n hp)) = L ->
fst (return_smallest_match n (project_hp hp)) = false.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. apply LowLang.lt_same_F in H0. inversion H0.
simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. unfold project_hp. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n. simpl. reflexivity. simpl.
rewrite->return_smallest_match_Sn_n with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
destruct n. simpl in H1. rewrite<-HeqBB in H1. inversion H1.
rewrite->return_smallest_match_Sn_n with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
Qed.
Lemma return_smallest_match_project_hp_not_hit:forall n hp,
n < length hp ->
SecLang.label (SecLang.efst (SecLang.heap_lookup n hp)) = H ->
fst (return_smallest_match n (project_hp hp)) = true.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. apply LowLang.lt_same_F in H0. inversion H0.
simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. unfold project_hp. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. destruct n. simpl in H1. rewrite<-HeqBB in H1. inversion H1.
rewrite->return_smallest_match_Sn_n with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
destruct n. assert (0<1). apply le_n. apply return_true_marked_heap with(hp:=hp)(n2:=1)in H2.
symmetry. apply H2.
rewrite->return_smallest_match_Sn_Sn with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
Qed.
Lemma return_smallest_match_F_length:forall n hp,
fst (return_smallest_match n (project_hp hp)) = false ->
n < length hp.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. unfold project_hp in H0. simpl in H0. remember (SecLang.label t) as BB.
destruct BB. destruct n. simpl. apply SecLang.n_iff_Sn_left. apply SecLang.zero_n.
simpl in H0. rewrite->return_smallest_match_Sn_n with(n2:=0)in H0. apply IHhp in H0.
simpl. apply SecLang.n_iff_Sn_left. apply H0. destruct n. simpl. apply SecLang.n_iff_Sn_left.
apply SecLang.zero_n. rewrite->return_smallest_match_Sn_Sn with(n2:=0) in H0. apply IHhp in H0.
simpl. apply SecLang.n_iff_Sn_left. apply H0.
Qed.
Lemma return_smallest_match_not_hit:forall n1 n2 n3 L hp,
n1 <> n2 ->
return_smallest_match n1 ((L,(n2,n3)) :: hp) = return_smallest_match n1 hp.
Proof. intros. remember (beq_nat n1 n2) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB in H0. apply LowLang.not_equal_nat in H0. inversion H0. simpl. rewrite->beq_nat_sym.
rewrite<-HeqBB. reflexivity.
Qed.
Lemma return_smallest_match_extend:forall n hp hp' a,
return_smallest_match n hp = return_smallest_match n hp' ->
return_smallest_match n (a :: hp) = return_smallest_match n (a :: hp').
Proof. intros. destruct a. destruct p0. remember (beq_nat n n0) as BB.
destruct BB. simpl. rewrite->beq_nat_sym. rewrite<-HeqBB. reflexivity.
simpl. rewrite->beq_nat_sym. rewrite<-HeqBB. apply H0.
Qed.
Lemma return_smallest_match_not_hit_snoc:forall n1 n2 n3 L hp,
n1 <> n2 ->
return_smallest_match n1 (LowLang.snoc hp (L,(n2,n3))) = return_smallest_match n1 hp.
Proof. intros. generalize dependent n1. generalize dependent n2. generalize dependent n3.
generalize dependent L0. induction hp.
intros. simpl. remember (beq_nat n2 n1) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB in H0. apply LowLang.not_equal_nat in H0. inversion H0. reflexivity.
intros. assert (LowLang.snoc (a :: hp)(L0,(n2,n3)) = a :: (LowLang.snoc hp (L0,(n2,n3)))). reflexivity.
rewrite->H1. apply return_smallest_match_extend. apply IHhp. apply H0.
Qed.
Lemma return_smallest_match_miss_one':forall n,
ble_nat n n = true.
Proof. intros. induction n. reflexivity. rewrite<-return_smallest_match_hit''. apply IHn.
Qed.
Lemma not_equal_le_S':forall n1 n2,
(S n1) <> (S n2) ->
n1 <> n2.
Proof. intros n1. destruct n1. intros. destruct n2. assert (1=1). reflexivity. apply H0 in H1. inversion H1.
intros contra. inversion contra. intros. destruct n2. intros contra. inversion contra. intros contra.
assert (S (S n1) = S (S n2)). rewrite->contra. reflexivity. apply H0 in H1. inversion H1.
Qed.
Lemma not_equal_le_S:forall n1 n2,
n1 <> n2 ->
(ble_nat (S n1) n2 = true) \/ (ble_nat (S n2) n1 = true).
Proof. intros n1. induction n1. intros. destruct n2. assert (0=0). reflexivity. apply H0 in H1.
inversion H1. left. simpl. reflexivity. intros. destruct n2. right. simpl. reflexivity.
apply not_equal_le_S' in H0. apply IHn1 in H0. inversion H0. left. rewrite<-return_smallest_match_hit''.
apply H1. right. rewrite<-return_smallest_match_hit''. apply H1.
Qed.
Lemma return_smallest_match_miss_one'':forall n1 n2,
false = ble_nat (S n1) n2 ->
false = ble_nat (S n2) n1 ->
n1 = n2.
Proof. intros. remember (beq_nat n1 n2) as BB. destruct BB. apply beq_nat_eq in HeqBB. apply HeqBB.
symmetry in HeqBB. apply beq_nat_false in HeqBB. apply not_equal_le_S in HeqBB. inversion HeqBB. rewrite->H2 in H0.
inversion H0. rewrite->H2 in H1. inversion H1.
Qed.
Lemma return_smallest_match_miss_one:forall n n1 n2 L,
n <> n1 ->
return_smallest_match n ((L,(n1,n2)) :: nil)= (true,(n,n)).
Proof. intros. simpl. remember (beq_nat n1 n) as BB. destruct BB. apply beq_nat_eq in HeqBB. symmetry in HeqBB. apply H0 in HeqBB.
inversion HeqBB. reflexivity.
Qed.
Lemma return_smallest_match_same_mark:forall hp hp' n,
same_mark hp hp' = true ->
fst (return_smallest_match n hp) = fst (return_smallest_match n hp').
Proof. intros hp. induction hp.
intros. destruct hp'. reflexivity. simpl in H0. inversion H0.
intros. destruct hp'. destruct a. destruct p0. simpl in H0. inversion H0.
destruct a. destruct p1. destruct p. destruct p1. simpl in H0.
remember (beq_nat n0 n2) as BB. remember (beq_nat n1 n3) as CC.
destruct BB. destruct CC. apply beq_nat_eq in HeqBB. apply beq_nat_eq in HeqCC.
rewrite->HeqBB. rewrite->HeqCC. remember (beq_nat n n2) as DD. destruct DD.
apply beq_nat_eq in HeqDD. rewrite->HeqDD. rewrite->return_smallest_match_hit.
rewrite->return_smallest_match_hit. reflexivity.
symmetry in HeqDD. apply beq_nat_false in HeqDD. destruct hp. destruct hp'.
assert (n<>n2). apply HeqDD. apply return_smallest_match_miss_one with (n2:=n3)(L:=p0)in HeqDD. rewrite->HeqDD.
apply return_smallest_match_miss_one with (n2:=n3)(L:=p)in H1. rewrite->H1. reflexivity. destruct p1. destruct p2. simpl in H0.
inversion H0. destruct hp'. destruct p1. destruct p2. simpl in H0. inversion H0.
assert (n<>n2). apply HeqDD. apply return_smallest_match_not_hit with (n3:=n3)(L:=p0)(hp:=p1 :: hp) in HeqDD. rewrite->HeqDD.
apply return_smallest_match_not_hit with (n3:=n3)(L:=p)(hp:=p2 :: hp') in H1. rewrite->H1. apply IHhp. apply H0.
inversion H0. inversion H0.
Qed.
Lemma return_smallest_match_same_mark':forall hp hp' n,
same_mark hp hp' = true ->
return_smallest_match n hp = return_smallest_match n hp'.
Proof. intros hp. induction hp.
intros. destruct hp'. reflexivity. simpl in H0. inversion H0.
intros. destruct hp'. destruct a. destruct p0. simpl in H0. inversion H0.
destruct a. destruct p1. destruct p. destruct p1. simpl in H0.
remember (beq_nat n0 n2) as BB. remember (beq_nat n1 n3) as CC.
destruct BB. destruct CC. apply beq_nat_eq in HeqBB. apply beq_nat_eq in HeqCC.
rewrite->HeqBB. rewrite->HeqCC. remember (beq_nat n n2) as DD. destruct DD.
apply beq_nat_eq in HeqDD. rewrite->HeqDD. rewrite->return_smallest_match_hit.
rewrite->return_smallest_match_hit. reflexivity.
symmetry in HeqDD. apply beq_nat_false in HeqDD. destruct hp. destruct hp'.
assert (n<>n2). apply HeqDD. apply return_smallest_match_miss_one with (n2:=n3)(L:=p0)in HeqDD. rewrite->HeqDD.
apply return_smallest_match_miss_one with (n2:=n3)(L:=p)in H1. rewrite->H1. reflexivity. destruct p1. destruct p2. simpl in H0.
inversion H0. destruct hp'. destruct p1. destruct p2. simpl in H0. inversion H0.
assert (n<>n2). apply HeqDD. apply return_smallest_match_not_hit with (n3:=n3)(L:=p0)(hp:=p1 :: hp) in HeqDD. rewrite->HeqDD.
apply return_smallest_match_not_hit with (n3:=n3)(L:=p)(hp:=p2 :: hp') in H1. rewrite->H1. apply IHhp. apply H0.
inversion H0. inversion H0.
Qed.
(**
Now given a position on the heap for us to insert one extra cell we have to
specify three functions before constructing the insert function for heap,
c. a function which upon a list and a number returns the prefix of the list
till indicated by that number
d. a function which upon a list and a number returns the suffix of the list
the starting point of which is indicated by that number
b. a function which upon a list increases the second number of its markers by
1,the "right shift"
*)
(*b. a function upon a list increase the second number of its markers by one*)
Fixpoint increase_snd (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) => (fst,(n1,n2+1)) :: (increase_snd t)
end
end
| nil => nil
end.
(*some test*)
Example test_increase_snd_1:
increase_snd (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,1)) :: ((LowLang.tcon 5,an int L),(2,2)) :: nil).
Proof. simpl. reflexivity. Qed.
(*c. a function upon a number and a list returns the prefix of the list till
the location indicated by that number*)
(**
To finish up,we also need to over-write the last element of the list with the following pair,
((tH,an int H),(n,n2)) where [(tH,an int H)] is chosen for [tH] is typable under all
types in [LowLang] while [n] indicates the position of the cell before projection and
[n2] indicates the current position of the cell
*)
Fixpoint prefix_hp (m:nat)(n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => match t with
| h' :: t' => h :: (prefix_hp m n' t)
| nil => match h with
| (fst,snd) => match snd with
| (n1,n2) => h :: ((LowLang.tH,an int H),(m,n2+1)) :: nil
end
end
end
| h :: t , 0 => match h with
| (fst,snd) => match snd with
| (n1,n2) =>((LowLang.tH,an int H),(m,n2)) :: nil
end
end
| nil , _ => nil (*this branch is never visited*)
end.
(*some examples*)
Example test_prefix_hp_1:
prefix_hp 100 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tH,an int H),(100,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_2:
prefix_hp 100 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tH,an int H),(100,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_3:
prefix_hp 100 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tH,an int H),(100,2)) :: nil).
Proof. simpl. reflexivity. Qed.
(**
d. a function which upon a number returns its suffix starting at the cell
indicated by that number
*)
Fixpoint suffix_hp (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => suffix_hp n' t
| h :: t , 0 => h :: t
| nil , _ => nil
end.
(*some examples*)
Example test_suffix_hp_1:
suffix_hp 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil)
= (((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_2:
suffix_hp 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_3:
suffix_hp 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_4:
suffix_hp 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= nil.
Proof. simpl. reflexivity. Qed.
(**
Now we can finally specify the insert function for the heap given a number
representing the position to be inserted and the marked heap
*)
(**
Note that the first argument of the following function is a pair where the
first component of it stands for the location on the heap before projection while
the second the location after
*)
Definition insert_hp (p:nat*nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
(prefix_hp (fst p) (snd p) hp) ++ (increase_snd (suffix_hp (snd p) hp)).
(*some examples*)
Example test_insert_hp_1:
insert_hp (1,1) (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tH,an int H),(1,1)) :: ((LowLang.tcon 5,an int L),(2,2)) :: nil).
Proof. reflexivity. Qed.
Example test_insert_hp_2:
insert_hp (6,0) (((LowLang.tcon 6,an int L),(7,0)) :: ((LowLang.tcon 5,an int L),(8,1)) :: nil)
= (((LowLang.tH,an int H),(6,0)) :: ((LowLang.tcon 6,an int L),(7,1)) :: ((LowLang.tcon 5,an int L),(8,2)) :: nil).
Proof. reflexivity. Qed.
Example test_insert_hp_3:
insert_hp (100,2) (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tH,an int H),(100,2)) :: nil).
Proof. reflexivity. Qed.
(**
About [insert_hp],upon a pair of numbers indicating the locations of a cell both before and
after the projection of the heap,it insert a "dummy cell" to some location on the
projected heap
*)
(**
Note that since the case where a low cell is being over-written by a high value is
being ruled out in [SecLang],the following discussion can be ignored.
*)
(**
Note the following function will be used by the projection function for the configuraiton
to remove some element from the marked heap in order to relieve us from dealing
with heap removal in [LowLang].
Consider the following projected configuration by [project_e] and [project_hp],
tassign (tloc (an int L) 2) tH / [L(6),L(5),L(4)]
0->0 2->1 4->2
which is a case where we try to over-write a low value with a high value.
One option for us,as discussed above, is to do projection as follows,
tassign (tloc (an int L) 1) tH / [L(6),L(5),L(4)]
0->0 2->1 4->2
where we have a match and the referred location is change to the acctual location
on the heap and that is it! If we stick to this projection method,we would have
to deal with reduction in [LowLang] where the heap before the reduction is actually
longer and we would have to deal with problems like type safety,rearranging referred
location, and so forth which is entirely unnecessary if we instead use the
following projection,
tassign (tloc (an int L) 2) tH / [L(6),L(4)]
0->0 4->1
where the low cell on the heap is removed while the referred location is changed
so that it is out of range. Actually it now is exactly the same as if we have
a case where we try to over-write a high cell with a high value.
Another example which requires the above treatment,
tassign (tloc (an int H) 2) v / [L(6),L(5),L(4)]
0->0 2->1 4->2
which is being projected as
tassign (tloc (an int H) 2) v / [L(6),L(4)]
0->0 4->1
*)
(**
In order to enable our project function so that the above method can be implemented we
need the following functions,
a. a function which decrease every second element of the marks on the heap
by 1
b. a function given a natural number and a heap returns its prefix to the cell
whose right neighbour is indicated by that number
c. a function given a natural number and a heap returns its suffix starting from
the cell whose left neighbour is indicated by that number
d. a function which puts all together to remove one cell from the marked heap
*)
(*a. a function which upon a marked heap decrease every second number of the mark by one*)
Fixpoint decrease_snd (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) => (fst,(n1,n2-1)) :: (decrease_snd t)
end
end
| nil => nil
end.
(*some example*)
Example test_decrease_snd_1:
decrease_snd (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,0)) :: nil).
Proof. simpl. reflexivity. Qed.
(*b. a function which upon a heap and a number returns its prefix to that number exclusive*)
Fixpoint prefix_hp_ex (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => match n' with
| S n'' => h :: (prefix_hp_ex n' t)
| 0 => h :: nil
end
| h :: t , 0 => nil
| nil , _ => nil
end.
(*some examples*)
Example test_prefix_hp_ex_1:
prefix_hp_ex 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=nil.
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_ex_2:
prefix_hp_ex 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_ex_3:
prefix_hp_ex 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
(*c. a function which upon a heap and a number returns its suffix starting from the next number*)
Fixpoint suffix_hp_ex (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => suffix_hp_ex n' t
| h :: t , 0 => t
| nil , _ => nil
end.
(*some examples*)
Example test_suffix_hp_ex_1:
suffix_hp_ex 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_ex_2:
suffix_hp_ex 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil) = nil.
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_ex_3:
suffix_hp_ex 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil) = nil.
Proof. simpl. reflexivity. Qed.
(*d. a function which removes one cell from the heap*)
Definition remove_hp (n:nat) (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
(prefix_hp_ex n hp) ++ (decrease_snd (suffix_hp_ex n hp)).
(*some examples*)
Example test_remove_hp_1:
remove_hp 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 5,an int L),(2,0)) :: ((LowLang.tcon 7,an int L),(4,1)) :: nil).
Proof. compute. reflexivity. Qed.
Example test_remove_hp_2:
remove_hp 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(4,1)) :: nil).
Proof. compute. reflexivity. Qed.
Example test_remove_hp_3:
remove_hp 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. compute. reflexivity. Qed.
Example test_remove_hp_4:
remove_hp 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil).
Proof. compute. reflexivity. Qed.
(**
Now what about the case where we want to over write a high cell referred to by
a pointer whose reference type is low with a low cell?
Should we do as suggested above that we insert a dummy cell to the heap which
then will be over-written by the low value? Not a good idear for by doing so
we introduce cell in the heap whose type is not clear and who is different from
the rest of the cells on the heap in [LowLang] which brings us complications when
we try to specify reduction relation.
Consider the following projected configuration by [project_e] and [project_hp],
tassign (tloc (an int L) 1) (7) / [L(6),L(5),L(4)]
0->0 2->1 4->2
which is a case where we over write a high cell with a low value, according to
the above suggested method we insert a dummy value onto the heap at the "right"
location and then change the referred location accordingly,
tassign (tloc (an int L) 1)(7) / [L(6), *,L(5),L(4)]
0->0 1->1 2->2 4->3
such method is thoroughly discussed in the next block of comments and so we are
not going to linger on furher.
A better approach,however,requires no insertion at all!for if we want to abstract
from all operations upon high value in the heap,then we should treat the case
of over-writing high cell with low cell the same as the case of over-writing high
cell with a high value and the projected heaps both before and after the projection
should be the same to [LowLang],thus,we should have the following projected configuration,
tassign (tloc (an int L) 3)(tH) / [L(6),L(5),L(4)]
0->0 2->1 4->2
where we simply replace the value with [tH] and replace the referred location as
the length of the heap to make it out of range which signals a high value in the
heap in [LowLang]. Then it is clear that we treat this case as the same as the case
when we try over-write a high cell with a high value.
*)
(**
Now we are ready for specifying the project function of the projected configuration
by both [project_e] and [project_hp].
Let us consider the projection sequence of the following configuration,
tapp (tassign (tloc (an int L) 2 L)(L(8)))
(tassign (tloc (an int L) 5 L)(L(9))) / [L(1),L(2),H(3),H(4),H(5),H(6),L(7)]
by[project_e]&[project_hp]
==========================>
tapp (tassign (tloc (an int L) 2)(8))
(tassign (tloc (an int L) 5)(9)) / [L(1),L(2),L(7)]
0->0 1->1 6->2
by[project_conf] \a
==========================>
tapp (tassign (tloc (an int L) {#3#})(tH))
(tassign (tloc (an int L) 5)(9)) / [L(1),L(2),L(7)]
0->0 1->1 6->2
by[project_conf] \b
==========================>
tapp (tassign (tloc (an int L) 3)(tH))
(tassign (tloc (an int L) {#3#})(tH)) / [L(1),L(2),L(7)]
0->0 1->1 6->2
by[project_conf] \c
==========================>
tapp (tassign (tloc (an int L) 3)(tH))
(tassign (tloc (an int L) 3)(tH)) / [L(1),L(2),L(7)]
Note that one important point from the above projection sequence is that
the further projection of the marked heap is simply removing the marks on the heap
. It is completely independent from the projected terms under consideration.
This characteristic will simplify our task of specifying the projection function
of the configuration.
*)
(**
the project function for configuration takes a term in [LowLang] and a marked heap
and returns a configuration in [LowLang]
*)
(*one auxiliary function to erase marks on the heap*)
Fixpoint erase_hp (hp:list (((LowLang.tm)*Ty)*(nat*nat))) : LowLang.heap := (*list ((LowLang.tm)*Ty)*)
match hp with
| h :: t => match h with
| (fst,snd) =>fst :: (erase_hp t)
end
| nil => nil
end.
(*some example*)
Example test_erase_hp_1:
erase_hp (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= ((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil).
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [erase_hp]*)
Lemma erase_hp_length:forall hp,
length (erase_hp hp) = length hp.
Proof. intros. induction hp. reflexivity. simpl. destruct a. simpl.
rewrite->IHhp. reflexivity.
Qed.
Lemma erase_hp_snoc:forall Hp L0 p,
erase_hp (LowLang.snoc Hp (L0,p)) = LowLang.snoc (erase_hp Hp) L0.
Proof. intros Hp. induction Hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. simpl. specialize (IHHp L0 p). rewrite->IHHp. reflexivity.
Qed.
Fixpoint project_conf'_e (e:LowLang.tm)(hp:list (((LowLang.tm)*Ty)*(nat*nat))) : (LowLang.tm) :=
match e with
| LowLang.tvar x => LowLang.tvar x
(*Block One:projection of values in [LowLang]*)
(**
Note the general principle here is that no modification is make to the value
term for their counter-parts in [SecLang] are either not reducible
or reducible high terms.
There are,however,two value terms which need to be further projected to account for
the cases where a referred location is involved,
a. [LowLang.tabs x T t] whose body needs to be projected with the marked heap
b. [LowLang.tloc T n] whose referring location needs to be modified given a marked heap
*)
| LowLang.tcon n => LowLang.tcon n
| LowLang.tabs x T t => LowLang.tabs x T (project_conf'_e t hp)
| LowLang.tunit => LowLang.tunit
| LowLang.tloc T (Some n) =>if (fst(return_smallest_match n hp))
(*no match*) then LowLang.tloc T None
(*match*) else LowLang.tloc T (Some (snd(snd(return_smallest_match n hp))))
| LowLang.tloc T None => LowLang.tloc T None
| LowLang.tH => LowLang.tH
(*End Block One*)
(*Block Two:compound expressions with only one argument*)
| LowLang.tref T t => LowLang.tref T (project_conf'_e t hp)
| LowLang.tderef t => LowLang.tderef (project_conf'_e t hp)
(*End Block Two*)
(*Block Three:compound expressions with two arguments*)
(*tapp*)
(**
Note the idea of projection here is that we first inspect the
first argument if it is not a value we project it with the marked heap leaving
the second argument unchanged;if it is however a value we proceed to inspect the
second argument;if it is a value then we project both of them;if the second is not
a value we only project the second one
*)
(**
Note the following block might be used when upgrading and downgrading are
taken into consideration
*)
(**
|LowLang.tapp t1 t2 =>match t1 with
| LowLang.tvar y =>LowLang.tapp t1 t2
| LowLang.tcon m =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tabs y T' t' =>match t2 with
| LowLang.tvar y =>LowLang.tapp t1 t2
| LowLang.tcon o =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tabs z T'' t'' =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tapp t1' t2' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tunit =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tref T'' t'' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tderef t'' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tloc T'' N =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tassign t1' t2' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tH =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
end
| LowLang.tapp t1' t2' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tunit =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tref T' t' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tderef t' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tloc T' N =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tassign t1' t2' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tH =>LowLang.tapp t1 (project_conf'_e t2 hp)
end
(*tassign*)
|LowLang.tassign t1 t2 =>match t1 with
| LowLang.tvar y =>LowLang.tassign t1 t2
| LowLang.tcon m =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tabs y T' t' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tapp t1' t2' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tunit =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tref T' t' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tderef t' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tloc T' N =>match t2 with
| LowLang.tvar y =>LowLang.tassign t1 t2
| LowLang.tcon o =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tabs z T'' t'' =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tapp t1' t2' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tunit =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tref T'' t'' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tderef t'' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tloc T'' N =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tassign t1' t2' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tH =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
end
| LowLang.tassign t1' t2' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tH =>LowLang.tassign t1 (project_conf'_e t2 hp)
end
*)
|LowLang.tapp t1 t2 =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
|LowLang.tassign t1 t2 =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
(*End Block Three*)
end.
(*some lemmas regarding [project_conf'_e]*)
Lemma project_conf'_e_same_mark:forall t hp hp',
same_mark hp hp' = true ->
project_conf'_e t hp = project_conf'_e t hp'.
Proof. intros t. induction t.
Case ("tvar"). intros. simpl. reflexivity.
Case ("tcon"). intros. simpl. reflexivity.
Case ("tabs"). intros. simpl. apply IHt in H0. rewrite->H0. reflexivity.
Case ("tapp"). intros. simpl. assert (same_mark hp hp' = true). apply H0. apply IHt1 in H0. apply IHt2 in H1.
rewrite->H0. rewrite->H1. reflexivity.
Case ("tunit"). intros. simpl. reflexivity.
Case ("tref"). intros. simpl. apply IHt in H0. rewrite->H0. reflexivity.
Case ("tderef"). intros. apply IHt in H0. simpl. rewrite->H0. reflexivity.
Case ("tloc"). intros. simpl. destruct o. apply return_smallest_match_same_mark' with(n:=n)in H0. rewrite->H0. reflexivity. reflexivity.
Case ("tassign"). intros. simpl. assert (same_mark hp hp' = true). apply H0. apply IHt1 in H0. apply IHt2 in H1. rewrite->H0.
rewrite->H1. reflexivity.
Case ("tH"). intros. simpl. reflexivity.
Qed.
(**
Now we are in a position to calculate the "right" heap in [LowLang] with
the following projection function. The result of it then will be used to
calculate the projection of the term in [LowLang]
*)
Fixpoint project_conf'_hp (hp1:list (((LowLang.tm)*Ty)*(nat*nat))) (hp2:list (((LowLang.tm)*Ty)*(nat*nat))): list (((LowLang.tm)*Ty)*(nat*nat)) :=
match hp1 with
|h :: t => match h with
|(l,r) => match l with
|(t0,T)=>((project_conf'_e t0 hp2,T),r) :: (project_conf'_hp t hp2)
end
end
| nil => nil
end.
(**
Note some interesting properties regarding [project_conf'_hp],
1. forall hp, length hp = length (project_conf'_hp hp)
2. forall n, nth element's mark of hp is the same as that of project_conf'_hp hp
*)
Lemma same_mark_heap_proj:forall hp hp' hp'',
same_mark (project_conf'_hp hp hp')(project_conf'_hp hp hp'') = true.
Proof. intros hp. induction hp.
intros. simpl. reflexivity.
intros. destruct a. destruct p0. simpl. destruct p. simpl. rewrite<-beq_nat_refl.
rewrite<-beq_nat_refl. apply IHhp.
Qed.
Lemma project_conf'_hp_same_mark:forall hp hp' hp'',
same_mark hp' hp'' = true ->
project_conf'_hp hp hp' = project_conf'_hp hp hp''.
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. simpl.
assert (same_mark hp' hp'' = true).
apply H0. apply project_conf'_e_same_mark with (t:=t)in H0.
rewrite->H0. apply IHhp in H1. rewrite->H1. reflexivity.
Qed.
Lemma project_conf'_hp_length:forall hp,
length (project_conf'_hp hp hp) = length hp.
Proof. intros. induction hp. simpl. reflexivity. simpl. destruct a. destruct p. simpl.
assert (same_mark (project_conf'_hp hp hp)(project_conf'_hp hp ((t,t0,p0) :: hp)) = true).
apply same_mark_heap_proj. apply same_mark_length in H0. rewrite<-H0. rewrite->IHhp. reflexivity.
Qed.
Lemma same_mark_heap:forall hp,
same_mark hp (project_conf'_hp hp hp) = true.
Proof. intros. induction hp.
simpl. reflexivity. destruct a. destruct p0. destruct p.
assert (project_conf'_hp (((t,t0),(n,n0)) :: hp)(((t,t0),(n,n0)) :: hp) = ((project_conf'_e t (((t,t0),(n,n0)) :: hp),t0),(n,n0)) :: (project_conf'_hp hp (((t,t0),(n,n0)) :: hp))).
simpl. reflexivity. rewrite->H0. clear H0. simpl. rewrite<-beq_nat_refl. rewrite<-beq_nat_refl.
simpl. rewrite->same_mark_sym. reflexivity.
assert (same_mark (project_conf'_hp hp (((t,t0),(n,n0)) :: hp))(project_conf'_hp hp hp) = true). apply same_mark_heap_proj.
apply same_mark_sym in IHhp. apply same_mark_sym in H0. apply same_mark_replace with (hp1:=project_conf'_hp hp hp). apply IHhp. apply H0.
Qed.
Lemma return_smallest_match_same_mark_false:forall n hp,
fst (return_smallest_match n (project_hp hp)) = false ->
fst (return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp))) = false.
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true).
apply same_mark_heap. apply return_smallest_match_same_mark with (n:=n)in H1. rewrite<-H1. apply H0.
Qed.
Lemma project_conf'_e_add_one_low:forall t hp L,
SecLang.well_formed t (length hp) ->
project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp)(project_hp hp))
=
project_conf'_e (project_e t)
(project_conf'_hp (LowLang.snoc (project_hp hp)(L,(length hp,length (project_hp hp))))
(LowLang.snoc (project_hp hp)(L,(length hp,length (project_hp hp))))).
Proof. intros t. induction t.
Case ("tvar"). intros. simpl. reflexivity.
Case ("tprot"). intros. destruct s. simpl. inversion H0. apply IHt with (L:=L0) in H4.
rewrite->H4. reflexivity. simpl. reflexivity.
Case ("tcon"). intros. destruct s. simpl. reflexivity. simpl. reflexivity.
Case ("tabs"). intros. destruct s. simpl. inversion H0. apply IHt with (L:=L0) in H6. rewrite->H6.
reflexivity. simpl. reflexivity.
Case ("tapp"). intros. simpl. inversion H0. apply IHt1 with (L:=L0) in H3. apply IHt2 with (L:=L0) in H5.
rewrite->H3. rewrite->H5. reflexivity.
Case ("tunit"). intros. destruct s. simpl. reflexivity. simpl. reflexivity.
Case ("tref"). intros. destruct s. simpl. inversion H0. apply IHt with (L:=L0) in H5.
rewrite->H5. reflexivity. simpl. reflexivity.
Case ("tderef"). intros. simpl. inversion H0. apply IHt with (L:=L0) in H2. rewrite->H2.
reflexivity.
Case ("tloc"). intros. destruct s. assert (project_e (SecLang.tloc t o L) = LowLang.tloc t o). reflexivity.
rewrite->H1.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp)) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with (t:=LowLang.tloc t o)in H2. rewrite<-H2.
assert (same_mark (LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp))))(project_conf'_hp
(LowLang.snoc (project_hp hp) (L0, (length hp, length (project_hp hp))))
(LowLang.snoc (project_hp hp) (L0, (length hp, length (project_hp hp))))
) = true). apply same_mark_heap. apply project_conf'_e_same_mark with (t:=LowLang.tloc t o)in H3.
rewrite<-H3. inversion H0. subst. remember (beq_nat n (length hp)) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB in H8. apply LowLang.lt_same_F in H8. inversion H8. symmetry in HeqBB. apply beq_nat_false in HeqBB.
apply return_smallest_match_not_hit_snoc with(n3:=length (project_hp hp))(L:=L0)(hp:=project_hp hp) in HeqBB. simpl. rewrite->HeqBB.
remember (fst (return_smallest_match n (project_hp hp))) as CC. destruct CC. reflexivity. reflexivity. simpl. reflexivity.
Case ("tassign"). intros. simpl. inversion H0. apply IHt1 with (L:=L0) in H3. rewrite->H3. apply IHt2 with (L:=L0) in H5. rewrite->H5.
reflexivity.
Qed.
(**
Lemma try:forall hp,
SecLang.heap_well_formed hp ->
(forall l L0, l < length hp
->
project_conf'_e (project_e (SecLang.efst (SecLang.heap_lookup l hp))) (project_hp hp)
=
project_conf'_e (project_e (SecLang.efst (SecLang.heap_lookup l hp))) (LowLang.snoc (project_hp hp) (L0,(length hp,length (project_hp hp))))
).
Proof. intros.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp)) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with(t:=project_e (SecLang.efst (SecLang.heap_lookup l hp))) in H2.
rewrite->H2.
assert (same_mark (LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp)))) (project_conf'_hp (LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp))))
(LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp))))) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e (SecLang.efst (SecLang.heap_lookup l hp)))in H3.
rewrite->H3. clear H2. clear H3. apply project_conf'_e_add_one_low. apply H0 in H1. apply H1.
Qed.
*)
Lemma marked_heap_well_formed_change_mark:forall hp n n1 n2 n3 n4,
marked_heap_well_formed (marked_heap (marked_heap' hp n1) n2) n ->
marked_heap_well_formed (marked_heap (marked_heap' hp n3) n4) n.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. apply nil_mhwf.
Case ("h::t"). intros. destruct a. assert (marked_heap' ((t,t0) :: hp) n3 = (t,t0,(n3,n3)) :: (marked_heap' hp (S n3))). simpl. destruct n3. reflexivity. reflexivity.
rewrite->H1. clear H1.
simpl. remember (SecLang.label t) as BB. destruct BB.
apply one_mhwf. simpl in H0. destruct n1. simpl in H0. rewrite<-HeqBB in H0. inversion H0. subst.
apply IHhp with (n1:=1)(n2:=n2). apply H6. simpl in H0. rewrite<-HeqBB in H0. inversion H0. subst.
apply IHhp with (n1:=S (S n1))(n2:=n2). apply H6. simpl in H0. destruct n1. simpl in H0. rewrite<-HeqBB in H0.
inversion H0. subst. apply H7. simpl in H0. rewrite<-HeqBB in H0. destruct n2. inversion H0. apply H7. inversion H0.
apply H7. simpl in H0. destruct n1. simpl in H0. rewrite<-HeqBB in H0. apply IHhp with (n1:=1)(n2:=S n2). apply H0.
simpl in H0. rewrite<-HeqBB in H0. apply IHhp with (n1:=S (S n1))(n2:=S n2). apply H0.
Qed.
Lemma SecLow_well_formed:forall t n,
SecLang.well_formed t n ->
LowLang.well_formed (project_e t) n.
Proof. intros t. induction t.
Case ("tvar"). intros. simpl. apply LowLang.wf_tvar.
Case ("tprot"). intros. destruct s. simpl. apply IHt. inversion H0. apply H4.
simpl. apply LowLang.wf_tH.
Case ("tcon"). intros. destruct s. simpl. apply LowLang.wf_tcon. simpl. apply LowLang.wf_tH.
intros. destruct s. simpl. apply LowLang.wf_tabs. apply IHt. inversion H0. apply H6.
simpl. apply LowLang.wf_tH.
Case ("tapp"). intros. simpl. apply LowLang.wf_tapp. apply IHt1. inversion H0. apply H3. apply IHt2.
inversion H0. apply H5.
Case ("tunit"). intros. destruct s. simpl. apply LowLang.wf_tunit. simpl. apply LowLang.wf_tH.
Case ("tref"). intros. destruct s. simpl. apply LowLang.wf_tref. apply IHt. inversion H0. apply H5.
simpl. apply LowLang.wf_tH.
Case ("tderef"). intros. simpl. apply LowLang.wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct s. simpl. destruct o. apply LowLang.wf_tloc. inversion H0. apply H5.
inversion H0. simpl. apply LowLang.wf_tH.
Case ("tassign"). intros. simpl. apply LowLang.wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2.
inversion H0. apply H5.
Qed.
Lemma heap_marked_heap_well_formed:forall hp n,
SecLang.heap_well_formed hp n ->
marked_heap_well_formed (project_hp hp) n.
Proof. intros hp. induction hp.
Case ("nil"). intros. compute. apply nil_mhwf.
Case ("h::t"). intros. destruct a. unfold project_hp. simpl. unfold project_hp in IHhp.
remember (SecLang.label t) as BB. destruct BB. apply one_mhwf. inversion H0.
apply marked_heap_well_formed_change_mark with (n1:=0)(n2:=0). apply IHhp. apply H5.
inversion H0. apply SecLow_well_formed. apply H6.
apply marked_heap_well_formed_change_mark with (n1:=0)(n2:=0). apply IHhp.
inversion H0. apply H5.
Qed.
Lemma project_conf'_e_add_one_low':forall Hp t n L0,
LowLang.well_formed t n ->
project_conf'_e t Hp = project_conf'_e t (LowLang.snoc Hp (L0,(n,length Hp))).
Proof. intros. generalize dependent Hp. generalize dependent L0. generalize dependent n.
induction t.
Case ("tvar"). intros. simpl. reflexivity.
Case ("tcon"). intros. simpl. reflexivity.
Case ("tabs"). intros. simpl. inversion H0. subst. apply IHt with (L0:=L0)(Hp:=Hp) in H5.
rewrite<-H5. reflexivity.
Case ("tapp"). intros. simpl. inversion H0. subst. apply IHt1 with (L0:=L0)(Hp:=Hp)in H3.
apply IHt2 with (L0:=L0)(Hp:=Hp) in H5. rewrite<-H3. rewrite<-H5. reflexivity.
Case ("tunit"). intros. simpl. reflexivity.
Case ("tref"). intros. simpl. inversion H0. subst. apply IHt with (L0:=L0)(Hp:=Hp)in H4. rewrite<-H4.
reflexivity.
Case ("tderef"). intros. simpl. inversion H0. subst. apply IHt with (L0:=L0)(Hp:=Hp) in H2. rewrite<-H2.
reflexivity.
Case ("tloc"). intros. destruct o. simpl. inversion H0. subst. assert (n0<>n). intros contra. subst. apply LowLang.lt_same_F in H4.
inversion H4. apply return_smallest_match_not_hit_snoc with (n3:=length Hp)(L:=L0)(hp:=Hp)in H1.
rewrite->H1. reflexivity.
inversion H0.
Case ("tassign"). intros. simpl. inversion H0. subst. apply IHt1 with(L0:=L0)(Hp:=Hp)in H3.
apply IHt2 with(L0:=L0)(Hp:=Hp) in H5. rewrite<-H3. rewrite<-H5. reflexivity.
Case ("tH"). intros. simpl. reflexivity.
Qed.
Lemma project_conf'_hp_add_one_low':forall Hp Hp' n L0,
marked_heap_well_formed Hp n ->
project_conf'_hp Hp
(LowLang.snoc Hp' ((L0,(n,length Hp'))))
=project_conf'_hp Hp Hp'.
Proof. intros. generalize dependent L0. generalize dependent Hp'.
generalize dependent n. induction Hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. simpl. assert (marked_heap_well_formed ((t,t0,p0) :: Hp) n).
apply H0. apply marked_heap_well_formed_shrink in H0.
apply IHHp with (Hp':=Hp')(L0:=L0)in H0. rewrite->H0. inversion H1. subst.
apply project_conf'_e_add_one_low' with (Hp:=Hp')(L0:=L0) in H8. rewrite->H8.
reflexivity.
Qed.
Lemma project_conf'_hp_add_one_low:forall hp L0,
SecLang.heap_well_formed hp (length hp) ->
project_conf'_hp (project_hp hp)
(LowLang.snoc (project_hp hp) ((L0,(length hp,length (project_hp hp)))))
=project_conf'_hp (project_hp hp) (project_hp hp).
Proof. intros. apply heap_marked_heap_well_formed in H0.
apply project_conf'_hp_add_one_low' with(Hp':=project_hp hp)(L0:=L0) in H0.
rewrite->H0. reflexivity.
Qed.
Lemma project_conf'_hp_snoc:forall hp hp' t T p,
project_conf'_hp
(LowLang.snoc hp ((t ,T),p))
hp'
= LowLang.snoc
(project_conf'_hp hp hp')
((project_conf'_e t hp',T),p).
Proof. intros. generalize dependent t. generalize dependent T. generalize dependent p.
generalize dependent hp'. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p0. simpl. specialize (IHhp hp' p T t).
rewrite->IHhp. reflexivity.
Qed.
(*some lemmas involving [project_conf'_hp]*)
(**
Lemma erase_hp_snoc:forall v hp rt,
LowLang.value v ->
v <> LowLang.tH ->
erase_hp (project_conf'_hp (LowLang.snoc (project_hp hp)((v,an rt L),(length hp,length (project_hp hp)))) (LowLang.snoc (project_hp hp)((v,an rt L),(length hp,length (project_hp hp)))))
=LowLang.snoc (erase_hp (project_conf'_hp (project_hp hp)(project_hp hp))) ((project_conf'_e v ,an rt L).
Proof. Admitted.
*)
(*some lemmas involves [project_conf'_hp]*)
Lemma project_conf'_hp_hp_snoc:forall hp hp' v T R,
LowLang.snoc (project_conf'_hp hp hp')((project_conf'_e v hp',T),R)
=project_conf'_hp (LowLang.snoc hp ((v,T),R)) hp'.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. simpl. specialize (IHhp hp' v T R).
rewrite->IHhp. reflexivity.
Qed.
Lemma return_smallest_match_snoc:forall hp v T,
LowLang.value v ->
v <> LowLang.tH ->
return_smallest_match (length hp) (project_conf'_hp ((LowLang.snoc (project_hp hp)((v,T),(length hp,length (project_hp hp)))))((LowLang.snoc (project_hp hp)((v,T),(length hp,length (project_hp hp))))))
= (false,(length hp,length (project_hp hp))).
Proof. intros. rewrite->project_conf'_hp_snoc. rewrite->project_conf'_hp_hp_snoc. assert (same_mark (LowLang.snoc (project_hp hp)
(v, T, (length hp, length (project_hp hp))))(project_conf'_hp (LowLang.snoc (project_hp hp)
(v, T, (length hp, length (project_hp hp))))(LowLang.snoc (project_hp hp)
(v, T, (length hp, length (project_hp hp)))))=true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp)in H2.
rewrite<-H2. clear H2. rewrite->return_smallest_match_hit_snoc. reflexivity.
Qed.
(*projection of configuration*)
Definition project_conf (e:LowLang.tm)(hp:list (((LowLang.tm)*Ty)*(nat*nat))): ((LowLang.tm))*(list (((LowLang.tm)*Ty))) :=
(project_conf'_e e (project_conf'_hp hp hp),erase_hp (project_conf'_hp hp hp)).
(*some examples*)
(**
Example test_project_conf_1:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note that as explained above,the case where we try to over-write a high cell via
a pointer whose reference type is low with a low value,we simply replace the value
with [tH] and the referred location with [None],thus treating it as
the case where a high cell is being replaced by a high value.
This is illustrated in [test_project_conf_1].
*)
*)
Example test_project_conf_2:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 2))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note in case where we want to over-write a low cell via a pointer whose reference
type is low with a low value, we need not change the heap at all. We should only
replace the referred location to the acctually location on the heap where the
cell to be over-written is located.
*)
Example test_project_conf_3:
project_conf (LowLang.tassign (LowLang.tloc (an int H) (Some 1))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note in case where we want to over-write a high cell via a pointer whose reference
type is high with a low value,since the side effect of such operation will not
be reflected at all in projected heap, we simply replace the referred location with
[None] and leave the rest to our reduction relation in [LowLang].
*)
Example test_project_conf_4:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tH))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note [test_project_conf_4] is a case where a high cell is being over-written by a high value.
Suppose we have the following projected configuration by [project_e] and [project_hp],
tassign (tloc (an int L) 1)(tH) / [L(6),L(5)]
0->0 2->1
which is to over-write a high value via a pointer whose reference type is low with
a high value. Since any side effect related with high security does not show up in
the projected heap, we should have the following configuration as the result of
our [project_conf] above,
tassign (tloc (an int L) 2)(tH) / [L(6),L(5)]
*)
(**
Example test_project_conf_5:
project_conf (LowLang.tapp
(LowLang.tassign (LowLang.tloc (an int L) (Some 2))(LowLang.tcon 8))
(LowLang.tassign (LowLang.tloc (an int L) (Some 5))(LowLang.tcon 9)))
(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(1,1)) :: ((LowLang.tcon 7,an int L),(6,2)) :: nil)
= (
LowLang.tapp
(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH))
(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH)),
((LowLang.tcon 1,an int L) :: (LowLang.tcon 2,an int L) :: (LowLang.tcon 7,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
Example test_project_conf_5':
project_conf (LowLang.tapp (LowLang.tH) (LowLang.tloc (an int L) (Some 2)))
(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tapp (LowLang.tH) (LowLang.tloc (an int L) (Some 1)),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
Example test_project_conf_6:
project_conf (LowLang.tderef(LowLang.tloc (an int H) (Some 1)))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tderef(LowLang.tloc (an int H) None),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
Example test_project_conf_7:
project_conf (LowLang.tderef(LowLang.tloc (an int L) (Some 2)))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tderef(LowLang.tloc (an int L) (Some 1)),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Example test_project_conf_8:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 2))(LowLang.tH))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L):: nil)).
Proof. compute. reflexivity. Qed.
(**
Note that the above example is the case where a low cell is being over-written by a high value.
Since it is the case excluded specifically in [SecLang],we need not consider the projection of it
at all
*)
*)
(**
Example test_project_conf_9:
project_conf (LowLang.tassign (LowLang.tloc (an int H) (Some 2))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int H) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Similar to [test_project_conf_8] where a low cell is being over-written by a high value
*)
*)
(*some lemmas regarding [project_conf']*)
Lemma project_conf'_subst:forall x v e hp,
project_conf'_e (LowLang.subst x v e) hp
= LowLang.subst x (project_conf'_e v hp) (project_conf'_e e hp).
Proof. intros. generalize dependent x. generalize dependent v. generalize dependent hp.
induction e.
Case ("tvar"). intros. simpl. remember (beq_id x i) as C. destruct C. reflexivity. reflexivity.
Case ("tcon"). intros. simpl. reflexivity.
Case ("tabs"). intros. simpl. remember (beq_id x i) as C. destruct C. reflexivity.
specialize (IHe hp v x). rewrite<-IHe. reflexivity.
Case ("tapp"). intros. simpl. specialize (IHe1 hp v x). specialize (IHe2 hp v x). rewrite->IHe1.
rewrite->IHe2. reflexivity.
Case ("tunit"). intros. simpl. reflexivity.
Case ("tref"). intros. simpl. specialize (IHe hp v x). rewrite<-IHe. reflexivity.
Case ("tderef"). intros. simpl. specialize (IHe hp v x). rewrite->IHe. reflexivity.
Case ("tloc"). intros. simpl. destruct o. remember (fst(return_smallest_match n hp)) as C. destruct C. simpl.
reflexivity. simpl. reflexivity. simpl. reflexivity.
Case ("tassign"). intros. simpl. specialize (IHe1 hp v x). specialize (IHe2 hp v x).
rewrite->IHe1. rewrite->IHe2. reflexivity.
Case ("tH"). intros. reflexivity.
Qed.
(**
Finally,we assemble the above three projection functions,[project_e],[project_hp],and [project_conf] together
*)
(*projection from a configuration in [SecLang] to one in [LowLang]*)
Definition project (c:SecLang.tm*SecLang.heap) : LowLang.tm*LowLang.heap :=
project_conf (project_e (fst c))(project_hp (snd c)).
(*some examples*)
(**
Example test_project_1:
project (SecLang.tassign (SecLang.tloc (an int L) (Some 1) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
= (LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
Example test_project_2:
project (SecLang.tassign (SecLang.tloc (an int L) (Some 2) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L)::nil))
=(LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
Example test_project_3:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 1) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Example test_project_4:
project (SecLang.tassign (SecLang.tloc (an int L) (Some 2) L)(SecLang.tcon 7 H),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=((LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tH)),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
(**
Example test_project_5:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 2) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
Example test_project_6:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 2) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note that in [test_project_6],the pointer is considerec to refer to high value
on the heap and that is why the referred location is projected to be [None]
*)
Example test_project_7:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 4) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
similar to that of [test_project_6]
*)
(*some important lemmas before NI*)
(*a single-step reduction in [SecLang] can be projected to be a multi-step reduction in [LowLang]*)
Lemma proj_hp_H_same:forall t t' hp hp',
SecLang.step (t,hp) H (t',hp') ->
project_hp hp = project_hp hp'.
Proof. intros t. induction t.
Case ("tvar").
intros. inversion H0.
Case ("tprot").
intros. inversion H0. subst. simpl in H9. apply IHt with (t':=t'0). apply H9. subst.
reflexivity.
Case ("tcon").
intros. inversion H0.
Case ("tabs").
intros. inversion H0.
Case ("tapp").
intros. inversion H0. subst. reflexivity. subst. apply IHt1 with (t':=t1'). apply H10.
subst. apply IHt2 with (t':=t2'). apply H11.
Case ("tunit").
intros. inversion H0.
Case ("tref").
intros. inversion H0. subst. assert (SecLang.joins s H = SecLang.joins H s). rewrite->SecLang.joins_refl. reflexivity.
rewrite->H1. simpl. destruct t. simpl. assert (SecLang.joins s0 H = SecLang.joins H s0). rewrite->SecLang.joins_refl. reflexivity.
rewrite->H2. clear H1. clear H2. simpl. apply project_hp_Hextend with (hp:=hp)(T:=an r s0) in H9. apply H9. subst. apply IHt with (t':=t'0).
apply H10.
Case ("tderef").
intros. inversion H0. subst. reflexivity. subst. apply IHt with (t':=t'0). apply H8.
Case ("tloc").
intros. inversion H0.
Case ("tassign").
intros. inversion H0. subst. simpl. destruct T. simpl. rewrite->SecLang.joins_refl. simpl.
apply project_hp_Hoverwrite. apply H8. apply H9. simpl in H14. apply H14.
(**
Here we have to prove that a high cell being replaced by high value won't make a difference in
[project_hp]
*)
subst. apply IHt1 with (t':=t1'). apply H10. subst. apply IHt2 with (t':=t2'). apply H11.
Qed.
(*some auxialary lemmas regarding [corresp_step]*)
Lemma SecLang_value_LowLang:forall v hp,
SecLang.value v ->
LowLang.value (project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. inversion H0.
Case ("tcon"). subst. destruct b. simpl. apply LowLang.v_c. simpl. apply LowLang.v_H.
Case ("tabs"). subst. destruct b. simpl. apply LowLang.v_f. simpl. apply LowLang.v_H.
Case ("tunit"). subst. destruct b. simpl. apply LowLang.v_u. simpl. apply LowLang.v_H.
Case ("tloc"). subst. destruct b. simpl. remember (fst(return_smallest_match n(project_conf'_hp (project_hp hp) (project_hp hp)))) as C.
destruct C. apply LowLang.v_l. apply LowLang.v_l. simpl. apply LowLang.v_H.
Qed.
Lemma multi_step_app1:forall c c' t2 PC,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tapp (fst c) t2,snd c) PC (LowLang.tapp (fst c') t2,snd c').
Proof. intros. generalize dependent t2. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tapp t t2,h)).
apply LowLang.st_app1. destruct x. apply H0. specialize (IHMulti t2). apply IHMulti.
Qed.
Lemma multi_step_app2:forall v1 c c' PC,
LowLang.value v1 ->
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tapp v1 (fst c),snd c) PC (LowLang.tapp v1 (fst c'),snd c').
Proof. intros. generalize dependent v1. induction H1.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. destruct x. apply LowLang.Multi_step with (y:=(LowLang.tapp v1 t,h)).
apply LowLang.st_app2. apply H2. apply H0. apply IHMulti. apply H2.
Qed.
Lemma multi_step_ref:forall c c' PC T,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tref T (fst c),snd c) PC (LowLang.tref T (fst c'),snd c').
Proof. intros. generalize dependent T. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tref T t,h)). apply LowLang.st_ref. destruct x.
apply H0. specialize (IHMulti T). apply IHMulti.
Qed.
Lemma multi_step_deref:forall c c' PC,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tderef (fst c),snd c) PC (LowLang.tderef (fst c'),snd c').
Proof. intros. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tderef t,h)). apply LowLang.st_deref. destruct x.
apply H0. apply IHMulti.
Qed.
Lemma multi_step_assign1:forall c c' t2 PC,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tassign (fst c) t2,snd c) PC (LowLang.tassign (fst c') t2,snd c').
Proof. intros. generalize dependent t2. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tassign t t2,h)).
apply LowLang.st_assign1. destruct x. apply H0. specialize (IHMulti t2). apply IHMulti.
Qed.
Lemma multi_step_assign2:forall v1 c c' PC,
LowLang.value v1 ->
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tassign v1 (fst c),snd c) PC (LowLang.tassign v1 (fst c'),snd c').
Proof. intros. generalize dependent v1. induction H1.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. destruct x. apply LowLang.Multi_step with (y:=(LowLang.tassign v1 t,h)).
apply LowLang.st_assign2. apply H2. apply H0. apply IHMulti. apply H2.
Qed.
Lemma step_same_mark_or_extend:forall t t' hp hp',
SecLang.step (t,hp) L (t',hp') ->
(same_mark (project_hp hp)(project_hp hp') = true) \/
(exists L0,project_hp hp' = LowLang.snoc (project_hp hp) (L0,(length hp,length (project_hp hp)))).
Proof. intros t. induction t.
Case ("tvar"). intros. inversion H0.
Case ("tprot"). intros. inversion H0. subst. destruct s. apply IHt in H9. apply H9. simpl in H9. apply proj_hp_H_same in H9.
left. rewrite->H9. apply same_mark_refl. subst. left. apply same_mark_refl.
Case ("tcon"). intros. inversion H0.
Case ("tabs"). intros. inversion H0.
Case ("tapp"). intros. inversion H0. subst. left. apply same_mark_refl. subst. apply IHt1 in H10. apply H10. subst. apply IHt2 in H11. apply H11.
Case ("tunit"). intros. inversion H0.
Case ("tref"). intros. inversion H0. subst. destruct t. destruct s0. destruct s. simpl. inversion H9. destruct b. rewrite->SecLang.join_tcon_b.
simpl. right. exists (LowLang.tcon n,an r L). apply project_hp_Lextend. apply SecLang.v_c. reflexivity. assert (SecLang.joinvs (SecLang.tcon n H) L = SecLang.joinvs (SecLang.tcon n L) H).
reflexivity. rewrite->H2. left. subst. assert (SecLang.value (SecLang.tcon n L)). apply SecLang.v_c. apply project_hp_Hextend with (hp:=hp)(T:=an r L)in H1. rewrite<-H1. apply same_mark_refl.
destruct b. rewrite->SecLang.join_tabs_b. simpl. right. exists (LowLang.tabs (Id n) T (project_e e),an r L). apply project_hp_Lextend. apply SecLang.v_f. reflexivity. assert (SecLang.joinvs (SecLang.tabs (Id n) T e H) L = SecLang.joinvs (SecLang.tabs (Id n) T e L) H).
reflexivity. rewrite->H2. left. assert (SecLang.value (SecLang.tabs (Id n) T e L)). apply SecLang.v_f. apply project_hp_Hextend with (hp:=hp)(T:=an r L) in H3. rewrite<-H3. apply same_mark_refl. destruct b. rewrite->SecLang.join_tunit_b. simpl. right.
exists (LowLang.tunit,an r L). apply project_hp_Lextend. apply SecLang.v_u. reflexivity. assert (SecLang.joinvs (SecLang.tunit H) L = SecLang.joinvs (SecLang.tunit L) H). reflexivity. rewrite->H2. left. assert (SecLang.value (SecLang.tunit L)). apply SecLang.v_u.
apply project_hp_Hextend with (hp:=hp)(T:=an r L) in H3. rewrite<-H3. apply same_mark_refl. destruct b. rewrite->SecLang.join_tloc_b. simpl. right. exists (LowLang.tloc T (Some n),an r L). apply project_hp_Lextend. apply SecLang.v_l. reflexivity. assert (SecLang.joinvs (SecLang.tloc T (Some n) H) L = SecLang.joinvs (SecLang.tloc T (Some n) L) H).
reflexivity. rewrite->H2. left. assert (SecLang.value (SecLang.tloc T (Some n) L)). apply SecLang.v_l. apply project_hp_Hextend with (hp:=hp)(T:=an r L)in H3. rewrite<-H3. apply same_mark_refl. left. simpl. apply project_hp_Hextend with (hp:=hp)(T:=an r L) in H9. rewrite<-H9. apply same_mark_refl. left. simpl. apply project_hp_Hextend with (hp:=hp)(T:=an r H) in H9.
rewrite<-H9. apply same_mark_refl. subst. destruct s. apply IHt in H10. apply H10. simpl in H10. apply proj_hp_H_same in H10. left. rewrite->H10. apply same_mark_refl.
Case ("tderef"). intros. inversion H0. subst. left. apply same_mark_refl. subst. apply IHt in H8. apply H8.
Case ("tloc"). intros. inversion H0.
Case ("tassign"). intros. inversion H0. subst. left. destruct T. destruct s. destruct b. simpl. inversion H9. destruct b. rewrite->SecLang.join_tcon_b. simpl. subst. simpl in H13. apply project_hp_Loverwrite.
apply H8. apply SecLang.v_c. reflexivity. symmetry. apply H13. subst. simpl in H13. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tcon n0 H) L,an r L) hp)).
assert (SecLang.joinvs (SecLang.tcon n0 H) L = SecLang.joinvs (SecLang.tcon n0 L) H). reflexivity. rewrite->H1. clear H1.
apply project_hp_Hoverwrite. apply H8. apply SecLang.v_c. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl. subst. destruct b. rewrite->SecLang.join_tabs_b. simpl. simpl in H13. apply project_hp_Loverwrite.
apply H8. apply SecLang.v_f. reflexivity. symmetry. apply H13. simpl in H13. assert (SecLang.joinvs (SecLang.tabs (Id n0) T e H) L = SecLang.joinvs (SecLang.tabs (Id n0) T e L) H). reflexivity. rewrite->H1. clear H1.
assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tabs (Id n0) T e L) H, an r L) hp) ). apply project_hp_Hoverwrite. apply H8. apply SecLang.v_f. rewrite<-H13. apply sub_refl. rewrite->H1. apply same_mark_refl.
subst. destruct b. rewrite->SecLang.join_tunit_b. simpl. apply project_hp_Loverwrite. apply H8. apply SecLang.v_u. reflexivity. simpl in H13. rewrite<-H13. reflexivity. assert (SecLang.joinvs (SecLang.tunit H) L = SecLang.joinvs (SecLang.tunit L) H). reflexivity.
rewrite->H1. clear H1. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tunit L) H, an r L) hp)). apply project_hp_Hoverwrite. apply H8. apply SecLang.v_u. simpl in H13. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl.
subst. destruct b. rewrite->SecLang.join_tloc_b. simpl. apply project_hp_Loverwrite. apply H8. apply SecLang.v_l. reflexivity. simpl in H13. rewrite<-H13. reflexivity. assert (SecLang.joinvs (SecLang.tloc T (Some n0) H) L = SecLang.joinvs (SecLang.tloc T (Some n0) L) H). reflexivity.
rewrite->H1. clear H1. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tloc T (Some n0) L) H, an r L) hp)). apply project_hp_Hoverwrite. apply H8. apply SecLang.v_l. simpl in H13. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl.
simpl. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t2 H, an r H) hp)). apply project_hp_Hoverwrite. apply H8. apply H9. simpl in H14. inversion H14. apply sub_refl. rewrite<-H1. apply same_mark_refl. assert (SecLang.joinTs (an r H)(SecLang.joins L b) = an r H). simpl.
destruct b. reflexivity. reflexivity. rewrite->H1. clear H1. simpl. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t2 H, an r H) hp)). apply project_hp_Hoverwrite. apply H8. apply H9. simpl in H13. remember (SecLang.label t2) as BB. destruct BB. simpl in H13. rewrite<-H13. apply sub_refl.
simpl in H13. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl. subst.
apply IHt1 in H10. apply H10. subst. apply IHt2 in H11. apply H11.
Qed.
(**
Note that marked_heap_lookup has to be respecified such that it searches the
marked_heap according to the first number of the relevant mark.
*)
(*some auxiliary lemmas*)
(*######################*)
Lemma n_plus_neq_n:forall n n',
n <> (n' + (S n)).
Proof. intros n. induction n. intros. intros contra. destruct n'. inversion contra. inversion contra.
intros. intros contra. rewrite<-plus_n_Sm in contra. inversion contra. apply IHn in H1. inversion H1.
Qed.
(*######################*)
(**
Note:[heap_marked_heap_low] guarantees that whenever the query function [return_smallest_match]
returns [false] upon a query [n],we know that the nth value on the marked heap is
[project_e t],given that the nth value on the heap is [t]
*)
Lemma heap_marked_heap_low':forall n t n1 n2 hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match (n+n1) (marked_heap (marked_heap' hp n1) n2)) ->
Some (project_e t) =
marked_efst (marked_heap_lookup (n+n1)
(marked_heap (marked_heap' hp n1) n2)).
Proof. intros. generalize dependent n. generalize dependent t. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. simpl in H1. inversion H1.
Case ("h::t"). intros. destruct n. destruct n1. destruct a. simpl.
remember (SecLang.label t0) as BB. destruct BB. simpl. simpl in H0. subst. reflexivity.
simpl in H1. rewrite<-HeqBB in H1. assert (0<1). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=S n2)in H2.
rewrite<-H2 in H1. inversion H1.
destruct a. simpl. destruct n2. simpl.
remember (SecLang.label t0) as BB. destruct BB. simpl. rewrite<-beq_nat_refl. simpl. simpl in H0. subst.
reflexivity. simpl in H1. rewrite<-HeqBB in H1.
assert (S n1<S (S n1)). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=1)in H2.
rewrite<-H2 in H1. inversion H1.
remember (SecLang.label t0) as BB. destruct BB. simpl. rewrite<-beq_nat_refl. simpl. simpl in H0. subst.
reflexivity. simpl in H1. rewrite<-HeqBB in H1.
assert (S n1<S (S n1)). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=S (S n2))in H2.
rewrite<-H2 in H1. inversion H1.
destruct a. simpl. destruct n1. simpl.
remember (SecLang.label t0) as BB. destruct BB. simpl.
rewrite->plus_n_Sm.
apply IHhp. simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1. simpl in H1.
rewrite->plus_n_Sm in H1. apply H1.
rewrite->plus_n_Sm.
apply IHhp. simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1.
rewrite->plus_n_Sm in H1. apply H1.
simpl. destruct n2.
remember (SecLang.label t0) as BB. destruct BB. simpl.
assert (n1<>n+(S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2.
rewrite->H2. clear H2.
rewrite->plus_n_Sm. apply IHhp.
simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1. simpl in H1.
assert (n1<>n+(S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2.
rewrite->H2 in H1. clear H2. rewrite->plus_n_Sm in H1. apply H1.
rewrite->plus_n_Sm. apply IHhp.
simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1.
rewrite->plus_n_Sm in H1. apply H1.
remember (SecLang.label t0) as BB. destruct BB. simpl.
assert (n1<>n+(S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2.
rewrite->H2. rewrite->plus_n_Sm.
apply IHhp. simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1. simpl in H1.
rewrite->H2 in H1.
rewrite->plus_n_Sm in H1. apply H1.
rewrite->plus_n_Sm. apply IHhp.
simpl in H0. apply H0.
simpl in H1. rewrite<-HeqBB in H1.
rewrite->plus_n_Sm in H1. apply H1.
Qed.
Lemma heap_marked_heap_low:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
Some (project_e t) =
marked_efst (marked_heap_lookup n
(project_hp hp)).
Proof. unfold project_hp. intros. assert (n = n+0). rewrite->plus_comm. reflexivity. rewrite->H2.
clear H2. apply heap_marked_heap_low'. apply H0. rewrite->plus_comm. simpl.
apply H1.
Qed.
(**
Note: Now we are trying to show that the position of the value with the matched
mark on the marked heap is the same as the second number of the matched mark
*)
(*some auxiliary lemmas*)
(*#####################*)
Lemma marked_heap_lookup_Sn_n:forall n n0 n1 n2 hp,
marked_efst (marked_heap_lookup (S n) (marked_heap (marked_heap' hp (S n0)) n1))
= marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n0) n2)).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n1. destruct n0. simpl.
destruct n. rewrite<-HeqBB. simpl. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp n2 0 1 (S n)). apply IHhp.
simpl. rewrite<-HeqBB. destruct n. destruct n2. simpl. specialize (IHhp 0 0 (S (S n0)) 0). apply IHhp. simpl.
specialize (IHhp (S n2) 0 (S (S n0)) 0). apply IHhp. destruct n2. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp 0 0 (S (S n0)) (S n)). apply IHhp. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp (S n2) 0 (S (S n0)) (S n)). apply IHhp. simpl. destruct n0. simpl. rewrite<-HeqBB. simpl.
destruct n. reflexivity. specialize (IHhp n2 (S n1) 1 (S n)). apply IHhp. simpl. rewrite<-HeqBB. destruct n2. simpl. destruct n.
specialize (IHhp 0 (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp 0 (S n1) (S (S n0)) (S n)). apply IHhp.
simpl. destruct n. specialize (IHhp (S n2) (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp (S n2) (S n1) (S (S n0)) (S n)). apply IHhp.
destruct n0. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) 1 n). apply IHhp. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) (S (S n0)) n). apply IHhp.
Qed.
Lemma heap_lookup_n_all_marks:forall hp n n1 n2 n3 n4,
efst (heap_lookup n (marked_heap (marked_heap' hp n1) n2)) =efst (heap_lookup n (marked_heap (marked_heap' hp n3) n4)).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. destruct n3. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n. simpl. reflexivity. simpl. apply IHhp. apply IHhp. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n4. destruct n. simpl. reflexivity. simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp.
apply IHhp. destruct n3. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n2. destruct n. simpl. reflexivity.
simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp. apply IHhp. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. destruct n4. destruct n. simpl. reflexivity. simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp.
destruct n4. destruct n. simpl. reflexivity. simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp.
apply IHhp.
Qed.
Lemma return_None_marked_heap_lookup:forall hp n n1 n2,
n < n1 ->
None = marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n1) n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct n. destruct a. simpl. destruct n1. apply LowLang.lt_same_F in H0.
inversion H0. simpl. destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0.
apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0. apply H0.
apply IHhp. apply le_S in H0. apply H0. destruct a. simpl. destruct n1. inversion H0. simpl.
destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl.
assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
Qed.
(*#####################*)
Lemma lt_Sn_zero:forall n,
0 < S n.
Proof. intros. induction n. apply le_n. apply le_S. apply IHn.
Qed.
Lemma marked_heap_value_tws':forall n n' hp,
marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n') n')) <> None ->
marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n') n')) =
efst (heap_lookup (snd(snd(return_smallest_match n (marked_heap (marked_heap' hp n') n')))) (marked_heap (marked_heap' hp n') n')).
Proof. intros. generalize dependent n. generalize dependent n'. induction hp.
Case ("nil"). intros. simpl. destruct n. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n'. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. destruct n. simpl.
reflexivity. simpl in H0.
rewrite<-HeqBB in H0. simpl in H0. rewrite->marked_heap_lookup_Sn_n with (n2:=0).
assert (0<=0). apply le_n. apply return_smallest_match_snd_Sn_n with (hp:=hp)(n:=n)in H1.
rewrite->H1. clear H1. simpl. rewrite->heap_lookup_n_all_marks with(n3:=0)(n4:=0).
apply IHhp. rewrite->marked_heap_lookup_Sn_n with (n2:=0) in H0. apply H0.
apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. destruct n.
assert (0<S n'). apply lt_Sn_zero.
apply return_None_marked_heap_lookup with(hp:=(t,t0)::hp)(n2:=S n')in H1. rewrite<-H1 in H0. assert (False).
apply H0. reflexivity. inversion H2.
remember (beq_nat n' n) as CC. destruct CC. simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite<-HeqCC in H0.
simpl. rewrite->minus_diag. simpl. reflexivity.
simpl. simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite<-HeqCC in H0.
rewrite->marked_heap_lookup_Sn_n with (n2:=S n'). assert (S n'<=S n'). apply le_n.
apply return_smallest_match_snd_Sn_n with (hp:=hp)(n:=n)in H1. rewrite->H1. clear H1. simpl.
rewrite->heap_lookup_n_all_marks with (n3:=S n')(n4:=S n'). apply IHhp. rewrite->marked_heap_lookup_Sn_n with(n2:=S n') in H0.
apply H0. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
Qed.
Lemma marked_heap_value_tws:forall n hp,
marked_efst (marked_heap_lookup n (project_hp hp)) <> None ->
marked_efst (marked_heap_lookup n (project_hp hp)) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (project_hp hp)).
Proof. unfold project_hp. intros. apply marked_heap_value_tws'. apply H0.
Qed.
(**
Now we are ready to prove the following equality,
v = efst (heap_lookup n hp) where
v = project_conf'_e (project_e t)(project_hp hp0)
n = snd(snd (return_smallest_match n (project_hp hp0)))
hp= erase_hp (project_conf'_hp (project_hp hp0)(project_hp hp0))
*)
(**
Step one,
we get started by proving some lemma where [project_e t] and
[snd(snd (return_smallest_match n (project_hp hp0)))] appear on opposite sides of
an equality,
*)
Lemma cs_derefloc_one:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
Some (project_e t) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (project_hp hp)).
Proof. intros. apply heap_marked_heap_low in H0. rewrite->H0. apply marked_heap_value_tws.
rewrite<-H0. intros contra. inversion contra. apply H1.
Qed.
(**
Step two,
we prove that if we use the same "query",[n],instead on the marked heap obtained
from evaluating every value on [project_hp hp] from [project_hp hp] we get a new
value obtained from evaluating the old one,[project_e t],from [project_hp hp],
*)
Lemma heap_lookup_project_conf'_hp':forall n hp hp' v,
efst (heap_lookup n hp) = Some v ->
efst (heap_lookup n (project_conf'_hp hp hp'))
= Some (project_conf'_e v hp').
Proof. intros. generalize dependent n. generalize dependent hp'. generalize dependent v.
induction hp.
Case ("nil"). intros. destruct n. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct n. destruct a. destruct p. simpl in H0. simpl. inversion H0.
reflexivity. destruct a. destruct p. simpl. apply IHhp. simpl in H0. apply H0.
Qed.
Lemma heap_lookup_project_conf'_hp:forall n hp v,
efst (heap_lookup n hp) = Some v ->
efst (heap_lookup n (project_conf'_hp hp hp))
= Some (project_conf'_e v hp).
Proof. intros. apply heap_lookup_project_conf'_hp'. apply H0.
Qed.
Lemma cs_derefloc_two':forall n t hp,
Some (project_e t) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (project_hp hp)) ->
Some (project_conf'_e (project_e t)(project_hp hp)) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp))))) (project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp)) = true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H1. rewrite<-H1. clear H1.
symmetry. apply heap_lookup_project_conf'_hp. symmetry. apply H0.
Qed.
Lemma cs_derefloc_two:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
Some (project_conf'_e (project_e t)(project_hp hp)) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp))))) (project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. apply cs_derefloc_two'. apply cs_derefloc_one. apply H0. apply H1.
Qed.
(*one extra lemma related to [cs_derefloc_two]*)
(*############################################*)
Lemma heap_lookup_n_length: forall hp n v,
efst (heap_lookup n hp) = Some v ->
n < length hp.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct n. simpl. apply lt_0_Sn. simpl. apply SecLang.n_iff_Sn_left. apply IHhp with (v:=v).
simpl in H0. apply H0.
Qed.
(*############################################*)
(**
Step three,
finishing up by establishing relation between [heap_lookup] and [efst] in [LowLang]
and their counterparts in the current block,
efst (heap_lookup n hp) = Some (LowLang.efst (LowLang.heap_lookup n (erase hp)))
when there is a hit,
*)
Lemma cs_derefloc_three:forall n hp,
efst (heap_lookup n hp) <> None ->
efst (heap_lookup n hp) = Some (LowLang.efst (LowLang.heap_lookup n (erase_hp hp))).
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. assert (False). apply H0. reflexivity.
inversion H1. simpl in H0. assert (False). apply H0. reflexivity. inversion H1.
Case ("h::t"). intros. destruct n. destruct a. destruct p. simpl. reflexivity. simpl. destruct a.
apply IHhp. simpl in H0. apply H0.
Qed.
Lemma cs_derefloc:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
project_conf'_e (project_e t)(project_hp hp) =
LowLang.efst (LowLang.heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (erase_hp (project_conf'_hp (project_hp hp)(project_hp hp)))).
Proof. intros. apply cs_derefloc_two in H0.
assert (efst (heap_lookup(snd(snd(return_smallest_match n
(project_conf'_hp (project_hp hp) (project_hp hp)))))
(project_conf'_hp (project_hp hp) (project_hp hp)))<>None).
intros contra. rewrite<-H0 in contra. inversion contra.
apply cs_derefloc_three in H2. rewrite->H2 in H0. clear H2. inversion H0.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true).
apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n) in H2.
rewrite->H2. clear H2. apply H3.
apply H1.
Qed.
(**
Note the following block contains lemmas necessary to prove the sub-case,[st_assign],
in [corresp_step]
*)
(*##################*)
Lemma replace_BA_marked_heap_project_hp:forall n n1 n2 (v:SecLang.tm) (T:Ty) (hp:SecLang.heap),
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
marked_heap (marked_heap' (SecLang.heap_replace n (v,T) hp) n1) n2 =
marked_heap_replace (n+n1) (project_e v,T) (marked_heap (marked_heap' hp n1) n2).
Proof. intros. generalize dependent n. generalize dependent n1. generalize dependent n2.
generalize dependent v. generalize dependent T.
induction hp.
Case ("nil"). intros. simpl in H0. destruct n. apply LowLang.lt_same_F in H0. inversion H0.
inversion H0.
Case ("h::t"). intros. destruct n.
SCase ("n=0").
destruct a. simpl. simpl in H1. destruct n1. simpl.
remember (SecLang.label v) as BB. destruct BB. rewrite<-H1.
simpl. reflexivity. rewrite<-H1. assert (0<1). apply le_n.
apply marked_heap_replace_same with (hp:=hp)(n2:=S n2)(p:=(project_e v,T)) in H2.
rewrite->H2. reflexivity.
simpl. remember (SecLang.label v) as BB. destruct BB. rewrite<-H1. destruct n2. simpl.
rewrite<-beq_nat_refl. reflexivity. simpl. rewrite<-beq_nat_refl. reflexivity. rewrite<-H1.
assert ((S n1)<(S (S n1))). apply le_n. apply marked_heap_replace_same with (hp:=hp)(n2:=S n2)(p:=(project_e v,T)) in H2.
rewrite->H2. reflexivity.
SCase ("n=S n'").
destruct a. simpl. destruct n1. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl.
specialize (IHhp T v n2 1 n). simpl in H0. apply SecLang.lt_same_F' in H0. apply IHhp in H0.
rewrite<-plus_n_O. rewrite->plus_comm in H0. simpl in H0. rewrite->H0. reflexivity. simpl in H1.
apply H1. rewrite->plus_comm. simpl. specialize (IHhp T v (S n2) 1 n). simpl in H0.
apply SecLang.lt_same_F' in H0. apply IHhp in H0. rewrite->plus_comm in H0. simpl in H0.
rewrite->H0. reflexivity. simpl in H1. apply H1. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. simpl. assert (n1<>(n+ S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2. rewrite->H2.
clear H2. specialize (IHhp T v 0 (S (S n1)) n). simpl in H0. apply SecLang.lt_same_F' in H0. apply IHhp in H0.
rewrite->plus_n_Sm. rewrite->H0. reflexivity. simpl in H1. apply H1. simpl.
assert (n1<>(n + S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2. rewrite->H2. clear H2.
specialize (IHhp T v (S n2)(S (S n1)) n). simpl in H0. apply SecLang.lt_same_F' in H0. apply IHhp in H0.
rewrite->plus_n_Sm. rewrite->H0. reflexivity. simpl in H1. apply H1. rewrite->plus_n_Sm.
simpl in H0. apply SecLang.lt_same_F' in H0. specialize (IHhp T v (S n2)(S (S n1)) n). apply IHhp in H0.
rewrite->H0. reflexivity. simpl in H1. apply H1.
Qed.
Lemma same_mark_marked_heap_replace':forall n (v:SecLang.tm) (T:Ty) (hp:SecLang.heap),
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
same_mark (marked_heap (marked_heap' hp 0)0)
(marked_heap (marked_heap' (SecLang.heap_replace n (v,T) hp)0)0) = true.
Proof. intros. inversion H0.
Case ("tcon"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_c. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tcon n0 H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_c. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tcon_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Case ("tabs"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_f. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tabs (Id n0) T0 e H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_f. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tabs_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Case ("tunit"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_u. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tunit H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_u. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tunit_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Case ("tloc"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_l. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tloc T0 (Some n0) H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_l. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tloc_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Qed.
Lemma same_mark_marked_heap_replace:forall n n1 n2 (v:SecLang.tm) (T:Ty) (hp:SecLang.heap),
n2<=n1 ->
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
same_mark (marked_heap (marked_heap' hp n1)n2)
(marked_heap (marked_heap' (SecLang.heap_replace n (v,T) hp)n1)n2) = true.
Proof. intros. apply same_mark_marked_heap_replace' with(n:=n)(T:=T)(hp:=hp) in H1.
apply same_mark_marked_heap_generalize. apply H0. apply H1. apply H2. apply H3.
Qed.
Lemma project_conf'_hp_marked_heap_replace_1:forall n v T hp,
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp))
=project_conf'_hp (marked_heap_replace n (project_e v,T) (project_hp hp)) (project_hp hp).
Proof. intros. assert (n<length hp). apply H1. apply replace_BA_marked_heap_project_hp with (n1:=0)(n2:=0)(v:=v)(T:=T)in H1.
rewrite->plus_comm in H1. simpl in H1. unfold project_hp. rewrite<-H1.
apply same_mark_marked_heap_replace' with (n:=n)(T:=T)(hp:=hp) in H0.
apply project_conf'_hp_same_mark with (hp:=marked_heap (marked_heap' (SecLang.heap_replace n (v, T) hp) 0) 0)in H0.
rewrite<-H0. reflexivity. apply H3. apply H2. apply H2.
Qed.
Lemma project_conf'_hp_marked_heap_replace_2:forall N V T HP HP',
project_conf'_hp (marked_heap_replace N (V,T) HP) HP'
= marked_heap_replace N (project_conf'_e V HP',T)(project_conf'_hp HP HP').
Proof. intros. generalize dependent N. generalize dependent V. generalize dependent T.
generalize dependent HP'. induction HP.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p0. simpl. remember (beq_nat n N) as BB. destruct BB.
destruct p. simpl. rewrite<-HeqBB. reflexivity. destruct p. simpl. rewrite<-HeqBB.
specialize (IHHP HP' T V N). rewrite->IHHP. reflexivity.
Qed.
Lemma project_conf'_hp_marked_heap_replace:forall v T n hp,
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp))
=marked_heap_replace n (project_conf'_e (project_e v) (project_conf'_hp (project_hp hp)(project_hp hp)),T)
(project_conf'_hp (project_hp hp)(project_hp hp)).
Proof. intros. apply project_conf'_hp_marked_heap_replace_1 with (n:=n)(T:=T)(hp:=hp)in H0.
assert (same_mark (project_hp hp) (project_conf'_hp (project_hp hp) (project_hp hp)) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e v)in H3. rewrite<-H3.
rewrite<-project_conf'_hp_marked_heap_replace_2. apply H0.
apply H1. apply H2.
Qed.
(*some auxiliary lemmas for the following lemma*)
(*##############################################*)
Lemma add_both_mark_marked_heap_replace:forall hp n n1 n2 V T,
n2<=n1 ->
marked_heap_replace (S n) (V,T) (marked_heap(marked_heap' hp (S n1))n2)
=add_both_mark (marked_heap_replace n (V,T) (marked_heap(marked_heap' hp n1)n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. destruct n1. simpl. destruct n. rewrite<-HeqBB. simpl.
assert (0<=1). apply le_S. apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1.
simpl in H1. rewrite<-H1. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp (S n) 1 0 V T).
assert (0<=1). apply le_S. apply le_n. apply IHhp in H1. rewrite->H1. reflexivity. simpl. rewrite<-HeqBB.
destruct n. simpl. rewrite->plus_comm. simpl. specialize (IHhp 0 (S (S n1)) 0 V T). apply le_S in H0.
apply IHhp in H0. rewrite<-H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC. simpl.
rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. assert (0<=S (S n1)). apply SecLang.zero_n.
apply marked_heap_add_both_mark with (hp:=hp) in H1. rewrite->plus_comm in H1. simpl in H1. rewrite<-H1.
reflexivity. simpl. rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. specialize (IHhp (S n) (S (S n1)) 0 V T).
apply le_S in H0. apply IHhp in H0. rewrite->H0. reflexivity. destruct n1. inversion H0. simpl. rewrite<-HeqBB.
destruct n2. destruct n. simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. specialize (IHhp 0 (S (S n1)) 1 V T).
apply le_S in H0. apply IHhp in H0. rewrite->H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC.
simpl. rewrite<-HeqCC. simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. apply le_S in H0.
apply marked_heap_add_both_mark with (hp:=hp) in H0. rewrite->plus_comm in H0. simpl in H0. rewrite<-H0. reflexivity.
simpl. rewrite<-HeqCC. simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. specialize (IHhp (S n) (S (S n1)) 1 V T).
apply le_S in H0. apply IHhp in H0. rewrite->H0. reflexivity. destruct n. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm.
simpl. assert (S (S n2)<=S n1). apply H0. apply SecLang.lt_snoc_1 in H0. apply minus_Sn_m in H0. rewrite->H0. simpl. specialize (IHhp 0 (S (S n1)) (S (S n2)) V T).
apply SecLang.lt_snoc_1 in H1. apply le_S in H1. apply SecLang.n_iff_Sn_left in H1. apply IHhp in H1. rewrite->H1. reflexivity.
remember (beq_nat n1 n) as CC. destruct CC. simpl. rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl. assert (S (S n2)<=S n1). apply H0.
apply SecLang.lt_snoc_1 in H0. apply minus_Sn_m in H0. rewrite->H0. simpl. apply le_S in H1. apply marked_heap_add_both_mark with (hp:=hp) in H1. rewrite->plus_comm in H1.
simpl in H1. rewrite->H1. reflexivity. simpl. rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl. assert (S (S n2)<=S n1). apply H0. apply SecLang.lt_snoc_1 in H0.
apply minus_Sn_m in H0. rewrite->H0. simpl. specialize (IHhp (S n) (S (S n1)) (S (S n2)) V T). apply le_S in H1. apply IHhp in H1. rewrite->H1. reflexivity. destruct n. destruct n1.
simpl. rewrite<-HeqBB. specialize (IHhp 0 1 (S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. rewrite->H0. reflexivity. simpl. rewrite<-HeqBB. specialize (IHhp 0 (S (S n1)) (S n2) V T).
apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0.
destruct n. destruct n1. simpl. rewrite<-HeqBB. specialize (IHhp 1 1 (S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0.
simpl. rewrite<-HeqBB. specialize (IHhp 1 (S (S n1))(S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0. destruct n1. simpl.
rewrite<-HeqBB. specialize (IHhp (S (S n)) 1 (S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0. simpl. rewrite<-HeqBB.
specialize (IHhp (S (S n))(S (S n1))(S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0.
Qed.
Lemma add_both_mark_heap_replace:forall hp n n1 n2 V T,
n2<=n1->
heap_replace n (V,T) (marked_heap(marked_heap' hp (S n1))n2)
=add_both_mark (heap_replace n (V,T) (marked_heap(marked_heap' hp n1)n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct n. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n2. destruct n1. simpl. rewrite<-HeqBB.
destruct n. simpl. assert (0<=1). apply le_S. apply le_n.
apply marked_heap_add_both_mark with (hp:=hp) in H1. simpl in H1.
rewrite->H1. clear H1. reflexivity. simpl. specialize (IHhp n 1 0 V T).
apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity. simpl. rewrite<-HeqBB. destruct n. simpl.
rewrite->plus_comm. simpl. assert (0<=S (S n1)). apply SecLang.zero_n.
apply marked_heap_add_both_mark with (hp:=hp) in H1. rewrite->plus_comm in H1.
simpl in H1. rewrite->H1. reflexivity. simpl. rewrite->plus_comm. simpl.
specialize (IHhp n (S (S n1)) 0 V T). apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity.
destruct n1. inversion H0. simpl. rewrite<-HeqBB. destruct n2. destruct n.
simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. apply le_S in H0.
apply marked_heap_add_both_mark with (hp:=hp) in H0. rewrite->plus_comm in H0.
simpl in H0. rewrite->H0. reflexivity. simpl. rewrite<-minus_n_O. rewrite->plus_comm.
simpl. specialize (IHhp n (S (S n1)) 1 V T). apply le_S in H0. apply IHhp in H0. rewrite->H0.
reflexivity. destruct n. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl.
assert (S n2<=n1). apply SecLang.lt_same_F' in H0.
apply H0. apply minus_Sn_m in H1. rewrite->H1. clear H1. simpl. apply le_S in H0.
apply marked_heap_add_both_mark with (hp:=hp) in H0. rewrite->plus_comm in H0. simpl in H0.
rewrite->H0. reflexivity. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl.
assert (S n2<=n1). apply SecLang.lt_same_F' in H0. apply H0. apply minus_Sn_m in H1. rewrite->H1.
clear H1. simpl. specialize (IHhp n (S (S n1))(S(S n2)) V T). apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity. destruct n1. destruct n. destruct n2.
assert (marked_heap((t,t0,(0,0))::marked_heap' hp 1)0=marked_heap(marked_heap' hp 1)1). simpl.
rewrite<-HeqBB. reflexivity. rewrite->H1. apply SecLang.n_iff_Sn_left in H0. specialize (IHhp 0 1 1 V T).
apply IHhp in H0. rewrite->H0. reflexivity. inversion H0. destruct n2.
assert (marked_heap((t,t0,(0,0))::marked_heap' hp 1)0=marked_heap(marked_heap' hp 1)1). simpl.
rewrite<-HeqBB. reflexivity. rewrite->H1. clear H1. apply SecLang.n_iff_Sn_left in H0.
specialize (IHhp (S n) 1 1 V T). apply IHhp in H0. apply H0. inversion H0.
assert (marked_heap((t,t0,(S n1,S n1))::marked_heap' hp (S (S n1)))n2=marked_heap(marked_heap' hp (S (S n1)))(S n2)). simpl.
rewrite<-HeqBB. reflexivity. rewrite->H1. clear H1. apply SecLang.n_iff_Sn_left in H0. specialize (IHhp n (S (S n1))(S n2) V T).
apply IHhp in H0. apply H0.
Qed.
(*##############################################*)
Lemma marked_heap_replace_heap_replace':forall n n' V T hp,
fst (return_smallest_match n (marked_heap (marked_heap' hp n') n')) = false -> (*restricted to "low to low" case*)
marked_heap_replace n (V,T) (marked_heap (marked_heap' hp n') n')
= heap_replace (snd(snd(return_smallest_match n (marked_heap (marked_heap' hp n') n'))))(V,T) (marked_heap (marked_heap' hp n') n').
Proof. intros. generalize dependent n. generalize dependent n'. generalize dependent V. generalize dependent T.
induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. simpl. destruct n'. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. destruct n. simpl. reflexivity. assert (0<=0). apply le_n.
apply return_smallest_match_snd_Sn_n with(hp:=hp)(n:=n) in H1. rewrite->H1. clear H1.
simpl. assert (0<=0). apply le_n. apply add_both_mark_marked_heap_replace with (hp:=hp)(n:=n)(V:=V)(T:=T)in H1.
rewrite->H1. clear H1. assert (0<=0). apply le_n.
apply add_both_mark_heap_replace with (hp:=hp)(n:=snd (snd (return_smallest_match n (marked_heap (marked_heap' hp 0) 0))))(V:=V)(T:=T) in H1.
rewrite->H1. clear H1. specialize (IHhp T V 0 n). simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite->return_smallest_match_Sn_n with (n:=n)(n1:=0)(n2:=0)in H0.
apply IHhp in H0. rewrite->H0. reflexivity. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. destruct n. assert (0<S n'). apply SecLang.n_iff_Sn_left. apply SecLang.zero_n. apply return_true_marked_heap with (hp:=((t,t0)::hp))(n2:=(S n'))in H1.
rewrite<-H1 in H0. clear H1. inversion H0. simpl. remember (beq_nat n' n) as CC. destruct CC.
simpl. rewrite->minus_diag. simpl. reflexivity. rewrite->minus_diag.
assert (S n'<=S n'). apply le_n. apply return_smallest_match_snd_Sn_n with(hp:=hp)(n:=n) in H1. rewrite->H1. clear H1. simpl.
assert (S n'<=S n'). apply le_n. apply add_both_mark_marked_heap_replace with (hp:=hp)(n:=n)(V:=V)(T:=T)in H1.
rewrite->H1. clear H1. assert (S n'<=S n'). apply le_n.
apply add_both_mark_heap_replace with (hp:=hp)(n:=snd (snd (return_smallest_match n (marked_heap (marked_heap' hp (S n')) (S n')))))(V:=V)(T:=T) in H1.
rewrite->H1. clear H1. specialize (IHhp T V (S n') n). simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite<-HeqCC in H0. rewrite->return_smallest_match_Sn_n with (n:=n)(n1:=S n')(n2:=S n')in H0.
apply IHhp in H0. rewrite->H0. reflexivity. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
Qed.
Lemma marked_heap_replace_project_conf'_hp:forall n v T HP HP',
marked_heap_replace n (project_conf'_e v HP',T)(project_conf'_hp HP HP')
=project_conf'_hp (marked_heap_replace n (v,T) HP) HP'.
Proof. intros. generalize dependent n. generalize dependent v. generalize dependent T. generalize dependent HP'.
induction HP.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. destruct p0. simpl. remember (beq_nat n0 n) as BB. destruct BB.
simpl. reflexivity. simpl. specialize (IHHP HP' T v n). rewrite->IHHP. reflexivity.
Qed.
Lemma heap_replace_project_conf'_hp:forall n v T HP HP',
heap_replace n (project_conf'_e v HP',T)(project_conf'_hp HP HP')
=project_conf'_hp (heap_replace n (v,T) HP) HP'.
Proof. intros. generalize dependent n. generalize dependent v. generalize dependent T.
generalize dependent HP'. induction HP.
Case ("nil"). intros. destruct n. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. destruct p0. simpl. destruct n. simpl. reflexivity.
simpl. specialize (IHHP HP' T v n). rewrite->IHHP. reflexivity.
Qed.
Lemma marked_heap_replace_heap_replace:forall n v T hp,
fst (return_smallest_match n (project_hp hp)) = false -> (*restricted to "low to low" case*)
marked_heap_replace n (project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T) (project_conf'_hp (project_hp hp)(project_hp hp))
= heap_replace (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp)))))
(project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T)
(project_conf'_hp (project_hp hp)(project_hp hp)).
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true). apply same_mark_heap. apply project_conf'_e_same_mark with(t:=project_e v)in H1.
rewrite<-H1. clear H1. rewrite->marked_heap_replace_project_conf'_hp.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H1.
rewrite<-H1. clear H1. rewrite->heap_replace_project_conf'_hp. unfold project_hp in H0. apply marked_heap_replace_heap_replace' with (V:=project_e v)(T:=T)in H0. unfold project_hp.
rewrite<-H0. reflexivity.
Qed.
Lemma project_conf'_hp_heap_replace':forall v T n hp,
SecLang.value v ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
fst (return_smallest_match n (project_hp hp)) = false ->
project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp))
=heap_replace (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp)))))
(project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T)
(project_conf'_hp (project_hp hp)(project_hp hp)).
Proof. intros. apply project_conf'_hp_marked_heap_replace with(T:=T)(n:=n)(hp:=hp) in H0.
apply marked_heap_replace_heap_replace with(v:=v)(T:=T)in H2. rewrite->H2 in H0. apply H0. apply return_smallest_match_F_length in H2.
apply H2. apply H1.
Qed.
Lemma project_conf'_hp_heap_replace'':forall N V T HP,
erase_hp (heap_replace N (V,T) HP)
=LowLang.heap_replace N (V,T)(erase_hp HP).
Proof. intros. generalize dependent N. generalize dependent V. generalize dependent T.
induction HP.
Case ("nil"). intros. destruct N. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. destruct N. simpl. reflexivity.
simpl. specialize (IHHP T V N). rewrite->IHHP. reflexivity.
Qed.
Lemma project_conf'_hp_heap_replace:forall v T n hp,
SecLang.value v ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
fst (return_smallest_match n (project_hp hp)) = false ->
erase_hp (project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp)))
=LowLang.heap_replace (snd(snd(return_smallest_match n (project_hp hp))))
(project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T)
(erase_hp (project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n)in H3. rewrite->H3. clear H3. rewrite<-project_conf'_hp_heap_replace''.
apply project_conf'_hp_heap_replace' with(T:=T)(n:=n)(hp:=hp)in H0. rewrite<-H0. reflexivity.
apply H1. apply H2.
Qed.
Lemma return_smallest_match_snd_length:forall n hp,
fst (return_smallest_match n (marked_heap(marked_heap' hp 0)0)) = false ->
snd(snd(return_smallest_match n (marked_heap(marked_heap' hp 0)0))) < length (marked_heap(marked_heap' hp 0)0).
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. simpl. destruct n. simpl.
apply SecLang.n_iff_Sn_left. apply SecLang.zero_n. assert (0<=0). apply le_n.
apply return_smallest_match_snd_Sn_n with (hp:=hp)(n:=n) in H1. rewrite->H1. clear H1. apply SecLang.n_iff_Sn_left.
rewrite->marked_heap_mark_length with (n3:=0)(n4:=0). simpl in H0. rewrite<-HeqBB in H0. simpl in H0.
rewrite->return_smallest_match_Sn_n with (n2:=0)in H0. apply IHhp. apply H0. simpl in H0. rewrite<-HeqBB in H0.
destruct n. assert (0<1). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=1)in H1. rewrite<-H1 in H0. clear H1.
inversion H0. assert (fst (return_smallest_match (S n)(marked_heap(marked_heap' hp 1)1))=false). apply H0.
rewrite->return_smallest_match_Sn_Sn with(n2:=0)in H1. apply return_smallest_match_snd_Sn_Sn in H1.
rewrite->H1. clear H1. rewrite->marked_heap_mark_length with(n3:=0)(n4:=0). apply IHhp.
rewrite->return_smallest_match_Sn_Sn with(n2:=0)in H0. apply H0.
Qed.
(*##################*)
Lemma corresp_step:forall e e' hp hp',
SecLang.step (e,hp) L (e',hp') ->
LowLang.Multi LowLang.step (project (e,hp)) L (project (e',hp')).
Proof. intros. induction H0. (*induction upon the reduction relation in [SecLang]*)
Case ("st_prot").
intros. destruct b. simpl. destruct PC. simpl in H0. apply IHstep. simpl in IHstep. apply IHstep.
destruct PC. simpl in IHstep. unfold project. simpl. simpl in H0. apply proj_hp_H_same in H2. rewrite->H2.
apply LowLang.Multi_refl.
unfold project. simpl. simpl in H2. apply proj_hp_H_same in H2. rewrite->H2. apply LowLang.Multi_refl.
Case ("st_protv").
destruct b. unfold project. simpl. inversion H2.
rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tabs_b.
rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl.
simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl.
inversion H2. rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl.
rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tunit_b.
rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl.
apply LowLang.Multi_refl.
Case ("st_appabs").
destruct b. unfold project. simpl. unfold project_conf. simpl. rewrite->project_e_subst. rewrite->project_conf'_subst.
apply LowLang.Multi_step with (y:=(LowLang.subst x
(project_conf'_e (project_e v)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))
(project_conf'_e (project_e e0)
(project_conf'_hp (project_hp hp0) (project_hp hp0))),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))).
apply LowLang.st_appabs. apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl. apply H3. unfold project. simpl. unfold project_conf.
simpl. apply LowLang.Multi_step with (y:=(LowLang.tH,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_apptH.
apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl.
Case ("st_app1").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H3. inversion H3.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H4. apply H5. apply same_mark_sym in H6. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H7. apply H6. apply project_conf'_e_same_mark with (t:=project_e t2)in H8. rewrite->H8. clear H4.
clear H5. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_app1. apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H4. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e t2)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H5. reflexivity. rewrite->H6. assert ((project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H2. rewrite<-H7. clear H5. clear H6. clear H7.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_app1. apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H3. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H3. reflexivity. rewrite->H4. clear H4.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_app1. apply IHstep.
Case ("tapp2").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H4. inversion H4.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H5. apply H6. apply same_mark_sym in H7. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H8. apply H7. apply project_conf'_e_same_mark with (t:=project_e v1)in H9. rewrite->H9. clear H5.
clear H6. clear H7. clear H8. clear H9.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_app2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H5. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e v1)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H6. reflexivity. rewrite->H7. assert ((project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e v1)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H1. rewrite<-H8. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H6. clear H6.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H6. clear H6. apply multi_step_app2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H4. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H4. reflexivity. rewrite->H5. clear H5.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_app2. apply SecLang_value_LowLang. apply H3. apply IHstep.
Case ("st_refv").
subst. destruct b.
unfold project. unfold project_conf. simpl.
inversion H2.
(*v=SecLang.tcon n b*)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tcon_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tcon n)). apply LowLang.v_c. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tcon n,an r L))in H0. rewrite->H0. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(LowLang.tcon n, an r L, (length hp0, length (project_hp hp0)))))). apply LowLang.st_refv. apply LowLang.v_c. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_c. right. left. reflexivity. apply LowLang.Multi_refl. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_c. right. right. reflexivity. apply LowLang.Multi_refl. subst. rewrite->SecLang.join_tcon_b. simpl. assert (SecLang.joinvs (SecLang.tcon n L) H = SecLang.tcon n H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tcon n L)). apply SecLang.v_c. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*v=SecLang.tabs (Id n) T0 e0 b*)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tabs_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tabs (Id n) T0 (project_e e0))). apply LowLang.v_f. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tabs (Id n) T0 (project_e e0),an r L))in H0. rewrite->H0. apply LowLang.Multi_step with (y:= (LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(LowLang.tabs (Id n) T0
(project_conf'_e (project_e e0)
(LowLang.snoc (project_hp hp0)
(LowLang.tabs (Id n) T0 (project_e e0), an r L,
(length hp0, length (project_hp hp0))))), an r L,
(length hp0, length (project_hp hp0)))))).
apply LowLang.st_refv. apply LowLang.v_f. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. inversion H1. subst. apply SecLow_well_formed in H9. apply project_conf'_e_add_one_low' with(Hp:=project_hp hp0)(L0:=(LowLang.tabs (Id n) T0 (project_e e0),an r L)) in H9. rewrite<-H9.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e e0) in H4. rewrite->H4.
clear H4.
reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_f. right. left. reflexivity. apply LowLang.Multi_refl. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_f. right. right. reflexivity. apply LowLang.Multi_refl. subst. rewrite->SecLang.join_tabs_b. simpl. assert (SecLang.joinvs (SecLang.tabs (Id n) T0 e0 L) H = SecLang.tabs (Id n) T0 e0 H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tabs (Id n) T0 e0 L)). apply SecLang.v_f. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*v=tunit b*)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tunit_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tunit)). apply LowLang.v_u. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tunit,an r L))in H0. rewrite->H0. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(LowLang.tunit, an r L, (length hp0, length (project_hp hp0)))))). apply LowLang.st_refv. apply LowLang.v_u. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_u. right. left. reflexivity. apply LowLang.Multi_refl. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_u. right. right. reflexivity. apply LowLang.Multi_refl. subst. rewrite->SecLang.join_tunit_b. simpl. assert (SecLang.joinvs (SecLang.tunit L) H = SecLang.tunit H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tunit L)). apply SecLang.v_u. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*v = SecLang.tloc T0 (Some n) b *)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tloc_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tloc T0 (Some n))). apply LowLang.v_l. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tloc T0 (Some n),an r L))in H0. rewrite->H0. inversion H1. subst. assert (n<>length hp0). intros contra. rewrite<-contra in H8. apply LowLang.lt_same_F in H8. inversion H8.
apply return_smallest_match_not_hit_snoc with (n3:=length (project_hp hp0))(L:=(LowLang.tloc T0 (Some n),an r L))(hp:=project_hp hp0) in H4. rewrite->H4. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H5. rewrite->H5.
clear H5.
apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(if fst (return_smallest_match n (project_hp hp0))
then LowLang.tloc T0 None
else
LowLang.tloc T0
(Some (snd (snd (return_smallest_match n (project_hp hp0))))),
an r L, (length hp0, length (project_hp hp0)))))). apply LowLang.st_refv. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
apply LowLang.v_l. apply LowLang.v_l. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
intros contra. inversion contra. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H4. rewrite->H4.
clear H4. clear H3. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_l. right. left. reflexivity.
apply LowLang.Multi_refl.
apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_l. right. left. reflexivity.
apply LowLang.Multi_refl.
simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H4. rewrite->H4.
clear H4. clear H3. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_l. right. right. reflexivity. apply LowLang.Multi_refl.
apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_l. right. right. reflexivity. apply LowLang.Multi_refl.
subst. rewrite->SecLang.join_tloc_b. simpl. assert (SecLang.joinvs (SecLang.tloc T0 (Some n) L) H = SecLang.tloc T0 (Some n) H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tloc T0 (Some n) L)). apply SecLang.v_l. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*high pointer*)
unfold project. unfold project_conf. simpl. rewrite->SecLang.joins_refl. simpl. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H2. rewrite<-H2. apply LowLang.Multi_refl.
Case ("st_ref").
destruct b. destruct PC. simpl in H2. unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_ref. apply IHstep. simpl in H2.
simpl in IHstep. unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_ref. apply IHstep. rewrite->SecLang.joins_refl in H2. simpl in H2. unfold project. simpl. apply proj_hp_H_same in H2. rewrite->H2. apply LowLang.Multi_refl.
Case ("st_derefloc").
destruct b. unfold project. unfold project_conf. simpl.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H3. rewrite<-H3. clear H3.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e t) in H3. rewrite<-H3. clear H3.
remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB. rewrite->H2. apply return_smallest_match_project_e_true in H1. rewrite->H1. apply LowLang.Multi_step with (y:=(project_conf'_e LowLang.tH (project_hp hp0),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_derefloctH. apply LowLang.Multi_refl. symmetry. apply HeqBB. unfold project_hp in HeqBB.
apply LowLang.Multi_step with (y:=(project_conf'_e (project_e t) (project_hp hp0),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_derefloc. (*referring to [marked_heap_value_tws]*)
apply cs_derefloc_two in H2. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H3. rewrite<-H3 in H2. clear H3. symmetry in H2. apply heap_lookup_n_length in H2.
rewrite->erase_hp_length. apply H2. apply HeqBB.
apply cs_derefloc in H2. apply H2. apply HeqBB. apply LowLang.Multi_refl.
unfold project. unfold project_conf. simpl. apply LowLang.Multi_step with (y:=(LowLang.tH, erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_dereftH. apply LowLang.Multi_refl.
Case ("st_deref").
destruct PC. unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_deref. apply IHstep.
unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_deref. apply IHstep.
Case ("st_assign").
unfold project. unfold project_conf. destruct PC. destruct b. destruct l. destruct b'. simpl. simpl in H6. rewrite->H6. simpl. simpl in H7.
(*low cell being over-written by a low value*)
apply return_smallest_match_project_hp_hit in H2. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H13. rewrite<-H13. clear H13. rewrite->H2.
apply LowLang.Multi_step with (y:=(LowLang.tunit,
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). apply LowLang.st_assign. rewrite->erase_hp_length. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true).
apply same_mark_heap. apply same_mark_length in H13. rewrite<-H13. clear H13. unfold project_hp. apply return_smallest_match_snd_length. apply H2.
apply SecLang_value_LowLang. apply H3. intros contra. inversion H3.
(*tcon*) subst. compute in H4. subst. simpl in contra. inversion contra.
(*tabs*) subst. compute in H4. subst. simpl in contra. inversion contra.
(*tunit*) subst. compute in H4. subst. simpl in contra. inversion contra.
(*tloc*) subst. compute in H4. subst. simpl in contra.
remember (fst(return_smallest_match n0(project_conf'_hp (project_hp hp0) (project_hp hp0)))) as C. destruct C.
inversion contra. inversion contra.
split. reflexivity. symmetry. apply H5. subst. assert (SecLang.joinTs T L = T).
destruct T. simpl. reflexivity. rewrite->H6. clear H6.
simpl. assert (SecLang.joinvs v L= v). inversion H3.
(*tcon*) subst. rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
(*tabs*) subst. rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
(*tunit*) subst. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
(*tloc*) subst. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
rewrite->H6. clear H6.
apply project_conf'_hp_heap_replace. apply H3. rewrite->H4 in H7. apply H7. apply H2.
apply LowLang.Multi_refl. symmetry. apply H7.
(*high cell being over-written by a high value*)
(*when PC is low*)
(*subcase 1: v <> tH & SecLang.label T = H*)
simpl. simpl in H6. rewrite->H6. simpl in H7. assert (n<length hp0). apply H2. apply return_smallest_match_project_hp_not_hit in H2.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H14. rewrite<-H14. clear H14. rewrite->H2. simpl in H9. subst.
apply project_hp_Hoverwrite with (t:=v)(T:=T)in H13.
assert (SecLang.joinTs T L=T). destruct T. simpl. reflexivity. rewrite->H6. clear H6. rewrite<-H13. simpl. apply LowLang.Multi_step with (y:=(LowLang.tunit,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_assigntH_L. apply SecLang_value_LowLang. apply H3.
reflexivity. right. symmetry. apply H5. apply LowLang.Multi_refl. apply H3. rewrite<-H7. apply sub_refl. symmetry. apply H7.
(*subcase 2: v= tH*)
simpl. simpl in H6. rewrite->H6. simpl in H7. assert (n<length hp0). apply H2. apply return_smallest_match_project_hp_not_hit in H2.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H14. rewrite<-H14. clear H14. rewrite->H2.
apply project_hp_Hoverwrite with (t:=v)(T:=T)in H13. subst.
assert (SecLang.joinvs v (SecLang.joins (SecLang.labelT T) L)= SecLang.joinvs v H). inversion H3.
(*tcon*) subst. compute in H4. subst. rewrite->SecLang.join_tcon_H. symmetry. apply SecLang.join_tcon_H.
(*tabs*) subst. compute in H4. subst. rewrite->SecLang.join_tabs_H. symmetry. apply SecLang.join_tabs_H.
(*tunit*) subst. compute in H4. subst. rewrite->SecLang.join_tunit_H. symmetry. apply SecLang.join_tunit_H.
(*tloc*) subst. compute in H4. subst. rewrite->SecLang.join_tloc_H. symmetry. apply SecLang.join_tloc_H.
rewrite->H5. clear H5.
assert (SecLang.joinTs T L=T). destruct T. simpl. reflexivity. rewrite->H5. clear H5. rewrite<-H13. simpl. apply LowLang.Multi_step with (y:=(LowLang.tunit,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_assigntH_L. apply SecLang_value_LowLang. apply H3.
reflexivity. left. inversion H3. subst. compute in H4. subst. simpl. reflexivity. subst. compute in H4. subst. simpl. reflexivity. subst. compute in H4. subst. simpl. reflexivity.
subst. compute in H4. subst. simpl. reflexivity.
apply LowLang.Multi_refl. apply H3. rewrite<-H7. apply sub_refl. symmetry. apply H7.
(*high pointer*)
simpl. simpl in H6. rewrite->H6. simpl. subst. apply project_hp_Hoverwrite with (t:=v)(T:=SecLang.joinTs T H)in H2. rewrite->SecLang.joins_refl. simpl. rewrite<-H2.
apply LowLang.Multi_step with (y:=(LowLang.tH, erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))).
apply LowLang.st_assignHP. apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl. apply H3. apply H8.
(*finishing up by casing [b],the label of the pointer*)
destruct b.
(*high cell being over-written by a high value*)
(*when PC is high*)
simpl. simpl in H6. rewrite->H6. assert (n<length hp0). apply H2. apply return_smallest_match_project_hp_not_hit in H2.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H14. rewrite<-H14. clear H14. rewrite->H2. subst.
apply project_hp_Hoverwrite with (t:=v)(T:=SecLang.joinTs T H)in H13.
rewrite->SecLang.joins_refl. simpl.
rewrite<-H13. apply LowLang.Multi_step with (y:=(LowLang.tH,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_assigntH_H. apply SecLang_value_LowLang. apply H3.
reflexivity. apply LowLang.Multi_refl. apply H3. apply H8. rewrite->H6 in H8. remember (SecLang.label (SecLang.efst (SecLang.heap_lookup n hp0))) as C.
destruct C. inversion H8. reflexivity.
(*high pointer*)
simpl. simpl in H6. rewrite->H6. simpl. subst. apply project_hp_Hoverwrite with (t:=v)(T:=SecLang.joinTs T H)in H2. rewrite->SecLang.joins_refl. simpl. rewrite<-H2.
apply LowLang.Multi_step with (y:=(LowLang.tH, erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))).
apply LowLang.st_assignHP. apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl. apply H3. apply H8.
Case ("st_assign1").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H3. inversion H3.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H4. apply H5. apply same_mark_sym in H6. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H7. apply H6. apply project_conf'_e_same_mark with (t:=project_e t2)in H8. rewrite->H8. clear H4.
clear H5. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_assign1. apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H4. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e t2)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H5. reflexivity. rewrite->H6. assert ((project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H2. rewrite<-H7. clear H5. clear H6. clear H7.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_assign1. apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H3. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H3. reflexivity. rewrite->H4. clear H4.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_assign1. apply IHstep.
Case ("st_assign2").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H4. inversion H4.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H5. apply H6. apply same_mark_sym in H7. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H8. apply H7. apply project_conf'_e_same_mark with (t:=project_e v1)in H9. rewrite->H9. clear H5.
clear H6. clear H7. clear H8. clear H9.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_assign2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H5. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e v1)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H6. reflexivity. rewrite->H7. assert ((project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e v1)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H1. rewrite<-H8. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H6. clear H6.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H6. clear H6. apply multi_step_assign2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H4. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H4. reflexivity. rewrite->H5. clear H5.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_assign2. apply SecLang_value_LowLang. apply H3. apply IHstep.
Qed.
(*Theorem 5 in Lu's paper*)
Lemma corresp_eval:forall e e' hp hp',
SecLang.Multi SecLang.step (e,hp) L (e',hp') ->
LowLang.Multi LowLang.step (project (e,hp)) L (project (e',hp')).
Proof. intros. remember L as B. induction H0. apply LowLang.Multi_refl. destruct x. destruct y. subst.
apply corresp_step in H0. unfold project in H0. unfold project_conf in H0.
apply LowLang.multi_trans with
(t':=project_conf'_e (project_e (fst (t0, h0)))(project_conf'_hp (project_hp (snd (t0, h0)))(project_hp (snd (t0, h0)))))
(hp':=erase_hp(project_conf'_hp (project_hp (snd (t0, h0)))(project_hp (snd (t0, h0))))).
apply H0. apply IHMulti. reflexivity.
Qed.
(*NI of static typing with reference*)
Theorem NI:forall x v1 v2 w1 w2 e HT pc rt hp hp' hp'',
SecLang.value v1 ->
SecLang.value v2 -> (*1*)
SecLang.has_type pc empty_context HT v1 (an rt H) -> (*3*)
SecLang.has_type pc empty_context HT v2 (an rt H) -> (*4*)
SecLang.label v1 = H ->
SecLang.label v2 = H -> (*5*)
SecLang.has_type pc (Cupdate empty_context x (Some (an rt H))) HT
e (an int L) -> (*6*)
SecLang.heap_well_typed HT hp -> (*7*) (*8*)
SecLang.value w1 ->
SecLang.value w2 -> (*2*)
SecLang.Multi SecLang.step (SecLang.subst x v1 e,hp) L (w1,hp') -> (*8*)
SecLang.Multi SecLang.step (SecLang.subst x v2 e,hp) L (w2,hp'')-> (*9*)
w1 = w2.
Proof. intros.
(*step one*)
(**
(3),(4),(6),and [substitution_preserves_typing] in [SecLang] imply that
both [SecLang.subst x v1 e] and [SecLang.subst x v2 e] are of type [an int L]
*)
assert (SecLang.has_type pc empty_context HT (SecLang.subst x v1 e) (an int L)).
apply SecLang.substitution_preserves_typing with(pc:=pc)(Gamma:=empty_context)(HT:=HT)(x:=x)(T1:=an rt H)(T2:=an int L)(e:=e) in H0.
apply H0. apply H2. apply H6.
assert (SecLang.has_type pc empty_context HT (SecLang.subst x v2 e) (an int L)).
apply SecLang.substitution_preserves_typing with(pc:=pc)(Gamma:=empty_context)(HT:=HT)(x:=x)(T1:=an rt H)(T2:=an int L)(e:=e) in H1.
apply H1. apply H3. apply H6.
(*step two*)
(**
From [H13] and [H14],obtained from step one,together with [type_uniqueness] in [SecLang]
we conclude that [w1] and [w2] are of type [an int L]
*)
assert (fst (SecLang.subst x v1 e,hp)=SecLang.subst x v1 e). reflexivity.
rewrite<-H14 in H12. clear H14.
apply SecLang.type_uniqueness with(z:=(w1,hp'))(PC:=L)in H12. simpl in H12.
assert (fst (SecLang.subst x v2 e,hp)=SecLang.subst x v2 e). reflexivity.
rewrite<-H14 in H13. clear H14.
apply SecLang.type_uniqueness with(z:=(w2,hp''))(PC:=L)in H13. simpl in H13.
(*step three*)
(**
From the conclusion of [step two] that [w1] and [w2] are of type [an int L] and
(2) we know that [w1=tcon n1 L] and [w2=tcon n2 L]
*)
assert (SecLang.value w1). apply H8. assert (SecLang.value w2). apply H9.
inversion H14. inversion H15. subst.
inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tcon in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H25. subst.
inversion H27. inversion H26. inversion H30. subst. inversion H24. subst.
inversion H13. inversion H28. inversion H31. apply SecLang.inversion_tcon in H33.
inversion H33. inversion H34. inversion H35. inversion H36. inversion H38. subst.
inversion H40. inversion H39. inversion H43. subst. inversion H37. subst.
(*step four*)
(**
From [corresp_eval],(1),(3),(4),[project_conf'_subst],and [determinism_extended]
we conclude that [n1 = n2]. Qed.
*)
apply corresp_eval in H10. apply corresp_eval in H11.
unfold project in H10. simpl in H10. unfold project_conf in H10.
assert (SecLang.value v1). apply H0. apply project_e_subst with (x:=x)(e:=e)in H41.
rewrite->H41 in H10. clear H41. rewrite->project_conf'_subst in H10. simpl in H10.
unfold project in H11. simpl in H11. unfold project_conf in H11.
assert (SecLang.value v2). apply H1. apply project_e_subst with (x:=x)(e:=e)in H41.
rewrite->H41 in H11. clear H41. rewrite->project_conf'_subst in H11. simpl in H11.
assert (project_e v1 = LowLang.tH). inversion H0. subst. compute in H4. subst. reflexivity.
subst. compute in H4. subst. reflexivity. subst. compute in H4. subst. reflexivity.
subst. compute in H4. subst. reflexivity. rewrite->H41 in H10. clear H41. simpl in H10.
assert (project_e v2 = LowLang.tH). inversion H1. subst. compute in H5. subst. reflexivity.
subst. compute in H5. subst. reflexivity. subst. compute in H5. subst. reflexivity.
subst. compute in H5. subst. reflexivity. rewrite->H41 in H11. clear H41. simpl in H11.
assert (LowLang.value (fst(LowLang.tcon n,erase_hp (project_conf'_hp (project_hp hp') (project_hp hp'))))).
simpl. apply LowLang.v_c.
assert (LowLang.value (fst(LowLang.tcon n0,erase_hp (project_conf'_hp (project_hp hp'') (project_hp hp''))))).
simpl. apply LowLang.v_c.
apply LowLang.determinism_extended with (x:=(LowLang.subst x LowLang.tH
(project_conf'_e (project_e e)(project_conf'_hp (project_hp hp) (project_hp hp))),
erase_hp (project_conf'_hp (project_hp hp) (project_hp hp))))
(y:=(LowLang.tcon n,
erase_hp (project_conf'_hp (project_hp hp') (project_hp hp'))))
(z:=(LowLang.tcon n0,
erase_hp (project_conf'_hp (project_hp hp'') (project_hp hp''))))
(PC:=L)in H41. simpl in H41. inversion H41. reflexivity.
simpl. apply LowLang.v_c. apply H10. apply H11.
(*contradictions*)
subst. inversion H13. inversion H16. inversion H18. apply SecLang.inversion_tabs in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H25.
inversion H26. inversion H27. inversion H29. inversion H31. inversion H33. inversion H35.
inversion H37. inversion H39. inversion H41.
subst. inversion H13. inversion H16. inversion H18. apply SecLang.inversion_tunit in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H25. inversion H27.
subst. inversion H29.
subst. inversion H13. inversion H16. inversion H18. apply SecLang.inversion_tloc in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H26.
inversion H28. inversion H30. inversion H32. subst. inversion H34.
subst. inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tabs in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H25.
inversion H26. inversion H27. inversion H29. inversion H31. inversion H33. inversion H35.
inversion H37. inversion H39. inversion H41.
subst. inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tunit in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H25. inversion H27.
subst. inversion H29.
subst. inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tloc in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H26.
inversion H28. inversion H30. inversion H32. subst. inversion H34.
(*tidy-up*)
simpl. apply H7. destruct pc. apply sub_refl. apply sub_LH. apply H11.
simpl. apply H7. destruct pc. apply sub_refl. apply sub_LH. apply H10.
Qed.
End Correspondence.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_1_V
`define SKY130_FD_SC_HS__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_1_V
|
// TimeHoldOver_Qsys_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [23:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [23:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire i_readdatavalid, // .readdatavalid
input wire eic_port_valid, // interrupt_controller_in.valid
input wire [44:0] eic_port_data, // .data
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
TimeHoldOver_Qsys_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.eic_port_valid (eic_port_valid), // interrupt_controller_in.valid
.eic_port_data (eic_port_data), // .data
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// Connects a buffer_BB to a stage and an mstore and takes care of
// transfering data.
module buffer_BB_to_stage
#(
parameter N = 8,
parameter LOG_N = 3,
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
// Start signals
input wire start,
// From buffer_BB
input wire read_full,
input wire [WIDTH+MWIDTH-1: 0] read_data,
output reg read_delete,
// To Stage
output wire [LOG_N-1:0] out_addr0,
output wire [LOG_N-1:0] out_addr1,
output reg out_nd,
output reg [WIDTH-1:0] out_data0,
output reg [WIDTH-1:0] out_data1,
// To mStore
output reg out_mnd,
output reg [MWIDTH-1:0] out_m,
// Whether it is active
output wire active,
output reg error
);
reg [LOG_N-1:0] addr;
assign out_addr0 = addr;
assign out_addr1 = addr + 1;
reg read_counter;
wire [WIDTH-1:0] read_data_s;
wire [MWIDTH-1:0] read_data_m;
assign {read_data_s, read_data_m} = read_data;
reg first_read;
reg active_o;
assign active = active_o | start;
always @ (posedge clk)
begin
// Set the default values;
out_nd <= 1'b0;
read_delete <= 1'b0;
out_mnd <= 1'b0;
if (~rst_n)
begin
active_o <= 1'b0;
addr <= {LOG_N{1'b0}};
read_counter <= 1'b0;
error <= 1'b0;
end
else if (start)
begin
if (active_o)
error <= 1'b1;
else
begin
active_o <= 1'b1;
addr <= {LOG_N{1'b0}};
read_counter <= 1'b0;
first_read <= 1'b1;
end
end
else if (active_o & read_full)
begin
out_mnd <= 1'b1;
out_m <= read_data_m;
// We can only read one item from the buffer each block
// cycle. But we write to the stage two at a time
// so we have to save values and only write every second
// clock cycle.
read_counter <= ~read_counter;
read_delete <= 1'b1;
if (~read_counter)
begin
out_data0 <= read_data_s;
if (~first_read)
addr <= addr + 2;
first_read <= 1'b0;
end
else
begin
out_data1 <= read_data_s;
out_nd <= 1'b1;
if (addr == N-2)
begin
active_o <= 1'b0;
end
end
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd3 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_V |
/*!
* \file ram_cell.v
* \brief Configurable Histogram Cell instance (as part of the HistogramHW module)
* \details This module computes Histograms over a line of pixel cells.
* \author Luca Maggiani
* \version 1.0
* \date Jan 2014
* \pre It needs ram_subcell and ram_module instances
* \param[in] data_in, dir_max, data_valid_in
* \param[out] data_out, data_valid_out
* \todo Why it does not work on odd cell width???
* \todo Different reset_n handling (could onoff signal be a reset
* trigger? (as an onoff_n signal)
* \todo 32bit RAM extension (and data bus as well)
* \see ram_subcell
* \see ram_module
*/
module ram_cell(
clk,
reset_n,
data_in,
dir_max,
data_valid_in,
data_out,
data_valid_out,
cellwidth,
cellinrow,
cellheight,
storecycles,
onoff,
mode,
n_bin_exp,
newcell_signal,
newline_signal,
loadcompleted,
storecompleted,
count_store_int,
address_a_int
);
parameter HISTOGRAM_WIDTH = 16;
parameter HISTMEM_WORD = 1024;
localparam HISTMEM_ADDR_WIDTH = $clog2(HISTMEM_WORD);
input clk, reset_n;
input [15:0] data_in;
input [7:0] dir_max;
input data_valid_in;
//% \brief cell width (in pixel) minus 1
input [9:0] cellwidth;
//% \brief number of cells in a complete frame row minus 1
input [9:0] cellinrow;
//% \brief cell height (in pixel) minus 1
input [9:0] cellheight;
//% \brief number of data_valid_out pulse during store phase
//% storecycles could be computed as:
//% \f[ store\_cycles = \frac{RAM\_WIDTH}{2^{n\_bin\_exp}} \f]
//% where:
//% - n_bin_exp input parameter
//% - RAM_WIDTH number of memory location (now is fixed to 1024)
//%
input [15:0] storecycles;
//% \brief Activation signal
//% onoff = 1 means active
//% onoff = 0 means not active
input onoff;
//% \brief Operation mode configuration
//% - mode = 0 means \a Luminance histogram
//% - mode = 1 means \a Gradient histogram
input mode;
//% \brief Number of Bins
//% Accepted values are:
//% - n_bin_exp = 2
//% - n_bin_exp = 3
//% - n_bin_exp = 4 which means \f$ 2^4 \f$ bins
input [3:0] n_bin_exp;
//% \todo 32bit extension for luminance histogram
output [(HISTOGRAM_WIDTH-1):0] data_out;
//% asserted when valid data are sent to output
output data_valid_out;
output newcell_signal;
output newline_signal;
output loadcompleted;
output storecompleted;
output [15:0] count_store_int;
output [(HISTMEM_ADDR_WIDTH-1):0] address_a_int;
/*! @brief Memory address LSBs
* @detail These signals point the current memory location
* according to the mode configuration
* @{
*/
reg [7:0] address_lowbits, address_lowbits_new;
/*! @} */
reg [(HISTMEM_ADDR_WIDTH-1):0] address_a;
reg [(HISTOGRAM_WIDTH-1):0] data_a;
reg [(HISTOGRAM_WIDTH-1):0] data_a_d1;
reg data_valid_in_msk;
/*! @brief Internal registers
* @{
*/
reg [9:0] count_cellwidth;
reg [9:0] count_cellinrow;
reg [9:0] count_cellheight;
wire [15:0] count_store;
//! @}
//~ reg loadcompleted_d1;
/*! @brief Data valid signal to subcells
* @{
*/
reg data_valid_subcell_0, data_valid_subcell_1;
//! @}
reg [3:0] store_fsm, store_fsm_new;
/*! @brief count_store register extended by 1bit
* @details It is used during the store phase to perform a 2cycles
* store and clean operation
* @{
*/
reg [15+1:0] count_store_extended;
//! @}
//% \brief It acts as a subcell trigger
reg active_cell;
/*! @brief It represents the count_store_extended LSB.
* @{
*/
wire store_clean_state;
//! @}
//% Asserted during switch to another cell
wire newcell_signal;
//% Asserted when an image line has been scanned (and resets count_cellwidth)
wire newline_signal;
//% Asserted when the load phase is completed
wire loadcompleted;
//% Asserted when the store phase is completed
wire storecompleted;
wire [(HISTOGRAM_WIDTH-1):0] q_b_subcell_0, q_b_subcell_1;
wire clear_signal;
localparam START_STATE = 4'b0001;
localparam WAIT_MEM = 4'b0010;
localparam WORK_STATE = 4'b0100;
localparam END_STATE = 4'b1000;
// keep in mind!
// mode = 0 luminance
// mode = 1 hog
//%
//% address_lowbits_new
//%
always@(*)
case (mode)
1'b0: address_lowbits_new[7:0] = data_in[7:0];
1'b1: address_lowbits_new[7:0] = dir_max[7:0];
default:
address_lowbits_new[7:0] = data_in[7:0];
endcase
//%
//% address_lowbits
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
address_lowbits <= 8'b0;
else
address_lowbits <= address_lowbits_new;
//%
//% address_a
//%
always@(*)
case (n_bin_exp)
// 4 bins
4'd2: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-2:0], address_lowbits[1:0]};
// 8 bins
4'd3: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-3:0], address_lowbits[2:0]};
// 16 bins
4'd4: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-4:0], address_lowbits[3:0]};
// 256 bins
4'd8: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-8:0], address_lowbits[7:0]};
default:
//% 16 bins default
address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-4:0], address_lowbits[3:0]};
endcase
//%
//% data_valid_in_msk
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_valid_in_msk <= 1'b0;
else
data_valid_in_msk <= data_valid_in & onoff;
//%
//% data_a
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_a <= {HISTOGRAM_WIDTH{1'b0}};
else
data_a <= (mode == 1) ? data_in : 1;
//%
//% data_a_d1
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_a_d1 <= {HISTOGRAM_WIDTH{1'b0}};
else
data_a_d1 <= data_a;
//%
//% active_cell
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 1'b0)
active_cell = 1'b0;
else
if (data_valid_in_msk)
active_cell <= ~active_cell;
else
active_cell <= active_cell;
//%
//% data_valid_subcell_0
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_valid_subcell_0 <= 1'b0;
else
data_valid_subcell_0 <= data_valid_in_msk & ~active_cell;//~count_cellwidth[0];
//%
//% data_valid_subcell_1
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_valid_subcell_1 <= 1'b0;
else
data_valid_subcell_1 <= data_valid_in_msk & active_cell;//count_cellwidth[0];
//%
//% newcell_signal
//%
assign newcell_signal = (count_cellwidth == cellwidth)
&& data_valid_in_msk;
//%
//% count_cellwidth
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_cellwidth <= 10'b0;
else
if (onoff == 0)
count_cellwidth <= 10'b0;
else
if (newcell_signal)
count_cellwidth <= 10'b0;
else
if (data_valid_in_msk)
count_cellwidth <= count_cellwidth + 1;
else
count_cellwidth <= count_cellwidth;
//%
//% newline_signal
//%
assign newline_signal = (count_cellinrow == cellinrow)
&& (count_cellwidth == cellwidth)
&& data_valid_in_msk;
//%
//% count_cellinrow
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_cellinrow <= 10'b0;
else
if (onoff == 0)
count_cellinrow <= 10'b0;
else
if (newline_signal)
count_cellinrow <= 10'b0;
else
if (newcell_signal)
count_cellinrow <= count_cellinrow + 1;
else
count_cellinrow <= count_cellinrow;
//%
//% loadcompleted
//%
assign loadcompleted = (count_cellheight == cellheight)
&& (count_cellinrow == cellinrow)
&& (count_cellwidth == cellwidth)
&& data_valid_in_msk;
//%
//% count_cellheight
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_cellheight <= 10'd0;
else
if (onoff == 0)
count_cellheight <= 10'd0;
else
if (loadcompleted)
count_cellheight <= 10'd0;
else
if (newline_signal)
count_cellheight <= count_cellheight + 1;
else
count_cellheight <= count_cellheight;
//%
//% loadcompleted_d1
//% acts as a store phase delay (useful on a one cell histogram test)
//%
//~ always@(posedge clk or negedge reset_n)
//~ if (reset_n == 0)
//~ loadcompleted_d1 <= 0;
//~ else
//~ loadcompleted_d1 <= loadcompleted;
//%
//% store_fsm
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
store_fsm <= START_STATE;
else
store_fsm <= store_fsm_new;
//%
//% store_fsm_new
//%
always@(*)
case (store_fsm)
START_STATE:
if (onoff == 1'b0)
store_fsm_new = START_STATE;
else
if (loadcompleted)
store_fsm_new = WAIT_MEM;
else
store_fsm_new = START_STATE;
WAIT_MEM:
if (onoff == 1'b0)
store_fsm_new = START_STATE;
else
store_fsm_new = WORK_STATE;
WORK_STATE:
if (onoff == 1'b0)
store_fsm_new = START_STATE;
else
if (storecompleted)
store_fsm_new = END_STATE;
else
store_fsm_new = WORK_STATE;
END_STATE:
store_fsm_new = START_STATE;
endcase
//%
//% store_clean_state
//%
assign store_clean_state = count_store_extended[0];
/*
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
store_clean_state <= 1'b0;
else
if (onoff == 0)
store_clean_state <= 1'b0;
else
if ((store_fsm == WORK_STATE) || (store_fsm == WAIT_MEM))
store_clean_state <= ~store_clean_state;
else
store_clean_state <= store_clean_state;
*/
//%
//% storecompleted
//% asserted when the store_fsm has completed
assign storecompleted = (count_store == storecycles);
//%
//% count_store
//%
assign count_store = count_store_extended[16:1];
/*
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_store <= 16'd0;
else
if (onoff == 0)
count_store <= 16'b0;
else
if (storecompleted)
count_store <= 16'b0;
else
count_store <= count_store + store_clean_state;
*/
//%
//% count_store_extended
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_store_extended <= 17'd0;
else
if (onoff == 0)
count_store_extended <= 17'd0;
else
if (storecompleted)
count_store_extended <= 17'd0;
else
if ((store_fsm == WORK_STATE) || (store_fsm == WAIT_MEM))
count_store_extended <= count_store_extended + 1'b1;
else
count_store_extended <= count_store_extended;
//%
//% data_valid_out
//%
assign data_valid_out = ~store_clean_state && (store_fsm == WORK_STATE);
//%
//% data_out
//%
assign data_out = q_b_subcell_0 + q_b_subcell_1;
//%
//% clear_signal
//%
assign clear_signal = (store_clean_state == 1'b1);
assign count_store_int = count_store;
assign address_a_int = address_a;
ram_subcell
#( .HISTMEM_WORD(HISTMEM_WORD),
.HISTOGRAM_WIDTH(HISTOGRAM_WIDTH) )
ram_subcell_0 (
.clk(clk),
.reset_n(reset_n),
.data_a(data_a_d1),
.data_b({HISTOGRAM_WIDTH{1'b0}}),
.data_valid_in(data_valid_subcell_0),
.address_a_valid(~active_cell),
.memory_clear(clear_signal),
.enable_wire(onoff),
.q_b(q_b_subcell_0),
.q_a(),
.address_a(address_a),
.address_b(count_store[(HISTMEM_ADDR_WIDTH-1):0])
);
ram_subcell
#( .HISTMEM_WORD(HISTMEM_WORD),
.HISTOGRAM_WIDTH(HISTOGRAM_WIDTH) )
ram_subcell_1 (
.clk(clk),
.reset_n(reset_n),
.data_a(data_a_d1),
.data_b({HISTOGRAM_WIDTH{1'b0}}),
.data_valid_in(data_valid_subcell_1),
.address_a_valid(active_cell),
.memory_clear(clear_signal),
.enable_wire(onoff),
.q_b(q_b_subcell_1),
.q_a(),
.address_a(address_a),
.address_b(count_store[(HISTMEM_ADDR_WIDTH-1):0])
);
endmodule
|
//#############################################################################
//# Function: Rising Edge Sampled Register #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_reg1 #(parameter DW = 1 // data width
)
( input nreset, //async active low reset
input clk, // clk
input en, // write enable
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
reg [DW-1:0] out_reg;
always @ (posedge clk or negedge nreset)
if(!nreset)
out_reg[DW-1:0] <= 'b0;
else if(en)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
endmodule // ohr_reg1
|
`include "macro.v"
module ex_mem_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire ex_write_enable,
input wire[`REGS_ADDR_BUS] ex_write_addr,
input wire[`REGS_DATA_BUS] ex_write_data,
input wire ex_write_hilo_enable,
input wire[`REGS_DATA_BUS] ex_write_hi_data,
input wire[`REGS_DATA_BUS] ex_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_current_result,
input wire[`CYCLE_BUS] ex_current_cycle,
input wire[`ALU_OPERATOR_BUS] ex_alu_operator,
input wire[`REGS_DATA_BUS] ex_alu_operand2,
input wire[`REGS_DATA_BUS] ex_ram_addr,
output reg mem_write_enable,
output reg[`REGS_ADDR_BUS] mem_write_addr,
output reg[`REGS_DATA_BUS] mem_write_data,
output reg mem_write_hilo_enable,
output reg[`REGS_DATA_BUS] mem_write_hi_data,
output reg[`REGS_DATA_BUS] mem_write_lo_data,
output reg[`DOUBLE_REGS_DATA_BUS] mem_last_result,
output reg[`CYCLE_BUS] mem_last_cycle,
output reg[`ALU_OPERATOR_BUS] mem_alu_operator,
output reg[`REGS_DATA_BUS] mem_alu_operand2,
output reg[`REGS_DATA_BUS] mem_ram_addr
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but 0 is used
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_lo_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_last_result <= 0; // FIXME: {`ZERO_WORD, `ZEROWORD} should be used here, but 0 is used
mem_last_cycle <= 0; // FIXME: 2'b00 should be used here, but 0 is used
mem_alu_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but 0 is used
mem_alu_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_ram_addr <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end if (stall[3] == `ENABLE && stall[4] == `DISABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but 0 is used
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_lo_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
mem_alu_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but 0 is used
mem_alu_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_ram_addr <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end else if (stall[3] == `DISABLE) begin
mem_write_enable <= ex_write_enable;
mem_write_addr <= ex_write_addr;
mem_write_data <= ex_write_data;
mem_write_hilo_enable <= ex_write_hilo_enable;
mem_write_hi_data <= ex_write_hi_data;
mem_write_lo_data <= ex_write_lo_data;
mem_last_result <= 0; // FIXME: {`ZERO_WORD, `ZEROWORD} should be used here, but 0 is used
mem_last_cycle <= 0; // FIXME: 2'b00 should be used here, but 0 is used
mem_alu_operator <= ex_alu_operator;
mem_alu_operand2 <= ex_alu_operand2;
mem_ram_addr <= ex_ram_addr;
end else begin
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
end
end
endmodule // ex_mem_buffer
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_tx.v
//----------------------------------------------------------------------------//
// File: axi_basic_tx.v //
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tready (s_axis_tx_tready ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
.s_axis_tx_tkeep (s_axis_tx_tkeep ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td (trn_td ),
.trn_tsof (trn_tsof ),
.trn_teof (trn_teof ),
.trn_tsrc_rdy (trn_tsrc_rdy ),
.trn_tdst_rdy (trn_tdst_rdy ),
.trn_tsrc_dsc (trn_tsrc_dsc ),
.trn_trem (trn_trem ),
.trn_terrfwd (trn_terrfwd ),
.trn_tstr (trn_tstr ),
.trn_tecrc_gen (trn_tecrc_gen ),
.trn_lnk_up (trn_lnk_up ),
// System
//-----------
.tready_thrtl (tready_thrtl ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok (user_turnoff_ok ),
.user_tcfg_gnt (user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av (trn_tbuf_av ),
.trn_tdst_rdy (trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req (trn_tcfg_req ),
.trn_tcfg_gnt (trn_tcfg_gnt ),
.trn_lnk_up (trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate ),
.trn_rdllp_data (trn_rdllp_data ),
.trn_rdllp_src_rdy (trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_turnoff_ok (cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl (tready_thrtl ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
/**
* @module decoder
* @author sabertazimi
* @email [email protected]
* @brief decode intruction to rs/rt/rd, sham/imm16/imm26, op/functy
* @param DATA_WIDTH data width
* @input instruction input instruction code
* @output op op field in intruction code
* @output rs rs field in intruction code
* @output rt rt field in intruction code
* @output rd rd field in intruction code
* @output sham sham field in intruction code
* @output funct funct field in intruction code
* @output imm16 imm16 field in intruction code
* @output imm26 imm26 field in intruction code
*/
module decoder
(
input [31:0] instruction,
output [5:0] op,
output [4:0] rs,
output [4:0] rt,
output [4:0] rd,
output [4:0] sham,
output [5:0] funct,
output [15:0] imm16,
output [25:0] imm26
);
`include "defines.vh"
assign op = instruction[`OP];
assign rs = instruction[`RS];
assign rt = instruction[`RT];
assign rd = instruction[`RD];
assign sham = instruction[`SHAM];
assign funct = instruction[`FUNCT];
assign imm16 = instruction[`IMM16];
assign imm26 = instruction[`IMM26];
endmodule // decoder
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:13 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_sim_netlist.v
// Design : ip_design_zed_audio_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
data_rdy_bit_reg,
D,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
\s_axi_rdata_i_reg[31] ,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
S_AXI_ACLK,
Q,
S_AXI_ARVALID,
s_axi_bvalid_i_reg_0,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
S_AXI_WVALID_0,
\state_reg[1] ,
S_AXI_ARESETN,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
\DataTx_R_reg[31] ,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
S_AXI_RREADY,
s_axi_rvalid_i_reg_0,
S_AXI_BREADY,
s_axi_bvalid_i_reg_1);
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output data_rdy_bit_reg;
output [1:0]D;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]\s_axi_rdata_i_reg[31] ;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
input S_AXI_ACLK;
input [1:0]Q;
input S_AXI_ARVALID;
input s_axi_bvalid_i_reg_0;
input [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input S_AXI_WVALID_0;
input \state_reg[1] ;
input S_AXI_ARESETN;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]\DataTx_R_reg[31] ;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input S_AXI_RREADY;
input s_axi_rvalid_i_reg_0;
input S_AXI_BREADY;
input s_axi_bvalid_i_reg_1;
wire Bus_RNW_reg_i_1_n_0;
wire [1:0]D;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [31:0]\DataTx_R_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire [1:0]Q;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARREADY_INST_0_i_1_n_0;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_RREADY;
wire S_AXI_WVALID;
wire S_AXI_WVALID_0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire ce_expnd_i_4;
wire cs_ce_clr;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire s_axi_bvalid_i0;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire s_axi_bvalid_i_reg_1;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[10]_i_2_n_0 ;
wire \s_axi_rdata_i[11]_i_2_n_0 ;
wire \s_axi_rdata_i[12]_i_2_n_0 ;
wire \s_axi_rdata_i[13]_i_2_n_0 ;
wire \s_axi_rdata_i[14]_i_2_n_0 ;
wire \s_axi_rdata_i[15]_i_2_n_0 ;
wire \s_axi_rdata_i[16]_i_2_n_0 ;
wire \s_axi_rdata_i[17]_i_2_n_0 ;
wire \s_axi_rdata_i[18]_i_2_n_0 ;
wire \s_axi_rdata_i[19]_i_2_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[20]_i_2_n_0 ;
wire \s_axi_rdata_i[21]_i_2_n_0 ;
wire \s_axi_rdata_i[22]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_3_n_0 ;
wire \s_axi_rdata_i[23]_i_4_n_0 ;
wire \s_axi_rdata_i[2]_i_2_n_0 ;
wire \s_axi_rdata_i[3]_i_2_n_0 ;
wire \s_axi_rdata_i[4]_i_2_n_0 ;
wire \s_axi_rdata_i[5]_i_2_n_0 ;
wire \s_axi_rdata_i[6]_i_2_n_0 ;
wire \s_axi_rdata_i[7]_i_2_n_0 ;
wire \s_axi_rdata_i[8]_i_2_n_0 ;
wire \s_axi_rdata_i[9]_i_2_n_0 ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire s_axi_rvalid_i0;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire start;
wire \state_reg[1] ;
LUT6 #(
.INIT(64'hFEFFFFFF02020202))
Bus_RNW_reg_i_1
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.I5(\DataTx_R_reg[0]_4 ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\DataTx_R_reg[0]_4 ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_L[31]_i_1
(.I0(\DataTx_R_reg[0]_0 ),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(\DataTx_L_reg[0] ));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_R[31]_i_1
(.I0(\DataTx_R_reg[0]_1 ),
.I1(\DataTx_R_reg[0]_0 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(E));
LUT6 #(
.INIT(64'h020202020202FF02))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_4));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_4),
.Q(\DataTx_R_reg[0]_3 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_3),
.Q(\DataTx_R_reg[0]_2 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[1]),
.I2(S_AXI_ARADDR[0]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[1]),
.I5(S_AXI_AWADDR[0]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_2),
.Q(\DataTx_R_reg[0]_1 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFF80808080808080))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_1));
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_ARADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3
(.I0(S_AXI_ARVALID),
.I1(S_AXI_WVALID),
.I2(S_AXI_AWVALID),
.I3(Q[1]),
.I4(Q[0]),
.I5(S_AXI_AWADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_1),
.Q(\DataTx_R_reg[0]_0 ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(S_AXI_ARESETN),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I2(S_AXI_ARREADY_INST_0_i_1_n_0),
.O(cs_ce_clr));
LUT5 #(
.INIT(32'h03020202))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.O(start));
LUT5 #(
.INIT(32'hAAAAAEAA))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ),
.I2(S_AXI_AWADDR[1]),
.I3(S_AXI_AWADDR[2]),
.I4(S_AXI_AWADDR[0]),
.O(ce_expnd_i_0));
LUT6 #(
.INIT(64'h0000000000000400))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4
(.I0(S_AXI_ARADDR[0]),
.I1(S_AXI_ARADDR[2]),
.I2(S_AXI_ARADDR[1]),
.I3(S_AXI_ARVALID),
.I4(Q[0]),
.I5(Q[1]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ));
LUT5 #(
.INIT(32'h00001000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_AWVALID),
.I3(S_AXI_WVALID),
.I4(S_AXI_ARVALID),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_0),
.Q(\DataTx_R_reg[0] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF8))
S_AXI_ARREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_ARREADY));
LUT5 #(
.INIT(32'hFFFFFFFE))
S_AXI_ARREADY_INST_0_i_1
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0]_1 ),
.O(S_AXI_ARREADY_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF4))
S_AXI_AWREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFFFE))
data_rdy_bit_i_2
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
data_rdy_bit_i_3
(.I0(\DataTx_R_reg[0]_3 ),
.I1(\DataTx_R_reg[0]_2 ),
.I2(\DataTx_R_reg[0]_1 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0] ),
.I5(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg));
LUT3 #(
.INIT(8'hBA))
s_axi_bvalid_i_i_1
(.I0(s_axi_bvalid_i0),
.I1(S_AXI_BREADY),
.I2(s_axi_bvalid_i_reg_1),
.O(s_axi_bvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000AE00))
s_axi_bvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[1]),
.I4(Q[0]),
.O(s_axi_bvalid_i0));
LUT6 #(
.INIT(64'hFFAAEAAAEAAAEAAA))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[0]_i_2_n_0 ),
.I1(data_rdy_bit),
.I2(\DataTx_R_reg[0] ),
.I3(\s_axi_rdata_i[0]_i_3_n_0 ),
.I4(\DataTx_R_reg[0]_0 ),
.I5(\DataTx_R_reg[31] [0]),
.O(\s_axi_rdata_i_reg[31] [0]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rdata_i[0]_i_2
(.I0(\s_axi_rdata_i[0]_i_4_n_0 ),
.I1(\DataTx_L_reg[31] [0]),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [0]),
.I4(\DataRx_L_reg[23] [0]),
.I5(\s_axi_rdata_i[23]_i_2_n_0 ),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\s_axi_rdata_i[0]_i_3
(.I0(\DataTx_R_reg[0]_4 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[0]_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_1 ),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[10]_i_1
(.I0(\DataRx_L_reg[23] [10]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [10]),
.I4(\s_axi_rdata_i[10]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [10]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[10]_i_2
(.I0(\DataTx_L_reg[31] [10]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [10]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[11]_i_1
(.I0(\DataRx_L_reg[23] [11]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [11]),
.I4(\s_axi_rdata_i[11]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [11]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[11]_i_2
(.I0(\DataTx_L_reg[31] [11]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [11]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[12]_i_1
(.I0(\DataRx_L_reg[23] [12]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [12]),
.I4(\s_axi_rdata_i[12]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [12]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[12]_i_2
(.I0(\DataTx_L_reg[31] [12]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [12]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[13]_i_1
(.I0(\DataRx_L_reg[23] [13]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [13]),
.I4(\s_axi_rdata_i[13]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [13]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[13]_i_2
(.I0(\DataTx_L_reg[31] [13]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [13]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[14]_i_1
(.I0(\DataRx_L_reg[23] [14]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [14]),
.I4(\s_axi_rdata_i[14]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [14]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[14]_i_2
(.I0(\DataTx_L_reg[31] [14]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [14]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[15]_i_1
(.I0(\DataRx_L_reg[23] [15]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [15]),
.I4(\s_axi_rdata_i[15]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [15]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[15]_i_2
(.I0(\DataTx_L_reg[31] [15]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [15]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[16]_i_1
(.I0(\DataRx_L_reg[23] [16]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [16]),
.I4(\s_axi_rdata_i[16]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [16]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[16]_i_2
(.I0(\DataTx_L_reg[31] [16]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [16]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[17]_i_1
(.I0(\DataRx_L_reg[23] [17]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [17]),
.I4(\s_axi_rdata_i[17]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [17]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[17]_i_2
(.I0(\DataTx_L_reg[31] [17]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [17]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[17]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[18]_i_1
(.I0(\DataRx_L_reg[23] [18]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [18]),
.I4(\s_axi_rdata_i[18]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [18]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[18]_i_2
(.I0(\DataTx_L_reg[31] [18]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [18]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[18]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[19]_i_1
(.I0(\DataRx_L_reg[23] [19]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [19]),
.I4(\s_axi_rdata_i[19]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [19]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[19]_i_2
(.I0(\DataTx_L_reg[31] [19]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [19]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[1]_i_1
(.I0(\DataRx_L_reg[23] [1]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [1]),
.I4(\s_axi_rdata_i[1]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [1]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[1]_i_2
(.I0(\DataTx_L_reg[31] [1]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[20]_i_1
(.I0(\DataRx_L_reg[23] [20]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [20]),
.I4(\s_axi_rdata_i[20]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [20]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[20]_i_2
(.I0(\DataTx_L_reg[31] [20]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [20]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[20]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[21]_i_1
(.I0(\DataRx_L_reg[23] [21]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [21]),
.I4(\s_axi_rdata_i[21]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [21]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[21]_i_2
(.I0(\DataTx_L_reg[31] [21]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [21]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[21]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[22]_i_1
(.I0(\DataRx_L_reg[23] [22]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [22]),
.I4(\s_axi_rdata_i[22]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [22]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[22]_i_2
(.I0(\DataTx_L_reg[31] [22]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [22]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[22]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[23]_i_1
(.I0(\DataRx_L_reg[23] [23]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [23]),
.I4(\s_axi_rdata_i[23]_i_4_n_0 ),
.O(\s_axi_rdata_i_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_3 ),
.O(\s_axi_rdata_i[23]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_2 ),
.O(\s_axi_rdata_i[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[23]_i_4
(.I0(\DataTx_L_reg[31] [23]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [23]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[24]_i_1
(.I0(\DataTx_L_reg[31] [24]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [24]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [24]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[25]_i_1
(.I0(\DataTx_L_reg[31] [25]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [25]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [25]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[26]_i_1
(.I0(\DataTx_L_reg[31] [26]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [26]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [26]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[27]_i_1
(.I0(\DataTx_L_reg[31] [27]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [27]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [27]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[28]_i_1
(.I0(\DataTx_L_reg[31] [28]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [28]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [28]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[29]_i_1
(.I0(\DataTx_L_reg[31] [29]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [29]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[2]_i_1
(.I0(\DataRx_L_reg[23] [2]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [2]),
.I4(\s_axi_rdata_i[2]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [2]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[2]_i_2
(.I0(\DataTx_L_reg[31] [2]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [2]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[30]_i_1
(.I0(\DataTx_L_reg[31] [30]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [30]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [30]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[31]_i_2
(.I0(\DataTx_L_reg[31] [31]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [31]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [31]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[3]_i_1
(.I0(\DataRx_L_reg[23] [3]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [3]),
.I4(\s_axi_rdata_i[3]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [3]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[3]_i_2
(.I0(\DataTx_L_reg[31] [3]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [3]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[4]_i_1
(.I0(\DataRx_L_reg[23] [4]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [4]),
.I4(\s_axi_rdata_i[4]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [4]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[4]_i_2
(.I0(\DataTx_L_reg[31] [4]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [4]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[5]_i_1
(.I0(\DataRx_L_reg[23] [5]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [5]),
.I4(\s_axi_rdata_i[5]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [5]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[5]_i_2
(.I0(\DataTx_L_reg[31] [5]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [5]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[6]_i_1
(.I0(\DataRx_L_reg[23] [6]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [6]),
.I4(\s_axi_rdata_i[6]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [6]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[6]_i_2
(.I0(\DataTx_L_reg[31] [6]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [6]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[7]_i_1
(.I0(\DataRx_L_reg[23] [7]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [7]),
.I4(\s_axi_rdata_i[7]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [7]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[7]_i_2
(.I0(\DataTx_L_reg[31] [7]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [7]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[8]_i_1
(.I0(\DataRx_L_reg[23] [8]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [8]),
.I4(\s_axi_rdata_i[8]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [8]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[8]_i_2
(.I0(\DataTx_L_reg[31] [8]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [8]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[9]_i_1
(.I0(\DataRx_L_reg[23] [9]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [9]),
.I4(\s_axi_rdata_i[9]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [9]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[9]_i_2
(.I0(\DataTx_L_reg[31] [9]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [9]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[9]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBA))
s_axi_rvalid_i_i_1
(.I0(s_axi_rvalid_i0),
.I1(S_AXI_RREADY),
.I2(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000EA00))
s_axi_rvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[0]),
.I4(Q[1]),
.O(s_axi_rvalid_i0));
LUT4 #(
.INIT(16'hFFF4))
\state[0]_i_1
(.I0(Q[1]),
.I1(S_AXI_ARVALID),
.I2(s_axi_bvalid_i0),
.I3(s_axi_bvalid_i_reg_0),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF4454))
\state[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_WVALID_0),
.I3(S_AXI_ARVALID),
.I4(\state_reg[1] ),
.I5(s_axi_rvalid_i0),
.O(D[1]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output Bus_RNW_reg;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Bus_RNW_reg;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\DataTx_R_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\DataTx_R_reg[0]_1 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\DataTx_R_reg[0]_2 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\DataTx_R_reg[0]_3 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\DataTx_R_reg[0]_4 (Bus_RNW_reg),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SR(SR),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl
(out,
S_AXI_RDATA,
S_AXI_AWREADY,
S_AXI_ARREADY,
S_AXI_BVALID,
S_AXI_RVALID,
SDATA_O,
S_AXI_ACLK,
SDATA_I,
S_AXI_WDATA,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID);
output [1:0]out;
output [31:0]S_AXI_RDATA;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output S_AXI_BVALID;
output S_AXI_RVALID;
output SDATA_O;
input S_AXI_ACLK;
input SDATA_I;
input [31:0]S_AXI_WDATA;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_8;
wire [23:0]DataRx_L;
wire [23:0]DataRx_R;
wire [31:0]DataTx_L;
wire [31:0]DataTx_R;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire SDATA_I;
wire SDATA_O;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
wire USER_LOGIC_I_n_0;
wire USER_LOGIC_I_n_69;
wire data_rdy_bit;
wire [1:0]out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\DataRx_L_reg[23] (DataRx_L),
.\DataRx_R_reg[23] (DataRx_R),
.\DataTx_L_reg[0] (AXI_LITE_IPIF_I_n_12),
.\DataTx_L_reg[31] (DataTx_L),
.E(AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (USER_LOGIC_I_n_0),
.Q(DataTx_R),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(AXI_LITE_IPIF_I_n_8),
.data_rdy_bit_reg_0(AXI_LITE_IPIF_I_n_13));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic USER_LOGIC_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI_LITE_IPIF_I_n_8),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (AXI_LITE_IPIF_I_n_13),
.Q(out),
.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_WDATA(S_AXI_WDATA),
.data_rdy_bit(data_rdy_bit),
.\s_axi_rdata_i_reg[23] (DataRx_L),
.\s_axi_rdata_i_reg[23]_0 (DataRx_R),
.\s_axi_rdata_i_reg[24] (USER_LOGIC_I_n_0),
.\s_axi_rdata_i_reg[31] (DataTx_L),
.\s_axi_rdata_i_reg[31]_0 (DataTx_R));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser
(lrclk_d1,
sclk_d1,
E,
\rdata_reg_reg[23]_0 ,
\bit_cntr_reg[4]_0 ,
sdata_reg_reg,
\FSM_onehot_iis_state_reg[0] ,
data_rdy_bit_reg,
\FSM_onehot_iis_state_reg[0]_0 ,
\DataRx_L_reg[23] ,
\DataRx_R_reg[23] ,
Q,
S_AXI_ACLK,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
out,
data_rdy_bit,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
S_AXI_ARESETN,
SDATA_I);
output lrclk_d1;
output sclk_d1;
output [0:0]E;
output [0:0]\rdata_reg_reg[23]_0 ;
output [0:0]\bit_cntr_reg[4]_0 ;
output sdata_reg_reg;
output \FSM_onehot_iis_state_reg[0] ;
output data_rdy_bit_reg;
output \FSM_onehot_iis_state_reg[0]_0 ;
output [23:0]\DataRx_L_reg[23] ;
output [23:0]\DataRx_R_reg[23] ;
input [1:0]Q;
input S_AXI_ACLK;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input [2:0]out;
input data_rdy_bit;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input S_AXI_ARESETN;
input SDATA_I;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state_reg[0] ;
wire \FSM_onehot_iis_state_reg[0]_0 ;
wire \FSM_sequential_iis_state[0]_i_1_n_0 ;
wire \FSM_sequential_iis_state[1]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_2_n_0 ;
wire \FSM_sequential_iis_state[2]_i_3_n_0 ;
wire \FSM_sequential_iis_state[2]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [1:0]Q;
wire SDATA_I;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire \bit_cntr[4]_i_1_n_0 ;
wire [0:0]\bit_cntr_reg[4]_0 ;
wire [4:0]bit_cntr_reg__0;
wire bit_rdy;
wire data_rdy_bit;
wire data_rdy_bit_i_4_n_0;
wire data_rdy_bit_reg;
wire eqOp;
(* RTL_KEEP = "yes" *) wire [2:0]iis_state;
wire ldata_reg;
wire ldata_reg0;
wire lrclk_d1;
wire [2:0]out;
wire [4:0]plusOp__1;
wire rdata_reg0;
wire [0:0]\rdata_reg_reg[23]_0 ;
wire sclk_d1;
wire sdata_reg_reg;
LUT4 #(
.INIT(16'h0080))
\DataRx_L[23]_i_1
(.I0(eqOp),
.I1(iis_state[2]),
.I2(iis_state[1]),
.I3(iis_state[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000020))
\DataRx_L[23]_i_2
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[2]),
.O(eqOp));
LUT3 #(
.INIT(8'h40))
\FSM_onehot_iis_state[4]_i_3
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[1]),
.O(\FSM_onehot_iis_state_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hDF))
\FSM_onehot_iis_state[4]_i_5
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[0]),
.O(\FSM_onehot_iis_state_reg[0] ));
LUT6 #(
.INIT(64'h75777F7745444044))
\FSM_sequential_iis_state[0]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[0]),
.O(\FSM_sequential_iis_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3A7B3F7B0A480048))
\FSM_sequential_iis_state[1]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[1]),
.O(\FSM_sequential_iis_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FB33FB30F800080))
\FSM_sequential_iis_state[2]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[2]),
.O(\FSM_sequential_iis_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFA33FF000A330F))
\FSM_sequential_iis_state[2]_i_2
(.I0(bit_rdy),
.I1(\FSM_sequential_iis_state[2]_i_4_n_0 ),
.I2(iis_state[2]),
.I3(iis_state[0]),
.I4(iis_state[1]),
.I5(eqOp),
.O(\FSM_sequential_iis_state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h22A222A2EEAE22A2))
\FSM_sequential_iis_state[2]_i_3
(.I0(bit_rdy),
.I1(iis_state[2]),
.I2(iis_state[0]),
.I3(iis_state[1]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\FSM_sequential_iis_state[2]_i_4
(.I0(Q[1]),
.I1(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_4_n_0 ));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[0]_i_1_n_0 ),
.Q(iis_state[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[1]_i_1_n_0 ),
.Q(iis_state[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[2]_i_1_n_0 ),
.Q(iis_state[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__1[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h6CCC))
\bit_cntr[3]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[3]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.O(plusOp__1[3]));
LUT3 #(
.INIT(8'hD7))
\bit_cntr[4]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(\bit_cntr[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(bit_rdy));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2__0
(.I0(sclk_d1),
.I1(Q[0]),
.O(\bit_cntr_reg[4]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h78F0F0F0))
\bit_cntr[4]_i_3
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[2]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[0]),
.O(plusOp__1[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCC00EA0000000000))
data_rdy_bit_i_1
(.I0(data_rdy_bit),
.I1(E),
.I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I4(data_rdy_bit_i_4_n_0),
.I5(S_AXI_ARESETN),
.O(data_rdy_bit_reg));
LUT6 #(
.INIT(64'h0000000090000000))
data_rdy_bit_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I2(eqOp),
.I3(iis_state[2]),
.I4(iis_state[1]),
.I5(iis_state[0]),
.O(data_rdy_bit_i_4_n_0));
LUT3 #(
.INIT(8'h01))
\ldata_reg[23]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(ldata_reg));
LUT5 #(
.INIT(32'h00004000))
\ldata_reg[23]_i_2
(.I0(iis_state[2]),
.I1(iis_state[0]),
.I2(iis_state[1]),
.I3(Q[0]),
.I4(sclk_d1),
.O(ldata_reg0));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(SDATA_I),
.Q(\DataRx_L_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [9]),
.Q(\DataRx_L_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [10]),
.Q(\DataRx_L_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [11]),
.Q(\DataRx_L_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [12]),
.Q(\DataRx_L_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [13]),
.Q(\DataRx_L_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [14]),
.Q(\DataRx_L_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [15]),
.Q(\DataRx_L_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [16]),
.Q(\DataRx_L_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [17]),
.Q(\DataRx_L_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [18]),
.Q(\DataRx_L_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [0]),
.Q(\DataRx_L_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [19]),
.Q(\DataRx_L_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [20]),
.Q(\DataRx_L_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [21]),
.Q(\DataRx_L_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [22]),
.Q(\DataRx_L_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [1]),
.Q(\DataRx_L_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [2]),
.Q(\DataRx_L_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [3]),
.Q(\DataRx_L_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [4]),
.Q(\DataRx_L_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [5]),
.Q(\DataRx_L_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [6]),
.Q(\DataRx_L_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [7]),
.Q(\DataRx_L_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [8]),
.Q(\DataRx_L_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
lrclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[1]),
.Q(lrclk_d1),
.R(1'b0));
LUT5 #(
.INIT(32'h00004000))
\rdata_reg[23]_i_1
(.I0(iis_state[0]),
.I1(iis_state[1]),
.I2(iis_state[2]),
.I3(Q[0]),
.I4(sclk_d1),
.O(rdata_reg0));
LUT6 #(
.INIT(64'h4040FF4040404040))
\rdata_reg[23]_i_1__0
(.I0(Q[0]),
.I1(sclk_d1),
.I2(out[2]),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\rdata_reg_reg[23]_0 ));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(SDATA_I),
.Q(\DataRx_R_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [9]),
.Q(\DataRx_R_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [10]),
.Q(\DataRx_R_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [11]),
.Q(\DataRx_R_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [12]),
.Q(\DataRx_R_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [13]),
.Q(\DataRx_R_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [14]),
.Q(\DataRx_R_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [15]),
.Q(\DataRx_R_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [16]),
.Q(\DataRx_R_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [17]),
.Q(\DataRx_R_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [18]),
.Q(\DataRx_R_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [0]),
.Q(\DataRx_R_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [19]),
.Q(\DataRx_R_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [20]),
.Q(\DataRx_R_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [21]),
.Q(\DataRx_R_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [22]),
.Q(\DataRx_R_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [1]),
.Q(\DataRx_R_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [2]),
.Q(\DataRx_R_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [3]),
.Q(\DataRx_R_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [4]),
.Q(\DataRx_R_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [5]),
.Q(\DataRx_R_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [6]),
.Q(\DataRx_R_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [7]),
.Q(\DataRx_R_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [8]),
.Q(\DataRx_R_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
sclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[0]),
.Q(sclk_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
sdata_reg_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(sdata_reg_reg));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser
(SDATA_O,
out,
S_AXI_ACLK,
Q,
sclk_d1,
lrclk_d1,
\DataTx_L_reg[23] ,
\DataTx_R_reg[23] ,
\clk_cntr_reg[4] ,
lrclk_d1_reg,
lrclk_d1_reg_0,
E,
sclk_d1_reg);
output SDATA_O;
output [2:0]out;
input S_AXI_ACLK;
input [1:0]Q;
input sclk_d1;
input lrclk_d1;
input [23:0]\DataTx_L_reg[23] ;
input [23:0]\DataTx_R_reg[23] ;
input \clk_cntr_reg[4] ;
input lrclk_d1_reg;
input lrclk_d1_reg_0;
input [0:0]E;
input [0:0]sclk_d1_reg;
wire [23:0]\DataTx_L_reg[23] ;
wire [23:0]\DataTx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state[1]_i_1_n_0 ;
wire \FSM_onehot_iis_state[2]_i_1_n_0 ;
wire \FSM_onehot_iis_state[3]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_2_n_0 ;
wire [1:0]Q;
wire SDATA_O;
wire S_AXI_ACLK;
wire \bit_cntr[4]_i_1__0_n_0 ;
wire [4:0]bit_cntr_reg__0;
wire \clk_cntr_reg[4] ;
wire eqOp;
(* RTL_KEEP = "yes" *) wire ldata_reg;
wire \ldata_reg[0]_i_1_n_0 ;
wire \ldata_reg[10]_i_1_n_0 ;
wire \ldata_reg[11]_i_1_n_0 ;
wire \ldata_reg[12]_i_1_n_0 ;
wire \ldata_reg[13]_i_1_n_0 ;
wire \ldata_reg[14]_i_1_n_0 ;
wire \ldata_reg[15]_i_1_n_0 ;
wire \ldata_reg[16]_i_1_n_0 ;
wire \ldata_reg[17]_i_1_n_0 ;
wire \ldata_reg[18]_i_1_n_0 ;
wire \ldata_reg[19]_i_1_n_0 ;
wire \ldata_reg[1]_i_1_n_0 ;
wire \ldata_reg[20]_i_1_n_0 ;
wire \ldata_reg[21]_i_1_n_0 ;
wire \ldata_reg[22]_i_1_n_0 ;
wire \ldata_reg[23]_i_1__0_n_0 ;
wire \ldata_reg[23]_i_2__0_n_0 ;
wire \ldata_reg[2]_i_1_n_0 ;
wire \ldata_reg[3]_i_1_n_0 ;
wire \ldata_reg[4]_i_1_n_0 ;
wire \ldata_reg[5]_i_1_n_0 ;
wire \ldata_reg[6]_i_1_n_0 ;
wire \ldata_reg[7]_i_1_n_0 ;
wire \ldata_reg[8]_i_1_n_0 ;
wire \ldata_reg[9]_i_1_n_0 ;
wire \ldata_reg_reg_n_0_[0] ;
wire \ldata_reg_reg_n_0_[10] ;
wire \ldata_reg_reg_n_0_[11] ;
wire \ldata_reg_reg_n_0_[12] ;
wire \ldata_reg_reg_n_0_[13] ;
wire \ldata_reg_reg_n_0_[14] ;
wire \ldata_reg_reg_n_0_[15] ;
wire \ldata_reg_reg_n_0_[16] ;
wire \ldata_reg_reg_n_0_[17] ;
wire \ldata_reg_reg_n_0_[18] ;
wire \ldata_reg_reg_n_0_[19] ;
wire \ldata_reg_reg_n_0_[1] ;
wire \ldata_reg_reg_n_0_[20] ;
wire \ldata_reg_reg_n_0_[21] ;
wire \ldata_reg_reg_n_0_[22] ;
wire \ldata_reg_reg_n_0_[2] ;
wire \ldata_reg_reg_n_0_[3] ;
wire \ldata_reg_reg_n_0_[4] ;
wire \ldata_reg_reg_n_0_[5] ;
wire \ldata_reg_reg_n_0_[6] ;
wire \ldata_reg_reg_n_0_[7] ;
wire \ldata_reg_reg_n_0_[8] ;
wire \ldata_reg_reg_n_0_[9] ;
wire lrclk_d1;
wire lrclk_d1_reg;
wire lrclk_d1_reg_0;
(* RTL_KEEP = "yes" *) wire [2:0]out;
(* RTL_KEEP = "yes" *) wire p_0_in2_in;
wire [23:0]p_1_in;
wire p_2_in;
wire [4:0]plusOp__2;
wire \rdata_reg_reg_n_0_[0] ;
wire \rdata_reg_reg_n_0_[10] ;
wire \rdata_reg_reg_n_0_[11] ;
wire \rdata_reg_reg_n_0_[12] ;
wire \rdata_reg_reg_n_0_[13] ;
wire \rdata_reg_reg_n_0_[14] ;
wire \rdata_reg_reg_n_0_[15] ;
wire \rdata_reg_reg_n_0_[16] ;
wire \rdata_reg_reg_n_0_[17] ;
wire \rdata_reg_reg_n_0_[18] ;
wire \rdata_reg_reg_n_0_[19] ;
wire \rdata_reg_reg_n_0_[1] ;
wire \rdata_reg_reg_n_0_[20] ;
wire \rdata_reg_reg_n_0_[21] ;
wire \rdata_reg_reg_n_0_[22] ;
wire \rdata_reg_reg_n_0_[23] ;
wire \rdata_reg_reg_n_0_[2] ;
wire \rdata_reg_reg_n_0_[3] ;
wire \rdata_reg_reg_n_0_[4] ;
wire \rdata_reg_reg_n_0_[5] ;
wire \rdata_reg_reg_n_0_[6] ;
wire \rdata_reg_reg_n_0_[7] ;
wire \rdata_reg_reg_n_0_[8] ;
wire \rdata_reg_reg_n_0_[9] ;
wire sclk_d1;
wire [0:0]sclk_d1_reg;
wire sdata_reg_i_1_n_0;
LUT5 #(
.INIT(32'hAAAAAABA))
\FSM_onehot_iis_state[1]_i_1
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[2]),
.I3(out[1]),
.I4(out[0]),
.O(\FSM_onehot_iis_state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0ACA))
\FSM_onehot_iis_state[2]_i_1
(.I0(p_0_in2_in),
.I1(out[0]),
.I2(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.I3(ldata_reg),
.O(\FSM_onehot_iis_state[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\FSM_onehot_iis_state[3]_i_1
(.I0(p_0_in2_in),
.I1(ldata_reg),
.I2(out[0]),
.O(\FSM_onehot_iis_state[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEEFFFFFEEEFFFF))
\FSM_onehot_iis_state[4]_i_1
(.I0(ldata_reg),
.I1(lrclk_d1_reg),
.I2(out[2]),
.I3(eqOp),
.I4(lrclk_d1_reg_0),
.I5(p_0_in2_in),
.O(\FSM_onehot_iis_state[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0010))
\FSM_onehot_iis_state[4]_i_2
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[1]),
.I3(out[0]),
.O(\FSM_onehot_iis_state[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h02000000))
\FSM_onehot_iis_state[4]_i_4
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[2]),
.I3(bit_cntr_reg__0[4]),
.I4(bit_cntr_reg__0[3]),
.O(eqOp));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(1'b0),
.Q(ldata_reg),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[1]_i_1_n_0 ),
.Q(out[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_onehot_iis_state[2]_i_1_n_0 ),
.Q(p_0_in2_in),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[3]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[3]_i_1_n_0 ),
.Q(out[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[4]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[4]_i_2_n_0 ),
.Q(out[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__2[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1__0
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\bit_cntr[3]_i_1__0
(.I0(bit_cntr_reg__0[2]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[1]),
.I3(bit_cntr_reg__0[3]),
.O(plusOp__2[3]));
LUT2 #(
.INIT(4'h1))
\bit_cntr[4]_i_1__0
(.I0(out[2]),
.I1(p_0_in2_in),
.O(\bit_cntr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bit_cntr[4]_i_3__0
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.I4(bit_cntr_reg__0[4]),
.O(plusOp__2[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h0800))
\ldata_reg[0]_i_1
(.I0(\DataTx_L_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(\ldata_reg[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[10]_i_1
(.I0(\ldata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [10]),
.O(\ldata_reg[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[11]_i_1
(.I0(\ldata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [11]),
.O(\ldata_reg[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[12]_i_1
(.I0(\ldata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [12]),
.O(\ldata_reg[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[13]_i_1
(.I0(\ldata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [13]),
.O(\ldata_reg[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[14]_i_1
(.I0(\ldata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [14]),
.O(\ldata_reg[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[15]_i_1
(.I0(\ldata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [15]),
.O(\ldata_reg[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[16]_i_1
(.I0(\ldata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [16]),
.O(\ldata_reg[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[17]_i_1
(.I0(\ldata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [17]),
.O(\ldata_reg[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[18]_i_1
(.I0(\ldata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [18]),
.O(\ldata_reg[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[19]_i_1
(.I0(\ldata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [19]),
.O(\ldata_reg[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[1]_i_1
(.I0(\ldata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [1]),
.O(\ldata_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[20]_i_1
(.I0(\ldata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [20]),
.O(\ldata_reg[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[21]_i_1
(.I0(\ldata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [21]),
.O(\ldata_reg[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[22]_i_1
(.I0(\ldata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [22]),
.O(\ldata_reg[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\ldata_reg[23]_i_1__0
(.I0(p_0_in2_in),
.I1(Q[0]),
.I2(sclk_d1),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\ldata_reg[23]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[23]_i_2__0
(.I0(\ldata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [23]),
.O(\ldata_reg[23]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[2]_i_1
(.I0(\ldata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [2]),
.O(\ldata_reg[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[3]_i_1
(.I0(\ldata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [3]),
.O(\ldata_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[4]_i_1
(.I0(\ldata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [4]),
.O(\ldata_reg[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[5]_i_1
(.I0(\ldata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [5]),
.O(\ldata_reg[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[6]_i_1
(.I0(\ldata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [6]),
.O(\ldata_reg[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[7]_i_1
(.I0(\ldata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [7]),
.O(\ldata_reg[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[8]_i_1
(.I0(\ldata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [8]),
.O(\ldata_reg[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[9]_i_1
(.I0(\ldata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [9]),
.O(\ldata_reg[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[0]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[10]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[11]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[12]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[13]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[14]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[15]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[16]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[17]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[18]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[19]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[1]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[20]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[21]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[22]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[23]_i_2__0_n_0 ),
.Q(p_2_in),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[2]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[3]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[4]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[5]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[6]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[7]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[8]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[9]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT4 #(
.INIT(16'h0800))
\rdata_reg[0]_i_1
(.I0(\DataTx_R_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(p_1_in[0]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[10]_i_1
(.I0(\rdata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [10]),
.O(p_1_in[10]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[11]_i_1
(.I0(\rdata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [11]),
.O(p_1_in[11]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[12]_i_1
(.I0(\rdata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [12]),
.O(p_1_in[12]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[13]_i_1
(.I0(\rdata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [13]),
.O(p_1_in[13]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[14]_i_1
(.I0(\rdata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [14]),
.O(p_1_in[14]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[15]_i_1
(.I0(\rdata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [15]),
.O(p_1_in[15]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[16]_i_1
(.I0(\rdata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [16]),
.O(p_1_in[16]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[17]_i_1
(.I0(\rdata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [17]),
.O(p_1_in[17]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[18]_i_1
(.I0(\rdata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [18]),
.O(p_1_in[18]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[19]_i_1
(.I0(\rdata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [19]),
.O(p_1_in[19]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[1]_i_1
(.I0(\rdata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [1]),
.O(p_1_in[1]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[20]_i_1
(.I0(\rdata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [20]),
.O(p_1_in[20]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[21]_i_1
(.I0(\rdata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [21]),
.O(p_1_in[21]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[22]_i_1
(.I0(\rdata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [22]),
.O(p_1_in[22]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[23]_i_2
(.I0(\rdata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [23]),
.O(p_1_in[23]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[2]_i_1
(.I0(\rdata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [2]),
.O(p_1_in[2]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[3]_i_1
(.I0(\rdata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [3]),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[4]_i_1
(.I0(\rdata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [4]),
.O(p_1_in[4]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[5]_i_1
(.I0(\rdata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [5]),
.O(p_1_in[5]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[6]_i_1
(.I0(\rdata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [6]),
.O(p_1_in[6]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[7]_i_1
(.I0(\rdata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [7]),
.O(p_1_in[7]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[8]_i_1
(.I0(\rdata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [8]),
.O(p_1_in[8]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[9]_i_1
(.I0(\rdata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [9]),
.O(p_1_in[9]));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[0]),
.Q(\rdata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[10]),
.Q(\rdata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[11]),
.Q(\rdata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[12]),
.Q(\rdata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[13]),
.Q(\rdata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[14]),
.Q(\rdata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[15]),
.Q(\rdata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[16]),
.Q(\rdata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[17]),
.Q(\rdata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[18]),
.Q(\rdata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[19]),
.Q(\rdata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[1]),
.Q(\rdata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[20]),
.Q(\rdata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[21]),
.Q(\rdata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[22]),
.Q(\rdata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[23]),
.Q(\rdata_reg_reg_n_0_[23] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[2]),
.Q(\rdata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[3]),
.Q(\rdata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[4]),
.Q(\rdata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[5]),
.Q(\rdata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[6]),
.Q(\rdata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[7]),
.Q(\rdata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[8]),
.Q(\rdata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[9]),
.Q(\rdata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT6 #(
.INIT(64'hFFFFCCAF0000CCA0))
sdata_reg_i_1
(.I0(\rdata_reg_reg_n_0_[23] ),
.I1(p_2_in),
.I2(out[2]),
.I3(p_0_in2_in),
.I4(\clk_cntr_reg[4] ),
.I5(SDATA_O),
.O(sdata_reg_i_1_n_0));
FDRE #(
.INIT(1'b0))
sdata_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(sdata_reg_i_1_n_0),
.Q(SDATA_O),
.R(ldata_reg));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "i2s_ctrl,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(BCLK,
LRCLK,
SDATA_I,
SDATA_O,
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_RREADY,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_AWREADY);
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
(* max_fanout = "10000" *) (* sigis = "Clk" *) (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input S_AXI_ACLK;
(* max_fanout = "10000" *) (* sigis = "Rst" *) (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW" *) input S_AXI_ARESETN;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]S_AXI_AWADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input S_AXI_AWVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]S_AXI_WDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]S_AXI_WSTRB;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input S_AXI_WVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input S_AXI_BREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]S_AXI_ARADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input S_AXI_ARVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input S_AXI_RREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output S_AXI_ARREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]S_AXI_RDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]S_AXI_RRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output S_AXI_RVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output S_AXI_WREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]S_AXI_BRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output S_AXI_BVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output S_AXI_AWREADY;
wire \<const0> ;
wire BCLK;
wire LRCLK;
wire SDATA_I;
wire SDATA_O;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire S_AXI_ACLK;
wire [31:0]S_AXI_ARADDR;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [31:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
assign S_AXI_BRESP[1] = \<const0> ;
assign S_AXI_BRESP[0] = \<const0> ;
assign S_AXI_RRESP[1] = \<const0> ;
assign S_AXI_RRESP[0] = \<const0> ;
assign S_AXI_WREADY = S_AXI_AWREADY;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl U0
(.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR[4:2]),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR[4:2]),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WVALID(S_AXI_WVALID),
.out({LRCLK,BCLK}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ;
wire [31:0]IP2Bus_Data;
wire I_DECODER_n_46;
wire I_DECODER_n_47;
wire I_DECODER_n_7;
wire I_DECODER_n_8;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire p_2_out;
wire [3:0]plusOp;
wire rst;
wire s_axi_rdata_i;
wire [1:0]state;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
wire timeout;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(p_2_out));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I3(timeout),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[3]),
.Q(timeout),
.R(p_2_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D({I_DECODER_n_7,I_DECODER_n_8}),
.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\DataTx_R_reg[0] ),
.\DataTx_R_reg[0]_0 (\DataTx_R_reg[0]_0 ),
.\DataTx_R_reg[0]_1 (\DataTx_R_reg[0]_1 ),
.\DataTx_R_reg[0]_2 (\DataTx_R_reg[0]_2 ),
.\DataTx_R_reg[0]_3 (\DataTx_R_reg[0]_3 ),
.\DataTx_R_reg[0]_4 (\DataTx_R_reg[0]_4 ),
.\DataTx_R_reg[31] (Q),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (timeout),
.Q(state),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WVALID_0(\state[1]_i_2_n_0 ),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0),
.s_axi_bvalid_i_reg(I_DECODER_n_47),
.s_axi_bvalid_i_reg_0(\state[0]_i_2_n_0 ),
.s_axi_bvalid_i_reg_1(S_AXI_BVALID),
.\s_axi_rdata_i_reg[31] (IP2Bus_Data),
.s_axi_rvalid_i_reg(I_DECODER_n_46),
.s_axi_rvalid_i_reg_0(S_AXI_RVALID),
.\state_reg[1] (\state[1]_i_3_n_0 ));
FDRE rst_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(SR),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_47),
.Q(S_AXI_BVALID),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(S_AXI_RDATA[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[10]),
.Q(S_AXI_RDATA[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[11]),
.Q(S_AXI_RDATA[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[12]),
.Q(S_AXI_RDATA[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[13]),
.Q(S_AXI_RDATA[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[14]),
.Q(S_AXI_RDATA[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[15]),
.Q(S_AXI_RDATA[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[16]),
.Q(S_AXI_RDATA[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[17]),
.Q(S_AXI_RDATA[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[18]),
.Q(S_AXI_RDATA[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[19]),
.Q(S_AXI_RDATA[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(S_AXI_RDATA[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[20]),
.Q(S_AXI_RDATA[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[21]),
.Q(S_AXI_RDATA[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[22]),
.Q(S_AXI_RDATA[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[23]),
.Q(S_AXI_RDATA[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[24]),
.Q(S_AXI_RDATA[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[25]),
.Q(S_AXI_RDATA[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[26]),
.Q(S_AXI_RDATA[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[27]),
.Q(S_AXI_RDATA[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[28]),
.Q(S_AXI_RDATA[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[29]),
.Q(S_AXI_RDATA[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[2]),
.Q(S_AXI_RDATA[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[30]),
.Q(S_AXI_RDATA[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(S_AXI_RDATA[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[3]),
.Q(S_AXI_RDATA[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[4]),
.Q(S_AXI_RDATA[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[5]),
.Q(S_AXI_RDATA[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[6]),
.Q(S_AXI_RDATA[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[7]),
.Q(S_AXI_RDATA[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[8]),
.Q(S_AXI_RDATA[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[9]),
.Q(S_AXI_RDATA[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_46),
.Q(S_AXI_RVALID),
.R(rst));
LUT6 #(
.INIT(64'h07770000FFFF0000))
\state[0]_i_2
(.I0(S_AXI_BVALID),
.I1(S_AXI_BREADY),
.I2(S_AXI_RREADY),
.I3(S_AXI_RVALID),
.I4(state[0]),
.I5(state[1]),
.O(\state[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_2
(.I0(S_AXI_AWVALID),
.I1(S_AXI_WVALID),
.O(\state[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h002A2A2A))
\state[1]_i_3
(.I0(state[1]),
.I1(S_AXI_RVALID),
.I2(S_AXI_RREADY),
.I3(S_AXI_BREADY),
.I4(S_AXI_BVALID),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_8),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_7),
.Q(state[1]),
.R(rst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic
(\s_axi_rdata_i_reg[24] ,
Q,
data_rdy_bit,
SDATA_O,
\s_axi_rdata_i_reg[31] ,
\s_axi_rdata_i_reg[31]_0 ,
SR,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[23]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
S_AXI_ACLK,
S_AXI_ARESETN,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
SDATA_I,
E,
S_AXI_WDATA,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] );
output \s_axi_rdata_i_reg[24] ;
output [1:0]Q;
output data_rdy_bit;
output SDATA_O;
output [31:0]\s_axi_rdata_i_reg[31] ;
output [31:0]\s_axi_rdata_i_reg[31]_0 ;
output [0:0]SR;
output [23:0]\s_axi_rdata_i_reg[23] ;
output [23:0]\s_axi_rdata_i_reg[23]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input SDATA_I;
input [0:0]E;
input [31:0]S_AXI_WDATA;
input [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire Bus_RNW_reg;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Inst_iis_deser_n_3;
wire Inst_iis_deser_n_33;
wire Inst_iis_deser_n_34;
wire Inst_iis_deser_n_35;
wire Inst_iis_deser_n_36;
wire Inst_iis_deser_n_37;
wire Inst_iis_deser_n_38;
wire Inst_iis_deser_n_39;
wire Inst_iis_deser_n_40;
wire Inst_iis_deser_n_41;
wire Inst_iis_deser_n_42;
wire Inst_iis_deser_n_43;
wire Inst_iis_deser_n_44;
wire Inst_iis_deser_n_45;
wire Inst_iis_deser_n_46;
wire Inst_iis_deser_n_47;
wire Inst_iis_deser_n_48;
wire Inst_iis_deser_n_49;
wire Inst_iis_deser_n_5;
wire Inst_iis_deser_n_50;
wire Inst_iis_deser_n_51;
wire Inst_iis_deser_n_52;
wire Inst_iis_deser_n_53;
wire Inst_iis_deser_n_54;
wire Inst_iis_deser_n_55;
wire Inst_iis_deser_n_56;
wire Inst_iis_deser_n_6;
wire Inst_iis_deser_n_7;
wire Inst_iis_deser_n_8;
wire Inst_iis_ser_n_1;
wire Inst_iis_ser_n_2;
wire [1:0]Q;
wire SDATA_I;
wire SDATA_O;
wire [0:0]SR;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire [31:0]S_AXI_WDATA;
wire \clk_cntr[10]_i_2_n_0 ;
wire \clk_cntr_reg_n_0_[0] ;
wire \clk_cntr_reg_n_0_[1] ;
wire \clk_cntr_reg_n_0_[2] ;
wire \clk_cntr_reg_n_0_[3] ;
wire \clk_cntr_reg_n_0_[5] ;
wire \clk_cntr_reg_n_0_[6] ;
wire \clk_cntr_reg_n_0_[7] ;
wire \clk_cntr_reg_n_0_[8] ;
wire \clk_cntr_reg_n_0_[9] ;
wire data_rdy;
wire data_rdy_bit;
wire [23:0]ldata_reg;
wire lrclk_d1;
wire p_0_in4_in;
wire [10:0]plusOp__0;
wire [23:0]\s_axi_rdata_i_reg[23] ;
wire [23:0]\s_axi_rdata_i_reg[23]_0 ;
wire \s_axi_rdata_i_reg[24] ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire [31:0]\s_axi_rdata_i_reg[31]_0 ;
wire sclk_d1;
wire write_bit;
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[0]),
.Q(\s_axi_rdata_i_reg[23] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[10]),
.Q(\s_axi_rdata_i_reg[23] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[11]),
.Q(\s_axi_rdata_i_reg[23] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[12]),
.Q(\s_axi_rdata_i_reg[23] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[13]),
.Q(\s_axi_rdata_i_reg[23] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[14]),
.Q(\s_axi_rdata_i_reg[23] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[15]),
.Q(\s_axi_rdata_i_reg[23] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[16]),
.Q(\s_axi_rdata_i_reg[23] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[17]),
.Q(\s_axi_rdata_i_reg[23] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[18]),
.Q(\s_axi_rdata_i_reg[23] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[19]),
.Q(\s_axi_rdata_i_reg[23] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[1]),
.Q(\s_axi_rdata_i_reg[23] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[20]),
.Q(\s_axi_rdata_i_reg[23] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[21]),
.Q(\s_axi_rdata_i_reg[23] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[22]),
.Q(\s_axi_rdata_i_reg[23] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[23]),
.Q(\s_axi_rdata_i_reg[23] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[2]),
.Q(\s_axi_rdata_i_reg[23] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[3]),
.Q(\s_axi_rdata_i_reg[23] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[4]),
.Q(\s_axi_rdata_i_reg[23] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[5]),
.Q(\s_axi_rdata_i_reg[23] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[6]),
.Q(\s_axi_rdata_i_reg[23] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[7]),
.Q(\s_axi_rdata_i_reg[23] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[8]),
.Q(\s_axi_rdata_i_reg[23] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[9]),
.Q(\s_axi_rdata_i_reg[23] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_56),
.Q(\s_axi_rdata_i_reg[23]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_46),
.Q(\s_axi_rdata_i_reg[23]_0 [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_45),
.Q(\s_axi_rdata_i_reg[23]_0 [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_44),
.Q(\s_axi_rdata_i_reg[23]_0 [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_43),
.Q(\s_axi_rdata_i_reg[23]_0 [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_42),
.Q(\s_axi_rdata_i_reg[23]_0 [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_41),
.Q(\s_axi_rdata_i_reg[23]_0 [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_40),
.Q(\s_axi_rdata_i_reg[23]_0 [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_39),
.Q(\s_axi_rdata_i_reg[23]_0 [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_38),
.Q(\s_axi_rdata_i_reg[23]_0 [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_37),
.Q(\s_axi_rdata_i_reg[23]_0 [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_55),
.Q(\s_axi_rdata_i_reg[23]_0 [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_36),
.Q(\s_axi_rdata_i_reg[23]_0 [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_35),
.Q(\s_axi_rdata_i_reg[23]_0 [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_34),
.Q(\s_axi_rdata_i_reg[23]_0 [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_33),
.Q(\s_axi_rdata_i_reg[23]_0 [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_54),
.Q(\s_axi_rdata_i_reg[23]_0 [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_53),
.Q(\s_axi_rdata_i_reg[23]_0 [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_52),
.Q(\s_axi_rdata_i_reg[23]_0 [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_51),
.Q(\s_axi_rdata_i_reg[23]_0 [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_50),
.Q(\s_axi_rdata_i_reg[23]_0 [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_49),
.Q(\s_axi_rdata_i_reg[23]_0 [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_48),
.Q(\s_axi_rdata_i_reg[23]_0 [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_47),
.Q(\s_axi_rdata_i_reg[23]_0 [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31] [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31] [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31] [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31] [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31] [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31] [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31] [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31] [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[24]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31] [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[25]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31] [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[26]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31] [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[27]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31] [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[28]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31] [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[29]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31] [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[30]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31] [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[31]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31] [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31] [9]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31]_0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31]_0 [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31]_0 [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31]_0 [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31]_0 [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31]_0 [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31]_0 [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31]_0 [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31]_0 [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31]_0 [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31]_0 [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31]_0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31]_0 [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31]_0 [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31]_0 [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31]_0 [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[24]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31]_0 [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[25]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31]_0 [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[26]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31]_0 [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[27]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31]_0 [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[28]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31]_0 [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[29]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31]_0 [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31]_0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[30]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31]_0 [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[31]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31]_0 [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31]_0 [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31]_0 [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31]_0 [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31]_0 [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31]_0 [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31]_0 [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31]_0 [9]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser Inst_iis_deser
(.\DataRx_L_reg[23] (ldata_reg),
.\DataRx_R_reg[23] ({Inst_iis_deser_n_33,Inst_iis_deser_n_34,Inst_iis_deser_n_35,Inst_iis_deser_n_36,Inst_iis_deser_n_37,Inst_iis_deser_n_38,Inst_iis_deser_n_39,Inst_iis_deser_n_40,Inst_iis_deser_n_41,Inst_iis_deser_n_42,Inst_iis_deser_n_43,Inst_iis_deser_n_44,Inst_iis_deser_n_45,Inst_iis_deser_n_46,Inst_iis_deser_n_47,Inst_iis_deser_n_48,Inst_iis_deser_n_49,Inst_iis_deser_n_50,Inst_iis_deser_n_51,Inst_iis_deser_n_52,Inst_iis_deser_n_53,Inst_iis_deser_n_54,Inst_iis_deser_n_55,Inst_iis_deser_n_56}),
.E(data_rdy),
.\FSM_onehot_iis_state_reg[0] (Inst_iis_deser_n_6),
.\FSM_onehot_iis_state_reg[0]_0 (Inst_iis_deser_n_8),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SDATA_I(SDATA_I),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.\bit_cntr_reg[4]_0 (write_bit),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(Inst_iis_deser_n_7),
.lrclk_d1(lrclk_d1),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.\rdata_reg_reg[23]_0 (Inst_iis_deser_n_3),
.sclk_d1(sclk_d1),
.sdata_reg_reg(Inst_iis_deser_n_5));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser Inst_iis_ser
(.\DataTx_L_reg[23] (\s_axi_rdata_i_reg[31] [23:0]),
.\DataTx_R_reg[23] (\s_axi_rdata_i_reg[31]_0 [23:0]),
.E(Inst_iis_deser_n_3),
.Q(Q),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.\clk_cntr_reg[4] (Inst_iis_deser_n_5),
.lrclk_d1(lrclk_d1),
.lrclk_d1_reg(Inst_iis_deser_n_8),
.lrclk_d1_reg_0(Inst_iis_deser_n_6),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.sclk_d1(sclk_d1),
.sclk_d1_reg(write_bit));
LUT1 #(
.INIT(2'h1))
\clk_cntr[0]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.O(plusOp__0[0]));
LUT6 #(
.INIT(64'hF7FFFFFF08000000))
\clk_cntr[10]_i_1
(.I0(\clk_cntr_reg_n_0_[9] ),
.I1(\clk_cntr_reg_n_0_[7] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[6] ),
.I4(\clk_cntr_reg_n_0_[8] ),
.I5(Q[1]),
.O(plusOp__0[10]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\clk_cntr[10]_i_2
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(\clk_cntr[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\clk_cntr[1]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\clk_cntr[2]_i_1
(.I0(\clk_cntr_reg_n_0_[1] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[2] ),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h7F80))
\clk_cntr[3]_i_1
(.I0(\clk_cntr_reg_n_0_[2] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[1] ),
.I3(\clk_cntr_reg_n_0_[3] ),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h7FFF8000))
\clk_cntr[4]_i_1
(.I0(\clk_cntr_reg_n_0_[3] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[2] ),
.I4(Q[0]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\clk_cntr[5]_i_1
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\clk_cntr[6]_i_1
(.I0(\clk_cntr[10]_i_2_n_0 ),
.I1(\clk_cntr_reg_n_0_[6] ),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hD2))
\clk_cntr[7]_i_1
(.I0(\clk_cntr_reg_n_0_[6] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[7] ),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hDF20))
\clk_cntr[8]_i_1
(.I0(\clk_cntr_reg_n_0_[7] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[6] ),
.I3(\clk_cntr_reg_n_0_[8] ),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hF7FF0800))
\clk_cntr[9]_i_1
(.I0(\clk_cntr_reg_n_0_[8] ),
.I1(\clk_cntr_reg_n_0_[6] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[7] ),
.I4(\clk_cntr_reg_n_0_[9] ),
.O(plusOp__0[9]));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[0]),
.Q(\clk_cntr_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[10]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[10]),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[1]),
.Q(\clk_cntr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[2]),
.Q(\clk_cntr_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[3]),
.Q(\clk_cntr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[4]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[5]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[5]),
.Q(\clk_cntr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[6]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[6]),
.Q(\clk_cntr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[7]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[7]),
.Q(\clk_cntr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[8]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[8]),
.Q(\clk_cntr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[9]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[9]),
.Q(\clk_cntr_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
data_rdy_bit_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Inst_iis_deser_n_7),
.Q(data_rdy_bit),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(S_AXI_ARESETN),
.O(SR));
LUT6 #(
.INIT(64'h0000000400040448))
slv_ip2bus_data
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I5(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(\s_axi_rdata_i_reg[24] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module tag_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(tag_width_lp)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter block_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)+`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input ready_o
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input v_o
, input yumi_i
, input [data_width_p-1:0] data_o
, input [id_width_p-1:0] id_o
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
`declare_bsg_cache_non_blocking_tag_info_s(tag_width_lp);
bsg_cache_non_blocking_tag_info_s [ways_p-1:0][sets_p-1:0] shadow_tag;
logic [data_width_p-1:0] result [*]; // indexed by id.
wire [lg_ways_lp-1:0] addr_way = cache_pkt.addr[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
wire [lg_sets_lp-1:0] addr_index = cache_pkt.addr[block_offset_width_lp+:lg_sets_lp];
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < ways_p; i++)
for (integer j = 0; j < ways_p; j++)
shadow_tag[i][j] <= '0;
end
else begin
if (v_i & ready_o & en_i) begin
case (cache_pkt.opcode)
TAGST: begin
result[cache_pkt.id] = '0;
shadow_tag[addr_way][addr_index].tag <= cache_pkt.data[0+:tag_width_lp];
shadow_tag[addr_way][addr_index].valid <= cache_pkt.data[data_width_p-1];
shadow_tag[addr_way][addr_index].lock <= cache_pkt.data[data_width_p-2];
end
TAGLV: begin
result[cache_pkt.id] = '0;
result[cache_pkt.id][1] = shadow_tag[addr_way][addr_index].lock;
result[cache_pkt.id][0] = shadow_tag[addr_way][addr_index].valid;
end
TAGLA: begin
result[cache_pkt.id] = {
shadow_tag[addr_way][addr_index].tag,
addr_index,
{block_offset_width_lp{1'b0}}
};
end
endcase
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
assert(result[id_o] == data_o)
else $fatal("[BSG_FATAL] Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o], data_o);
end
end
endmodule
`BSG_ABSTRACT_MODULE(tag_checker)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostControl.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbHostControl(
busClk, rstSyncToBusClk,
usbClk, rstSyncToUsbClk,
//sendPacket
TxFifoRE, TxFifoData, TxFifoEmpty,
//getPacket
RxFifoWE, RxFifoData, RxFifoFull,
RxByteStatus, RxData, RxDataValid,
SIERxTimeOut, SIERxTimeOutEn,
//speedCtrlMux
fullSpeedRate, fullSpeedPol,
//HCTxPortArbiter
HCTxPortEn, HCTxPortRdy,
HCTxPortData, HCTxPortCtrl,
//rxStatusMonitor
connectStateIn,
resumeDetectedIn,
//USBHostControlBI
busAddress,
busDataIn,
busDataOut,
busWriteEn,
busStrobe_i,
SOFSentIntOut,
connEventIntOut,
resumeIntOut,
transDoneIntOut,
hostControlSelect
);
input busClk;
input rstSyncToBusClk;
input usbClk;
input rstSyncToUsbClk;
//sendPacket
output TxFifoRE;
input [7:0] TxFifoData;
input TxFifoEmpty;
//getPacket
output RxFifoWE;
output [7:0] RxFifoData;
input RxFifoFull;
input [7:0] RxByteStatus;
input [7:0] RxData;
input RxDataValid;
input SIERxTimeOut;
output SIERxTimeOutEn;
//speedCtrlMux
output fullSpeedRate;
output fullSpeedPol;
//HCTxPortArbiter
output HCTxPortEn;
input HCTxPortRdy;
output [7:0] HCTxPortData;
output [7:0] HCTxPortCtrl;
//rxStatusMonitor
input [1:0] connectStateIn;
input resumeDetectedIn;
//USBHostControlBI
input [3:0] busAddress;
input [7:0] busDataIn;
output [7:0] busDataOut;
input busWriteEn;
input busStrobe_i;
output SOFSentIntOut;
output connEventIntOut;
output resumeIntOut;
output transDoneIntOut;
input hostControlSelect;
wire busClk;
wire rstSyncToBusClk;
wire usbClk;
wire rstSyncToUsbClk;
wire [10:0] frameNum;
wire SOFSent;
wire TxFifoRE;
wire [7:0] TxFifoData;
wire TxFifoEmpty;
wire RxFifoWE;
wire [7:0] RxFifoData;
wire RxFifoFull;
wire [7:0] RxByteStatus;
wire [7:0] RxData;
wire RxDataValid;
wire SIERxTimeOut;
wire SIERxTimeOutEn;
wire fullSpeedRate;
wire fullSpeedPol;
wire HCTxPortEn;
wire HCTxPortRdy;
wire [7:0] HCTxPortData;
wire [7:0] HCTxPortCtrl;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
wire [3:0] busAddress;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire busWriteEn;
wire busStrobe_i;
wire SOFSentIntOut;
wire connEventIntOut;
wire resumeIntOut;
wire transDoneIntOut;
wire hostControlSelect;
//internal wiring
wire SOFTimerClr;
wire getPacketREn;
wire getPacketRdy;
wire HCTxGnt;
wire HCTxReq;
wire [3:0] HC_PID;
wire HC_SP_WEn;
wire SOFTxGnt;
wire SOFTxReq;
wire SOF_SP_WEn;
wire SOFEnable;
wire SOFSyncEn;
wire sendPacketCPReadyIn;
wire sendPacketCPReadyOut;
wire [3:0] sendPacketCPPIDIn;
wire [3:0] sendPacketCPPIDOut;
wire sendPacketCPWEnIn;
wire sendPacketCPWEnOut;
wire [7:0] SOFCntlCntl;
wire [7:0] SOFCntlData;
wire SOFCntlGnt;
wire SOFCntlReq;
wire SOFCntlWEn;
wire [7:0] directCntlCntl;
wire [7:0] directCntlData;
wire directCntlGnt;
wire directCntlReq;
wire directCntlWEn;
wire [7:0] sendPacketCntl;
wire [7:0] sendPacketData;
wire sendPacketGnt;
wire sendPacketReq;
wire sendPacketWEn;
wire [15:0] SOFTimer;
wire clrTxReq;
wire transDone;
wire transReq;
wire isoEn;
wire [1:0] transType;
wire preAmbleEnable;
wire [1:0] directLineState;
wire directLineCtrlEn;
wire [6:0] TxAddr;
wire [3:0] TxEndP;
wire [7:0] RxPktStatus;
wire [3:0] RxPID;
wire [1:0] connectStateOut;
wire resumeIntFromRxStatusMon;
wire connectionEventFromRxStatusMon;
USBHostControlBI u_USBHostControlBI
(.address(busAddress),
.dataIn(busDataIn),
.dataOut(busDataOut),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.SOFSentIntOut(SOFSentIntOut),
.connEventIntOut(connEventIntOut),
.resumeIntOut(resumeIntOut),
.transDoneIntOut(transDoneIntOut),
.TxTransTypeReg(transType),
.TxSOFEnableReg(SOFEnable),
.TxAddrReg(TxAddr),
.TxEndPReg(TxEndP),
.frameNumIn(frameNum),
.RxPktStatusIn(RxPktStatus),
.RxPIDIn(RxPID),
.connectStateIn(connectStateOut),
.SOFSentIn(SOFSent),
.connEventIn(connectionEventFromRxStatusMon),
.resumeIntIn(resumeIntFromRxStatusMon),
.transDoneIn(transDone),
.hostControlSelect(hostControlSelect),
.clrTransReq(clrTxReq),
.preambleEn(preAmbleEnable),
.SOFSync(SOFSyncEn),
.TxLineState(directLineState),
.LineDirectControlEn(directLineCtrlEn),
.fullSpeedPol(fullSpeedPol),
.fullSpeedRate(fullSpeedRate),
.transReq(transReq),
.isoEn(isoEn),
.SOFTimer(SOFTimer)
);
hostcontroller u_hostController
(.RXStatus(RxPktStatus),
.clearTXReq(clrTxReq),
.clk(usbClk),
.getPacketREn(getPacketREn),
.getPacketRdy(getPacketRdy),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(HCTxGnt),
.sendPacketArbiterReq(HCTxReq),
.sendPacketPID(HC_PID),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(HC_SP_WEn),
.transDone(transDone),
.transReq(transReq),
.transType(transType),
.isoEn(isoEn) );
SOFController u_SOFController
(.HCTxPortCntl(SOFCntlCntl),
.HCTxPortData(SOFCntlData),
.HCTxPortGnt(SOFCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(SOFCntlReq),
.HCTxPortWEn(SOFCntlWEn),
.SOFEnable(SOFEnable),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
SOFTransmit u_SOFTransmit
(.SOFEnable(SOFEnable),
.SOFSent(SOFSent),
.SOFSyncEn(SOFSyncEn),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(SOFTxGnt),
.sendPacketArbiterReq(SOFTxReq),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(SOF_SP_WEn),
.fullSpeedRate(fullSpeedRate) );
sendPacketArbiter u_sendPacketArbiter
(.HCTxGnt(HCTxGnt),
.HCTxReq(HCTxReq),
.HC_PID(HC_PID),
.HC_SP_WEn(HC_SP_WEn),
.SOFTxGnt(SOFTxGnt),
.SOFTxReq(SOFTxReq),
.SOF_SP_WEn(SOF_SP_WEn),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketPID(sendPacketCPPIDIn),
.sendPacketWEnable(sendPacketCPWEnIn) );
sendPacketCheckPreamble u_sendPacketCheckPreamble
(.sendPacketCPPID(sendPacketCPPIDIn),
.clk(usbClk),
.preAmbleEnable(preAmbleEnable),
.rst(rstSyncToUsbClk),
.sendPacketCPReady(sendPacketCPReadyOut),
.sendPacketCPWEn(sendPacketCPWEnIn),
.sendPacketPID(sendPacketCPPIDOut),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut) );
sendPacket u_sendPacket
(.HCTxPortCntl(sendPacketCntl),
.HCTxPortData(sendPacketData),
.HCTxPortGnt(sendPacketGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(sendPacketReq),
.HCTxPortWEn(sendPacketWEn),
.PID(sendPacketCPPIDOut),
.TxAddr(TxAddr),
.TxEndP(TxEndP),
.clk(usbClk),
.fifoData(TxFifoData),
.fifoEmpty(TxFifoEmpty),
.fifoReadEn(TxFifoRE),
.frameNum(frameNum),
.rst(rstSyncToUsbClk),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut),
.fullSpeedPolarity(fullSpeedPol) );
directControl u_directControl
(.HCTxPortCntl(directCntlCntl),
.HCTxPortData(directCntlData),
.HCTxPortGnt(directCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(directCntlReq),
.HCTxPortWEn(directCntlWEn),
.clk(usbClk),
.directControlEn(directLineCtrlEn),
.directControlLineState(directLineState),
.rst(rstSyncToUsbClk) );
HCTxPortArbiter u_HCTxPortArbiter
(.HCTxPortCntl(HCTxPortCtrl),
.HCTxPortData(HCTxPortData),
.HCTxPortWEnable(HCTxPortEn),
.SOFCntlCntl(SOFCntlCntl),
.SOFCntlData(SOFCntlData),
.SOFCntlGnt(SOFCntlGnt),
.SOFCntlReq(SOFCntlReq),
.SOFCntlWEn(SOFCntlWEn),
.clk(usbClk),
.directCntlCntl(directCntlCntl),
.directCntlData(directCntlData),
.directCntlGnt(directCntlGnt),
.directCntlReq(directCntlReq),
.directCntlWEn(directCntlWEn),
.rst(rstSyncToUsbClk),
.sendPacketCntl(sendPacketCntl),
.sendPacketData(sendPacketData),
.sendPacketGnt(sendPacketGnt),
.sendPacketReq(sendPacketReq),
.sendPacketWEn(sendPacketWEn) );
getPacket u_getPacket
(.RXDataIn(RxData),
.RXDataValid(RxDataValid),
.RXFifoData(RxFifoData),
.RXFifoFull(RxFifoFull),
.RXFifoWEn(RxFifoWE),
.RXPacketRdy(getPacketRdy),
.RXPktStatus(RxPktStatus),
.RXStreamStatusIn(RxByteStatus),
.RxPID(RxPID),
.SIERxTimeOut(SIERxTimeOut),
.SIERxTimeOutEn(SIERxTimeOutEn),
.clk(usbClk),
.getPacketEn(getPacketREn),
.rst(rstSyncToUsbClk) );
rxStatusMonitor u_rxStatusMonitor
(.connectStateIn(connectStateIn),
.connectStateOut(connectStateOut),
.resumeDetectedIn(resumeDetectedIn),
.connectionEventOut(connectionEventFromRxStatusMon),
.resumeIntOut(resumeIntFromRxStatusMon),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_1_V
`define SKY130_FD_SC_MS__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_1_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecc_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecc_e.v,v 1.1 2004/04/06 10:50:52 wig Exp $
// $Date: 2004/04/06 10:50:52 $
// $Log: inst_ecc_e.v,v $
// Revision 1.1 2004/04/06 10:50:52 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ecc_e
//
// No `defines in this module
module inst_ecc_e
//
// Generated module inst_ecc
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// vim: ts=4 sw=4 noexpandtab
/*
* Synchronize a signal to a clock
*
* Copyright (c) 2019 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`ifndef SYNC_SIGNAL_MOD_V_
`define SYNC_SIGNAL_MOD_V_
module sync_signal(
input clk, /* clock */
input in, /* input signal */
output out, /* synchronized output signal */
output falling, /* synchronized falling edge output */
output rising, /* synchronized rising edge output */
);
reg [2:0] shiftreg;
initial begin
shiftreg <= 0;
end
always @(posedge clk) begin
shiftreg[2:1] <= shiftreg[1:0];
shiftreg[0] <= in;
end
assign out = shiftreg[1];
assign falling = shiftreg[2] & ~shiftreg[1];
assign rising = ~shiftreg[2] & shiftreg[1];
endmodule
`endif /* SYNC_SIGNAL_MOD_V_ */
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_0_b_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_0_b_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// system_acl_iface_acl_kernel_clk.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_clk (
output wire kernel_clk2x_clk, // kernel_clk2x.clk
input wire pll_refclk_clk, // pll_refclk.clk
output wire ctrl_waitrequest, // ctrl.waitrequest
output wire [31:0] ctrl_readdata, // .readdata
output wire ctrl_readdatavalid, // .readdatavalid
input wire [0:0] ctrl_burstcount, // .burstcount
input wire [31:0] ctrl_writedata, // .writedata
input wire [10:0] ctrl_address, // .address
input wire ctrl_write, // .write
input wire ctrl_read, // .read
input wire [3:0] ctrl_byteenable, // .byteenable
input wire ctrl_debugaccess, // .debugaccess
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_pll_locked_export, // kernel_pll_locked.export
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
wire [63:0] pll_reconfig_0_reconfig_to_pll_reconfig_to_pll; // pll_reconfig_0:reconfig_to_pll -> kernel_pll:reconfig_to_pll
wire [63:0] kernel_pll_reconfig_from_pll_reconfig_from_pll; // kernel_pll:reconfig_from_pll -> pll_reconfig_0:reconfig_from_pll
wire kernel_pll_outclk0_clk; // kernel_pll:outclk_0 -> global_routing_kernel_clk:s
wire kernel_pll_outclk1_clk; // kernel_pll:outclk_1 -> [counter:clk2x, global_routing_kernel_clk2x:s]
wire kernel_pll_locked_export_signal; // kernel_pll:locked -> pll_lock_avs_0:lock
wire ctrl_m0_waitrequest; // mm_interconnect_0:ctrl_m0_waitrequest -> ctrl:m0_waitrequest
wire [31:0] ctrl_m0_readdata; // mm_interconnect_0:ctrl_m0_readdata -> ctrl:m0_readdata
wire ctrl_m0_debugaccess; // ctrl:m0_debugaccess -> mm_interconnect_0:ctrl_m0_debugaccess
wire [10:0] ctrl_m0_address; // ctrl:m0_address -> mm_interconnect_0:ctrl_m0_address
wire ctrl_m0_read; // ctrl:m0_read -> mm_interconnect_0:ctrl_m0_read
wire [3:0] ctrl_m0_byteenable; // ctrl:m0_byteenable -> mm_interconnect_0:ctrl_m0_byteenable
wire ctrl_m0_readdatavalid; // mm_interconnect_0:ctrl_m0_readdatavalid -> ctrl:m0_readdatavalid
wire [31:0] ctrl_m0_writedata; // ctrl:m0_writedata -> mm_interconnect_0:ctrl_m0_writedata
wire ctrl_m0_write; // ctrl:m0_write -> mm_interconnect_0:ctrl_m0_write
wire [0:0] ctrl_m0_burstcount; // ctrl:m0_burstcount -> mm_interconnect_0:ctrl_m0_burstcount
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata; // pll_reconfig_0:mgmt_readdata -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_readdata
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest; // pll_reconfig_0:mgmt_waitrequest -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_waitrequest
wire [5:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_address -> pll_reconfig_0:mgmt_address
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_read -> pll_reconfig_0:mgmt_read
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_write -> pll_reconfig_0:mgmt_write
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_writedata -> pll_reconfig_0:mgmt_writedata
wire mm_interconnect_0_pll_rom_s1_chipselect; // mm_interconnect_0:pll_rom_s1_chipselect -> pll_rom:chipselect
wire [31:0] mm_interconnect_0_pll_rom_s1_readdata; // pll_rom:readdata -> mm_interconnect_0:pll_rom_s1_readdata
wire mm_interconnect_0_pll_rom_s1_debugaccess; // mm_interconnect_0:pll_rom_s1_debugaccess -> pll_rom:debugaccess
wire [7:0] mm_interconnect_0_pll_rom_s1_address; // mm_interconnect_0:pll_rom_s1_address -> pll_rom:address
wire [3:0] mm_interconnect_0_pll_rom_s1_byteenable; // mm_interconnect_0:pll_rom_s1_byteenable -> pll_rom:byteenable
wire mm_interconnect_0_pll_rom_s1_write; // mm_interconnect_0:pll_rom_s1_write -> pll_rom:write
wire [31:0] mm_interconnect_0_pll_rom_s1_writedata; // mm_interconnect_0:pll_rom_s1_writedata -> pll_rom:writedata
wire mm_interconnect_0_pll_rom_s1_clken; // mm_interconnect_0:pll_rom_s1_clken -> pll_rom:clken
wire [31:0] mm_interconnect_0_counter_s_readdata; // counter:slave_readdata -> mm_interconnect_0:counter_s_readdata
wire mm_interconnect_0_counter_s_waitrequest; // counter:slave_waitrequest -> mm_interconnect_0:counter_s_waitrequest
wire [1:0] mm_interconnect_0_counter_s_address; // mm_interconnect_0:counter_s_address -> counter:slave_address
wire mm_interconnect_0_counter_s_read; // mm_interconnect_0:counter_s_read -> counter:slave_read
wire [3:0] mm_interconnect_0_counter_s_byteenable; // mm_interconnect_0:counter_s_byteenable -> counter:slave_byteenable
wire mm_interconnect_0_counter_s_readdatavalid; // counter:slave_readdatavalid -> mm_interconnect_0:counter_s_readdatavalid
wire mm_interconnect_0_counter_s_write; // mm_interconnect_0:counter_s_write -> counter:slave_write
wire [31:0] mm_interconnect_0_counter_s_writedata; // mm_interconnect_0:counter_s_writedata -> counter:slave_writedata
wire [31:0] mm_interconnect_0_pll_sw_reset_s_readdata; // pll_sw_reset:slave_readdata -> mm_interconnect_0:pll_sw_reset_s_readdata
wire mm_interconnect_0_pll_sw_reset_s_waitrequest; // pll_sw_reset:slave_waitrequest -> mm_interconnect_0:pll_sw_reset_s_waitrequest
wire mm_interconnect_0_pll_sw_reset_s_read; // mm_interconnect_0:pll_sw_reset_s_read -> pll_sw_reset:slave_read
wire [3:0] mm_interconnect_0_pll_sw_reset_s_byteenable; // mm_interconnect_0:pll_sw_reset_s_byteenable -> pll_sw_reset:slave_byteenable
wire mm_interconnect_0_pll_sw_reset_s_write; // mm_interconnect_0:pll_sw_reset_s_write -> pll_sw_reset:slave_write
wire [31:0] mm_interconnect_0_pll_sw_reset_s_writedata; // mm_interconnect_0:pll_sw_reset_s_writedata -> pll_sw_reset:slave_writedata
wire [31:0] mm_interconnect_0_pll_lock_avs_0_s_readdata; // pll_lock_avs_0:slave_readdata -> mm_interconnect_0:pll_lock_avs_0_s_readdata
wire mm_interconnect_0_pll_lock_avs_0_s_read; // mm_interconnect_0:pll_lock_avs_0_s_read -> pll_lock_avs_0:slave_read
wire [31:0] mm_interconnect_0_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_0:version_id_0_s_readdata
wire mm_interconnect_0_version_id_0_s_read; // mm_interconnect_0:version_id_0_s_read -> version_id_0:slave_read
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> kernel_pll:rst
wire pll_sw_reset_sw_reset_reset; // pll_sw_reset:sw_reset_n_out -> rst_controller:reset_in0
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [ctrl:reset, mm_interconnect_0:ctrl_reset_reset_bridge_in_reset_reset, pll_lock_avs_0:resetn, pll_reconfig_0:mgmt_reset, pll_rom:reset, pll_sw_reset:resetn, rst_translator:in_reset, version_id_0:resetn]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [pll_rom:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [counter:resetn, mm_interconnect_0:counter_clk_reset_reset_bridge_in_reset_reset]
system_acl_iface_acl_kernel_clk_kernel_pll kernel_pll (
.refclk (pll_refclk_clk), // refclk.clk
.rst (rst_controller_reset_out_reset), // reset.reset
.outclk_0 (kernel_pll_outclk0_clk), // outclk0.clk
.outclk_1 (kernel_pll_outclk1_clk), // outclk1.clk
.locked (kernel_pll_locked_export_signal), // locked.export
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.reconf_width (64),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("")
) pll_reconfig_0 (
.mgmt_clk (clk_clk), // mgmt_clk.clk
.mgmt_reset (rst_controller_001_reset_out_reset), // mgmt_reset.reset
.mgmt_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // mgmt_avalon_slave.readdata
.mgmt_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.mgmt_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.mgmt_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.mgmt_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // .address
.mgmt_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
system_acl_iface_acl_kernel_clk_pll_rom pll_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_pll_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_0_pll_rom_s1_write), // .write
.readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset), // reset1.reset
.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
);
timer #(
.WIDTH (32),
.S_WIDTH_A (2)
) counter (
.clk (kernel_clk_clk), // clk.clk
.clk2x (kernel_pll_outclk1_clk), // clk2x.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_address (mm_interconnect_0_counter_s_address), // s.address
.slave_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.slave_read (mm_interconnect_0_counter_s_read), // .read
.slave_write (mm_interconnect_0_counter_s_write), // .write
.slave_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.slave_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.slave_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.slave_readdatavalid (mm_interconnect_0_counter_s_readdatavalid) // .readdatavalid
);
global_routing global_routing_kernel_clk (
.s (kernel_pll_outclk0_clk), // clk.clk
.g (kernel_clk_clk) // global_clk.clk
);
global_routing global_routing_kernel_clk2x (
.s (kernel_pll_outclk1_clk), // clk.clk
.g (kernel_clk2x_clk) // global_clk.clk
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (11),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (0),
.PIPELINE_RESPONSE (0)
) ctrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.s0_waitrequest (ctrl_waitrequest), // s0.waitrequest
.s0_readdata (ctrl_readdata), // .readdata
.s0_readdatavalid (ctrl_readdatavalid), // .readdatavalid
.s0_burstcount (ctrl_burstcount), // .burstcount
.s0_writedata (ctrl_writedata), // .writedata
.s0_address (ctrl_address), // .address
.s0_write (ctrl_write), // .write
.s0_read (ctrl_read), // .read
.s0_byteenable (ctrl_byteenable), // .byteenable
.s0_debugaccess (ctrl_debugaccess), // .debugaccess
.m0_waitrequest (ctrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (ctrl_m0_readdata), // .readdata
.m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (ctrl_m0_burstcount), // .burstcount
.m0_writedata (ctrl_m0_writedata), // .writedata
.m0_address (ctrl_m0_address), // .address
.m0_write (ctrl_m0_write), // .write
.m0_read (ctrl_m0_read), // .read
.m0_byteenable (ctrl_m0_byteenable), // .byteenable
.m0_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
sw_reset #(
.WIDTH (32),
.LOG2_RESET_CYCLES (10)
) pll_sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_0_pll_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (pll_sw_reset_sw_reset_reset) // sw_reset.reset_n
);
pll_lock_avs #(
.WIDTH (32)
) pll_lock_avs_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.lock (kernel_pll_locked_export_signal), // lock.export
.lock_export (kernel_pll_locked_export), // lock_export.export
.slave_read (mm_interconnect_0_pll_lock_avs_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata) // .readdata
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.global_routing_kernel_clk_global_clk_clk (kernel_clk_clk), // global_routing_kernel_clk_global_clk.clk
.counter_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // counter_clk_reset_reset_bridge_in_reset.reset
.ctrl_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ctrl_reset_reset_bridge_in_reset.reset
.ctrl_m0_address (ctrl_m0_address), // ctrl_m0.address
.ctrl_m0_waitrequest (ctrl_m0_waitrequest), // .waitrequest
.ctrl_m0_burstcount (ctrl_m0_burstcount), // .burstcount
.ctrl_m0_byteenable (ctrl_m0_byteenable), // .byteenable
.ctrl_m0_read (ctrl_m0_read), // .read
.ctrl_m0_readdata (ctrl_m0_readdata), // .readdata
.ctrl_m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.ctrl_m0_write (ctrl_m0_write), // .write
.ctrl_m0_writedata (ctrl_m0_writedata), // .writedata
.ctrl_m0_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.counter_s_address (mm_interconnect_0_counter_s_address), // counter_s.address
.counter_s_write (mm_interconnect_0_counter_s_write), // .write
.counter_s_read (mm_interconnect_0_counter_s_read), // .read
.counter_s_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.counter_s_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.counter_s_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.counter_s_readdatavalid (mm_interconnect_0_counter_s_readdatavalid), // .readdatavalid
.counter_s_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.pll_lock_avs_0_s_read (mm_interconnect_0_pll_lock_avs_0_s_read), // pll_lock_avs_0_s.read
.pll_lock_avs_0_s_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // pll_reconfig_0_mgmt_avalon_slave.address
.pll_reconfig_0_mgmt_avalon_slave_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.pll_reconfig_0_mgmt_avalon_slave_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.pll_reconfig_0_mgmt_avalon_slave_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.pll_reconfig_0_mgmt_avalon_slave_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.pll_rom_s1_address (mm_interconnect_0_pll_rom_s1_address), // pll_rom_s1.address
.pll_rom_s1_write (mm_interconnect_0_pll_rom_s1_write), // .write
.pll_rom_s1_readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.pll_rom_s1_writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.pll_rom_s1_byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.pll_rom_s1_chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.pll_rom_s1_clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.pll_rom_s1_debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.pll_sw_reset_s_write (mm_interconnect_0_pll_sw_reset_s_write), // pll_sw_reset_s.write
.pll_sw_reset_s_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.pll_sw_reset_s_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.pll_sw_reset_s_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.pll_sw_reset_s_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.pll_sw_reset_s_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.version_id_0_s_read (mm_interconnect_0_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("none"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~pll_sw_reset_sw_reset_reset), // reset_in0.reset
.reset_in1 (~reset_reset_n), // reset_in1.reset
.clk (), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:10:01 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/xfft/xfft_stub.v
// Design : xfft
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xfft_v9_0,Vivado 2014.1" *)
module xfft(aclk, s_axis_config_tdata, s_axis_config_tvalid, s_axis_config_tready, s_axis_data_tdata, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tlast, m_axis_data_tdata, m_axis_data_tuser, m_axis_data_tvalid, m_axis_data_tready, m_axis_data_tlast, event_frame_started, event_tlast_unexpected, event_tlast_missing, event_status_channel_halt, event_data_in_channel_halt, event_data_out_channel_halt)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tdata[7:0],s_axis_config_tvalid,s_axis_config_tready,s_axis_data_tdata[31:0],s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tlast,m_axis_data_tdata[63:0],m_axis_data_tuser[15:0],m_axis_data_tvalid,m_axis_data_tready,m_axis_data_tlast,event_frame_started,event_tlast_unexpected,event_tlast_missing,event_status_channel_halt,event_data_in_channel_halt,event_data_out_channel_halt" */;
input aclk;
input [7:0]s_axis_config_tdata;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [31:0]s_axis_data_tdata;
input s_axis_data_tvalid;
output s_axis_data_tready;
input s_axis_data_tlast;
output [63:0]m_axis_data_tdata;
output [15:0]m_axis_data_tuser;
output m_axis_data_tvalid;
input m_axis_data_tready;
output m_axis_data_tlast;
output event_frame_started;
output event_tlast_unexpected;
output event_tlast_missing;
output event_status_channel_halt;
output event_data_in_channel_halt;
output event_data_out_channel_halt;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_demux_64_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_0_axis_tdata;
wire [7:0] output_0_axis_tkeep;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [63:0] output_1_axis_tdata;
wire [7:0] output_1_axis_tkeep;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [63:0] output_2_axis_tdata;
wire [7:0] output_2_axis_tkeep;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [63:0] output_3_axis_tdata;
wire [7:0] output_3_axis_tkeep;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
// dump file
$dumpfile("test_axis_demux_64_4.lxt");
$dumpvars(0, test_axis_demux_64_4);
end
axis_demux_64_4 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
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