input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
list |
|---|---|---|---|---|---|
{"name": "trans_RSC_rrrr", "code": "__int64 __fastcall trans_RSC_rrrr ( __int64 @@a1@@ , int * @@a2@@ ) { void ( __fastcall * @@v2@@ ) ( __int64 , __int64 , __int64 ) ; if ( @@a2@@ [ Number ] ) @@v2@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_rsc_CC ; else @@v2@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_rsc ; return op_s_rrr_shr ( @@a1@@ , @@a2@@ , @@v2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v2", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}, {"n": "v2", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,221 |
[
"{\"name\": \"gen_rsc\", \"code\": \"__int64 __fastcall gen_rsc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return gen_sub_carry ( @@a1@@ , @@a3@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_rsc_CC\", \"code\": \"__int64 __fastcall gen_rsc_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return gen_sbc_CC ( @@a1@@ , @@a3@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_RSC_rri", "code": "__int64 __fastcall trans_RSC_rri ( __int64 @@a1@@ , int * @@a2@@ ) { void ( __fastcall * @@v2@@ ) ( __int64 , __int64 , __int64 ) ; if ( @@a2@@ [ Number ] ) @@v2@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_rsc_CC ; else @@v2@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_rsc ; return op_s_rri_rot ( @@a1@@ , @@a2@@ , @@v2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v2", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}, {"n": "v2", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,222 |
[
"{\"name\": \"gen_rsc\", \"code\": \"__int64 __fastcall gen_rsc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return gen_sub_carry ( @@a1@@ , @@a3@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_rsc_CC\", \"code\": \"__int64 __fastcall gen_rsc_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return gen_sbc_CC ( @@a1@@ , @@a3@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TST_xrri", "code": "__int64 __fastcall trans_TST_xrri ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_s_rrr_shi ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_and_i32 , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,223 |
[
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TST_xrrr", "code": "__int64 __fastcall trans_TST_xrrr ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rrr_shr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_and_i32 , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,224 |
[
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TST_xri", "code": "__int64 __fastcall trans_TST_xri ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rri_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_and_i32 , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,225 |
[
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TEQ_xrri", "code": "__int64 __fastcall trans_TEQ_xrri ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_s_rrr_shi ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_xor_i32 , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,226 |
[
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TEQ_xrrr", "code": "__int64 __fastcall trans_TEQ_xrrr ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rrr_shr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_xor_i32 , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,227 |
[
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TEQ_xri", "code": "__int64 __fastcall trans_TEQ_xri ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rri_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_xor_i32 , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,228 |
[
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CMN_xrri", "code": "__int64 __fastcall trans_CMN_xrri ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_s_rrr_shi ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add_CC , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,229 |
[
"{\"name\": \"gen_add_CC\", \"code\": \"__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CMN_xrrr", "code": "__int64 __fastcall trans_CMN_xrrr ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rrr_shr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add_CC , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,230 |
[
"{\"name\": \"gen_add_CC\", \"code\": \"__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CMN_xri", "code": "__int64 __fastcall trans_CMN_xri ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rri_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add_CC , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,231 |
[
"{\"name\": \"gen_add_CC\", \"code\": \"__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CMP_xrri", "code": "__int64 __fastcall trans_CMP_xrri ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_s_rrr_shi ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_sub_CC , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,232 |
[
"{\"name\": \"gen_sub_CC\", \"code\": \"__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CMP_xrrr", "code": "__int64 __fastcall trans_CMP_xrrr ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rrr_shr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_sub_CC , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,233 |
[
"{\"name\": \"gen_sub_CC\", \"code\": \"__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CMP_xri", "code": "__int64 __fastcall trans_CMP_xri ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rri_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_sub_CC , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,234 |
[
"{\"name\": \"gen_sub_CC\", \"code\": \"__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_ADD_rrri", "code": "__int64 __fastcall trans_ADD_rrri ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int v2 ; void ( __fastcall * v3 ) ( __int64 , __int64 , __int64 ) ; unsigned int @@v5@@ ; if ( * @@a2@@ == Number && @@a2@@ [ Number ] == Number ) v2 = Number ; else v2 = Number ; @@v5@@ = v2 ; if ( @@a2@@ [ Number ] ) v3 = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add_CC ; else v3 = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ; return op_s_rrr_shi ( @@a1@@ , ( __int64 ) @@a2@@ , v3 , Number , @@v5@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}, {"n": "k", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s4"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,235 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_add_CC\", \"code\": \"__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_ADD_rrrr", "code": "__int64 __fastcall trans_ADD_rrrr ( __int64 @@a1@@ , int * @@a2@@ ) { int v2 ; void ( __fastcall * v3 ) ( __int64 , __int64 , __int64 ) ; unsigned int @@v5@@ ; if ( * @@a2@@ == Number && @@a2@@ [ Number ] == Number ) v2 = Number ; else v2 = Number ; @@v5@@ = v2 ; if ( @@a2@@ [ Number ] ) v3 = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add_CC ; else v3 = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ; return op_s_rrr_shr ( @@a1@@ , @@a2@@ , v3 , Number , @@v5@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}, {"n": "k", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s4"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,236 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_add_CC\", \"code\": \"__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_ADD_rri", "code": "__int64 __fastcall trans_ADD_rri ( __int64 @@a1@@ , int * @@a2@@ ) { int v2 ; void ( __fastcall * v3 ) ( __int64 , __int64 , __int64 ) ; unsigned int @@v5@@ ; if ( @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] == Number ) v2 = Number ; else v2 = Number ; @@v5@@ = v2 ; if ( @@a2@@ [ Number ] ) v3 = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add_CC ; else v3 = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ; return op_s_rri_rot ( @@a1@@ , @@a2@@ , v3 , Number , @@v5@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}, {"n": "k", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s4"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,237 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_add_CC\", \"code\": \"__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SUB_rrri", "code": "__int64 __fastcall trans_SUB_rrri ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { void ( __fastcall * @@v3@@ ) ( __int64 , __int64 , __int64 ) ; unsigned int @@v4@@ ; @@v4@@ = Number ; if ( * @@a2@@ == Number && @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } @@a2@@ [ Number ] = Number ; @@v4@@ = Number ; } else if ( * @@a2@@ == Number && @@a2@@ [ Number ] == Number ) { @@v4@@ = Number ; } if ( @@a2@@ [ Number ] ) @@v3@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_sub_CC ; else @@v3@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_sub_i32 ; return op_s_rrr_shi ( @@a1@@ , ( __int64 ) @@a2@@ , @@v3@@ , Number , @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}, {"n": "v3", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r8"}, {"n": "ret", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,238 |
[
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sub_CC\", \"code\": \"__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SUB_rrrr", "code": "__int64 __fastcall trans_SUB_rrrr ( __int64 @@a1@@ , int * @@a2@@ ) { void ( __fastcall * @@v3@@ ) ( __int64 , __int64 , __int64 ) ; unsigned int @@v4@@ ; @@v4@@ = Number ; if ( * @@a2@@ == Number && @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } @@a2@@ [ Number ] = Number ; @@v4@@ = Number ; } else if ( * @@a2@@ == Number && @@a2@@ [ Number ] == Number ) { @@v4@@ = Number ; } if ( @@a2@@ [ Number ] ) @@v3@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_sub_CC ; else @@v3@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_sub_i32 ; return op_s_rrr_shr ( @@a1@@ , @@a2@@ , @@v3@@ , Number , @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}, {"n": "v3", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r8"}, {"n": "ret", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,239 |
[
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sub_CC\", \"code\": \"__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_s_rrr_shr\", \"code\": \"__int64 __fastcall op_s_rrr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 v9 ; __int64 v10 ; __int64 @@v11@@ ; v9 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v11@@ , @@a2@@ [ Number ] , v9 , @@a4@@ ) ; v10 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( v10 , v10 , @@v11@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( @@a4@@ ) gen_logic_CC ( v10 ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , v10 , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SUB_rri", "code": "__int64 __fastcall trans_SUB_rri ( __int64 @@a1@@ , int * @@a2@@ ) { void ( __fastcall * @@v3@@ ) ( __int64 , __int64 , __int64 ) ; unsigned int @@v4@@ ; @@v4@@ = Number ; if ( @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } @@a2@@ [ Number ] = Number ; @@v4@@ = Number ; } else if ( @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] == Number ) { @@v4@@ = Number ; } if ( @@a2@@ [ Number ] ) @@v3@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_sub_CC ; else @@v3@@ = ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_sub_i32 ; return op_s_rri_rot ( @@a1@@ , @@a2@@ , @@v3@@ , Number , @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}, {"n": "v3", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r8"}, {"n": "ret", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,240 |
[
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sub_CC\", \"code\": \"__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MOV_rxri", "code": "__int64 __fastcall trans_MOV_rxri ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; @@v3@@ = Number ; if ( * @@a2@@ == Number && @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } @@a2@@ [ Number ] = Number ; @@v3@@ = Number ; } else if ( * @@a2@@ == Number ) { @@v3@@ = Number ; } return op_s_rxr_shi ( @@a1@@ , ( __int64 ) @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_mov_i32 , @@a2@@ [ Number ] , @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}, {"n": "ret", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,241 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_s_rxr_shi\", \"code\": \"__int64 __fastcall op_s_rxr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@a3@@ ( @@v9@@ , @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v9@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v9@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MOV_rxrr", "code": "__int64 __fastcall trans_MOV_rxrr ( __int64 @@a1@@ , int * @@a2@@ ) { unsigned int @@v3@@ ; @@v3@@ = Number ; if ( * @@a2@@ == Number && @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } @@a2@@ [ Number ] = Number ; @@v3@@ = Number ; } else if ( * @@a2@@ == Number ) { @@v3@@ = Number ; } return op_s_rxr_shr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_mov_i32 , @@a2@@ [ Number ] , @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}, {"n": "ret", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,242 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_s_rxr_shr\", \"code\": \"__int64 __fastcall op_s_rxr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v10@@ , @@a2@@ [ Number ] , @@v9@@ , @@a4@@ ) ; @@a3@@ ( @@v10@@ , @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MOV_rxi", "code": "__int64 __fastcall trans_MOV_rxi ( __int64 @@a1@@ , int * @@a2@@ ) { unsigned int @@v3@@ ; @@v3@@ = Number ; if ( @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } @@a2@@ [ Number ] = Number ; @@v3@@ = Number ; } else if ( @@a2@@ [ Number ] == Number ) { @@v3@@ = Number ; } return op_s_rxi_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_mov_i32 , @@a2@@ [ Number ] , @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}, {"n": "ret", "t": {"T": 1, "n": "StoreRegKind", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,243 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_s_rxi_rot\", \"code\": \"__int64 __fastcall op_s_rxi_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@a3@@ ( @@v10@@ , @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MVN_rxri", "code": "__int64 __fastcall trans_MVN_rxri ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_s_rxr_shi ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_not_i32 , * ( _DWORD * ) ( @@a2@@ + Number ) , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,244 |
[
"{\"name\": \"tcg_gen_not_i32\", \"code\": \"__int64 __fastcall tcg_gen_not_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rxr_shi\", \"code\": \"__int64 __fastcall op_s_rxr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@a3@@ ( @@v9@@ , @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v9@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v9@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MVN_rxrr", "code": "__int64 __fastcall trans_MVN_rxrr ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rxr_shr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_not_i32 , @@a2@@ [ Number ] , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,245 |
[
"{\"name\": \"tcg_gen_not_i32\", \"code\": \"__int64 __fastcall tcg_gen_not_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rxr_shr\", \"code\": \"__int64 __fastcall op_s_rxr_shr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_reg ( @@v10@@ , @@a2@@ [ Number ] , @@v9@@ , @@a4@@ ) ; @@a3@@ ( @@v10@@ , @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MVN_rxi", "code": "__int64 __fastcall trans_MVN_rxi ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rxi_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_not_i32 , @@a2@@ [ Number ] , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,246 |
[
"{\"name\": \"tcg_gen_not_i32\", \"code\": \"__int64 __fastcall tcg_gen_not_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_s_rxi_rot\", \"code\": \"__int64 __fastcall op_s_rxi_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@a3@@ ( @@v10@@ , @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_ORN_rrri", "code": "__int64 __fastcall trans_ORN_rrri ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_s_rrr_shi ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) & tcg_gen_orc_i32 , * ( _DWORD * ) ( @@a2@@ + Number ) , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrr_shi"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,247 |
[
"{\"name\": \"op_s_rrr_shi\", \"code\": \"__int64 __fastcall op_s_rrr_shi ( __int64 @@a1@@ , __int64 @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; __int64 @@v10@@ ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_arm_shift_im ( @@v9@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) , @@a4@@ ) ; @@v10@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@a3@@ ( @@v10@@ , @@v10@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v10@@ ) ; return store_reg_kind ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v10@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_ORN_rri", "code": "__int64 __fastcall trans_ORN_rri ( __int64 @@a1@@ , int * @@a2@@ ) { return op_s_rri_rot ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) & tcg_gen_orc_i32 , @@a2@@ [ Number ] , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rri_rot"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,248 |
[
"{\"name\": \"op_s_rri_rot\", \"code\": \"__int64 __fastcall op_s_rri_rot ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) , int @@a4@@ , unsigned int @@a5@@ ) { unsigned int @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; @@v9@@ = ror32 ( * @@a2@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ && @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( cpu_CF , @@v9@@ >> Number ) ; @@v10@@ = tcg_const_i32 ( @@v9@@ ) ; @@v11@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v11@@ , @@v11@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; if ( @@a4@@ ) gen_logic_CC ( @@v11@@ ) ; return store_reg_kind ( @@a1@@ , @@a2@@ [ Number ] , @@v11@@ , @@a5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_ADR", "code": "__int64 __fastcall trans_ADR ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = add_reg_for_lit ( @@a1@@ , Number , * ( _DWORD * ) @@a2@@ ) ; store_reg_bx ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , @@v2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,249 |
[
"{\"name\": \"add_reg_for_lit\", \"code\": \"__int64 __fastcall add_reg_for_lit ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { int @@v3@@ ; __int64 @@v6@@ ; @@v6@@ = tcg_temp_new_i32 ( ) ; if ( @@a2@@ == Number ) { @@v3@@ = read_pc ( @@a1@@ ) ; tcg_gen_movi_i32 ( @@v6@@ , ( @@v3@@ & Number ) + @@a3@@ ) ; } else { tcg_gen_addi_i32 ( @@v6@@ , cpu_R [ @@a2@@ ] , @@a3@@ ) ; } return @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg_bx\", \"code\": \"__int64 __fastcall store_reg_bx ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a2@@ == Number && arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = gen_bx ( @@a1@@ , @@a3@@ ) ; else @@result@@ = store_reg ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_MOVW", "code": "__int64 __fastcall trans_MOVW ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = tcg_const_i32 ( * @@a2@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MOVW"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,250 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_MOVT", "code": "__int64 __fastcall trans_MOVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_ext16u_i32 ( @@v3@@ , @@v3@@ ) ; tcg_gen_ori_i32 ( @@v3@@ , @@v3@@ , ( unsigned int ) ( * @@a2@@ << Number ) ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MOVW"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,251 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_mla", "code": "__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}]}
|
[{"n": "add", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrrr"}, "location": "r64"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,252 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_logic_CC\", \"code\": \"__int64 __fastcall gen_logic_CC ( __int64 @@a1@@ ) { tcg_gen_mov_i32 ( cpu_NF , @@a1@@ ) ; return tcg_gen_mov_i32 ( cpu_ZF , @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_MUL", "code": "__int64 __fastcall trans_MUL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mla ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MUL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,253 |
[
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}"
] |
{"name": "trans_MLA", "code": "__int64 __fastcall trans_MLA ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mla ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MLA"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,254 |
[
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}"
] |
{"name": "trans_MLS", "code": "__int64 __fastcall trans_MLS ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; __int64 v4 ; __int64 v5 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v4 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v3@@ , @@v3@@ , v4 ) ; tcg_temp_free_i32 ( v4 ) ; v5 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_sub_i32 ( @@v3@@ , v5 , @@v3@@ ) ; tcg_temp_free_i32 ( v5 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MLS"}, "location": "r64"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,255 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_mlal", "code": "__int64 __fastcall op_mlal ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_mulu2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; else tcg_gen_muls2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; if ( @@a4@@ ) { @@v9@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a2@@ [ Number ] ) gen_logicq_cc ( @@v7@@ , @@v8@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "uns", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "add", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_s_rrrr"}, "location": "r64"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "t3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,256 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_logicq_cc\", \"code\": \"__int64 __fastcall gen_logicq_cc ( __int64 @@a1@@ , __int64 @@a2@@ ) { tcg_gen_mov_i32 ( cpu_NF , @@a2@@ ) ; return tcg_gen_or_i32 ( cpu_ZF , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}"
] |
{"name": "trans_UMULL", "code": "__int64 __fastcall trans_UMULL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_UMULL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,257 |
[
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"op_mlal\", \"code\": \"__int64 __fastcall op_mlal ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_mulu2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; else tcg_gen_muls2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; if ( @@a4@@ ) { @@v9@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a2@@ [ Number ] ) gen_logicq_cc ( @@v7@@ , @@v8@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMULL", "code": "__int64 __fastcall trans_SMULL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SMULL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,258 |
[
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"op_mlal\", \"code\": \"__int64 __fastcall op_mlal ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_mulu2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; else tcg_gen_muls2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; if ( @@a4@@ ) { @@v9@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a2@@ [ Number ] ) gen_logicq_cc ( @@v7@@ , @@v8@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UMLAL", "code": "__int64 __fastcall trans_UMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_UMLAL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,259 |
[
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"op_mlal\", \"code\": \"__int64 __fastcall op_mlal ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_mulu2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; else tcg_gen_muls2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; if ( @@a4@@ ) { @@v9@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a2@@ [ Number ] ) gen_logicq_cc ( @@v7@@ , @@v8@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLAL", "code": "__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SMLAL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,260 |
[
"{\"name\": \"op_mla\", \"code\": \"__int64 __fastcall op_mla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; __int64 v6 ; __int64 v7 ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mul_i32 ( @@v5@@ , @@v5@@ , v6 ) ; tcg_temp_free_i32 ( v6 ) ; if ( @@a3@@ ) { v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v5@@ , @@v5@@ , v7 ) ; tcg_temp_free_i32 ( v7 ) ; } if ( @@a2@@ [ Number ] ) gen_logic_CC ( @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"op_mlal\", \"code\": \"__int64 __fastcall op_mlal ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_mulu2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; else tcg_gen_muls2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ ) ; if ( @@a4@@ ) { @@v9@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add2_i32 ( @@v7@@ , @@v8@@ , @@v7@@ , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a2@@ [ Number ] ) gen_logicq_cc ( @@v7@@ , @@v8@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UMAAL", "code": "__int64 __fastcall trans_UMAAL ( __int64 @@a1@@ , int * @@a2@@ ) { bool @@v2@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 v7 ; __int64 v8 ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v2@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v2@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v2@@ ) return Number L ; @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_mulu2_i32 ( @@v4@@ , @@v5@@ , @@v4@@ , @@v5@@ ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; v7 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add2_i32 ( @@v4@@ , @@v5@@ , @@v4@@ , @@v5@@ , v7 , @@v6@@ ) ; tcg_temp_free_i32 ( v7 ) ; v8 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add2_i32 ( @@v4@@ , @@v5@@ , @@v4@@ , @@v5@@ , v8 , @@v6@@ ) ; tcg_temp_free_i32 ( v8 ) ; tcg_temp_free_i32 ( @@v6@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v4@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_UMAAL"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "zero", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,261 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_qaddsub", "code": "__int64 __fastcall op_qaddsub ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) gen_helper_add_saturate ( @@v9@@ , cpu_env , @@v9@@ , @@v9@@ ) ; if ( @@a3@@ ) gen_helper_add_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; else gen_helper_sub_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "add", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "doub", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "t0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,262 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_add_saturate\", \"code\": \"unsigned __int64 __fastcall gen_helper_add_saturate ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_add_saturate , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_sub_saturate\", \"code\": \"unsigned __int64 __fastcall gen_helper_sub_saturate ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sub_saturate , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_QADD", "code": "__int64 __fastcall trans_QADD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,263 |
[
"{\"name\": \"op_qaddsub\", \"code\": \"__int64 __fastcall op_qaddsub ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) gen_helper_add_saturate ( @@v9@@ , cpu_env , @@v9@@ , @@v9@@ ) ; if ( @@a3@@ ) gen_helper_add_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; else gen_helper_sub_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QSUB", "code": "__int64 __fastcall trans_QSUB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,264 |
[
"{\"name\": \"op_qaddsub\", \"code\": \"__int64 __fastcall op_qaddsub ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) gen_helper_add_saturate ( @@v9@@ , cpu_env , @@v9@@ , @@v9@@ ) ; if ( @@a3@@ ) gen_helper_add_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; else gen_helper_sub_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QDADD", "code": "__int64 __fastcall trans_QDADD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,265 |
[
"{\"name\": \"op_qaddsub\", \"code\": \"__int64 __fastcall op_qaddsub ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) gen_helper_add_saturate ( @@v9@@ , cpu_env , @@v9@@ , @@v9@@ ) ; if ( @@a3@@ ) gen_helper_add_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; else gen_helper_sub_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QDSUB", "code": "__int64 __fastcall trans_QDSUB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,266 |
[
"{\"name\": \"op_qaddsub\", \"code\": \"__int64 __fastcall op_qaddsub ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) gen_helper_add_saturate ( @@v9@@ , cpu_env , @@v9@@ , @@v9@@ ) ; if ( @@a3@@ ) gen_helper_add_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; else gen_helper_sub_saturate ( @@v8@@ , cpu_env , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_smlaxxx", "code": "__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned __int8", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned __int8", "s": 1}, "location": "r72"}, {"n": "v5", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v14", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v15", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "add_long", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "nt", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}, {"n": "mt", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r72"}, {"n": "v5", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "tl", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "th", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,267 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_add_setq\", \"code\": \"unsigned __int64 __fastcall gen_helper_add_setq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_add_setq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_mulxy\", \"code\": \"__int64 __fastcall gen_mulxy ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( @@a3@@ ) tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , Number L ) ; else tcg_gen_ext16s_i32 ( @@a1@@ , @@a1@@ ) ; if ( @@a4@@ ) tcg_gen_sari_i32 ( @@a2@@ , @@a2@@ , Number L ) ; else tcg_gen_ext16s_i32 ( @@a2@@ , @@a2@@ ) ; return tcg_gen_mul_i32 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SMULBB", "code": "__int64 __fastcall trans_SMULBB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,268 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMULBT", "code": "__int64 __fastcall trans_SMULBT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,269 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMULTB", "code": "__int64 __fastcall trans_SMULTB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,270 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMULTT", "code": "__int64 __fastcall trans_SMULTT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,271 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLABB", "code": "__int64 __fastcall trans_SMLABB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,272 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLABT", "code": "__int64 __fastcall trans_SMLABT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,273 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLATB", "code": "__int64 __fastcall trans_SMLATB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,274 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLATT", "code": "__int64 __fastcall trans_SMLATT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,275 |
[
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLALBB", "code": "__int64 __fastcall trans_SMLALBB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,276 |
[
"{\"name\": \"trans_SMLAL\", \"code\": \"__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLALBT", "code": "__int64 __fastcall trans_SMLALBT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,277 |
[
"{\"name\": \"trans_SMLAL\", \"code\": \"__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLALTB", "code": "__int64 __fastcall trans_SMLALTB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,278 |
[
"{\"name\": \"trans_SMLAL\", \"code\": \"__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLALTT", "code": "__int64 __fastcall trans_SMLALTT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlaxxx ( @@a1@@ , @@a2@@ , Number , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,279 |
[
"{\"name\": \"trans_SMLAL\", \"code\": \"__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_smlaxxx\", \"code\": \"__int64 __fastcall op_smlaxxx ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , unsigned __int8 @@a4@@ , unsigned __int8 @@a5@@ ) { bool @@v5@@ ; __int64 @@v10@@ ; __int64 v11 ; __int64 v12 ; __int64 v13 ; __int64 @@v14@@ ; __int64 @@v15@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v5@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v5@@ ) return Number L ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v11 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_mulxy ( @@v10@@ , v11 , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i32 ( v11 ) ; if ( @@a3@@ == Number ) { @@v14@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v15@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v13 = tcg_temp_new_i32 ( ) ; tcg_gen_sari_i32 ( v13 , @@v10@@ , Number L ) ; tcg_gen_add2_i32 ( @@v14@@ , @@v15@@ , @@v14@@ , @@v15@@ , @@v10@@ , v13 ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( v13 ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v14@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; } else { if ( @@a3@@ > Number ) { LABEL_14 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return Number L ; } if ( @@a3@@ ) { if ( @@a3@@ != Number ) goto LABEL_14 ; v12 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v10@@ , cpu_env , @@v10@@ , v12 ) ; tcg_temp_free_i32 ( v12 ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } else { store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v10@@ ) ; } } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_smlawx", "code": "__int64 __fastcall op_smlawx ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 v7 ; __int64 v8 ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; v7 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) tcg_gen_andi_i32 ( @@v9@@ , @@v9@@ , Number L ) ; else tcg_gen_shli_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_muls2_i32 ( v7 , @@v9@@ , v7 , @@v9@@ ) ; tcg_temp_free_i32 ( v7 ) ; if ( @@a3@@ ) { v8 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v9@@ , cpu_env , @@v9@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "add", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "mt", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,280 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_add_setq\", \"code\": \"unsigned __int64 __fastcall gen_helper_add_setq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_add_setq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMULWB", "code": "__int64 __fastcall trans_SMULWB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlawx ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,281 |
[
"{\"name\": \"op_smlawx\", \"code\": \"__int64 __fastcall op_smlawx ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 v7 ; __int64 v8 ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; v7 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) tcg_gen_andi_i32 ( @@v9@@ , @@v9@@ , Number L ) ; else tcg_gen_shli_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_muls2_i32 ( v7 , @@v9@@ , v7 , @@v9@@ ) ; tcg_temp_free_i32 ( v7 ) ; if ( @@a3@@ ) { v8 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v9@@ , cpu_env , @@v9@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMULWT", "code": "__int64 __fastcall trans_SMULWT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlawx ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,282 |
[
"{\"name\": \"op_smlawx\", \"code\": \"__int64 __fastcall op_smlawx ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 v7 ; __int64 v8 ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; v7 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) tcg_gen_andi_i32 ( @@v9@@ , @@v9@@ , Number L ) ; else tcg_gen_shli_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_muls2_i32 ( v7 , @@v9@@ , v7 , @@v9@@ ) ; tcg_temp_free_i32 ( v7 ) ; if ( @@a3@@ ) { v8 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v9@@ , cpu_env , @@v9@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLAWB", "code": "__int64 __fastcall trans_SMLAWB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlawx ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,283 |
[
"{\"name\": \"op_smlawx\", \"code\": \"__int64 __fastcall op_smlawx ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 v7 ; __int64 v8 ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; v7 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) tcg_gen_andi_i32 ( @@v9@@ , @@v9@@ , Number L ) ; else tcg_gen_shli_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_muls2_i32 ( v7 , @@v9@@ , v7 , @@v9@@ ) ; tcg_temp_free_i32 ( v7 ) ; if ( @@a3@@ ) { v8 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v9@@ , cpu_env , @@v9@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLAWT", "code": "__int64 __fastcall trans_SMLAWT ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlawx ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,284 |
[
"{\"name\": \"op_smlawx\", \"code\": \"__int64 __fastcall op_smlawx ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 v7 ; __int64 v8 ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; v7 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ ) tcg_gen_andi_i32 ( @@v9@@ , @@v9@@ , Number L ) ; else tcg_gen_shli_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_muls2_i32 ( v7 , @@v9@@ , v7 , @@v9@@ ) ; tcg_temp_free_i32 ( v7 ) ; if ( @@a3@@ ) { v8 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v9@@ , cpu_env , @@v9@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_YIELD", "code": "__int64 __fastcall trans_YIELD ( __int64 @@a1@@ ) { if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) == Number ) { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,285 |
[
"{\"name\": \"tb_cflags\", \"code\": \"__int64 __fastcall tb_cflags ( __int64 @@a1@@ ) { return * ( unsigned int * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_WFE", "code": "__int64 __fastcall trans_WFE ( __int64 @@a1@@ ) { if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) == Number ) { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,286 |
[
"{\"name\": \"tb_cflags\", \"code\": \"__int64 __fastcall tb_cflags ( __int64 @@a1@@ ) { return * ( unsigned int * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_WFI", "code": "__int64 __fastcall trans_WFI ( __int64 @@a1@@ ) { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,287 |
[
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_MSR_imm", "code": "__int64 __fastcall trans_MSR_imm ( __int64 @@a1@@ , __int64 @@a2@@ ) { int @@v3@@ ; unsigned int @@v4@@ ; @@v3@@ = ror32 ( * ( _DWORD * ) @@a2@@ , Number * * ( _BYTE * ) ( @@a2@@ + Number ) ) ; @@v4@@ = msr_mask ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; if ( ( unsigned int ) gen_set_psr_im ( @@a1@@ , @@v4@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , @@v3@@ ) ) unallocated_encoding ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MSR_imm"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s4"}, {"n": "val", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,288 |
[
"{\"name\": \"ror32\", \"code\": \"__int64 __fastcall ror32 ( int @@a1@@ , char @@a2@@ ) { return ( unsigned int ) __ROR4__ ( @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"msr_mask\", \"code\": \"__int64 __fastcall msr_mask ( __int64 @@a1@@ , char @@a2@@ , int @@a3@@ ) { int v5 ; unsigned int v6 ; v5 = Number ; if ( ( @@a2@@ & Number ) != Number ) v5 = Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; v6 = v5 & Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! @@a3@@ ) v6 &= Number ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v6 &= Number ; return v6 ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_psr\", \"code\": \"__int64 __fastcall gen_set_psr ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v6@@ ; if ( @@a3@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v6@@ = load_cpu_offset ( Number ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , ~ @@a2@@ ) ; tcg_gen_andi_i32 ( @@a4@@ , @@a4@@ , @@a2@@ ) ; tcg_gen_or_i32 ( @@v6@@ , @@v6@@ , @@a4@@ ) ; store_cpu_offset ( @@v6@@ , Number ) ; } else { gen_set_cpsr ( @@a4@@ , @@a2@@ ) ; } tcg_temp_free_i32 ( @@a4@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_psr_im\", \"code\": \"__int64 __fastcall gen_set_psr_im ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v7@@ , @@a4@@ ) ; return gen_set_psr ( @@a1@@ , @@a2@@ , @@a3@@ , @@v7@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_crc32", "code": "__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "c", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "sz", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,289 |
[
"{\"name\": \"isar_feature_aa32_crc32\", \"code\": \"bool __fastcall isar_feature_aa32_crc32 ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_crc32\", \"code\": \"unsigned __int64 __fastcall gen_helper_crc32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_crc32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crc32c\", \"code\": \"unsigned __int64 __fastcall gen_helper_crc32c ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_crc32c , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_CRC32B", "code": "__int64 __fastcall trans_CRC32B ( __int64 @@a1@@ , int * @@a2@@ ) { return op_crc32 ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,290 |
[
"{\"name\": \"op_crc32\", \"code\": \"__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CRC32H", "code": "__int64 __fastcall trans_CRC32H ( __int64 @@a1@@ , int * @@a2@@ ) { return op_crc32 ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,291 |
[
"{\"name\": \"op_crc32\", \"code\": \"__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CRC32W", "code": "__int64 __fastcall trans_CRC32W ( __int64 @@a1@@ , int * @@a2@@ ) { return op_crc32 ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,292 |
[
"{\"name\": \"op_crc32\", \"code\": \"__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CRC32CB", "code": "__int64 __fastcall trans_CRC32CB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_crc32 ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,293 |
[
"{\"name\": \"op_crc32\", \"code\": \"__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CRC32CH", "code": "__int64 __fastcall trans_CRC32CH ( __int64 @@a1@@ , int * @@a2@@ ) { return op_crc32 ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,294 |
[
"{\"name\": \"op_crc32\", \"code\": \"__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CRC32CW", "code": "__int64 __fastcall trans_CRC32CW ( __int64 @@a1@@ , int * @@a2@@ ) { return op_crc32 ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,295 |
[
"{\"name\": \"op_crc32\", \"code\": \"__int64 __fastcall op_crc32 ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! isar_feature_aa32_crc32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a4@@ != Number ) { if ( @@a4@@ > Number ) { g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; } else if ( @@a4@@ ) { tcg_gen_ext16u_i32 ( @@v8@@ , @@v8@@ ) ; } else { tcg_gen_ext8u_i32 ( @@v8@@ , @@v8@@ ) ; } } @@v9@@ = tcg_const_i32 ( ( unsigned int ) ( Number << @@a4@@ ) ) ; if ( @@a3@@ ) gen_helper_crc32c ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; else gen_helper_crc32 ( @@v7@@ , @@v7@@ , @@v8@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MRS_bank", "code": "__int64 __fastcall trans_MRS_bank ( __int64 @@a1@@ , int * @@a2@@ ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; gen_mrs_banked ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MRS_bank"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,296 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_mrs_banked\", \"code\": \"unsigned __int64 __fastcall gen_mrs_banked ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v6@@ = Number ; @@v7@@ = Number ; if ( ( unsigned __int8 ) msr_banked_access_decode ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , & @@v6@@ , ( int * ) & @@v7@@ ) == Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; @@v9@@ = tcg_const_i32 ( @@v6@@ ) ; @@v10@@ = tcg_const_i32 ( @@v7@@ ) ; gen_helper_mrs_banked ( @@v8@@ , cpu_env , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; store_reg ( @@a1@@ , @@a4@@ , @@v8@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MSR_bank", "code": "__int64 __fastcall trans_MSR_bank ( __int64 @@a1@@ , int * @@a2@@ ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; gen_msr_banked ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MSR_bank"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,297 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_msr_banked\", \"code\": \"unsigned __int64 __fastcall gen_msr_banked ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v6@@ = Number ; @@v7@@ = Number ; if ( ( unsigned __int8 ) msr_banked_access_decode ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , & @@v6@@ , ( int * ) & @@v7@@ ) == Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v8@@ = load_reg ( @@a1@@ , @@a4@@ ) ; @@v9@@ = tcg_const_i32 ( @@v6@@ ) ; @@v10@@ = tcg_const_i32 ( @@v7@@ ) ; gen_helper_msr_banked ( cpu_env , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MRS_reg", "code": "__int64 __fastcall trans_MRS_reg ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 v3 ; __int64 v4 ; if ( arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * @@a2@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; } v3 = load_cpu_offset ( Number ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , v3 ) ; } else { v4 = tcg_temp_new_i32 ( ) ; gen_helper_cpsr_read ( v4 , cpu_env ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , v4 ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MRS_reg"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,298 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_cpsr_read\", \"code\": \"unsigned __int64 __fastcall gen_helper_cpsr_read ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_ptr_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_cpsr_read , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_MSR_reg", "code": "__int64 __fastcall trans_MSR_reg ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; __int64 @@v4@@ ; @@v3@@ = msr_mask ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] ) ; if ( arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( ( unsigned int ) gen_set_psr ( @@a1@@ , @@v3@@ , @@a2@@ [ Number ] , @@v4@@ ) ) unallocated_encoding ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MSR_reg"}, "location": "r64"}, {"n": "mask", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s12"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,299 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"msr_mask\", \"code\": \"__int64 __fastcall msr_mask ( __int64 @@a1@@ , char @@a2@@ , int @@a3@@ ) { int v5 ; unsigned int v6 ; v5 = Number ; if ( ( @@a2@@ & Number ) != Number ) v5 = Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; v6 = v5 & Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! @@a3@@ ) v6 &= Number ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v6 &= Number ; return v6 ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_psr\", \"code\": \"__int64 __fastcall gen_set_psr ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v6@@ ; if ( @@a3@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v6@@ = load_cpu_offset ( Number ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , ~ @@a2@@ ) ; tcg_gen_andi_i32 ( @@a4@@ , @@a4@@ , @@a2@@ ) ; tcg_gen_or_i32 ( @@v6@@ , @@v6@@ , @@a4@@ ) ; store_cpu_offset ( @@v6@@ , Number ) ; } else { gen_set_cpsr ( @@a4@@ , @@a2@@ ) ; } tcg_temp_free_i32 ( @@a4@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_MRS_v7m", "code": "__int64 __fastcall trans_MRS_v7m ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = tcg_const_i32 ( * ( unsigned int * ) ( @@a2@@ + Number ) ) ; gen_helper_v7m_mrs ( @@v3@@ , cpu_env , @@v3@@ ) ; store_reg ( @@a1@@ , * ( _DWORD * ) @@a2@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MRS_v7m"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,300 |
[
"{\"name\": \"gen_helper_v7m_mrs\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_mrs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_v7m_mrs , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_MSR_v7m", "code": "__int64 __fastcall trans_MSR_v7m ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = tcg_const_i32 ( ( unsigned int ) ( ( * @@a2@@ << Number ) | @@a2@@ [ Number ] ) ) ; @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_helper_v7m_msr ( cpu_env , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; @@v5@@ = tcg_const_i32 ( * ( unsigned int * ) ( @@a1@@ + Number ) ) ; gen_helper_rebuild_hflags_m32 ( cpu_env , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_MSR_v7m"}, "location": "r64"}, {"n": "reg", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "el", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,301 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v7m_msr\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_msr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_v7m_msr , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rebuild_hflags_m32\", \"code\": \"unsigned __int64 __fastcall gen_helper_rebuild_hflags_m32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_rebuild_hflags_m32 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_lookup_tb\", \"code\": \"__int64 __fastcall gen_lookup_tb ( __int64 @@a1@@ ) { __int64 @@result@@ ; tcg_gen_movi_i32 ( qword_4BEB8 , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BX", "code": "__int64 __fastcall trans_BX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_bx_excret ( @@a1@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BX"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,302 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx_excret\", \"code\": \"__int64 __fastcall gen_bx_excret ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; gen_bx ( @@a1@@ , @@a2@@ ) ; if ( arm_dc_feature ( @@a1@@ , Number ) || ( @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) , ( _BYTE ) @@result@@ ) && ( @@result@@ = arm_dc_feature ( @@a1@@ , Number ) , ( _DWORD ) @@result@@ ) ) { @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BXJ", "code": "__int64 __fastcall trans_BXJ ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! isar_feature_jazelle ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_bx ( @@a1@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BXJ"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,303 |
[
"{\"name\": \"isar_feature_jazelle\", \"code\": \"bool __fastcall isar_feature_jazelle ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"trans_BX\", \"code\": \"__int64 __fastcall trans_BX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_bx_excret ( @@a1@@ , @@v3@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BLX_r", "code": "__int64 __fastcall trans_BLX_r ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; gen_bx ( @@a1@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BLX_r"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,304 |
[
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BL\", \"code\": \"__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BXNS", "code": "__int64 __fastcall trans_BXNS ( __int64 @@a1@@ , int * @@a2@@ ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) unallocated_encoding ( @@a1@@ ) ; else gen_bxns ( @@a1@@ , * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BXNS"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,305 |
[
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bxns\", \"code\": \"__int64 __fastcall gen_bxns ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ ) ; gen_helper_v7m_bxns ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BX\", \"code\": \"__int64 __fastcall trans_BX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_bx_excret ( @@a1@@ , @@v3@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BLXNS", "code": "__int64 __fastcall trans_BLXNS ( __int64 @@a1@@ , int * @@a2@@ ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) unallocated_encoding ( @@a1@@ ) ; else gen_blxns ( @@a1@@ , * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BLXNS"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,306 |
[
"{\"name\": \"gen_blxns\", \"code\": \"__int64 __fastcall gen_blxns ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; gen_helper_v7m_blxns ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BL\", \"code\": \"__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_CLZ", "code": "__int64 __fastcall trans_CLZ ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_clzi_i32 ( @@v3@@ , @@v3@@ , Number L ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_CLZ"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,307 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_ERET", "code": "__int64 __fastcall trans_ERET ( __int64 @@a1@@ ) { __int64 @@result@@ ; __int64 @@v2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) @@v2@@ = load_cpu_offset ( Number ) ; else @@v2@@ = load_reg ( @@a1@@ , Number ) ; gen_exception_return ( @@a1@@ , @@v2@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,308 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception_return\", \"code\": \"__int64 __fastcall gen_exception_return ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = load_cpu_offset ( Number ) ; return gen_rfe ( @@a1@@ , @@a2@@ , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_HLT", "code": "__int64 __fastcall trans_HLT ( __int64 @@a1@@ , int * @@a2@@ ) { gen_hlt ( @@a1@@ , * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_HLT"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,309 |
[
"{\"name\": \"gen_hlt\", \"code\": \"__int64 __fastcall gen_hlt ( __int64 @@a1@@ , int @@a2@@ ) { int v2 ; __int64 result ; if ( ( unsigned __int8 ) semihosting_enabled ( ) && * ( _DWORD * ) ( @@a1@@ + Number ) && ( ! * ( _DWORD * ) ( @@a1@@ + Number ) ? ( v2 = Number ) : ( v2 = Number ) , v2 == @@a2@@ ) ) { result = gen_exception_internal_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number ) ; } else { result = unallocated_encoding ( @@a1@@ ) ; } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_BKPT", "code": "__int64 __fastcall trans_BKPT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( arm_dc_feature ( @@a1@@ , Number ) && ( unsigned __int8 ) semihosting_enabled ( ) && ! * ( _DWORD * ) ( @@a1@@ + Number ) && * @@a2@@ == Number ) { gen_exception_internal_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number ) ; } else { @@v3@@ = syn_aa32_bkpt ( * @@a2@@ , Number ) ; gen_exception_bkpt_insn ( @@a1@@ , @@v3@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BKPT"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,310 |
[
"{\"name\": \"syn_aa32_bkpt\", \"code\": \"__int64 __fastcall syn_aa32_bkpt ( unsigned __int16 @@a1@@ , char @@a2@@ ) { int @@v2@@ ; if ( @@a2@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; return @@v2@@ | @@a1@@ | Number ; }\", \"source\": [{\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int16\", \"s\": 2}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal\", \"code\": \"__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal_insn\", \"code\": \"__int64 __fastcall gen_exception_internal_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception_internal ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception_bkpt_insn\", \"code\": \"__int64 __fastcall gen_exception_bkpt_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v3@@ = tcg_const_i32 ( @@a2@@ ) ; gen_helper_exception_bkpt_insn ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_HVC", "code": "__int64 __fastcall trans_HVC ( __int64 @@a1@@ , int * @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) unallocated_encoding ( @@a1@@ ) ; else gen_hvc ( @@a1@@ , * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_HVC"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,311 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_hvc\", \"code\": \"__int64 __fastcall gen_hvc ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; gen_helper_pre_hvc ( cpu_env ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a2@@ ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_SMC", "code": "__int64 __fastcall trans_SMC ( __int64 @@a1@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) unallocated_encoding ( @@a1@@ ) ; else gen_smc ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,312 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_smc\", \"code\": \"__int64 __fastcall gen_smc ( __int64 @@a1@@ ) { unsigned int v1 ; __int64 result ; __int64 @@v3@@ ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; v1 = syn_aa32_smc ( ) ; @@v3@@ = tcg_const_i32 ( v1 ) ; gen_helper_pre_smc ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; result = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_SG", "code": "__int64 __fastcall trans_SG ( __int64 @@a1@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,313 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_TT", "code": "__int64 __fastcall trans_TT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || * @@a2@@ && * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v4@@ = tcg_const_i32 ( ( unsigned int ) ( Number * * @@a2@@ ) | @@a2@@ [ Number ] ) ; gen_helper_v7m_tt ( @@v4@@ , cpu_env , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v4@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_TT"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,314 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v7m_tt\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_tt ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_v7m_tt , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "make_issinfo", "code": "__int64 __fastcall make_issinfo ( __int64 @@a1@@ , unsigned int @@a2@@ , char @@a3@@ , char @@a4@@ ) { if ( ! @@a3@@ || @@a4@@ == Number ) @@a2@@ = Number ; return @@a2@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}]}
|
[{"n": "p", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "w", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,315 |
[] |
{"name": "op_addr_rr_pre", "code": "__int64 __fastcall op_addr_rr_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v3@@ ) ; if ( * @@a2@@ ) { @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v4@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; else tcg_gen_sub_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "ofs", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,316 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v8m_stackcheck\", \"code\": \"unsigned __int64 __fastcall gen_helper_v8m_stackcheck ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v8m_stackcheck , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_arm_shift_im\", \"code\": \"void __fastcall gen_arm_shift_im ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ ) { unsigned int @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = @@a3@@ ; if ( @@a2@@ == Number ) { if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@a3@@ - Number ) ; tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else { @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v6@@ , cpu_CF , Number L ) ; if ( @@a4@@ ) shifter_out_im ( @@a1@@ , Number ) ; tcg_gen_shri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { if ( ! @@a3@@ ) @@v5@@ = Number ; if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@v5@@ - Number ) ; if ( @@v5@@ == Number ) @@v5@@ = Number ; tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) { if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@a3@@ - Number ) ; tcg_gen_shri_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else { if ( @@a4@@ ) tcg_gen_shri_i32 ( cpu_CF , @@a1@@ , Number L ) ; tcg_gen_movi_i32 ( @@a1@@ , Number ) ; } } } else if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , Number - @@a3@@ ) ; tcg_gen_shli_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } } }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_addr_rr_post", "code": "__int64 __fastcall op_addr_rr_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v7@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; else tcg_gen_sub_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@a4@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "addr", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "address_offset", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "ofs", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,317 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_arm_shift_im\", \"code\": \"void __fastcall gen_arm_shift_im ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ ) { unsigned int @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = @@a3@@ ; if ( @@a2@@ == Number ) { if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@a3@@ - Number ) ; tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else { @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v6@@ , cpu_CF , Number L ) ; if ( @@a4@@ ) shifter_out_im ( @@a1@@ , Number ) ; tcg_gen_shri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { if ( ! @@a3@@ ) @@v5@@ = Number ; if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@v5@@ - Number ) ; if ( @@v5@@ == Number ) @@v5@@ = Number ; tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) { if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@a3@@ - Number ) ; tcg_gen_shri_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else { if ( @@a4@@ ) tcg_gen_shri_i32 ( cpu_CF , @@a1@@ , Number L ) ; tcg_gen_movi_i32 ( @@a1@@ , Number ) ; } } } else if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , Number - @@a3@@ ) ; tcg_gen_shli_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } } }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_load_rr", "code": "__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "s20"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "issinfo", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,318 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_set_da_iss\", \"code\": \"__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg_from_load\", \"code\": \"__int64 __fastcall store_reg_from_load ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a2@@ == Number && arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = gen_bx_excret ( @@a1@@ , @@a3@@ ) ; else @@result@@ = store_reg ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"make_issinfo\", \"code\": \"__int64 __fastcall make_issinfo ( __int64 @@a1@@ , unsigned int @@a2@@ , char @@a3@@ , char @@a4@@ ) { if ( ! @@a3@@ || @@a4@@ == Number ) @@a2@@ = Number ; return @@a2@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"op_addr_rr_pre\", \"code\": \"__int64 __fastcall op_addr_rr_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v3@@ ) ; if ( * @@a2@@ ) { @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v4@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; else tcg_gen_sub_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_rr_post\", \"code\": \"__int64 __fastcall op_addr_rr_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v7@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; else tcg_gen_sub_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@a4@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_store_rr", "code": "__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "r8"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "s20"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "r8"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "issinfo", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,319 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"disas_set_da_iss\", \"code\": \"__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"make_issinfo\", \"code\": \"__int64 __fastcall make_issinfo ( __int64 @@a1@@ , unsigned int @@a2@@ , char @@a3@@ , char @@a4@@ ) { if ( ! @@a3@@ || @@a4@@ == Number ) @@a2@@ = Number ; return @@a2@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"op_addr_rr_pre\", \"code\": \"__int64 __fastcall op_addr_rr_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v3@@ ) ; if ( * @@a2@@ ) { @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v4@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; else tcg_gen_sub_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_rr_post\", \"code\": \"__int64 __fastcall op_addr_rr_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v7@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; else tcg_gen_sub_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@a4@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRD_rr", "code": "__int64 __fastcall trans_LDRD_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v3@@ ; __int64 @@v4@@ ; __int64 v5 ; __int64 v6 ; @@v3@@ = get_mem_index ( @@a1@@ ) ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; } else { @@v4@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; v5 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v5 , @@v4@@ , @@v3@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , v5 ) ; tcg_gen_addi_i32 ( @@v4@@ , @@v4@@ , Number L ) ; v6 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v6 , @@v4@@ , @@v3@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] + Number , v6 ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v4@@ , Number ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,320 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_addr_rr_pre\", \"code\": \"__int64 __fastcall op_addr_rr_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v3@@ ) ; if ( * @@a2@@ ) { @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v4@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; else tcg_gen_sub_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_rr_post\", \"code\": \"__int64 __fastcall op_addr_rr_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v7@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; else tcg_gen_sub_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@a4@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
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