input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
list |
|---|---|---|---|---|---|
{"name": "trans_STRD_rr", "code": "__int64 __fastcall trans_STRD_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v3@@ ; __int64 @@v4@@ ; __int64 v5 ; __int64 v6 ; @@v3@@ = get_mem_index ( @@a1@@ ) ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; } else { @@v4@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; v5 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , v5 , @@v4@@ , @@v3@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v5 ) ; tcg_gen_addi_i32 ( @@v4@@ , @@v4@@ , Number L ) ; v6 = load_reg ( @@a1@@ , @@a2@@ [ Number ] + Number ) ; gen_aa32_st_i32 ( @@a1@@ , v6 , @@v4@@ , @@v3@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v6 ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v4@@ , Number ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,321 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_addr_rr_pre\", \"code\": \"__int64 __fastcall op_addr_rr_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v3@@ ) ; if ( * @@a2@@ ) { @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v4@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; else tcg_gen_sub_i32 ( @@v3@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_rr_post\", \"code\": \"__int64 __fastcall op_addr_rr_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v7@@ ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_arm_shift_im ( @@v7@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; if ( @@a2@@ [ Number ] ) tcg_gen_add_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; else tcg_gen_sub_i32 ( @@a3@@ , @@a3@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@a4@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_addr_ri_pre", "code": "__int64 __fastcall op_addr_ri_pre ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { unsigned int @@v2@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = * @@a2@@ ; if ( ! @@a2@@ [ Number ] ) @@v4@@ = - @@v4@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( @@a2@@ [ Number ] ) { gen_helper_v8m_stackcheck ( cpu_env , qword_4BEA8 ) ; } else { @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_addi_i32 ( @@v5@@ , qword_4BEA8 , @@v4@@ ) ; gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; } } if ( @@a2@@ [ Number ] ) @@v2@@ = @@v4@@ ; else @@v2@@ = Number ; return add_reg_for_lit ( @@a1@@ , @@a2@@ [ Number ] , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "ofs", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "newsp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,322 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_v8m_stackcheck\", \"code\": \"unsigned __int64 __fastcall gen_helper_v8m_stackcheck ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v8m_stackcheck , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"add_reg_for_lit\", \"code\": \"__int64 __fastcall add_reg_for_lit ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { int @@v3@@ ; __int64 @@v6@@ ; @@v6@@ = tcg_temp_new_i32 ( ) ; if ( @@a2@@ == Number ) { @@v3@@ = read_pc ( @@a1@@ ) ; tcg_gen_movi_i32 ( @@v6@@ , ( @@v3@@ & Number ) + @@a3@@ ) ; } else { tcg_gen_addi_i32 ( @@v6@@ , cpu_R [ @@a2@@ ] , @@a3@@ ) ; } return @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_addr_ri_post", "code": "__int64 __fastcall op_addr_ri_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v5@@ ; @@v5@@ = @@a4@@ ; if ( @@a2@@ [ Number ] ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else if ( @@a2@@ [ Number ] ) { @@v5@@ = * @@a2@@ + @@a4@@ ; } else { @@v5@@ = @@a4@@ - * @@a2@@ ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@v5@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}]}
|
[{"n": "addr", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "address_offset", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "address_offseta", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,323 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_load_ri", "code": "__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "s20"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "issinfo", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,324 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_set_da_iss\", \"code\": \"__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg_from_load\", \"code\": \"__int64 __fastcall store_reg_from_load ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a2@@ == Number && arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = gen_bx_excret ( @@a1@@ , @@a3@@ ) ; else @@result@@ = store_reg ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"make_issinfo\", \"code\": \"__int64 __fastcall make_issinfo ( __int64 @@a1@@ , unsigned int @@a2@@ , char @@a3@@ , char @@a4@@ ) { if ( ! @@a3@@ || @@a4@@ == Number ) @@a2@@ = Number ; return @@a2@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"op_addr_ri_pre\", \"code\": \"__int64 __fastcall op_addr_ri_pre ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { unsigned int @@v2@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = * @@a2@@ ; if ( ! @@a2@@ [ Number ] ) @@v4@@ = - @@v4@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( @@a2@@ [ Number ] ) { gen_helper_v8m_stackcheck ( cpu_env , qword_4BEA8 ) ; } else { @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_addi_i32 ( @@v5@@ , qword_4BEA8 , @@v4@@ ) ; gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; } } if ( @@a2@@ [ Number ] ) @@v2@@ = @@v4@@ ; else @@v2@@ = Number ; return add_reg_for_lit ( @@a1@@ , @@a2@@ [ Number ] , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_ri_post\", \"code\": \"__int64 __fastcall op_addr_ri_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v5@@ ; @@v5@@ = @@a4@@ ; if ( @@a2@@ [ Number ] ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else if ( @@a2@@ [ Number ] ) { @@v5@@ = * @@a2@@ + @@a4@@ ; } else { @@v5@@ = @@a4@@ - * @@a2@@ ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@v5@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s28\"}]}"
] |
{"name": "op_store_ri", "code": "__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "r8"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "s20"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "r8"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "issinfo", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "s20"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,325 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"disas_set_da_iss\", \"code\": \"__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"make_issinfo\", \"code\": \"__int64 __fastcall make_issinfo ( __int64 @@a1@@ , unsigned int @@a2@@ , char @@a3@@ , char @@a4@@ ) { if ( ! @@a3@@ || @@a4@@ == Number ) @@a2@@ = Number ; return @@a2@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"op_addr_ri_pre\", \"code\": \"__int64 __fastcall op_addr_ri_pre ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { unsigned int @@v2@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = * @@a2@@ ; if ( ! @@a2@@ [ Number ] ) @@v4@@ = - @@v4@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( @@a2@@ [ Number ] ) { gen_helper_v8m_stackcheck ( cpu_env , qword_4BEA8 ) ; } else { @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_addi_i32 ( @@v5@@ , qword_4BEA8 , @@v4@@ ) ; gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; } } if ( @@a2@@ [ Number ] ) @@v2@@ = @@v4@@ ; else @@v2@@ = Number ; return add_reg_for_lit ( @@a1@@ , @@a2@@ [ Number ] , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_ri_post\", \"code\": \"__int64 __fastcall op_addr_ri_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v5@@ ; @@v5@@ = @@a4@@ ; if ( @@a2@@ [ Number ] ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else if ( @@a2@@ [ Number ] ) { @@v5@@ = * @@a2@@ + @@a4@@ ; } else { @@v5@@ = @@a4@@ - * @@a2@@ ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@v5@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s28\"}]}"
] |
{"name": "op_ldrd_ri", "code": "__int64 __fastcall op_ldrd_ri ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v6@@ ; __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; @@v6@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = op_addr_ri_pre ( @@a1@@ , ( unsigned int * ) @@a2@@ ) ; v8 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v8 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , v8 ) ; tcg_gen_addi_i32 ( @@v7@@ , @@v7@@ , Number L ) ; v9 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v9 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , @@a3@@ , v9 ) ; op_addr_ri_post ( @@a1@@ , ( _DWORD * ) @@a2@@ , @@v7@@ , Number ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]}
|
[{"n": "rt2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,326 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_ri_pre\", \"code\": \"__int64 __fastcall op_addr_ri_pre ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { unsigned int @@v2@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = * @@a2@@ ; if ( ! @@a2@@ [ Number ] ) @@v4@@ = - @@v4@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( @@a2@@ [ Number ] ) { gen_helper_v8m_stackcheck ( cpu_env , qword_4BEA8 ) ; } else { @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_addi_i32 ( @@v5@@ , qword_4BEA8 , @@v4@@ ) ; gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; } } if ( @@a2@@ [ Number ] ) @@v2@@ = @@v4@@ ; else @@v2@@ = Number ; return add_reg_for_lit ( @@a1@@ , @@a2@@ [ Number ] , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_ri_post\", \"code\": \"__int64 __fastcall op_addr_ri_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v5@@ ; @@v5@@ = @@a4@@ ; if ( @@a2@@ [ Number ] ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else if ( @@a2@@ [ Number ] ) { @@v5@@ = * @@a2@@ + @@a4@@ ; } else { @@v5@@ = @@a4@@ - * @@a2@@ ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@v5@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s28\"}]}"
] |
{"name": "trans_LDRD_ri_a32", "code": "__int64 __fastcall trans_LDRD_ri_a32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ( * ( _DWORD * ) ( @@a2@@ + Number ) & Number ) == Number ) @@result@@ = op_ldrd_ri ( @@a1@@ , @@a2@@ , * ( _DWORD * ) ( @@a2@@ + Number ) + Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,327 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrd_ri\", \"code\": \"__int64 __fastcall op_ldrd_ri ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v6@@ ; __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; @@v6@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = op_addr_ri_pre ( @@a1@@ , ( unsigned int * ) @@a2@@ ) ; v8 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v8 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , v8 ) ; tcg_gen_addi_i32 ( @@v7@@ , @@v7@@ , Number L ) ; v9 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v9 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , @@a3@@ , v9 ) ; op_addr_ri_post ( @@a1@@ , ( _DWORD * ) @@a2@@ , @@v7@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}]}"
] |
{"name": "trans_LDRD_ri_t32", "code": "__int64 __fastcall trans_LDRD_ri_t32 ( __int64 @@a1@@ , int * @@a2@@ ) { int @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = * @@a2@@ ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; return op_ldrd_ri ( @@a1@@ , ( __int64 ) @@v3@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 2, "n": 6, "s": 4, "t": "int"}, "location": "s32"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri2"}, "location": "r64"}, {"n": "b", "t": {"T": 6, "n": "arg_ldst_ri", "l": [{"T": 4, "n": "imm", "t": "int", "s": 4}, {"T": 4, "n": "p", "t": "int", "s": 4}, {"T": 4, "n": "rn", "t": "int", "s": 4}, {"T": 4, "n": "rt", "t": "int", "s": 4}, {"T": 4, "n": "u", "t": "int", "s": 4}, {"T": 4, "n": "w", "t": "int", "s": 4}]}, "location": "s32"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,328 |
[
"{\"name\": \"op_ldrd_ri\", \"code\": \"__int64 __fastcall op_ldrd_ri ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v6@@ ; __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; @@v6@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = op_addr_ri_pre ( @@a1@@ , ( unsigned int * ) @@a2@@ ) ; v8 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v8 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , v8 ) ; tcg_gen_addi_i32 ( @@v7@@ , @@v7@@ , Number L ) ; v9 = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , v9 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; store_reg ( @@a1@@ , @@a3@@ , v9 ) ; op_addr_ri_post ( @@a1@@ , ( _DWORD * ) @@a2@@ , @@v7@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}]}"
] |
{"name": "op_strd_ri", "code": "__int64 __fastcall op_strd_ri ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v6@@ ; __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; @@v6@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = op_addr_ri_pre ( @@a1@@ , ( unsigned int * ) @@a2@@ ) ; v8 = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_aa32_st_i32 ( @@a1@@ , v8 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v8 ) ; tcg_gen_addi_i32 ( @@v7@@ , @@v7@@ , Number L ) ; v9 = load_reg ( @@a1@@ , @@a3@@ ) ; gen_aa32_st_i32 ( @@a1@@ , v9 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v9 ) ; op_addr_ri_post ( @@a1@@ , ( _DWORD * ) @@a2@@ , @@v7@@ , Number ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]}
|
[{"n": "rt2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,329 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_ri_pre\", \"code\": \"__int64 __fastcall op_addr_ri_pre ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { unsigned int @@v2@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = * @@a2@@ ; if ( ! @@a2@@ [ Number ] ) @@v4@@ = - @@v4@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) { if ( @@a2@@ [ Number ] ) { gen_helper_v8m_stackcheck ( cpu_env , qword_4BEA8 ) ; } else { @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_addi_i32 ( @@v5@@ , qword_4BEA8 , @@v4@@ ) ; gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; } } if ( @@a2@@ [ Number ] ) @@v2@@ = @@v4@@ ; else @@v2@@ = Number ; return add_reg_for_lit ( @@a1@@ , @@a2@@ [ Number ] , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_ri_post\", \"code\": \"__int64 __fastcall op_addr_ri_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , unsigned int @@a4@@ ) { unsigned int @@v5@@ ; @@v5@@ = @@a4@@ ; if ( @@a2@@ [ Number ] ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; } else if ( @@a2@@ [ Number ] ) { @@v5@@ = * @@a2@@ + @@a4@@ ; } else { @@v5@@ = @@a4@@ - * @@a2@@ ; } tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , @@v5@@ ) ; return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s28\"}]}"
] |
{"name": "trans_STRD_ri_a32", "code": "__int64 __fastcall trans_STRD_ri_a32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ( * ( _DWORD * ) ( @@a2@@ + Number ) & Number ) == Number ) @@result@@ = op_strd_ri ( @@a1@@ , @@a2@@ , * ( _DWORD * ) ( @@a2@@ + Number ) + Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,330 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strd_ri\", \"code\": \"__int64 __fastcall op_strd_ri ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v6@@ ; __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; @@v6@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = op_addr_ri_pre ( @@a1@@ , ( unsigned int * ) @@a2@@ ) ; v8 = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_aa32_st_i32 ( @@a1@@ , v8 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v8 ) ; tcg_gen_addi_i32 ( @@v7@@ , @@v7@@ , Number L ) ; v9 = load_reg ( @@a1@@ , @@a3@@ ) ; gen_aa32_st_i32 ( @@a1@@ , v9 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v9 ) ; op_addr_ri_post ( @@a1@@ , ( _DWORD * ) @@a2@@ , @@v7@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}]}"
] |
{"name": "trans_STRD_ri_t32", "code": "__int64 __fastcall trans_STRD_ri_t32 ( __int64 @@a1@@ , int * @@a2@@ ) { int @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = * @@a2@@ ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; @@v3@@ [ Number ] = @@a2@@ [ Number ] ; return op_strd_ri ( @@a1@@ , ( __int64 ) @@v3@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 2, "n": 6, "s": 4, "t": "int"}, "location": "s32"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri2"}, "location": "r64"}, {"n": "b", "t": {"T": 6, "n": "arg_ldst_ri", "l": [{"T": 4, "n": "imm", "t": "int", "s": 4}, {"T": 4, "n": "p", "t": "int", "s": 4}, {"T": 4, "n": "rn", "t": "int", "s": 4}, {"T": 4, "n": "rt", "t": "int", "s": 4}, {"T": 4, "n": "u", "t": "int", "s": 4}, {"T": 4, "n": "w", "t": "int", "s": 4}]}, "location": "s32"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,331 |
[
"{\"name\": \"op_strd_ri\", \"code\": \"__int64 __fastcall op_strd_ri ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v6@@ ; __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; @@v6@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = op_addr_ri_pre ( @@a1@@ , ( unsigned int * ) @@a2@@ ) ; v8 = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; gen_aa32_st_i32 ( @@a1@@ , v8 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v8 ) ; tcg_gen_addi_i32 ( @@v7@@ , @@v7@@ , Number L ) ; v9 = load_reg ( @@a1@@ , @@a3@@ ) ; gen_aa32_st_i32 ( @@a1@@ , v9 , @@v7@@ , @@v6@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; tcg_temp_free_i32 ( v9 ) ; op_addr_ri_post ( @@a1@@ , ( _DWORD * ) @@a2@@ , @@v7@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s20\"}]}"
] |
{"name": "trans_LDR_ri", "code": "__int64 __fastcall trans_LDR_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,332 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRT_ri", "code": "__int64 __fastcall trans_LDRT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,333 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDR_rr", "code": "__int64 __fastcall trans_LDR_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,334 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRT_rr", "code": "__int64 __fastcall trans_LDRT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,335 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRB_ri", "code": "__int64 __fastcall trans_LDRB_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,336 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRBT_ri", "code": "__int64 __fastcall trans_LDRBT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,337 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRB_rr", "code": "__int64 __fastcall trans_LDRB_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,338 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRBT_rr", "code": "__int64 __fastcall trans_LDRBT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,339 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRH_ri", "code": "__int64 __fastcall trans_LDRH_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,340 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRHT_ri", "code": "__int64 __fastcall trans_LDRHT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,341 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRH_rr", "code": "__int64 __fastcall trans_LDRH_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,342 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRHT_rr", "code": "__int64 __fastcall trans_LDRHT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,343 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSB_ri", "code": "__int64 __fastcall trans_LDRSB_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,344 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSBT_ri", "code": "__int64 __fastcall trans_LDRSBT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,345 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSB_rr", "code": "__int64 __fastcall trans_LDRSB_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,346 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSBT_rr", "code": "__int64 __fastcall trans_LDRSBT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,347 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSH_ri", "code": "__int64 __fastcall trans_LDRSH_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,348 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSHT_ri", "code": "__int64 __fastcall trans_LDRSHT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,349 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_ri\", \"code\": \"__int64 __fastcall op_load_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSH_rr", "code": "__int64 __fastcall trans_LDRSH_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,350 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDRSHT_rr", "code": "__int64 __fastcall trans_LDRSHT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_load_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,351 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_load_rr\", \"code\": \"__int64 __fastcall op_load_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v7@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; @@v8@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v9@@ = tcg_temp_new_i32 ( ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v7@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v8@@ , Number ) ; store_reg_from_load ( @@a1@@ , @@a2@@ [ Number ] , @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STR_ri", "code": "__int64 __fastcall trans_STR_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_store_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,352 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_store_ri\", \"code\": \"__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRT_ri", "code": "__int64 __fastcall trans_STRT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_store_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,353 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_store_ri\", \"code\": \"__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STR_rr", "code": "__int64 __fastcall trans_STR_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_store_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,354 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_store_rr\", \"code\": \"__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRT_rr", "code": "__int64 __fastcall trans_STRT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_store_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,355 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_store_rr\", \"code\": \"__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRB_ri", "code": "__int64 __fastcall trans_STRB_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_store_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,356 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_store_ri\", \"code\": \"__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRBT_ri", "code": "__int64 __fastcall trans_STRBT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_store_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,357 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_store_ri\", \"code\": \"__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRB_rr", "code": "__int64 __fastcall trans_STRB_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_store_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,358 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_store_rr\", \"code\": \"__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRBT_rr", "code": "__int64 __fastcall trans_STRBT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_store_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,359 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_store_rr\", \"code\": \"__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRH_ri", "code": "__int64 __fastcall trans_STRH_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_store_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,360 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_store_ri\", \"code\": \"__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRHT_ri", "code": "__int64 __fastcall trans_STRHT_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_store_ri ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_ri"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,361 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_store_ri\", \"code\": \"__int64 __fastcall op_store_ri ( __int64 @@a1@@ , unsigned int * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_ri_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_ri_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRH_rr", "code": "__int64 __fastcall trans_STRH_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_mem_index ( @@a1@@ ) ; return op_store_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,362 |
[
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"op_store_rr\", \"code\": \"__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STRHT_rr", "code": "__int64 __fastcall trans_STRHT_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = get_a32_user_mem_index ( @@a1@@ ) ; return op_store_rr ( @@a1@@ , @@a2@@ , Number , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_rr"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,363 |
[
"{\"name\": \"get_a32_user_mem_index\", \"code\": \"__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"op_store_rr\", \"code\": \"__int64 __fastcall op_store_rr ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int16 @@v4@@ ; __int16 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; @@v4@@ = make_issinfo ( @@a1@@ , @@a2@@ [ Number ] , * @@a2@@ != Number , @@a2@@ [ Number ] != Number ) ; LOBYTE ( @@v4@@ ) = @@v4@@ | Number ; @@v8@@ = @@v4@@ ; @@v9@@ = op_addr_rr_pre ( @@a1@@ , @@a2@@ ) ; @@v10@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_aa32_st_i32 ( @@a1@@ , @@v10@@ , @@v9@@ , @@a4@@ , @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; op_addr_rr_post ( @@a1@@ , @@a2@@ , @@v9@@ , Number ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r8\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"s20\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_swp", "code": "__int64 __fastcall op_swp ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ ) { int @@v3@@ ; unsigned int @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | @@a3@@ ; @@v6@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v7@@ = gen_aa32_addr ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v3@@ = get_mem_index ( @@a1@@ ) ; tcg_gen_atomic_xchg_i32 ( @@v8@@ , @@v7@@ , @@v8@@ , @@v3@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s52"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "opc", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SWP"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "taddr", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "opca", "t": {"T": 1, "n": "__int32", "s": 4}, "location": "s52"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,364 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_addr\", \"code\": \"__int64 __fastcall gen_aa32_addr ( __int64 @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v5@@ , @@a2@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a3@@ & Number ) == Number ) tcg_gen_xori_i64 ( @@v5@@ , @@v5@@ , Number - ( Number << ( @@a3@@ & Number ) ) ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SWP", "code": "__int64 __fastcall trans_SWP ( __int64 @@a1@@ , int * @@a2@@ ) { return op_swp ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SWP"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,365 |
[
"{\"name\": \"op_swp\", \"code\": \"__int64 __fastcall op_swp ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ ) { int @@v3@@ ; unsigned int @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | @@a3@@ ; @@v6@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v7@@ = gen_aa32_addr ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v3@@ = get_mem_index ( @@a1@@ ) ; tcg_gen_atomic_xchg_i32 ( @@v8@@ , @@v7@@ , @@v8@@ , @@v3@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SWPB", "code": "__int64 __fastcall trans_SWPB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_swp ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SWP"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,366 |
[
"{\"name\": \"op_swp\", \"code\": \"__int64 __fastcall op_swp ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ ) { int @@v3@@ ; unsigned int @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | @@a3@@ ; @@v6@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; @@v7@@ = gen_aa32_addr ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v3@@ = get_mem_index ( @@a1@@ ) ; tcg_gen_atomic_xchg_i32 ( @@v8@@ , @@v7@@ , @@v8@@ , @@v3@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v7@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SWP\", \"code\": \"__int64 __fastcall trans_SWP ( __int64 @@a1@@ , int * @@a2@@ ) { return op_swp ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "op_strex", "code": "__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "rel", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,367 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_local_new_i32\", \"code\": \"__int64 tcg_temp_local_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg_var\", \"code\": \"__int64 __fastcall load_reg_var ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v3@@ ; if ( @@a3@@ != Number ) return tcg_gen_mov_i32 ( @@a2@@ , cpu_R [ @@a3@@ ] ) ; @@v3@@ = read_pc ( @@a1@@ ) ; return tcg_gen_movi_i32 ( @@a2@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_store_exclusive\", \"code\": \"__int64 __fastcall gen_store_exclusive ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , __int64 @@a5@@ , int @@a6@@ ) { int v6 ; int v7 ; unsigned int @@v13@@ ; _BYTE * @@v14@@ ; _BYTE * @@v15@@ ; __int64 @@v16@@ ; __int64 @@v17@@ ; __int64 @@v18@@ ; __int64 @@v19@@ ; __int64 v20 ; __int64 v21 ; __int64 @@v22@@ ; __int64 @@v23@@ ; @@v13@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | @@a6@@ | Number ; @@v14@@ = ( _BYTE * ) gen_new_label ( ) ; @@v15@@ = ( _BYTE * ) gen_new_label ( ) ; @@v16@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v16@@ , @@a5@@ ) ; tcg_gen_brcond_i64 ( Number L , @@v16@@ , cpu_exclusive_addr , @@v14@@ ) ; tcg_temp_free_i64 ( @@v16@@ ) ; @@v17@@ = gen_aa32_addr ( @@a1@@ , @@a5@@ , @@v13@@ ) ; @@v18@@ = tcg_temp_new_i32 ( ) ; @@v19@@ = load_reg ( @@a1@@ , @@a3@@ ) ; if ( @@a6@@ == Number ) { @@v22@@ = tcg_temp_new_i64 ( ) ; @@v23@@ = tcg_temp_new_i64 ( ) ; v20 = load_reg ( @@a1@@ , @@a4@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) tcg_gen_concat_i32_i64 ( @@v23@@ , v20 , @@v19@@ ) ; else tcg_gen_concat_i32_i64 ( @@v23@@ , @@v19@@ , v20 ) ; tcg_temp_free_i32 ( v20 ) ; v6 = get_mem_index ( @@a1@@ ) ; tcg_gen_atomic_cmpxchg_i64 ( @@v22@@ , @@v17@@ , cpu_exclusive_val , @@v23@@ , v6 , @@v13@@ ) ; tcg_temp_free_i64 ( @@v23@@ ) ; tcg_gen_setcond_i64 ( Number L , @@v22@@ , @@v22@@ , cpu_exclusive_val ) ; tcg_gen_extrl_i64_i32 ( @@v18@@ , @@v22@@ ) ; tcg_temp_free_i64 ( @@v22@@ ) ; } else { v21 = tcg_temp_new_i32 ( ) ; tcg_gen_extrl_i64_i32 ( v21 , cpu_exclusive_val ) ; v7 = get_mem_index ( @@a1@@ ) ; tcg_gen_atomic_cmpxchg_i32 ( @@v18@@ , @@v17@@ , v21 , @@v19@@ , v7 , @@v13@@ ) ; tcg_gen_setcond_i32 ( Number L , @@v18@@ , @@v18@@ , v21 ) ; tcg_temp_free_i32 ( v21 ) ; } tcg_temp_free_i32 ( @@v19@@ ) ; tcg_temp_free_i64 ( @@v17@@ ) ; tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@v18@@ ) ; tcg_temp_free_i32 ( @@v18@@ ) ; tcg_gen_br ( ( __int64 ) @@v15@@ ) ; gen_set_label ( @@v14@@ ) ; tcg_gen_movi_i32 ( cpu_R [ @@a2@@ ] , Number ) ; gen_set_label ( @@v15@@ ) ; return tcg_gen_movi_i64 ( cpu_exclusive_addr , Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r80\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v15\", \"t\": {\"T\": 3, \"t\": \"_BYTE\"}, \"location\": \"s64\"}, {\"n\": \"v14\", \"t\": {\"T\": 3, \"t\": \"_BYTE\"}, \"location\": \"s72\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STREX", "code": "__int64 __fastcall trans_STREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,368 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STREXD_a32", "code": "__int64 __fastcall trans_STREXD_a32 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@a2@@ [ Number ] = @@a2@@ [ Number ] + Number ; @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,369 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STREX\", \"code\": \"__int64 __fastcall trans_STREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_STREXD_t32", "code": "__int64 __fastcall trans_STREXD_t32 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,370 |
[
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STREX\", \"code\": \"__int64 __fastcall trans_STREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_STREXB", "code": "__int64 __fastcall trans_STREXB ( __int64 @@a1@@ , int * @@a2@@ ) { bool v2 ; __int64 result ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; else v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( v2 ) result = Number L ; else result = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,371 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STREX\", \"code\": \"__int64 __fastcall trans_STREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_STREXH", "code": "__int64 __fastcall trans_STREXH ( __int64 @@a1@@ , int * @@a2@@ ) { bool v2 ; __int64 result ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; else v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( v2 ) result = Number L ; else result = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,372 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STREX\", \"code\": \"__int64 __fastcall trans_STREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_STLEX", "code": "__int64 __fastcall trans_STLEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,373 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_STLEXD_a32", "code": "__int64 __fastcall trans_STLEXD_a32 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@a2@@ [ Number ] = @@a2@@ [ Number ] + Number ; @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,374 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STLEX\", \"code\": \"__int64 __fastcall trans_STLEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_STLEXD_t32", "code": "__int64 __fastcall trans_STLEXD_t32 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,375 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STLEX\", \"code\": \"__int64 __fastcall trans_STLEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_STLEXB", "code": "__int64 __fastcall trans_STLEXB ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,376 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STLEX\", \"code\": \"__int64 __fastcall trans_STLEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_STLEXH", "code": "__int64 __fastcall trans_STLEXH ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,377 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_strex\", \"code\": \"__int64 __fastcall op_strex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number ) || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_store_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STLEX\", \"code\": \"__int64 __fastcall trans_STLEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_strex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "op_stl", "code": "__int64 __fastcall op_stl ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; int v6 ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; tcg_gen_mb ( Number L ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , v5 , @@v4@@ ) ; v6 = * ( _DWORD * ) ( @@a2@@ + Number ) ; LOBYTE ( v6 ) = v6 | Number ; disas_set_da_iss ( @@a1@@ , @@a3@@ , v6 ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "v4", "t": {"T": 1, "n": "__int32", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STL"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,378 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"disas_set_da_iss\", \"code\": \"__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_STL", "code": "__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,379 |
[
"{\"name\": \"op_stl\", \"code\": \"__int64 __fastcall op_stl ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; int v6 ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; tcg_gen_mb ( Number L ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , v5 , @@v4@@ ) ; v6 = * ( _DWORD * ) ( @@a2@@ + Number ) ; LOBYTE ( v6 ) = v6 | Number ; disas_set_da_iss ( @@a1@@ , @@a3@@ , v6 ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}"
] |
{"name": "trans_STLB", "code": "__int64 __fastcall trans_STLB ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,380 |
[
"{\"name\": \"op_stl\", \"code\": \"__int64 __fastcall op_stl ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; int v6 ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; tcg_gen_mb ( Number L ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , v5 , @@v4@@ ) ; v6 = * ( _DWORD * ) ( @@a2@@ + Number ) ; LOBYTE ( v6 ) = v6 | Number ; disas_set_da_iss ( @@a1@@ , @@a3@@ , v6 ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_STLH", "code": "__int64 __fastcall trans_STLH ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_STL"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,381 |
[
"{\"name\": \"op_stl\", \"code\": \"__int64 __fastcall op_stl ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; int v6 ; __int64 @@v8@@ ; __int64 @@v9@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v9@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; tcg_gen_mb ( Number L ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , @@v9@@ , @@v8@@ , v5 , @@v4@@ ) ; v6 = * ( _DWORD * ) ( @@a2@@ + Number ) ; LOBYTE ( v6 ) = v6 | Number ; disas_set_da_iss ( @@a1@@ , @@a3@@ , v6 ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}",
"{\"name\": \"trans_STL\", \"code\": \"__int64 __fastcall trans_STL ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_stl ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "op_ldrex", "code": "__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "acq", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,382 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_local_new_i32\", \"code\": \"__int64 tcg_temp_local_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg_var\", \"code\": \"__int64 __fastcall load_reg_var ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v3@@ ; if ( @@a3@@ != Number ) return tcg_gen_mov_i32 ( @@a2@@ , cpu_R [ @@a3@@ ] ) ; @@v3@@ = read_pc ( @@a1@@ ) ; return tcg_gen_movi_i32 ( @@a2@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_load_exclusive\", \"code\": \"__int64 __fastcall gen_load_exclusive ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ , int @@a5@@ ) { int v5 ; int v6 ; unsigned int @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; @@v12@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | @@a5@@ | Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = Number ; if ( @@a5@@ == Number ) { @@v13@@ = tcg_temp_new_i32 ( ) ; @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = gen_aa32_addr ( @@a1@@ , @@a4@@ , @@v11@@ ) ; v5 = get_mem_index ( @@a1@@ ) ; tcg_gen_qemu_ld_i64 ( @@v14@@ , @@v15@@ , v5 , @@v11@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_gen_mov_i64 ( cpu_exclusive_val , @@v14@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) tcg_gen_extr_i64_i32 ( @@v13@@ , @@v12@@ , @@v14@@ ) ; else tcg_gen_extr_i64_i32 ( @@v12@@ , @@v13@@ , @@v14@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; store_reg ( @@a1@@ , @@a3@@ , @@v13@@ ) ; } else { v6 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v12@@ , @@a4@@ , v6 , @@v11@@ ) ; tcg_gen_extu_i32_i64 ( cpu_exclusive_val , @@v12@@ ) ; } store_reg ( @@a1@@ , @@a2@@ , @@v12@@ ) ; return tcg_gen_extu_i32_i64 ( cpu_exclusive_addr , @@a4@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDREX", "code": "__int64 __fastcall trans_LDREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,383 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_LDREXD_a32", "code": "__int64 __fastcall trans_LDREXD_a32 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@a2@@ [ Number ] = @@a2@@ [ Number ] + Number ; @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,384 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDREX\", \"code\": \"__int64 __fastcall trans_LDREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_LDREXD_t32", "code": "__int64 __fastcall trans_LDREXD_t32 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,385 |
[
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDREX\", \"code\": \"__int64 __fastcall trans_LDREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_LDREXB", "code": "__int64 __fastcall trans_LDREXB ( __int64 @@a1@@ , int * @@a2@@ ) { bool v2 ; __int64 result ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; else v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( v2 ) result = Number L ; else result = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,386 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDREX\", \"code\": \"__int64 __fastcall trans_LDREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_LDREXH", "code": "__int64 __fastcall trans_LDREXH ( __int64 @@a1@@ , int * @@a2@@ ) { bool v2 ; __int64 result ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; else v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( v2 ) result = Number L ; else result = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,387 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDREX\", \"code\": \"__int64 __fastcall trans_LDREX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_LDAEX", "code": "__int64 __fastcall trans_LDAEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,388 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_LDAEXD_a32", "code": "__int64 __fastcall trans_LDAEXD_a32 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@a2@@ [ Number ] = @@a2@@ [ Number ] + Number ; @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,389 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDAEX\", \"code\": \"__int64 __fastcall trans_LDAEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_LDAEXD_t32", "code": "__int64 __fastcall trans_LDAEXD_t32 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,390 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDAEX\", \"code\": \"__int64 __fastcall trans_LDAEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_LDAEXB", "code": "__int64 __fastcall trans_LDAEXB ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,391 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDAEX\", \"code\": \"__int64 __fastcall trans_LDAEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_LDAEXH", "code": "__int64 __fastcall trans_LDAEXH ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDREX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,392 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_ldrex\", \"code\": \"__int64 __fastcall op_ldrex ( __int64 @@a1@@ , int * @@a2@@ , int @@a3@@ , char @@a4@@ ) { bool v4 ; __int64 result ; __int64 @@v8@@ ; v4 = arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == Number || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number || @@a3@@ == Number && ( @@a2@@ [ Number ] == Number || @@a2@@ [ Number ] == @@a2@@ [ Number ] || ! v4 && * ( _DWORD * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v8@@ = tcg_temp_local_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v8@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , ( unsigned int ) * @@a2@@ ) ; gen_load_exclusive ( @@a1@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , @@v8@@ , @@a3@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_LDAEX\", \"code\": \"__int64 __fastcall trans_LDAEX ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_ldrex ( @@a1@@ , @@a2@@ , Number , Number ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "op_lda", "code": "__int64 __fastcall op_lda ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v7@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v7@@ , v5 , @@v4@@ ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , * ( _WORD * ) ( @@a2@@ + Number ) | Number ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , @@v8@@ ) ; tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}]}
|
[{"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "v4", "t": {"T": 1, "n": "__int32", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDA"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,393 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"disas_set_da_iss\", \"code\": \"__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_LDA", "code": "__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDA"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,394 |
[
"{\"name\": \"op_lda\", \"code\": \"__int64 __fastcall op_lda ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v7@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v7@@ , v5 , @@v4@@ ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , * ( _WORD * ) ( @@a2@@ + Number ) | Number ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , @@v8@@ ) ; tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}"
] |
{"name": "trans_LDAB", "code": "__int64 __fastcall trans_LDAB ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDA"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,395 |
[
"{\"name\": \"op_lda\", \"code\": \"__int64 __fastcall op_lda ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v7@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v7@@ , v5 , @@v4@@ ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , * ( _WORD * ) ( @@a2@@ + Number ) | Number ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , @@v8@@ ) ; tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_LDAH", "code": "__int64 __fastcall trans_LDAH ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_LDA"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,396 |
[
"{\"name\": \"op_lda\", \"code\": \"__int64 __fastcall op_lda ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { __int64 result ; int @@v4@@ ; int v5 ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a2@@ + Number ) == Number || * ( _DWORD * ) ( @@a2@@ + Number ) == Number ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v7@@ = load_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = @@a3@@ | * ( _DWORD * ) ( @@a1@@ + Number ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v7@@ , v5 , @@v4@@ ) ; disas_set_da_iss ( @@a1@@ , @@a3@@ , * ( _WORD * ) ( @@a2@@ + Number ) | Number ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * ( _DWORD * ) ( @@a2@@ + Number ) , @@v8@@ ) ; tcg_gen_mb ( Number L ) ; result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}",
"{\"name\": \"trans_LDA\", \"code\": \"__int64 __fastcall trans_LDA ( __int64 @@a1@@ , __int64 @@a2@@ ) { return op_lda ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_USADA8", "code": "__int64 __fastcall trans_USADA8 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@v3@@ ; __int64 v4 ; __int64 v5 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v4 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; gen_helper_usad8 ( @@v3@@ , @@v3@@ , v4 ) ; tcg_temp_free_i32 ( v4 ) ; if ( * @@a2@@ != Number ) { v5 = load_reg ( @@a1@@ , * @@a2@@ ) ; tcg_gen_add_i32 ( @@v3@@ , @@v3@@ , v5 ) ; tcg_temp_free_i32 ( v5 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_USADA8"}, "location": "r64"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,397 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_usad8\", \"code\": \"unsigned __int64 __fastcall gen_helper_usad8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usad8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_bfx", "code": "__int64 __fastcall op_bfx ( __int64 @@a1@@ , unsigned int * @@a2@@ , char @@a3@@ ) { __int64 @@result@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = @@a2@@ [ Number ] + Number ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( int ) ( @@v6@@ + @@v5@@ ) <= Number ) { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_extract_i32 ( @@v7@@ , @@v7@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_sextract_i32 ( @@v7@@ , @@v7@@ , @@v6@@ , @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; @@result@@ = Number L ; } else { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "u", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_UBFX"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "shift", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "width", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,398 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_SBFX", "code": "__int64 __fastcall trans_SBFX ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return op_bfx ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SBFX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,399 |
[
"{\"name\": \"op_bfx\", \"code\": \"__int64 __fastcall op_bfx ( __int64 @@a1@@ , unsigned int * @@a2@@ , char @@a3@@ ) { __int64 @@result@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = @@a2@@ [ Number ] + Number ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( int ) ( @@v6@@ + @@v5@@ ) <= Number ) { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_extract_i32 ( @@v7@@ , @@v7@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_sextract_i32 ( @@v7@@ , @@v7@@ , @@v6@@ , @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; @@result@@ = Number L ; } else { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SB\", \"code\": \"__int64 __fastcall trans_SB ( __int64 @@a1@@ ) { if ( ! isar_feature_aa32_sb ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; tcg_gen_mb ( Number L ) ; gen_goto_tb ( @@a1@@ , Number , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_UBFX", "code": "__int64 __fastcall trans_UBFX ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return op_bfx ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_UBFX"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,400 |
[
"{\"name\": \"op_bfx\", \"code\": \"__int64 __fastcall op_bfx ( __int64 @@a1@@ , unsigned int * @@a2@@ , char @@a3@@ ) { __int64 @@result@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = @@a2@@ [ Number ] + Number ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( int ) ( @@v6@@ + @@v5@@ ) <= Number ) { @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) tcg_gen_extract_i32 ( @@v7@@ , @@v7@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_sextract_i32 ( @@v7@@ , @@v7@@ , @@v6@@ , @@v5@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; @@result@@ = Number L ; } else { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_BFCI", "code": "__int64 __fastcall trans_BFCI ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@result@@ ; int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; @@v3@@ = @@a2@@ [ Number ] ; @@v4@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( @@v3@@ >= ( int ) @@v4@@ ) { if ( @@a2@@ [ Number ] == Number ) @@v5@@ = tcg_const_i32 ( Number L ) ; else @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@v3@@ - @@v4@@ != Number ) { @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_deposit_i32 ( @@v5@@ , @@v6@@ , @@v5@@ , @@v4@@ , @@v3@@ - @@v4@@ + Number ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; @@result@@ = Number L ; } else { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BFCI"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "lsb", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "msb", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,401 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_UDF", "code": "__int64 __fastcall trans_UDF ( __int64 @@a1@@ ) { unallocated_encoding ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,402 |
[
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "op_par_addsub", "code": "__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "gen", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "t0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,403 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_par_addsub_ge", "code": "__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64, __int64)"}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "gen", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr)"}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "ge", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,404 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_ptr\", \"code\": \"__int64 tcg_temp_new_ptr ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_ptr ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_addi_ptr\", \"code\": \"__int64 __fastcall tcg_gen_addi_ptr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_addi_i64 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SADD16", "code": "__int64 __fastcall trans_SADD16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_sadd16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,405 |
[
"{\"name\": \"gen_helper_sadd16\", \"code\": \"unsigned __int64 __fastcall gen_helper_sadd16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sadd16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SASX", "code": "__int64 __fastcall trans_SASX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_saddsubx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,406 |
[
"{\"name\": \"gen_helper_saddsubx\", \"code\": \"unsigned __int64 __fastcall gen_helper_saddsubx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_saddsubx , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SSAX", "code": "__int64 __fastcall trans_SSAX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_ssubaddx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,407 |
[
"{\"name\": \"gen_helper_ssubaddx\", \"code\": \"unsigned __int64 __fastcall gen_helper_ssubaddx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ssubaddx , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SSUB16", "code": "__int64 __fastcall trans_SSUB16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_ssub16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,408 |
[
"{\"name\": \"gen_helper_ssub16\", \"code\": \"unsigned __int64 __fastcall gen_helper_ssub16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ssub16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SADD8", "code": "__int64 __fastcall trans_SADD8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_sadd8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,409 |
[
"{\"name\": \"gen_helper_sadd8\", \"code\": \"unsigned __int64 __fastcall gen_helper_sadd8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sadd8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SSUB8", "code": "__int64 __fastcall trans_SSUB8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_ssub8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,410 |
[
"{\"name\": \"gen_helper_ssub8\", \"code\": \"unsigned __int64 __fastcall gen_helper_ssub8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ssub8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UADD16", "code": "__int64 __fastcall trans_UADD16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_uadd16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,411 |
[
"{\"name\": \"gen_helper_uadd16\", \"code\": \"unsigned __int64 __fastcall gen_helper_uadd16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uadd16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UASX", "code": "__int64 __fastcall trans_UASX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_uaddsubx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,412 |
[
"{\"name\": \"gen_helper_uaddsubx\", \"code\": \"unsigned __int64 __fastcall gen_helper_uaddsubx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uaddsubx , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_USAX", "code": "__int64 __fastcall trans_USAX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_usubaddx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,413 |
[
"{\"name\": \"gen_helper_usubaddx\", \"code\": \"unsigned __int64 __fastcall gen_helper_usubaddx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usubaddx , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_USUB16", "code": "__int64 __fastcall trans_USUB16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_usub16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,414 |
[
"{\"name\": \"gen_helper_usub16\", \"code\": \"unsigned __int64 __fastcall gen_helper_usub16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usub16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UADD8", "code": "__int64 __fastcall trans_UADD8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_uadd8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,415 |
[
"{\"name\": \"gen_helper_uadd8\", \"code\": \"unsigned __int64 __fastcall gen_helper_uadd8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uadd8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_USUB8", "code": "__int64 __fastcall trans_USUB8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub_ge ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_usub8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,416 |
[
"{\"name\": \"gen_helper_usub8\", \"code\": \"unsigned __int64 __fastcall gen_helper_usub8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usub8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub_ge\", \"code\": \"__int64 __fastcall op_par_addsub_ge ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = tcg_temp_new_ptr ( ) ; tcg_gen_addi_ptr ( @@v8@@ , cpu_env , Number L ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QADD16", "code": "__int64 __fastcall trans_QADD16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_qadd16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,417 |
[
"{\"name\": \"gen_helper_qadd16\", \"code\": \"unsigned __int64 __fastcall gen_helper_qadd16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_qadd16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_QADD\", \"code\": \"__int64 __fastcall trans_QADD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QASX", "code": "__int64 __fastcall trans_QASX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_qaddsubx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,418 |
[
"{\"name\": \"gen_helper_qaddsubx\", \"code\": \"unsigned __int64 __fastcall gen_helper_qaddsubx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_qaddsubx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QSAX", "code": "__int64 __fastcall trans_QSAX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_qsubaddx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,419 |
[
"{\"name\": \"gen_helper_qsubaddx\", \"code\": \"unsigned __int64 __fastcall gen_helper_qsubaddx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_qsubaddx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QSUB16", "code": "__int64 __fastcall trans_QSUB16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_qsub16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,420 |
[
"{\"name\": \"gen_helper_qsub16\", \"code\": \"unsigned __int64 __fastcall gen_helper_qsub16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_qsub16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_QSUB\", \"code\": \"__int64 __fastcall trans_QSUB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
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