code
stringlengths 0
23.9M
|
|---|
/* SPDX-License-Identifier: GPL-2.0-only */
/******************************************************************************
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* Contact Information:
* Intel Linux Wireless <[email protected]>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*
*****************************************************************************/
#ifndef __il_4965_h__
#define __il_4965_h__
struct il_rx_queue;
struct il_rx_buf;
struct il_rx_pkt;
struct il_tx_queue;
struct il_rxon_context;
/* configuration for the _4965 devices */
extern struct il_cfg il4965_cfg;
extern const struct il_ops il4965_ops;
extern struct il_mod_params il4965_mod_params;
/* tx queue */
void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid,
int freed);
/* RXON */
void il4965_set_rxon_chain(struct il_priv *il);
/* uCode */
int il4965_verify_ucode(struct il_priv *il);
/* lib */
void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status);
void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
int il4965_hw_nic_init(struct il_priv *il);
int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
void il4965_nic_config(struct il_priv *il);
/* rx */
void il4965_rx_queue_restock(struct il_priv *il);
void il4965_rx_replenish(struct il_priv *il);
void il4965_rx_replenish_now(struct il_priv *il);
void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
int il4965_rxq_stop(struct il_priv *il);
int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum nl80211_band band);
void il4965_rx_handle(struct il_priv *il);
/* tx */
void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
dma_addr_t addr, u16 len, u8 reset, u8 pad);
int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
struct ieee80211_tx_info *info);
int il4965_tx_skb(struct il_priv *il,
struct ieee80211_sta *sta,
struct sk_buff *skb);
int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid, u16 * ssn);
int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid);
int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id);
int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
void il4965_hw_txq_ctx_free(struct il_priv *il);
int il4965_txq_ctx_alloc(struct il_priv *il);
void il4965_txq_ctx_reset(struct il_priv *il);
void il4965_txq_ctx_stop(struct il_priv *il);
void il4965_txq_set_sched(struct il_priv *il, u32 mask);
/*
* Acquire il->lock before calling this function !
*/
void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
/**
* il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
* @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
* @scd_retry: (1) Indicates queue will be used in aggregation mode
*
* NOTE: Acquire il->lock before calling this function !
*/
void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
int tx_fifo_id, int scd_retry);
/* scan */
int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
/* station mgmt */
int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
bool add);
/* hcmd */
int il4965_send_beacon_cmd(struct il_priv *il);
#ifdef CONFIG_IWLEGACY_DEBUG
const char *il4965_get_tx_fail_reason(u32 status);
#else
static inline const char *
il4965_get_tx_fail_reason(u32 status)
{
return "";
}
#endif
/* station management */
int il4965_alloc_bcast_station(struct il_priv *il);
int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r);
int il4965_remove_default_wep_key(struct il_priv *il,
struct ieee80211_key_conf *key);
int il4965_set_default_wep_key(struct il_priv *il,
struct ieee80211_key_conf *key);
int il4965_restore_default_wep_keys(struct il_priv *il);
int il4965_set_dynamic_key(struct il_priv *il,
struct ieee80211_key_conf *key, u8 sta_id);
int il4965_remove_dynamic_key(struct il_priv *il,
struct ieee80211_key_conf *key, u8 sta_id);
void il4965_update_tkip_key(struct il_priv *il,
struct ieee80211_key_conf *keyconf,
struct ieee80211_sta *sta, u32 iv32,
u16 *phase1key);
int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid);
int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
int tid, u16 ssn);
int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
int tid);
void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt);
int il4965_update_bcast_stations(struct il_priv *il);
/* rate */
static inline u8
il4965_hw_get_rate(__le32 rate_n_flags)
{
return le32_to_cpu(rate_n_flags) & 0xFF;
}
/* eeprom */
void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac);
int il4965_eeprom_acquire_semaphore(struct il_priv *il);
void il4965_eeprom_release_semaphore(struct il_priv *il);
int il4965_eeprom_check_version(struct il_priv *il);
/* mac80211 handlers (for 4965) */
void il4965_mac_tx(struct ieee80211_hw *hw,
struct ieee80211_tx_control *control,
struct sk_buff *skb);
int il4965_mac_start(struct ieee80211_hw *hw);
void il4965_mac_stop(struct ieee80211_hw *hw, bool suspend);
void il4965_configure_filter(struct ieee80211_hw *hw,
unsigned int changed_flags,
unsigned int *total_flags, u64 multicast);
int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
struct ieee80211_vif *vif, struct ieee80211_sta *sta,
struct ieee80211_key_conf *key);
void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_key_conf *keyconf,
struct ieee80211_sta *sta, u32 iv32,
u16 *phase1key);
int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_ampdu_params *params);
int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta);
void
il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_channel_switch *ch_switch);
void il4965_led_enable(struct il_priv *il);
/* EEPROM */
#define IL4965_EEPROM_IMG_SIZE 1024
/*
* uCode queue management definitions ...
* The first queue used for block-ack aggregation is #7 (4965 only).
* All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
*/
#define IL49_FIRST_AMPDU_QUEUE 7
/* Sizes and addresses for instruction and data memory (SRAM) in
* 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
#define IL49_RTC_INST_LOWER_BOUND (0x000000)
#define IL49_RTC_INST_UPPER_BOUND (0x018000)
#define IL49_RTC_DATA_LOWER_BOUND (0x800000)
#define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
#define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
IL49_RTC_INST_LOWER_BOUND)
#define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
IL49_RTC_DATA_LOWER_BOUND)
#define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
#define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
/* Size of uCode instruction memory in bootstrap state machine */
#define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
static inline int
il4965_hw_valid_rtc_data_addr(u32 addr)
{
return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
addr < IL49_RTC_DATA_UPPER_BOUND);
}
/********************* START TEMPERATURE *************************************/
/**
* 4965 temperature calculation.
*
* The driver must calculate the device temperature before calculating
* a txpower setting (amplifier gain is temperature dependent). The
* calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
* values used for the life of the driver, and one of which (R4) is the
* real-time temperature indicator.
*
* uCode provides all 4 values to the driver via the "initialize alive"
* notification (see struct il4965_init_alive_resp). After the runtime uCode
* image loads, uCode updates the R4 value via stats notifications
* (see N_STATS), which occur after each received beacon
* when associated, or can be requested via C_STATS.
*
* NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
* must sign-extend to 32 bits before applying formula below.
*
* Formula:
*
* degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
*
* NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
* an additional correction, which should be centered around 0 degrees
* Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
* centering the 97/100 correction around 0 degrees K.
*
* Add 273 to Kelvin value to find degrees Celsius, for comparing current
* temperature with factory-measured temperatures when calculating txpower
* settings.
*/
#define TEMPERATURE_CALIB_KELVIN_OFFSET 8
#define TEMPERATURE_CALIB_A_VAL 259
/* Limit range of calculated temperature to be between these Kelvin values */
#define IL_TX_POWER_TEMPERATURE_MIN (263)
#define IL_TX_POWER_TEMPERATURE_MAX (410)
#define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
((t) < IL_TX_POWER_TEMPERATURE_MIN || \
(t) > IL_TX_POWER_TEMPERATURE_MAX)
void il4965_temperature_calib(struct il_priv *il);
/********************* END TEMPERATURE ***************************************/
/********************* START TXPOWER *****************************************/
/**
* 4965 txpower calculations rely on information from three sources:
*
* 1) EEPROM
* 2) "initialize" alive notification
* 3) stats notifications
*
* EEPROM data consists of:
*
* 1) Regulatory information (max txpower and channel usage flags) is provided
* separately for each channel that can possibly supported by 4965.
* 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
* (legacy) channels.
*
* See struct il4965_eeprom_channel for format, and struct il4965_eeprom
* for locations in EEPROM.
*
* 2) Factory txpower calibration information is provided separately for
* sub-bands of contiguous channels. 2.4GHz has just one sub-band,
* but 5 GHz has several sub-bands.
*
* In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
*
* See struct il4965_eeprom_calib_info (and the tree of structures
* contained within it) for format, and struct il4965_eeprom for
* locations in EEPROM.
*
* "Initialization alive" notification (see struct il4965_init_alive_resp)
* consists of:
*
* 1) Temperature calculation parameters.
*
* 2) Power supply voltage measurement.
*
* 3) Tx gain compensation to balance 2 transmitters for MIMO use.
*
* Statistics notifications deliver:
*
* 1) Current values for temperature param R4.
*/
/**
* To calculate a txpower setting for a given desired target txpower, channel,
* modulation bit rate, and transmitter chain (4965 has 2 transmitters to
* support MIMO and transmit diversity), driver must do the following:
*
* 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
* Do not exceed regulatory limit; reduce target txpower if necessary.
*
* If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
* 2 transmitters will be used simultaneously; driver must reduce the
* regulatory limit by 3 dB (half-power) for each transmitter, so the
* combined total output of the 2 transmitters is within regulatory limits.
*
*
* 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
* backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
* reduce target txpower if necessary.
*
* Backoff values below are in 1/2 dB units (equivalent to steps in
* txpower gain tables):
*
* OFDM 6 - 36 MBit: 10 steps (5 dB)
* OFDM 48 MBit: 15 steps (7.5 dB)
* OFDM 54 MBit: 17 steps (8.5 dB)
* OFDM 60 MBit: 20 steps (10 dB)
* CCK all rates: 10 steps (5 dB)
*
* Backoff values apply to saturation txpower on a per-transmitter basis;
* when using MIMO (2 transmitters), each transmitter uses the same
* saturation level provided in EEPROM, and the same backoff values;
* no reduction (such as with regulatory txpower limits) is required.
*
* Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
* widths and 40 Mhz (.11n HT40) channel widths; there is no separate
* factory measurement for ht40 channels.
*
* The result of this step is the final target txpower. The rest of
* the steps figure out the proper settings for the device to achieve
* that target txpower.
*
*
* 3) Determine (EEPROM) calibration sub band for the target channel, by
* comparing against first and last channels in each sub band
* (see struct il4965_eeprom_calib_subband_info).
*
*
* 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
* referencing the 2 factory-measured (sample) channels within the sub band.
*
* Interpolation is based on difference between target channel's frequency
* and the sample channels' frequencies. Since channel numbers are based
* on frequency (5 MHz between each channel number), this is equivalent
* to interpolating based on channel number differences.
*
* Note that the sample channels may or may not be the channels at the
* edges of the sub band. The target channel may be "outside" of the
* span of the sampled channels.
*
* Driver may choose the pair (for 2 Tx chains) of measurements (see
* struct il4965_eeprom_calib_ch_info) for which the actual measured
* txpower comes closest to the desired txpower. Usually, though,
* the middle set of measurements is closest to the regulatory limits,
* and is therefore a good choice for all txpower calculations (this
* assumes that high accuracy is needed for maximizing legal txpower,
* while lower txpower configurations do not need as much accuracy).
*
* Driver should interpolate both members of the chosen measurement pair,
* i.e. for both Tx chains (radio transmitters), unless the driver knows
* that only one of the chains will be used (e.g. only one tx antenna
* connected, but this should be unusual). The rate scaling algorithm
* switches antennas to find best performance, so both Tx chains will
* be used (although only one at a time) even for non-MIMO transmissions.
*
* Driver should interpolate factory values for temperature, gain table
* idx, and actual power. The power amplifier detector values are
* not used by the driver.
*
* Sanity check: If the target channel happens to be one of the sample
* channels, the results should agree with the sample channel's
* measurements!
*
*
* 5) Find difference between desired txpower and (interpolated)
* factory-measured txpower. Using (interpolated) factory gain table idx
* (shown elsewhere) as a starting point, adjust this idx lower to
* increase txpower, or higher to decrease txpower, until the target
* txpower is reached. Each step in the gain table is 1/2 dB.
*
* For example, if factory measured txpower is 16 dBm, and target txpower
* is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
* by 3 dB.
*
*
* 6) Find difference between current device temperature and (interpolated)
* factory-measured temperature for sub-band. Factory values are in
* degrees Celsius. To calculate current temperature, see comments for
* "4965 temperature calculation".
*
* If current temperature is higher than factory temperature, driver must
* increase gain (lower gain table idx), and vice verse.
*
* Temperature affects gain differently for different channels:
*
* 2.4 GHz all channels: 3.5 degrees per half-dB step
* 5 GHz channels 34-43: 4.5 degrees per half-dB step
* 5 GHz channels >= 44: 4.0 degrees per half-dB step
*
* NOTE: Temperature can increase rapidly when transmitting, especially
* with heavy traffic at high txpowers. Driver should update
* temperature calculations often under these conditions to
* maintain strong txpower in the face of rising temperature.
*
*
* 7) Find difference between current power supply voltage indicator
* (from "initialize alive") and factory-measured power supply voltage
* indicator (EEPROM).
*
* If the current voltage is higher (indicator is lower) than factory
* voltage, gain should be reduced (gain table idx increased) by:
*
* (eeprom - current) / 7
*
* If the current voltage is lower (indicator is higher) than factory
* voltage, gain should be increased (gain table idx decreased) by:
*
* 2 * (current - eeprom) / 7
*
* If number of idx steps in either direction turns out to be > 2,
* something is wrong ... just use 0.
*
* NOTE: Voltage compensation is independent of band/channel.
*
* NOTE: "Initialize" uCode measures current voltage, which is assumed
* to be constant after this initial measurement. Voltage
* compensation for txpower (number of steps in gain table)
* may be calculated once and used until the next uCode bootload.
*
*
* 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
* adjust txpower for each transmitter chain, so txpower is balanced
* between the two chains. There are 5 pairs of tx_atten[group][chain]
* values in "initialize alive", one pair for each of 5 channel ranges:
*
* Group 0: 5 GHz channel 34-43
* Group 1: 5 GHz channel 44-70
* Group 2: 5 GHz channel 71-124
* Group 3: 5 GHz channel 125-200
* Group 4: 2.4 GHz all channels
*
* Add the tx_atten[group][chain] value to the idx for the target chain.
* The values are signed, but are in pairs of 0 and a non-negative number,
* so as to reduce gain (if necessary) of the "hotter" channel. This
* avoids any need to double-check for regulatory compliance after
* this step.
*
*
* 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
* value to the idx:
*
* Hardware rev B: 9 steps (4.5 dB)
* Hardware rev C: 5 steps (2.5 dB)
*
* Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
* bits [3:2], 1 = B, 2 = C.
*
* NOTE: This compensation is in addition to any saturation backoff that
* might have been applied in an earlier step.
*
*
* 10) Select the gain table, based on band (2.4 vs 5 GHz).
*
* Limit the adjusted idx to stay within the table!
*
*
* 11) Read gain table entries for DSP and radio gain, place into appropriate
* location(s) in command (struct il4965_txpowertable_cmd).
*/
/**
* When MIMO is used (2 transmitters operating simultaneously), driver should
* limit each transmitter to deliver a max of 3 dB below the regulatory limit
* for the device. That is, use half power for each transmitter, so total
* txpower is within regulatory limits.
*
* The value "6" represents number of steps in gain table to reduce power 3 dB.
* Each step is 1/2 dB.
*/
#define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
/**
* CCK gain compensation.
*
* When calculating txpowers for CCK, after making sure that the target power
* is within regulatory and saturation limits, driver must additionally
* back off gain by adding these values to the gain table idx.
*
* Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
* bits [3:2], 1 = B, 2 = C.
*/
#define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
#define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
/*
* 4965 power supply voltage compensation for txpower
*/
#define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
/**
* Gain tables.
*
* The following tables contain pair of values for setting txpower, i.e.
* gain settings for the output of the device's digital signal processor (DSP),
* and for the analog gain structure of the transmitter.
*
* Each entry in the gain tables represents a step of 1/2 dB. Note that these
* are *relative* steps, not indications of absolute output power. Output
* power varies with temperature, voltage, and channel frequency, and also
* requires consideration of average power (to satisfy regulatory constraints),
* and peak power (to avoid distortion of the output signal).
*
* Each entry contains two values:
* 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
* linear value that multiplies the output of the digital signal processor,
* before being sent to the analog radio.
* 2) Radio gain. This sets the analog gain of the radio Tx path.
* It is a coarser setting, and behaves in a logarithmic (dB) fashion.
*
* EEPROM contains factory calibration data for txpower. This maps actual
* measured txpower levels to gain settings in the "well known" tables
* below ("well-known" means here that both factory calibration *and* the
* driver work with the same table).
*
* There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
* has an extension (into negative idxes), in case the driver needs to
* boost power setting for high device temperatures (higher than would be
* present during factory calibration). A 5 Ghz EEPROM idx of "40"
* corresponds to the 49th entry in the table used by the driver.
*/
#define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */
#define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
/**
* 2.4 GHz gain table
*
* Index Dsp gain Radio gain
* 0 110 0x3f (highest gain)
* 1 104 0x3f
* 2 98 0x3f
* 3 110 0x3e
* 4 104 0x3e
* 5 98 0x3e
* 6 110 0x3d
* 7 104 0x3d
* 8 98 0x3d
* 9 110 0x3c
* 10 104 0x3c
* 11 98 0x3c
* 12 110 0x3b
* 13 104 0x3b
* 14 98 0x3b
* 15 110 0x3a
* 16 104 0x3a
* 17 98 0x3a
* 18 110 0x39
* 19 104 0x39
* 20 98 0x39
* 21 110 0x38
* 22 104 0x38
* 23 98 0x38
* 24 110 0x37
* 25 104 0x37
* 26 98 0x37
* 27 110 0x36
* 28 104 0x36
* 29 98 0x36
* 30 110 0x35
* 31 104 0x35
* 32 98 0x35
* 33 110 0x34
* 34 104 0x34
* 35 98 0x34
* 36 110 0x33
* 37 104 0x33
* 38 98 0x33
* 39 110 0x32
* 40 104 0x32
* 41 98 0x32
* 42 110 0x31
* 43 104 0x31
* 44 98 0x31
* 45 110 0x30
* 46 104 0x30
* 47 98 0x30
* 48 110 0x6
* 49 104 0x6
* 50 98 0x6
* 51 110 0x5
* 52 104 0x5
* 53 98 0x5
* 54 110 0x4
* 55 104 0x4
* 56 98 0x4
* 57 110 0x3
* 58 104 0x3
* 59 98 0x3
* 60 110 0x2
* 61 104 0x2
* 62 98 0x2
* 63 110 0x1
* 64 104 0x1
* 65 98 0x1
* 66 110 0x0
* 67 104 0x0
* 68 98 0x0
* 69 97 0
* 70 96 0
* 71 95 0
* 72 94 0
* 73 93 0
* 74 92 0
* 75 91 0
* 76 90 0
* 77 89 0
* 78 88 0
* 79 87 0
* 80 86 0
* 81 85 0
* 82 84 0
* 83 83 0
* 84 82 0
* 85 81 0
* 86 80 0
* 87 79 0
* 88 78 0
* 89 77 0
* 90 76 0
* 91 75 0
* 92 74 0
* 93 73 0
* 94 72 0
* 95 71 0
* 96 70 0
* 97 69 0
* 98 68 0
*/
/**
* 5 GHz gain table
*
* Index Dsp gain Radio gain
* -9 123 0x3F (highest gain)
* -8 117 0x3F
* -7 110 0x3F
* -6 104 0x3F
* -5 98 0x3F
* -4 110 0x3E
* -3 104 0x3E
* -2 98 0x3E
* -1 110 0x3D
* 0 104 0x3D
* 1 98 0x3D
* 2 110 0x3C
* 3 104 0x3C
* 4 98 0x3C
* 5 110 0x3B
* 6 104 0x3B
* 7 98 0x3B
* 8 110 0x3A
* 9 104 0x3A
* 10 98 0x3A
* 11 110 0x39
* 12 104 0x39
* 13 98 0x39
* 14 110 0x38
* 15 104 0x38
* 16 98 0x38
* 17 110 0x37
* 18 104 0x37
* 19 98 0x37
* 20 110 0x36
* 21 104 0x36
* 22 98 0x36
* 23 110 0x35
* 24 104 0x35
* 25 98 0x35
* 26 110 0x34
* 27 104 0x34
* 28 98 0x34
* 29 110 0x33
* 30 104 0x33
* 31 98 0x33
* 32 110 0x32
* 33 104 0x32
* 34 98 0x32
* 35 110 0x31
* 36 104 0x31
* 37 98 0x31
* 38 110 0x30
* 39 104 0x30
* 40 98 0x30
* 41 110 0x25
* 42 104 0x25
* 43 98 0x25
* 44 110 0x24
* 45 104 0x24
* 46 98 0x24
* 47 110 0x23
* 48 104 0x23
* 49 98 0x23
* 50 110 0x22
* 51 104 0x18
* 52 98 0x18
* 53 110 0x17
* 54 104 0x17
* 55 98 0x17
* 56 110 0x16
* 57 104 0x16
* 58 98 0x16
* 59 110 0x15
* 60 104 0x15
* 61 98 0x15
* 62 110 0x14
* 63 104 0x14
* 64 98 0x14
* 65 110 0x13
* 66 104 0x13
* 67 98 0x13
* 68 110 0x12
* 69 104 0x08
* 70 98 0x08
* 71 110 0x07
* 72 104 0x07
* 73 98 0x07
* 74 110 0x06
* 75 104 0x06
* 76 98 0x06
* 77 110 0x05
* 78 104 0x05
* 79 98 0x05
* 80 110 0x04
* 81 104 0x04
* 82 98 0x04
* 83 110 0x03
* 84 104 0x03
* 85 98 0x03
* 86 110 0x02
* 87 104 0x02
* 88 98 0x02
* 89 110 0x01
* 90 104 0x01
* 91 98 0x01
* 92 110 0x00
* 93 104 0x00
* 94 98 0x00
* 95 93 0x00
* 96 88 0x00
* 97 83 0x00
* 98 78 0x00
*/
/**
* Sanity checks and default values for EEPROM regulatory levels.
* If EEPROM values fall outside MIN/MAX range, use default values.
*
* Regulatory limits refer to the maximum average txpower allowed by
* regulatory agencies in the geographies in which the device is meant
* to be operated. These limits are SKU-specific (i.e. geography-specific),
* and channel-specific; each channel has an individual regulatory limit
* listed in the EEPROM.
*
* Units are in half-dBm (i.e. "34" means 17 dBm).
*/
#define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
#define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
#define IL_TX_POWER_REGULATORY_MIN (0)
#define IL_TX_POWER_REGULATORY_MAX (34)
/**
* Sanity checks and default values for EEPROM saturation levels.
* If EEPROM values fall outside MIN/MAX range, use default values.
*
* Saturation is the highest level that the output power amplifier can produce
* without significant clipping distortion. This is a "peak" power level.
* Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
* require differing amounts of backoff, relative to their average power output,
* in order to avoid clipping distortion.
*
* Driver must make sure that it is violating neither the saturation limit,
* nor the regulatory limit, when calculating Tx power settings for various
* rates.
*
* Units are in half-dBm (i.e. "38" means 19 dBm).
*/
#define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
#define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
#define IL_TX_POWER_SATURATION_MIN (20)
#define IL_TX_POWER_SATURATION_MAX (50)
/**
* Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
* and thermal Txpower calibration.
*
* When calculating txpower, driver must compensate for current device
* temperature; higher temperature requires higher gain. Driver must calculate
* current temperature (see "4965 temperature calculation"), then compare vs.
* factory calibration temperature in EEPROM; if current temperature is higher
* than factory temperature, driver must *increase* gain by proportions shown
* in table below. If current temperature is lower than factory, driver must
* *decrease* gain.
*
* Different frequency ranges require different compensation, as shown below.
*/
/* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
#define CALIB_IL_TX_ATTEN_GR1_FCH 34
#define CALIB_IL_TX_ATTEN_GR1_LCH 43
/* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
#define CALIB_IL_TX_ATTEN_GR2_FCH 44
#define CALIB_IL_TX_ATTEN_GR2_LCH 70
/* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
#define CALIB_IL_TX_ATTEN_GR3_FCH 71
#define CALIB_IL_TX_ATTEN_GR3_LCH 124
/* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
#define CALIB_IL_TX_ATTEN_GR4_FCH 125
#define CALIB_IL_TX_ATTEN_GR4_LCH 200
/* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
#define CALIB_IL_TX_ATTEN_GR5_FCH 1
#define CALIB_IL_TX_ATTEN_GR5_LCH 20
enum {
CALIB_CH_GROUP_1 = 0,
CALIB_CH_GROUP_2 = 1,
CALIB_CH_GROUP_3 = 2,
CALIB_CH_GROUP_4 = 3,
CALIB_CH_GROUP_5 = 4,
CALIB_CH_GROUP_MAX
};
/********************* END TXPOWER *****************************************/
/**
* Tx/Rx Queues
*
* Most communication between driver and 4965 is via queues of data buffers.
* For example, all commands that the driver issues to device's embedded
* controller (uCode) are via the command queue (one of the Tx queues). All
* uCode command responses/replies/notifications, including Rx frames, are
* conveyed from uCode to driver via the Rx queue.
*
* Most support for these queues, including handshake support, resides in
* structures in host DRAM, shared between the driver and the device. When
* allocating this memory, the driver must make sure that data written by
* the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
* cache memory), so DRAM and cache are consistent, and the device can
* immediately see changes made by the driver.
*
* 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
* up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
* in DRAM containing 256 Transmit Frame Descriptors (TFDs).
*/
#define IL49_NUM_FIFOS 7
#define IL49_CMD_FIFO_NUM 4
#define IL49_NUM_QUEUES 16
#define IL49_NUM_AMPDU_QUEUES 8
/**
* struct il4965_schedq_bc_tbl
*
* Byte Count table
*
* Each Tx queue uses a byte-count table containing 320 entries:
* one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
* duplicate the first 64 entries (to avoid wrap-around within a Tx win;
* max Tx win is 64 TFDs).
*
* When driver sets up a new TFD, it must also enter the total byte count
* of the frame to be transmitted into the corresponding entry in the byte
* count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
* must duplicate the byte count entry in corresponding idx 256-319.
*
* padding puts each byte count table on a 1024-byte boundary;
* 4965 assumes tables are separated by 1024 bytes.
*/
struct il4965_scd_bc_tbl {
__le16 tfd_offset[TFD_QUEUE_BC_SIZE];
u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
} __packed;
#define IL4965_RTC_INST_LOWER_BOUND (0x000000)
/* RSSI to dBm */
#define IL4965_RSSI_OFFSET 44
/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT 0x041
#define IL4965_DEFAULT_TX_RETRY 15
/* EEPROM */
#define IL4965_FIRST_AMPDU_QUEUE 10
/* Calibration */
void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
void il4965_init_sensitivity(struct il_priv *il);
void il4965_reset_run_time_calib(struct il_priv *il);
/* Debug */
#ifdef CONFIG_IWLEGACY_DEBUGFS
extern const struct il_debugfs_ops il4965_debugfs_ops;
#endif
/****************************/
/* Flow Handler Definitions */
/****************************/
/**
* This I/O area is directly read/writable by driver (e.g. Linux uses writel())
* Addresses are offsets from device's PCI hardware base address.
*/
#define FH49_MEM_LOWER_BOUND (0x1000)
#define FH49_MEM_UPPER_BOUND (0x2000)
/**
* Keep-Warm (KW) buffer base address.
*
* Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
* host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
* DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
* from going into a power-savings mode that would cause higher DRAM latency,
* and possible data over/under-runs, before all Tx/Rx is complete.
*
* Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
* of the buffer, which must be 4K aligned. Once this is set up, the 4965
* automatically invokes keep-warm accesses when normal accesses might not
* be sufficient to maintain fast DRAM response.
*
* Bit fields:
* 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
*/
#define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
/**
* TFD Circular Buffers Base (CBBC) addresses
*
* 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
* circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
* (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
* bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
* aligned (address bits 0-7 must be 0).
*
* Bit fields in each pointer register:
* 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
*/
#define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
#define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
/* Find TFD CB base pointer for given queue (range 0-15). */
#define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
/**
* Rx SRAM Control and Status Registers (RSCSR)
*
* These registers provide handshake between driver and 4965 for the Rx queue
* (this queue handles *all* command responses, notifications, Rx data, etc.
* sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
* queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
* concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
* Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
* mapping between RBDs and RBs.
*
* Driver must allocate host DRAM memory for the following, and set the
* physical address of each into 4965 registers:
*
* 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
* entries (although any power of 2, up to 4096, is selectable by driver).
* Each entry (1 dword) points to a receive buffer (RB) of consistent size
* (typically 4K, although 8K or 16K are also selectable by driver).
* Driver sets up RB size and number of RBDs in the CB via Rx config
* register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
*
* Bit fields within one RBD:
* 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
*
* Driver sets physical address [35:8] of base of RBD circular buffer
* into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
*
* 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
* (RBs) have been filled, via a "write pointer", actually the idx of
* the RB's corresponding RBD within the circular buffer. Driver sets
* physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
*
* Bit fields in lower dword of Rx status buffer (upper dword not used
* by driver; see struct il4965_shared, val0):
* 31-12: Not used by driver
* 11- 0: Index of last filled Rx buffer descriptor
* (4965 writes, driver reads this value)
*
* As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
* enter pointers to these RBs into contiguous RBD circular buffer entries,
* and update the 4965's "write" idx register,
* FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
*
* This "write" idx corresponds to the *next* RBD that the driver will make
* available, i.e. one RBD past the tail of the ready-to-fill RBDs within
* the circular buffer. This value should initially be 0 (before preparing any
* RBs), should be 8 after preparing the first 8 RBs (for example), and must
* wrap back to 0 at the end of the circular buffer (but don't wrap before
* "read" idx has advanced past 1! See below).
* NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
*
* As the 4965 fills RBs (referenced from contiguous RBDs within the circular
* buffer), it updates the Rx status buffer in host DRAM, 2) described above,
* to tell the driver the idx of the latest filled RBD. The driver must
* read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
*
* The driver must also internally keep track of a third idx, which is the
* next RBD to process. When receiving an Rx interrupt, driver should process
* all filled but unprocessed RBs up to, but not including, the RB
* corresponding to the "read" idx. For example, if "read" idx becomes "1",
* driver may process the RB pointed to by RBD 0. Depending on volume of
* traffic, there may be many RBs to process.
*
* If read idx == write idx, 4965 thinks there is no room to put new data.
* Due to this, the maximum number of filled RBs is 255, instead of 256. To
* be safe, make sure that there is a gap of at least 2 RBDs between "write"
* and "read" idxes; that is, make sure that there are no more than 254
* buffers waiting to be filled.
*/
#define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
#define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
#define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
/**
* Physical base address of 8-byte Rx Status buffer.
* Bit fields:
* 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
*/
#define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
/**
* Physical base address of Rx Buffer Descriptor Circular Buffer.
* Bit fields:
* 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
*/
#define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
/**
* Rx write pointer (idx, really!).
* Bit fields:
* 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
* NOTE: For 256-entry circular buffer, use only bits [7:0].
*/
#define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
#define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
/**
* Rx Config/Status Registers (RCSR)
* Rx Config Reg for channel 0 (only channel used)
*
* Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
* normal operation (see bit fields).
*
* Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
* Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
* FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
*
* Bit fields:
* 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
* '10' operate normally
* 29-24: reserved
* 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
* min "5" for 32 RBDs, max "12" for 4096 RBDs.
* 19-18: reserved
* 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
* '10' 12K, '11' 16K.
* 15-14: reserved
* 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
* 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
* typical value 0x10 (about 1/2 msec)
* 3- 0: reserved
*/
#define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
#define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
#define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
#define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
#define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
#define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
#define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
#define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
#define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */
#define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
#define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
#define RX_RB_TIMEOUT (0x10)
#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
#define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
#define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
/**
* Rx Shared Status Registers (RSSR)
*
* After stopping Rx DMA channel (writing 0 to
* FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
* FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
*
* Bit fields:
* 24: 1 = Channel 0 is idle
*
* FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
* contain default values that should not be altered by the driver.
*/
#define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
#define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
#define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
#define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
#define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
(FH49_MEM_RSSR_LOWER_BOUND + 0x008)
#define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
#define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
/* TFDB Area - TFDs buffer table */
#define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
#define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
#define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
#define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
#define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
/**
* Transmit DMA Channel Control/Status Registers (TCSR)
*
* 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
* supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
* which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
*
* To use a Tx DMA channel, driver must initialize its
* FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
*
* FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
* FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
*
* All other bits should be 0.
*
* Bit fields:
* 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
* '10' operate normally
* 29- 4: Reserved, set to "0"
* 3: Enable internal DMA requests (1, normal operation), disable (0)
* 2- 0: Reserved, set to "0"
*/
#define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
#define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
/* Find Control/Status reg for given Tx DMA/FIFO channel */
#define FH49_TCSR_CHNL_NUM (7)
#define FH50_TCSR_CHNL_NUM (8)
/* TCSR: tx_config register values */
#define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
(FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
#define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
(FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
#define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
(FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
/**
* Tx Shared Status Registers (TSSR)
*
* After stopping Tx DMA channel (writing 0 to
* FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
* FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
* (channel's buffers empty | no pending requests).
*
* Bit fields:
* 31-24: 1 = Channel buffers empty (channel 7:0)
* 23-16: 1 = No pending requests (channel 7:0)
*/
#define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
#define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
#define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
/**
* Bit fields for TSSR(Tx Shared Status & Control) error status register:
* 31: Indicates an address error when accessed to internal memory
* uCode/driver must write "1" in order to clear this flag
* 30: Indicates that Host did not send the expected number of dwords to FH
* uCode/driver must write "1" in order to clear this flag
* 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
* command was received from the scheduler while the TRB was already full
* with previous command
* uCode/driver must write "1" in order to clear this flag
* 7-0: Each status bit indicates a channel's TxCredit error. When an error
* bit is set, it indicates that the FH has received a full indication
* from the RTC TxFIFO and the current value of the TxCredit counter was
* not equal to zero. This mean that the credit mechanism was not
* synchronized to the TxFIFO status
* uCode/driver must write "1" in order to clear this flag
*/
#define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
#define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
/* Tx service channels */
#define FH49_SRVC_CHNL (9)
#define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
#define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
#define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
(FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
#define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
/* Instruct FH to increment the retry count of a packet when
* it is brought from the memory to TX-FIFO
*/
#define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
/* Keep Warm Size */
#define IL_KW_SIZE 0x1000 /* 4k */
#endif /* __il_4965_h__ */
|
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/ingenic,jz4770-cgu.h>
#include <dt-bindings/clock/ingenic,tcu.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ingenic,jz4770";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4770_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
intc: interrupt-controller@10001000 {
compatible = "ingenic,jz4770-intc";
reg = <0x10001000 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
ext: ext {
compatible = "fixed-clock";
#clock-cells = <0>;
};
osc32k: osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
cgu: jz4770-cgu@10000000 {
compatible = "ingenic,jz4770-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x100>;
clocks = <&ext>, <&osc32k>;
clock-names = "ext", "osc32k";
#clock-cells = <1>;
otg_phy: usb-phy@3c {
compatible = "ingenic,jz4770-phy";
reg = <0x3c 0x10>;
clocks = <&cgu JZ4770_CLK_OTG_PHY>;
#phy-cells = <0>;
};
};
tcu: timer@10002000 {
compatible = "ingenic,jz4770-tcu", "simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4770_CLK_RTC>,
<&cgu JZ4770_CLK_EXT>,
<&cgu JZ4770_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <27 26 25>;
watchdog: watchdog@0 {
compatible = "ingenic,jz4770-watchdog",
"ingenic,jz4740-watchdog";
reg = <0x0 0xc>;
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
pwm: pwm@40 {
compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm";
reg = <0x40 0x80>;
#pwm-cells = <3>;
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
<&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
clock-names = "timer0", "timer1", "timer2", "timer3",
"timer4", "timer5", "timer6", "timer7";
};
ost: timer@e0 {
compatible = "ingenic,jz4770-ost";
reg = <0xe0 0x20>;
clocks = <&tcu TCU_CLK_OST>;
clock-names = "ost";
interrupts = <15>;
};
};
rtc: rtc@10003000 {
compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc";
reg = <0x10003000 0x40>;
interrupt-parent = <&intc>;
interrupts = <32>;
};
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4770-pinctrl";
reg = <0x10010000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4770-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <17>;
};
gpb: gpio@1 {
compatible = "ingenic,jz4770-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <16>;
};
gpc: gpio@2 {
compatible = "ingenic,jz4770-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <15>;
};
gpd: gpio@3 {
compatible = "ingenic,jz4770-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
gpe: gpio@4 {
compatible = "ingenic,jz4770-gpio";
reg = <4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <13>;
};
gpf: gpio@5 {
compatible = "ingenic,jz4770-gpio";
reg = <5>;
gpio-controller;
gpio-ranges = <&pinctrl 0 160 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <12>;
};
};
aic: audio-controller@10020000 {
compatible = "ingenic,jz4770-i2s";
reg = <0x10020000 0x94>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>;
clock-names = "aic", "i2s";
interrupt-parent = <&intc>;
interrupts = <34>;
dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>;
dma-names = "rx", "tx";
};
codec: audio-codec@100200a0 {
compatible = "ingenic,jz4770-codec";
reg = <0x100200a4 0x8>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4770_CLK_AIC>;
clock-names = "aic";
};
mmc0: mmc@10021000 {
compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
reg = <0x10021000 0x1000>;
clocks = <&cgu JZ4770_CLK_MMC0>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <37>;
dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
status = "disabled";
};
mmc1: mmc@10022000 {
compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
reg = <0x10022000 0x1000>;
clocks = <&cgu JZ4770_CLK_MMC1>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <36>;
dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
status = "disabled";
};
mmc2: mmc@10023000 {
compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
reg = <0x10023000 0x1000>;
clocks = <&cgu JZ4770_CLK_MMC2>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <35>;
dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
status = "disabled";
};
uart0: serial@10030000 {
compatible = "ingenic,jz4770-uart";
reg = <0x10030000 0x100>;
clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
clock-names = "baud", "module";
interrupt-parent = <&intc>;
interrupts = <5>;
status = "disabled";
};
uart1: serial@10031000 {
compatible = "ingenic,jz4770-uart";
reg = <0x10031000 0x100>;
clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
clock-names = "baud", "module";
interrupt-parent = <&intc>;
interrupts = <4>;
status = "disabled";
};
uart2: serial@10032000 {
compatible = "ingenic,jz4770-uart";
reg = <0x10032000 0x100>;
clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
clock-names = "baud", "module";
interrupt-parent = <&intc>;
interrupts = <3>;
status = "disabled";
};
uart3: serial@10033000 {
compatible = "ingenic,jz4770-uart";
reg = <0x10033000 0x100>;
clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
clock-names = "baud", "module";
interrupt-parent = <&intc>;
interrupts = <2>;
status = "disabled";
};
adc: adc@10070000 {
compatible = "ingenic,jz4770-adc";
reg = <0x10070000 0x30>;
#io-channel-cells = <1>;
clocks = <&cgu JZ4770_CLK_ADC>;
clock-names = "adc";
interrupt-parent = <&intc>;
interrupts = <18>;
};
gpu: gpu@13040000 {
compatible = "vivante,gc";
reg = <0x13040000 0x10000>;
clocks = <&cgu JZ4770_CLK_GPU>,
<&cgu JZ4770_CLK_GPU>,
<&cgu JZ4770_CLK_GPU>;
clock-names = "bus", "core", "shader";
interrupt-parent = <&intc>;
interrupts = <6>;
};
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4770-lcd";
reg = <0x13050000 0x130>; /* tbc */
interrupt-parent = <&intc>;
interrupts = <31>;
clocks = <&cgu JZ4770_CLK_LPCLK_MUX>;
clock-names = "lcd_pclk";
};
dmac0: dma-controller@13420000 {
compatible = "ingenic,jz4770-dma";
reg = <0x13420000 0xC0>, <0x13420300 0x20>;
#dma-cells = <2>;
clocks = <&cgu JZ4770_CLK_DMA>;
interrupt-parent = <&intc>;
interrupts = <24>;
};
dmac1: dma-controller@13420100 {
compatible = "ingenic,jz4770-dma";
reg = <0x13420100 0xC0>, <0x13420400 0x20>;
#dma-cells = <2>;
clocks = <&cgu JZ4770_CLK_DMA>;
interrupt-parent = <&intc>;
interrupts = <23>;
};
uhc: usb@13430000 {
compatible = "generic-ohci";
reg = <0x13430000 0x1000>;
clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
assigned-clocks = <&cgu JZ4770_CLK_UHC>;
assigned-clock-rates = <48000000>;
interrupt-parent = <&intc>;
interrupts = <20>;
status = "disabled";
};
usb_otg: usb@13440000 {
compatible = "ingenic,jz4770-musb";
reg = <0x13440000 0x10000>;
clocks = <&cgu JZ4770_CLK_OTG>;
clock-names = "udc";
interrupt-parent = <&intc>;
interrupts = <21>;
interrupt-names = "mc";
phys = <&otg_phy>;
usb-role-switch;
};
rom: memory@1fc00000 {
compatible = "mtd-rom";
reg = <0x1fc00000 0x2000>;
bank-width = <4>;
device-width = <1>;
};
};
|
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
*
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
wkup_conf: bus@43000000 {
compatible = "simple-bus";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x43000000 0x20000>;
bootph-all;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
bootph-all;
};
opp_efuse_table: syscon@18 {
compatible = "ti,am62-opp-efuse-table", "syscon";
reg = <0x18 0x4>;
};
cpsw_mac_syscon: ethernet-mac-syscon@200 {
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
reg = <0x200 0x8>;
};
usb0_phy_ctrl: syscon@4008 {
compatible = "ti,am62-usb-phy-ctrl", "syscon";
reg = <0x4008 0x4>;
};
usb1_phy_ctrl: syscon@4018 {
compatible = "ti,am62-usb-phy-ctrl", "syscon";
reg = <0x4018 0x4>;
};
};
wkup_uart0: serial@2b300000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x2b300000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
status = "disabled";
};
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 4>;
clock-names = "fck";
status = "disabled";
};
wkup_rtc0: rtc@2b1f0000 {
compatible = "ti,am62-rtc";
reg = <0x00 0x2b1f0000 0x00 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
clock-names = "vbus", "osc32k";
power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
wakeup-source;
};
wkup_rti0: watchdog@2b000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2b000000 0x00 0x100>;
clocks = <&k3_clks 132 0>;
power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 132 0>;
assigned-clock-parents = <&k3_clks 132 2>;
/* Used by DM firmware */
status = "reserved";
};
wkup_vtm0: temperature-sensor@b00000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0xb00000 0x00 0x400>,
<0x00 0xb01000 0x00 0x400>;
power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
wkup_r5fss0: r5fss@78000000 {
compatible = "ti,am62-r5fss";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x78000000 0x00 0x78000000 0x8000>,
<0x78100000 0x00 0x78100000 0x8000>;
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
wkup_r5fss0_core0: r5f@78000000 {
compatible = "ti,am62-r5f";
reg = <0x78000000 0x00008000>,
<0x78100000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <121>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 121 1>;
firmware-name = "am62-wkup-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
};
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Voltage regulators coupler for MediaTek SoCs
*
* Copyright (C) 2022 Collabora, Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/regulator/coupler.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/suspend.h>
#define to_mediatek_coupler(x) container_of(x, struct mediatek_regulator_coupler, coupler)
struct mediatek_regulator_coupler {
struct regulator_coupler coupler;
struct regulator_dev *vsram_rdev;
};
/*
* We currently support only couples of not more than two vregs and
* modify the vsram voltage only when changing voltage of vgpu.
*
* This function is limited to the GPU<->SRAM voltages relationships.
*/
static int mediatek_regulator_balance_voltage(struct regulator_coupler *coupler,
struct regulator_dev *rdev,
suspend_state_t state)
{
struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler);
int max_spread = rdev->constraints->max_spread[0];
int vsram_min_uV = mrc->vsram_rdev->constraints->min_uV;
int vsram_max_uV = mrc->vsram_rdev->constraints->max_uV;
int vsram_target_min_uV, vsram_target_max_uV;
int min_uV = 0;
int max_uV = INT_MAX;
int ret;
/*
* If the target device is on, setting the SRAM voltage directly
* is not supported as it scales through its coupled supply voltage.
*
* An exception is made in case the use_count is zero: this means
* that this is the first time we power up the SRAM regulator, which
* implies that the target device has yet to perform initialization
* and setting a voltage at that time is harmless.
*/
if (rdev == mrc->vsram_rdev) {
if (rdev->use_count == 0)
return regulator_do_balance_voltage(rdev, state, true);
return -EPERM;
}
ret = regulator_check_consumers(rdev, &min_uV, &max_uV, state);
if (ret < 0)
return ret;
if (min_uV == 0) {
ret = regulator_get_voltage_rdev(rdev);
if (ret < 0)
return ret;
min_uV = ret;
}
ret = regulator_check_voltage(rdev, &min_uV, &max_uV);
if (ret < 0)
return ret;
/*
* If we're asked to set a voltage less than VSRAM min_uV, set
* the minimum allowed voltage on VSRAM, as in this case it is
* safe to ignore the max_spread parameter.
*/
vsram_target_min_uV = max(vsram_min_uV, min_uV + max_spread);
vsram_target_max_uV = min(vsram_max_uV, vsram_target_min_uV + max_spread);
/* Make sure we're not out of range */
vsram_target_min_uV = min(vsram_target_min_uV, vsram_max_uV);
pr_debug("Setting voltage %d-%duV on %s (minuV %d)\n",
vsram_target_min_uV, vsram_target_max_uV,
rdev_get_name(mrc->vsram_rdev), min_uV);
ret = regulator_set_voltage_rdev(mrc->vsram_rdev, vsram_target_min_uV,
vsram_target_max_uV, state);
if (ret)
return ret;
/* The sram voltage is now balanced: update the target vreg voltage */
return regulator_do_balance_voltage(rdev, state, true);
}
static int mediatek_regulator_attach(struct regulator_coupler *coupler,
struct regulator_dev *rdev)
{
struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler);
const char *rdev_name = rdev_get_name(rdev);
/*
* If we're getting a coupling of more than two regulators here and
* this means that this is surely not a GPU<->SRAM couple: in that
* case, we may want to use another coupler implementation, if any,
* or the generic one: the regulator core will keep walking through
* the list of couplers when any .attach_regulator() cb returns 1.
*/
if (rdev->coupling_desc.n_coupled > 2)
return 1;
if (strstr(rdev_name, "sram")) {
if (mrc->vsram_rdev)
return -EINVAL;
mrc->vsram_rdev = rdev;
} else if (!strstr(rdev_name, "vgpu") && !strstr(rdev_name, "Vgpu")) {
return 1;
}
return 0;
}
static int mediatek_regulator_detach(struct regulator_coupler *coupler,
struct regulator_dev *rdev)
{
struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler);
if (rdev == mrc->vsram_rdev)
mrc->vsram_rdev = NULL;
return 0;
}
static struct mediatek_regulator_coupler mediatek_coupler = {
.coupler = {
.attach_regulator = mediatek_regulator_attach,
.detach_regulator = mediatek_regulator_detach,
.balance_voltage = mediatek_regulator_balance_voltage,
},
};
static int mediatek_regulator_coupler_init(void)
{
if (!of_machine_is_compatible("mediatek,mt8183") &&
!of_machine_is_compatible("mediatek,mt8186") &&
!of_machine_is_compatible("mediatek,mt8188") &&
!of_machine_is_compatible("mediatek,mt8192"))
return 0;
return regulator_coupler_register(&mediatek_coupler.coupler);
}
arch_initcall(mediatek_regulator_coupler_init);
MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
MODULE_DESCRIPTION("MediaTek Regulator Coupler driver");
MODULE_LICENSE("GPL");
|
// SPDX-License-Identifier: GPL-2.0
/* Lock down the kernel
*
* Copyright (C) 2016 Red Hat, Inc. All Rights Reserved.
* Written by David Howells ([email protected])
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#include <linux/security.h>
#include <linux/export.h>
#include <linux/lsm_hooks.h>
#include <uapi/linux/lsm.h>
static enum lockdown_reason kernel_locked_down;
static const enum lockdown_reason lockdown_levels[] = {LOCKDOWN_NONE,
LOCKDOWN_INTEGRITY_MAX,
LOCKDOWN_CONFIDENTIALITY_MAX};
/*
* Put the kernel into lock-down mode.
*/
static int lock_kernel_down(const char *where, enum lockdown_reason level)
{
if (kernel_locked_down >= level)
return -EPERM;
kernel_locked_down = level;
pr_notice("Kernel is locked down from %s; see man kernel_lockdown.7\n",
where);
return 0;
}
static int __init lockdown_param(char *level)
{
if (!level)
return -EINVAL;
if (strcmp(level, "integrity") == 0)
lock_kernel_down("command line", LOCKDOWN_INTEGRITY_MAX);
else if (strcmp(level, "confidentiality") == 0)
lock_kernel_down("command line", LOCKDOWN_CONFIDENTIALITY_MAX);
else
return -EINVAL;
return 0;
}
early_param("lockdown", lockdown_param);
/**
* lockdown_is_locked_down - Find out if the kernel is locked down
* @what: Tag to use in notice generated if lockdown is in effect
*/
static int lockdown_is_locked_down(enum lockdown_reason what)
{
if (WARN(what >= LOCKDOWN_CONFIDENTIALITY_MAX,
"Invalid lockdown reason"))
return -EPERM;
if (kernel_locked_down >= what) {
if (lockdown_reasons[what])
pr_notice_ratelimited("Lockdown: %s: %s is restricted; see man kernel_lockdown.7\n",
current->comm, lockdown_reasons[what]);
return -EPERM;
}
return 0;
}
static struct security_hook_list lockdown_hooks[] __ro_after_init = {
LSM_HOOK_INIT(locked_down, lockdown_is_locked_down),
};
static const struct lsm_id lockdown_lsmid = {
.name = "lockdown",
.id = LSM_ID_LOCKDOWN,
};
static int __init lockdown_lsm_init(void)
{
#if defined(CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY)
lock_kernel_down("Kernel configuration", LOCKDOWN_INTEGRITY_MAX);
#elif defined(CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY)
lock_kernel_down("Kernel configuration", LOCKDOWN_CONFIDENTIALITY_MAX);
#endif
security_add_hooks(lockdown_hooks, ARRAY_SIZE(lockdown_hooks),
&lockdown_lsmid);
return 0;
}
static ssize_t lockdown_read(struct file *filp, char __user *buf, size_t count,
loff_t *ppos)
{
char temp[80];
int i, offset = 0;
for (i = 0; i < ARRAY_SIZE(lockdown_levels); i++) {
enum lockdown_reason level = lockdown_levels[i];
if (lockdown_reasons[level]) {
const char *label = lockdown_reasons[level];
if (kernel_locked_down == level)
offset += sprintf(temp+offset, "[%s] ", label);
else
offset += sprintf(temp+offset, "%s ", label);
}
}
/* Convert the last space to a newline if needed. */
if (offset > 0)
temp[offset-1] = '\n';
return simple_read_from_buffer(buf, count, ppos, temp, strlen(temp));
}
static ssize_t lockdown_write(struct file *file, const char __user *buf,
size_t n, loff_t *ppos)
{
char *state;
int i, len, err = -EINVAL;
state = memdup_user_nul(buf, n);
if (IS_ERR(state))
return PTR_ERR(state);
len = strlen(state);
if (len && state[len-1] == '\n') {
state[len-1] = '\0';
len--;
}
for (i = 0; i < ARRAY_SIZE(lockdown_levels); i++) {
enum lockdown_reason level = lockdown_levels[i];
const char *label = lockdown_reasons[level];
if (label && !strcmp(state, label))
err = lock_kernel_down("securityfs", level);
}
kfree(state);
return err ? err : n;
}
static const struct file_operations lockdown_ops = {
.read = lockdown_read,
.write = lockdown_write,
};
static int __init lockdown_secfs_init(void)
{
struct dentry *dentry;
dentry = securityfs_create_file("lockdown", 0644, NULL, NULL,
&lockdown_ops);
return PTR_ERR_OR_ZERO(dentry);
}
core_initcall(lockdown_secfs_init);
#ifdef CONFIG_SECURITY_LOCKDOWN_LSM_EARLY
DEFINE_EARLY_LSM(lockdown) = {
#else
DEFINE_LSM(lockdown) = {
#endif
.name = "lockdown",
.init = lockdown_lsm_init,
};
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Public Key Encryption
*
* Copyright (c) 2015, Intel Corporation
* Authors: Tadeusz Struk <[email protected]>
*/
#ifndef _CRYPTO_AKCIPHER_INT_H
#define _CRYPTO_AKCIPHER_INT_H
#include <crypto/akcipher.h>
#include <crypto/algapi.h>
struct akcipher_instance {
void (*free)(struct akcipher_instance *inst);
union {
struct {
char head[offsetof(struct akcipher_alg, base)];
struct crypto_instance base;
} s;
struct akcipher_alg alg;
};
};
struct crypto_akcipher_spawn {
struct crypto_spawn base;
};
/*
* Transform internal helpers.
*/
static inline void *akcipher_request_ctx(struct akcipher_request *req)
{
return req->__ctx;
}
static inline void *akcipher_request_ctx_dma(struct akcipher_request *req)
{
unsigned int align = crypto_dma_align();
if (align <= crypto_tfm_ctx_alignment())
align = 1;
return PTR_ALIGN(akcipher_request_ctx(req), align);
}
static inline void akcipher_set_reqsize(struct crypto_akcipher *akcipher,
unsigned int reqsize)
{
akcipher->reqsize = reqsize;
}
static inline void akcipher_set_reqsize_dma(struct crypto_akcipher *akcipher,
unsigned int reqsize)
{
reqsize += crypto_dma_align() & ~(crypto_tfm_ctx_alignment() - 1);
akcipher->reqsize = reqsize;
}
static inline void *akcipher_tfm_ctx(struct crypto_akcipher *tfm)
{
return crypto_tfm_ctx(&tfm->base);
}
static inline void *akcipher_tfm_ctx_dma(struct crypto_akcipher *tfm)
{
return crypto_tfm_ctx_dma(&tfm->base);
}
static inline void akcipher_request_complete(struct akcipher_request *req,
int err)
{
crypto_request_complete(&req->base, err);
}
static inline const char *akcipher_alg_name(struct crypto_akcipher *tfm)
{
return crypto_akcipher_tfm(tfm)->__crt_alg->cra_name;
}
static inline struct crypto_instance *akcipher_crypto_instance(
struct akcipher_instance *inst)
{
return container_of(&inst->alg.base, struct crypto_instance, alg);
}
static inline struct akcipher_instance *akcipher_instance(
struct crypto_instance *inst)
{
return container_of(&inst->alg, struct akcipher_instance, alg.base);
}
static inline struct akcipher_instance *akcipher_alg_instance(
struct crypto_akcipher *akcipher)
{
return akcipher_instance(crypto_tfm_alg_instance(&akcipher->base));
}
static inline void *akcipher_instance_ctx(struct akcipher_instance *inst)
{
return crypto_instance_ctx(akcipher_crypto_instance(inst));
}
int crypto_grab_akcipher(struct crypto_akcipher_spawn *spawn,
struct crypto_instance *inst,
const char *name, u32 type, u32 mask);
static inline struct crypto_akcipher *crypto_spawn_akcipher(
struct crypto_akcipher_spawn *spawn)
{
return crypto_spawn_tfm2(&spawn->base);
}
static inline void crypto_drop_akcipher(struct crypto_akcipher_spawn *spawn)
{
crypto_drop_spawn(&spawn->base);
}
static inline struct akcipher_alg *crypto_spawn_akcipher_alg(
struct crypto_akcipher_spawn *spawn)
{
return container_of(spawn->base.alg, struct akcipher_alg, base);
}
/**
* crypto_register_akcipher() -- Register public key algorithm
*
* Function registers an implementation of a public key cipher algorithm
*
* @alg: algorithm definition
*
* Return: zero on success; error code in case of error
*/
int crypto_register_akcipher(struct akcipher_alg *alg);
/**
* crypto_unregister_akcipher() -- Unregister public key algorithm
*
* Function unregisters an implementation of a public key cipher algorithm
*
* @alg: algorithm definition
*/
void crypto_unregister_akcipher(struct akcipher_alg *alg);
/**
* akcipher_register_instance() -- Unregister public key template instance
*
* Function registers an implementation of an asymmetric key algorithm
* created from a template
*
* @tmpl: the template from which the algorithm was created
* @inst: the template instance
*/
int akcipher_register_instance(struct crypto_template *tmpl,
struct akcipher_instance *inst);
#endif
|
// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.
#include "dml2_internal_shared_types.h"
#include "dml_top.h"
#include "dml2_mcg_factory.h"
#include "dml2_core_factory.h"
#include "dml2_dpmm_factory.h"
#include "dml2_pmo_factory.h"
#include "dml_top_mcache.h"
#include "dml2_top_optimization.h"
#include "dml2_external_lib_deps.h"
unsigned int dml2_get_instance_size_bytes(void)
{
return sizeof(struct dml2_instance);
}
bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out)
{
struct dml2_instance *dml = (struct dml2_instance *)in_out->dml2_instance;
struct dml2_initialize_instance_locals *l = &dml->scratch.initialize_instance_locals;
struct dml2_core_initialize_in_out core_init_params = { 0 };
struct dml2_mcg_build_min_clock_table_params_in_out mcg_build_min_clk_params = { 0 };
struct dml2_pmo_initialize_in_out pmo_init_params = { 0 };
bool result = false;
memset(l, 0, sizeof(struct dml2_initialize_instance_locals));
memset(dml, 0, sizeof(struct dml2_instance));
memcpy(&dml->ip_caps, &in_out->ip_caps, sizeof(struct dml2_ip_capabilities));
memcpy(&dml->soc_bbox, &in_out->soc_bb, sizeof(struct dml2_soc_bb));
dml->project_id = in_out->options.project_id;
dml->pmo_options = in_out->options.pmo_options;
// Initialize All Components
result = dml2_mcg_create(in_out->options.project_id, &dml->mcg_instance);
if (result)
result = dml2_dpmm_create(in_out->options.project_id, &dml->dpmm_instance);
if (result)
result = dml2_core_create(in_out->options.project_id, &dml->core_instance);
if (result) {
mcg_build_min_clk_params.soc_bb = &in_out->soc_bb;
mcg_build_min_clk_params.min_clk_table = &dml->min_clk_table;
result = dml->mcg_instance.build_min_clock_table(&mcg_build_min_clk_params);
}
if (result) {
core_init_params.project_id = in_out->options.project_id;
core_init_params.instance = &dml->core_instance;
core_init_params.minimum_clock_table = &dml->min_clk_table;
core_init_params.explicit_ip_bb = in_out->overrides.explicit_ip_bb;
core_init_params.explicit_ip_bb_size = in_out->overrides.explicit_ip_bb_size;
core_init_params.ip_caps = &in_out->ip_caps;
core_init_params.soc_bb = &in_out->soc_bb;
result = dml->core_instance.initialize(&core_init_params);
if (core_init_params.explicit_ip_bb && core_init_params.explicit_ip_bb_size > 0) {
memcpy(&dml->ip_caps, &in_out->ip_caps, sizeof(struct dml2_ip_capabilities));
}
}
if (result)
result = dml2_pmo_create(in_out->options.project_id, &dml->pmo_instance);
if (result) {
pmo_init_params.instance = &dml->pmo_instance;
pmo_init_params.soc_bb = &dml->soc_bbox;
pmo_init_params.ip_caps = &dml->ip_caps;
pmo_init_params.mcg_clock_table_size = dml->min_clk_table.dram_bw_table.num_entries;
pmo_init_params.options = &dml->pmo_options;
dml->pmo_instance.initialize(&pmo_init_params);
}
return result;
}
static void setup_unoptimized_display_config_with_meta(const struct dml2_instance *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config)
{
memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg));
out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->min_clk_table.clean_me_up.soc_bb.num_states - 1;
}
static void setup_speculative_display_config_with_meta(const struct dml2_instance *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config)
{
memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg));
out->stage1.min_clk_index_for_latency = 0;
}
bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out)
{
struct dml2_instance *dml = (struct dml2_instance *)in_out->dml2_instance;
struct dml2_check_mode_supported_locals *l = &dml->scratch.check_mode_supported_locals;
struct dml2_display_cfg_programming *dpmm_programming = &dml->dpmm_instance.dpmm_scratch.programming;
bool result = false;
bool mcache_success = false;
memset(dpmm_programming, 0, sizeof(struct dml2_display_cfg_programming));
setup_unoptimized_display_config_with_meta(dml, &l->base_display_config_with_meta, in_out->display_config);
l->mode_support_params.instance = &dml->core_instance;
l->mode_support_params.display_cfg = &l->base_display_config_with_meta;
l->mode_support_params.min_clk_table = &dml->min_clk_table;
l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_latency;
result = dml->core_instance.mode_support(&l->mode_support_params);
l->base_display_config_with_meta.mode_support_result = l->mode_support_params.mode_support_result;
if (result) {
struct optimization_phase_params mcache_phase = {
.dml = dml,
.display_config = &l->base_display_config_with_meta,
.test_function = dml2_top_optimization_test_function_mcache,
.optimize_function = dml2_top_optimization_optimize_function_mcache,
.optimized_display_config = &l->optimized_display_config_with_meta,
.all_or_nothing = false,
};
mcache_success = dml2_top_optimization_perform_optimization_phase(&l->optimization_phase_locals, &mcache_phase);
}
/*
* Call DPMM to map all requirements to minimum clock state
*/
if (result) {
l->dppm_map_mode_params.min_clk_table = &dml->min_clk_table;
l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta;
l->dppm_map_mode_params.programming = dpmm_programming;
l->dppm_map_mode_params.soc_bb = &dml->soc_bbox;
l->dppm_map_mode_params.ip = &dml->core_instance.clean_me_up.mode_lib.ip;
result = dml->dpmm_instance.map_mode_to_soc_dpm(&l->dppm_map_mode_params);
}
in_out->is_supported = mcache_success;
result = result && in_out->is_supported;
return result;
}
bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out)
{
struct dml2_instance *dml = (struct dml2_instance *)in_out->dml2_instance;
struct dml2_build_mode_programming_locals *l = &dml->scratch.build_mode_programming_locals;
bool result = false;
bool mcache_success = false;
bool uclk_pstate_success = false;
bool vmin_success = false;
bool stutter_success = false;
unsigned int i;
memset(l, 0, sizeof(struct dml2_build_mode_programming_locals));
memset(in_out->programming, 0, sizeof(struct dml2_display_cfg_programming));
memcpy(&in_out->programming->display_config, in_out->display_config, sizeof(struct dml2_display_cfg));
setup_speculative_display_config_with_meta(dml, &l->base_display_config_with_meta, in_out->display_config);
l->mode_support_params.instance = &dml->core_instance;
l->mode_support_params.display_cfg = &l->base_display_config_with_meta;
l->mode_support_params.min_clk_table = &dml->min_clk_table;
l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_latency;
result = dml->core_instance.mode_support(&l->mode_support_params);
l->base_display_config_with_meta.mode_support_result = l->mode_support_params.mode_support_result;
if (!result) {
setup_unoptimized_display_config_with_meta(dml, &l->base_display_config_with_meta, in_out->display_config);
l->mode_support_params.instance = &dml->core_instance;
l->mode_support_params.display_cfg = &l->base_display_config_with_meta;
l->mode_support_params.min_clk_table = &dml->min_clk_table;
l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_latency;
result = dml->core_instance.mode_support(&l->mode_support_params);
l->base_display_config_with_meta.mode_support_result = l->mode_support_params.mode_support_result;
if (!result) {
l->informative_params.instance = &dml->core_instance;
l->informative_params.programming = in_out->programming;
l->informative_params.mode_is_supported = false;
dml->core_instance.populate_informative(&l->informative_params);
return false;
}
/*
* Phase 1: Determine minimum clocks to satisfy latency requirements for this mode
*/
memset(&l->min_clock_for_latency_phase, 0, sizeof(struct optimization_phase_params));
l->min_clock_for_latency_phase.dml = dml;
l->min_clock_for_latency_phase.display_config = &l->base_display_config_with_meta;
l->min_clock_for_latency_phase.init_function = dml2_top_optimization_init_function_min_clk_for_latency;
l->min_clock_for_latency_phase.test_function = dml2_top_optimization_test_function_min_clk_for_latency;
l->min_clock_for_latency_phase.optimize_function = dml2_top_optimization_optimize_function_min_clk_for_latency;
l->min_clock_for_latency_phase.optimized_display_config = &l->optimized_display_config_with_meta;
l->min_clock_for_latency_phase.all_or_nothing = false;
dml2_top_optimization_perform_optimization_phase_1(&l->optimization_phase_locals, &l->min_clock_for_latency_phase);
memcpy(&l->base_display_config_with_meta, &l->optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));
}
/*
* Phase 2: Satisfy DCC mcache requirements
*/
memset(&l->mcache_phase, 0, sizeof(struct optimization_phase_params));
l->mcache_phase.dml = dml;
l->mcache_phase.display_config = &l->base_display_config_with_meta;
l->mcache_phase.test_function = dml2_top_optimization_test_function_mcache;
l->mcache_phase.optimize_function = dml2_top_optimization_optimize_function_mcache;
l->mcache_phase.optimized_display_config = &l->optimized_display_config_with_meta;
l->mcache_phase.all_or_nothing = true;
mcache_success = dml2_top_optimization_perform_optimization_phase(&l->optimization_phase_locals, &l->mcache_phase);
if (!mcache_success) {
l->informative_params.instance = &dml->core_instance;
l->informative_params.programming = in_out->programming;
l->informative_params.mode_is_supported = false;
dml->core_instance.populate_informative(&l->informative_params);
in_out->programming->informative.failed_mcache_validation = true;
return false;
}
memcpy(&l->base_display_config_with_meta, &l->optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));
/*
* Phase 3: Optimize for Pstate
*/
memset(&l->uclk_pstate_phase, 0, sizeof(struct optimization_phase_params));
l->uclk_pstate_phase.dml = dml;
l->uclk_pstate_phase.display_config = &l->base_display_config_with_meta;
l->uclk_pstate_phase.init_function = dml2_top_optimization_init_function_uclk_pstate;
l->uclk_pstate_phase.test_function = dml2_top_optimization_test_function_uclk_pstate;
l->uclk_pstate_phase.optimize_function = dml2_top_optimization_optimize_function_uclk_pstate;
l->uclk_pstate_phase.optimized_display_config = &l->optimized_display_config_with_meta;
l->uclk_pstate_phase.all_or_nothing = true;
uclk_pstate_success = dml2_top_optimization_perform_optimization_phase(&l->optimization_phase_locals, &l->uclk_pstate_phase);
if (uclk_pstate_success) {
memcpy(&l->base_display_config_with_meta, &l->optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));
l->base_display_config_with_meta.stage3.success = true;
}
/*
* Phase 4: Optimize for Vmin
*/
memset(&l->vmin_phase, 0, sizeof(struct optimization_phase_params));
l->vmin_phase.dml = dml;
l->vmin_phase.display_config = &l->base_display_config_with_meta;
l->vmin_phase.init_function = dml2_top_optimization_init_function_vmin;
l->vmin_phase.test_function = dml2_top_optimization_test_function_vmin;
l->vmin_phase.optimize_function = dml2_top_optimization_optimize_function_vmin;
l->vmin_phase.optimized_display_config = &l->optimized_display_config_with_meta;
l->vmin_phase.all_or_nothing = false;
vmin_success = dml2_top_optimization_perform_optimization_phase(&l->optimization_phase_locals, &l->vmin_phase);
if (l->optimized_display_config_with_meta.stage4.performed) {
/*
* when performed is true, optimization has applied to
* optimized_display_config_with_meta and it has passed mode
* support. However it may or may not pass the test function to
* reach actual Vmin. As long as voltage is optimized even if it
* doesn't reach Vmin level, there is still power benefit so in
* this case we will still copy this optimization into base
* display config.
*/
memcpy(&l->base_display_config_with_meta, &l->optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));
l->base_display_config_with_meta.stage4.success = vmin_success;
}
/*
* Phase 5: Optimize for Stutter
*/
memset(&l->stutter_phase, 0, sizeof(struct optimization_phase_params));
l->stutter_phase.dml = dml;
l->stutter_phase.display_config = &l->base_display_config_with_meta;
l->stutter_phase.init_function = dml2_top_optimization_init_function_stutter;
l->stutter_phase.test_function = dml2_top_optimization_test_function_stutter;
l->stutter_phase.optimize_function = dml2_top_optimization_optimize_function_stutter;
l->stutter_phase.optimized_display_config = &l->optimized_display_config_with_meta;
l->stutter_phase.all_or_nothing = true;
stutter_success = dml2_top_optimization_perform_optimization_phase(&l->optimization_phase_locals, &l->stutter_phase);
if (stutter_success) {
memcpy(&l->base_display_config_with_meta, &l->optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));
l->base_display_config_with_meta.stage5.success = true;
}
/*
* Populate mcache programming
*/
for (i = 0; i < in_out->display_config->num_planes; i++) {
in_out->programming->plane_programming[i].mcache_allocation = l->base_display_config_with_meta.stage2.mcache_allocations[i];
}
/*
* Call DPMM to map all requirements to minimum clock state
*/
if (result) {
l->dppm_map_mode_params.min_clk_table = &dml->min_clk_table;
l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta;
l->dppm_map_mode_params.programming = in_out->programming;
l->dppm_map_mode_params.soc_bb = &dml->soc_bbox;
l->dppm_map_mode_params.ip = &dml->core_instance.clean_me_up.mode_lib.ip;
result = dml->dpmm_instance.map_mode_to_soc_dpm(&l->dppm_map_mode_params);
if (!result)
in_out->programming->informative.failed_dpmm = true;
}
if (result) {
l->mode_programming_params.instance = &dml->core_instance;
l->mode_programming_params.display_cfg = &l->base_display_config_with_meta;
l->mode_programming_params.cfg_support_info = &l->base_display_config_with_meta.mode_support_result.cfg_support_info;
l->mode_programming_params.programming = in_out->programming;
result = dml->core_instance.mode_programming(&l->mode_programming_params);
if (!result)
in_out->programming->informative.failed_mode_programming = true;
}
if (result) {
l->dppm_map_watermarks_params.core = &dml->core_instance;
l->dppm_map_watermarks_params.display_cfg = &l->base_display_config_with_meta;
l->dppm_map_watermarks_params.programming = in_out->programming;
result = dml->dpmm_instance.map_watermarks(&l->dppm_map_watermarks_params);
}
l->informative_params.instance = &dml->core_instance;
l->informative_params.programming = in_out->programming;
l->informative_params.mode_is_supported = result;
dml->core_instance.populate_informative(&l->informative_params);
return result;
}
bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out)
{
return dml2_top_mcache_build_mcache_programming(in_out);
}
|
// SPDX-License-Identifier: GPL-2.0
/*
* STM32 Factory-programmed memory read access driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author: Fabrice Gasnier <[email protected]> for STMicroelectronics.
*/
#include <linux/arm-smccc.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/tee_drv.h>
#include "stm32-bsec-optee-ta.h"
/* BSEC secure service access from non-secure */
#define STM32_SMC_BSEC 0x82001003
#define STM32_SMC_READ_SHADOW 0x01
#define STM32_SMC_PROG_OTP 0x02
#define STM32_SMC_WRITE_SHADOW 0x03
#define STM32_SMC_READ_OTP 0x04
/* shadow registers offset */
#define STM32MP15_BSEC_DATA0 0x200
struct stm32_romem_cfg {
int size;
u8 lower;
bool ta;
};
struct stm32_romem_priv {
void __iomem *base;
struct nvmem_config cfg;
u8 lower;
struct tee_context *ctx;
};
static int stm32_romem_read(void *context, unsigned int offset, void *buf,
size_t bytes)
{
struct stm32_romem_priv *priv = context;
u8 *buf8 = buf;
int i;
for (i = offset; i < offset + bytes; i++)
*buf8++ = readb_relaxed(priv->base + i);
return 0;
}
static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
{
#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
struct arm_smccc_res res;
arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
if (res.a0)
return -EIO;
if (result)
*result = (u32)res.a1;
return 0;
#else
return -ENXIO;
#endif
}
static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
size_t bytes)
{
struct stm32_romem_priv *priv = context;
struct device *dev = priv->cfg.dev;
u32 roffset, rbytes, val;
u8 *buf8 = buf, *val8 = (u8 *)&val;
int i, j = 0, ret, skip_bytes, size;
/* Round unaligned access to 32-bits */
roffset = rounddown(offset, 4);
skip_bytes = offset & 0x3;
rbytes = roundup(bytes + skip_bytes, 4);
if (roffset + rbytes > priv->cfg.size)
return -EINVAL;
for (i = roffset; (i < roffset + rbytes); i += 4) {
u32 otp = i >> 2;
if (otp < priv->lower) {
/* read lower data from shadow registers */
val = readl_relaxed(
priv->base + STM32MP15_BSEC_DATA0 + i);
} else {
ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
&val);
if (ret) {
dev_err(dev, "Can't read data%d (%d)\n", otp,
ret);
return ret;
}
}
/* skip first bytes in case of unaligned read */
if (skip_bytes)
size = min(bytes, (size_t)(4 - skip_bytes));
else
size = min(bytes, (size_t)4);
memcpy(&buf8[j], &val8[skip_bytes], size);
bytes -= size;
j += size;
skip_bytes = 0;
}
return 0;
}
static int stm32_bsec_write(void *context, unsigned int offset, void *buf,
size_t bytes)
{
struct stm32_romem_priv *priv = context;
struct device *dev = priv->cfg.dev;
u32 *buf32 = buf;
int ret, i;
/* Allow only writing complete 32-bits aligned words */
if ((bytes % 4) || (offset % 4))
return -EINVAL;
for (i = offset; i < offset + bytes; i += 4) {
ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
NULL);
if (ret) {
dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
return ret;
}
}
if (offset + bytes >= priv->lower * 4)
dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n");
return 0;
}
static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf,
size_t bytes)
{
struct stm32_romem_priv *priv = context;
return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);
}
static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf,
size_t bytes)
{
struct stm32_romem_priv *priv = context;
return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);
}
static bool stm32_bsec_smc_check(void)
{
u32 val;
int ret;
/* check that the OP-TEE support the BSEC SMC (legacy mode) */
ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);
return !ret;
}
static bool optee_presence_check(void)
{
struct device_node *np;
bool tee_detected = false;
/* check that the OP-TEE node is present and available. */
np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
if (np && of_device_is_available(np))
tee_detected = true;
of_node_put(np);
return tee_detected;
}
static int stm32_romem_probe(struct platform_device *pdev)
{
const struct stm32_romem_cfg *cfg;
struct device *dev = &pdev->dev;
struct stm32_romem_priv *priv;
struct resource *res;
int rc;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->cfg.name = "stm32-romem";
priv->cfg.word_size = 1;
priv->cfg.stride = 1;
priv->cfg.dev = dev;
priv->cfg.priv = priv;
priv->cfg.owner = THIS_MODULE;
priv->cfg.type = NVMEM_TYPE_OTP;
priv->cfg.add_legacy_fixed_of_cells = true;
priv->lower = 0;
cfg = device_get_match_data(dev);
if (!cfg) {
priv->cfg.read_only = true;
priv->cfg.size = resource_size(res);
priv->cfg.reg_read = stm32_romem_read;
} else {
priv->cfg.size = cfg->size;
priv->lower = cfg->lower;
if (cfg->ta || optee_presence_check()) {
rc = stm32_bsec_optee_ta_open(&priv->ctx);
if (rc) {
/* wait for OP-TEE client driver to be up and ready */
if (rc == -EPROBE_DEFER)
return -EPROBE_DEFER;
/* BSEC PTA is required or SMC not supported */
if (cfg->ta || !stm32_bsec_smc_check())
return rc;
}
}
if (priv->ctx) {
rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);
if (rc) {
dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);
return rc;
}
priv->cfg.reg_read = stm32_bsec_pta_read;
priv->cfg.reg_write = stm32_bsec_pta_write;
} else {
priv->cfg.reg_read = stm32_bsec_read;
priv->cfg.reg_write = stm32_bsec_write;
}
}
return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
}
/*
* STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
* => 96 x 32-bits data words
* - Lower: 1K bits, 2:1 redundancy, incremental bit programming
* => 32 (x 32-bits) lower shadow registers = words 0 to 31
* - Upper: 2K bits, ECC protection, word programming only
* => 64 (x 32-bits) = words 32 to 95
*/
static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
.size = 384,
.lower = 32,
.ta = false,
};
static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {
.size = 384,
.lower = 32,
.ta = true,
};
/*
* STM32MP25 BSEC OTP: 3 regions of 32-bits data words
* lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
* mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
* upper OTP (OTP256 to OTP383), bulk (32-bit) programmable
* but no access to HWKEY and ECIES key: limited at OTP367
*/
static const struct stm32_romem_cfg stm32mp25_bsec_cfg = {
.size = 368 * 4,
.lower = 127,
.ta = true,
};
static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {
{ .compatible = "st,stm32f4-otp", }, {
.compatible = "st,stm32mp15-bsec",
.data = (void *)&stm32mp15_bsec_cfg,
}, {
.compatible = "st,stm32mp13-bsec",
.data = (void *)&stm32mp13_bsec_cfg,
}, {
.compatible = "st,stm32mp25-bsec",
.data = (void *)&stm32mp25_bsec_cfg,
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
static struct platform_driver stm32_romem_driver = {
.probe = stm32_romem_probe,
.driver = {
.name = "stm32-romem",
.of_match_table = of_match_ptr(stm32_romem_of_match),
},
};
module_platform_driver(stm32_romem_driver);
MODULE_AUTHOR("Fabrice Gasnier <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
MODULE_ALIAS("platform:nvmem-stm32-romem");
MODULE_LICENSE("GPL v2");
|
/{
cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1000000 1000000 1300000>;
clock-latency-ns = <2000000>;
};
opp-912000000 {
opp-hz = /bits/ 64 <912000000>;
opp-microvolt = <1100000 1100000 1300000>;
clock-latency-ns = <2000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1160000 1160000 1300000>;
clock-latency-ns = <2000000>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1240000 1240000 1300000>;
clock-latency-ns = <2000000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1300000 1300000 1300000>;
clock-latency-ns = <2000000>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu0_opp_table>;
};
&cpu1 {
operating-points-v2 = <&cpu0_opp_table>;
};
&cpu2 {
operating-points-v2 = <&cpu0_opp_table>;
};
&cpu3 {
operating-points-v2 = <&cpu0_opp_table>;
};
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/export.h>
#include <linux/netfilter/ipset/pfxlen.h>
/* Prefixlen maps for fast conversions, by Jan Engelhardt. */
#ifdef E
#undef E
#endif
#define PREFIXES_MAP \
E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFC00000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFE00000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFF00000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFF80000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFC0000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFE0000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFF8000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFC000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFE000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFF000, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFF800, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFC00, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFE00, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFF00, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFF80, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFC0, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFE0, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFF0, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFF8, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFC, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFE, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0x80000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xC0000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xE0000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xF0000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xF8000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFC000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFE000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFF000000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFF800000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFC00000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFE00000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFF00000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFF80000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFC0000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFE0000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFF0000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFF8000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFC000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFE000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFF000, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFF800, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFC00, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFE00, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFF00, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFF80, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFC0, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFE0, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFF0, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFF8, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFC, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFE, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0x80000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xC0000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xE0000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xF0000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xF8000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFC000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFE000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFF000000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFF800000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFC00000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFE00000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFF00000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFF80000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFC0000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFE0000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF0000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF8000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFC000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFE000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF000, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF800, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFC00, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFE00, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFF00, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFF80, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFC0, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFE0, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFF0, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFF8, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFC, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFE, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x80000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xC0000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xE0000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xF0000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xF8000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFC000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFE000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF000000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF800000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFC00000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFE00000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF00000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF80000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFC0000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFE0000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF0000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF8000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFC000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFE000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF000), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF800), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFC00), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFE00), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFF00), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFF80), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFC0), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFE0), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFF0), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFF8), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFC), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFE), \
E(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF),
#define E(a, b, c, d) \
{.ip6 = { \
htonl(a), htonl(b), \
htonl(c), htonl(d), \
} }
/* This table works for both IPv4 and IPv6;
* just use prefixlen_netmask_map[prefixlength].ip.
*/
const union nf_inet_addr ip_set_netmask_map[] = {
PREFIXES_MAP
};
EXPORT_SYMBOL_GPL(ip_set_netmask_map);
#undef E
#define E(a, b, c, d) \
{.ip6 = { (__force __be32)a, (__force __be32)b, \
(__force __be32)c, (__force __be32)d, \
} }
/* This table works for both IPv4 and IPv6;
* just use prefixlen_hostmask_map[prefixlength].ip.
*/
const union nf_inet_addr ip_set_hostmask_map[] = {
PREFIXES_MAP
};
EXPORT_SYMBOL_GPL(ip_set_hostmask_map);
/* Find the largest network which matches the range from left, in host order. */
u32
ip_set_range_to_cidr(u32 from, u32 to, u8 *cidr)
{
u32 last;
u8 i;
for (i = 1; i < 32; i++) {
if ((from & ip_set_hostmask(i)) != from)
continue;
last = from | ~ip_set_hostmask(i);
if (!after(last, to)) {
*cidr = i;
return last;
}
}
*cidr = 32;
return from;
}
EXPORT_SYMBOL_GPL(ip_set_range_to_cidr);
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _KERNEL_SCHED_AUTOGROUP_H
#define _KERNEL_SCHED_AUTOGROUP_H
#ifdef CONFIG_SCHED_AUTOGROUP
struct autogroup {
/*
* Reference doesn't mean how many threads attach to this
* autogroup now. It just stands for the number of tasks
* which could use this autogroup.
*/
struct kref kref;
struct task_group *tg;
struct rw_semaphore lock;
unsigned long id;
int nice;
};
extern void autogroup_init(struct task_struct *init_task);
extern void autogroup_free(struct task_group *tg);
static inline bool task_group_is_autogroup(struct task_group *tg)
{
return !!tg->autogroup;
}
extern bool task_wants_autogroup(struct task_struct *p, struct task_group *tg);
static inline struct task_group *
autogroup_task_group(struct task_struct *p, struct task_group *tg)
{
extern unsigned int sysctl_sched_autogroup_enabled;
int enabled = READ_ONCE(sysctl_sched_autogroup_enabled);
if (enabled && task_wants_autogroup(p, tg))
return p->signal->autogroup->tg;
return tg;
}
extern int autogroup_path(struct task_group *tg, char *buf, int buflen);
#else /* !CONFIG_SCHED_AUTOGROUP */
static inline void autogroup_init(struct task_struct *init_task) { }
static inline void autogroup_free(struct task_group *tg) { }
static inline bool task_group_is_autogroup(struct task_group *tg)
{
return 0;
}
static inline struct task_group *
autogroup_task_group(struct task_struct *p, struct task_group *tg)
{
return tg;
}
static inline int autogroup_path(struct task_group *tg, char *buf, int buflen)
{
return 0;
}
#endif /* CONFIG_SCHED_AUTOGROUP */
#endif /* _KERNEL_SCHED_AUTOGROUP_H */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* kretprobe_example.c
*
* Here's a sample kernel module showing the use of return probes to
* report the return value and total time taken for probed function
* to run.
*
* usage: insmod kretprobe_example.ko func=<func_name>
*
* If no func_name is specified, kernel_clone is instrumented
*
* For more information on theory of operation of kretprobes, see
* Documentation/trace/kprobes.rst
*
* Build and insert the kernel module as done in the kprobe example.
* You will see the trace data in /var/log/messages and on the console
* whenever the probed function returns. (Some messages may be suppressed
* if syslogd is configured to eliminate duplicate messages.)
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/kprobes.h>
#include <linux/ktime.h>
#include <linux/sched.h>
static char func_name[KSYM_NAME_LEN] = "kernel_clone";
module_param_string(func, func_name, KSYM_NAME_LEN, 0644);
MODULE_PARM_DESC(func, "Function to kretprobe; this module will report the"
" function's execution time");
/* per-instance private data */
struct my_data {
ktime_t entry_stamp;
};
/* Here we use the entry_handler to timestamp function entry */
static int entry_handler(struct kretprobe_instance *ri, struct pt_regs *regs)
{
struct my_data *data;
if (!current->mm)
return 1; /* Skip kernel threads */
data = (struct my_data *)ri->data;
data->entry_stamp = ktime_get();
return 0;
}
NOKPROBE_SYMBOL(entry_handler);
/*
* Return-probe handler: Log the return value and duration. Duration may turn
* out to be zero consistently, depending upon the granularity of time
* accounting on the platform.
*/
static int ret_handler(struct kretprobe_instance *ri, struct pt_regs *regs)
{
unsigned long retval = regs_return_value(regs);
struct my_data *data = (struct my_data *)ri->data;
s64 delta;
ktime_t now;
now = ktime_get();
delta = ktime_to_ns(ktime_sub(now, data->entry_stamp));
pr_info("%s returned %lu and took %lld ns to execute\n",
func_name, retval, (long long)delta);
return 0;
}
NOKPROBE_SYMBOL(ret_handler);
static struct kretprobe my_kretprobe = {
.handler = ret_handler,
.entry_handler = entry_handler,
.data_size = sizeof(struct my_data),
/* Probe up to 20 instances concurrently. */
.maxactive = 20,
};
static int __init kretprobe_init(void)
{
int ret;
my_kretprobe.kp.symbol_name = func_name;
ret = register_kretprobe(&my_kretprobe);
if (ret < 0) {
pr_err("register_kretprobe failed, returned %d\n", ret);
return ret;
}
pr_info("Planted return probe at %s: %p\n",
my_kretprobe.kp.symbol_name, my_kretprobe.kp.addr);
return 0;
}
static void __exit kretprobe_exit(void)
{
unregister_kretprobe(&my_kretprobe);
pr_info("kretprobe at %p unregistered\n", my_kretprobe.kp.addr);
/* nmissed > 0 suggests that maxactive was set too low. */
pr_info("Missed probing %d instances of %s\n",
my_kretprobe.nmissed, my_kretprobe.kp.symbol_name);
}
module_init(kretprobe_init)
module_exit(kretprobe_exit)
MODULE_DESCRIPTION("sample kernel module showing the use of return probes");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/um/include/sysdep-i386/archsetjmp.h
*/
#ifndef _KLIBC_ARCHSETJMP_H
#define _KLIBC_ARCHSETJMP_H
struct __jmp_buf {
unsigned int __ebx;
unsigned int __esp;
unsigned int __ebp;
unsigned int __esi;
unsigned int __edi;
unsigned int __eip;
};
typedef struct __jmp_buf jmp_buf[1];
#define JB_IP __eip
#define JB_SP __esp
#endif /* _SETJMP_H */
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2017 Chelsio Communications. All rights reserved.
*/
#ifndef __CUDBG_IF_H__
#define __CUDBG_IF_H__
/* Error codes */
#define CUDBG_STATUS_NO_MEM -19
#define CUDBG_STATUS_ENTITY_NOT_FOUND -24
#define CUDBG_STATUS_NOT_IMPLEMENTED -28
#define CUDBG_SYSTEM_ERROR -29
#define CUDBG_STATUS_CCLK_NOT_DEFINED -32
#define CUDBG_STATUS_PARTIAL_DATA -41
#define CUDBG_MAJOR_VERSION 1
#define CUDBG_MINOR_VERSION 14
enum cudbg_dbg_entity_type {
CUDBG_REG_DUMP = 1,
CUDBG_DEV_LOG = 2,
CUDBG_CIM_LA = 3,
CUDBG_CIM_MA_LA = 4,
CUDBG_CIM_QCFG = 5,
CUDBG_CIM_IBQ_TP0 = 6,
CUDBG_CIM_IBQ_TP1 = 7,
CUDBG_CIM_IBQ_ULP = 8,
CUDBG_CIM_IBQ_SGE0 = 9,
CUDBG_CIM_IBQ_SGE1 = 10,
CUDBG_CIM_IBQ_NCSI = 11,
CUDBG_CIM_OBQ_ULP0 = 12,
CUDBG_CIM_OBQ_ULP1 = 13,
CUDBG_CIM_OBQ_ULP2 = 14,
CUDBG_CIM_OBQ_ULP3 = 15,
CUDBG_CIM_OBQ_SGE = 16,
CUDBG_CIM_OBQ_NCSI = 17,
CUDBG_EDC0 = 18,
CUDBG_EDC1 = 19,
CUDBG_MC0 = 20,
CUDBG_MC1 = 21,
CUDBG_RSS = 22,
CUDBG_RSS_VF_CONF = 25,
CUDBG_PATH_MTU = 27,
CUDBG_PM_STATS = 30,
CUDBG_HW_SCHED = 31,
CUDBG_TP_INDIRECT = 36,
CUDBG_SGE_INDIRECT = 37,
CUDBG_ULPRX_LA = 41,
CUDBG_TP_LA = 43,
CUDBG_MEMINFO = 44,
CUDBG_CIM_PIF_LA = 45,
CUDBG_CLK = 46,
CUDBG_CIM_OBQ_RXQ0 = 47,
CUDBG_CIM_OBQ_RXQ1 = 48,
CUDBG_PCIE_INDIRECT = 50,
CUDBG_PM_INDIRECT = 51,
CUDBG_TID_INFO = 54,
CUDBG_PCIE_CONFIG = 55,
CUDBG_DUMP_CONTEXT = 56,
CUDBG_MPS_TCAM = 57,
CUDBG_VPD_DATA = 58,
CUDBG_LE_TCAM = 59,
CUDBG_CCTRL = 60,
CUDBG_MA_INDIRECT = 61,
CUDBG_ULPTX_LA = 62,
CUDBG_UP_CIM_INDIRECT = 64,
CUDBG_PBT_TABLE = 65,
CUDBG_MBOX_LOG = 66,
CUDBG_HMA_INDIRECT = 67,
CUDBG_HMA = 68,
CUDBG_QDESC = 70,
CUDBG_FLASH = 71,
CUDBG_MAX_ENTITY = 72,
};
struct cudbg_init {
struct adapter *adap; /* Pointer to adapter structure */
void *outbuf; /* Output buffer */
u32 outbuf_size; /* Output buffer size */
u8 compress_type; /* Type of compression to use */
void *compress_buff; /* Compression buffer */
u32 compress_buff_size; /* Compression buffer size */
void *workspace; /* Workspace for zlib */
};
static inline unsigned int cudbg_mbytes_to_bytes(unsigned int size)
{
return size * 1024 * 1024;
}
#endif /* __CUDBG_IF_H__ */
|
/*
* B4420 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of
* this software, even if advised of the possibility of such damage.
*/
/include/ "b4si-post.dtsi"
/* controller at 0x200000 */
&pci0 {
compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
};
&dcsr {
dcsr-epu@0 {
compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
};
dcsr-npc {
compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
};
dcsr-dpaa@9000 {
compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
};
dcsr-ocn@11000 {
compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
};
dcsr-nal@18000 {
compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
};
dcsr-rcpm@22000 {
compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
};
dcsr-snpc@30000 {
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
};
dcsr-snpc@31000 {
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
};
dcsr-cpu-sb-proxy@108000 {
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x108000 0x1000 0x109000 0x1000>;
};
};
&soc {
cpc: l3-cache-controller@10000 {
compatible = "fsl,b4420-l3-cache-controller", "cache";
};
guts: global-utilities@e0000 {
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
};
global-utilities@e1000 {
compatible = "fsl,b4420-clockgen", "fsl,b4-clockgen",
"fsl,qoriq-clockgen-2.0";
};
rcpm: global-utilities@e2000 {
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
};
L2_1: l2-cache-controller@c20000 {
compatible = "fsl,b4420-l2-cache-controller";
reg = <0xc20000 0x40000>;
next-level-cache = <&cpc>;
};
};
|
// SPDX-License-Identifier: GPL-2.0+
/*
* comedi/drivers/ni_routing/ni_device_routes/pxi-6225.c
* List of valid routes for specific NI boards.
*
* COMEDI - Linux Control and Measurement Device Interface
* Copyright (C) 2016 Spencer E. Olson <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* The contents of this file are generated using the tools in
* comedi/drivers/ni_routing/tools
*
* Please use those tools to help maintain the contents of this file.
*/
#include "../ni_device_routes.h"
#include "all.h"
struct ni_device_routes ni_pxi_6225_device_routes = {
.device = "pxi-6225",
.routes = (struct ni_route_set[]){
{
.dest = NI_PFI(0),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(1),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(2),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(3),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(4),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(5),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(6),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(7),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(8),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(9),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(10),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(11),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(12),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(13),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(14),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_PFI(15),
.src = (int[]){
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_DI_SampleClock,
NI_DO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(2),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(3),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(4),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(5),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(6),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = TRIGGER_LINE(7),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_CtrSource(0),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_AO_StartTrigger,
NI_10MHzRefClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrSource(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
PXI_Clk10,
NI_20MHzTimebase,
NI_80MHzTimebase,
NI_100kHzTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrSource(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrGate(0),
PXI_Clk10,
NI_20MHzTimebase,
NI_80MHzTimebase,
NI_100kHzTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrGate(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(1),
NI_CtrInternalOutput(1),
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrGate(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrInternalOutput(0),
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrAux(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(1),
NI_CtrGate(0),
NI_CtrInternalOutput(1),
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrAux(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrSource(0),
NI_CtrGate(0),
NI_CtrInternalOutput(0),
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrA(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrA(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrB(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrB(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrZ(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrZ(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrArmStartTrigger(0),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(1),
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_CtrArmStartTrigger(1),
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_AI_StartTrigger,
NI_AI_ReferenceTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AI_SampleClock,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClockTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AI_SampleClockTimebase,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
PXI_Clk10,
NI_20MHzTimebase,
NI_100kHzTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AI_StartTrigger,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AI_ReferenceTrigger,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AI_ConvertClock,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_ConvertClockTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AI_ConvertClockTimebase,
.src = (int[]){
NI_AI_SampleClockTimebase,
NI_20MHzTimebase,
0, /* Termination */
}
},
{
.dest = NI_AI_PauseTrigger,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AO_SampleClock,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AO_SampleClockTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AO_SampleClockTimebase,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
PXI_Clk10,
NI_20MHzTimebase,
NI_100kHzTimebase,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AO_StartTrigger,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AI_StartTrigger,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_AO_PauseTrigger,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_DI_SampleClock,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{
.dest = NI_DO_SampleClock,
.src = (int[]){
NI_PFI(0),
NI_PFI(1),
NI_PFI(2),
NI_PFI(3),
NI_PFI(4),
NI_PFI(5),
NI_PFI(6),
NI_PFI(7),
NI_PFI(8),
NI_PFI(9),
NI_PFI(10),
NI_PFI(11),
NI_PFI(12),
NI_PFI(13),
NI_PFI(14),
NI_PFI(15),
TRIGGER_LINE(0),
TRIGGER_LINE(1),
TRIGGER_LINE(2),
TRIGGER_LINE(3),
TRIGGER_LINE(4),
TRIGGER_LINE(5),
TRIGGER_LINE(6),
TRIGGER_LINE(7),
NI_CtrInternalOutput(0),
NI_CtrInternalOutput(1),
NI_AI_SampleClock,
NI_AI_ConvertClock,
NI_AO_SampleClock,
NI_FrequencyOutput,
NI_ChangeDetectionEvent,
NI_AnalogComparisonEvent,
0, /* Termination */
}
},
{ /* Termination of list */
.dest = 0,
},
},
};
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
* (https://www.khadas.com)
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
/ {
aliases {
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
};
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: regulator-vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: regulator-vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: regulator-vcc5v0-host {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vsys_5v0>;
};
vdd_log: regulator-vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vsys_3v3>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
};
vsys: regulator-vsys {
compatible = "regulator-fixed";
regulator-name = "vsys";
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: regulator-vsys-3v3 {
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys>;
};
vsys_5v0: regulator-vsys-5v0 {
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vsys>;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
linux,rc-map-name = "rc-khadas";
pinctrl-names = "default";
pinctrl-0 = <&ir_rx>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&sys_led_pin>, <&user_led_pin>;
sys_led: led-0 {
label = "sys_led";
linux,default-trigger = "heartbeat";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
};
user_led: led-1 {
label = "user_led";
default-state = "off";
gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 150 200 255>;
#cooling-cells = <2>;
fan-supply = <&vsys_5v0>;
pwms = <&pwm0 0 40000 0>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_thermal {
trips {
cpu_warm: cpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map2 {
trip = <&cpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map3 {
trip = <&cpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&gpu_thermal {
trips {
gpu_warm: gpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
gpu_hot: gpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&gpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&gpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vsys_3v3>;
vcc2-supply = <&vsys_3v3>;
vcc3-supply = <&vsys_3v3>;
vcc4-supply = <&vsys_3v3>;
vcc6-supply = <&vsys_3v3>;
vcc7-supply = <&vsys_3v3>;
vcc8-supply = <&vsys_3v3>;
vcc9-supply = <&vsys_3v3>;
vcc10-supply = <&vsys_3v3>;
vcc11-supply = <&vsys_3v3>;
vcc12-supply = <&vsys_3v3>;
vddio-supply = <&vcc_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_apio2: LDO_REG1 {
regulator-name = "vcc1v8_apio2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_vldo2: LDO_REG2 {
regulator-name = "vcc_vldo2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmupll: LDO_REG3 {
regulator-name = "vcc1v8_pmupll";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG4 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc_vldo5: LDO_REG5 {
regulator-name = "vcc_vldo5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc1v8_codec: LDO_REG7 {
regulator-name = "vcc1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpu_b_sleep>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vsys_3v3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpu_sleep>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vsys_3v3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c8 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc1v8_apio2>;
audio-supply = <&vcc1v8_codec>;
sdmmc-supply = <&vccio_sd>;
gpio1830-supply = <&vcc_3v0>;
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_1v8>;
status = "okay";
};
&pinctrl {
bt {
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_reg_on_h: bt-reg-on-h {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
ir {
ir_rx: ir-rx {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
sys_led_pin: sys-led-pin {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led_pin: user-led-pin {
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
gpu_sleep: gpu-sleep {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
/* WiFi & BT combo module Ampak AP6356S */
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
vqmmc-supply = <&vcc1v8_s3>;
vmmc-supply = <&vccio_sd>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
spiflash: flash@0 {
compatible = "winbond,w25q128fw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
};
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
vbat-supply = <&vsys_3v3>;
vddio-supply = <&vcc_1v8>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*/
/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
|
/* SPDX-License-Identifier: GPL-2.0 */
extern struct btree_geo btree_geo128;
struct btree_head128 { struct btree_head h; };
static inline void btree_init_mempool128(struct btree_head128 *head,
mempool_t *mempool)
{
btree_init_mempool(&head->h, mempool);
}
static inline int btree_init128(struct btree_head128 *head)
{
return btree_init(&head->h);
}
static inline void btree_destroy128(struct btree_head128 *head)
{
btree_destroy(&head->h);
}
static inline void *btree_lookup128(struct btree_head128 *head, u64 k1, u64 k2)
{
u64 key[2] = {k1, k2};
return btree_lookup(&head->h, &btree_geo128, (unsigned long *)&key);
}
static inline void *btree_get_prev128(struct btree_head128 *head,
u64 *k1, u64 *k2)
{
u64 key[2] = {*k1, *k2};
void *val;
val = btree_get_prev(&head->h, &btree_geo128,
(unsigned long *)&key);
*k1 = key[0];
*k2 = key[1];
return val;
}
static inline int btree_insert128(struct btree_head128 *head, u64 k1, u64 k2,
void *val, gfp_t gfp)
{
u64 key[2] = {k1, k2};
return btree_insert(&head->h, &btree_geo128,
(unsigned long *)&key, val, gfp);
}
static inline int btree_update128(struct btree_head128 *head, u64 k1, u64 k2,
void *val)
{
u64 key[2] = {k1, k2};
return btree_update(&head->h, &btree_geo128,
(unsigned long *)&key, val);
}
static inline void *btree_remove128(struct btree_head128 *head, u64 k1, u64 k2)
{
u64 key[2] = {k1, k2};
return btree_remove(&head->h, &btree_geo128, (unsigned long *)&key);
}
static inline void *btree_last128(struct btree_head128 *head, u64 *k1, u64 *k2)
{
u64 key[2];
void *val;
val = btree_last(&head->h, &btree_geo128, (unsigned long *)&key[0]);
if (val) {
*k1 = key[0];
*k2 = key[1];
}
return val;
}
static inline int btree_merge128(struct btree_head128 *target,
struct btree_head128 *victim,
gfp_t gfp)
{
return btree_merge(&target->h, &victim->h, &btree_geo128, gfp);
}
void visitor128(void *elem, unsigned long opaque, unsigned long *__key,
size_t index, void *__func);
typedef void (*visitor128_t)(void *elem, unsigned long opaque,
u64 key1, u64 key2, size_t index);
static inline size_t btree_visitor128(struct btree_head128 *head,
unsigned long opaque,
visitor128_t func2)
{
return btree_visitor(&head->h, &btree_geo128, opaque,
visitor128, func2);
}
static inline size_t btree_grim_visitor128(struct btree_head128 *head,
unsigned long opaque,
visitor128_t func2)
{
return btree_grim_visitor(&head->h, &btree_geo128, opaque,
visitor128, func2);
}
#define btree_for_each_safe128(head, k1, k2, val) \
for (val = btree_last128(head, &k1, &k2); \
val; \
val = btree_get_prev128(head, &k1, &k2))
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* mchp23k256.c
*
* Driver for Microchip 23k256 SPI RAM chips
*
* Copyright © 2016 Andrew Lunn <[email protected]>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mutex.h>
#include <linux/sched.h>
#include <linux/sizes.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/of.h>
#define MAX_CMD_SIZE 4
struct mchp23_caps {
u8 addr_width;
unsigned int size;
};
struct mchp23k256_flash {
struct spi_device *spi;
struct mutex lock;
struct mtd_info mtd;
const struct mchp23_caps *caps;
};
#define MCHP23K256_CMD_WRITE_STATUS 0x01
#define MCHP23K256_CMD_WRITE 0x02
#define MCHP23K256_CMD_READ 0x03
#define MCHP23K256_MODE_SEQ BIT(6)
#define to_mchp23k256_flash(x) container_of(x, struct mchp23k256_flash, mtd)
static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash,
unsigned int addr, u8 *cmd)
{
int i;
/*
* Address is sent in big endian (MSB first) and we skip
* the first entry of the cmd array which contains the cmd
* opcode.
*/
for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8)
cmd[i] = addr;
}
static int mchp23k256_cmdsz(struct mchp23k256_flash *flash)
{
return 1 + flash->caps->addr_width;
}
static int mchp23k256_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const unsigned char *buf)
{
struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
struct spi_transfer transfer[2] = {};
struct spi_message message;
unsigned char command[MAX_CMD_SIZE];
int ret, cmd_len;
spi_message_init(&message);
cmd_len = mchp23k256_cmdsz(flash);
command[0] = MCHP23K256_CMD_WRITE;
mchp23k256_addr2cmd(flash, to, command);
transfer[0].tx_buf = command;
transfer[0].len = cmd_len;
spi_message_add_tail(&transfer[0], &message);
transfer[1].tx_buf = buf;
transfer[1].len = len;
spi_message_add_tail(&transfer[1], &message);
mutex_lock(&flash->lock);
ret = spi_sync(flash->spi, &message);
mutex_unlock(&flash->lock);
if (ret)
return ret;
if (retlen && message.actual_length > cmd_len)
*retlen += message.actual_length - cmd_len;
return 0;
}
static int mchp23k256_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, unsigned char *buf)
{
struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
struct spi_transfer transfer[2] = {};
struct spi_message message;
unsigned char command[MAX_CMD_SIZE];
int ret, cmd_len;
spi_message_init(&message);
cmd_len = mchp23k256_cmdsz(flash);
memset(&transfer, 0, sizeof(transfer));
command[0] = MCHP23K256_CMD_READ;
mchp23k256_addr2cmd(flash, from, command);
transfer[0].tx_buf = command;
transfer[0].len = cmd_len;
spi_message_add_tail(&transfer[0], &message);
transfer[1].rx_buf = buf;
transfer[1].len = len;
spi_message_add_tail(&transfer[1], &message);
mutex_lock(&flash->lock);
ret = spi_sync(flash->spi, &message);
mutex_unlock(&flash->lock);
if (ret)
return ret;
if (retlen && message.actual_length > cmd_len)
*retlen += message.actual_length - cmd_len;
return 0;
}
/*
* Set the device into sequential mode. This allows read/writes to the
* entire SRAM in a single operation
*/
static int mchp23k256_set_mode(struct spi_device *spi)
{
struct spi_transfer transfer = {};
struct spi_message message;
unsigned char command[2];
spi_message_init(&message);
command[0] = MCHP23K256_CMD_WRITE_STATUS;
command[1] = MCHP23K256_MODE_SEQ;
transfer.tx_buf = command;
transfer.len = sizeof(command);
spi_message_add_tail(&transfer, &message);
return spi_sync(spi, &message);
}
static const struct mchp23_caps mchp23k256_caps = {
.size = SZ_32K,
.addr_width = 2,
};
static const struct mchp23_caps mchp23lcv1024_caps = {
.size = SZ_128K,
.addr_width = 3,
};
static int mchp23k256_probe(struct spi_device *spi)
{
struct mchp23k256_flash *flash;
struct flash_platform_data *data;
int err;
flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
if (!flash)
return -ENOMEM;
flash->spi = spi;
mutex_init(&flash->lock);
spi_set_drvdata(spi, flash);
err = mchp23k256_set_mode(spi);
if (err)
return err;
data = dev_get_platdata(&spi->dev);
flash->caps = of_device_get_match_data(&spi->dev);
if (!flash->caps)
flash->caps = &mchp23k256_caps;
mtd_set_of_node(&flash->mtd, spi->dev.of_node);
flash->mtd.dev.parent = &spi->dev;
flash->mtd.type = MTD_RAM;
flash->mtd.flags = MTD_CAP_RAM;
flash->mtd.writesize = 1;
flash->mtd.size = flash->caps->size;
flash->mtd._read = mchp23k256_read;
flash->mtd._write = mchp23k256_write;
err = mtd_device_register(&flash->mtd, data ? data->parts : NULL,
data ? data->nr_parts : 0);
if (err)
return err;
return 0;
}
static void mchp23k256_remove(struct spi_device *spi)
{
struct mchp23k256_flash *flash = spi_get_drvdata(spi);
WARN_ON(mtd_device_unregister(&flash->mtd));
}
static const struct of_device_id mchp23k256_of_table[] = {
{
.compatible = "microchip,mchp23k256",
.data = &mchp23k256_caps,
},
{
.compatible = "microchip,mchp23lcv1024",
.data = &mchp23lcv1024_caps,
},
{}
};
MODULE_DEVICE_TABLE(of, mchp23k256_of_table);
static const struct spi_device_id mchp23k256_spi_ids[] = {
{
.name = "mchp23k256",
.driver_data = (kernel_ulong_t)&mchp23k256_caps,
},
{
.name = "mchp23lcv1024",
.driver_data = (kernel_ulong_t)&mchp23lcv1024_caps,
},
{}
};
MODULE_DEVICE_TABLE(spi, mchp23k256_spi_ids);
static struct spi_driver mchp23k256_driver = {
.driver = {
.name = "mchp23k256",
.of_match_table = mchp23k256_of_table,
},
.probe = mchp23k256_probe,
.remove = mchp23k256_remove,
.id_table = mchp23k256_spi_ids,
};
module_spi_driver(mchp23k256_driver);
MODULE_DESCRIPTION("MTD SPI driver for MCHP23K256 RAM chips");
MODULE_AUTHOR("Andrew Lunn <[email protected]>");
MODULE_LICENSE("GPL v2");
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* SCTP kernel implementation
* (C) Copyright IBM Corp. 2001, 2004
* Copyright (c) 1999-2000 Cisco, Inc.
* Copyright (c) 1999-2001 Motorola, Inc.
* Copyright (c) 2001 Intel Corp.
* Copyright (c) 2001 La Monte H.P. Yarroll
*
* This file is part of the SCTP kernel implementation
*
* This module provides the abstraction for an SCTP association.
*
* Please send any bug reports or fixes you make to the
* email address(es):
* lksctp developers <[email protected]>
*
* Written or modified by:
* La Monte H.P. Yarroll <[email protected]>
* Karl Knutson <[email protected]>
* Jon Grimm <[email protected]>
* Xingang Guo <[email protected]>
* Hui Huang <[email protected]>
* Sridhar Samudrala <[email protected]>
* Daisy Chang <[email protected]>
* Ryan Layer <[email protected]>
* Kevin Gao <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/in.h>
#include <net/ipv6.h>
#include <net/sctp/sctp.h>
#include <net/sctp/sm.h>
/* Forward declarations for internal functions. */
static void sctp_select_active_and_retran_path(struct sctp_association *asoc);
static void sctp_assoc_bh_rcv(struct work_struct *work);
static void sctp_assoc_free_asconf_acks(struct sctp_association *asoc);
static void sctp_assoc_free_asconf_queue(struct sctp_association *asoc);
/* 1st Level Abstractions. */
/* Initialize a new association from provided memory. */
static struct sctp_association *sctp_association_init(
struct sctp_association *asoc,
const struct sctp_endpoint *ep,
const struct sock *sk,
enum sctp_scope scope, gfp_t gfp)
{
struct sctp_sock *sp;
struct sctp_paramhdr *p;
int i;
/* Retrieve the SCTP per socket area. */
sp = sctp_sk((struct sock *)sk);
/* Discarding const is appropriate here. */
asoc->ep = (struct sctp_endpoint *)ep;
asoc->base.sk = (struct sock *)sk;
asoc->base.net = sock_net(sk);
sctp_endpoint_hold(asoc->ep);
sock_hold(asoc->base.sk);
/* Initialize the common base substructure. */
asoc->base.type = SCTP_EP_TYPE_ASSOCIATION;
/* Initialize the object handling fields. */
refcount_set(&asoc->base.refcnt, 1);
/* Initialize the bind addr area. */
sctp_bind_addr_init(&asoc->base.bind_addr, ep->base.bind_addr.port);
asoc->state = SCTP_STATE_CLOSED;
asoc->cookie_life = ms_to_ktime(sp->assocparams.sasoc_cookie_life);
asoc->user_frag = sp->user_frag;
/* Set the association max_retrans and RTO values from the
* socket values.
*/
asoc->max_retrans = sp->assocparams.sasoc_asocmaxrxt;
asoc->pf_retrans = sp->pf_retrans;
asoc->ps_retrans = sp->ps_retrans;
asoc->pf_expose = sp->pf_expose;
asoc->rto_initial = msecs_to_jiffies(sp->rtoinfo.srto_initial);
asoc->rto_max = msecs_to_jiffies(sp->rtoinfo.srto_max);
asoc->rto_min = msecs_to_jiffies(sp->rtoinfo.srto_min);
/* Initialize the association's heartbeat interval based on the
* sock configured value.
*/
asoc->hbinterval = msecs_to_jiffies(sp->hbinterval);
asoc->probe_interval = msecs_to_jiffies(sp->probe_interval);
asoc->encap_port = sp->encap_port;
/* Initialize path max retrans value. */
asoc->pathmaxrxt = sp->pathmaxrxt;
asoc->flowlabel = sp->flowlabel;
asoc->dscp = sp->dscp;
/* Set association default SACK delay */
asoc->sackdelay = msecs_to_jiffies(sp->sackdelay);
asoc->sackfreq = sp->sackfreq;
/* Set the association default flags controlling
* Heartbeat, SACK delay, and Path MTU Discovery.
*/
asoc->param_flags = sp->param_flags;
/* Initialize the maximum number of new data packets that can be sent
* in a burst.
*/
asoc->max_burst = sp->max_burst;
asoc->subscribe = sp->subscribe;
/* initialize association timers */
asoc->timeouts[SCTP_EVENT_TIMEOUT_T1_COOKIE] = asoc->rto_initial;
asoc->timeouts[SCTP_EVENT_TIMEOUT_T1_INIT] = asoc->rto_initial;
asoc->timeouts[SCTP_EVENT_TIMEOUT_T2_SHUTDOWN] = asoc->rto_initial;
/* sctpimpguide Section 2.12.2
* If the 'T5-shutdown-guard' timer is used, it SHOULD be set to the
* recommended value of 5 times 'RTO.Max'.
*/
asoc->timeouts[SCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD]
= 5 * asoc->rto_max;
asoc->timeouts[SCTP_EVENT_TIMEOUT_SACK] = asoc->sackdelay;
asoc->timeouts[SCTP_EVENT_TIMEOUT_AUTOCLOSE] = sp->autoclose * HZ;
/* Initializes the timers */
for (i = SCTP_EVENT_TIMEOUT_NONE; i < SCTP_NUM_TIMEOUT_TYPES; ++i)
timer_setup(&asoc->timers[i], sctp_timer_events[i], 0);
/* Pull default initialization values from the sock options.
* Note: This assumes that the values have already been
* validated in the sock.
*/
asoc->c.sinit_max_instreams = sp->initmsg.sinit_max_instreams;
asoc->c.sinit_num_ostreams = sp->initmsg.sinit_num_ostreams;
asoc->max_init_attempts = sp->initmsg.sinit_max_attempts;
asoc->max_init_timeo =
msecs_to_jiffies(sp->initmsg.sinit_max_init_timeo);
/* Set the local window size for receive.
* This is also the rcvbuf space per association.
* RFC 6 - A SCTP receiver MUST be able to receive a minimum of
* 1500 bytes in one SCTP packet.
*/
if ((sk->sk_rcvbuf/2) < SCTP_DEFAULT_MINWINDOW)
asoc->rwnd = SCTP_DEFAULT_MINWINDOW;
else
asoc->rwnd = sk->sk_rcvbuf/2;
asoc->a_rwnd = asoc->rwnd;
/* Use my own max window until I learn something better. */
asoc->peer.rwnd = SCTP_DEFAULT_MAXWINDOW;
/* Initialize the receive memory counter */
atomic_set(&asoc->rmem_alloc, 0);
init_waitqueue_head(&asoc->wait);
asoc->c.my_vtag = sctp_generate_tag(ep);
asoc->c.my_port = ep->base.bind_addr.port;
asoc->c.initial_tsn = sctp_generate_tsn(ep);
asoc->next_tsn = asoc->c.initial_tsn;
asoc->ctsn_ack_point = asoc->next_tsn - 1;
asoc->adv_peer_ack_point = asoc->ctsn_ack_point;
asoc->highest_sacked = asoc->ctsn_ack_point;
asoc->last_cwr_tsn = asoc->ctsn_ack_point;
/* ADDIP Section 4.1 Asconf Chunk Procedures
*
* When an endpoint has an ASCONF signaled change to be sent to the
* remote endpoint it should do the following:
* ...
* A2) a serial number should be assigned to the chunk. The serial
* number SHOULD be a monotonically increasing number. The serial
* numbers SHOULD be initialized at the start of the
* association to the same value as the initial TSN.
*/
asoc->addip_serial = asoc->c.initial_tsn;
asoc->strreset_outseq = asoc->c.initial_tsn;
INIT_LIST_HEAD(&asoc->addip_chunk_list);
INIT_LIST_HEAD(&asoc->asconf_ack_list);
/* Make an empty list of remote transport addresses. */
INIT_LIST_HEAD(&asoc->peer.transport_addr_list);
/* RFC 2960 5.1 Normal Establishment of an Association
*
* After the reception of the first data chunk in an
* association the endpoint must immediately respond with a
* sack to acknowledge the data chunk. Subsequent
* acknowledgements should be done as described in Section
* 6.2.
*
* [We implement this by telling a new association that it
* already received one packet.]
*/
asoc->peer.sack_needed = 1;
asoc->peer.sack_generation = 1;
/* Create an input queue. */
sctp_inq_init(&asoc->base.inqueue);
sctp_inq_set_th_handler(&asoc->base.inqueue, sctp_assoc_bh_rcv);
/* Create an output queue. */
sctp_outq_init(asoc, &asoc->outqueue);
sctp_ulpq_init(&asoc->ulpq, asoc);
if (sctp_stream_init(&asoc->stream, asoc->c.sinit_num_ostreams, 0, gfp))
goto stream_free;
/* Initialize default path MTU. */
asoc->pathmtu = sp->pathmtu;
sctp_assoc_update_frag_point(asoc);
/* Assume that peer would support both address types unless we are
* told otherwise.
*/
asoc->peer.ipv4_address = 1;
if (asoc->base.sk->sk_family == PF_INET6)
asoc->peer.ipv6_address = 1;
INIT_LIST_HEAD(&asoc->asocs);
asoc->default_stream = sp->default_stream;
asoc->default_ppid = sp->default_ppid;
asoc->default_flags = sp->default_flags;
asoc->default_context = sp->default_context;
asoc->default_timetolive = sp->default_timetolive;
asoc->default_rcv_context = sp->default_rcv_context;
/* AUTH related initializations */
INIT_LIST_HEAD(&asoc->endpoint_shared_keys);
if (sctp_auth_asoc_copy_shkeys(ep, asoc, gfp))
goto stream_free;
asoc->active_key_id = ep->active_key_id;
asoc->strreset_enable = ep->strreset_enable;
/* Save the hmacs and chunks list into this association */
if (ep->auth_hmacs_list)
memcpy(asoc->c.auth_hmacs, ep->auth_hmacs_list,
ntohs(ep->auth_hmacs_list->param_hdr.length));
if (ep->auth_chunk_list)
memcpy(asoc->c.auth_chunks, ep->auth_chunk_list,
ntohs(ep->auth_chunk_list->param_hdr.length));
/* Get the AUTH random number for this association */
p = (struct sctp_paramhdr *)asoc->c.auth_random;
p->type = SCTP_PARAM_RANDOM;
p->length = htons(sizeof(*p) + SCTP_AUTH_RANDOM_LENGTH);
get_random_bytes(p+1, SCTP_AUTH_RANDOM_LENGTH);
return asoc;
stream_free:
sctp_stream_free(&asoc->stream);
sock_put(asoc->base.sk);
sctp_endpoint_put(asoc->ep);
return NULL;
}
/* Allocate and initialize a new association */
struct sctp_association *sctp_association_new(const struct sctp_endpoint *ep,
const struct sock *sk,
enum sctp_scope scope, gfp_t gfp)
{
struct sctp_association *asoc;
asoc = kzalloc(sizeof(*asoc), gfp);
if (!asoc)
goto fail;
if (!sctp_association_init(asoc, ep, sk, scope, gfp))
goto fail_init;
SCTP_DBG_OBJCNT_INC(assoc);
pr_debug("Created asoc %p\n", asoc);
return asoc;
fail_init:
kfree(asoc);
fail:
return NULL;
}
/* Free this association if possible. There may still be users, so
* the actual deallocation may be delayed.
*/
void sctp_association_free(struct sctp_association *asoc)
{
struct sock *sk = asoc->base.sk;
struct sctp_transport *transport;
struct list_head *pos, *temp;
int i;
/* Only real associations count against the endpoint, so
* don't bother for if this is a temporary association.
*/
if (!list_empty(&asoc->asocs)) {
list_del(&asoc->asocs);
/* Decrement the backlog value for a TCP-style listening
* socket.
*/
if (sctp_style(sk, TCP) && sctp_sstate(sk, LISTENING))
sk_acceptq_removed(sk);
}
/* Mark as dead, so other users can know this structure is
* going away.
*/
asoc->base.dead = true;
/* Dispose of any data lying around in the outqueue. */
sctp_outq_free(&asoc->outqueue);
/* Dispose of any pending messages for the upper layer. */
sctp_ulpq_free(&asoc->ulpq);
/* Dispose of any pending chunks on the inqueue. */
sctp_inq_free(&asoc->base.inqueue);
sctp_tsnmap_free(&asoc->peer.tsn_map);
/* Free stream information. */
sctp_stream_free(&asoc->stream);
if (asoc->strreset_chunk)
sctp_chunk_free(asoc->strreset_chunk);
/* Clean up the bound address list. */
sctp_bind_addr_free(&asoc->base.bind_addr);
/* Do we need to go through all of our timers and
* delete them? To be safe we will try to delete all, but we
* should be able to go through and make a guess based
* on our state.
*/
for (i = SCTP_EVENT_TIMEOUT_NONE; i < SCTP_NUM_TIMEOUT_TYPES; ++i) {
if (del_timer(&asoc->timers[i]))
sctp_association_put(asoc);
}
/* Free peer's cached cookie. */
kfree(asoc->peer.cookie);
kfree(asoc->peer.peer_random);
kfree(asoc->peer.peer_chunks);
kfree(asoc->peer.peer_hmacs);
/* Release the transport structures. */
list_for_each_safe(pos, temp, &asoc->peer.transport_addr_list) {
transport = list_entry(pos, struct sctp_transport, transports);
list_del_rcu(pos);
sctp_unhash_transport(transport);
sctp_transport_free(transport);
}
asoc->peer.transport_count = 0;
sctp_asconf_queue_teardown(asoc);
/* Free pending address space being deleted */
kfree(asoc->asconf_addr_del_pending);
/* AUTH - Free the endpoint shared keys */
sctp_auth_destroy_keys(&asoc->endpoint_shared_keys);
/* AUTH - Free the association shared key */
sctp_auth_key_put(asoc->asoc_shared_key);
sctp_association_put(asoc);
}
/* Cleanup and free up an association. */
static void sctp_association_destroy(struct sctp_association *asoc)
{
if (unlikely(!asoc->base.dead)) {
WARN(1, "Attempt to destroy undead association %p!\n", asoc);
return;
}
sctp_endpoint_put(asoc->ep);
sock_put(asoc->base.sk);
if (asoc->assoc_id != 0) {
spin_lock_bh(&sctp_assocs_id_lock);
idr_remove(&sctp_assocs_id, asoc->assoc_id);
spin_unlock_bh(&sctp_assocs_id_lock);
}
WARN_ON(atomic_read(&asoc->rmem_alloc));
kfree_rcu(asoc, rcu);
SCTP_DBG_OBJCNT_DEC(assoc);
}
/* Change the primary destination address for the peer. */
void sctp_assoc_set_primary(struct sctp_association *asoc,
struct sctp_transport *transport)
{
int changeover = 0;
/* it's a changeover only if we already have a primary path
* that we are changing
*/
if (asoc->peer.primary_path != NULL &&
asoc->peer.primary_path != transport)
changeover = 1 ;
asoc->peer.primary_path = transport;
sctp_ulpevent_notify_peer_addr_change(transport,
SCTP_ADDR_MADE_PRIM, 0);
/* Set a default msg_name for events. */
memcpy(&asoc->peer.primary_addr, &transport->ipaddr,
sizeof(union sctp_addr));
/* If the primary path is changing, assume that the
* user wants to use this new path.
*/
if ((transport->state == SCTP_ACTIVE) ||
(transport->state == SCTP_UNKNOWN))
asoc->peer.active_path = transport;
/*
* SFR-CACC algorithm:
* Upon the receipt of a request to change the primary
* destination address, on the data structure for the new
* primary destination, the sender MUST do the following:
*
* 1) If CHANGEOVER_ACTIVE is set, then there was a switch
* to this destination address earlier. The sender MUST set
* CYCLING_CHANGEOVER to indicate that this switch is a
* double switch to the same destination address.
*
* Really, only bother is we have data queued or outstanding on
* the association.
*/
if (!asoc->outqueue.outstanding_bytes && !asoc->outqueue.out_qlen)
return;
if (transport->cacc.changeover_active)
transport->cacc.cycling_changeover = changeover;
/* 2) The sender MUST set CHANGEOVER_ACTIVE to indicate that
* a changeover has occurred.
*/
transport->cacc.changeover_active = changeover;
/* 3) The sender MUST store the next TSN to be sent in
* next_tsn_at_change.
*/
transport->cacc.next_tsn_at_change = asoc->next_tsn;
}
/* Remove a transport from an association. */
void sctp_assoc_rm_peer(struct sctp_association *asoc,
struct sctp_transport *peer)
{
struct sctp_transport *transport;
struct list_head *pos;
struct sctp_chunk *ch;
pr_debug("%s: association:%p addr:%pISpc\n",
__func__, asoc, &peer->ipaddr.sa);
/* If we are to remove the current retran_path, update it
* to the next peer before removing this peer from the list.
*/
if (asoc->peer.retran_path == peer)
sctp_assoc_update_retran_path(asoc);
/* Remove this peer from the list. */
list_del_rcu(&peer->transports);
/* Remove this peer from the transport hashtable */
sctp_unhash_transport(peer);
/* Get the first transport of asoc. */
pos = asoc->peer.transport_addr_list.next;
transport = list_entry(pos, struct sctp_transport, transports);
/* Update any entries that match the peer to be deleted. */
if (asoc->peer.primary_path == peer)
sctp_assoc_set_primary(asoc, transport);
if (asoc->peer.active_path == peer)
asoc->peer.active_path = transport;
if (asoc->peer.retran_path == peer)
asoc->peer.retran_path = transport;
if (asoc->peer.last_data_from == peer)
asoc->peer.last_data_from = transport;
if (asoc->strreset_chunk &&
asoc->strreset_chunk->transport == peer) {
asoc->strreset_chunk->transport = transport;
sctp_transport_reset_reconf_timer(transport);
}
/* If we remove the transport an INIT was last sent to, set it to
* NULL. Combined with the update of the retran path above, this
* will cause the next INIT to be sent to the next available
* transport, maintaining the cycle.
*/
if (asoc->init_last_sent_to == peer)
asoc->init_last_sent_to = NULL;
/* If we remove the transport an SHUTDOWN was last sent to, set it
* to NULL. Combined with the update of the retran path above, this
* will cause the next SHUTDOWN to be sent to the next available
* transport, maintaining the cycle.
*/
if (asoc->shutdown_last_sent_to == peer)
asoc->shutdown_last_sent_to = NULL;
/* If we remove the transport an ASCONF was last sent to, set it to
* NULL.
*/
if (asoc->addip_last_asconf &&
asoc->addip_last_asconf->transport == peer)
asoc->addip_last_asconf->transport = NULL;
/* If we have something on the transmitted list, we have to
* save it off. The best place is the active path.
*/
if (!list_empty(&peer->transmitted)) {
struct sctp_transport *active = asoc->peer.active_path;
/* Reset the transport of each chunk on this list */
list_for_each_entry(ch, &peer->transmitted,
transmitted_list) {
ch->transport = NULL;
ch->rtt_in_progress = 0;
}
list_splice_tail_init(&peer->transmitted,
&active->transmitted);
/* Start a T3 timer here in case it wasn't running so
* that these migrated packets have a chance to get
* retransmitted.
*/
if (!timer_pending(&active->T3_rtx_timer))
if (!mod_timer(&active->T3_rtx_timer,
jiffies + active->rto))
sctp_transport_hold(active);
}
list_for_each_entry(ch, &asoc->outqueue.out_chunk_list, list)
if (ch->transport == peer)
ch->transport = NULL;
asoc->peer.transport_count--;
sctp_ulpevent_notify_peer_addr_change(peer, SCTP_ADDR_REMOVED, 0);
sctp_transport_free(peer);
}
/* Add a transport address to an association. */
struct sctp_transport *sctp_assoc_add_peer(struct sctp_association *asoc,
const union sctp_addr *addr,
const gfp_t gfp,
const int peer_state)
{
struct sctp_transport *peer;
struct sctp_sock *sp;
unsigned short port;
sp = sctp_sk(asoc->base.sk);
/* AF_INET and AF_INET6 share common port field. */
port = ntohs(addr->v4.sin_port);
pr_debug("%s: association:%p addr:%pISpc state:%d\n", __func__,
asoc, &addr->sa, peer_state);
/* Set the port if it has not been set yet. */
if (0 == asoc->peer.port)
asoc->peer.port = port;
/* Check to see if this is a duplicate. */
peer = sctp_assoc_lookup_paddr(asoc, addr);
if (peer) {
/* An UNKNOWN state is only set on transports added by
* user in sctp_connectx() call. Such transports should be
* considered CONFIRMED per RFC 4960, Section 5.4.
*/
if (peer->state == SCTP_UNKNOWN) {
peer->state = SCTP_ACTIVE;
}
return peer;
}
peer = sctp_transport_new(asoc->base.net, addr, gfp);
if (!peer)
return NULL;
sctp_transport_set_owner(peer, asoc);
/* Initialize the peer's heartbeat interval based on the
* association configured value.
*/
peer->hbinterval = asoc->hbinterval;
peer->probe_interval = asoc->probe_interval;
peer->encap_port = asoc->encap_port;
/* Set the path max_retrans. */
peer->pathmaxrxt = asoc->pathmaxrxt;
/* And the partial failure retrans threshold */
peer->pf_retrans = asoc->pf_retrans;
/* And the primary path switchover retrans threshold */
peer->ps_retrans = asoc->ps_retrans;
/* Initialize the peer's SACK delay timeout based on the
* association configured value.
*/
peer->sackdelay = asoc->sackdelay;
peer->sackfreq = asoc->sackfreq;
if (addr->sa.sa_family == AF_INET6) {
__be32 info = addr->v6.sin6_flowinfo;
if (info) {
peer->flowlabel = ntohl(info & IPV6_FLOWLABEL_MASK);
peer->flowlabel |= SCTP_FLOWLABEL_SET_MASK;
} else {
peer->flowlabel = asoc->flowlabel;
}
}
peer->dscp = asoc->dscp;
/* Enable/disable heartbeat, SACK delay, and path MTU discovery
* based on association setting.
*/
peer->param_flags = asoc->param_flags;
/* Initialize the pmtu of the transport. */
sctp_transport_route(peer, NULL, sp);
/* If this is the first transport addr on this association,
* initialize the association PMTU to the peer's PMTU.
* If not and the current association PMTU is higher than the new
* peer's PMTU, reset the association PMTU to the new peer's PMTU.
*/
sctp_assoc_set_pmtu(asoc, asoc->pathmtu ?
min_t(int, peer->pathmtu, asoc->pathmtu) :
peer->pathmtu);
peer->pmtu_pending = 0;
/* The asoc->peer.port might not be meaningful yet, but
* initialize the packet structure anyway.
*/
sctp_packet_init(&peer->packet, peer, asoc->base.bind_addr.port,
asoc->peer.port);
/* 7.2.1 Slow-Start
*
* o The initial cwnd before DATA transmission or after a sufficiently
* long idle period MUST be set to
* min(4*MTU, max(2*MTU, 4380 bytes))
*
* o The initial value of ssthresh MAY be arbitrarily high
* (for example, implementations MAY use the size of the
* receiver advertised window).
*/
peer->cwnd = min(4*asoc->pathmtu, max_t(__u32, 2*asoc->pathmtu, 4380));
/* At this point, we may not have the receiver's advertised window,
* so initialize ssthresh to the default value and it will be set
* later when we process the INIT.
*/
peer->ssthresh = SCTP_DEFAULT_MAXWINDOW;
peer->partial_bytes_acked = 0;
peer->flight_size = 0;
peer->burst_limited = 0;
/* Set the transport's RTO.initial value */
peer->rto = asoc->rto_initial;
sctp_max_rto(asoc, peer);
/* Set the peer's active state. */
peer->state = peer_state;
/* Add this peer into the transport hashtable */
if (sctp_hash_transport(peer)) {
sctp_transport_free(peer);
return NULL;
}
sctp_transport_pl_reset(peer);
/* Attach the remote transport to our asoc. */
list_add_tail_rcu(&peer->transports, &asoc->peer.transport_addr_list);
asoc->peer.transport_count++;
sctp_ulpevent_notify_peer_addr_change(peer, SCTP_ADDR_ADDED, 0);
/* If we do not yet have a primary path, set one. */
if (!asoc->peer.primary_path) {
sctp_assoc_set_primary(asoc, peer);
asoc->peer.retran_path = peer;
}
if (asoc->peer.active_path == asoc->peer.retran_path &&
peer->state != SCTP_UNCONFIRMED) {
asoc->peer.retran_path = peer;
}
return peer;
}
/* Delete a transport address from an association. */
void sctp_assoc_del_peer(struct sctp_association *asoc,
const union sctp_addr *addr)
{
struct list_head *pos;
struct list_head *temp;
struct sctp_transport *transport;
list_for_each_safe(pos, temp, &asoc->peer.transport_addr_list) {
transport = list_entry(pos, struct sctp_transport, transports);
if (sctp_cmp_addr_exact(addr, &transport->ipaddr)) {
/* Do book keeping for removing the peer and free it. */
sctp_assoc_rm_peer(asoc, transport);
break;
}
}
}
/* Lookup a transport by address. */
struct sctp_transport *sctp_assoc_lookup_paddr(
const struct sctp_association *asoc,
const union sctp_addr *address)
{
struct sctp_transport *t;
/* Cycle through all transports searching for a peer address. */
list_for_each_entry(t, &asoc->peer.transport_addr_list,
transports) {
if (sctp_cmp_addr_exact(address, &t->ipaddr))
return t;
}
return NULL;
}
/* Remove all transports except a give one */
void sctp_assoc_del_nonprimary_peers(struct sctp_association *asoc,
struct sctp_transport *primary)
{
struct sctp_transport *temp;
struct sctp_transport *t;
list_for_each_entry_safe(t, temp, &asoc->peer.transport_addr_list,
transports) {
/* if the current transport is not the primary one, delete it */
if (t != primary)
sctp_assoc_rm_peer(asoc, t);
}
}
/* Engage in transport control operations.
* Mark the transport up or down and send a notification to the user.
* Select and update the new active and retran paths.
*/
void sctp_assoc_control_transport(struct sctp_association *asoc,
struct sctp_transport *transport,
enum sctp_transport_cmd command,
sctp_sn_error_t error)
{
int spc_state = SCTP_ADDR_AVAILABLE;
bool ulp_notify = true;
/* Record the transition on the transport. */
switch (command) {
case SCTP_TRANSPORT_UP:
/* If we are moving from UNCONFIRMED state due
* to heartbeat success, report the SCTP_ADDR_CONFIRMED
* state to the user, otherwise report SCTP_ADDR_AVAILABLE.
*/
if (transport->state == SCTP_PF &&
asoc->pf_expose != SCTP_PF_EXPOSE_ENABLE)
ulp_notify = false;
else if (transport->state == SCTP_UNCONFIRMED &&
error == SCTP_HEARTBEAT_SUCCESS)
spc_state = SCTP_ADDR_CONFIRMED;
transport->state = SCTP_ACTIVE;
sctp_transport_pl_reset(transport);
break;
case SCTP_TRANSPORT_DOWN:
/* If the transport was never confirmed, do not transition it
* to inactive state. Also, release the cached route since
* there may be a better route next time.
*/
if (transport->state != SCTP_UNCONFIRMED) {
transport->state = SCTP_INACTIVE;
sctp_transport_pl_reset(transport);
spc_state = SCTP_ADDR_UNREACHABLE;
} else {
sctp_transport_dst_release(transport);
ulp_notify = false;
}
break;
case SCTP_TRANSPORT_PF:
transport->state = SCTP_PF;
if (asoc->pf_expose != SCTP_PF_EXPOSE_ENABLE)
ulp_notify = false;
else
spc_state = SCTP_ADDR_POTENTIALLY_FAILED;
break;
default:
return;
}
/* Generate and send a SCTP_PEER_ADDR_CHANGE notification
* to the user.
*/
if (ulp_notify)
sctp_ulpevent_notify_peer_addr_change(transport,
spc_state, error);
/* Select new active and retran paths. */
sctp_select_active_and_retran_path(asoc);
}
/* Hold a reference to an association. */
void sctp_association_hold(struct sctp_association *asoc)
{
refcount_inc(&asoc->base.refcnt);
}
/* Release a reference to an association and cleanup
* if there are no more references.
*/
void sctp_association_put(struct sctp_association *asoc)
{
if (refcount_dec_and_test(&asoc->base.refcnt))
sctp_association_destroy(asoc);
}
/* Allocate the next TSN, Transmission Sequence Number, for the given
* association.
*/
__u32 sctp_association_get_next_tsn(struct sctp_association *asoc)
{
/* From Section 1.6 Serial Number Arithmetic:
* Transmission Sequence Numbers wrap around when they reach
* 2**32 - 1. That is, the next TSN a DATA chunk MUST use
* after transmitting TSN = 2*32 - 1 is TSN = 0.
*/
__u32 retval = asoc->next_tsn;
asoc->next_tsn++;
asoc->unack_data++;
return retval;
}
/* Compare two addresses to see if they match. Wildcard addresses
* only match themselves.
*/
int sctp_cmp_addr_exact(const union sctp_addr *ss1,
const union sctp_addr *ss2)
{
struct sctp_af *af;
af = sctp_get_af_specific(ss1->sa.sa_family);
if (unlikely(!af))
return 0;
return af->cmp_addr(ss1, ss2);
}
/* Return an ecne chunk to get prepended to a packet.
* Note: We are sly and return a shared, prealloced chunk. FIXME:
* No we don't, but we could/should.
*/
struct sctp_chunk *sctp_get_ecne_prepend(struct sctp_association *asoc)
{
if (!asoc->need_ecne)
return NULL;
/* Send ECNE if needed.
* Not being able to allocate a chunk here is not deadly.
*/
return sctp_make_ecne(asoc, asoc->last_ecne_tsn);
}
/*
* Find which transport this TSN was sent on.
*/
struct sctp_transport *sctp_assoc_lookup_tsn(struct sctp_association *asoc,
__u32 tsn)
{
struct sctp_transport *active;
struct sctp_transport *match;
struct sctp_transport *transport;
struct sctp_chunk *chunk;
__be32 key = htonl(tsn);
match = NULL;
/*
* FIXME: In general, find a more efficient data structure for
* searching.
*/
/*
* The general strategy is to search each transport's transmitted
* list. Return which transport this TSN lives on.
*
* Let's be hopeful and check the active_path first.
* Another optimization would be to know if there is only one
* outbound path and not have to look for the TSN at all.
*
*/
active = asoc->peer.active_path;
list_for_each_entry(chunk, &active->transmitted,
transmitted_list) {
if (key == chunk->subh.data_hdr->tsn) {
match = active;
goto out;
}
}
/* If not found, go search all the other transports. */
list_for_each_entry(transport, &asoc->peer.transport_addr_list,
transports) {
if (transport == active)
continue;
list_for_each_entry(chunk, &transport->transmitted,
transmitted_list) {
if (key == chunk->subh.data_hdr->tsn) {
match = transport;
goto out;
}
}
}
out:
return match;
}
/* Do delayed input processing. This is scheduled by sctp_rcv(). */
static void sctp_assoc_bh_rcv(struct work_struct *work)
{
struct sctp_association *asoc =
container_of(work, struct sctp_association,
base.inqueue.immediate);
struct net *net = asoc->base.net;
union sctp_subtype subtype;
struct sctp_endpoint *ep;
struct sctp_chunk *chunk;
struct sctp_inq *inqueue;
int first_time = 1; /* is this the first time through the loop */
int error = 0;
int state;
/* The association should be held so we should be safe. */
ep = asoc->ep;
inqueue = &asoc->base.inqueue;
sctp_association_hold(asoc);
while (NULL != (chunk = sctp_inq_pop(inqueue))) {
state = asoc->state;
subtype = SCTP_ST_CHUNK(chunk->chunk_hdr->type);
/* If the first chunk in the packet is AUTH, do special
* processing specified in Section 6.3 of SCTP-AUTH spec
*/
if (first_time && subtype.chunk == SCTP_CID_AUTH) {
struct sctp_chunkhdr *next_hdr;
next_hdr = sctp_inq_peek(inqueue);
if (!next_hdr)
goto normal;
/* If the next chunk is COOKIE-ECHO, skip the AUTH
* chunk while saving a pointer to it so we can do
* Authentication later (during cookie-echo
* processing).
*/
if (next_hdr->type == SCTP_CID_COOKIE_ECHO) {
chunk->auth_chunk = skb_clone(chunk->skb,
GFP_ATOMIC);
chunk->auth = 1;
continue;
}
}
normal:
/* SCTP-AUTH, Section 6.3:
* The receiver has a list of chunk types which it expects
* to be received only after an AUTH-chunk. This list has
* been sent to the peer during the association setup. It
* MUST silently discard these chunks if they are not placed
* after an AUTH chunk in the packet.
*/
if (sctp_auth_recv_cid(subtype.chunk, asoc) && !chunk->auth)
continue;
/* Remember where the last DATA chunk came from so we
* know where to send the SACK.
*/
if (sctp_chunk_is_data(chunk))
asoc->peer.last_data_from = chunk->transport;
else {
SCTP_INC_STATS(net, SCTP_MIB_INCTRLCHUNKS);
asoc->stats.ictrlchunks++;
if (chunk->chunk_hdr->type == SCTP_CID_SACK)
asoc->stats.isacks++;
}
if (chunk->transport)
chunk->transport->last_time_heard = ktime_get();
/* Run through the state machine. */
error = sctp_do_sm(net, SCTP_EVENT_T_CHUNK, subtype,
state, ep, asoc, chunk, GFP_ATOMIC);
/* Check to see if the association is freed in response to
* the incoming chunk. If so, get out of the while loop.
*/
if (asoc->base.dead)
break;
/* If there is an error on chunk, discard this packet. */
if (error && chunk)
chunk->pdiscard = 1;
if (first_time)
first_time = 0;
}
sctp_association_put(asoc);
}
/* This routine moves an association from its old sk to a new sk. */
void sctp_assoc_migrate(struct sctp_association *assoc, struct sock *newsk)
{
struct sctp_sock *newsp = sctp_sk(newsk);
struct sock *oldsk = assoc->base.sk;
/* Delete the association from the old endpoint's list of
* associations.
*/
list_del_init(&assoc->asocs);
/* Decrement the backlog value for a TCP-style socket. */
if (sctp_style(oldsk, TCP))
sk_acceptq_removed(oldsk);
/* Release references to the old endpoint and the sock. */
sctp_endpoint_put(assoc->ep);
sock_put(assoc->base.sk);
/* Get a reference to the new endpoint. */
assoc->ep = newsp->ep;
sctp_endpoint_hold(assoc->ep);
/* Get a reference to the new sock. */
assoc->base.sk = newsk;
sock_hold(assoc->base.sk);
/* Add the association to the new endpoint's list of associations. */
sctp_endpoint_add_asoc(newsp->ep, assoc);
}
/* Update an association (possibly from unexpected COOKIE-ECHO processing). */
int sctp_assoc_update(struct sctp_association *asoc,
struct sctp_association *new)
{
struct sctp_transport *trans;
struct list_head *pos, *temp;
/* Copy in new parameters of peer. */
asoc->c = new->c;
asoc->peer.rwnd = new->peer.rwnd;
asoc->peer.sack_needed = new->peer.sack_needed;
asoc->peer.auth_capable = new->peer.auth_capable;
asoc->peer.i = new->peer.i;
if (!sctp_tsnmap_init(&asoc->peer.tsn_map, SCTP_TSN_MAP_INITIAL,
asoc->peer.i.initial_tsn, GFP_ATOMIC))
return -ENOMEM;
/* Remove any peer addresses not present in the new association. */
list_for_each_safe(pos, temp, &asoc->peer.transport_addr_list) {
trans = list_entry(pos, struct sctp_transport, transports);
if (!sctp_assoc_lookup_paddr(new, &trans->ipaddr)) {
sctp_assoc_rm_peer(asoc, trans);
continue;
}
if (asoc->state >= SCTP_STATE_ESTABLISHED)
sctp_transport_reset(trans);
}
/* If the case is A (association restart), use
* initial_tsn as next_tsn. If the case is B, use
* current next_tsn in case data sent to peer
* has been discarded and needs retransmission.
*/
if (asoc->state >= SCTP_STATE_ESTABLISHED) {
asoc->next_tsn = new->next_tsn;
asoc->ctsn_ack_point = new->ctsn_ack_point;
asoc->adv_peer_ack_point = new->adv_peer_ack_point;
/* Reinitialize SSN for both local streams
* and peer's streams.
*/
sctp_stream_clear(&asoc->stream);
/* Flush the ULP reassembly and ordered queue.
* Any data there will now be stale and will
* cause problems.
*/
sctp_ulpq_flush(&asoc->ulpq);
/* reset the overall association error count so
* that the restarted association doesn't get torn
* down on the next retransmission timer.
*/
asoc->overall_error_count = 0;
} else {
/* Add any peer addresses from the new association. */
list_for_each_entry(trans, &new->peer.transport_addr_list,
transports)
if (!sctp_assoc_add_peer(asoc, &trans->ipaddr,
GFP_ATOMIC, trans->state))
return -ENOMEM;
asoc->ctsn_ack_point = asoc->next_tsn - 1;
asoc->adv_peer_ack_point = asoc->ctsn_ack_point;
if (sctp_state(asoc, COOKIE_WAIT))
sctp_stream_update(&asoc->stream, &new->stream);
/* get a new assoc id if we don't have one yet. */
if (sctp_assoc_set_id(asoc, GFP_ATOMIC))
return -ENOMEM;
}
/* SCTP-AUTH: Save the peer parameters from the new associations
* and also move the association shared keys over
*/
kfree(asoc->peer.peer_random);
asoc->peer.peer_random = new->peer.peer_random;
new->peer.peer_random = NULL;
kfree(asoc->peer.peer_chunks);
asoc->peer.peer_chunks = new->peer.peer_chunks;
new->peer.peer_chunks = NULL;
kfree(asoc->peer.peer_hmacs);
asoc->peer.peer_hmacs = new->peer.peer_hmacs;
new->peer.peer_hmacs = NULL;
return sctp_auth_asoc_init_active_key(asoc, GFP_ATOMIC);
}
/* Update the retran path for sending a retransmitted packet.
* See also RFC4960, 6.4. Multi-Homed SCTP Endpoints:
*
* When there is outbound data to send and the primary path
* becomes inactive (e.g., due to failures), or where the
* SCTP user explicitly requests to send data to an
* inactive destination transport address, before reporting
* an error to its ULP, the SCTP endpoint should try to send
* the data to an alternate active destination transport
* address if one exists.
*
* When retransmitting data that timed out, if the endpoint
* is multihomed, it should consider each source-destination
* address pair in its retransmission selection policy.
* When retransmitting timed-out data, the endpoint should
* attempt to pick the most divergent source-destination
* pair from the original source-destination pair to which
* the packet was transmitted.
*
* Note: Rules for picking the most divergent source-destination
* pair are an implementation decision and are not specified
* within this document.
*
* Our basic strategy is to round-robin transports in priorities
* according to sctp_trans_score() e.g., if no such
* transport with state SCTP_ACTIVE exists, round-robin through
* SCTP_UNKNOWN, etc. You get the picture.
*/
static u8 sctp_trans_score(const struct sctp_transport *trans)
{
switch (trans->state) {
case SCTP_ACTIVE:
return 3; /* best case */
case SCTP_UNKNOWN:
return 2;
case SCTP_PF:
return 1;
default: /* case SCTP_INACTIVE */
return 0; /* worst case */
}
}
static struct sctp_transport *sctp_trans_elect_tie(struct sctp_transport *trans1,
struct sctp_transport *trans2)
{
if (trans1->error_count > trans2->error_count) {
return trans2;
} else if (trans1->error_count == trans2->error_count &&
ktime_after(trans2->last_time_heard,
trans1->last_time_heard)) {
return trans2;
} else {
return trans1;
}
}
static struct sctp_transport *sctp_trans_elect_best(struct sctp_transport *curr,
struct sctp_transport *best)
{
u8 score_curr, score_best;
if (best == NULL || curr == best)
return curr;
score_curr = sctp_trans_score(curr);
score_best = sctp_trans_score(best);
/* First, try a score-based selection if both transport states
* differ. If we're in a tie, lets try to make a more clever
* decision here based on error counts and last time heard.
*/
if (score_curr > score_best)
return curr;
else if (score_curr == score_best)
return sctp_trans_elect_tie(best, curr);
else
return best;
}
void sctp_assoc_update_retran_path(struct sctp_association *asoc)
{
struct sctp_transport *trans = asoc->peer.retran_path;
struct sctp_transport *trans_next = NULL;
/* We're done as we only have the one and only path. */
if (asoc->peer.transport_count == 1)
return;
/* If active_path and retran_path are the same and active,
* then this is the only active path. Use it.
*/
if (asoc->peer.active_path == asoc->peer.retran_path &&
asoc->peer.active_path->state == SCTP_ACTIVE)
return;
/* Iterate from retran_path's successor back to retran_path. */
for (trans = list_next_entry(trans, transports); 1;
trans = list_next_entry(trans, transports)) {
/* Manually skip the head element. */
if (&trans->transports == &asoc->peer.transport_addr_list)
continue;
if (trans->state == SCTP_UNCONFIRMED)
continue;
trans_next = sctp_trans_elect_best(trans, trans_next);
/* Active is good enough for immediate return. */
if (trans_next->state == SCTP_ACTIVE)
break;
/* We've reached the end, time to update path. */
if (trans == asoc->peer.retran_path)
break;
}
asoc->peer.retran_path = trans_next;
pr_debug("%s: association:%p updated new path to addr:%pISpc\n",
__func__, asoc, &asoc->peer.retran_path->ipaddr.sa);
}
static void sctp_select_active_and_retran_path(struct sctp_association *asoc)
{
struct sctp_transport *trans, *trans_pri = NULL, *trans_sec = NULL;
struct sctp_transport *trans_pf = NULL;
/* Look for the two most recently used active transports. */
list_for_each_entry(trans, &asoc->peer.transport_addr_list,
transports) {
/* Skip uninteresting transports. */
if (trans->state == SCTP_INACTIVE ||
trans->state == SCTP_UNCONFIRMED)
continue;
/* Keep track of the best PF transport from our
* list in case we don't find an active one.
*/
if (trans->state == SCTP_PF) {
trans_pf = sctp_trans_elect_best(trans, trans_pf);
continue;
}
/* For active transports, pick the most recent ones. */
if (trans_pri == NULL ||
ktime_after(trans->last_time_heard,
trans_pri->last_time_heard)) {
trans_sec = trans_pri;
trans_pri = trans;
} else if (trans_sec == NULL ||
ktime_after(trans->last_time_heard,
trans_sec->last_time_heard)) {
trans_sec = trans;
}
}
/* RFC 2960 6.4 Multi-Homed SCTP Endpoints
*
* By default, an endpoint should always transmit to the primary
* path, unless the SCTP user explicitly specifies the
* destination transport address (and possibly source transport
* address) to use. [If the primary is active but not most recent,
* bump the most recently used transport.]
*/
if ((asoc->peer.primary_path->state == SCTP_ACTIVE ||
asoc->peer.primary_path->state == SCTP_UNKNOWN) &&
asoc->peer.primary_path != trans_pri) {
trans_sec = trans_pri;
trans_pri = asoc->peer.primary_path;
}
/* We did not find anything useful for a possible retransmission
* path; either primary path that we found is the same as
* the current one, or we didn't generally find an active one.
*/
if (trans_sec == NULL)
trans_sec = trans_pri;
/* If we failed to find a usable transport, just camp on the
* active or pick a PF iff it's the better choice.
*/
if (trans_pri == NULL) {
trans_pri = sctp_trans_elect_best(asoc->peer.active_path, trans_pf);
trans_sec = trans_pri;
}
/* Set the active and retran transports. */
asoc->peer.active_path = trans_pri;
asoc->peer.retran_path = trans_sec;
}
struct sctp_transport *
sctp_assoc_choose_alter_transport(struct sctp_association *asoc,
struct sctp_transport *last_sent_to)
{
/* If this is the first time packet is sent, use the active path,
* else use the retran path. If the last packet was sent over the
* retran path, update the retran path and use it.
*/
if (last_sent_to == NULL) {
return asoc->peer.active_path;
} else {
if (last_sent_to == asoc->peer.retran_path)
sctp_assoc_update_retran_path(asoc);
return asoc->peer.retran_path;
}
}
void sctp_assoc_update_frag_point(struct sctp_association *asoc)
{
int frag = sctp_mtu_payload(sctp_sk(asoc->base.sk), asoc->pathmtu,
sctp_datachk_len(&asoc->stream));
if (asoc->user_frag)
frag = min_t(int, frag, asoc->user_frag);
frag = min_t(int, frag, SCTP_MAX_CHUNK_LEN -
sctp_datachk_len(&asoc->stream));
asoc->frag_point = SCTP_TRUNC4(frag);
}
void sctp_assoc_set_pmtu(struct sctp_association *asoc, __u32 pmtu)
{
if (asoc->pathmtu != pmtu) {
asoc->pathmtu = pmtu;
sctp_assoc_update_frag_point(asoc);
}
pr_debug("%s: asoc:%p, pmtu:%d, frag_point:%d\n", __func__, asoc,
asoc->pathmtu, asoc->frag_point);
}
/* Update the association's pmtu and frag_point by going through all the
* transports. This routine is called when a transport's PMTU has changed.
*/
void sctp_assoc_sync_pmtu(struct sctp_association *asoc)
{
struct sctp_transport *t;
__u32 pmtu = 0;
if (!asoc)
return;
/* Get the lowest pmtu of all the transports. */
list_for_each_entry(t, &asoc->peer.transport_addr_list, transports) {
if (t->pmtu_pending && t->dst) {
sctp_transport_update_pmtu(t,
atomic_read(&t->mtu_info));
t->pmtu_pending = 0;
}
if (!pmtu || (t->pathmtu < pmtu))
pmtu = t->pathmtu;
}
sctp_assoc_set_pmtu(asoc, pmtu);
}
/* Should we send a SACK to update our peer? */
static inline bool sctp_peer_needs_update(struct sctp_association *asoc)
{
struct net *net = asoc->base.net;
switch (asoc->state) {
case SCTP_STATE_ESTABLISHED:
case SCTP_STATE_SHUTDOWN_PENDING:
case SCTP_STATE_SHUTDOWN_RECEIVED:
case SCTP_STATE_SHUTDOWN_SENT:
if ((asoc->rwnd > asoc->a_rwnd) &&
((asoc->rwnd - asoc->a_rwnd) >= max_t(__u32,
(asoc->base.sk->sk_rcvbuf >> net->sctp.rwnd_upd_shift),
asoc->pathmtu)))
return true;
break;
default:
break;
}
return false;
}
/* Increase asoc's rwnd by len and send any window update SACK if needed. */
void sctp_assoc_rwnd_increase(struct sctp_association *asoc, unsigned int len)
{
struct sctp_chunk *sack;
struct timer_list *timer;
if (asoc->rwnd_over) {
if (asoc->rwnd_over >= len) {
asoc->rwnd_over -= len;
} else {
asoc->rwnd += (len - asoc->rwnd_over);
asoc->rwnd_over = 0;
}
} else {
asoc->rwnd += len;
}
/* If we had window pressure, start recovering it
* once our rwnd had reached the accumulated pressure
* threshold. The idea is to recover slowly, but up
* to the initial advertised window.
*/
if (asoc->rwnd_press) {
int change = min(asoc->pathmtu, asoc->rwnd_press);
asoc->rwnd += change;
asoc->rwnd_press -= change;
}
pr_debug("%s: asoc:%p rwnd increased by %d to (%u, %u) - %u\n",
__func__, asoc, len, asoc->rwnd, asoc->rwnd_over,
asoc->a_rwnd);
/* Send a window update SACK if the rwnd has increased by at least the
* minimum of the association's PMTU and half of the receive buffer.
* The algorithm used is similar to the one described in
* Section 4.2.3.3 of RFC 1122.
*/
if (sctp_peer_needs_update(asoc)) {
asoc->a_rwnd = asoc->rwnd;
pr_debug("%s: sending window update SACK- asoc:%p rwnd:%u "
"a_rwnd:%u\n", __func__, asoc, asoc->rwnd,
asoc->a_rwnd);
sack = sctp_make_sack(asoc);
if (!sack)
return;
asoc->peer.sack_needed = 0;
sctp_outq_tail(&asoc->outqueue, sack, GFP_ATOMIC);
/* Stop the SACK timer. */
timer = &asoc->timers[SCTP_EVENT_TIMEOUT_SACK];
if (del_timer(timer))
sctp_association_put(asoc);
}
}
/* Decrease asoc's rwnd by len. */
void sctp_assoc_rwnd_decrease(struct sctp_association *asoc, unsigned int len)
{
int rx_count;
int over = 0;
if (unlikely(!asoc->rwnd || asoc->rwnd_over))
pr_debug("%s: association:%p has asoc->rwnd:%u, "
"asoc->rwnd_over:%u!\n", __func__, asoc,
asoc->rwnd, asoc->rwnd_over);
if (asoc->ep->rcvbuf_policy)
rx_count = atomic_read(&asoc->rmem_alloc);
else
rx_count = atomic_read(&asoc->base.sk->sk_rmem_alloc);
/* If we've reached or overflowed our receive buffer, announce
* a 0 rwnd if rwnd would still be positive. Store the
* potential pressure overflow so that the window can be restored
* back to original value.
*/
if (rx_count >= asoc->base.sk->sk_rcvbuf)
over = 1;
if (asoc->rwnd >= len) {
asoc->rwnd -= len;
if (over) {
asoc->rwnd_press += asoc->rwnd;
asoc->rwnd = 0;
}
} else {
asoc->rwnd_over += len - asoc->rwnd;
asoc->rwnd = 0;
}
pr_debug("%s: asoc:%p rwnd decreased by %d to (%u, %u, %u)\n",
__func__, asoc, len, asoc->rwnd, asoc->rwnd_over,
asoc->rwnd_press);
}
/* Build the bind address list for the association based on info from the
* local endpoint and the remote peer.
*/
int sctp_assoc_set_bind_addr_from_ep(struct sctp_association *asoc,
enum sctp_scope scope, gfp_t gfp)
{
struct sock *sk = asoc->base.sk;
int flags;
/* Use scoping rules to determine the subset of addresses from
* the endpoint.
*/
flags = (PF_INET6 == sk->sk_family) ? SCTP_ADDR6_ALLOWED : 0;
if (!inet_v6_ipv6only(sk))
flags |= SCTP_ADDR4_ALLOWED;
if (asoc->peer.ipv4_address)
flags |= SCTP_ADDR4_PEERSUPP;
if (asoc->peer.ipv6_address)
flags |= SCTP_ADDR6_PEERSUPP;
return sctp_bind_addr_copy(asoc->base.net,
&asoc->base.bind_addr,
&asoc->ep->base.bind_addr,
scope, gfp, flags);
}
/* Build the association's bind address list from the cookie. */
int sctp_assoc_set_bind_addr_from_cookie(struct sctp_association *asoc,
struct sctp_cookie *cookie,
gfp_t gfp)
{
struct sctp_init_chunk *peer_init = (struct sctp_init_chunk *)(cookie + 1);
int var_size2 = ntohs(peer_init->chunk_hdr.length);
int var_size3 = cookie->raw_addr_list_len;
__u8 *raw = (__u8 *)peer_init + var_size2;
return sctp_raw_to_bind_addrs(&asoc->base.bind_addr, raw, var_size3,
asoc->ep->base.bind_addr.port, gfp);
}
/* Lookup laddr in the bind address list of an association. */
int sctp_assoc_lookup_laddr(struct sctp_association *asoc,
const union sctp_addr *laddr)
{
int found = 0;
if ((asoc->base.bind_addr.port == ntohs(laddr->v4.sin_port)) &&
sctp_bind_addr_match(&asoc->base.bind_addr, laddr,
sctp_sk(asoc->base.sk)))
found = 1;
return found;
}
/* Set an association id for a given association */
int sctp_assoc_set_id(struct sctp_association *asoc, gfp_t gfp)
{
bool preload = gfpflags_allow_blocking(gfp);
int ret;
/* If the id is already assigned, keep it. */
if (asoc->assoc_id)
return 0;
if (preload)
idr_preload(gfp);
spin_lock_bh(&sctp_assocs_id_lock);
/* 0, 1, 2 are used as SCTP_FUTURE_ASSOC, SCTP_CURRENT_ASSOC and
* SCTP_ALL_ASSOC, so an available id must be > SCTP_ALL_ASSOC.
*/
ret = idr_alloc_cyclic(&sctp_assocs_id, asoc, SCTP_ALL_ASSOC + 1, 0,
GFP_NOWAIT);
spin_unlock_bh(&sctp_assocs_id_lock);
if (preload)
idr_preload_end();
if (ret < 0)
return ret;
asoc->assoc_id = (sctp_assoc_t)ret;
return 0;
}
/* Free the ASCONF queue */
static void sctp_assoc_free_asconf_queue(struct sctp_association *asoc)
{
struct sctp_chunk *asconf;
struct sctp_chunk *tmp;
list_for_each_entry_safe(asconf, tmp, &asoc->addip_chunk_list, list) {
list_del_init(&asconf->list);
sctp_chunk_free(asconf);
}
}
/* Free asconf_ack cache */
static void sctp_assoc_free_asconf_acks(struct sctp_association *asoc)
{
struct sctp_chunk *ack;
struct sctp_chunk *tmp;
list_for_each_entry_safe(ack, tmp, &asoc->asconf_ack_list,
transmitted_list) {
list_del_init(&ack->transmitted_list);
sctp_chunk_free(ack);
}
}
/* Clean up the ASCONF_ACK queue */
void sctp_assoc_clean_asconf_ack_cache(const struct sctp_association *asoc)
{
struct sctp_chunk *ack;
struct sctp_chunk *tmp;
/* We can remove all the entries from the queue up to
* the "Peer-Sequence-Number".
*/
list_for_each_entry_safe(ack, tmp, &asoc->asconf_ack_list,
transmitted_list) {
if (ack->subh.addip_hdr->serial ==
htonl(asoc->peer.addip_serial))
break;
list_del_init(&ack->transmitted_list);
sctp_chunk_free(ack);
}
}
/* Find the ASCONF_ACK whose serial number matches ASCONF */
struct sctp_chunk *sctp_assoc_lookup_asconf_ack(
const struct sctp_association *asoc,
__be32 serial)
{
struct sctp_chunk *ack;
/* Walk through the list of cached ASCONF-ACKs and find the
* ack chunk whose serial number matches that of the request.
*/
list_for_each_entry(ack, &asoc->asconf_ack_list, transmitted_list) {
if (sctp_chunk_pending(ack))
continue;
if (ack->subh.addip_hdr->serial == serial) {
sctp_chunk_hold(ack);
return ack;
}
}
return NULL;
}
void sctp_asconf_queue_teardown(struct sctp_association *asoc)
{
/* Free any cached ASCONF_ACK chunk. */
sctp_assoc_free_asconf_acks(asoc);
/* Free the ASCONF queue. */
sctp_assoc_free_asconf_queue(asoc);
/* Free any cached ASCONF chunk. */
if (asoc->addip_last_asconf)
sctp_chunk_free(asoc->addip_last_asconf);
}
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* HID driver for Sony / PS2 / PS3 / PS4 BD devices.
*
* Copyright (c) 1999 Andreas Gal
* Copyright (c) 2000-2005 Vojtech Pavlik <[email protected]>
* Copyright (c) 2005 Michael Haboustak <[email protected]> for Concept2, Inc
* Copyright (c) 2008 Jiri Slaby
* Copyright (c) 2012 David Dillow <[email protected]>
* Copyright (c) 2006-2013 Jiri Kosina
* Copyright (c) 2013 Colin Leitner <[email protected]>
* Copyright (c) 2014-2016 Frank Praznik <[email protected]>
* Copyright (c) 2018 Todd Kelner
* Copyright (c) 2020-2021 Pascal Giard <[email protected]>
* Copyright (c) 2020 Sanjay Govind <[email protected]>
* Copyright (c) 2021 Daniel Nguyen <[email protected]>
*/
/*
*/
/*
* NOTE: in order for the Sony PS3 BD Remote Control to be found by
* a Bluetooth host, the key combination Start+Enter has to be kept pressed
* for about 7 seconds with the Bluetooth Host Controller in discovering mode.
*
* There will be no PIN request from the device.
*/
#include <linux/device.h>
#include <linux/hid.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/leds.h>
#include <linux/power_supply.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/idr.h>
#include <linux/input/mt.h>
#include <linux/crc32.h>
#include <linux/usb.h>
#include <linux/timer.h>
#include <linux/unaligned.h>
#include "hid-ids.h"
#define VAIO_RDESC_CONSTANT BIT(0)
#define SIXAXIS_CONTROLLER_USB BIT(1)
#define SIXAXIS_CONTROLLER_BT BIT(2)
#define BUZZ_CONTROLLER BIT(3)
#define PS3REMOTE BIT(4)
#define MOTION_CONTROLLER_USB BIT(5)
#define MOTION_CONTROLLER_BT BIT(6)
#define NAVIGATION_CONTROLLER_USB BIT(7)
#define NAVIGATION_CONTROLLER_BT BIT(8)
#define SINO_LITE_CONTROLLER BIT(9)
#define FUTUREMAX_DANCE_MAT BIT(10)
#define NSG_MR5U_REMOTE_BT BIT(11)
#define NSG_MR7U_REMOTE_BT BIT(12)
#define SHANWAN_GAMEPAD BIT(13)
#define GH_GUITAR_CONTROLLER BIT(14)
#define GHL_GUITAR_PS3WIIU BIT(15)
#define GHL_GUITAR_PS4 BIT(16)
#define SIXAXIS_CONTROLLER (SIXAXIS_CONTROLLER_USB | SIXAXIS_CONTROLLER_BT)
#define MOTION_CONTROLLER (MOTION_CONTROLLER_USB | MOTION_CONTROLLER_BT)
#define NAVIGATION_CONTROLLER (NAVIGATION_CONTROLLER_USB |\
NAVIGATION_CONTROLLER_BT)
#define SONY_LED_SUPPORT (SIXAXIS_CONTROLLER | BUZZ_CONTROLLER |\
MOTION_CONTROLLER | NAVIGATION_CONTROLLER)
#define SONY_BATTERY_SUPPORT (SIXAXIS_CONTROLLER | MOTION_CONTROLLER_BT | NAVIGATION_CONTROLLER)
#define SONY_FF_SUPPORT (SIXAXIS_CONTROLLER | MOTION_CONTROLLER)
#define SONY_BT_DEVICE (SIXAXIS_CONTROLLER_BT | MOTION_CONTROLLER_BT | NAVIGATION_CONTROLLER_BT)
#define NSG_MRXU_REMOTE (NSG_MR5U_REMOTE_BT | NSG_MR7U_REMOTE_BT)
#define MAX_LEDS 4
#define NSG_MRXU_MAX_X 1667
#define NSG_MRXU_MAX_Y 1868
/* The PS3/Wii U dongles require a poke every 10 seconds, but the PS4
* requires one every 8 seconds. Using 8 seconds for all for simplicity.
*/
#define GHL_GUITAR_POKE_INTERVAL 8 /* In seconds */
#define GUITAR_TILT_USAGE 44
/* Magic data taken from GHLtarUtility:
* https://github.com/ghlre/GHLtarUtility/blob/master/PS3Guitar.cs
* Note: The Wii U and PS3 dongles happen to share the same!
*/
static const char ghl_ps3wiiu_magic_data[] = {
0x02, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00
};
/* Magic data for the PS4 dongles sniffed with a USB protocol
* analyzer.
*/
static const char ghl_ps4_magic_data[] = {
0x30, 0x02, 0x08, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00
};
/* PS/3 Motion controller */
static const u8 motion_rdesc[] = {
0x05, 0x01, /* Usage Page (Desktop), */
0x09, 0x04, /* Usage (Joystick), */
0xA1, 0x01, /* Collection (Application), */
0xA1, 0x02, /* Collection (Logical), */
0x85, 0x01, /* Report ID (1), */
0x75, 0x01, /* Report Size (1), */
0x95, 0x15, /* Report Count (21), */
0x15, 0x00, /* Logical Minimum (0), */
0x25, 0x01, /* Logical Maximum (1), */
0x35, 0x00, /* Physical Minimum (0), */
0x45, 0x01, /* Physical Maximum (1), */
0x05, 0x09, /* Usage Page (Button), */
0x19, 0x01, /* Usage Minimum (01h), */
0x29, 0x15, /* Usage Maximum (15h), */
0x81, 0x02, /* Input (Variable), * Buttons */
0x95, 0x0B, /* Report Count (11), */
0x06, 0x00, 0xFF, /* Usage Page (FF00h), */
0x81, 0x03, /* Input (Constant, Variable), * Padding */
0x15, 0x00, /* Logical Minimum (0), */
0x26, 0xFF, 0x00, /* Logical Maximum (255), */
0x05, 0x01, /* Usage Page (Desktop), */
0xA1, 0x00, /* Collection (Physical), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x01, /* Report Count (1), */
0x35, 0x00, /* Physical Minimum (0), */
0x46, 0xFF, 0x00, /* Physical Maximum (255), */
0x09, 0x30, /* Usage (X), */
0x81, 0x02, /* Input (Variable), * Trigger */
0xC0, /* End Collection, */
0x06, 0x00, 0xFF, /* Usage Page (FF00h), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x07, /* Report Count (7), * skip 7 bytes */
0x81, 0x02, /* Input (Variable), */
0x05, 0x01, /* Usage Page (Desktop), */
0x75, 0x10, /* Report Size (16), */
0x46, 0xFF, 0xFF, /* Physical Maximum (65535), */
0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535), */
0x95, 0x03, /* Report Count (3), * 3x Accels */
0x09, 0x33, /* Usage (rX), */
0x09, 0x34, /* Usage (rY), */
0x09, 0x35, /* Usage (rZ), */
0x81, 0x02, /* Input (Variable), */
0x06, 0x00, 0xFF, /* Usage Page (FF00h), */
0x95, 0x03, /* Report Count (3), * Skip Accels 2nd frame */
0x81, 0x02, /* Input (Variable), */
0x05, 0x01, /* Usage Page (Desktop), */
0x09, 0x01, /* Usage (Pointer), */
0x95, 0x03, /* Report Count (3), * 3x Gyros */
0x81, 0x02, /* Input (Variable), */
0x06, 0x00, 0xFF, /* Usage Page (FF00h), */
0x95, 0x03, /* Report Count (3), * Skip Gyros 2nd frame */
0x81, 0x02, /* Input (Variable), */
0x75, 0x0C, /* Report Size (12), */
0x46, 0xFF, 0x0F, /* Physical Maximum (4095), */
0x26, 0xFF, 0x0F, /* Logical Maximum (4095), */
0x95, 0x04, /* Report Count (4), * Skip Temp and Magnetometers */
0x81, 0x02, /* Input (Variable), */
0x75, 0x08, /* Report Size (8), */
0x46, 0xFF, 0x00, /* Physical Maximum (255), */
0x26, 0xFF, 0x00, /* Logical Maximum (255), */
0x95, 0x06, /* Report Count (6), * Skip Timestamp and Extension Bytes */
0x81, 0x02, /* Input (Variable), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x30, /* Report Count (48), */
0x09, 0x01, /* Usage (Pointer), */
0x91, 0x02, /* Output (Variable), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x30, /* Report Count (48), */
0x09, 0x01, /* Usage (Pointer), */
0xB1, 0x02, /* Feature (Variable), */
0xC0, /* End Collection, */
0xA1, 0x02, /* Collection (Logical), */
0x85, 0x02, /* Report ID (2), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x30, /* Report Count (48), */
0x09, 0x01, /* Usage (Pointer), */
0xB1, 0x02, /* Feature (Variable), */
0xC0, /* End Collection, */
0xA1, 0x02, /* Collection (Logical), */
0x85, 0xEE, /* Report ID (238), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x30, /* Report Count (48), */
0x09, 0x01, /* Usage (Pointer), */
0xB1, 0x02, /* Feature (Variable), */
0xC0, /* End Collection, */
0xA1, 0x02, /* Collection (Logical), */
0x85, 0xEF, /* Report ID (239), */
0x75, 0x08, /* Report Size (8), */
0x95, 0x30, /* Report Count (48), */
0x09, 0x01, /* Usage (Pointer), */
0xB1, 0x02, /* Feature (Variable), */
0xC0, /* End Collection, */
0xC0 /* End Collection */
};
static const u8 ps3remote_rdesc[] = {
0x05, 0x01, /* GUsagePage Generic Desktop */
0x09, 0x05, /* LUsage 0x05 [Game Pad] */
0xA1, 0x01, /* MCollection Application (mouse, keyboard) */
/* Use collection 1 for joypad buttons */
0xA1, 0x02, /* MCollection Logical (interrelated data) */
/*
* Ignore the 1st byte, maybe it is used for a controller
* number but it's not needed for correct operation
*/
0x75, 0x08, /* GReportSize 0x08 [8] */
0x95, 0x01, /* GReportCount 0x01 [1] */
0x81, 0x01, /* MInput 0x01 (Const[0] Arr[1] Abs[2]) */
/*
* Bytes from 2nd to 4th are a bitmap for joypad buttons, for these
* buttons multiple keypresses are allowed
*/
0x05, 0x09, /* GUsagePage Button */
0x19, 0x01, /* LUsageMinimum 0x01 [Button 1 (primary/trigger)] */
0x29, 0x18, /* LUsageMaximum 0x18 [Button 24] */
0x14, /* GLogicalMinimum [0] */
0x25, 0x01, /* GLogicalMaximum 0x01 [1] */
0x75, 0x01, /* GReportSize 0x01 [1] */
0x95, 0x18, /* GReportCount 0x18 [24] */
0x81, 0x02, /* MInput 0x02 (Data[0] Var[1] Abs[2]) */
0xC0, /* MEndCollection */
/* Use collection 2 for remote control buttons */
0xA1, 0x02, /* MCollection Logical (interrelated data) */
/* 5th byte is used for remote control buttons */
0x05, 0x09, /* GUsagePage Button */
0x18, /* LUsageMinimum [No button pressed] */
0x29, 0xFE, /* LUsageMaximum 0xFE [Button 254] */
0x14, /* GLogicalMinimum [0] */
0x26, 0xFE, 0x00, /* GLogicalMaximum 0x00FE [254] */
0x75, 0x08, /* GReportSize 0x08 [8] */
0x95, 0x01, /* GReportCount 0x01 [1] */
0x80, /* MInput */
/*
* Ignore bytes from 6th to 11th, 6th to 10th are always constant at
* 0xff and 11th is for press indication
*/
0x75, 0x08, /* GReportSize 0x08 [8] */
0x95, 0x06, /* GReportCount 0x06 [6] */
0x81, 0x01, /* MInput 0x01 (Const[0] Arr[1] Abs[2]) */
/* 12th byte is for battery strength */
0x05, 0x06, /* GUsagePage Generic Device Controls */
0x09, 0x20, /* LUsage 0x20 [Battery Strength] */
0x14, /* GLogicalMinimum [0] */
0x25, 0x05, /* GLogicalMaximum 0x05 [5] */
0x75, 0x08, /* GReportSize 0x08 [8] */
0x95, 0x01, /* GReportCount 0x01 [1] */
0x81, 0x02, /* MInput 0x02 (Data[0] Var[1] Abs[2]) */
0xC0, /* MEndCollection */
0xC0 /* MEndCollection [Game Pad] */
};
static const unsigned int ps3remote_keymap_joypad_buttons[] = {
[0x01] = KEY_SELECT,
[0x02] = BTN_THUMBL, /* L3 */
[0x03] = BTN_THUMBR, /* R3 */
[0x04] = BTN_START,
[0x05] = KEY_UP,
[0x06] = KEY_RIGHT,
[0x07] = KEY_DOWN,
[0x08] = KEY_LEFT,
[0x09] = BTN_TL2, /* L2 */
[0x0a] = BTN_TR2, /* R2 */
[0x0b] = BTN_TL, /* L1 */
[0x0c] = BTN_TR, /* R1 */
[0x0d] = KEY_OPTION, /* options/triangle */
[0x0e] = KEY_BACK, /* back/circle */
[0x0f] = BTN_0, /* cross */
[0x10] = KEY_SCREEN, /* view/square */
[0x11] = KEY_HOMEPAGE, /* PS button */
[0x14] = KEY_ENTER,
};
static const unsigned int ps3remote_keymap_remote_buttons[] = {
[0x00] = KEY_1,
[0x01] = KEY_2,
[0x02] = KEY_3,
[0x03] = KEY_4,
[0x04] = KEY_5,
[0x05] = KEY_6,
[0x06] = KEY_7,
[0x07] = KEY_8,
[0x08] = KEY_9,
[0x09] = KEY_0,
[0x0e] = KEY_ESC, /* return */
[0x0f] = KEY_CLEAR,
[0x16] = KEY_EJECTCD,
[0x1a] = KEY_MENU, /* top menu */
[0x28] = KEY_TIME,
[0x30] = KEY_PREVIOUS,
[0x31] = KEY_NEXT,
[0x32] = KEY_PLAY,
[0x33] = KEY_REWIND, /* scan back */
[0x34] = KEY_FORWARD, /* scan forward */
[0x38] = KEY_STOP,
[0x39] = KEY_PAUSE,
[0x40] = KEY_CONTEXT_MENU, /* pop up/menu */
[0x60] = KEY_FRAMEBACK, /* slow/step back */
[0x61] = KEY_FRAMEFORWARD, /* slow/step forward */
[0x63] = KEY_SUBTITLE,
[0x64] = KEY_AUDIO,
[0x65] = KEY_ANGLE,
[0x70] = KEY_INFO, /* display */
[0x80] = KEY_BLUE,
[0x81] = KEY_RED,
[0x82] = KEY_GREEN,
[0x83] = KEY_YELLOW,
};
static const unsigned int buzz_keymap[] = {
/*
* The controller has 4 remote buzzers, each with one LED and 5
* buttons.
*
* We use the mapping chosen by the controller, which is:
*
* Key Offset
* -------------------
* Buzz 1
* Blue 5
* Orange 4
* Green 3
* Yellow 2
*
* So, for example, the orange button on the third buzzer is mapped to
* BTN_TRIGGER_HAPPY14
*/
[1] = BTN_TRIGGER_HAPPY1,
[2] = BTN_TRIGGER_HAPPY2,
[3] = BTN_TRIGGER_HAPPY3,
[4] = BTN_TRIGGER_HAPPY4,
[5] = BTN_TRIGGER_HAPPY5,
[6] = BTN_TRIGGER_HAPPY6,
[7] = BTN_TRIGGER_HAPPY7,
[8] = BTN_TRIGGER_HAPPY8,
[9] = BTN_TRIGGER_HAPPY9,
[10] = BTN_TRIGGER_HAPPY10,
[11] = BTN_TRIGGER_HAPPY11,
[12] = BTN_TRIGGER_HAPPY12,
[13] = BTN_TRIGGER_HAPPY13,
[14] = BTN_TRIGGER_HAPPY14,
[15] = BTN_TRIGGER_HAPPY15,
[16] = BTN_TRIGGER_HAPPY16,
[17] = BTN_TRIGGER_HAPPY17,
[18] = BTN_TRIGGER_HAPPY18,
[19] = BTN_TRIGGER_HAPPY19,
[20] = BTN_TRIGGER_HAPPY20,
};
/* The Navigation controller is a partial DS3 and uses the same HID report
* and hence the same keymap indices, however not all axes/buttons
* are physically present. We use the same axis and button mapping as
* the DS3, which uses the Linux gamepad spec.
*/
static const unsigned int navigation_absmap[] = {
[0x30] = ABS_X,
[0x31] = ABS_Y,
[0x33] = ABS_Z, /* L2 */
};
/* Buttons not physically available on the device, but still available
* in the reports are explicitly set to 0 for documentation purposes.
*/
static const unsigned int navigation_keymap[] = {
[0x01] = 0, /* Select */
[0x02] = BTN_THUMBL, /* L3 */
[0x03] = 0, /* R3 */
[0x04] = 0, /* Start */
[0x05] = BTN_DPAD_UP, /* Up */
[0x06] = BTN_DPAD_RIGHT, /* Right */
[0x07] = BTN_DPAD_DOWN, /* Down */
[0x08] = BTN_DPAD_LEFT, /* Left */
[0x09] = BTN_TL2, /* L2 */
[0x0a] = 0, /* R2 */
[0x0b] = BTN_TL, /* L1 */
[0x0c] = 0, /* R1 */
[0x0d] = BTN_NORTH, /* Triangle */
[0x0e] = BTN_EAST, /* Circle */
[0x0f] = BTN_SOUTH, /* Cross */
[0x10] = BTN_WEST, /* Square */
[0x11] = BTN_MODE, /* PS */
};
static const unsigned int sixaxis_absmap[] = {
[0x30] = ABS_X,
[0x31] = ABS_Y,
[0x32] = ABS_RX, /* right stick X */
[0x35] = ABS_RY, /* right stick Y */
};
static const unsigned int sixaxis_keymap[] = {
[0x01] = BTN_SELECT, /* Select */
[0x02] = BTN_THUMBL, /* L3 */
[0x03] = BTN_THUMBR, /* R3 */
[0x04] = BTN_START, /* Start */
[0x05] = BTN_DPAD_UP, /* Up */
[0x06] = BTN_DPAD_RIGHT, /* Right */
[0x07] = BTN_DPAD_DOWN, /* Down */
[0x08] = BTN_DPAD_LEFT, /* Left */
[0x09] = BTN_TL2, /* L2 */
[0x0a] = BTN_TR2, /* R2 */
[0x0b] = BTN_TL, /* L1 */
[0x0c] = BTN_TR, /* R1 */
[0x0d] = BTN_NORTH, /* Triangle */
[0x0e] = BTN_EAST, /* Circle */
[0x0f] = BTN_SOUTH, /* Cross */
[0x10] = BTN_WEST, /* Square */
[0x11] = BTN_MODE, /* PS */
};
static enum power_supply_property sony_battery_props[] = {
POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_CAPACITY,
POWER_SUPPLY_PROP_SCOPE,
POWER_SUPPLY_PROP_STATUS,
};
struct sixaxis_led {
u8 time_enabled; /* the total time the led is active (0xff means forever) */
u8 duty_length; /* how long a cycle is in deciseconds (0 means "really fast") */
u8 enabled;
u8 duty_off; /* % of duty_length the led is off (0xff means 100%) */
u8 duty_on; /* % of duty_length the led is on (0xff mean 100%) */
} __packed;
struct sixaxis_rumble {
u8 padding;
u8 right_duration; /* Right motor duration (0xff means forever) */
u8 right_motor_on; /* Right (small) motor on/off, only supports values of 0 or 1 (off/on) */
u8 left_duration; /* Left motor duration (0xff means forever) */
u8 left_motor_force; /* left (large) motor, supports force values from 0 to 255 */
} __packed;
struct sixaxis_output_report {
u8 report_id;
struct sixaxis_rumble rumble;
u8 padding[4];
u8 leds_bitmap; /* bitmap of enabled LEDs: LED_1 = 0x02, LED_2 = 0x04, ... */
struct sixaxis_led led[4]; /* LEDx at (4 - x) */
struct sixaxis_led _reserved; /* LED5, not actually soldered */
} __packed;
union sixaxis_output_report_01 {
struct sixaxis_output_report data;
u8 buf[36];
};
struct motion_output_report_02 {
u8 type, zero;
u8 r, g, b;
u8 zero2;
u8 rumble;
};
#define SIXAXIS_REPORT_0xF2_SIZE 17
#define SIXAXIS_REPORT_0xF5_SIZE 8
#define MOTION_REPORT_0x02_SIZE 49
#define SENSOR_SUFFIX " Motion Sensors"
#define TOUCHPAD_SUFFIX " Touchpad"
#define SIXAXIS_INPUT_REPORT_ACC_X_OFFSET 41
#define SIXAXIS_ACC_RES_PER_G 113
static DEFINE_SPINLOCK(sony_dev_list_lock);
static LIST_HEAD(sony_device_list);
static DEFINE_IDA(sony_device_id_allocator);
enum sony_worker {
SONY_WORKER_STATE
};
struct sony_sc {
spinlock_t lock;
struct list_head list_node;
struct hid_device *hdev;
struct input_dev *touchpad;
struct input_dev *sensor_dev;
struct led_classdev *leds[MAX_LEDS];
unsigned long quirks;
struct work_struct state_worker;
void (*send_output_report)(struct sony_sc *);
struct power_supply *battery;
struct power_supply_desc battery_desc;
int device_id;
u8 *output_report_dmabuf;
#ifdef CONFIG_SONY_FF
u8 left;
u8 right;
#endif
u8 mac_address[6];
u8 state_worker_initialized;
u8 defer_initialization;
u8 battery_capacity;
int battery_status;
u8 led_state[MAX_LEDS];
u8 led_delay_on[MAX_LEDS];
u8 led_delay_off[MAX_LEDS];
u8 led_count;
/* GH Live */
struct urb *ghl_urb;
struct timer_list ghl_poke_timer;
};
static void sony_set_leds(struct sony_sc *sc);
static inline void sony_schedule_work(struct sony_sc *sc,
enum sony_worker which)
{
unsigned long flags;
switch (which) {
case SONY_WORKER_STATE:
spin_lock_irqsave(&sc->lock, flags);
if (!sc->defer_initialization && sc->state_worker_initialized)
schedule_work(&sc->state_worker);
spin_unlock_irqrestore(&sc->lock, flags);
break;
}
}
static void ghl_magic_poke_cb(struct urb *urb)
{
struct sony_sc *sc = urb->context;
if (urb->status < 0)
hid_err(sc->hdev, "URB transfer failed : %d", urb->status);
mod_timer(&sc->ghl_poke_timer, jiffies + GHL_GUITAR_POKE_INTERVAL*HZ);
}
static void ghl_magic_poke(struct timer_list *t)
{
int ret;
struct sony_sc *sc = from_timer(sc, t, ghl_poke_timer);
ret = usb_submit_urb(sc->ghl_urb, GFP_ATOMIC);
if (ret < 0)
hid_err(sc->hdev, "usb_submit_urb failed: %d", ret);
}
static int ghl_init_urb(struct sony_sc *sc, struct usb_device *usbdev,
const char ghl_magic_data[], u16 poke_size)
{
struct usb_ctrlrequest *cr;
u8 *databuf;
unsigned int pipe;
u16 ghl_magic_value = (((HID_OUTPUT_REPORT + 1) << 8) | ghl_magic_data[0]);
pipe = usb_sndctrlpipe(usbdev, 0);
cr = devm_kzalloc(&sc->hdev->dev, sizeof(*cr), GFP_ATOMIC);
if (cr == NULL)
return -ENOMEM;
databuf = devm_kzalloc(&sc->hdev->dev, poke_size, GFP_ATOMIC);
if (databuf == NULL)
return -ENOMEM;
cr->bRequestType =
USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_OUT;
cr->bRequest = USB_REQ_SET_CONFIGURATION;
cr->wValue = cpu_to_le16(ghl_magic_value);
cr->wIndex = 0;
cr->wLength = cpu_to_le16(poke_size);
memcpy(databuf, ghl_magic_data, poke_size);
usb_fill_control_urb(
sc->ghl_urb, usbdev, pipe,
(unsigned char *) cr, databuf, poke_size,
ghl_magic_poke_cb, sc);
return 0;
}
static int guitar_mapping(struct hid_device *hdev, struct hid_input *hi,
struct hid_field *field, struct hid_usage *usage,
unsigned long **bit, int *max)
{
if ((usage->hid & HID_USAGE_PAGE) == HID_UP_MSVENDOR) {
unsigned int abs = usage->hid & HID_USAGE;
if (abs == GUITAR_TILT_USAGE) {
hid_map_usage_clear(hi, usage, bit, max, EV_ABS, ABS_RY);
return 1;
}
}
return 0;
}
static const u8 *motion_fixup(struct hid_device *hdev, u8 *rdesc,
unsigned int *rsize)
{
*rsize = sizeof(motion_rdesc);
return motion_rdesc;
}
static const u8 *ps3remote_fixup(struct hid_device *hdev, u8 *rdesc,
unsigned int *rsize)
{
*rsize = sizeof(ps3remote_rdesc);
return ps3remote_rdesc;
}
static int ps3remote_mapping(struct hid_device *hdev, struct hid_input *hi,
struct hid_field *field, struct hid_usage *usage,
unsigned long **bit, int *max)
{
unsigned int key = usage->hid & HID_USAGE;
if ((usage->hid & HID_USAGE_PAGE) != HID_UP_BUTTON)
return -1;
switch (usage->collection_index) {
case 1:
if (key >= ARRAY_SIZE(ps3remote_keymap_joypad_buttons))
return -1;
key = ps3remote_keymap_joypad_buttons[key];
if (!key)
return -1;
break;
case 2:
if (key >= ARRAY_SIZE(ps3remote_keymap_remote_buttons))
return -1;
key = ps3remote_keymap_remote_buttons[key];
if (!key)
return -1;
break;
default:
return -1;
}
hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key);
return 1;
}
static int navigation_mapping(struct hid_device *hdev, struct hid_input *hi,
struct hid_field *field, struct hid_usage *usage,
unsigned long **bit, int *max)
{
if ((usage->hid & HID_USAGE_PAGE) == HID_UP_BUTTON) {
unsigned int key = usage->hid & HID_USAGE;
if (key >= ARRAY_SIZE(sixaxis_keymap))
return -1;
key = navigation_keymap[key];
if (!key)
return -1;
hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key);
return 1;
} else if (usage->hid == HID_GD_POINTER) {
/* See comment in sixaxis_mapping, basically the L2 (and R2)
* triggers are reported through GD Pointer.
* In addition we ignore any analog button 'axes' and only
* support digital buttons.
*/
switch (usage->usage_index) {
case 8: /* L2 */
usage->hid = HID_GD_Z;
break;
default:
return -1;
}
hid_map_usage_clear(hi, usage, bit, max, EV_ABS, usage->hid & 0xf);
return 1;
} else if ((usage->hid & HID_USAGE_PAGE) == HID_UP_GENDESK) {
unsigned int abs = usage->hid & HID_USAGE;
if (abs >= ARRAY_SIZE(navigation_absmap))
return -1;
abs = navigation_absmap[abs];
hid_map_usage_clear(hi, usage, bit, max, EV_ABS, abs);
return 1;
}
return -1;
}
static int sixaxis_mapping(struct hid_device *hdev, struct hid_input *hi,
struct hid_field *field, struct hid_usage *usage,
unsigned long **bit, int *max)
{
if ((usage->hid & HID_USAGE_PAGE) == HID_UP_BUTTON) {
unsigned int key = usage->hid & HID_USAGE;
if (key >= ARRAY_SIZE(sixaxis_keymap))
return -1;
key = sixaxis_keymap[key];
hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key);
return 1;
} else if (usage->hid == HID_GD_POINTER) {
/* The DS3 provides analog values for most buttons and even
* for HAT axes through GD Pointer. L2 and R2 are reported
* among these as well instead of as GD Z / RZ. Remap L2
* and R2 and ignore other analog 'button axes' as there is
* no good way for reporting them.
*/
switch (usage->usage_index) {
case 8: /* L2 */
usage->hid = HID_GD_Z;
break;
case 9: /* R2 */
usage->hid = HID_GD_RZ;
break;
default:
return -1;
}
hid_map_usage_clear(hi, usage, bit, max, EV_ABS, usage->hid & 0xf);
return 1;
} else if ((usage->hid & HID_USAGE_PAGE) == HID_UP_GENDESK) {
unsigned int abs = usage->hid & HID_USAGE;
if (abs >= ARRAY_SIZE(sixaxis_absmap))
return -1;
abs = sixaxis_absmap[abs];
hid_map_usage_clear(hi, usage, bit, max, EV_ABS, abs);
return 1;
}
return -1;
}
static const u8 *sony_report_fixup(struct hid_device *hdev, u8 *rdesc,
unsigned int *rsize)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
if (sc->quirks & (SINO_LITE_CONTROLLER | FUTUREMAX_DANCE_MAT))
return rdesc;
/*
* Some Sony RF receivers wrongly declare the mouse pointer as a
* a constant non-data variable.
*/
if ((sc->quirks & VAIO_RDESC_CONSTANT) && *rsize >= 56 &&
/* usage page: generic desktop controls */
/* rdesc[0] == 0x05 && rdesc[1] == 0x01 && */
/* usage: mouse */
rdesc[2] == 0x09 && rdesc[3] == 0x02 &&
/* input (usage page for x,y axes): constant, variable, relative */
rdesc[54] == 0x81 && rdesc[55] == 0x07) {
hid_info(hdev, "Fixing up Sony RF Receiver report descriptor\n");
/* input: data, variable, relative */
rdesc[55] = 0x06;
}
if (sc->quirks & MOTION_CONTROLLER)
return motion_fixup(hdev, rdesc, rsize);
if (sc->quirks & PS3REMOTE)
return ps3remote_fixup(hdev, rdesc, rsize);
/*
* Some knock-off USB dongles incorrectly report their button count
* as 13 instead of 16 causing three non-functional buttons.
*/
if ((sc->quirks & SIXAXIS_CONTROLLER_USB) && *rsize >= 45 &&
/* Report Count (13) */
rdesc[23] == 0x95 && rdesc[24] == 0x0D &&
/* Usage Maximum (13) */
rdesc[37] == 0x29 && rdesc[38] == 0x0D &&
/* Report Count (3) */
rdesc[43] == 0x95 && rdesc[44] == 0x03) {
hid_info(hdev, "Fixing up USB dongle report descriptor\n");
rdesc[24] = 0x10;
rdesc[38] = 0x10;
rdesc[44] = 0x00;
}
return rdesc;
}
static void sixaxis_parse_report(struct sony_sc *sc, u8 *rd, int size)
{
static const u8 sixaxis_battery_capacity[] = { 0, 1, 25, 50, 75, 100 };
unsigned long flags;
int offset;
u8 battery_capacity;
int battery_status;
/*
* The sixaxis is charging if the battery value is 0xee
* and it is fully charged if the value is 0xef.
* It does not report the actual level while charging so it
* is set to 100% while charging is in progress.
*/
offset = (sc->quirks & MOTION_CONTROLLER) ? 12 : 30;
if (rd[offset] >= 0xee) {
battery_capacity = 100;
battery_status = (rd[offset] & 0x01) ? POWER_SUPPLY_STATUS_FULL : POWER_SUPPLY_STATUS_CHARGING;
} else {
u8 index = rd[offset] <= 5 ? rd[offset] : 5;
battery_capacity = sixaxis_battery_capacity[index];
battery_status = POWER_SUPPLY_STATUS_DISCHARGING;
}
spin_lock_irqsave(&sc->lock, flags);
sc->battery_capacity = battery_capacity;
sc->battery_status = battery_status;
spin_unlock_irqrestore(&sc->lock, flags);
if (sc->quirks & SIXAXIS_CONTROLLER) {
int val;
offset = SIXAXIS_INPUT_REPORT_ACC_X_OFFSET;
val = ((rd[offset+1] << 8) | rd[offset]) - 511;
input_report_abs(sc->sensor_dev, ABS_X, val);
/* Y and Z are swapped and inversed */
val = 511 - ((rd[offset+5] << 8) | rd[offset+4]);
input_report_abs(sc->sensor_dev, ABS_Y, val);
val = 511 - ((rd[offset+3] << 8) | rd[offset+2]);
input_report_abs(sc->sensor_dev, ABS_Z, val);
input_sync(sc->sensor_dev);
}
}
static void nsg_mrxu_parse_report(struct sony_sc *sc, u8 *rd, int size)
{
int n, offset, relx, rely;
u8 active;
/*
* The NSG-MRxU multi-touch trackpad data starts at offset 1 and
* the touch-related data starts at offset 2.
* For the first byte, bit 0 is set when touchpad button is pressed.
* Bit 2 is set when a touch is active and the drag (Fn) key is pressed.
* This drag key is mapped to BTN_LEFT. It is operational only when a
* touch point is active.
* Bit 4 is set when only the first touch point is active.
* Bit 6 is set when only the second touch point is active.
* Bits 5 and 7 are set when both touch points are active.
* The next 3 bytes are two 12 bit X/Y coordinates for the first touch.
* The following byte, offset 5, has the touch width and length.
* Bits 0-4=X (width), bits 5-7=Y (length).
* A signed relative X coordinate is at offset 6.
* The bytes at offset 7-9 are the second touch X/Y coordinates.
* Offset 10 has the second touch width and length.
* Offset 11 has the relative Y coordinate.
*/
offset = 1;
input_report_key(sc->touchpad, BTN_LEFT, rd[offset] & 0x0F);
active = (rd[offset] >> 4);
relx = (s8) rd[offset+5];
rely = ((s8) rd[offset+10]) * -1;
offset++;
for (n = 0; n < 2; n++) {
u16 x, y;
u8 contactx, contacty;
x = rd[offset] | ((rd[offset+1] & 0x0F) << 8);
y = ((rd[offset+1] & 0xF0) >> 4) | (rd[offset+2] << 4);
input_mt_slot(sc->touchpad, n);
input_mt_report_slot_state(sc->touchpad, MT_TOOL_FINGER, active & 0x03);
if (active & 0x03) {
contactx = rd[offset+3] & 0x0F;
contacty = rd[offset+3] >> 4;
input_report_abs(sc->touchpad, ABS_MT_TOUCH_MAJOR,
max(contactx, contacty));
input_report_abs(sc->touchpad, ABS_MT_TOUCH_MINOR,
min(contactx, contacty));
input_report_abs(sc->touchpad, ABS_MT_ORIENTATION,
(bool) (contactx > contacty));
input_report_abs(sc->touchpad, ABS_MT_POSITION_X, x);
input_report_abs(sc->touchpad, ABS_MT_POSITION_Y,
NSG_MRXU_MAX_Y - y);
/*
* The relative coordinates belong to the first touch
* point, when present, or to the second touch point
* when the first is not active.
*/
if ((n == 0) || ((n == 1) && (active & 0x01))) {
input_report_rel(sc->touchpad, REL_X, relx);
input_report_rel(sc->touchpad, REL_Y, rely);
}
}
offset += 5;
active >>= 2;
}
input_mt_sync_frame(sc->touchpad);
input_sync(sc->touchpad);
}
static int sony_raw_event(struct hid_device *hdev, struct hid_report *report,
u8 *rd, int size)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
/*
* Sixaxis HID report has acclerometers/gyro with MSByte first, this
* has to be BYTE_SWAPPED before passing up to joystick interface
*/
if ((sc->quirks & SIXAXIS_CONTROLLER) && rd[0] == 0x01 && size == 49) {
/*
* When connected via Bluetooth the Sixaxis occasionally sends
* a report with the second byte 0xff and the rest zeroed.
*
* This report does not reflect the actual state of the
* controller must be ignored to avoid generating false input
* events.
*/
if (rd[1] == 0xff)
return -EINVAL;
swap(rd[41], rd[42]);
swap(rd[43], rd[44]);
swap(rd[45], rd[46]);
swap(rd[47], rd[48]);
sixaxis_parse_report(sc, rd, size);
} else if ((sc->quirks & MOTION_CONTROLLER_BT) && rd[0] == 0x01 && size == 49) {
sixaxis_parse_report(sc, rd, size);
} else if ((sc->quirks & NAVIGATION_CONTROLLER) && rd[0] == 0x01 &&
size == 49) {
sixaxis_parse_report(sc, rd, size);
} else if ((sc->quirks & NSG_MRXU_REMOTE) && rd[0] == 0x02) {
nsg_mrxu_parse_report(sc, rd, size);
return 1;
}
if (sc->defer_initialization) {
sc->defer_initialization = 0;
sony_schedule_work(sc, SONY_WORKER_STATE);
}
return 0;
}
static int sony_mapping(struct hid_device *hdev, struct hid_input *hi,
struct hid_field *field, struct hid_usage *usage,
unsigned long **bit, int *max)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
if (sc->quirks & BUZZ_CONTROLLER) {
unsigned int key = usage->hid & HID_USAGE;
if ((usage->hid & HID_USAGE_PAGE) != HID_UP_BUTTON)
return -1;
switch (usage->collection_index) {
case 1:
if (key >= ARRAY_SIZE(buzz_keymap))
return -1;
key = buzz_keymap[key];
if (!key)
return -1;
break;
default:
return -1;
}
hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key);
return 1;
}
if (sc->quirks & PS3REMOTE)
return ps3remote_mapping(hdev, hi, field, usage, bit, max);
if (sc->quirks & NAVIGATION_CONTROLLER)
return navigation_mapping(hdev, hi, field, usage, bit, max);
if (sc->quirks & SIXAXIS_CONTROLLER)
return sixaxis_mapping(hdev, hi, field, usage, bit, max);
if (sc->quirks & GH_GUITAR_CONTROLLER)
return guitar_mapping(hdev, hi, field, usage, bit, max);
/* Let hid-core decide for the others */
return 0;
}
static int sony_register_touchpad(struct sony_sc *sc, int touch_count,
int w, int h, int touch_major, int touch_minor, int orientation)
{
size_t name_sz;
char *name;
int ret;
sc->touchpad = devm_input_allocate_device(&sc->hdev->dev);
if (!sc->touchpad)
return -ENOMEM;
input_set_drvdata(sc->touchpad, sc);
sc->touchpad->dev.parent = &sc->hdev->dev;
sc->touchpad->phys = sc->hdev->phys;
sc->touchpad->uniq = sc->hdev->uniq;
sc->touchpad->id.bustype = sc->hdev->bus;
sc->touchpad->id.vendor = sc->hdev->vendor;
sc->touchpad->id.product = sc->hdev->product;
sc->touchpad->id.version = sc->hdev->version;
/* This suffix was originally apended when hid-sony also
* supported DS4 devices. The DS4 was implemented using multiple
* evdev nodes and hence had the need to separete them out using
* a suffix. Other devices which were added later like Sony TV remotes
* inhirited this suffix.
*/
name_sz = strlen(sc->hdev->name) + sizeof(TOUCHPAD_SUFFIX);
name = devm_kzalloc(&sc->hdev->dev, name_sz, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(name, name_sz, "%s" TOUCHPAD_SUFFIX, sc->hdev->name);
sc->touchpad->name = name;
/* We map the button underneath the touchpad to BTN_LEFT. */
__set_bit(EV_KEY, sc->touchpad->evbit);
__set_bit(BTN_LEFT, sc->touchpad->keybit);
__set_bit(INPUT_PROP_BUTTONPAD, sc->touchpad->propbit);
input_set_abs_params(sc->touchpad, ABS_MT_POSITION_X, 0, w, 0, 0);
input_set_abs_params(sc->touchpad, ABS_MT_POSITION_Y, 0, h, 0, 0);
if (touch_major > 0) {
input_set_abs_params(sc->touchpad, ABS_MT_TOUCH_MAJOR,
0, touch_major, 0, 0);
if (touch_minor > 0)
input_set_abs_params(sc->touchpad, ABS_MT_TOUCH_MINOR,
0, touch_minor, 0, 0);
if (orientation > 0)
input_set_abs_params(sc->touchpad, ABS_MT_ORIENTATION,
0, orientation, 0, 0);
}
if (sc->quirks & NSG_MRXU_REMOTE) {
__set_bit(EV_REL, sc->touchpad->evbit);
}
ret = input_mt_init_slots(sc->touchpad, touch_count, INPUT_MT_POINTER);
if (ret < 0)
return ret;
ret = input_register_device(sc->touchpad);
if (ret < 0)
return ret;
return 0;
}
static int sony_register_sensors(struct sony_sc *sc)
{
size_t name_sz;
char *name;
int ret;
sc->sensor_dev = devm_input_allocate_device(&sc->hdev->dev);
if (!sc->sensor_dev)
return -ENOMEM;
input_set_drvdata(sc->sensor_dev, sc);
sc->sensor_dev->dev.parent = &sc->hdev->dev;
sc->sensor_dev->phys = sc->hdev->phys;
sc->sensor_dev->uniq = sc->hdev->uniq;
sc->sensor_dev->id.bustype = sc->hdev->bus;
sc->sensor_dev->id.vendor = sc->hdev->vendor;
sc->sensor_dev->id.product = sc->hdev->product;
sc->sensor_dev->id.version = sc->hdev->version;
/* Append a suffix to the controller name as there are various
* DS4 compatible non-Sony devices with different names.
*/
name_sz = strlen(sc->hdev->name) + sizeof(SENSOR_SUFFIX);
name = devm_kzalloc(&sc->hdev->dev, name_sz, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(name, name_sz, "%s" SENSOR_SUFFIX, sc->hdev->name);
sc->sensor_dev->name = name;
if (sc->quirks & SIXAXIS_CONTROLLER) {
/* For the DS3 we only support the accelerometer, which works
* quite well even without calibration. The device also has
* a 1-axis gyro, but it is very difficult to manage from within
* the driver even to get data, the sensor is inaccurate and
* the behavior is very different between hardware revisions.
*/
input_set_abs_params(sc->sensor_dev, ABS_X, -512, 511, 4, 0);
input_set_abs_params(sc->sensor_dev, ABS_Y, -512, 511, 4, 0);
input_set_abs_params(sc->sensor_dev, ABS_Z, -512, 511, 4, 0);
input_abs_set_res(sc->sensor_dev, ABS_X, SIXAXIS_ACC_RES_PER_G);
input_abs_set_res(sc->sensor_dev, ABS_Y, SIXAXIS_ACC_RES_PER_G);
input_abs_set_res(sc->sensor_dev, ABS_Z, SIXAXIS_ACC_RES_PER_G);
}
__set_bit(INPUT_PROP_ACCELEROMETER, sc->sensor_dev->propbit);
ret = input_register_device(sc->sensor_dev);
if (ret < 0)
return ret;
return 0;
}
/*
* Sending HID_REQ_GET_REPORT changes the operation mode of the ps3 controller
* to "operational". Without this, the ps3 controller will not report any
* events.
*/
static int sixaxis_set_operational_usb(struct hid_device *hdev)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
const int buf_size =
max(SIXAXIS_REPORT_0xF2_SIZE, SIXAXIS_REPORT_0xF5_SIZE);
u8 *buf;
int ret;
buf = kmalloc(buf_size, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = hid_hw_raw_request(hdev, 0xf2, buf, SIXAXIS_REPORT_0xF2_SIZE,
HID_FEATURE_REPORT, HID_REQ_GET_REPORT);
if (ret < 0) {
hid_err(hdev, "can't set operational mode: step 1\n");
goto out;
}
/*
* Some compatible controllers like the Speedlink Strike FX and
* Gasia need another query plus an USB interrupt to get operational.
*/
ret = hid_hw_raw_request(hdev, 0xf5, buf, SIXAXIS_REPORT_0xF5_SIZE,
HID_FEATURE_REPORT, HID_REQ_GET_REPORT);
if (ret < 0) {
hid_err(hdev, "can't set operational mode: step 2\n");
goto out;
}
/*
* But the USB interrupt would cause SHANWAN controllers to
* start rumbling non-stop, so skip step 3 for these controllers.
*/
if (sc->quirks & SHANWAN_GAMEPAD)
goto out;
ret = hid_hw_output_report(hdev, buf, 1);
if (ret < 0) {
hid_info(hdev, "can't set operational mode: step 3, ignoring\n");
ret = 0;
}
out:
kfree(buf);
return ret;
}
static int sixaxis_set_operational_bt(struct hid_device *hdev)
{
static const u8 report[] = { 0xf4, 0x42, 0x03, 0x00, 0x00 };
u8 *buf;
int ret;
buf = kmemdup(report, sizeof(report), GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = hid_hw_raw_request(hdev, buf[0], buf, sizeof(report),
HID_FEATURE_REPORT, HID_REQ_SET_REPORT);
kfree(buf);
return ret;
}
static void sixaxis_set_leds_from_id(struct sony_sc *sc)
{
static const u8 sixaxis_leds[10][4] = {
{ 0x01, 0x00, 0x00, 0x00 },
{ 0x00, 0x01, 0x00, 0x00 },
{ 0x00, 0x00, 0x01, 0x00 },
{ 0x00, 0x00, 0x00, 0x01 },
{ 0x01, 0x00, 0x00, 0x01 },
{ 0x00, 0x01, 0x00, 0x01 },
{ 0x00, 0x00, 0x01, 0x01 },
{ 0x01, 0x00, 0x01, 0x01 },
{ 0x00, 0x01, 0x01, 0x01 },
{ 0x01, 0x01, 0x01, 0x01 }
};
int id = sc->device_id;
BUILD_BUG_ON(MAX_LEDS < ARRAY_SIZE(sixaxis_leds[0]));
if (id < 0)
return;
id %= 10;
memcpy(sc->led_state, sixaxis_leds[id], sizeof(sixaxis_leds[id]));
}
static void buzz_set_leds(struct sony_sc *sc)
{
struct hid_device *hdev = sc->hdev;
struct list_head *report_list =
&hdev->report_enum[HID_OUTPUT_REPORT].report_list;
struct hid_report *report = list_entry(report_list->next,
struct hid_report, list);
s32 *value = report->field[0]->value;
BUILD_BUG_ON(MAX_LEDS < 4);
value[0] = 0x00;
value[1] = sc->led_state[0] ? 0xff : 0x00;
value[2] = sc->led_state[1] ? 0xff : 0x00;
value[3] = sc->led_state[2] ? 0xff : 0x00;
value[4] = sc->led_state[3] ? 0xff : 0x00;
value[5] = 0x00;
value[6] = 0x00;
hid_hw_request(hdev, report, HID_REQ_SET_REPORT);
}
static void sony_set_leds(struct sony_sc *sc)
{
if (!(sc->quirks & BUZZ_CONTROLLER))
sony_schedule_work(sc, SONY_WORKER_STATE);
else
buzz_set_leds(sc);
}
static void sony_led_set_brightness(struct led_classdev *led,
enum led_brightness value)
{
struct device *dev = led->dev->parent;
struct hid_device *hdev = to_hid_device(dev);
struct sony_sc *drv_data;
int n;
int force_update;
drv_data = hid_get_drvdata(hdev);
if (!drv_data) {
hid_err(hdev, "No device data\n");
return;
}
/*
* The Sixaxis on USB will override any LED settings sent to it
* and keep flashing all of the LEDs until the PS button is pressed.
* Updates, even if redundant, must be always be sent to the
* controller to avoid having to toggle the state of an LED just to
* stop the flashing later on.
*/
force_update = !!(drv_data->quirks & SIXAXIS_CONTROLLER_USB);
for (n = 0; n < drv_data->led_count; n++) {
if (led == drv_data->leds[n] && (force_update ||
(value != drv_data->led_state[n] ||
drv_data->led_delay_on[n] ||
drv_data->led_delay_off[n]))) {
drv_data->led_state[n] = value;
/* Setting the brightness stops the blinking */
drv_data->led_delay_on[n] = 0;
drv_data->led_delay_off[n] = 0;
sony_set_leds(drv_data);
break;
}
}
}
static enum led_brightness sony_led_get_brightness(struct led_classdev *led)
{
struct device *dev = led->dev->parent;
struct hid_device *hdev = to_hid_device(dev);
struct sony_sc *drv_data;
int n;
drv_data = hid_get_drvdata(hdev);
if (!drv_data) {
hid_err(hdev, "No device data\n");
return LED_OFF;
}
for (n = 0; n < drv_data->led_count; n++) {
if (led == drv_data->leds[n])
return drv_data->led_state[n];
}
return LED_OFF;
}
static int sony_led_blink_set(struct led_classdev *led, unsigned long *delay_on,
unsigned long *delay_off)
{
struct device *dev = led->dev->parent;
struct hid_device *hdev = to_hid_device(dev);
struct sony_sc *drv_data = hid_get_drvdata(hdev);
int n;
u8 new_on, new_off;
if (!drv_data) {
hid_err(hdev, "No device data\n");
return -EINVAL;
}
/* Max delay is 255 deciseconds or 2550 milliseconds */
if (*delay_on > 2550)
*delay_on = 2550;
if (*delay_off > 2550)
*delay_off = 2550;
/* Blink at 1 Hz if both values are zero */
if (!*delay_on && !*delay_off)
*delay_on = *delay_off = 500;
new_on = *delay_on / 10;
new_off = *delay_off / 10;
for (n = 0; n < drv_data->led_count; n++) {
if (led == drv_data->leds[n])
break;
}
/* This LED is not registered on this device */
if (n >= drv_data->led_count)
return -EINVAL;
/* Don't schedule work if the values didn't change */
if (new_on != drv_data->led_delay_on[n] ||
new_off != drv_data->led_delay_off[n]) {
drv_data->led_delay_on[n] = new_on;
drv_data->led_delay_off[n] = new_off;
sony_schedule_work(drv_data, SONY_WORKER_STATE);
}
return 0;
}
static int sony_leds_init(struct sony_sc *sc)
{
struct hid_device *hdev = sc->hdev;
int n, ret = 0;
int use_color_names;
struct led_classdev *led;
size_t name_sz;
char *name;
size_t name_len;
const char *name_fmt;
static const char * const color_name_str[] = { "red", "green", "blue",
"global" };
u8 max_brightness[MAX_LEDS] = { [0 ... (MAX_LEDS - 1)] = 1 };
u8 use_hw_blink[MAX_LEDS] = { 0 };
if (WARN_ON(!(sc->quirks & SONY_LED_SUPPORT)))
return -EINVAL;
if (sc->quirks & BUZZ_CONTROLLER) {
sc->led_count = 4;
use_color_names = 0;
name_len = strlen("::buzz#");
name_fmt = "%s::buzz%d";
/* Validate expected report characteristics. */
if (!hid_validate_values(hdev, HID_OUTPUT_REPORT, 0, 0, 7))
return -ENODEV;
} else if (sc->quirks & MOTION_CONTROLLER) {
sc->led_count = 3;
memset(max_brightness, 255, 3);
use_color_names = 1;
name_len = 0;
name_fmt = "%s:%s";
} else if (sc->quirks & NAVIGATION_CONTROLLER) {
static const u8 navigation_leds[4] = {0x01, 0x00, 0x00, 0x00};
memcpy(sc->led_state, navigation_leds, sizeof(navigation_leds));
sc->led_count = 1;
memset(use_hw_blink, 1, 4);
use_color_names = 0;
name_len = strlen("::sony#");
name_fmt = "%s::sony%d";
} else {
sixaxis_set_leds_from_id(sc);
sc->led_count = 4;
memset(use_hw_blink, 1, 4);
use_color_names = 0;
name_len = strlen("::sony#");
name_fmt = "%s::sony%d";
}
/*
* Clear LEDs as we have no way of reading their initial state. This is
* only relevant if the driver is loaded after somebody actively set the
* LEDs to on
*/
sony_set_leds(sc);
name_sz = strlen(dev_name(&hdev->dev)) + name_len + 1;
for (n = 0; n < sc->led_count; n++) {
if (use_color_names)
name_sz = strlen(dev_name(&hdev->dev)) + strlen(color_name_str[n]) + 2;
led = devm_kzalloc(&hdev->dev, sizeof(struct led_classdev) + name_sz, GFP_KERNEL);
if (!led) {
hid_err(hdev, "Couldn't allocate memory for LED %d\n", n);
return -ENOMEM;
}
name = (void *)(&led[1]);
if (use_color_names)
snprintf(name, name_sz, name_fmt, dev_name(&hdev->dev),
color_name_str[n]);
else
snprintf(name, name_sz, name_fmt, dev_name(&hdev->dev), n + 1);
led->name = name;
led->brightness = sc->led_state[n];
led->max_brightness = max_brightness[n];
led->flags = LED_CORE_SUSPENDRESUME;
led->brightness_get = sony_led_get_brightness;
led->brightness_set = sony_led_set_brightness;
if (use_hw_blink[n])
led->blink_set = sony_led_blink_set;
sc->leds[n] = led;
ret = devm_led_classdev_register(&hdev->dev, led);
if (ret) {
hid_err(hdev, "Failed to register LED %d\n", n);
return ret;
}
}
return 0;
}
static void sixaxis_send_output_report(struct sony_sc *sc)
{
static const union sixaxis_output_report_01 default_report = {
.buf = {
0x01,
0x01, 0xff, 0x00, 0xff, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
0xff, 0x27, 0x10, 0x00, 0x32,
0xff, 0x27, 0x10, 0x00, 0x32,
0xff, 0x27, 0x10, 0x00, 0x32,
0xff, 0x27, 0x10, 0x00, 0x32,
0x00, 0x00, 0x00, 0x00, 0x00
}
};
struct sixaxis_output_report *report =
(struct sixaxis_output_report *)sc->output_report_dmabuf;
int n;
/* Initialize the report with default values */
memcpy(report, &default_report, sizeof(struct sixaxis_output_report));
#ifdef CONFIG_SONY_FF
report->rumble.right_motor_on = sc->right ? 1 : 0;
report->rumble.left_motor_force = sc->left;
#endif
report->leds_bitmap |= sc->led_state[0] << 1;
report->leds_bitmap |= sc->led_state[1] << 2;
report->leds_bitmap |= sc->led_state[2] << 3;
report->leds_bitmap |= sc->led_state[3] << 4;
/* Set flag for all leds off, required for 3rd party INTEC controller */
if ((report->leds_bitmap & 0x1E) == 0)
report->leds_bitmap |= 0x20;
/*
* The LEDs in the report are indexed in reverse order to their
* corresponding light on the controller.
* Index 0 = LED 4, index 1 = LED 3, etc...
*
* In the case of both delay values being zero (blinking disabled) the
* default report values should be used or the controller LED will be
* always off.
*/
for (n = 0; n < 4; n++) {
if (sc->led_delay_on[n] || sc->led_delay_off[n]) {
report->led[3 - n].duty_off = sc->led_delay_off[n];
report->led[3 - n].duty_on = sc->led_delay_on[n];
}
}
/* SHANWAN controllers require output reports via intr channel */
if (sc->quirks & SHANWAN_GAMEPAD)
hid_hw_output_report(sc->hdev, (u8 *)report,
sizeof(struct sixaxis_output_report));
else
hid_hw_raw_request(sc->hdev, report->report_id, (u8 *)report,
sizeof(struct sixaxis_output_report),
HID_OUTPUT_REPORT, HID_REQ_SET_REPORT);
}
static void motion_send_output_report(struct sony_sc *sc)
{
struct hid_device *hdev = sc->hdev;
struct motion_output_report_02 *report =
(struct motion_output_report_02 *)sc->output_report_dmabuf;
memset(report, 0, MOTION_REPORT_0x02_SIZE);
report->type = 0x02; /* set leds */
report->r = sc->led_state[0];
report->g = sc->led_state[1];
report->b = sc->led_state[2];
#ifdef CONFIG_SONY_FF
report->rumble = max(sc->right, sc->left);
#endif
hid_hw_output_report(hdev, (u8 *)report, MOTION_REPORT_0x02_SIZE);
}
#ifdef CONFIG_SONY_FF
static inline void sony_send_output_report(struct sony_sc *sc)
{
if (sc->send_output_report)
sc->send_output_report(sc);
}
#endif
static void sony_state_worker(struct work_struct *work)
{
struct sony_sc *sc = container_of(work, struct sony_sc, state_worker);
sc->send_output_report(sc);
}
static int sony_allocate_output_report(struct sony_sc *sc)
{
if ((sc->quirks & SIXAXIS_CONTROLLER) ||
(sc->quirks & NAVIGATION_CONTROLLER))
sc->output_report_dmabuf =
devm_kmalloc(&sc->hdev->dev,
sizeof(union sixaxis_output_report_01),
GFP_KERNEL);
else if (sc->quirks & MOTION_CONTROLLER)
sc->output_report_dmabuf = devm_kmalloc(&sc->hdev->dev,
MOTION_REPORT_0x02_SIZE,
GFP_KERNEL);
else
return 0;
if (!sc->output_report_dmabuf)
return -ENOMEM;
return 0;
}
#ifdef CONFIG_SONY_FF
static int sony_play_effect(struct input_dev *dev, void *data,
struct ff_effect *effect)
{
struct hid_device *hid = input_get_drvdata(dev);
struct sony_sc *sc = hid_get_drvdata(hid);
if (effect->type != FF_RUMBLE)
return 0;
sc->left = effect->u.rumble.strong_magnitude / 256;
sc->right = effect->u.rumble.weak_magnitude / 256;
sony_schedule_work(sc, SONY_WORKER_STATE);
return 0;
}
static int sony_init_ff(struct sony_sc *sc)
{
struct hid_input *hidinput;
struct input_dev *input_dev;
if (list_empty(&sc->hdev->inputs)) {
hid_err(sc->hdev, "no inputs found\n");
return -ENODEV;
}
hidinput = list_entry(sc->hdev->inputs.next, struct hid_input, list);
input_dev = hidinput->input;
input_set_capability(input_dev, EV_FF, FF_RUMBLE);
return input_ff_create_memless(input_dev, NULL, sony_play_effect);
}
#else
static int sony_init_ff(struct sony_sc *sc)
{
return 0;
}
#endif
static int sony_battery_get_property(struct power_supply *psy,
enum power_supply_property psp,
union power_supply_propval *val)
{
struct sony_sc *sc = power_supply_get_drvdata(psy);
unsigned long flags;
int ret = 0;
u8 battery_capacity;
int battery_status;
spin_lock_irqsave(&sc->lock, flags);
battery_capacity = sc->battery_capacity;
battery_status = sc->battery_status;
spin_unlock_irqrestore(&sc->lock, flags);
switch (psp) {
case POWER_SUPPLY_PROP_PRESENT:
val->intval = 1;
break;
case POWER_SUPPLY_PROP_SCOPE:
val->intval = POWER_SUPPLY_SCOPE_DEVICE;
break;
case POWER_SUPPLY_PROP_CAPACITY:
val->intval = battery_capacity;
break;
case POWER_SUPPLY_PROP_STATUS:
val->intval = battery_status;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int sony_battery_probe(struct sony_sc *sc, int append_dev_id)
{
const char *battery_str_fmt = append_dev_id ?
"sony_controller_battery_%pMR_%i" :
"sony_controller_battery_%pMR";
struct power_supply_config psy_cfg = { .drv_data = sc, };
struct hid_device *hdev = sc->hdev;
int ret;
/*
* Set the default battery level to 100% to avoid low battery warnings
* if the battery is polled before the first device report is received.
*/
sc->battery_capacity = 100;
sc->battery_desc.properties = sony_battery_props;
sc->battery_desc.num_properties = ARRAY_SIZE(sony_battery_props);
sc->battery_desc.get_property = sony_battery_get_property;
sc->battery_desc.type = POWER_SUPPLY_TYPE_BATTERY;
sc->battery_desc.use_for_apm = 0;
sc->battery_desc.name = devm_kasprintf(&hdev->dev, GFP_KERNEL,
battery_str_fmt, sc->mac_address, sc->device_id);
if (!sc->battery_desc.name)
return -ENOMEM;
sc->battery = devm_power_supply_register(&hdev->dev, &sc->battery_desc,
&psy_cfg);
if (IS_ERR(sc->battery)) {
ret = PTR_ERR(sc->battery);
hid_err(hdev, "Unable to register battery device\n");
return ret;
}
power_supply_powers(sc->battery, &hdev->dev);
return 0;
}
/*
* If a controller is plugged in via USB while already connected via Bluetooth
* it will show up as two devices. A global list of connected controllers and
* their MAC addresses is maintained to ensure that a device is only connected
* once.
*
* Some USB-only devices masquerade as Sixaxis controllers and all have the
* same dummy Bluetooth address, so a comparison of the connection type is
* required. Devices are only rejected in the case where two devices have
* matching Bluetooth addresses on different bus types.
*/
static inline int sony_compare_connection_type(struct sony_sc *sc0,
struct sony_sc *sc1)
{
const int sc0_not_bt = !(sc0->quirks & SONY_BT_DEVICE);
const int sc1_not_bt = !(sc1->quirks & SONY_BT_DEVICE);
return sc0_not_bt == sc1_not_bt;
}
static int sony_check_add_dev_list(struct sony_sc *sc)
{
struct sony_sc *entry;
unsigned long flags;
int ret;
spin_lock_irqsave(&sony_dev_list_lock, flags);
list_for_each_entry(entry, &sony_device_list, list_node) {
ret = memcmp(sc->mac_address, entry->mac_address,
sizeof(sc->mac_address));
if (!ret) {
if (sony_compare_connection_type(sc, entry)) {
ret = 1;
} else {
ret = -EEXIST;
hid_info(sc->hdev,
"controller with MAC address %pMR already connected\n",
sc->mac_address);
}
goto unlock;
}
}
ret = 0;
list_add(&(sc->list_node), &sony_device_list);
unlock:
spin_unlock_irqrestore(&sony_dev_list_lock, flags);
return ret;
}
static void sony_remove_dev_list(struct sony_sc *sc)
{
unsigned long flags;
if (sc->list_node.next) {
spin_lock_irqsave(&sony_dev_list_lock, flags);
list_del(&(sc->list_node));
spin_unlock_irqrestore(&sony_dev_list_lock, flags);
}
}
static int sony_get_bt_devaddr(struct sony_sc *sc)
{
int ret;
/* HIDP stores the device MAC address as a string in the uniq field. */
ret = strlen(sc->hdev->uniq);
if (ret != 17)
return -EINVAL;
ret = sscanf(sc->hdev->uniq,
"%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
&sc->mac_address[5], &sc->mac_address[4], &sc->mac_address[3],
&sc->mac_address[2], &sc->mac_address[1], &sc->mac_address[0]);
if (ret != 6)
return -EINVAL;
return 0;
}
static int sony_check_add(struct sony_sc *sc)
{
u8 *buf = NULL;
int n, ret;
if ((sc->quirks & MOTION_CONTROLLER_BT) ||
(sc->quirks & NAVIGATION_CONTROLLER_BT) ||
(sc->quirks & SIXAXIS_CONTROLLER_BT)) {
/*
* sony_get_bt_devaddr() attempts to parse the Bluetooth MAC
* address from the uniq string where HIDP stores it.
* As uniq cannot be guaranteed to be a MAC address in all cases
* a failure of this function should not prevent the connection.
*/
if (sony_get_bt_devaddr(sc) < 0) {
hid_warn(sc->hdev, "UNIQ does not contain a MAC address; duplicate check skipped\n");
return 0;
}
} else if ((sc->quirks & SIXAXIS_CONTROLLER_USB) ||
(sc->quirks & NAVIGATION_CONTROLLER_USB)) {
buf = kmalloc(SIXAXIS_REPORT_0xF2_SIZE, GFP_KERNEL);
if (!buf)
return -ENOMEM;
/*
* The MAC address of a Sixaxis controller connected via USB can
* be retrieved with feature report 0xf2. The address begins at
* offset 4.
*/
ret = hid_hw_raw_request(sc->hdev, 0xf2, buf,
SIXAXIS_REPORT_0xF2_SIZE, HID_FEATURE_REPORT,
HID_REQ_GET_REPORT);
if (ret != SIXAXIS_REPORT_0xF2_SIZE) {
hid_err(sc->hdev, "failed to retrieve feature report 0xf2 with the Sixaxis MAC address\n");
ret = ret < 0 ? ret : -EINVAL;
goto out_free;
}
/*
* The Sixaxis device MAC in the report is big-endian and must
* be byte-swapped.
*/
for (n = 0; n < 6; n++)
sc->mac_address[5-n] = buf[4+n];
snprintf(sc->hdev->uniq, sizeof(sc->hdev->uniq),
"%pMR", sc->mac_address);
} else {
return 0;
}
ret = sony_check_add_dev_list(sc);
out_free:
kfree(buf);
return ret;
}
static int sony_set_device_id(struct sony_sc *sc)
{
int ret;
/*
* Only Sixaxis controllers get an id.
* All others are set to -1.
*/
if (sc->quirks & SIXAXIS_CONTROLLER) {
ret = ida_alloc(&sony_device_id_allocator, GFP_KERNEL);
if (ret < 0) {
sc->device_id = -1;
return ret;
}
sc->device_id = ret;
} else {
sc->device_id = -1;
}
return 0;
}
static void sony_release_device_id(struct sony_sc *sc)
{
if (sc->device_id >= 0) {
ida_free(&sony_device_id_allocator, sc->device_id);
sc->device_id = -1;
}
}
static inline void sony_init_output_report(struct sony_sc *sc,
void (*send_output_report)(struct sony_sc *))
{
sc->send_output_report = send_output_report;
if (!sc->state_worker_initialized)
INIT_WORK(&sc->state_worker, sony_state_worker);
sc->state_worker_initialized = 1;
}
static inline void sony_cancel_work_sync(struct sony_sc *sc)
{
unsigned long flags;
if (sc->state_worker_initialized) {
spin_lock_irqsave(&sc->lock, flags);
sc->state_worker_initialized = 0;
spin_unlock_irqrestore(&sc->lock, flags);
cancel_work_sync(&sc->state_worker);
}
}
static int sony_input_configured(struct hid_device *hdev,
struct hid_input *hidinput)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
int append_dev_id;
int ret;
ret = sony_set_device_id(sc);
if (ret < 0) {
hid_err(hdev, "failed to allocate the device id\n");
goto err_stop;
}
ret = append_dev_id = sony_check_add(sc);
if (ret < 0)
goto err_stop;
ret = sony_allocate_output_report(sc);
if (ret < 0) {
hid_err(hdev, "failed to allocate the output report buffer\n");
goto err_stop;
}
if (sc->quirks & NAVIGATION_CONTROLLER_USB) {
/*
* The Sony Sixaxis does not handle HID Output Reports on the
* Interrupt EP like it could, so we need to force HID Output
* Reports to use HID_REQ_SET_REPORT on the Control EP.
*
* There is also another issue about HID Output Reports via USB,
* the Sixaxis does not want the report_id as part of the data
* packet, so we have to discard buf[0] when sending the actual
* control message, even for numbered reports, humpf!
*
* Additionally, the Sixaxis on USB isn't properly initialized
* until the PS logo button is pressed and as such won't retain
* any state set by an output report, so the initial
* configuration report is deferred until the first input
* report arrives.
*/
hdev->quirks |= HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP;
hdev->quirks |= HID_QUIRK_SKIP_OUTPUT_REPORT_ID;
sc->defer_initialization = 1;
ret = sixaxis_set_operational_usb(hdev);
if (ret < 0) {
hid_err(hdev, "Failed to set controller into operational mode\n");
goto err_stop;
}
sony_init_output_report(sc, sixaxis_send_output_report);
} else if (sc->quirks & NAVIGATION_CONTROLLER_BT) {
/*
* The Navigation controller wants output reports sent on the ctrl
* endpoint when connected via Bluetooth.
*/
hdev->quirks |= HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP;
ret = sixaxis_set_operational_bt(hdev);
if (ret < 0) {
hid_err(hdev, "Failed to set controller into operational mode\n");
goto err_stop;
}
sony_init_output_report(sc, sixaxis_send_output_report);
} else if (sc->quirks & SIXAXIS_CONTROLLER_USB) {
/*
* The Sony Sixaxis does not handle HID Output Reports on the
* Interrupt EP and the device only becomes active when the
* PS button is pressed. See comment for Navigation controller
* above for more details.
*/
hdev->quirks |= HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP;
hdev->quirks |= HID_QUIRK_SKIP_OUTPUT_REPORT_ID;
sc->defer_initialization = 1;
ret = sixaxis_set_operational_usb(hdev);
if (ret < 0) {
hid_err(hdev, "Failed to set controller into operational mode\n");
goto err_stop;
}
ret = sony_register_sensors(sc);
if (ret) {
hid_err(sc->hdev,
"Unable to initialize motion sensors: %d\n", ret);
goto err_stop;
}
sony_init_output_report(sc, sixaxis_send_output_report);
} else if (sc->quirks & SIXAXIS_CONTROLLER_BT) {
/*
* The Sixaxis wants output reports sent on the ctrl endpoint
* when connected via Bluetooth.
*/
hdev->quirks |= HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP;
ret = sixaxis_set_operational_bt(hdev);
if (ret < 0) {
hid_err(hdev, "Failed to set controller into operational mode\n");
goto err_stop;
}
ret = sony_register_sensors(sc);
if (ret) {
hid_err(sc->hdev,
"Unable to initialize motion sensors: %d\n", ret);
goto err_stop;
}
sony_init_output_report(sc, sixaxis_send_output_report);
} else if (sc->quirks & NSG_MRXU_REMOTE) {
/*
* The NSG-MRxU touchpad supports 2 touches and has a
* resolution of 1667x1868
*/
ret = sony_register_touchpad(sc, 2,
NSG_MRXU_MAX_X, NSG_MRXU_MAX_Y, 15, 15, 1);
if (ret) {
hid_err(sc->hdev,
"Unable to initialize multi-touch slots: %d\n",
ret);
goto err_stop;
}
} else if (sc->quirks & MOTION_CONTROLLER) {
sony_init_output_report(sc, motion_send_output_report);
}
if (sc->quirks & SONY_LED_SUPPORT) {
ret = sony_leds_init(sc);
if (ret < 0)
goto err_stop;
}
if (sc->quirks & SONY_BATTERY_SUPPORT) {
ret = sony_battery_probe(sc, append_dev_id);
if (ret < 0)
goto err_stop;
/* Open the device to receive reports with battery info */
ret = hid_hw_open(hdev);
if (ret < 0) {
hid_err(hdev, "hw open failed\n");
goto err_stop;
}
}
if (sc->quirks & SONY_FF_SUPPORT) {
ret = sony_init_ff(sc);
if (ret < 0)
goto err_close;
}
return 0;
err_close:
hid_hw_close(hdev);
err_stop:
sony_cancel_work_sync(sc);
sony_remove_dev_list(sc);
sony_release_device_id(sc);
return ret;
}
static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id)
{
int ret;
unsigned long quirks = id->driver_data;
struct sony_sc *sc;
struct usb_device *usbdev;
unsigned int connect_mask = HID_CONNECT_DEFAULT;
if (!strcmp(hdev->name, "FutureMax Dance Mat"))
quirks |= FUTUREMAX_DANCE_MAT;
if (!strcmp(hdev->name, "SHANWAN PS3 GamePad") ||
!strcmp(hdev->name, "ShanWan PS(R) Ga`epad"))
quirks |= SHANWAN_GAMEPAD;
sc = devm_kzalloc(&hdev->dev, sizeof(*sc), GFP_KERNEL);
if (sc == NULL) {
hid_err(hdev, "can't alloc sony descriptor\n");
return -ENOMEM;
}
spin_lock_init(&sc->lock);
sc->quirks = quirks;
hid_set_drvdata(hdev, sc);
sc->hdev = hdev;
ret = hid_parse(hdev);
if (ret) {
hid_err(hdev, "parse failed\n");
return ret;
}
if (sc->quirks & VAIO_RDESC_CONSTANT)
connect_mask |= HID_CONNECT_HIDDEV_FORCE;
else if (sc->quirks & SIXAXIS_CONTROLLER)
connect_mask |= HID_CONNECT_HIDDEV_FORCE;
/* Patch the hw version on DS3 compatible devices, so applications can
* distinguish between the default HID mappings and the mappings defined
* by the Linux game controller spec. This is important for the SDL2
* library, which has a game controller database, which uses device ids
* in combination with version as a key.
*/
if (sc->quirks & SIXAXIS_CONTROLLER)
hdev->version |= 0x8000;
ret = hid_hw_start(hdev, connect_mask);
if (ret) {
hid_err(hdev, "hw start failed\n");
return ret;
}
/* sony_input_configured can fail, but this doesn't result
* in hid_hw_start failures (intended). Check whether
* the HID layer claimed the device else fail.
* We don't know the actual reason for the failure, most
* likely it is due to EEXIST in case of double connection
* of USB and Bluetooth, but could have been due to ENOMEM
* or other reasons as well.
*/
if (!(hdev->claimed & HID_CLAIMED_INPUT)) {
hid_err(hdev, "failed to claim input\n");
ret = -ENODEV;
goto err;
}
if (sc->quirks & (GHL_GUITAR_PS3WIIU | GHL_GUITAR_PS4)) {
if (!hid_is_usb(hdev)) {
ret = -EINVAL;
goto err;
}
usbdev = to_usb_device(sc->hdev->dev.parent->parent);
sc->ghl_urb = usb_alloc_urb(0, GFP_ATOMIC);
if (!sc->ghl_urb) {
ret = -ENOMEM;
goto err;
}
if (sc->quirks & GHL_GUITAR_PS3WIIU)
ret = ghl_init_urb(sc, usbdev, ghl_ps3wiiu_magic_data,
ARRAY_SIZE(ghl_ps3wiiu_magic_data));
else if (sc->quirks & GHL_GUITAR_PS4)
ret = ghl_init_urb(sc, usbdev, ghl_ps4_magic_data,
ARRAY_SIZE(ghl_ps4_magic_data));
if (ret) {
hid_err(hdev, "error preparing URB\n");
goto err;
}
timer_setup(&sc->ghl_poke_timer, ghl_magic_poke, 0);
mod_timer(&sc->ghl_poke_timer,
jiffies + GHL_GUITAR_POKE_INTERVAL*HZ);
}
return ret;
err:
usb_free_urb(sc->ghl_urb);
hid_hw_stop(hdev);
return ret;
}
static void sony_remove(struct hid_device *hdev)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
if (sc->quirks & (GHL_GUITAR_PS3WIIU | GHL_GUITAR_PS4)) {
del_timer_sync(&sc->ghl_poke_timer);
usb_free_urb(sc->ghl_urb);
}
hid_hw_close(hdev);
sony_cancel_work_sync(sc);
sony_remove_dev_list(sc);
sony_release_device_id(sc);
hid_hw_stop(hdev);
}
#ifdef CONFIG_PM
static int sony_suspend(struct hid_device *hdev, pm_message_t message)
{
#ifdef CONFIG_SONY_FF
/* On suspend stop any running force-feedback events */
if (SONY_FF_SUPPORT) {
struct sony_sc *sc = hid_get_drvdata(hdev);
sc->left = sc->right = 0;
sony_send_output_report(sc);
}
#endif
return 0;
}
static int sony_resume(struct hid_device *hdev)
{
struct sony_sc *sc = hid_get_drvdata(hdev);
/*
* The Sixaxis and navigation controllers on USB need to be
* reinitialized on resume or they won't behave properly.
*/
if ((sc->quirks & SIXAXIS_CONTROLLER_USB) ||
(sc->quirks & NAVIGATION_CONTROLLER_USB)) {
sixaxis_set_operational_usb(sc->hdev);
sc->defer_initialization = 1;
}
return 0;
}
#endif
static const struct hid_device_id sony_devices[] = {
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER),
.driver_data = SIXAXIS_CONTROLLER_USB },
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_NAVIGATION_CONTROLLER),
.driver_data = NAVIGATION_CONTROLLER_USB },
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_NAVIGATION_CONTROLLER),
.driver_data = NAVIGATION_CONTROLLER_BT },
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_MOTION_CONTROLLER),
.driver_data = MOTION_CONTROLLER_USB },
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_MOTION_CONTROLLER),
.driver_data = MOTION_CONTROLLER_BT },
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER),
.driver_data = SIXAXIS_CONTROLLER_BT },
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE),
.driver_data = VAIO_RDESC_CONSTANT },
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE),
.driver_data = VAIO_RDESC_CONSTANT },
/*
* Wired Buzz Controller. Reported as Sony Hub from its USB ID and as
* Logitech joystick from the device descriptor.
*/
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_BUZZ_CONTROLLER),
.driver_data = BUZZ_CONTROLLER },
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER),
.driver_data = BUZZ_CONTROLLER },
/* PS3 BD Remote Control */
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_BDREMOTE),
.driver_data = PS3REMOTE },
/* Logitech Harmony Adapter for PS3 */
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_PS3),
.driver_data = PS3REMOTE },
/* SMK-Link PS3 BD Remote Control */
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SMK_PS3_BDREMOTE),
.driver_data = PS3REMOTE },
/* Nyko Core Controller for PS3 */
{ HID_USB_DEVICE(USB_VENDOR_ID_SINO_LITE, USB_DEVICE_ID_SINO_LITE_CONTROLLER),
.driver_data = SIXAXIS_CONTROLLER_USB | SINO_LITE_CONTROLLER },
/* SMK-Link NSG-MR5U Remote Control */
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SMK_NSG_MR5U_REMOTE),
.driver_data = NSG_MR5U_REMOTE_BT },
/* SMK-Link NSG-MR7U Remote Control */
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SMK_NSG_MR7U_REMOTE),
.driver_data = NSG_MR7U_REMOTE_BT },
/* Guitar Hero Live PS3 and Wii U guitar dongles */
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY_RHYTHM, USB_DEVICE_ID_SONY_PS3WIIU_GHLIVE_DONGLE),
.driver_data = GHL_GUITAR_PS3WIIU | GH_GUITAR_CONTROLLER },
/* Guitar Hero PC Guitar Dongle */
{ HID_USB_DEVICE(USB_VENDOR_ID_REDOCTANE, USB_DEVICE_ID_REDOCTANE_GUITAR_DONGLE),
.driver_data = GH_GUITAR_CONTROLLER },
/* Guitar Hero PS3 World Tour Guitar Dongle */
{ HID_USB_DEVICE(USB_VENDOR_ID_SONY_RHYTHM, USB_DEVICE_ID_SONY_PS3_GUITAR_DONGLE),
.driver_data = GH_GUITAR_CONTROLLER },
/* Guitar Hero Live PS4 guitar dongles */
{ HID_USB_DEVICE(USB_VENDOR_ID_REDOCTANE, USB_DEVICE_ID_REDOCTANE_PS4_GHLIVE_DONGLE),
.driver_data = GHL_GUITAR_PS4 | GH_GUITAR_CONTROLLER },
{ }
};
MODULE_DEVICE_TABLE(hid, sony_devices);
static struct hid_driver sony_driver = {
.name = "sony",
.id_table = sony_devices,
.input_mapping = sony_mapping,
.input_configured = sony_input_configured,
.probe = sony_probe,
.remove = sony_remove,
.report_fixup = sony_report_fixup,
.raw_event = sony_raw_event,
#ifdef CONFIG_PM
.suspend = sony_suspend,
.resume = sony_resume,
.reset_resume = sony_resume,
#endif
};
static int __init sony_init(void)
{
dbg_hid("Sony:%s\n", __func__);
return hid_register_driver(&sony_driver);
}
static void __exit sony_exit(void)
{
dbg_hid("Sony:%s\n", __func__);
hid_unregister_driver(&sony_driver);
ida_destroy(&sony_device_id_allocator);
}
module_init(sony_init);
module_exit(sony_exit);
MODULE_DESCRIPTION("HID driver for Sony / PS2 / PS3 / PS4 BD devices");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* Atlantic Network Driver
*
* Copyright (C) 2014-2019 aQuantia Corporation
* Copyright (C) 2019-2020 Marvell International Ltd.
*/
/* File aq_nic.h: Declaration of common code for NIC. */
#ifndef AQ_NIC_H
#define AQ_NIC_H
#include <linux/ethtool.h>
#include <net/xdp.h>
#include <linux/bpf.h>
#include "aq_common.h"
#include "aq_rss.h"
#include "aq_hw.h"
struct aq_ring_s;
struct aq_hw_ops;
struct aq_fw_s;
struct aq_vec_s;
struct aq_macsec_cfg;
struct aq_ptp_s;
enum aq_rx_filter_type;
enum aq_fc_mode {
AQ_NIC_FC_OFF = 0,
AQ_NIC_FC_TX,
AQ_NIC_FC_RX,
AQ_NIC_FC_FULL,
};
struct aq_fc_info {
enum aq_fc_mode req;
enum aq_fc_mode cur;
};
struct aq_nic_cfg_s {
const struct aq_hw_caps_s *aq_hw_caps;
u64 features;
u32 rxds; /* rx ring size, descriptors # */
u32 txds; /* tx ring size, descriptors # */
u32 vecs; /* allocated rx/tx vectors */
u32 link_irq_vec;
u32 irq_type;
u32 itr;
u16 rx_itr;
u16 tx_itr;
u32 rxpageorder;
u32 num_rss_queues;
u32 mtu;
struct aq_fc_info fc;
u32 link_speed_msk;
u32 wol;
u8 is_vlan_rx_strip;
u8 is_vlan_tx_insert;
bool is_vlan_force_promisc;
u16 is_mc_list_enabled;
u16 mc_list_count;
bool is_autoneg;
bool is_polling;
bool is_rss;
bool is_lro;
bool is_qos;
bool is_ptp;
bool is_media_detect;
int downshift_counter;
enum aq_tc_mode tc_mode;
u32 priv_flags;
u8 tcs;
u8 prio_tc_map[8];
u32 tc_max_rate[AQ_CFG_TCS_MAX];
unsigned long tc_min_rate_msk;
u32 tc_min_rate[AQ_CFG_TCS_MAX];
struct aq_rss_parameters aq_rss;
u32 eee_speeds;
};
#define AQ_NIC_FLAG_STARTED 0x00000004U
#define AQ_NIC_FLAG_STOPPING 0x00000008U
#define AQ_NIC_FLAG_RESETTING 0x00000010U
#define AQ_NIC_FLAG_CLOSING 0x00000020U
#define AQ_NIC_PTP_DPATH_UP 0x02000000U
#define AQ_NIC_LINK_DOWN 0x04000000U
#define AQ_NIC_FLAG_ERR_UNPLUG 0x40000000U
#define AQ_NIC_FLAG_ERR_HW 0x80000000U
#define AQ_NIC_QUIRK_BAD_PTP BIT(0)
#define AQ_NIC_WOL_MODES (WAKE_MAGIC |\
WAKE_PHY)
#define AQ_NIC_CFG_RING_PER_TC(_NIC_CFG_) \
(((_NIC_CFG_)->tc_mode == AQ_TC_MODE_4TCS) ? 8 : 4)
#define AQ_NIC_CFG_TCVEC2RING(_NIC_CFG_, _TC_, _VEC_) \
((_TC_) * AQ_NIC_CFG_RING_PER_TC(_NIC_CFG_) + (_VEC_))
#define AQ_NIC_RING2QMAP(_NIC_, _ID_) \
((_ID_) / AQ_NIC_CFG_RING_PER_TC(&(_NIC_)->aq_nic_cfg) * \
(_NIC_)->aq_vecs + \
((_ID_) % AQ_NIC_CFG_RING_PER_TC(&(_NIC_)->aq_nic_cfg)))
struct aq_hw_rx_fl2 {
struct aq_rx_filter_vlan aq_vlans[AQ_VLAN_MAX_FILTERS];
};
struct aq_hw_rx_fl3l4 {
u8 active_ipv4;
u8 active_ipv6:2;
u8 is_ipv6;
u8 reserved_count;
};
struct aq_hw_rx_fltrs_s {
struct hlist_head filter_list;
u16 active_filters;
struct aq_hw_rx_fl2 fl2;
struct aq_hw_rx_fl3l4 fl3l4;
/* filter ether type */
u8 fet_reserved_count;
};
struct aq_nic_s {
atomic_t flags;
u32 msg_enable;
struct aq_vec_s *aq_vec[AQ_CFG_VECS_MAX];
struct aq_ring_s *aq_ring_tx[AQ_HW_QUEUES_MAX];
struct aq_hw_s *aq_hw;
struct bpf_prog *xdp_prog;
struct net_device *ndev;
unsigned int aq_vecs;
unsigned int packet_filter;
unsigned int power_state;
u8 port;
const struct aq_hw_ops *aq_hw_ops;
const struct aq_fw_ops *aq_fw_ops;
struct aq_nic_cfg_s aq_nic_cfg;
struct timer_list service_timer;
struct work_struct service_task;
struct timer_list polling_timer;
struct aq_hw_link_status_s link_status;
struct {
u32 count;
u8 ar[AQ_HW_MULTICAST_ADDRESS_MAX][ETH_ALEN];
} mc_list;
/* Bitmask of currently assigned vlans from linux */
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
struct pci_dev *pdev;
unsigned int msix_entry_mask;
u32 irqvecs;
/* mutex to serialize FW interface access operations */
struct mutex fwreq_mutex;
#if IS_ENABLED(CONFIG_MACSEC)
struct aq_macsec_cfg *macsec_cfg;
/* mutex to protect data in macsec_cfg */
struct mutex macsec_mutex;
#endif
/* PTP support */
struct aq_ptp_s *aq_ptp;
struct aq_hw_rx_fltrs_s aq_hw_rx_fltrs;
};
static inline struct device *aq_nic_get_dev(struct aq_nic_s *self)
{
return self->ndev->dev.parent;
}
void aq_nic_ndev_init(struct aq_nic_s *self);
struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
struct aq_ring_s *ring);
struct net_device *aq_nic_get_ndev(struct aq_nic_s *self);
int aq_nic_init(struct aq_nic_s *self);
void aq_nic_cfg_start(struct aq_nic_s *self);
int aq_nic_ndev_register(struct aq_nic_s *self);
void aq_nic_ndev_free(struct aq_nic_s *self);
int aq_nic_start(struct aq_nic_s *self);
unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb,
struct aq_ring_s *ring);
int aq_nic_xmit_xdpf(struct aq_nic_s *aq_nic, struct aq_ring_s *tx_ring,
struct xdp_frame *xdpf);
int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb);
int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p);
int aq_nic_get_regs_count(struct aq_nic_s *self);
u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data);
int aq_nic_stop(struct aq_nic_s *self);
void aq_nic_deinit(struct aq_nic_s *self, bool link_down);
void aq_nic_set_power(struct aq_nic_s *self);
void aq_nic_free_hot_resources(struct aq_nic_s *self);
void aq_nic_free_vectors(struct aq_nic_s *self);
int aq_nic_realloc_vectors(struct aq_nic_s *self);
int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu);
int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev);
int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags);
int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev);
unsigned int aq_nic_get_link_speed(struct aq_nic_s *self);
void aq_nic_get_link_ksettings(struct aq_nic_s *self,
struct ethtool_link_ksettings *cmd);
int aq_nic_set_link_ksettings(struct aq_nic_s *self,
const struct ethtool_link_ksettings *cmd);
struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self);
u32 aq_nic_get_fw_version(struct aq_nic_s *self);
int aq_nic_set_loopback(struct aq_nic_s *self);
int aq_nic_set_downshift(struct aq_nic_s *self, int val);
int aq_nic_set_media_detect(struct aq_nic_s *self, int val);
int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self);
void aq_nic_shutdown(struct aq_nic_s *self);
u8 aq_nic_reserve_filter(struct aq_nic_s *self, enum aq_rx_filter_type type);
void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type,
u32 location);
int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map);
int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc,
const u32 max_rate);
int aq_nic_setup_tc_min_rate(struct aq_nic_s *self, const unsigned int tc,
const u32 min_rate);
#endif /* AQ_NIC_H */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2008 Intel Corporation
* Author: Matthew Wilcox <[email protected]>
*
* This file implements counting semaphores.
* A counting semaphore may be acquired 'n' times before sleeping.
* See mutex.c for single-acquisition sleeping locks which enforce
* rules which allow code to be debugged more easily.
*/
/*
* Some notes on the implementation:
*
* The spinlock controls access to the other members of the semaphore.
* down_trylock() and up() can be called from interrupt context, so we
* have to disable interrupts when taking the lock. It turns out various
* parts of the kernel expect to be able to use down() on a semaphore in
* interrupt context when they know it will succeed, so we have to use
* irqsave variants for down(), down_interruptible() and down_killable()
* too.
*
* The ->count variable represents how many more tasks can acquire this
* semaphore. If it's zero, there may be tasks waiting on the wait_list.
*/
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/semaphore.h>
#include <linux/spinlock.h>
#include <linux/ftrace.h>
#include <trace/events/lock.h>
static noinline void __down(struct semaphore *sem);
static noinline int __down_interruptible(struct semaphore *sem);
static noinline int __down_killable(struct semaphore *sem);
static noinline int __down_timeout(struct semaphore *sem, long timeout);
static noinline void __up(struct semaphore *sem);
/**
* down - acquire the semaphore
* @sem: the semaphore to be acquired
*
* Acquires the semaphore. If no more tasks are allowed to acquire the
* semaphore, calling this function will put the task to sleep until the
* semaphore is released.
*
* Use of this function is deprecated, please use down_interruptible() or
* down_killable() instead.
*/
void __sched down(struct semaphore *sem)
{
unsigned long flags;
might_sleep();
raw_spin_lock_irqsave(&sem->lock, flags);
if (likely(sem->count > 0))
sem->count--;
else
__down(sem);
raw_spin_unlock_irqrestore(&sem->lock, flags);
}
EXPORT_SYMBOL(down);
/**
* down_interruptible - acquire the semaphore unless interrupted
* @sem: the semaphore to be acquired
*
* Attempts to acquire the semaphore. If no more tasks are allowed to
* acquire the semaphore, calling this function will put the task to sleep.
* If the sleep is interrupted by a signal, this function will return -EINTR.
* If the semaphore is successfully acquired, this function returns 0.
*/
int __sched down_interruptible(struct semaphore *sem)
{
unsigned long flags;
int result = 0;
might_sleep();
raw_spin_lock_irqsave(&sem->lock, flags);
if (likely(sem->count > 0))
sem->count--;
else
result = __down_interruptible(sem);
raw_spin_unlock_irqrestore(&sem->lock, flags);
return result;
}
EXPORT_SYMBOL(down_interruptible);
/**
* down_killable - acquire the semaphore unless killed
* @sem: the semaphore to be acquired
*
* Attempts to acquire the semaphore. If no more tasks are allowed to
* acquire the semaphore, calling this function will put the task to sleep.
* If the sleep is interrupted by a fatal signal, this function will return
* -EINTR. If the semaphore is successfully acquired, this function returns
* 0.
*/
int __sched down_killable(struct semaphore *sem)
{
unsigned long flags;
int result = 0;
might_sleep();
raw_spin_lock_irqsave(&sem->lock, flags);
if (likely(sem->count > 0))
sem->count--;
else
result = __down_killable(sem);
raw_spin_unlock_irqrestore(&sem->lock, flags);
return result;
}
EXPORT_SYMBOL(down_killable);
/**
* down_trylock - try to acquire the semaphore, without waiting
* @sem: the semaphore to be acquired
*
* Try to acquire the semaphore atomically. Returns 0 if the semaphore has
* been acquired successfully or 1 if it cannot be acquired.
*
* NOTE: This return value is inverted from both spin_trylock and
* mutex_trylock! Be careful about this when converting code.
*
* Unlike mutex_trylock, this function can be used from interrupt context,
* and the semaphore can be released by any task or interrupt.
*/
int __sched down_trylock(struct semaphore *sem)
{
unsigned long flags;
int count;
raw_spin_lock_irqsave(&sem->lock, flags);
count = sem->count - 1;
if (likely(count >= 0))
sem->count = count;
raw_spin_unlock_irqrestore(&sem->lock, flags);
return (count < 0);
}
EXPORT_SYMBOL(down_trylock);
/**
* down_timeout - acquire the semaphore within a specified time
* @sem: the semaphore to be acquired
* @timeout: how long to wait before failing
*
* Attempts to acquire the semaphore. If no more tasks are allowed to
* acquire the semaphore, calling this function will put the task to sleep.
* If the semaphore is not released within the specified number of jiffies,
* this function returns -ETIME. It returns 0 if the semaphore was acquired.
*/
int __sched down_timeout(struct semaphore *sem, long timeout)
{
unsigned long flags;
int result = 0;
might_sleep();
raw_spin_lock_irqsave(&sem->lock, flags);
if (likely(sem->count > 0))
sem->count--;
else
result = __down_timeout(sem, timeout);
raw_spin_unlock_irqrestore(&sem->lock, flags);
return result;
}
EXPORT_SYMBOL(down_timeout);
/**
* up - release the semaphore
* @sem: the semaphore to release
*
* Release the semaphore. Unlike mutexes, up() may be called from any
* context and even by tasks which have never called down().
*/
void __sched up(struct semaphore *sem)
{
unsigned long flags;
raw_spin_lock_irqsave(&sem->lock, flags);
if (likely(list_empty(&sem->wait_list)))
sem->count++;
else
__up(sem);
raw_spin_unlock_irqrestore(&sem->lock, flags);
}
EXPORT_SYMBOL(up);
/* Functions for the contended case */
struct semaphore_waiter {
struct list_head list;
struct task_struct *task;
bool up;
};
/*
* Because this function is inlined, the 'state' parameter will be
* constant, and thus optimised away by the compiler. Likewise the
* 'timeout' parameter for the cases without timeouts.
*/
static inline int __sched ___down_common(struct semaphore *sem, long state,
long timeout)
{
struct semaphore_waiter waiter;
list_add_tail(&waiter.list, &sem->wait_list);
waiter.task = current;
waiter.up = false;
for (;;) {
if (signal_pending_state(state, current))
goto interrupted;
if (unlikely(timeout <= 0))
goto timed_out;
__set_current_state(state);
raw_spin_unlock_irq(&sem->lock);
timeout = schedule_timeout(timeout);
raw_spin_lock_irq(&sem->lock);
if (waiter.up)
return 0;
}
timed_out:
list_del(&waiter.list);
return -ETIME;
interrupted:
list_del(&waiter.list);
return -EINTR;
}
static inline int __sched __down_common(struct semaphore *sem, long state,
long timeout)
{
int ret;
trace_contention_begin(sem, 0);
ret = ___down_common(sem, state, timeout);
trace_contention_end(sem, ret);
return ret;
}
static noinline void __sched __down(struct semaphore *sem)
{
__down_common(sem, TASK_UNINTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT);
}
static noinline int __sched __down_interruptible(struct semaphore *sem)
{
return __down_common(sem, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT);
}
static noinline int __sched __down_killable(struct semaphore *sem)
{
return __down_common(sem, TASK_KILLABLE, MAX_SCHEDULE_TIMEOUT);
}
static noinline int __sched __down_timeout(struct semaphore *sem, long timeout)
{
return __down_common(sem, TASK_UNINTERRUPTIBLE, timeout);
}
static noinline void __sched __up(struct semaphore *sem)
{
struct semaphore_waiter *waiter = list_first_entry(&sem->wait_list,
struct semaphore_waiter, list);
list_del(&waiter->list);
waiter->up = true;
wake_up_process(waiter->task);
}
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
I2C functions
Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
Copyright (C) 2005-2007 Hans Verkuil <[email protected]>
*/
/*
This file includes an i2c implementation that was reverse engineered
from the Hauppauge windows driver. Older ivtv versions used i2c-algo-bit,
which whilst fine under most circumstances, had trouble with the Zilog
CPU on the PVR-150 which handles IR functions (occasional inability to
communicate with the chip until it was reset) and also with the i2c
bus being completely unreachable when multiple PVR cards were present.
The implementation is very similar to i2c-algo-bit, but there are enough
subtle differences that the two are hard to merge. The general strategy
employed by i2c-algo-bit is to use udelay() to implement the timing
when putting out bits on the scl/sda lines. The general strategy taken
here is to poll the lines for state changes (see ivtv_waitscl and
ivtv_waitsda). In addition there are small delays at various locations
which poll the SCL line 5 times (ivtv_scldelay). I would guess that
since this is memory mapped I/O that the length of those delays is tied
to the PCI bus clock. There is some extra code to do with recovery
and retries. Since it is not known what causes the actual i2c problems
in the first place, the only goal if one was to attempt to use
i2c-algo-bit would be to try to make it follow the same code path.
This would be a lot of work, and I'm also not convinced that it would
provide a generic benefit to i2c-algo-bit. Therefore consider this
an engineering solution -- not pretty, but it works.
Some more general comments about what we are doing:
The i2c bus is a 2 wire serial bus, with clock (SCL) and data (SDA)
lines. To communicate on the bus (as a master, we don't act as a slave),
we first initiate a start condition (ivtv_start). We then write the
address of the device that we want to communicate with, along with a flag
that indicates whether this is a read or a write. The slave then issues
an ACK signal (ivtv_ack), which tells us that it is ready for reading /
writing. We then proceed with reading or writing (ivtv_read/ivtv_write),
and finally issue a stop condition (ivtv_stop) to make the bus available
to other masters.
There is an additional form of transaction where a write may be
immediately followed by a read. In this case, there is no intervening
stop condition. (Only the msp3400 chip uses this method of data transfer).
*/
#include "ivtv-driver.h"
#include "ivtv-cards.h"
#include "ivtv-gpio.h"
#include "ivtv-i2c.h"
#include <media/drv-intf/cx25840.h>
/* i2c implementation for cx23415/6 chip, ivtv project.
* Author: Kevin Thayer (nufan_wfk at yahoo.com)
*/
/* i2c stuff */
#define IVTV_REG_I2C_SETSCL_OFFSET 0x7000
#define IVTV_REG_I2C_SETSDA_OFFSET 0x7004
#define IVTV_REG_I2C_GETSCL_OFFSET 0x7008
#define IVTV_REG_I2C_GETSDA_OFFSET 0x700c
#define IVTV_CS53L32A_I2C_ADDR 0x11
#define IVTV_M52790_I2C_ADDR 0x48
#define IVTV_CX25840_I2C_ADDR 0x44
#define IVTV_SAA7115_I2C_ADDR 0x21
#define IVTV_SAA7127_I2C_ADDR 0x44
#define IVTV_SAA717x_I2C_ADDR 0x21
#define IVTV_MSP3400_I2C_ADDR 0x40
#define IVTV_HAUPPAUGE_I2C_ADDR 0x50
#define IVTV_WM8739_I2C_ADDR 0x1a
#define IVTV_WM8775_I2C_ADDR 0x1b
#define IVTV_TEA5767_I2C_ADDR 0x60
#define IVTV_UPD64031A_I2C_ADDR 0x12
#define IVTV_UPD64083_I2C_ADDR 0x5c
#define IVTV_VP27SMPX_I2C_ADDR 0x5b
#define IVTV_M52790_I2C_ADDR 0x48
#define IVTV_AVERMEDIA_IR_RX_I2C_ADDR 0x40
#define IVTV_HAUP_EXT_IR_RX_I2C_ADDR 0x1a
#define IVTV_HAUP_INT_IR_RX_I2C_ADDR 0x18
#define IVTV_Z8F0811_IR_TX_I2C_ADDR 0x70
#define IVTV_Z8F0811_IR_RX_I2C_ADDR 0x71
#define IVTV_ADAPTEC_IR_ADDR 0x6b
/* This array should match the IVTV_HW_ defines */
static const u8 hw_addrs[IVTV_HW_MAX_BITS] = {
IVTV_CX25840_I2C_ADDR,
IVTV_SAA7115_I2C_ADDR,
IVTV_SAA7127_I2C_ADDR,
IVTV_MSP3400_I2C_ADDR,
0,
IVTV_WM8775_I2C_ADDR,
IVTV_CS53L32A_I2C_ADDR,
0,
IVTV_SAA7115_I2C_ADDR,
IVTV_UPD64031A_I2C_ADDR,
IVTV_UPD64083_I2C_ADDR,
IVTV_SAA717x_I2C_ADDR,
IVTV_WM8739_I2C_ADDR,
IVTV_VP27SMPX_I2C_ADDR,
IVTV_M52790_I2C_ADDR,
0, /* IVTV_HW_GPIO dummy driver ID */
IVTV_AVERMEDIA_IR_RX_I2C_ADDR, /* IVTV_HW_I2C_IR_RX_AVER */
IVTV_HAUP_EXT_IR_RX_I2C_ADDR, /* IVTV_HW_I2C_IR_RX_HAUP_EXT */
IVTV_HAUP_INT_IR_RX_I2C_ADDR, /* IVTV_HW_I2C_IR_RX_HAUP_INT */
IVTV_Z8F0811_IR_RX_I2C_ADDR, /* IVTV_HW_Z8F0811_IR_HAUP */
IVTV_ADAPTEC_IR_ADDR, /* IVTV_HW_I2C_IR_RX_ADAPTEC */
};
/* This array should match the IVTV_HW_ defines */
static const char * const hw_devicenames[IVTV_HW_MAX_BITS] = {
"cx25840",
"saa7115",
"saa7127_auto", /* saa7127 or saa7129 */
"msp3400",
"tuner",
"wm8775",
"cs53l32a",
"tveeprom",
"saa7114",
"upd64031a",
"upd64083",
"saa717x",
"wm8739",
"vp27smpx",
"m52790",
"gpio",
"ir_video", /* IVTV_HW_I2C_IR_RX_AVER */
"ir_video", /* IVTV_HW_I2C_IR_RX_HAUP_EXT */
"ir_video", /* IVTV_HW_I2C_IR_RX_HAUP_INT */
"ir_z8f0811_haup", /* IVTV_HW_Z8F0811_IR_HAUP */
"ir_video", /* IVTV_HW_I2C_IR_RX_ADAPTEC */
};
static int get_key_adaptec(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
unsigned char keybuf[4];
keybuf[0] = 0x00;
i2c_master_send(ir->c, keybuf, 1);
/* poll IR chip */
if (i2c_master_recv(ir->c, keybuf, sizeof(keybuf)) != sizeof(keybuf)) {
return 0;
}
/* key pressed ? */
if (keybuf[2] == 0xff)
return 0;
/* remove repeat bit */
keybuf[2] &= 0x7f;
keybuf[3] |= 0x80;
*protocol = RC_PROTO_UNKNOWN;
*scancode = keybuf[3] | keybuf[2] << 8 | keybuf[1] << 16 |keybuf[0] << 24;
*toggle = 0;
return 1;
}
static int ivtv_i2c_new_ir(struct ivtv *itv, u32 hw, const char *type, u8 addr)
{
struct i2c_board_info info;
struct i2c_adapter *adap = &itv->i2c_adap;
struct IR_i2c_init_data *init_data = &itv->ir_i2c_init_data;
unsigned short addr_list[2] = { addr, I2C_CLIENT_END };
/* Only allow one IR receiver to be registered per board */
if (itv->hw_flags & IVTV_HW_IR_ANY)
return -1;
/* Our default information for ir-kbd-i2c.c to use */
switch (hw) {
case IVTV_HW_I2C_IR_RX_AVER:
init_data->ir_codes = RC_MAP_AVERMEDIA_CARDBUS;
init_data->internal_get_key_func =
IR_KBD_GET_KEY_AVERMEDIA_CARDBUS;
init_data->type = RC_PROTO_BIT_OTHER;
init_data->name = "AVerMedia AVerTV card";
break;
case IVTV_HW_I2C_IR_RX_HAUP_EXT:
case IVTV_HW_I2C_IR_RX_HAUP_INT:
init_data->ir_codes = RC_MAP_HAUPPAUGE;
init_data->internal_get_key_func = IR_KBD_GET_KEY_HAUP;
init_data->type = RC_PROTO_BIT_RC5;
init_data->name = itv->card_name;
break;
case IVTV_HW_Z8F0811_IR_HAUP:
/* Default to grey remote */
init_data->ir_codes = RC_MAP_HAUPPAUGE;
init_data->internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR;
init_data->type = RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC6_MCE |
RC_PROTO_BIT_RC6_6A_32;
init_data->name = itv->card_name;
break;
case IVTV_HW_I2C_IR_RX_ADAPTEC:
init_data->get_key = get_key_adaptec;
init_data->name = itv->card_name;
/* FIXME: The protocol and RC_MAP needs to be corrected */
init_data->ir_codes = RC_MAP_EMPTY;
init_data->type = RC_PROTO_BIT_UNKNOWN;
break;
}
memset(&info, 0, sizeof(struct i2c_board_info));
info.platform_data = init_data;
strscpy(info.type, type, I2C_NAME_SIZE);
return IS_ERR(i2c_new_scanned_device(adap, &info, addr_list, NULL)) ?
-1 : 0;
}
/* Instantiate the IR receiver device using probing -- undesirable */
void ivtv_i2c_new_ir_legacy(struct ivtv *itv)
{
struct i2c_board_info info;
/*
* The external IR receiver is at i2c address 0x34.
* The internal IR receiver is at i2c address 0x30.
*
* In theory, both can be fitted, and Hauppauge suggests an external
* overrides an internal. That's why we probe 0x1a (~0x34) first. CB
*
* Some of these addresses we probe may collide with other i2c address
* allocations, so this function must be called after all other i2c
* devices we care about are registered.
*/
static const unsigned short addr_list[] = {
0x1a, /* Hauppauge IR external - collides with WM8739 */
0x18, /* Hauppauge IR internal */
I2C_CLIENT_END
};
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "ir_video", I2C_NAME_SIZE);
i2c_new_scanned_device(&itv->i2c_adap, &info, addr_list, NULL);
}
int ivtv_i2c_register(struct ivtv *itv, unsigned idx)
{
struct i2c_adapter *adap = &itv->i2c_adap;
struct v4l2_subdev *sd;
const char *type;
u32 hw;
if (idx >= IVTV_HW_MAX_BITS)
return -ENODEV;
type = hw_devicenames[idx];
hw = 1 << idx;
if (hw == IVTV_HW_TUNER) {
/* special tuner handling */
sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, adap, type, 0,
itv->card_i2c->radio);
if (sd)
sd->grp_id = 1 << idx;
sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, adap, type, 0,
itv->card_i2c->demod);
if (sd)
sd->grp_id = 1 << idx;
sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, adap, type, 0,
itv->card_i2c->tv);
if (sd)
sd->grp_id = 1 << idx;
return sd ? 0 : -1;
}
if (hw & IVTV_HW_IR_ANY)
return ivtv_i2c_new_ir(itv, hw, type, hw_addrs[idx]);
/* Is it not an I2C device or one we do not wish to register? */
if (!hw_addrs[idx])
return -1;
/* It's an I2C device other than an analog tuner or IR chip */
if (hw == IVTV_HW_UPD64031A || hw == IVTV_HW_UPD6408X) {
sd = v4l2_i2c_new_subdev(&itv->v4l2_dev,
adap, type, 0, I2C_ADDRS(hw_addrs[idx]));
} else if (hw == IVTV_HW_CX25840) {
struct cx25840_platform_data pdata;
struct i2c_board_info cx25840_info = {
.type = "cx25840",
.addr = hw_addrs[idx],
.platform_data = &pdata,
};
memset(&pdata, 0, sizeof(pdata));
pdata.pvr150_workaround = itv->pvr150_workaround;
sd = v4l2_i2c_new_subdev_board(&itv->v4l2_dev, adap,
&cx25840_info, NULL);
} else {
sd = v4l2_i2c_new_subdev(&itv->v4l2_dev,
adap, type, hw_addrs[idx], NULL);
}
if (sd)
sd->grp_id = 1 << idx;
return sd ? 0 : -1;
}
struct v4l2_subdev *ivtv_find_hw(struct ivtv *itv, u32 hw)
{
struct v4l2_subdev *result = NULL;
struct v4l2_subdev *sd;
spin_lock(&itv->v4l2_dev.lock);
v4l2_device_for_each_subdev(sd, &itv->v4l2_dev) {
if (sd->grp_id == hw) {
result = sd;
break;
}
}
spin_unlock(&itv->v4l2_dev.lock);
return result;
}
/* Set the serial clock line to the desired state */
static void ivtv_setscl(struct ivtv *itv, int state)
{
/* write them out */
/* write bits are inverted */
write_reg(~state, IVTV_REG_I2C_SETSCL_OFFSET);
}
/* Set the serial data line to the desired state */
static void ivtv_setsda(struct ivtv *itv, int state)
{
/* write them out */
/* write bits are inverted */
write_reg(~state & 1, IVTV_REG_I2C_SETSDA_OFFSET);
}
/* Read the serial clock line */
static int ivtv_getscl(struct ivtv *itv)
{
return read_reg(IVTV_REG_I2C_GETSCL_OFFSET) & 1;
}
/* Read the serial data line */
static int ivtv_getsda(struct ivtv *itv)
{
return read_reg(IVTV_REG_I2C_GETSDA_OFFSET) & 1;
}
/* Implement a short delay by polling the serial clock line */
static void ivtv_scldelay(struct ivtv *itv)
{
int i;
for (i = 0; i < 5; ++i)
ivtv_getscl(itv);
}
/* Wait for the serial clock line to become set to a specific value */
static int ivtv_waitscl(struct ivtv *itv, int val)
{
int i;
ivtv_scldelay(itv);
for (i = 0; i < 1000; ++i) {
if (ivtv_getscl(itv) == val)
return 1;
}
return 0;
}
/* Wait for the serial data line to become set to a specific value */
static int ivtv_waitsda(struct ivtv *itv, int val)
{
int i;
ivtv_scldelay(itv);
for (i = 0; i < 1000; ++i) {
if (ivtv_getsda(itv) == val)
return 1;
}
return 0;
}
/* Wait for the slave to issue an ACK */
static int ivtv_ack(struct ivtv *itv)
{
int ret = 0;
if (ivtv_getscl(itv) == 1) {
IVTV_DEBUG_HI_I2C("SCL was high starting an ack\n");
ivtv_setscl(itv, 0);
if (!ivtv_waitscl(itv, 0)) {
IVTV_DEBUG_I2C("Could not set SCL low starting an ack\n");
return -EREMOTEIO;
}
}
ivtv_setsda(itv, 1);
ivtv_scldelay(itv);
ivtv_setscl(itv, 1);
if (!ivtv_waitsda(itv, 0)) {
IVTV_DEBUG_I2C("Slave did not ack\n");
ret = -EREMOTEIO;
}
ivtv_setscl(itv, 0);
if (!ivtv_waitscl(itv, 0)) {
IVTV_DEBUG_I2C("Failed to set SCL low after ACK\n");
ret = -EREMOTEIO;
}
return ret;
}
/* Write a single byte to the i2c bus and wait for the slave to ACK */
static int ivtv_sendbyte(struct ivtv *itv, unsigned char byte)
{
int i, bit;
IVTV_DEBUG_HI_I2C("write %x\n",byte);
for (i = 0; i < 8; ++i, byte<<=1) {
ivtv_setscl(itv, 0);
if (!ivtv_waitscl(itv, 0)) {
IVTV_DEBUG_I2C("Error setting SCL low\n");
return -EREMOTEIO;
}
bit = (byte>>7)&1;
ivtv_setsda(itv, bit);
if (!ivtv_waitsda(itv, bit)) {
IVTV_DEBUG_I2C("Error setting SDA\n");
return -EREMOTEIO;
}
ivtv_setscl(itv, 1);
if (!ivtv_waitscl(itv, 1)) {
IVTV_DEBUG_I2C("Slave not ready for bit\n");
return -EREMOTEIO;
}
}
ivtv_setscl(itv, 0);
if (!ivtv_waitscl(itv, 0)) {
IVTV_DEBUG_I2C("Error setting SCL low\n");
return -EREMOTEIO;
}
return ivtv_ack(itv);
}
/* Read a byte from the i2c bus and send a NACK if applicable (i.e. for the
final byte) */
static int ivtv_readbyte(struct ivtv *itv, unsigned char *byte, int nack)
{
int i;
*byte = 0;
ivtv_setsda(itv, 1);
ivtv_scldelay(itv);
for (i = 0; i < 8; ++i) {
ivtv_setscl(itv, 0);
ivtv_scldelay(itv);
ivtv_setscl(itv, 1);
if (!ivtv_waitscl(itv, 1)) {
IVTV_DEBUG_I2C("Error setting SCL high\n");
return -EREMOTEIO;
}
*byte = ((*byte)<<1)|ivtv_getsda(itv);
}
ivtv_setscl(itv, 0);
ivtv_scldelay(itv);
ivtv_setsda(itv, nack);
ivtv_scldelay(itv);
ivtv_setscl(itv, 1);
ivtv_scldelay(itv);
ivtv_setscl(itv, 0);
ivtv_scldelay(itv);
IVTV_DEBUG_HI_I2C("read %x\n",*byte);
return 0;
}
/* Issue a start condition on the i2c bus to alert slaves to prepare for
an address write */
static int ivtv_start(struct ivtv *itv)
{
int sda;
sda = ivtv_getsda(itv);
if (sda != 1) {
IVTV_DEBUG_HI_I2C("SDA was low at start\n");
ivtv_setsda(itv, 1);
if (!ivtv_waitsda(itv, 1)) {
IVTV_DEBUG_I2C("SDA stuck low\n");
return -EREMOTEIO;
}
}
if (ivtv_getscl(itv) != 1) {
ivtv_setscl(itv, 1);
if (!ivtv_waitscl(itv, 1)) {
IVTV_DEBUG_I2C("SCL stuck low at start\n");
return -EREMOTEIO;
}
}
ivtv_setsda(itv, 0);
ivtv_scldelay(itv);
return 0;
}
/* Issue a stop condition on the i2c bus to release it */
static int ivtv_stop(struct ivtv *itv)
{
int i;
if (ivtv_getscl(itv) != 0) {
IVTV_DEBUG_HI_I2C("SCL not low when stopping\n");
ivtv_setscl(itv, 0);
if (!ivtv_waitscl(itv, 0)) {
IVTV_DEBUG_I2C("SCL could not be set low\n");
}
}
ivtv_setsda(itv, 0);
ivtv_scldelay(itv);
ivtv_setscl(itv, 1);
if (!ivtv_waitscl(itv, 1)) {
IVTV_DEBUG_I2C("SCL could not be set high\n");
return -EREMOTEIO;
}
ivtv_scldelay(itv);
ivtv_setsda(itv, 1);
if (!ivtv_waitsda(itv, 1)) {
IVTV_DEBUG_I2C("resetting I2C\n");
for (i = 0; i < 16; ++i) {
ivtv_setscl(itv, 0);
ivtv_scldelay(itv);
ivtv_setscl(itv, 1);
ivtv_scldelay(itv);
ivtv_setsda(itv, 1);
}
ivtv_waitsda(itv, 1);
return -EREMOTEIO;
}
return 0;
}
/* Write a message to the given i2c slave. do_stop may be 0 to prevent
issuing the i2c stop condition (when following with a read) */
static int ivtv_write(struct ivtv *itv, unsigned char addr, unsigned char *data, u32 len, int do_stop)
{
int retry, ret = -EREMOTEIO;
u32 i;
for (retry = 0; ret != 0 && retry < 8; ++retry) {
ret = ivtv_start(itv);
if (ret == 0) {
ret = ivtv_sendbyte(itv, addr<<1);
for (i = 0; ret == 0 && i < len; ++i)
ret = ivtv_sendbyte(itv, data[i]);
}
if (ret != 0 || do_stop) {
ivtv_stop(itv);
}
}
if (ret)
IVTV_DEBUG_I2C("i2c write to %x failed\n", addr);
return ret;
}
/* Read data from the given i2c slave. A stop condition is always issued. */
static int ivtv_read(struct ivtv *itv, unsigned char addr, unsigned char *data, u32 len)
{
int retry, ret = -EREMOTEIO;
u32 i;
for (retry = 0; ret != 0 && retry < 8; ++retry) {
ret = ivtv_start(itv);
if (ret == 0)
ret = ivtv_sendbyte(itv, (addr << 1) | 1);
for (i = 0; ret == 0 && i < len; ++i) {
ret = ivtv_readbyte(itv, &data[i], i == len - 1);
}
ivtv_stop(itv);
}
if (ret)
IVTV_DEBUG_I2C("i2c read from %x failed\n", addr);
return ret;
}
/* Kernel i2c transfer implementation. Takes a number of messages to be read
or written. If a read follows a write, this will occur without an
intervening stop condition */
static int ivtv_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
{
struct v4l2_device *v4l2_dev = i2c_get_adapdata(i2c_adap);
struct ivtv *itv = to_ivtv(v4l2_dev);
int retval;
int i;
mutex_lock(&itv->i2c_bus_lock);
for (i = retval = 0; retval == 0 && i < num; i++) {
if (msgs[i].flags & I2C_M_RD)
retval = ivtv_read(itv, msgs[i].addr, msgs[i].buf, msgs[i].len);
else {
/* if followed by a read, don't stop */
int stop = !(i + 1 < num && msgs[i + 1].flags == I2C_M_RD);
retval = ivtv_write(itv, msgs[i].addr, msgs[i].buf, msgs[i].len, stop);
}
}
mutex_unlock(&itv->i2c_bus_lock);
return retval ? retval : num;
}
/* Kernel i2c capabilities */
static u32 ivtv_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm ivtv_algo = {
.master_xfer = ivtv_xfer,
.functionality = ivtv_functionality,
};
/* template for our-bit banger */
static const struct i2c_adapter ivtv_i2c_adap_hw_template = {
.name = "ivtv i2c driver",
.algo = &ivtv_algo,
.algo_data = NULL, /* filled from template */
.owner = THIS_MODULE,
};
static void ivtv_setscl_old(void *data, int state)
{
struct ivtv *itv = (struct ivtv *)data;
if (state)
itv->i2c_state |= 0x01;
else
itv->i2c_state &= ~0x01;
/* write them out */
/* write bits are inverted */
write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSCL_OFFSET);
}
static void ivtv_setsda_old(void *data, int state)
{
struct ivtv *itv = (struct ivtv *)data;
if (state)
itv->i2c_state |= 0x01;
else
itv->i2c_state &= ~0x01;
/* write them out */
/* write bits are inverted */
write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSDA_OFFSET);
}
static int ivtv_getscl_old(void *data)
{
struct ivtv *itv = (struct ivtv *)data;
return read_reg(IVTV_REG_I2C_GETSCL_OFFSET) & 1;
}
static int ivtv_getsda_old(void *data)
{
struct ivtv *itv = (struct ivtv *)data;
return read_reg(IVTV_REG_I2C_GETSDA_OFFSET) & 1;
}
/* template for i2c-bit-algo */
static const struct i2c_adapter ivtv_i2c_adap_template = {
.name = "ivtv i2c driver",
.algo = NULL, /* set by i2c-algo-bit */
.algo_data = NULL, /* filled from template */
.owner = THIS_MODULE,
};
#define IVTV_ALGO_BIT_TIMEOUT (2) /* seconds */
static const struct i2c_algo_bit_data ivtv_i2c_algo_template = {
.setsda = ivtv_setsda_old,
.setscl = ivtv_setscl_old,
.getsda = ivtv_getsda_old,
.getscl = ivtv_getscl_old,
.udelay = IVTV_DEFAULT_I2C_CLOCK_PERIOD / 2, /* microseconds */
.timeout = IVTV_ALGO_BIT_TIMEOUT * HZ, /* jiffies */
};
static const struct i2c_client ivtv_i2c_client_template = {
.name = "ivtv internal",
};
/* init + register i2c adapter */
int init_ivtv_i2c(struct ivtv *itv)
{
int retval;
IVTV_DEBUG_I2C("i2c init\n");
/* Sanity checks for the I2C hardware arrays. They must be the
* same size.
*/
if (ARRAY_SIZE(hw_devicenames) != ARRAY_SIZE(hw_addrs)) {
IVTV_ERR("Mismatched I2C hardware arrays\n");
return -ENODEV;
}
if (itv->options.newi2c > 0) {
itv->i2c_adap = ivtv_i2c_adap_hw_template;
} else {
itv->i2c_adap = ivtv_i2c_adap_template;
itv->i2c_algo = ivtv_i2c_algo_template;
}
itv->i2c_algo.udelay = itv->options.i2c_clock_period / 2;
itv->i2c_algo.data = itv;
itv->i2c_adap.algo_data = &itv->i2c_algo;
sprintf(itv->i2c_adap.name + strlen(itv->i2c_adap.name), " #%d",
itv->instance);
i2c_set_adapdata(&itv->i2c_adap, &itv->v4l2_dev);
itv->i2c_client = ivtv_i2c_client_template;
itv->i2c_client.adapter = &itv->i2c_adap;
itv->i2c_adap.dev.parent = &itv->pdev->dev;
IVTV_DEBUG_I2C("setting scl and sda to 1\n");
ivtv_setscl(itv, 1);
ivtv_setsda(itv, 1);
if (itv->options.newi2c > 0)
retval = i2c_add_adapter(&itv->i2c_adap);
else
retval = i2c_bit_add_bus(&itv->i2c_adap);
return retval;
}
void exit_ivtv_i2c(struct ivtv *itv)
{
IVTV_DEBUG_I2C("i2c exit\n");
i2c_del_adapter(&itv->i2c_adap);
}
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Common values and helper functions for the NHPoly1305 hash function.
*/
#ifndef _NHPOLY1305_H
#define _NHPOLY1305_H
#include <crypto/hash.h>
#include <crypto/internal/poly1305.h>
/* NH parameterization: */
/* Endianness: little */
/* Word size: 32 bits (works well on NEON, SSE2, AVX2) */
/* Stride: 2 words (optimal on ARM32 NEON; works okay on other CPUs too) */
#define NH_PAIR_STRIDE 2
#define NH_MESSAGE_UNIT (NH_PAIR_STRIDE * 2 * sizeof(u32))
/* Num passes (Toeplitz iteration count): 4, to give ε = 2^{-128} */
#define NH_NUM_PASSES 4
#define NH_HASH_BYTES (NH_NUM_PASSES * sizeof(u64))
/* Max message size: 1024 bytes (32x compression factor) */
#define NH_NUM_STRIDES 64
#define NH_MESSAGE_WORDS (NH_PAIR_STRIDE * 2 * NH_NUM_STRIDES)
#define NH_MESSAGE_BYTES (NH_MESSAGE_WORDS * sizeof(u32))
#define NH_KEY_WORDS (NH_MESSAGE_WORDS + \
NH_PAIR_STRIDE * 2 * (NH_NUM_PASSES - 1))
#define NH_KEY_BYTES (NH_KEY_WORDS * sizeof(u32))
#define NHPOLY1305_KEY_SIZE (POLY1305_BLOCK_SIZE + NH_KEY_BYTES)
struct nhpoly1305_key {
struct poly1305_core_key poly_key;
u32 nh_key[NH_KEY_WORDS];
};
struct nhpoly1305_state {
/* Running total of polynomial evaluation */
struct poly1305_state poly_state;
/* Partial block buffer */
u8 buffer[NH_MESSAGE_UNIT];
unsigned int buflen;
/*
* Number of bytes remaining until the current NH message reaches
* NH_MESSAGE_BYTES. When nonzero, 'nh_hash' holds the partial NH hash.
*/
unsigned int nh_remaining;
__le64 nh_hash[NH_NUM_PASSES];
};
typedef void (*nh_t)(const u32 *key, const u8 *message, size_t message_len,
__le64 hash[NH_NUM_PASSES]);
int crypto_nhpoly1305_setkey(struct crypto_shash *tfm,
const u8 *key, unsigned int keylen);
int crypto_nhpoly1305_init(struct shash_desc *desc);
int crypto_nhpoly1305_update(struct shash_desc *desc,
const u8 *src, unsigned int srclen);
int crypto_nhpoly1305_update_helper(struct shash_desc *desc,
const u8 *src, unsigned int srclen,
nh_t nh_fn);
int crypto_nhpoly1305_final(struct shash_desc *desc, u8 *dst);
int crypto_nhpoly1305_final_helper(struct shash_desc *desc, u8 *dst,
nh_t nh_fn);
#endif /* _NHPOLY1305_H */
|
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pm_qos.h>
#include <linux/irq.h>
#include <media/rc-core.h>
#define GPIO_IR_DEVICE_NAME "gpio_ir_recv"
struct gpio_rc_dev {
struct rc_dev *rcdev;
struct gpio_desc *gpiod;
int irq;
struct device *pmdev;
struct pm_qos_request qos;
};
static irqreturn_t gpio_ir_recv_irq(int irq, void *dev_id)
{
int val;
struct gpio_rc_dev *gpio_dev = dev_id;
struct device *pmdev = gpio_dev->pmdev;
/*
* For some cpuidle systems, not all:
* Respond to interrupt taking more latency when cpu in idle.
* Invoke asynchronous pm runtime get from interrupt context,
* this may introduce a millisecond delay to call resume callback,
* where to disable cpuilde.
*
* Two issues lead to fail to decode first frame, one is latency to
* respond to interrupt, another is delay introduced by async api.
*/
if (pmdev)
pm_runtime_get(pmdev);
val = gpiod_get_value(gpio_dev->gpiod);
if (val >= 0)
ir_raw_event_store_edge(gpio_dev->rcdev, val == 1);
if (pmdev) {
pm_runtime_mark_last_busy(pmdev);
pm_runtime_put_autosuspend(pmdev);
}
return IRQ_HANDLED;
}
static int gpio_ir_recv_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct gpio_rc_dev *gpio_dev;
struct rc_dev *rcdev;
u32 period = 0;
int rc;
if (!np)
return -ENODEV;
gpio_dev = devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL);
if (!gpio_dev)
return -ENOMEM;
gpio_dev->gpiod = devm_gpiod_get(dev, NULL, GPIOD_IN);
if (IS_ERR(gpio_dev->gpiod))
return dev_err_probe(dev, PTR_ERR(gpio_dev->gpiod),
"error getting gpio\n");
gpio_dev->irq = gpiod_to_irq(gpio_dev->gpiod);
if (gpio_dev->irq < 0)
return gpio_dev->irq;
rcdev = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
if (!rcdev)
return -ENOMEM;
rcdev->priv = gpio_dev;
rcdev->device_name = GPIO_IR_DEVICE_NAME;
rcdev->input_phys = GPIO_IR_DEVICE_NAME "/input0";
rcdev->input_id.bustype = BUS_HOST;
rcdev->input_id.vendor = 0x0001;
rcdev->input_id.product = 0x0001;
rcdev->input_id.version = 0x0100;
rcdev->dev.parent = dev;
rcdev->driver_name = KBUILD_MODNAME;
rcdev->min_timeout = 1;
rcdev->timeout = IR_DEFAULT_TIMEOUT;
rcdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
rcdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
rcdev->map_name = of_get_property(np, "linux,rc-map-name", NULL);
if (!rcdev->map_name)
rcdev->map_name = RC_MAP_EMPTY;
gpio_dev->rcdev = rcdev;
if (of_property_read_bool(np, "wakeup-source"))
device_init_wakeup(dev, true);
rc = devm_rc_register_device(dev, rcdev);
if (rc < 0) {
dev_err(dev, "failed to register rc device (%d)\n", rc);
return rc;
}
of_property_read_u32(np, "linux,autosuspend-period", &period);
if (period) {
gpio_dev->pmdev = dev;
pm_runtime_set_autosuspend_delay(dev, period);
pm_runtime_use_autosuspend(dev);
pm_runtime_set_suspended(dev);
pm_runtime_enable(dev);
}
platform_set_drvdata(pdev, gpio_dev);
return devm_request_irq(dev, gpio_dev->irq, gpio_ir_recv_irq,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
"gpio-ir-recv-irq", gpio_dev);
}
static void gpio_ir_recv_remove(struct platform_device *pdev)
{
struct gpio_rc_dev *gpio_dev = platform_get_drvdata(pdev);
struct device *pmdev = gpio_dev->pmdev;
if (pmdev) {
pm_runtime_get_sync(pmdev);
cpu_latency_qos_remove_request(&gpio_dev->qos);
pm_runtime_disable(pmdev);
pm_runtime_put_noidle(pmdev);
pm_runtime_set_suspended(pmdev);
}
}
#ifdef CONFIG_PM
static int gpio_ir_recv_suspend(struct device *dev)
{
struct gpio_rc_dev *gpio_dev = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(gpio_dev->irq);
else
disable_irq(gpio_dev->irq);
return 0;
}
static int gpio_ir_recv_resume(struct device *dev)
{
struct gpio_rc_dev *gpio_dev = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(gpio_dev->irq);
else
enable_irq(gpio_dev->irq);
return 0;
}
static int gpio_ir_recv_runtime_suspend(struct device *dev)
{
struct gpio_rc_dev *gpio_dev = dev_get_drvdata(dev);
cpu_latency_qos_remove_request(&gpio_dev->qos);
return 0;
}
static int gpio_ir_recv_runtime_resume(struct device *dev)
{
struct gpio_rc_dev *gpio_dev = dev_get_drvdata(dev);
cpu_latency_qos_add_request(&gpio_dev->qos, 0);
return 0;
}
static const struct dev_pm_ops gpio_ir_recv_pm_ops = {
.suspend = gpio_ir_recv_suspend,
.resume = gpio_ir_recv_resume,
.runtime_suspend = gpio_ir_recv_runtime_suspend,
.runtime_resume = gpio_ir_recv_runtime_resume,
};
#endif
static const struct of_device_id gpio_ir_recv_of_match[] = {
{ .compatible = "gpio-ir-receiver", },
{ },
};
MODULE_DEVICE_TABLE(of, gpio_ir_recv_of_match);
static struct platform_driver gpio_ir_recv_driver = {
.probe = gpio_ir_recv_probe,
.remove = gpio_ir_recv_remove,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = gpio_ir_recv_of_match,
#ifdef CONFIG_PM
.pm = &gpio_ir_recv_pm_ops,
#endif
},
};
module_platform_driver(gpio_ir_recv_driver);
MODULE_DESCRIPTION("GPIO IR Receiver driver");
MODULE_LICENSE("GPL v2");
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Cell Platform common data structures
*
* Copyright 2015, Daniel Axtens, IBM Corporation
*/
#ifndef CELL_H
#define CELL_H
#include <asm/pci-bridge.h>
extern struct pci_controller_ops cell_pci_controller_ops;
#endif
|
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
#include "k3-serdes.h"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
chosen {
stdout-path = &main_uart0;
};
aliases {
serial0 = &mcu_uart0;
serial1 = &main_uart1;
serial2 = &main_uart0;
serial3 = &main_uart3;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
ethernet2 = &icssg1_emac0;
};
memory@80000000 {
bootph-all;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: m4f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: regulator-0 {
/* main DC jack */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: regulator-1 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: regulator-2 {
/* output of LM5140 */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
/* TPS2051BD */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
vddb: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
vtt_supply: regulator-5 {
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
vin-supply = <&vsys_3v3>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
led-0 {
label = "am64-evm:red:heartbeat";
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
};
mdio_mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
};
mdio_mux_1: mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mdio_mux>;
mdio-parent-bus = <&cpsw3g_mdio>;
#address-cells = <1>;
#size-cells = <0>;
mdio@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
cpsw3g_phy3: ethernet-phy@3 {
reg = <3>;
};
};
};
transceiver1: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
};
transceiver2: can-phy1 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
};
icssg1_eth: icssg1-eth {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_rgmii1_pins_default>;
sram = <&oc_sram>;
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
ti,mii-g-rt = <&icssg1_mii_g_rt>;
ti,mii-rt = <&icssg1_mii_rt>;
ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
ti,pa-stats = <&icssg1_pa_stats>;
interrupt-parent = <&icssg1_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
<&main_pktdma 0xc201 15>, /* egress slice 0 */
<&main_pktdma 0xc202 15>, /* egress slice 0 */
<&main_pktdma 0xc203 15>, /* egress slice 0 */
<&main_pktdma 0xc204 15>, /* egress slice 1 */
<&main_pktdma 0xc205 15>, /* egress slice 1 */
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
icssg1_emac0: port@0 {
reg = <0>;
phy-handle = <&icssg1_phy1>;
phy-mode = "rgmii-id";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
icssg1_emac1: port@1 {
reg = <1>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
};
};
};
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
rgmii2_pins_default: rgmii2-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
main_usb0_pins_default: main-usb0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
ddr_vtt_pins_default: ddr-vtt-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
icssg1_mdio1_pins_default: icssg1-mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
>;
};
icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
>;
};
icssg1_iep0_pins_default: icssg1-iep0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
>;
};
};
&main_uart0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_i2c0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
gpio@38 {
/* TCA9554 */
compatible = "nxp,pca9554";
reg = <0x38>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "HSE_DETECT";
};
eeprom@50 {
/* AT24CM01 */
compatible = "atmel,24c1024";
reg = <0x50>;
};
};
&main_i2c1 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@22 {
bootph-all;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
"MMC1_SD_EN", "FSI_FET_SEL",
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
"CPSW_FET_SEL", "CPSW_FET2_SEL",
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
"GPIO_OLED_RESETn", "VPP_LDO_EN",
"TEST_LED1", "TP92", "TP90", "TP88",
"TP87", "TP86", "TP89", "TP91";
};
/* osd9616p0899-10 */
display@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
vbat-supply = <&vddb>;
solomon,height = <16>;
solomon,width = <96>;
solomon,com-seq;
solomon,com-invdir;
solomon,page-offset = <0>;
solomon,prechargep1 = <2>;
solomon,prechargep2 = <13>;
};
};
&main_gpio0 {
bootph-all;
};
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_gpio_intr {
status = "reserved";
};
&main_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <16>;
};
};
/* eMMC */
&sdhci0 {
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
bootph-all;
};
/* SD/MMC */
&sdhci1 {
bootph-all;
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
};
&usbss0 {
bootph-all;
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
bootph-all;
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
&cpsw3g {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
status = "okay";
};
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
status = "okay";
};
&cpsw3g_mdio {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
bootph-all;
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
status = "okay";
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J12 */
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};
&main_mcan0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver1>;
};
&main_mcan1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&transceiver2>;
};
&icssg1_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_mdio1_pins_default>;
icssg1_phy1: ethernet-phy@f {
reg = <0xf>;
tx-internal-delay-ps = <250>;
rx-internal-delay-ps = <2000>;
};
};
&gpmc0 {
ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
};
&icssg1_iep0 {
pinctrl-names = "default";
pinctrl-0 = <&icssg1_iep0_pins_default>;
};
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Red Hat, Inc.
*
* This file is released under the GPL.
*/
#include "dm-space-map-common.h"
#include "dm-transaction-manager.h"
#include "dm-btree-internal.h"
#include "dm-persistent-data-internal.h"
#include <linux/bitops.h>
#include <linux/device-mapper.h>
#define DM_MSG_PREFIX "space map common"
/*----------------------------------------------------------------*/
/*
* Index validator.
*/
#define INDEX_CSUM_XOR 160478
static void index_prepare_for_write(const struct dm_block_validator *v,
struct dm_block *b,
size_t block_size)
{
struct disk_metadata_index *mi_le = dm_block_data(b);
mi_le->blocknr = cpu_to_le64(dm_block_location(b));
mi_le->csum = cpu_to_le32(dm_bm_checksum(&mi_le->padding,
block_size - sizeof(__le32),
INDEX_CSUM_XOR));
}
static int index_check(const struct dm_block_validator *v,
struct dm_block *b,
size_t block_size)
{
struct disk_metadata_index *mi_le = dm_block_data(b);
__le32 csum_disk;
if (dm_block_location(b) != le64_to_cpu(mi_le->blocknr)) {
DMERR_LIMIT("%s failed: blocknr %llu != wanted %llu", __func__,
le64_to_cpu(mi_le->blocknr), dm_block_location(b));
return -ENOTBLK;
}
csum_disk = cpu_to_le32(dm_bm_checksum(&mi_le->padding,
block_size - sizeof(__le32),
INDEX_CSUM_XOR));
if (csum_disk != mi_le->csum) {
DMERR_LIMIT("%s failed: csum %u != wanted %u", __func__,
le32_to_cpu(csum_disk), le32_to_cpu(mi_le->csum));
return -EILSEQ;
}
return 0;
}
static const struct dm_block_validator index_validator = {
.name = "index",
.prepare_for_write = index_prepare_for_write,
.check = index_check
};
/*----------------------------------------------------------------*/
/*
* Bitmap validator
*/
#define BITMAP_CSUM_XOR 240779
static void dm_bitmap_prepare_for_write(const struct dm_block_validator *v,
struct dm_block *b,
size_t block_size)
{
struct disk_bitmap_header *disk_header = dm_block_data(b);
disk_header->blocknr = cpu_to_le64(dm_block_location(b));
disk_header->csum = cpu_to_le32(dm_bm_checksum(&disk_header->not_used,
block_size - sizeof(__le32),
BITMAP_CSUM_XOR));
}
static int dm_bitmap_check(const struct dm_block_validator *v,
struct dm_block *b,
size_t block_size)
{
struct disk_bitmap_header *disk_header = dm_block_data(b);
__le32 csum_disk;
if (dm_block_location(b) != le64_to_cpu(disk_header->blocknr)) {
DMERR_LIMIT("bitmap check failed: blocknr %llu != wanted %llu",
le64_to_cpu(disk_header->blocknr), dm_block_location(b));
return -ENOTBLK;
}
csum_disk = cpu_to_le32(dm_bm_checksum(&disk_header->not_used,
block_size - sizeof(__le32),
BITMAP_CSUM_XOR));
if (csum_disk != disk_header->csum) {
DMERR_LIMIT("bitmap check failed: csum %u != wanted %u",
le32_to_cpu(csum_disk), le32_to_cpu(disk_header->csum));
return -EILSEQ;
}
return 0;
}
static const struct dm_block_validator dm_sm_bitmap_validator = {
.name = "sm_bitmap",
.prepare_for_write = dm_bitmap_prepare_for_write,
.check = dm_bitmap_check,
};
/*----------------------------------------------------------------*/
#define ENTRIES_PER_WORD 32
#define ENTRIES_SHIFT 5
static void *dm_bitmap_data(struct dm_block *b)
{
return dm_block_data(b) + sizeof(struct disk_bitmap_header);
}
#define WORD_MASK_HIGH 0xAAAAAAAAAAAAAAAAULL
static unsigned int dm_bitmap_word_used(void *addr, unsigned int b)
{
__le64 *words_le = addr;
__le64 *w_le = words_le + (b >> ENTRIES_SHIFT);
uint64_t bits = le64_to_cpu(*w_le);
uint64_t mask = (bits + WORD_MASK_HIGH + 1) & WORD_MASK_HIGH;
return !(~bits & mask);
}
static unsigned int sm_lookup_bitmap(void *addr, unsigned int b)
{
__le64 *words_le = addr;
__le64 *w_le = words_le + (b >> ENTRIES_SHIFT);
unsigned int hi, lo;
b = (b & (ENTRIES_PER_WORD - 1)) << 1;
hi = !!test_bit_le(b, (void *) w_le);
lo = !!test_bit_le(b + 1, (void *) w_le);
return (hi << 1) | lo;
}
static void sm_set_bitmap(void *addr, unsigned int b, unsigned int val)
{
__le64 *words_le = addr;
__le64 *w_le = words_le + (b >> ENTRIES_SHIFT);
b = (b & (ENTRIES_PER_WORD - 1)) << 1;
if (val & 2)
__set_bit_le(b, (void *) w_le);
else
__clear_bit_le(b, (void *) w_le);
if (val & 1)
__set_bit_le(b + 1, (void *) w_le);
else
__clear_bit_le(b + 1, (void *) w_le);
}
static int sm_find_free(void *addr, unsigned int begin, unsigned int end,
unsigned int *result)
{
while (begin < end) {
if (!(begin & (ENTRIES_PER_WORD - 1)) &&
dm_bitmap_word_used(addr, begin)) {
begin += ENTRIES_PER_WORD;
continue;
}
if (!sm_lookup_bitmap(addr, begin)) {
*result = begin;
return 0;
}
begin++;
}
return -ENOSPC;
}
/*----------------------------------------------------------------*/
static int sm_ll_init(struct ll_disk *ll, struct dm_transaction_manager *tm)
{
memset(ll, 0, sizeof(struct ll_disk));
ll->tm = tm;
ll->bitmap_info.tm = tm;
ll->bitmap_info.levels = 1;
/*
* Because the new bitmap blocks are created via a shadow
* operation, the old entry has already had its reference count
* decremented and we don't need the btree to do any bookkeeping.
*/
ll->bitmap_info.value_type.size = sizeof(struct disk_index_entry);
ll->bitmap_info.value_type.inc = NULL;
ll->bitmap_info.value_type.dec = NULL;
ll->bitmap_info.value_type.equal = NULL;
ll->ref_count_info.tm = tm;
ll->ref_count_info.levels = 1;
ll->ref_count_info.value_type.size = sizeof(uint32_t);
ll->ref_count_info.value_type.inc = NULL;
ll->ref_count_info.value_type.dec = NULL;
ll->ref_count_info.value_type.equal = NULL;
ll->block_size = dm_bm_block_size(dm_tm_get_bm(tm));
if (ll->block_size > (1 << 30)) {
DMERR("block size too big to hold bitmaps");
return -EINVAL;
}
ll->entries_per_block = (ll->block_size - sizeof(struct disk_bitmap_header)) *
ENTRIES_PER_BYTE;
ll->nr_blocks = 0;
ll->bitmap_root = 0;
ll->ref_count_root = 0;
ll->bitmap_index_changed = false;
return 0;
}
int sm_ll_extend(struct ll_disk *ll, dm_block_t extra_blocks)
{
int r;
dm_block_t i, nr_blocks, nr_indexes;
unsigned int old_blocks, blocks;
nr_blocks = ll->nr_blocks + extra_blocks;
old_blocks = dm_sector_div_up(ll->nr_blocks, ll->entries_per_block);
blocks = dm_sector_div_up(nr_blocks, ll->entries_per_block);
nr_indexes = dm_sector_div_up(nr_blocks, ll->entries_per_block);
if (nr_indexes > ll->max_entries(ll)) {
DMERR("space map too large");
return -EINVAL;
}
/*
* We need to set this before the dm_tm_new_block() call below.
*/
ll->nr_blocks = nr_blocks;
for (i = old_blocks; i < blocks; i++) {
struct dm_block *b;
struct disk_index_entry idx;
r = dm_tm_new_block(ll->tm, &dm_sm_bitmap_validator, &b);
if (r < 0)
return r;
idx.blocknr = cpu_to_le64(dm_block_location(b));
dm_tm_unlock(ll->tm, b);
idx.nr_free = cpu_to_le32(ll->entries_per_block);
idx.none_free_before = 0;
r = ll->save_ie(ll, i, &idx);
if (r < 0)
return r;
}
return 0;
}
int sm_ll_lookup_bitmap(struct ll_disk *ll, dm_block_t b, uint32_t *result)
{
int r;
dm_block_t index = b;
struct disk_index_entry ie_disk;
struct dm_block *blk;
if (b >= ll->nr_blocks) {
DMERR_LIMIT("metadata block out of bounds");
return -EINVAL;
}
b = do_div(index, ll->entries_per_block);
r = ll->load_ie(ll, index, &ie_disk);
if (r < 0)
return r;
r = dm_tm_read_lock(ll->tm, le64_to_cpu(ie_disk.blocknr),
&dm_sm_bitmap_validator, &blk);
if (r < 0)
return r;
*result = sm_lookup_bitmap(dm_bitmap_data(blk), b);
dm_tm_unlock(ll->tm, blk);
return 0;
}
static int sm_ll_lookup_big_ref_count(struct ll_disk *ll, dm_block_t b,
uint32_t *result)
{
__le32 le_rc;
int r;
r = dm_btree_lookup(&ll->ref_count_info, ll->ref_count_root, &b, &le_rc);
if (r < 0)
return r;
*result = le32_to_cpu(le_rc);
return r;
}
int sm_ll_lookup(struct ll_disk *ll, dm_block_t b, uint32_t *result)
{
int r = sm_ll_lookup_bitmap(ll, b, result);
if (r)
return r;
if (*result != 3)
return r;
return sm_ll_lookup_big_ref_count(ll, b, result);
}
int sm_ll_find_free_block(struct ll_disk *ll, dm_block_t begin,
dm_block_t end, dm_block_t *result)
{
int r;
struct disk_index_entry ie_disk;
dm_block_t i, index_begin = begin;
dm_block_t index_end = dm_sector_div_up(end, ll->entries_per_block);
/*
* FIXME: Use shifts
*/
begin = do_div(index_begin, ll->entries_per_block);
end = do_div(end, ll->entries_per_block);
if (end == 0)
end = ll->entries_per_block;
for (i = index_begin; i < index_end; i++, begin = 0) {
struct dm_block *blk;
unsigned int position;
uint32_t bit_end;
r = ll->load_ie(ll, i, &ie_disk);
if (r < 0)
return r;
if (le32_to_cpu(ie_disk.nr_free) == 0)
continue;
r = dm_tm_read_lock(ll->tm, le64_to_cpu(ie_disk.blocknr),
&dm_sm_bitmap_validator, &blk);
if (r < 0)
return r;
bit_end = (i == index_end - 1) ? end : ll->entries_per_block;
r = sm_find_free(dm_bitmap_data(blk),
max_t(unsigned int, begin, le32_to_cpu(ie_disk.none_free_before)),
bit_end, &position);
if (r == -ENOSPC) {
/*
* This might happen because we started searching
* part way through the bitmap.
*/
dm_tm_unlock(ll->tm, blk);
continue;
}
dm_tm_unlock(ll->tm, blk);
*result = i * ll->entries_per_block + (dm_block_t) position;
return 0;
}
return -ENOSPC;
}
int sm_ll_find_common_free_block(struct ll_disk *old_ll, struct ll_disk *new_ll,
dm_block_t begin, dm_block_t end, dm_block_t *b)
{
int r;
uint32_t count;
do {
r = sm_ll_find_free_block(new_ll, begin, new_ll->nr_blocks, b);
if (r)
break;
/* double check this block wasn't used in the old transaction */
if (*b >= old_ll->nr_blocks)
count = 0;
else {
r = sm_ll_lookup(old_ll, *b, &count);
if (r)
break;
if (count)
begin = *b + 1;
}
} while (count);
return r;
}
/*----------------------------------------------------------------*/
int sm_ll_insert(struct ll_disk *ll, dm_block_t b,
uint32_t ref_count, int32_t *nr_allocations)
{
int r;
uint32_t bit, old;
struct dm_block *nb;
dm_block_t index = b;
struct disk_index_entry ie_disk;
void *bm_le;
int inc;
bit = do_div(index, ll->entries_per_block);
r = ll->load_ie(ll, index, &ie_disk);
if (r < 0)
return r;
r = dm_tm_shadow_block(ll->tm, le64_to_cpu(ie_disk.blocknr),
&dm_sm_bitmap_validator, &nb, &inc);
if (r < 0) {
DMERR("dm_tm_shadow_block() failed");
return r;
}
ie_disk.blocknr = cpu_to_le64(dm_block_location(nb));
bm_le = dm_bitmap_data(nb);
old = sm_lookup_bitmap(bm_le, bit);
if (old > 2) {
r = sm_ll_lookup_big_ref_count(ll, b, &old);
if (r < 0) {
dm_tm_unlock(ll->tm, nb);
return r;
}
}
if (r) {
dm_tm_unlock(ll->tm, nb);
return r;
}
if (ref_count <= 2) {
sm_set_bitmap(bm_le, bit, ref_count);
dm_tm_unlock(ll->tm, nb);
if (old > 2) {
r = dm_btree_remove(&ll->ref_count_info,
ll->ref_count_root,
&b, &ll->ref_count_root);
if (r)
return r;
}
} else {
__le32 le_rc = cpu_to_le32(ref_count);
sm_set_bitmap(bm_le, bit, 3);
dm_tm_unlock(ll->tm, nb);
__dm_bless_for_disk(&le_rc);
r = dm_btree_insert(&ll->ref_count_info, ll->ref_count_root,
&b, &le_rc, &ll->ref_count_root);
if (r < 0) {
DMERR("ref count insert failed");
return r;
}
}
if (ref_count && !old) {
*nr_allocations = 1;
ll->nr_allocated++;
le32_add_cpu(&ie_disk.nr_free, -1);
if (le32_to_cpu(ie_disk.none_free_before) == bit)
ie_disk.none_free_before = cpu_to_le32(bit + 1);
} else if (old && !ref_count) {
*nr_allocations = -1;
ll->nr_allocated--;
le32_add_cpu(&ie_disk.nr_free, 1);
ie_disk.none_free_before = cpu_to_le32(min(le32_to_cpu(ie_disk.none_free_before), bit));
} else
*nr_allocations = 0;
return ll->save_ie(ll, index, &ie_disk);
}
/*----------------------------------------------------------------*/
/*
* Holds useful intermediate results for the range based inc and dec
* operations.
*/
struct inc_context {
struct disk_index_entry ie_disk;
struct dm_block *bitmap_block;
void *bitmap;
struct dm_block *overflow_leaf;
};
static inline void init_inc_context(struct inc_context *ic)
{
ic->bitmap_block = NULL;
ic->bitmap = NULL;
ic->overflow_leaf = NULL;
}
static inline void exit_inc_context(struct ll_disk *ll, struct inc_context *ic)
{
if (ic->bitmap_block)
dm_tm_unlock(ll->tm, ic->bitmap_block);
if (ic->overflow_leaf)
dm_tm_unlock(ll->tm, ic->overflow_leaf);
}
static inline void reset_inc_context(struct ll_disk *ll, struct inc_context *ic)
{
exit_inc_context(ll, ic);
init_inc_context(ic);
}
/*
* Confirms a btree node contains a particular key at an index.
*/
static bool contains_key(struct btree_node *n, uint64_t key, int index)
{
return index >= 0 &&
index < le32_to_cpu(n->header.nr_entries) &&
le64_to_cpu(n->keys[index]) == key;
}
static int __sm_ll_inc_overflow(struct ll_disk *ll, dm_block_t b, struct inc_context *ic)
{
int r;
int index;
struct btree_node *n;
__le32 *v_ptr;
uint32_t rc;
/*
* bitmap_block needs to be unlocked because getting the
* overflow_leaf may need to allocate, and thus use the space map.
*/
reset_inc_context(ll, ic);
r = btree_get_overwrite_leaf(&ll->ref_count_info, ll->ref_count_root,
b, &index, &ll->ref_count_root, &ic->overflow_leaf);
if (r < 0)
return r;
n = dm_block_data(ic->overflow_leaf);
if (!contains_key(n, b, index)) {
DMERR("overflow btree is missing an entry");
return -EINVAL;
}
v_ptr = value_ptr(n, index);
rc = le32_to_cpu(*v_ptr) + 1;
*v_ptr = cpu_to_le32(rc);
return 0;
}
static int sm_ll_inc_overflow(struct ll_disk *ll, dm_block_t b, struct inc_context *ic)
{
int index;
struct btree_node *n;
__le32 *v_ptr;
uint32_t rc;
/*
* Do we already have the correct overflow leaf?
*/
if (ic->overflow_leaf) {
n = dm_block_data(ic->overflow_leaf);
index = lower_bound(n, b);
if (contains_key(n, b, index)) {
v_ptr = value_ptr(n, index);
rc = le32_to_cpu(*v_ptr) + 1;
*v_ptr = cpu_to_le32(rc);
return 0;
}
}
return __sm_ll_inc_overflow(ll, b, ic);
}
static inline int shadow_bitmap(struct ll_disk *ll, struct inc_context *ic)
{
int r, inc;
r = dm_tm_shadow_block(ll->tm, le64_to_cpu(ic->ie_disk.blocknr),
&dm_sm_bitmap_validator, &ic->bitmap_block, &inc);
if (r < 0) {
DMERR("dm_tm_shadow_block() failed");
return r;
}
ic->ie_disk.blocknr = cpu_to_le64(dm_block_location(ic->bitmap_block));
ic->bitmap = dm_bitmap_data(ic->bitmap_block);
return 0;
}
/*
* Once shadow_bitmap has been called, which always happens at the start of inc/dec,
* we can reopen the bitmap with a simple write lock, rather than re calling
* dm_tm_shadow_block().
*/
static inline int ensure_bitmap(struct ll_disk *ll, struct inc_context *ic)
{
if (!ic->bitmap_block) {
int r = dm_bm_write_lock(dm_tm_get_bm(ll->tm), le64_to_cpu(ic->ie_disk.blocknr),
&dm_sm_bitmap_validator, &ic->bitmap_block);
if (r) {
DMERR("unable to re-get write lock for bitmap");
return r;
}
ic->bitmap = dm_bitmap_data(ic->bitmap_block);
}
return 0;
}
/*
* Loops round incrementing entries in a single bitmap.
*/
static inline int sm_ll_inc_bitmap(struct ll_disk *ll, dm_block_t b,
uint32_t bit, uint32_t bit_end,
int32_t *nr_allocations, dm_block_t *new_b,
struct inc_context *ic)
{
int r;
__le32 le_rc;
uint32_t old;
for (; bit != bit_end; bit++, b++) {
/*
* We only need to drop the bitmap if we need to find a new btree
* leaf for the overflow. So if it was dropped last iteration,
* we now re-get it.
*/
r = ensure_bitmap(ll, ic);
if (r)
return r;
old = sm_lookup_bitmap(ic->bitmap, bit);
switch (old) {
case 0:
/* inc bitmap, adjust nr_allocated */
sm_set_bitmap(ic->bitmap, bit, 1);
(*nr_allocations)++;
ll->nr_allocated++;
le32_add_cpu(&ic->ie_disk.nr_free, -1);
if (le32_to_cpu(ic->ie_disk.none_free_before) == bit)
ic->ie_disk.none_free_before = cpu_to_le32(bit + 1);
break;
case 1:
/* inc bitmap */
sm_set_bitmap(ic->bitmap, bit, 2);
break;
case 2:
/* inc bitmap and insert into overflow */
sm_set_bitmap(ic->bitmap, bit, 3);
reset_inc_context(ll, ic);
le_rc = cpu_to_le32(3);
__dm_bless_for_disk(&le_rc);
r = dm_btree_insert(&ll->ref_count_info, ll->ref_count_root,
&b, &le_rc, &ll->ref_count_root);
if (r < 0) {
DMERR("ref count insert failed");
return r;
}
break;
default:
/*
* inc within the overflow tree only.
*/
r = sm_ll_inc_overflow(ll, b, ic);
if (r < 0)
return r;
}
}
*new_b = b;
return 0;
}
/*
* Finds a bitmap that contains entries in the block range, and increments
* them.
*/
static int __sm_ll_inc(struct ll_disk *ll, dm_block_t b, dm_block_t e,
int32_t *nr_allocations, dm_block_t *new_b)
{
int r;
struct inc_context ic;
uint32_t bit, bit_end;
dm_block_t index = b;
init_inc_context(&ic);
bit = do_div(index, ll->entries_per_block);
r = ll->load_ie(ll, index, &ic.ie_disk);
if (r < 0)
return r;
r = shadow_bitmap(ll, &ic);
if (r)
return r;
bit_end = min(bit + (e - b), (dm_block_t) ll->entries_per_block);
r = sm_ll_inc_bitmap(ll, b, bit, bit_end, nr_allocations, new_b, &ic);
exit_inc_context(ll, &ic);
if (r)
return r;
return ll->save_ie(ll, index, &ic.ie_disk);
}
int sm_ll_inc(struct ll_disk *ll, dm_block_t b, dm_block_t e,
int32_t *nr_allocations)
{
*nr_allocations = 0;
while (b != e) {
int r = __sm_ll_inc(ll, b, e, nr_allocations, &b);
if (r)
return r;
}
return 0;
}
/*----------------------------------------------------------------*/
static int __sm_ll_del_overflow(struct ll_disk *ll, dm_block_t b,
struct inc_context *ic)
{
reset_inc_context(ll, ic);
return dm_btree_remove(&ll->ref_count_info, ll->ref_count_root,
&b, &ll->ref_count_root);
}
static int __sm_ll_dec_overflow(struct ll_disk *ll, dm_block_t b,
struct inc_context *ic, uint32_t *old_rc)
{
int r;
int index = -1;
struct btree_node *n;
__le32 *v_ptr;
uint32_t rc;
reset_inc_context(ll, ic);
r = btree_get_overwrite_leaf(&ll->ref_count_info, ll->ref_count_root,
b, &index, &ll->ref_count_root, &ic->overflow_leaf);
if (r < 0)
return r;
n = dm_block_data(ic->overflow_leaf);
if (!contains_key(n, b, index)) {
DMERR("overflow btree is missing an entry");
return -EINVAL;
}
v_ptr = value_ptr(n, index);
rc = le32_to_cpu(*v_ptr);
*old_rc = rc;
if (rc == 3)
return __sm_ll_del_overflow(ll, b, ic);
rc--;
*v_ptr = cpu_to_le32(rc);
return 0;
}
static int sm_ll_dec_overflow(struct ll_disk *ll, dm_block_t b,
struct inc_context *ic, uint32_t *old_rc)
{
/*
* Do we already have the correct overflow leaf?
*/
if (ic->overflow_leaf) {
int index;
struct btree_node *n;
__le32 *v_ptr;
uint32_t rc;
n = dm_block_data(ic->overflow_leaf);
index = lower_bound(n, b);
if (contains_key(n, b, index)) {
v_ptr = value_ptr(n, index);
rc = le32_to_cpu(*v_ptr);
*old_rc = rc;
if (rc > 3) {
rc--;
*v_ptr = cpu_to_le32(rc);
return 0;
} else {
return __sm_ll_del_overflow(ll, b, ic);
}
}
}
return __sm_ll_dec_overflow(ll, b, ic, old_rc);
}
/*
* Loops round incrementing entries in a single bitmap.
*/
static inline int sm_ll_dec_bitmap(struct ll_disk *ll, dm_block_t b,
uint32_t bit, uint32_t bit_end,
struct inc_context *ic,
int32_t *nr_allocations, dm_block_t *new_b)
{
int r;
uint32_t old;
for (; bit != bit_end; bit++, b++) {
/*
* We only need to drop the bitmap if we need to find a new btree
* leaf for the overflow. So if it was dropped last iteration,
* we now re-get it.
*/
r = ensure_bitmap(ll, ic);
if (r)
return r;
old = sm_lookup_bitmap(ic->bitmap, bit);
switch (old) {
case 0:
DMERR("unable to decrement block");
return -EINVAL;
case 1:
/* dec bitmap */
sm_set_bitmap(ic->bitmap, bit, 0);
(*nr_allocations)--;
ll->nr_allocated--;
le32_add_cpu(&ic->ie_disk.nr_free, 1);
ic->ie_disk.none_free_before =
cpu_to_le32(min(le32_to_cpu(ic->ie_disk.none_free_before), bit));
break;
case 2:
/* dec bitmap and insert into overflow */
sm_set_bitmap(ic->bitmap, bit, 1);
break;
case 3:
r = sm_ll_dec_overflow(ll, b, ic, &old);
if (r < 0)
return r;
if (old == 3) {
r = ensure_bitmap(ll, ic);
if (r)
return r;
sm_set_bitmap(ic->bitmap, bit, 2);
}
break;
}
}
*new_b = b;
return 0;
}
static int __sm_ll_dec(struct ll_disk *ll, dm_block_t b, dm_block_t e,
int32_t *nr_allocations, dm_block_t *new_b)
{
int r;
uint32_t bit, bit_end;
struct inc_context ic;
dm_block_t index = b;
init_inc_context(&ic);
bit = do_div(index, ll->entries_per_block);
r = ll->load_ie(ll, index, &ic.ie_disk);
if (r < 0)
return r;
r = shadow_bitmap(ll, &ic);
if (r)
return r;
bit_end = min(bit + (e - b), (dm_block_t) ll->entries_per_block);
r = sm_ll_dec_bitmap(ll, b, bit, bit_end, &ic, nr_allocations, new_b);
exit_inc_context(ll, &ic);
if (r)
return r;
return ll->save_ie(ll, index, &ic.ie_disk);
}
int sm_ll_dec(struct ll_disk *ll, dm_block_t b, dm_block_t e,
int32_t *nr_allocations)
{
*nr_allocations = 0;
while (b != e) {
int r = __sm_ll_dec(ll, b, e, nr_allocations, &b);
if (r)
return r;
}
return 0;
}
/*----------------------------------------------------------------*/
int sm_ll_commit(struct ll_disk *ll)
{
int r = 0;
if (ll->bitmap_index_changed) {
r = ll->commit(ll);
if (!r)
ll->bitmap_index_changed = false;
}
return r;
}
/*----------------------------------------------------------------*/
static int metadata_ll_load_ie(struct ll_disk *ll, dm_block_t index,
struct disk_index_entry *ie)
{
memcpy(ie, ll->mi_le.index + index, sizeof(*ie));
return 0;
}
static int metadata_ll_save_ie(struct ll_disk *ll, dm_block_t index,
struct disk_index_entry *ie)
{
ll->bitmap_index_changed = true;
memcpy(ll->mi_le.index + index, ie, sizeof(*ie));
return 0;
}
static int metadata_ll_init_index(struct ll_disk *ll)
{
int r;
struct dm_block *b;
r = dm_tm_new_block(ll->tm, &index_validator, &b);
if (r < 0)
return r;
ll->bitmap_root = dm_block_location(b);
dm_tm_unlock(ll->tm, b);
return 0;
}
static int metadata_ll_open(struct ll_disk *ll)
{
int r;
struct dm_block *block;
r = dm_tm_read_lock(ll->tm, ll->bitmap_root,
&index_validator, &block);
if (r)
return r;
memcpy(&ll->mi_le, dm_block_data(block), sizeof(ll->mi_le));
dm_tm_unlock(ll->tm, block);
return 0;
}
static dm_block_t metadata_ll_max_entries(struct ll_disk *ll)
{
return MAX_METADATA_BITMAPS;
}
static int metadata_ll_commit(struct ll_disk *ll)
{
int r, inc;
struct dm_block *b;
r = dm_tm_shadow_block(ll->tm, ll->bitmap_root, &index_validator, &b, &inc);
if (r)
return r;
memcpy(dm_block_data(b), &ll->mi_le, sizeof(ll->mi_le));
ll->bitmap_root = dm_block_location(b);
dm_tm_unlock(ll->tm, b);
return 0;
}
int sm_ll_new_metadata(struct ll_disk *ll, struct dm_transaction_manager *tm)
{
int r;
r = sm_ll_init(ll, tm);
if (r < 0)
return r;
ll->load_ie = metadata_ll_load_ie;
ll->save_ie = metadata_ll_save_ie;
ll->init_index = metadata_ll_init_index;
ll->open_index = metadata_ll_open;
ll->max_entries = metadata_ll_max_entries;
ll->commit = metadata_ll_commit;
ll->nr_blocks = 0;
ll->nr_allocated = 0;
r = ll->init_index(ll);
if (r < 0)
return r;
r = dm_btree_empty(&ll->ref_count_info, &ll->ref_count_root);
if (r < 0)
return r;
return 0;
}
int sm_ll_open_metadata(struct ll_disk *ll, struct dm_transaction_manager *tm,
void *root_le, size_t len)
{
int r;
struct disk_sm_root smr;
if (len < sizeof(struct disk_sm_root)) {
DMERR("sm_metadata root too small");
return -ENOMEM;
}
/*
* We don't know the alignment of the root_le buffer, so need to
* copy into a new structure.
*/
memcpy(&smr, root_le, sizeof(smr));
r = sm_ll_init(ll, tm);
if (r < 0)
return r;
ll->load_ie = metadata_ll_load_ie;
ll->save_ie = metadata_ll_save_ie;
ll->init_index = metadata_ll_init_index;
ll->open_index = metadata_ll_open;
ll->max_entries = metadata_ll_max_entries;
ll->commit = metadata_ll_commit;
ll->nr_blocks = le64_to_cpu(smr.nr_blocks);
ll->nr_allocated = le64_to_cpu(smr.nr_allocated);
ll->bitmap_root = le64_to_cpu(smr.bitmap_root);
ll->ref_count_root = le64_to_cpu(smr.ref_count_root);
return ll->open_index(ll);
}
/*----------------------------------------------------------------*/
static inline int ie_cache_writeback(struct ll_disk *ll, struct ie_cache *iec)
{
iec->dirty = false;
__dm_bless_for_disk(iec->ie);
return dm_btree_insert(&ll->bitmap_info, ll->bitmap_root,
&iec->index, &iec->ie, &ll->bitmap_root);
}
static inline unsigned int hash_index(dm_block_t index)
{
return dm_hash_block(index, IE_CACHE_MASK);
}
static int disk_ll_load_ie(struct ll_disk *ll, dm_block_t index,
struct disk_index_entry *ie)
{
int r;
unsigned int h = hash_index(index);
struct ie_cache *iec = ll->ie_cache + h;
if (iec->valid) {
if (iec->index == index) {
memcpy(ie, &iec->ie, sizeof(*ie));
return 0;
}
if (iec->dirty) {
r = ie_cache_writeback(ll, iec);
if (r)
return r;
}
}
r = dm_btree_lookup(&ll->bitmap_info, ll->bitmap_root, &index, ie);
if (!r) {
iec->valid = true;
iec->dirty = false;
iec->index = index;
memcpy(&iec->ie, ie, sizeof(*ie));
}
return r;
}
static int disk_ll_save_ie(struct ll_disk *ll, dm_block_t index,
struct disk_index_entry *ie)
{
int r;
unsigned int h = hash_index(index);
struct ie_cache *iec = ll->ie_cache + h;
ll->bitmap_index_changed = true;
if (iec->valid) {
if (iec->index == index) {
memcpy(&iec->ie, ie, sizeof(*ie));
iec->dirty = true;
return 0;
}
if (iec->dirty) {
r = ie_cache_writeback(ll, iec);
if (r)
return r;
}
}
iec->valid = true;
iec->dirty = true;
iec->index = index;
memcpy(&iec->ie, ie, sizeof(*ie));
return 0;
}
static int disk_ll_init_index(struct ll_disk *ll)
{
unsigned int i;
for (i = 0; i < IE_CACHE_SIZE; i++) {
struct ie_cache *iec = ll->ie_cache + i;
iec->valid = false;
iec->dirty = false;
}
return dm_btree_empty(&ll->bitmap_info, &ll->bitmap_root);
}
static int disk_ll_open(struct ll_disk *ll)
{
return 0;
}
static dm_block_t disk_ll_max_entries(struct ll_disk *ll)
{
return -1ULL;
}
static int disk_ll_commit(struct ll_disk *ll)
{
int r = 0;
unsigned int i;
for (i = 0; i < IE_CACHE_SIZE; i++) {
struct ie_cache *iec = ll->ie_cache + i;
if (iec->valid && iec->dirty)
r = ie_cache_writeback(ll, iec);
}
return r;
}
int sm_ll_new_disk(struct ll_disk *ll, struct dm_transaction_manager *tm)
{
int r;
r = sm_ll_init(ll, tm);
if (r < 0)
return r;
ll->load_ie = disk_ll_load_ie;
ll->save_ie = disk_ll_save_ie;
ll->init_index = disk_ll_init_index;
ll->open_index = disk_ll_open;
ll->max_entries = disk_ll_max_entries;
ll->commit = disk_ll_commit;
ll->nr_blocks = 0;
ll->nr_allocated = 0;
r = ll->init_index(ll);
if (r < 0)
return r;
r = dm_btree_empty(&ll->ref_count_info, &ll->ref_count_root);
if (r < 0)
return r;
return 0;
}
int sm_ll_open_disk(struct ll_disk *ll, struct dm_transaction_manager *tm,
void *root_le, size_t len)
{
int r;
struct disk_sm_root *smr = root_le;
if (len < sizeof(struct disk_sm_root)) {
DMERR("sm_metadata root too small");
return -ENOMEM;
}
r = sm_ll_init(ll, tm);
if (r < 0)
return r;
ll->load_ie = disk_ll_load_ie;
ll->save_ie = disk_ll_save_ie;
ll->init_index = disk_ll_init_index;
ll->open_index = disk_ll_open;
ll->max_entries = disk_ll_max_entries;
ll->commit = disk_ll_commit;
ll->nr_blocks = le64_to_cpu(smr->nr_blocks);
ll->nr_allocated = le64_to_cpu(smr->nr_allocated);
ll->bitmap_root = le64_to_cpu(smr->bitmap_root);
ll->ref_count_root = le64_to_cpu(smr->ref_count_root);
return ll->open_index(ll);
}
/*----------------------------------------------------------------*/
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* VLAN netlink control interface
*
* Copyright (c) 2007 Patrick McHardy <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#include <linux/module.h>
#include <net/net_namespace.h>
#include <net/netlink.h>
#include <net/rtnetlink.h>
#include "vlan.h"
static const struct nla_policy vlan_policy[IFLA_VLAN_MAX + 1] = {
[IFLA_VLAN_ID] = { .type = NLA_U16 },
[IFLA_VLAN_FLAGS] = { .len = sizeof(struct ifla_vlan_flags) },
[IFLA_VLAN_EGRESS_QOS] = { .type = NLA_NESTED },
[IFLA_VLAN_INGRESS_QOS] = { .type = NLA_NESTED },
[IFLA_VLAN_PROTOCOL] = { .type = NLA_U16 },
};
static const struct nla_policy vlan_map_policy[IFLA_VLAN_QOS_MAX + 1] = {
[IFLA_VLAN_QOS_MAPPING] = { .len = sizeof(struct ifla_vlan_qos_mapping) },
};
static inline int vlan_validate_qos_map(struct nlattr *attr)
{
if (!attr)
return 0;
return nla_validate_nested_deprecated(attr, IFLA_VLAN_QOS_MAX,
vlan_map_policy, NULL);
}
static int vlan_validate(struct nlattr *tb[], struct nlattr *data[],
struct netlink_ext_ack *extack)
{
struct ifla_vlan_flags *flags;
u16 id;
int err;
if (tb[IFLA_ADDRESS]) {
if (nla_len(tb[IFLA_ADDRESS]) != ETH_ALEN) {
NL_SET_ERR_MSG_MOD(extack, "Invalid link address");
return -EINVAL;
}
if (!is_valid_ether_addr(nla_data(tb[IFLA_ADDRESS]))) {
NL_SET_ERR_MSG_MOD(extack, "Invalid link address");
return -EADDRNOTAVAIL;
}
}
if (!data) {
NL_SET_ERR_MSG_MOD(extack, "VLAN properties not specified");
return -EINVAL;
}
if (data[IFLA_VLAN_PROTOCOL]) {
switch (nla_get_be16(data[IFLA_VLAN_PROTOCOL])) {
case htons(ETH_P_8021Q):
case htons(ETH_P_8021AD):
break;
default:
NL_SET_ERR_MSG_MOD(extack, "Invalid VLAN protocol");
return -EPROTONOSUPPORT;
}
}
if (data[IFLA_VLAN_ID]) {
id = nla_get_u16(data[IFLA_VLAN_ID]);
if (id >= VLAN_VID_MASK) {
NL_SET_ERR_MSG_MOD(extack, "Invalid VLAN id");
return -ERANGE;
}
}
if (data[IFLA_VLAN_FLAGS]) {
flags = nla_data(data[IFLA_VLAN_FLAGS]);
if ((flags->flags & flags->mask) &
~(VLAN_FLAG_REORDER_HDR | VLAN_FLAG_GVRP |
VLAN_FLAG_LOOSE_BINDING | VLAN_FLAG_MVRP |
VLAN_FLAG_BRIDGE_BINDING)) {
NL_SET_ERR_MSG_MOD(extack, "Invalid VLAN flags");
return -EINVAL;
}
}
err = vlan_validate_qos_map(data[IFLA_VLAN_INGRESS_QOS]);
if (err < 0) {
NL_SET_ERR_MSG_MOD(extack, "Invalid ingress QOS map");
return err;
}
err = vlan_validate_qos_map(data[IFLA_VLAN_EGRESS_QOS]);
if (err < 0) {
NL_SET_ERR_MSG_MOD(extack, "Invalid egress QOS map");
return err;
}
return 0;
}
static int vlan_changelink(struct net_device *dev, struct nlattr *tb[],
struct nlattr *data[],
struct netlink_ext_ack *extack)
{
struct ifla_vlan_flags *flags;
struct ifla_vlan_qos_mapping *m;
struct nlattr *attr;
int rem, err;
if (data[IFLA_VLAN_FLAGS]) {
flags = nla_data(data[IFLA_VLAN_FLAGS]);
err = vlan_dev_change_flags(dev, flags->flags, flags->mask);
if (err)
return err;
}
if (data[IFLA_VLAN_INGRESS_QOS]) {
nla_for_each_nested_type(attr, IFLA_VLAN_QOS_MAPPING,
data[IFLA_VLAN_INGRESS_QOS], rem) {
m = nla_data(attr);
vlan_dev_set_ingress_priority(dev, m->to, m->from);
}
}
if (data[IFLA_VLAN_EGRESS_QOS]) {
nla_for_each_nested_type(attr, IFLA_VLAN_QOS_MAPPING,
data[IFLA_VLAN_EGRESS_QOS], rem) {
m = nla_data(attr);
err = vlan_dev_set_egress_priority(dev, m->from, m->to);
if (err)
return err;
}
}
return 0;
}
static int vlan_newlink(struct net *src_net, struct net_device *dev,
struct nlattr *tb[], struct nlattr *data[],
struct netlink_ext_ack *extack)
{
struct vlan_dev_priv *vlan = vlan_dev_priv(dev);
struct net_device *real_dev;
unsigned int max_mtu;
__be16 proto;
int err;
if (!data[IFLA_VLAN_ID]) {
NL_SET_ERR_MSG_MOD(extack, "VLAN id not specified");
return -EINVAL;
}
if (!tb[IFLA_LINK]) {
NL_SET_ERR_MSG_MOD(extack, "link not specified");
return -EINVAL;
}
real_dev = __dev_get_by_index(src_net, nla_get_u32(tb[IFLA_LINK]));
if (!real_dev) {
NL_SET_ERR_MSG_MOD(extack, "link does not exist");
return -ENODEV;
}
proto = nla_get_be16_default(data[IFLA_VLAN_PROTOCOL],
htons(ETH_P_8021Q));
vlan->vlan_proto = proto;
vlan->vlan_id = nla_get_u16(data[IFLA_VLAN_ID]);
vlan->real_dev = real_dev;
dev->priv_flags |= (real_dev->priv_flags & IFF_XMIT_DST_RELEASE);
vlan->flags = VLAN_FLAG_REORDER_HDR;
err = vlan_check_real_dev(real_dev, vlan->vlan_proto, vlan->vlan_id,
extack);
if (err < 0)
return err;
max_mtu = netif_reduces_vlan_mtu(real_dev) ? real_dev->mtu - VLAN_HLEN :
real_dev->mtu;
if (!tb[IFLA_MTU])
dev->mtu = max_mtu;
else if (dev->mtu > max_mtu)
return -EINVAL;
/* Note: If this initial vlan_changelink() fails, we need
* to call vlan_dev_free_egress_priority() to free memory.
*/
err = vlan_changelink(dev, tb, data, extack);
if (!err)
err = register_vlan_dev(dev, extack);
if (err)
vlan_dev_free_egress_priority(dev);
return err;
}
static inline size_t vlan_qos_map_size(unsigned int n)
{
if (n == 0)
return 0;
/* IFLA_VLAN_{EGRESS,INGRESS}_QOS + n * IFLA_VLAN_QOS_MAPPING */
return nla_total_size(sizeof(struct nlattr)) +
nla_total_size(sizeof(struct ifla_vlan_qos_mapping)) * n;
}
static size_t vlan_get_size(const struct net_device *dev)
{
struct vlan_dev_priv *vlan = vlan_dev_priv(dev);
return nla_total_size(2) + /* IFLA_VLAN_PROTOCOL */
nla_total_size(2) + /* IFLA_VLAN_ID */
nla_total_size(sizeof(struct ifla_vlan_flags)) + /* IFLA_VLAN_FLAGS */
vlan_qos_map_size(vlan->nr_ingress_mappings) +
vlan_qos_map_size(vlan->nr_egress_mappings);
}
static int vlan_fill_info(struct sk_buff *skb, const struct net_device *dev)
{
struct vlan_dev_priv *vlan = vlan_dev_priv(dev);
struct vlan_priority_tci_mapping *pm;
struct ifla_vlan_flags f;
struct ifla_vlan_qos_mapping m;
struct nlattr *nest;
unsigned int i;
if (nla_put_be16(skb, IFLA_VLAN_PROTOCOL, vlan->vlan_proto) ||
nla_put_u16(skb, IFLA_VLAN_ID, vlan->vlan_id))
goto nla_put_failure;
if (vlan->flags) {
f.flags = vlan->flags;
f.mask = ~0;
if (nla_put(skb, IFLA_VLAN_FLAGS, sizeof(f), &f))
goto nla_put_failure;
}
if (vlan->nr_ingress_mappings) {
nest = nla_nest_start_noflag(skb, IFLA_VLAN_INGRESS_QOS);
if (nest == NULL)
goto nla_put_failure;
for (i = 0; i < ARRAY_SIZE(vlan->ingress_priority_map); i++) {
if (!vlan->ingress_priority_map[i])
continue;
m.from = i;
m.to = vlan->ingress_priority_map[i];
if (nla_put(skb, IFLA_VLAN_QOS_MAPPING,
sizeof(m), &m))
goto nla_put_failure;
}
nla_nest_end(skb, nest);
}
if (vlan->nr_egress_mappings) {
nest = nla_nest_start_noflag(skb, IFLA_VLAN_EGRESS_QOS);
if (nest == NULL)
goto nla_put_failure;
for (i = 0; i < ARRAY_SIZE(vlan->egress_priority_map); i++) {
for (pm = vlan->egress_priority_map[i]; pm;
pm = pm->next) {
if (!pm->vlan_qos)
continue;
m.from = pm->priority;
m.to = (pm->vlan_qos >> 13) & 0x7;
if (nla_put(skb, IFLA_VLAN_QOS_MAPPING,
sizeof(m), &m))
goto nla_put_failure;
}
}
nla_nest_end(skb, nest);
}
return 0;
nla_put_failure:
return -EMSGSIZE;
}
static struct net *vlan_get_link_net(const struct net_device *dev)
{
struct net_device *real_dev = vlan_dev_priv(dev)->real_dev;
return dev_net(real_dev);
}
struct rtnl_link_ops vlan_link_ops __read_mostly = {
.kind = "vlan",
.maxtype = IFLA_VLAN_MAX,
.policy = vlan_policy,
.priv_size = sizeof(struct vlan_dev_priv),
.setup = vlan_setup,
.validate = vlan_validate,
.newlink = vlan_newlink,
.changelink = vlan_changelink,
.dellink = unregister_vlan_dev,
.get_size = vlan_get_size,
.fill_info = vlan_fill_info,
.get_link_net = vlan_get_link_net,
};
int __init vlan_netlink_init(void)
{
return rtnl_link_register(&vlan_link_ops);
}
void __exit vlan_netlink_fini(void)
{
rtnl_link_unregister(&vlan_link_ops);
}
MODULE_ALIAS_RTNL_LINK("vlan");
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Mikko Perttunen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/interconnect-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/sort.h>
#include <linux/string.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/mc.h>
#include "mc.h"
#define EMC_FBIO_CFG5 0x104
#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
#define EMC_FBIO_CFG5_DRAM_WIDTH_X64 BIT(4)
#define EMC_INTSTATUS 0x0
#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
#define EMC_CFG 0xc
#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
#define EMC_CFG_DRAM_ACPD BIT(29)
#define EMC_CFG_DYN_SREF BIT(28)
#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18)
#define EMC_REFCTRL 0x20
#define EMC_REFCTRL_DEV_SEL_SHIFT 0
#define EMC_REFCTRL_ENABLE BIT(31)
#define EMC_TIMING_CONTROL 0x28
#define EMC_RC 0x2c
#define EMC_RFC 0x30
#define EMC_RAS 0x34
#define EMC_RP 0x38
#define EMC_R2W 0x3c
#define EMC_W2R 0x40
#define EMC_R2P 0x44
#define EMC_W2P 0x48
#define EMC_RD_RCD 0x4c
#define EMC_WR_RCD 0x50
#define EMC_RRD 0x54
#define EMC_REXT 0x58
#define EMC_WDV 0x5c
#define EMC_QUSE 0x60
#define EMC_QRST 0x64
#define EMC_QSAFE 0x68
#define EMC_RDV 0x6c
#define EMC_REFRESH 0x70
#define EMC_BURST_REFRESH_NUM 0x74
#define EMC_PDEX2WR 0x78
#define EMC_PDEX2RD 0x7c
#define EMC_PCHG2PDEN 0x80
#define EMC_ACT2PDEN 0x84
#define EMC_AR2PDEN 0x88
#define EMC_RW2PDEN 0x8c
#define EMC_TXSR 0x90
#define EMC_TCKE 0x94
#define EMC_TFAW 0x98
#define EMC_TRPAB 0x9c
#define EMC_TCLKSTABLE 0xa0
#define EMC_TCLKSTOP 0xa4
#define EMC_TREFBW 0xa8
#define EMC_ODT_WRITE 0xb0
#define EMC_ODT_READ 0xb4
#define EMC_WEXT 0xb8
#define EMC_CTT 0xbc
#define EMC_RFC_SLR 0xc0
#define EMC_MRS_WAIT_CNT2 0xc4
#define EMC_MRS_WAIT_CNT 0xc8
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
#define EMC_MRS 0xcc
#define EMC_MODE_SET_DLL_RESET BIT(8)
#define EMC_MODE_SET_LONG_CNT BIT(26)
#define EMC_EMRS 0xd0
#define EMC_REF 0xd4
#define EMC_PRE 0xd8
#define EMC_SELF_REF 0xe0
#define EMC_SELF_REF_CMD_ENABLED BIT(0)
#define EMC_SELF_REF_DEV_SEL_SHIFT 30
#define EMC_MRW 0xe8
#define EMC_MRR 0xec
#define EMC_MRR_MA_SHIFT 16
#define LPDDR2_MR4_TEMP_SHIFT 0
#define EMC_XM2DQSPADCTRL3 0xf8
#define EMC_FBIO_SPARE 0x100
#define EMC_FBIO_CFG6 0x114
#define EMC_EMRS2 0x12c
#define EMC_MRW2 0x134
#define EMC_MRW4 0x13c
#define EMC_EINPUT 0x14c
#define EMC_EINPUT_DURATION 0x150
#define EMC_PUTERM_EXTRA 0x154
#define EMC_TCKESR 0x158
#define EMC_TPD 0x15c
#define EMC_AUTO_CAL_CONFIG 0x2a4
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
#define EMC_AUTO_CAL_INTERVAL 0x2a8
#define EMC_AUTO_CAL_STATUS 0x2ac
#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
#define EMC_STATUS 0x2b4
#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
#define EMC_CFG_2 0x2b8
#define EMC_CFG_2_MODE_SHIFT 0
#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6)
#define EMC_CFG_DIG_DLL 0x2bc
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
#define EMC_RDV_MASK 0x2cc
#define EMC_WDV_MASK 0x2d0
#define EMC_CTT_DURATION 0x2d8
#define EMC_CTT_TERM_CTRL 0x2dc
#define EMC_ZCAL_INTERVAL 0x2e0
#define EMC_ZCAL_WAIT_CNT 0x2e4
#define EMC_ZQ_CAL 0x2ec
#define EMC_ZQ_CAL_CMD BIT(0)
#define EMC_ZQ_CAL_LONG BIT(4)
#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_XM2CMDPADCTRL 0x2f0
#define EMC_XM2DQSPADCTRL 0x2f8
#define EMC_XM2DQSPADCTRL2 0x2fc
#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
#define EMC_XM2DQPADCTRL 0x300
#define EMC_XM2DQPADCTRL2 0x304
#define EMC_XM2CLKPADCTRL 0x308
#define EMC_XM2COMPPADCTRL 0x30c
#define EMC_XM2VTTGENPADCTRL 0x310
#define EMC_XM2VTTGENPADCTRL2 0x314
#define EMC_XM2VTTGENPADCTRL3 0x318
#define EMC_XM2DQSPADCTRL4 0x320
#define EMC_DLL_XFORM_DQS0 0x328
#define EMC_DLL_XFORM_DQS1 0x32c
#define EMC_DLL_XFORM_DQS2 0x330
#define EMC_DLL_XFORM_DQS3 0x334
#define EMC_DLL_XFORM_DQS4 0x338
#define EMC_DLL_XFORM_DQS5 0x33c
#define EMC_DLL_XFORM_DQS6 0x340
#define EMC_DLL_XFORM_DQS7 0x344
#define EMC_DLL_XFORM_QUSE0 0x348
#define EMC_DLL_XFORM_QUSE1 0x34c
#define EMC_DLL_XFORM_QUSE2 0x350
#define EMC_DLL_XFORM_QUSE3 0x354
#define EMC_DLL_XFORM_QUSE4 0x358
#define EMC_DLL_XFORM_QUSE5 0x35c
#define EMC_DLL_XFORM_QUSE6 0x360
#define EMC_DLL_XFORM_QUSE7 0x364
#define EMC_DLL_XFORM_DQ0 0x368
#define EMC_DLL_XFORM_DQ1 0x36c
#define EMC_DLL_XFORM_DQ2 0x370
#define EMC_DLL_XFORM_DQ3 0x374
#define EMC_DLI_TRIM_TXDQS0 0x3a8
#define EMC_DLI_TRIM_TXDQS1 0x3ac
#define EMC_DLI_TRIM_TXDQS2 0x3b0
#define EMC_DLI_TRIM_TXDQS3 0x3b4
#define EMC_DLI_TRIM_TXDQS4 0x3b8
#define EMC_DLI_TRIM_TXDQS5 0x3bc
#define EMC_DLI_TRIM_TXDQS6 0x3c0
#define EMC_DLI_TRIM_TXDQS7 0x3c4
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
#define EMC_SEL_DPD_CTRL 0x3d8
#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8)
#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5)
#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2)
#define EMC_SEL_DPD_CTRL_DDR3_MASK \
((0xf << 2) | BIT(8))
#define EMC_SEL_DPD_CTRL_MASK \
((0x3 << 2) | BIT(5) | BIT(8))
#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
#define EMC_DYN_SELF_REF_CONTROL 0x3e0
#define EMC_TXSRDLL 0x3e4
#define EMC_CCFIFO_ADDR 0x3e8
#define EMC_CCFIFO_DATA 0x3ec
#define EMC_CCFIFO_STATUS 0x3f0
#define EMC_CDB_CNTL_1 0x3f4
#define EMC_CDB_CNTL_2 0x3f8
#define EMC_XM2CLKPADCTRL2 0x3fc
#define EMC_AUTO_CAL_CONFIG2 0x458
#define EMC_AUTO_CAL_CONFIG3 0x45c
#define EMC_IBDLY 0x468
#define EMC_DLL_XFORM_ADDR0 0x46c
#define EMC_DLL_XFORM_ADDR1 0x470
#define EMC_DLL_XFORM_ADDR2 0x474
#define EMC_DSR_VTTGEN_DRV 0x47c
#define EMC_TXDSRVTTGEN 0x480
#define EMC_XM2CMDPADCTRL4 0x484
#define EMC_XM2CMDPADCTRL5 0x488
#define EMC_DLL_XFORM_DQS8 0x4a0
#define EMC_DLL_XFORM_DQS9 0x4a4
#define EMC_DLL_XFORM_DQS10 0x4a8
#define EMC_DLL_XFORM_DQS11 0x4ac
#define EMC_DLL_XFORM_DQS12 0x4b0
#define EMC_DLL_XFORM_DQS13 0x4b4
#define EMC_DLL_XFORM_DQS14 0x4b8
#define EMC_DLL_XFORM_DQS15 0x4bc
#define EMC_DLL_XFORM_QUSE8 0x4c0
#define EMC_DLL_XFORM_QUSE9 0x4c4
#define EMC_DLL_XFORM_QUSE10 0x4c8
#define EMC_DLL_XFORM_QUSE11 0x4cc
#define EMC_DLL_XFORM_QUSE12 0x4d0
#define EMC_DLL_XFORM_QUSE13 0x4d4
#define EMC_DLL_XFORM_QUSE14 0x4d8
#define EMC_DLL_XFORM_QUSE15 0x4dc
#define EMC_DLL_XFORM_DQ4 0x4e0
#define EMC_DLL_XFORM_DQ5 0x4e4
#define EMC_DLL_XFORM_DQ6 0x4e8
#define EMC_DLL_XFORM_DQ7 0x4ec
#define EMC_DLI_TRIM_TXDQS8 0x520
#define EMC_DLI_TRIM_TXDQS9 0x524
#define EMC_DLI_TRIM_TXDQS10 0x528
#define EMC_DLI_TRIM_TXDQS11 0x52c
#define EMC_DLI_TRIM_TXDQS12 0x530
#define EMC_DLI_TRIM_TXDQS13 0x534
#define EMC_DLI_TRIM_TXDQS14 0x538
#define EMC_DLI_TRIM_TXDQS15 0x53c
#define EMC_CDB_CNTL_3 0x540
#define EMC_XM2DQSPADCTRL5 0x544
#define EMC_XM2DQSPADCTRL6 0x548
#define EMC_XM2DQPADCTRL3 0x54c
#define EMC_DLL_XFORM_ADDR3 0x550
#define EMC_DLL_XFORM_ADDR4 0x554
#define EMC_DLL_XFORM_ADDR5 0x558
#define EMC_CFG_PIPE 0x560
#define EMC_QPOP 0x564
#define EMC_QUSE_WIDTH 0x568
#define EMC_PUTERM_WIDTH 0x56c
#define EMC_BGBIAS_CTL0 0x570
#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
#define EMC_PUTERM_ADJ 0x574
#define DRAM_DEV_SEL_ALL 0
#define DRAM_DEV_SEL_0 BIT(31)
#define DRAM_DEV_SEL_1 BIT(30)
#define EMC_CFG_POWER_FEATURES_MASK \
(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
/* Maximum amount of time in us. to wait for changes to become effective */
#define EMC_STATUS_UPDATE_TIMEOUT 1000
enum emc_dram_type {
DRAM_TYPE_DDR3 = 0,
DRAM_TYPE_DDR1 = 1,
DRAM_TYPE_LPDDR3 = 2,
DRAM_TYPE_DDR2 = 3
};
enum emc_dll_change {
DLL_CHANGE_NONE,
DLL_CHANGE_ON,
DLL_CHANGE_OFF
};
static const unsigned long emc_burst_regs[] = {
EMC_RC,
EMC_RFC,
EMC_RFC_SLR,
EMC_RAS,
EMC_RP,
EMC_R2W,
EMC_W2R,
EMC_R2P,
EMC_W2P,
EMC_RD_RCD,
EMC_WR_RCD,
EMC_RRD,
EMC_REXT,
EMC_WEXT,
EMC_WDV,
EMC_WDV_MASK,
EMC_QUSE,
EMC_QUSE_WIDTH,
EMC_IBDLY,
EMC_EINPUT,
EMC_EINPUT_DURATION,
EMC_PUTERM_EXTRA,
EMC_PUTERM_WIDTH,
EMC_PUTERM_ADJ,
EMC_CDB_CNTL_1,
EMC_CDB_CNTL_2,
EMC_CDB_CNTL_3,
EMC_QRST,
EMC_QSAFE,
EMC_RDV,
EMC_RDV_MASK,
EMC_REFRESH,
EMC_BURST_REFRESH_NUM,
EMC_PRE_REFRESH_REQ_CNT,
EMC_PDEX2WR,
EMC_PDEX2RD,
EMC_PCHG2PDEN,
EMC_ACT2PDEN,
EMC_AR2PDEN,
EMC_RW2PDEN,
EMC_TXSR,
EMC_TXSRDLL,
EMC_TCKE,
EMC_TCKESR,
EMC_TPD,
EMC_TFAW,
EMC_TRPAB,
EMC_TCLKSTABLE,
EMC_TCLKSTOP,
EMC_TREFBW,
EMC_FBIO_CFG6,
EMC_ODT_WRITE,
EMC_ODT_READ,
EMC_FBIO_CFG5,
EMC_CFG_DIG_DLL,
EMC_CFG_DIG_DLL_PERIOD,
EMC_DLL_XFORM_DQS0,
EMC_DLL_XFORM_DQS1,
EMC_DLL_XFORM_DQS2,
EMC_DLL_XFORM_DQS3,
EMC_DLL_XFORM_DQS4,
EMC_DLL_XFORM_DQS5,
EMC_DLL_XFORM_DQS6,
EMC_DLL_XFORM_DQS7,
EMC_DLL_XFORM_DQS8,
EMC_DLL_XFORM_DQS9,
EMC_DLL_XFORM_DQS10,
EMC_DLL_XFORM_DQS11,
EMC_DLL_XFORM_DQS12,
EMC_DLL_XFORM_DQS13,
EMC_DLL_XFORM_DQS14,
EMC_DLL_XFORM_DQS15,
EMC_DLL_XFORM_QUSE0,
EMC_DLL_XFORM_QUSE1,
EMC_DLL_XFORM_QUSE2,
EMC_DLL_XFORM_QUSE3,
EMC_DLL_XFORM_QUSE4,
EMC_DLL_XFORM_QUSE5,
EMC_DLL_XFORM_QUSE6,
EMC_DLL_XFORM_QUSE7,
EMC_DLL_XFORM_ADDR0,
EMC_DLL_XFORM_ADDR1,
EMC_DLL_XFORM_ADDR2,
EMC_DLL_XFORM_ADDR3,
EMC_DLL_XFORM_ADDR4,
EMC_DLL_XFORM_ADDR5,
EMC_DLL_XFORM_QUSE8,
EMC_DLL_XFORM_QUSE9,
EMC_DLL_XFORM_QUSE10,
EMC_DLL_XFORM_QUSE11,
EMC_DLL_XFORM_QUSE12,
EMC_DLL_XFORM_QUSE13,
EMC_DLL_XFORM_QUSE14,
EMC_DLL_XFORM_QUSE15,
EMC_DLI_TRIM_TXDQS0,
EMC_DLI_TRIM_TXDQS1,
EMC_DLI_TRIM_TXDQS2,
EMC_DLI_TRIM_TXDQS3,
EMC_DLI_TRIM_TXDQS4,
EMC_DLI_TRIM_TXDQS5,
EMC_DLI_TRIM_TXDQS6,
EMC_DLI_TRIM_TXDQS7,
EMC_DLI_TRIM_TXDQS8,
EMC_DLI_TRIM_TXDQS9,
EMC_DLI_TRIM_TXDQS10,
EMC_DLI_TRIM_TXDQS11,
EMC_DLI_TRIM_TXDQS12,
EMC_DLI_TRIM_TXDQS13,
EMC_DLI_TRIM_TXDQS14,
EMC_DLI_TRIM_TXDQS15,
EMC_DLL_XFORM_DQ0,
EMC_DLL_XFORM_DQ1,
EMC_DLL_XFORM_DQ2,
EMC_DLL_XFORM_DQ3,
EMC_DLL_XFORM_DQ4,
EMC_DLL_XFORM_DQ5,
EMC_DLL_XFORM_DQ6,
EMC_DLL_XFORM_DQ7,
EMC_XM2CMDPADCTRL,
EMC_XM2CMDPADCTRL4,
EMC_XM2CMDPADCTRL5,
EMC_XM2DQPADCTRL2,
EMC_XM2DQPADCTRL3,
EMC_XM2CLKPADCTRL,
EMC_XM2CLKPADCTRL2,
EMC_XM2COMPPADCTRL,
EMC_XM2VTTGENPADCTRL,
EMC_XM2VTTGENPADCTRL2,
EMC_XM2VTTGENPADCTRL3,
EMC_XM2DQSPADCTRL3,
EMC_XM2DQSPADCTRL4,
EMC_XM2DQSPADCTRL5,
EMC_XM2DQSPADCTRL6,
EMC_DSR_VTTGEN_DRV,
EMC_TXDSRVTTGEN,
EMC_FBIO_SPARE,
EMC_ZCAL_WAIT_CNT,
EMC_MRS_WAIT_CNT2,
EMC_CTT,
EMC_CTT_DURATION,
EMC_CFG_PIPE,
EMC_DYN_SELF_REF_CONTROL,
EMC_QPOP
};
struct emc_timing {
unsigned long rate;
u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
u32 emc_auto_cal_config;
u32 emc_auto_cal_config2;
u32 emc_auto_cal_config3;
u32 emc_auto_cal_interval;
u32 emc_bgbias_ctl0;
u32 emc_cfg;
u32 emc_cfg_2;
u32 emc_ctt_term_ctrl;
u32 emc_mode_1;
u32 emc_mode_2;
u32 emc_mode_4;
u32 emc_mode_reset;
u32 emc_mrs_wait_cnt;
u32 emc_sel_dpd_ctrl;
u32 emc_xm2dqspadctrl2;
u32 emc_zcal_cnt_long;
u32 emc_zcal_interval;
};
enum emc_rate_request_type {
EMC_RATE_DEBUG,
EMC_RATE_ICC,
EMC_RATE_TYPE_MAX,
};
struct emc_rate_request {
unsigned long min_rate;
unsigned long max_rate;
};
struct tegra_emc {
struct device *dev;
struct tegra_mc *mc;
void __iomem *regs;
struct clk *clk;
enum emc_dram_type dram_type;
unsigned int dram_bus_width;
unsigned int dram_num;
struct emc_timing last_timing;
struct emc_timing *timings;
unsigned int num_timings;
struct {
struct dentry *root;
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
struct icc_provider provider;
/*
* There are multiple sources in the EMC driver which could request
* a min/max clock rate, these rates are contained in this array.
*/
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
/* protect shared rate-change code path */
struct mutex rate_lock;
};
/* Timing change sequence functions */
static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
unsigned long offset)
{
writel(value, emc->regs + EMC_CCFIFO_DATA);
writel(offset, emc->regs + EMC_CCFIFO_ADDR);
}
static void emc_seq_update_timing(struct tegra_emc *emc)
{
unsigned int i;
u32 value;
writel(1, emc->regs + EMC_TIMING_CONTROL);
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
value = readl(emc->regs + EMC_STATUS);
if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
return;
udelay(1);
}
dev_err(emc->dev, "timing update timed out\n");
}
static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
{
unsigned int i;
u32 value;
writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
return;
udelay(1);
}
dev_err(emc->dev, "auto cal disable timed out\n");
}
static void emc_seq_wait_clkchange(struct tegra_emc *emc)
{
unsigned int i;
u32 value;
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
value = readl(emc->regs + EMC_INTSTATUS);
if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
return;
udelay(1);
}
dev_err(emc->dev, "clock change timed out\n");
}
static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = NULL;
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate == rate) {
timing = &emc->timings[i];
break;
}
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu\n", rate);
return NULL;
}
return timing;
}
static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
struct emc_timing *last = &emc->last_timing;
enum emc_dll_change dll_change;
unsigned int pre_wait = 0;
u32 val, val2, mask;
bool update = false;
unsigned int i;
if (!timing)
return -ENOENT;
if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
dll_change = DLL_CHANGE_NONE;
else if (timing->emc_mode_1 & 0x1)
dll_change = DLL_CHANGE_ON;
else
dll_change = DLL_CHANGE_OFF;
/* Clear CLKCHANGE_COMPLETE interrupts */
writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
/* Disable dynamic self-refresh */
val = readl(emc->regs + EMC_CFG);
if (val & EMC_CFG_PWR_MASK) {
val &= ~EMC_CFG_POWER_FEATURES_MASK;
writel(val, emc->regs + EMC_CFG);
pre_wait = 5;
}
/* Disable SEL_DPD_CTRL for clock change */
if (emc->dram_type == DRAM_TYPE_DDR3)
mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
else
mask = EMC_SEL_DPD_CTRL_MASK;
val = readl(emc->regs + EMC_SEL_DPD_CTRL);
if (val & mask) {
val &= ~mask;
writel(val, emc->regs + EMC_SEL_DPD_CTRL);
}
/* Prepare DQ/DQS for clock change */
val = readl(emc->regs + EMC_BGBIAS_CTL0);
val2 = last->emc_bgbias_ctl0;
if (!(timing->emc_bgbias_ctl0 &
EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
(val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
update = true;
}
if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
(val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
update = true;
}
if (update) {
writel(val2, emc->regs + EMC_BGBIAS_CTL0);
if (pre_wait < 5)
pre_wait = 5;
}
update = false;
val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
update = true;
}
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
!(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
update = true;
}
if (update) {
writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
if (pre_wait < 30)
pre_wait = 30;
}
/* Wait to settle */
if (pre_wait) {
emc_seq_update_timing(emc);
udelay(pre_wait);
}
/* Program CTT_TERM control */
if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
emc_seq_disable_auto_cal(emc);
writel(timing->emc_ctt_term_ctrl,
emc->regs + EMC_CTT_TERM_CTRL);
emc_seq_update_timing(emc);
}
/* Program burst shadow registers */
for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
writel(timing->emc_burst_data[i],
emc->regs + emc_burst_regs[i]);
writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
tegra_mc_write_emem_configuration(emc->mc, timing->rate);
val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
emc_ccfifo_writel(emc, val, EMC_CFG);
/* Program AUTO_CAL_CONFIG */
if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
EMC_AUTO_CAL_CONFIG2);
if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
EMC_AUTO_CAL_CONFIG3);
if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
val = timing->emc_auto_cal_config;
val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
}
/* DDR3: predict MRS long wait count */
if (emc->dram_type == DRAM_TYPE_DDR3 &&
dll_change == DLL_CHANGE_ON) {
u32 cnt = 512;
if (timing->emc_zcal_interval != 0 &&
last->emc_zcal_interval == 0)
cnt -= emc->dram_num * 256;
val = (timing->emc_mrs_wait_cnt
& EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
>> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
if (cnt < val)
cnt = val;
val = timing->emc_mrs_wait_cnt
& ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
& EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
writel(val, emc->regs + EMC_MRS_WAIT_CNT);
}
val = timing->emc_cfg_2;
val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
emc_ccfifo_writel(emc, val, EMC_CFG_2);
/* DDR3: Turn off DLL and enter self-refresh */
if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
/* Disable refresh controller */
emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
EMC_REFCTRL);
if (emc->dram_type == DRAM_TYPE_DDR3)
emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
EMC_SELF_REF_CMD_ENABLED,
EMC_SELF_REF);
/* Flow control marker */
emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
/* DDR3: Exit self-refresh */
if (emc->dram_type == DRAM_TYPE_DDR3)
emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
EMC_SELF_REF);
emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
EMC_REFCTRL_ENABLE,
EMC_REFCTRL);
/* Set DRAM mode registers */
if (emc->dram_type == DRAM_TYPE_DDR3) {
if (timing->emc_mode_1 != last->emc_mode_1)
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
if (timing->emc_mode_2 != last->emc_mode_2)
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
if ((timing->emc_mode_reset != last->emc_mode_reset) ||
dll_change == DLL_CHANGE_ON) {
val = timing->emc_mode_reset;
if (dll_change == DLL_CHANGE_ON) {
val |= EMC_MODE_SET_DLL_RESET;
val |= EMC_MODE_SET_LONG_CNT;
} else {
val &= ~EMC_MODE_SET_DLL_RESET;
}
emc_ccfifo_writel(emc, val, EMC_MRS);
}
} else {
if (timing->emc_mode_2 != last->emc_mode_2)
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
if (timing->emc_mode_1 != last->emc_mode_1)
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
if (timing->emc_mode_4 != last->emc_mode_4)
emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
}
/* Issue ZCAL command if turning ZCAL on */
if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
if (emc->dram_num > 1)
emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
EMC_ZQ_CAL);
}
/* Write to RO register to remove stall after change */
emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
/* Disable AUTO_CAL for clock change */
emc_seq_disable_auto_cal(emc);
/* Read register to wait until programming has settled */
readl(emc->regs + EMC_INTSTATUS);
return 0;
}
static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
struct emc_timing *last = &emc->last_timing;
u32 val;
if (!timing)
return;
/* Wait until the state machine has settled */
emc_seq_wait_clkchange(emc);
/* Restore AUTO_CAL */
if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
writel(timing->emc_auto_cal_interval,
emc->regs + EMC_AUTO_CAL_INTERVAL);
/* Restore dynamic self-refresh */
if (timing->emc_cfg & EMC_CFG_PWR_MASK)
writel(timing->emc_cfg, emc->regs + EMC_CFG);
/* Set ZCAL wait count */
writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
/* LPDDR3: Turn off BGBIAS if low frequency */
if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
timing->emc_bgbias_ctl0 &
EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
val = timing->emc_bgbias_ctl0;
val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
writel(val, emc->regs + EMC_BGBIAS_CTL0);
} else {
if (emc->dram_type == DRAM_TYPE_DDR3 &&
readl(emc->regs + EMC_BGBIAS_CTL0) !=
timing->emc_bgbias_ctl0) {
writel(timing->emc_bgbias_ctl0,
emc->regs + EMC_BGBIAS_CTL0);
}
writel(timing->emc_auto_cal_interval,
emc->regs + EMC_AUTO_CAL_INTERVAL);
}
/* Wait for timing to settle */
udelay(2);
/* Reprogram SEL_DPD_CTRL */
writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
emc_seq_update_timing(emc);
emc->last_timing = *timing;
}
/* Initialization and deinitialization */
static void emc_read_current_timing(struct tegra_emc *emc,
struct emc_timing *timing)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
timing->emc_burst_data[i] =
readl(emc->regs + emc_burst_regs[i]);
timing->emc_cfg = readl(emc->regs + EMC_CFG);
timing->emc_auto_cal_interval = 0;
timing->emc_zcal_cnt_long = 0;
timing->emc_mode_1 = 0;
timing->emc_mode_2 = 0;
timing->emc_mode_4 = 0;
timing->emc_mode_reset = 0;
}
static int emc_init(struct tegra_emc *emc)
{
emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64)
emc->dram_bus_width = 64;
else
emc->dram_bus_width = 32;
dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
emc_read_current_timing(emc, &emc->last_timing);
return 0;
}
static int load_one_timing_from_dt(struct tegra_emc *emc,
struct emc_timing *timing,
struct device_node *node)
{
u32 value;
int err;
err = of_property_read_u32(node, "clock-frequency", &value);
if (err) {
dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
node, err);
return err;
}
timing->rate = value;
err = of_property_read_u32_array(node, "nvidia,emc-configuration",
timing->emc_burst_data,
ARRAY_SIZE(timing->emc_burst_data));
if (err) {
dev_err(emc->dev,
"timing %pOFn: failed to read emc burst data: %d\n",
node, err);
return err;
}
#define EMC_READ_PROP(prop, dtprop) { \
err = of_property_read_u32(node, dtprop, &timing->prop); \
if (err) { \
dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
node, err); \
return err; \
} \
}
EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
#undef EMC_READ_PROP
return 0;
}
static int cmp_timings(const void *_a, const void *_b)
{
const struct emc_timing *a = _a;
const struct emc_timing *b = _b;
if (a->rate < b->rate)
return -1;
else if (a->rate == b->rate)
return 0;
else
return 1;
}
static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
struct device_node *node)
{
int child_count = of_get_child_count(node);
struct emc_timing *timing;
unsigned int i = 0;
int err;
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
GFP_KERNEL);
if (!emc->timings)
return -ENOMEM;
emc->num_timings = child_count;
for_each_child_of_node_scoped(node, child) {
timing = &emc->timings[i++];
err = load_one_timing_from_dt(emc, timing, child);
if (err)
return err;
}
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
NULL);
return 0;
}
static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra124-emc" },
{ .compatible = "nvidia,tegra132-emc" },
{}
};
MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct device_node *
tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
{
struct device_node *np;
int err;
for_each_child_of_node(node, np) {
u32 value;
err = of_property_read_u32(np, "nvidia,ram-code", &value);
if (err || (value != ram_code))
continue;
return np;
}
return NULL;
}
static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
{
unsigned int i;
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
emc->requested_rate[i].min_rate = 0;
emc->requested_rate[i].max_rate = ULONG_MAX;
}
}
static int emc_request_rate(struct tegra_emc *emc,
unsigned long new_min_rate,
unsigned long new_max_rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = emc->requested_rate;
unsigned long min_rate = 0, max_rate = ULONG_MAX;
unsigned int i;
int err;
/* select minimum and maximum rates among the requested rates */
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
if (i == type) {
min_rate = max(new_min_rate, min_rate);
max_rate = min(new_max_rate, max_rate);
} else {
min_rate = max(req->min_rate, min_rate);
max_rate = min(req->max_rate, max_rate);
}
}
if (min_rate > max_rate) {
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
__func__, type, min_rate, max_rate);
return -ERANGE;
}
/*
* EMC rate-changes should go via OPP API because it manages voltage
* changes.
*/
err = dev_pm_opp_set_rate(emc->dev, min_rate);
if (err)
return err;
emc->requested_rate[type].min_rate = new_min_rate;
emc->requested_rate[type].max_rate = new_max_rate;
return 0;
}
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, rate, req->max_rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, req->min_rate, rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
/*
* debugfs interface
*
* The memory controller driver exposes some files in debugfs that can be used
* to control the EMC frequency. The top-level directory can be found here:
*
* /sys/kernel/debug/emc
*
* It contains the following files:
*
* - available_rates: This file contains a list of valid, space-separated
* EMC frequencies.
*
* - min_rate: Writing a value to this file sets the given frequency as the
* floor of the permitted range. If this is higher than the currently
* configured EMC frequency, this will cause the frequency to be
* increased so that it stays within the valid range.
*
* - max_rate: Similarily to the min_rate file, writing a value to this file
* sets the given frequency as the ceiling of the permitted range. If
* the value is lower than the currently configured EMC frequency, this
* will cause the frequency to be decreased so that it stays within the
* valid range.
*/
static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (rate == emc->timings[i].rate)
return true;
return false;
}
static int tegra_emc_debug_available_rates_show(struct seq_file *s,
void *data)
{
struct tegra_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.min_rate;
return 0;
}
static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.min_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
tegra_emc_debug_min_rate_get,
tegra_emc_debug_min_rate_set, "%llu\n");
static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.max_rate;
return 0;
}
static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.max_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
tegra_emc_debug_max_rate_get,
tegra_emc_debug_max_rate_set, "%llu\n");
static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
{
unsigned int i;
int err;
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->timings[i].rate;
if (emc->timings[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->timings[i].rate;
}
if (!emc->num_timings) {
emc->debugfs.min_rate = clk_get_rate(emc->clk);
emc->debugfs.max_rate = emc->debugfs.min_rate;
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
emc->debugfs.max_rate);
if (err < 0) {
dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate,
emc->clk);
return;
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_max_rate_fops);
}
static inline struct tegra_emc *
to_tegra_emc_provider(struct icc_provider *provider)
{
return container_of(provider, struct tegra_emc, provider);
}
static struct icc_node_data *
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
{
struct icc_provider *provider = data;
struct icc_node_data *ndata;
struct icc_node *node;
/* External Memory is the only possible ICC route */
list_for_each_entry(node, &provider->nodes, node_list) {
if (node->id != TEGRA_ICC_EMEM)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
/*
* SRC and DST nodes should have matching TAG in order to have
* it set by default for a requested path.
*/
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
ndata->node = node;
return ndata;
}
return ERR_PTR(-EPROBE_DEFER);
}
static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
unsigned long long rate = max(avg_bw, peak_bw);
unsigned int dram_data_bus_width_bytes;
const unsigned int ddr = 2;
int err;
/*
* Tegra124 EMC runs on a clock rate of SDRAM bus. This means that
* EMC clock rate is twice smaller than the peak data rate because
* data is sampled on both EMC clock edges.
*/
dram_data_bus_width_bytes = emc->dram_bus_width / 8;
do_div(rate, ddr * dram_data_bus_width_bytes);
rate = min_t(u64, rate, U32_MAX);
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
if (err)
return err;
return 0;
}
static int tegra_emc_interconnect_init(struct tegra_emc *emc)
{
const struct tegra_mc_soc *soc = emc->mc->soc;
struct icc_node *node;
int err;
emc->provider.dev = emc->dev;
emc->provider.set = emc_icc_set;
emc->provider.data = &emc->provider;
emc->provider.aggregate = soc->icc_ops->aggregate;
emc->provider.xlate_extended = emc_of_icc_xlate_extended;
icc_provider_init(&emc->provider);
/* create External Memory Controller node */
node = icc_node_create(TEGRA_ICC_EMC);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto err_msg;
}
node->name = "External Memory Controller";
icc_node_add(node, &emc->provider);
/* link External Memory Controller to External Memory (DRAM) */
err = icc_link_create(node, TEGRA_ICC_EMEM);
if (err)
goto remove_nodes;
/* create External Memory node */
node = icc_node_create(TEGRA_ICC_EMEM);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto remove_nodes;
}
node->name = "External Memory (DRAM)";
icc_node_add(node, &emc->provider);
err = icc_provider_register(&emc->provider);
if (err)
goto remove_nodes;
return 0;
remove_nodes:
icc_nodes_remove(&emc->provider);
err_msg:
dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
return err;
}
static int tegra_emc_opp_table_init(struct tegra_emc *emc)
{
u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
int opp_token, err;
err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
if (err < 0) {
dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
return err;
}
opp_token = err;
err = dev_pm_opp_of_add_table(emc->dev);
if (err) {
if (err == -ENODEV)
dev_err(emc->dev, "OPP table not found, please update your device tree\n");
else
dev_err(emc->dev, "failed to add OPP table: %d\n", err);
goto put_hw_table;
}
dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
hw_version, clk_get_rate(emc->clk) / 1000000);
/* first dummy rate-set initializes voltage state */
err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
if (err) {
dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
goto remove_table;
}
return 0;
remove_table:
dev_pm_opp_of_remove_table(emc->dev);
put_hw_table:
dev_pm_opp_put_supported_hw(opp_token);
return err;
}
static void devm_tegra_emc_unset_callback(void *data)
{
tegra124_clk_set_emc_callbacks(NULL, NULL);
}
static int tegra_emc_probe(struct platform_device *pdev)
{
struct device_node *np;
struct tegra_emc *emc;
u32 ram_code;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
if (!emc)
return -ENOMEM;
mutex_init(&emc->rate_lock);
emc->dev = &pdev->dev;
emc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emc->regs))
return PTR_ERR(emc->regs);
emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
if (IS_ERR(emc->mc))
return PTR_ERR(emc->mc);
ram_code = tegra_read_ram_code();
np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
if (np) {
err = tegra_emc_load_timings_from_dt(emc, np);
of_node_put(np);
if (err)
return err;
} else {
dev_info_once(&pdev->dev,
"no memory timings for RAM code %u found in DT\n",
ram_code);
}
err = emc_init(emc);
if (err) {
dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
return err;
}
platform_set_drvdata(pdev, emc);
tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change,
tegra_emc_complete_timing_change);
err = devm_add_action_or_reset(&pdev->dev, devm_tegra_emc_unset_callback,
NULL);
if (err)
return err;
emc->clk = devm_clk_get(&pdev->dev, "emc");
if (IS_ERR(emc->clk)) {
err = PTR_ERR(emc->clk);
dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
return err;
}
err = tegra_emc_opp_table_init(emc);
if (err)
return err;
tegra_emc_rate_requests_init(emc);
if (IS_ENABLED(CONFIG_DEBUG_FS))
emc_debugfs_init(&pdev->dev, emc);
tegra_emc_interconnect_init(emc);
/*
* Don't allow the kernel module to be unloaded. Unloading adds some
* extra complexity which doesn't really worth the effort in a case of
* this driver.
*/
try_module_get(THIS_MODULE);
return 0;
};
static struct platform_driver tegra_emc_driver = {
.probe = tegra_emc_probe,
.driver = {
.name = "tegra-emc",
.of_match_table = tegra_emc_of_match,
.suppress_bind_attrs = true,
.sync_state = icc_sync_state,
},
};
module_platform_driver(tegra_emc_driver);
MODULE_AUTHOR("Mikko Perttunen <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver");
MODULE_LICENSE("GPL v2");
|
// SPDX-License-Identifier: GPL-2.0+
/*
* OWL SoC's Pinctrl driver
*
* Copyright (c) 2014 Actions Semi Inc.
* Author: David Liu <[email protected]>
*
* Copyright (c) 2018 Linaro Ltd.
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-owl.h"
/**
* struct owl_pinctrl - pinctrl state of the device
* @dev: device handle
* @pctrldev: pinctrl handle
* @chip: gpio chip
* @lock: spinlock to protect registers
* @clk: clock control
* @soc: reference to soc_data
* @base: pinctrl register base address
* @num_irq: number of possible interrupts
* @irq: interrupt numbers
*/
struct owl_pinctrl {
struct device *dev;
struct pinctrl_dev *pctrldev;
struct gpio_chip chip;
raw_spinlock_t lock;
struct clk *clk;
const struct owl_pinctrl_soc_data *soc;
void __iomem *base;
unsigned int num_irq;
unsigned int *irq;
};
static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
{
u32 reg_val;
reg_val = readl_relaxed(base);
reg_val = (reg_val & ~mask) | (val & mask);
writel_relaxed(reg_val, base);
}
static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
u32 bit, u32 width)
{
u32 tmp, mask;
tmp = readl_relaxed(pctrl->base + reg);
mask = (1 << width) - 1;
return (tmp >> bit) & mask;
}
static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
u32 bit, u32 width)
{
u32 mask;
mask = (1 << width) - 1;
mask = mask << bit;
owl_update_bits(pctrl->base + reg, mask, (arg << bit));
}
static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->ngroups;
}
static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
unsigned int group)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->groups[group].name;
}
static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
*pins = pctrl->soc->groups[group].pads;
*num_pins = pctrl->soc->groups[group].npads;
return 0;
}
static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
struct seq_file *s,
unsigned int offset)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
seq_printf(s, "%s", dev_name(pctrl->dev));
}
static const struct pinctrl_ops owl_pinctrl_ops = {
.get_groups_count = owl_get_groups_count,
.get_group_name = owl_get_group_name,
.get_group_pins = owl_get_group_pins,
.pin_dbg_show = owl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->nfunctions;
}
static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
unsigned int function)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->functions[function].name;
}
static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
*groups = pctrl->soc->functions[function].groups;
*num_groups = pctrl->soc->functions[function].ngroups;
return 0;
}
static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
int function,
u32 *mask,
u32 *val)
{
int id;
u32 option_num;
u32 option_mask;
for (id = 0; id < g->nfuncs; id++) {
if (g->funcs[id] == function)
break;
}
if (WARN_ON(id == g->nfuncs))
return -EINVAL;
option_num = (1 << g->mfpctl_width);
if (id > option_num)
id -= option_num;
option_mask = option_num - 1;
*mask = (option_mask << g->mfpctl_shift);
*val = (id << g->mfpctl_shift);
return 0;
}
static int owl_set_mux(struct pinctrl_dev *pctrldev,
unsigned int function,
unsigned int group)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
const struct owl_pingroup *g;
unsigned long flags;
u32 val, mask;
g = &pctrl->soc->groups[group];
if (get_group_mfp_mask_val(g, function, &mask, &val))
return -EINVAL;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static const struct pinmux_ops owl_pinmux_ops = {
.get_functions_count = owl_get_funcs_count,
.get_function_name = owl_get_func_name,
.get_function_groups = owl_get_func_groups,
.set_mux = owl_set_mux,
};
static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
unsigned int param,
u32 *reg,
u32 *bit,
u32 *width)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
if (!info->pullctl)
return -EINVAL;
*reg = info->pullctl->reg;
*bit = info->pullctl->shift;
*width = info->pullctl->width;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!info->st)
return -EINVAL;
*reg = info->st->reg;
*bit = info->st->shift;
*width = info->st->width;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *config)
{
int ret = 0;
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
const struct owl_padinfo *info;
unsigned int param = pinconf_to_config_param(*config);
u32 reg, bit, width, arg;
info = &pctrl->soc->padinfo[pin];
ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
if (ret)
return ret;
arg = owl_read_field(pctrl, reg, bit, width);
if (!pctrl->soc->padctl_val2arg)
return -ENOTSUPP;
ret = pctrl->soc->padctl_val2arg(info, param, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return ret;
}
static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *configs,
unsigned int num_configs)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
const struct owl_padinfo *info;
unsigned long flags;
unsigned int param;
u32 reg, bit, width, arg;
int ret = 0, i;
info = &pctrl->soc->padinfo[pin];
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
if (ret)
return ret;
if (!pctrl->soc->padctl_arg2val)
return -ENOTSUPP;
ret = pctrl->soc->padctl_arg2val(info, param, &arg);
if (ret)
return ret;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_write_field(pctrl, reg, arg, bit, width);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
return ret;
}
static int owl_group_pinconf_reg(const struct owl_pingroup *g,
unsigned int param,
u32 *reg,
u32 *bit,
u32 *width)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
if (g->drv_reg < 0)
return -EINVAL;
*reg = g->drv_reg;
*bit = g->drv_shift;
*width = g->drv_width;
break;
case PIN_CONFIG_SLEW_RATE:
if (g->sr_reg < 0)
return -EINVAL;
*reg = g->sr_reg;
*bit = g->sr_shift;
*width = g->sr_width;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
switch (*arg) {
case 2:
*arg = OWL_PINCONF_DRV_2MA;
break;
case 4:
*arg = OWL_PINCONF_DRV_4MA;
break;
case 8:
*arg = OWL_PINCONF_DRV_8MA;
break;
case 12:
*arg = OWL_PINCONF_DRV_12MA;
break;
default:
return -EINVAL;
}
break;
case PIN_CONFIG_SLEW_RATE:
if (*arg)
*arg = OWL_PINCONF_SLEW_FAST;
else
*arg = OWL_PINCONF_SLEW_SLOW;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
switch (*arg) {
case OWL_PINCONF_DRV_2MA:
*arg = 2;
break;
case OWL_PINCONF_DRV_4MA:
*arg = 4;
break;
case OWL_PINCONF_DRV_8MA:
*arg = 8;
break;
case OWL_PINCONF_DRV_12MA:
*arg = 12;
break;
default:
return -EINVAL;
}
break;
case PIN_CONFIG_SLEW_RATE:
if (*arg)
*arg = 1;
else
*arg = 0;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_group_config_get(struct pinctrl_dev *pctrldev,
unsigned int group,
unsigned long *config)
{
const struct owl_pingroup *g;
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
unsigned int param = pinconf_to_config_param(*config);
u32 reg, bit, width, arg;
int ret;
g = &pctrl->soc->groups[group];
ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
if (ret)
return ret;
arg = owl_read_field(pctrl, reg, bit, width);
ret = owl_group_pinconf_val2arg(g, param, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return ret;
}
static int owl_group_config_set(struct pinctrl_dev *pctrldev,
unsigned int group,
unsigned long *configs,
unsigned int num_configs)
{
const struct owl_pingroup *g;
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
unsigned long flags;
unsigned int param;
u32 reg, bit, width, arg;
int ret, i;
g = &pctrl->soc->groups[group];
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
if (ret)
return ret;
ret = owl_group_pinconf_arg2val(g, param, &arg);
if (ret)
return ret;
/* Update register */
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_write_field(pctrl, reg, arg, bit, width);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
return 0;
}
static const struct pinconf_ops owl_pinconf_ops = {
.is_generic = true,
.pin_config_get = owl_pin_config_get,
.pin_config_set = owl_pin_config_set,
.pin_config_group_get = owl_group_config_get,
.pin_config_group_set = owl_group_config_set,
};
static struct pinctrl_desc owl_pinctrl_desc = {
.pctlops = &owl_pinctrl_ops,
.pmxops = &owl_pinmux_ops,
.confops = &owl_pinconf_ops,
.owner = THIS_MODULE,
};
static const struct owl_gpio_port *
owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
{
unsigned int start = 0, i;
for (i = 0; i < pctrl->soc->nports; i++) {
const struct owl_gpio_port *port = &pctrl->soc->ports[i];
if (*pin >= start && *pin < start + port->pins) {
*pin -= start;
return port;
}
start += port->pins;
}
return NULL;
}
static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
{
u32 val;
val = readl_relaxed(base);
if (flag)
val |= BIT(pin);
else
val &= ~BIT(pin);
writel_relaxed(val, base);
}
static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
/*
* GPIOs have higher priority over other modules, so either setting
* them as OUT or IN is sufficient
*/
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->outen, offset, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* disable gpio output */
owl_gpio_update_reg(gpio_base + port->outen, offset, false);
/* disable gpio input */
owl_gpio_update_reg(gpio_base + port->inen, offset, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
u32 val;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
val = readl_relaxed(gpio_base + port->dat);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return !!(val & BIT(offset));
}
static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->dat, offset, value);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->outen, offset, false);
owl_gpio_update_reg(gpio_base + port->inen, offset, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static int owl_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->inen, offset, false);
owl_gpio_update_reg(gpio_base + port->outen, offset, true);
owl_gpio_update_reg(gpio_base + port->dat, offset, value);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
{
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
unsigned int offset, value, irq_type = 0;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
/*
* Since the hardware doesn't support interrupts on both edges,
* emulate it in the software by setting the single edge
* interrupt and switching to the opposite edge while ACKing
* the interrupt
*/
if (owl_gpio_get(&pctrl->chip, gpio))
irq_type = OWL_GPIO_INT_EDGE_FALLING;
else
irq_type = OWL_GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_RISING:
irq_type = OWL_GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
irq_type = OWL_GPIO_INT_EDGE_FALLING;
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_type = OWL_GPIO_INT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
irq_type = OWL_GPIO_INT_LEVEL_LOW;
break;
default:
break;
}
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
offset = (gpio < 16) ? 4 : 0;
value = readl_relaxed(gpio_base + port->intc_type + offset);
value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
value |= irq_type << ((gpio % 16) * 2);
writel_relaxed(value, gpio_base + port->intc_type + offset);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
const struct owl_gpio_port *port;
unsigned int gpio = hwirq;
void __iomem *gpio_base;
unsigned long flags;
u32 val;
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
/* disable port interrupt if no interrupt pending bit is active */
val = readl_relaxed(gpio_base + port->intc_msk);
if (val == 0)
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
gpiochip_disable_irq(gc, hwirq);
}
static void owl_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
const struct owl_gpio_port *port;
unsigned int gpio = hwirq;
void __iomem *gpio_base;
unsigned long flags;
u32 value;
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpiochip_enable_irq(gc, hwirq);
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* enable port interrupt */
value = readl_relaxed(gpio_base + port->intc_ctl);
value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
<< port->shared_ctl_offset * 5);
writel_relaxed(value, gpio_base + port->intc_ctl);
/* enable GPIO interrupt */
owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
const struct owl_gpio_port *port;
unsigned int gpio = hwirq;
void __iomem *gpio_base;
unsigned long flags;
/*
* Switch the interrupt edge to the opposite edge of the interrupt
* which got triggered for the case of emulating both edges
*/
if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
if (owl_gpio_get(gc, hwirq))
irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING);
else
irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING);
}
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
irq_set_handler_locked(data, handle_level_irq);
else
irq_set_handler_locked(data, handle_edge_irq);
irq_set_type(pctrl, data->hwirq, type);
return 0;
}
static const struct irq_chip owl_gpio_irqchip = {
.name = "owl-irq",
.irq_ack = owl_gpio_irq_ack,
.irq_mask = owl_gpio_irq_mask,
.irq_unmask = owl_gpio_irq_unmask,
.irq_set_type = owl_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void owl_gpio_irq_handler(struct irq_desc *desc)
{
struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *domain = pctrl->chip.irq.domain;
unsigned int parent = irq_desc_get_irq(desc);
const struct owl_gpio_port *port;
void __iomem *base;
unsigned int pin, offset = 0, i;
unsigned long pending_irq;
chained_irq_enter(chip, desc);
for (i = 0; i < pctrl->soc->nports; i++) {
port = &pctrl->soc->ports[i];
base = pctrl->base + port->offset;
/* skip ports that are not associated with this irq */
if (parent != pctrl->irq[i])
goto skip;
pending_irq = readl_relaxed(base + port->intc_pd);
for_each_set_bit(pin, &pending_irq, port->pins) {
generic_handle_domain_irq(domain, offset + pin);
/* clear pending interrupt */
owl_gpio_update_reg(base + port->intc_pd, pin, true);
}
skip:
offset += port->pins;
}
chained_irq_exit(chip, desc);
}
static int owl_gpio_init(struct owl_pinctrl *pctrl)
{
struct gpio_chip *chip;
struct gpio_irq_chip *gpio_irq;
int ret, i, j, offset;
chip = &pctrl->chip;
chip->base = -1;
chip->ngpio = pctrl->soc->ngpios;
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;
gpio_irq = &chip->irq;
gpio_irq_chip_set_chip(gpio_irq, &owl_gpio_irqchip);
gpio_irq->handler = handle_simple_irq;
gpio_irq->default_type = IRQ_TYPE_NONE;
gpio_irq->parent_handler = owl_gpio_irq_handler;
gpio_irq->parent_handler_data = pctrl;
gpio_irq->num_parents = pctrl->num_irq;
gpio_irq->parents = pctrl->irq;
gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
sizeof(*gpio_irq->map), GFP_KERNEL);
if (!gpio_irq->map)
return -ENOMEM;
for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
const struct owl_gpio_port *port = &pctrl->soc->ports[i];
for (j = 0; j < port->pins; j++)
gpio_irq->map[offset + j] = gpio_irq->parents[i];
offset += port->pins;
}
ret = gpiochip_add_data(&pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to register gpiochip\n");
return ret;
}
return 0;
}
int owl_pinctrl_probe(struct platform_device *pdev,
struct owl_pinctrl_soc_data *soc_data)
{
struct owl_pinctrl *pctrl;
int ret, i;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->base))
return PTR_ERR(pctrl->base);
/* enable GPIO/MFP clock */
pctrl->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pctrl->clk)) {
dev_err(&pdev->dev, "no clock defined\n");
return PTR_ERR(pctrl->clk);
}
ret = clk_prepare_enable(pctrl->clk);
if (ret) {
dev_err(&pdev->dev, "clk enable failed\n");
return ret;
}
raw_spin_lock_init(&pctrl->lock);
owl_pinctrl_desc.name = dev_name(&pdev->dev);
owl_pinctrl_desc.pins = soc_data->pins;
owl_pinctrl_desc.npins = soc_data->npins;
pctrl->chip.direction_input = owl_gpio_direction_input;
pctrl->chip.direction_output = owl_gpio_direction_output;
pctrl->chip.get = owl_gpio_get;
pctrl->chip.set = owl_gpio_set;
pctrl->chip.request = owl_gpio_request;
pctrl->chip.free = owl_gpio_free;
pctrl->soc = soc_data;
pctrl->dev = &pdev->dev;
pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
&owl_pinctrl_desc, pctrl);
if (IS_ERR(pctrl->pctrldev)) {
dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
ret = PTR_ERR(pctrl->pctrldev);
goto err_exit;
}
ret = platform_irq_count(pdev);
if (ret < 0)
goto err_exit;
pctrl->num_irq = ret;
pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
sizeof(*pctrl->irq), GFP_KERNEL);
if (!pctrl->irq) {
ret = -ENOMEM;
goto err_exit;
}
for (i = 0; i < pctrl->num_irq ; i++) {
ret = platform_get_irq(pdev, i);
if (ret < 0)
goto err_exit;
pctrl->irq[i] = ret;
}
ret = owl_gpio_init(pctrl);
if (ret)
goto err_exit;
platform_set_drvdata(pdev, pctrl);
return 0;
err_exit:
clk_disable_unprepare(pctrl->clk);
return ret;
}
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __HID_LG4FF_H
#define __HID_LG4FF_H
#ifdef CONFIG_LOGIWHEELS_FF
extern int lg4ff_no_autoswitch; /* From hid-lg.c */
int lg4ff_adjust_input_event(struct hid_device *hid, struct hid_field *field,
struct hid_usage *usage, s32 value, struct lg_drv_data *drv_data);
int lg4ff_raw_event(struct hid_device *hdev, struct hid_report *report,
u8 *rd, int size, struct lg_drv_data *drv_data);
int lg4ff_init(struct hid_device *hdev);
int lg4ff_deinit(struct hid_device *hdev);
#else
static inline int lg4ff_adjust_input_event(struct hid_device *hid, struct hid_field *field,
struct hid_usage *usage, s32 value, struct lg_drv_data *drv_data) { return 0; }
static inline int lg4ff_raw_event(struct hid_device *hdev, struct hid_report *report,
u8 *rd, int size, struct lg_drv_data *drv_data) { return 0; }
static inline int lg4ff_init(struct hid_device *hdev) { return -1; }
static inline int lg4ff_deinit(struct hid_device *hdev) { return -1; }
#endif
#endif
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* rt700.h -- RT700 ALSA SoC audio driver header
*
* Copyright(c) 2019 Realtek Semiconductor Corp.
*/
#ifndef __RT700_H__
#define __RT700_H__
extern const struct dev_pm_ops rt700_runtime_pm;
struct rt700_priv {
struct snd_soc_component *component;
struct regmap *regmap;
struct regmap *sdw_regmap;
struct sdw_slave *slave;
struct sdw_bus_params params;
bool hw_init;
bool first_hw_init;
struct snd_soc_jack *hs_jack;
struct delayed_work jack_detect_work;
struct delayed_work jack_btn_check_work;
int jack_type;
struct mutex disable_irq_lock; /* imp-def irq lock protection */
bool disable_irq;
};
/* NID */
#define RT700_AUDIO_FUNCTION_GROUP 0x01
#define RT700_DAC_OUT1 0x02
#define RT700_DAC_OUT2 0x03
#define RT700_ADC_IN1 0x09
#define RT700_ADC_IN2 0x08
#define RT700_DMIC1 0x12
#define RT700_DMIC2 0x13
#define RT700_SPK_OUT 0x14
#define RT700_MIC2 0x19
#define RT700_LINE1 0x1a
#define RT700_LINE2 0x1b
#define RT700_BEEP 0x1d
#define RT700_SPDIF 0x1e
#define RT700_VENDOR_REGISTERS 0x20
#define RT700_HP_OUT 0x21
#define RT700_MIXER_IN1 0x22
#define RT700_MIXER_IN2 0x23
#define RT700_INLINE_CMD 0x55
/* Index (NID:20h) */
#define RT700_DAC_DC_CALI_CTL1 0x00
#define RT700_PARA_VERB_CTL 0x1a
#define RT700_COMBO_JACK_AUTO_CTL1 0x45
#define RT700_COMBO_JACK_AUTO_CTL2 0x46
#define RT700_INLINE_CMD_CTL 0x48
#define RT700_DIGITAL_MISC_CTRL4 0x4a
#define RT700_VREFOUT_CTL 0x6b
#define RT700_FSM_CTL 0x6f
#define RT700_IRQ_FLAG_TABLE1 0x80
#define RT700_IRQ_FLAG_TABLE2 0x81
#define RT700_IRQ_FLAG_TABLE3 0x82
/* Verb */
#define RT700_VERB_SET_CONNECT_SEL 0x3100
#define RT700_VERB_SET_EAPD_BTLENABLE 0x3c00
#define RT700_VERB_GET_CONNECT_SEL 0xb100
#define RT700_VERB_SET_POWER_STATE 0x3500
#define RT700_VERB_SET_CHANNEL_STREAMID 0x3600
#define RT700_VERB_SET_PIN_WIDGET_CONTROL 0x3700
#define RT700_VERB_SET_UNSOLICITED_ENABLE 0x3800
#define RT700_SET_AMP_GAIN_MUTE_H 0x7300
#define RT700_SET_AMP_GAIN_MUTE_L 0x8380
#define RT700_VERB_GET_PIN_SENSE 0xb900
#define RT700_READ_HDA_3 0x2012
#define RT700_READ_HDA_2 0x2013
#define RT700_READ_HDA_1 0x2014
#define RT700_READ_HDA_0 0x2015
#define RT700_PRIV_INDEX_W_H 0x7520
#define RT700_PRIV_INDEX_W_L 0x85a0
#define RT700_PRIV_DATA_W_H 0x7420
#define RT700_PRIV_DATA_W_L 0x84a0
#define RT700_PRIV_INDEX_R_H 0x9d20
#define RT700_PRIV_INDEX_R_L 0xada0
#define RT700_PRIV_DATA_R_H 0x9c20
#define RT700_PRIV_DATA_R_L 0xaca0
#define RT700_DAC_FORMAT_H 0x7203
#define RT700_DAC_FORMAT_L 0x8283
#define RT700_ADC_FORMAT_H 0x7209
#define RT700_ADC_FORMAT_L 0x8289
#define RT700_SET_AUDIO_POWER_STATE\
(RT700_VERB_SET_POWER_STATE | RT700_AUDIO_FUNCTION_GROUP)
#define RT700_SET_PIN_DMIC1\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_DMIC1)
#define RT700_SET_PIN_DMIC2\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_DMIC2)
#define RT700_SET_PIN_SPK\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_SPK_OUT)
#define RT700_SET_PIN_HP\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_HP_OUT)
#define RT700_SET_PIN_MIC2\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_MIC2)
#define RT700_SET_PIN_LINE1\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_LINE1)
#define RT700_SET_PIN_LINE2\
(RT700_VERB_SET_PIN_WIDGET_CONTROL | RT700_LINE2)
#define RT700_SET_MIC2_UNSOLICITED_ENABLE\
(RT700_VERB_SET_UNSOLICITED_ENABLE | RT700_MIC2)
#define RT700_SET_HP_UNSOLICITED_ENABLE\
(RT700_VERB_SET_UNSOLICITED_ENABLE | RT700_HP_OUT)
#define RT700_SET_INLINE_UNSOLICITED_ENABLE\
(RT700_VERB_SET_UNSOLICITED_ENABLE | RT700_INLINE_CMD)
#define RT700_SET_STREAMID_DAC1\
(RT700_VERB_SET_CHANNEL_STREAMID | RT700_DAC_OUT1)
#define RT700_SET_STREAMID_DAC2\
(RT700_VERB_SET_CHANNEL_STREAMID | RT700_DAC_OUT2)
#define RT700_SET_STREAMID_ADC1\
(RT700_VERB_SET_CHANNEL_STREAMID | RT700_ADC_IN1)
#define RT700_SET_STREAMID_ADC2\
(RT700_VERB_SET_CHANNEL_STREAMID | RT700_ADC_IN2)
#define RT700_SET_GAIN_DAC1_L\
(RT700_SET_AMP_GAIN_MUTE_L | RT700_DAC_OUT1)
#define RT700_SET_GAIN_DAC1_H\
(RT700_SET_AMP_GAIN_MUTE_H | RT700_DAC_OUT1)
#define RT700_SET_GAIN_ADC1_L\
(RT700_SET_AMP_GAIN_MUTE_L | RT700_ADC_IN1)
#define RT700_SET_GAIN_ADC1_H\
(RT700_SET_AMP_GAIN_MUTE_H | RT700_ADC_IN1)
#define RT700_SET_GAIN_ADC2_L\
(RT700_SET_AMP_GAIN_MUTE_L | RT700_ADC_IN2)
#define RT700_SET_GAIN_ADC2_H\
(RT700_SET_AMP_GAIN_MUTE_H | RT700_ADC_IN2)
#define RT700_SET_GAIN_AMIC_L\
(RT700_SET_AMP_GAIN_MUTE_L | RT700_MIC2)
#define RT700_SET_GAIN_AMIC_H\
(RT700_SET_AMP_GAIN_MUTE_H | RT700_MIC2)
#define RT700_SET_GAIN_HP_L\
(RT700_SET_AMP_GAIN_MUTE_L | RT700_HP_OUT)
#define RT700_SET_GAIN_HP_H\
(RT700_SET_AMP_GAIN_MUTE_H | RT700_HP_OUT)
#define RT700_SET_GAIN_SPK_L\
(RT700_SET_AMP_GAIN_MUTE_L | RT700_SPK_OUT)
#define RT700_SET_GAIN_SPK_H\
(RT700_SET_AMP_GAIN_MUTE_H | RT700_SPK_OUT)
#define RT700_SET_EAPD_SPK\
(RT700_VERB_SET_EAPD_BTLENABLE | RT700_SPK_OUT)
/* combo jack auto switch control 2 (0x46)(NID:20h) */
#define RT700_COMBOJACK_AUTO_DET_STATUS (0x1 << 11)
#define RT700_COMBOJACK_AUTO_DET_TRS (0x1 << 10)
#define RT700_COMBOJACK_AUTO_DET_CTIA (0x1 << 9)
#define RT700_COMBOJACK_AUTO_DET_OMTP (0x1 << 8)
#define RT700_EAPD_HIGH 0x2
#define RT700_EAPD_LOW 0x0
#define RT700_MUTE_SFT 7
#define RT700_DIR_IN_SFT 6
#define RT700_DIR_OUT_SFT 7
enum {
RT700_AIF1,
RT700_AIF2,
RT700_AIFS,
};
int rt700_io_init(struct device *dev, struct sdw_slave *slave);
int rt700_init(struct device *dev, struct regmap *sdw_regmap,
struct regmap *regmap, struct sdw_slave *slave);
int rt700_jack_detect(struct rt700_priv *rt700, bool *hp, bool *mic);
int rt700_clock_config(struct device *dev);
#endif /* __RT700_H__ */
|
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2014, Insignal Co., Ltd.
//
// Author: Claude <[email protected]>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "../codecs/wm8994.h"
#include "i2s.h"
static int arndale_rt5631_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
int rfs, ret;
unsigned long rclk;
rfs = 256;
rclk = params_rate(params) * rfs;
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK,
0, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_RCLKSRC_0,
0, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_ops arndale_rt5631_ops = {
.hw_params = arndale_rt5631_hw_params,
};
static int arndale_wm1811_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
unsigned int rfs, rclk;
/* Ensure AIF1CLK is >= 3 MHz for optimal performance */
if (params_width(params) == 24)
rfs = 384;
else if (params_rate(params) == 8000 || params_rate(params) == 11025)
rfs = 512;
else
rfs = 256;
rclk = params_rate(params) * rfs;
/*
* We add 1 to the frequency value to ensure proper EPLL setting
* for each audio sampling rate (see epll_24mhz_tbl in drivers/clk/
* samsung/clk-exynos5250.c for list of available EPLL rates).
* The CODEC uses clk API and the value will be rounded hence the MCLK1
* clock's frequency will still be exact multiple of the sample rate.
*/
return snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK1,
rclk + 1, SND_SOC_CLOCK_IN);
}
static const struct snd_soc_ops arndale_wm1811_ops = {
.hw_params = arndale_wm1811_hw_params,
};
SND_SOC_DAILINK_DEFS(rt5631_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5631-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link arndale_rt5631_dai[] = {
{
.name = "RT5631 HiFi",
.stream_name = "Primary",
.dai_fmt = SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBS_CFS,
.ops = &arndale_rt5631_ops,
SND_SOC_DAILINK_REG(rt5631_hifi),
},
};
SND_SOC_DAILINK_DEFS(wm1811_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link arndale_wm1811_dai[] = {
{
.name = "WM1811 HiFi",
.stream_name = "Primary",
.dai_fmt = SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ops = &arndale_wm1811_ops,
SND_SOC_DAILINK_REG(wm1811_hifi),
},
};
static struct snd_soc_card arndale_rt5631 = {
.name = "Arndale RT5631",
.owner = THIS_MODULE,
.dai_link = arndale_rt5631_dai,
.num_links = ARRAY_SIZE(arndale_rt5631_dai),
};
static struct snd_soc_card arndale_wm1811 = {
.name = "Arndale WM1811",
.owner = THIS_MODULE,
.dai_link = arndale_wm1811_dai,
.num_links = ARRAY_SIZE(arndale_wm1811_dai),
};
static void arndale_put_of_nodes(struct snd_soc_card *card)
{
struct snd_soc_dai_link *dai_link;
int i;
for_each_card_prelinks(card, i, dai_link) {
of_node_put(dai_link->cpus->of_node);
of_node_put(dai_link->codecs->of_node);
}
}
static int arndale_audio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct snd_soc_card *card;
struct snd_soc_dai_link *dai_link;
int ret;
card = (struct snd_soc_card *)of_device_get_match_data(&pdev->dev);
card->dev = &pdev->dev;
dai_link = card->dai_link;
dai_link->cpus->of_node = of_parse_phandle(np, "samsung,audio-cpu", 0);
if (!dai_link->cpus->of_node) {
dev_err(&pdev->dev,
"Property 'samsung,audio-cpu' missing or invalid\n");
return -EINVAL;
}
if (!dai_link->platforms->name)
dai_link->platforms->of_node = dai_link->cpus->of_node;
dai_link->codecs->of_node = of_parse_phandle(np, "samsung,audio-codec", 0);
if (!dai_link->codecs->of_node) {
dev_err(&pdev->dev,
"Property 'samsung,audio-codec' missing or invalid\n");
ret = -EINVAL;
goto err_put_of_nodes;
}
ret = devm_snd_soc_register_card(card->dev, card);
if (ret) {
dev_err_probe(&pdev->dev, ret,
"snd_soc_register_card() failed\n");
goto err_put_of_nodes;
}
return 0;
err_put_of_nodes:
arndale_put_of_nodes(card);
return ret;
}
static void arndale_audio_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
arndale_put_of_nodes(card);
}
static const struct of_device_id arndale_audio_of_match[] = {
{ .compatible = "samsung,arndale-rt5631", .data = &arndale_rt5631 },
{ .compatible = "samsung,arndale-alc5631", .data = &arndale_rt5631 },
{ .compatible = "samsung,arndale-wm1811", .data = &arndale_wm1811 },
{},
};
MODULE_DEVICE_TABLE(of, arndale_audio_of_match);
static struct platform_driver arndale_audio_driver = {
.driver = {
.name = "arndale-audio",
.pm = &snd_soc_pm_ops,
.of_match_table = arndale_audio_of_match,
},
.probe = arndale_audio_probe,
.remove = arndale_audio_remove,
};
module_platform_driver(arndale_audio_driver);
MODULE_AUTHOR("Claude <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC Driver for Arndale Board");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _KBD_KERN_H
#define _KBD_KERN_H
#include <linux/tty.h>
#include <linux/interrupt.h>
#include <linux/keyboard.h>
extern char *func_table[MAX_NR_FUNC];
/*
* kbd->xxx contains the VC-local things (flag settings etc..)
*
* Note: externally visible are LED_SCR, LED_NUM, LED_CAP defined in kd.h
* The code in KDGETLED / KDSETLED depends on the internal and
* external order being the same.
*
* Note: lockstate is used as index in the array key_map.
*/
struct kbd_struct {
unsigned char lockstate;
/* 8 modifiers - the names do not have any meaning at all;
they can be associated to arbitrarily chosen keys */
#define VC_SHIFTLOCK KG_SHIFT /* shift lock mode */
#define VC_ALTGRLOCK KG_ALTGR /* altgr lock mode */
#define VC_CTRLLOCK KG_CTRL /* control lock mode */
#define VC_ALTLOCK KG_ALT /* alt lock mode */
#define VC_SHIFTLLOCK KG_SHIFTL /* shiftl lock mode */
#define VC_SHIFTRLOCK KG_SHIFTR /* shiftr lock mode */
#define VC_CTRLLLOCK KG_CTRLL /* ctrll lock mode */
#define VC_CTRLRLOCK KG_CTRLR /* ctrlr lock mode */
unsigned char slockstate; /* for `sticky' Shift, Ctrl, etc. */
unsigned char ledmode:1;
#define LED_SHOW_FLAGS 0 /* traditional state */
#define LED_SHOW_IOCTL 1 /* only change leds upon ioctl */
unsigned char ledflagstate:4; /* flags, not lights */
unsigned char default_ledflagstate:4;
#define VC_SCROLLOCK 0 /* scroll-lock mode */
#define VC_NUMLOCK 1 /* numeric lock mode */
#define VC_CAPSLOCK 2 /* capslock mode */
#define VC_KANALOCK 3 /* kanalock mode */
unsigned char kbdmode:3; /* one 3-bit value */
#define VC_XLATE 0 /* translate keycodes using keymap */
#define VC_MEDIUMRAW 1 /* medium raw (keycode) mode */
#define VC_RAW 2 /* raw (scancode) mode */
#define VC_UNICODE 3 /* Unicode mode */
#define VC_OFF 4 /* disabled mode */
unsigned char modeflags:5;
#define VC_APPLIC 0 /* application key mode */
#define VC_CKMODE 1 /* cursor key mode */
#define VC_REPEAT 2 /* keyboard repeat */
#define VC_CRLF 3 /* 0 - enter sends CR, 1 - enter sends CRLF */
#define VC_META 4 /* 0 - meta, 1 - meta=prefix with ESC */
};
extern int kbd_init(void);
extern void setledstate(struct kbd_struct *kbd, unsigned int led);
extern int do_poke_blanked_console;
extern void (*kbd_ledfunc)(unsigned int led);
extern int set_console(int nr);
extern void schedule_console_callback(void);
static inline int vc_kbd_mode(struct kbd_struct * kbd, int flag)
{
return ((kbd->modeflags >> flag) & 1);
}
static inline int vc_kbd_led(struct kbd_struct * kbd, int flag)
{
return ((kbd->ledflagstate >> flag) & 1);
}
static inline void set_vc_kbd_mode(struct kbd_struct * kbd, int flag)
{
kbd->modeflags |= 1 << flag;
}
static inline void set_vc_kbd_led(struct kbd_struct * kbd, int flag)
{
kbd->ledflagstate |= 1 << flag;
}
static inline void clr_vc_kbd_mode(struct kbd_struct * kbd, int flag)
{
kbd->modeflags &= ~(1 << flag);
}
static inline void clr_vc_kbd_led(struct kbd_struct * kbd, int flag)
{
kbd->ledflagstate &= ~(1 << flag);
}
static inline void chg_vc_kbd_lock(struct kbd_struct * kbd, int flag)
{
kbd->lockstate ^= 1 << flag;
}
static inline void chg_vc_kbd_slock(struct kbd_struct * kbd, int flag)
{
kbd->slockstate ^= 1 << flag;
}
static inline void chg_vc_kbd_mode(struct kbd_struct * kbd, int flag)
{
kbd->modeflags ^= 1 << flag;
}
static inline void chg_vc_kbd_led(struct kbd_struct * kbd, int flag)
{
kbd->ledflagstate ^= 1 << flag;
}
#define U(x) ((x) ^ 0xf000)
#define BRL_UC_ROW 0x2800
/* keyboard.c */
struct console;
void vt_set_leds_compute_shiftstate(void);
/* defkeymap.c */
extern unsigned int keymap_count;
#endif
|
// SPDX-License-Identifier: GPL-2.0
#define pr_fmt(fmt) "mtd_test: " fmt
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/printk.h>
#include "mtd_test.h"
int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum)
{
int err;
struct erase_info ei;
loff_t addr = (loff_t)ebnum * mtd->erasesize;
memset(&ei, 0, sizeof(struct erase_info));
ei.addr = addr;
ei.len = mtd->erasesize;
err = mtd_erase(mtd, &ei);
if (err) {
pr_info("error %d while erasing EB %d\n", err, ebnum);
return err;
}
return 0;
}
EXPORT_SYMBOL_GPL(mtdtest_erase_eraseblock);
static int is_block_bad(struct mtd_info *mtd, unsigned int ebnum)
{
int ret;
loff_t addr = (loff_t)ebnum * mtd->erasesize;
ret = mtd_block_isbad(mtd, addr);
if (ret)
pr_info("block %d is bad\n", ebnum);
return ret;
}
int mtdtest_scan_for_bad_eraseblocks(struct mtd_info *mtd, unsigned char *bbt,
unsigned int eb, int ebcnt)
{
int i, bad = 0;
if (!mtd_can_have_bb(mtd))
return 0;
pr_info("scanning for bad eraseblocks\n");
for (i = 0; i < ebcnt; ++i) {
bbt[i] = is_block_bad(mtd, eb + i) ? 1 : 0;
if (bbt[i])
bad += 1;
cond_resched();
}
pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
return 0;
}
EXPORT_SYMBOL_GPL(mtdtest_scan_for_bad_eraseblocks);
int mtdtest_erase_good_eraseblocks(struct mtd_info *mtd, unsigned char *bbt,
unsigned int eb, int ebcnt)
{
int err;
unsigned int i;
for (i = 0; i < ebcnt; ++i) {
if (bbt[i])
continue;
err = mtdtest_erase_eraseblock(mtd, eb + i);
if (err)
return err;
cond_resched();
}
return 0;
}
EXPORT_SYMBOL_GPL(mtdtest_erase_good_eraseblocks);
int mtdtest_read(struct mtd_info *mtd, loff_t addr, size_t size, void *buf)
{
size_t read;
int err;
err = mtd_read(mtd, addr, size, &read, buf);
/* Ignore corrected ECC errors */
if (mtd_is_bitflip(err))
err = 0;
if (!err && read != size)
err = -EIO;
if (err)
pr_err("error: read failed at %#llx\n", addr);
return err;
}
EXPORT_SYMBOL_GPL(mtdtest_read);
int mtdtest_write(struct mtd_info *mtd, loff_t addr, size_t size,
const void *buf)
{
size_t written;
int err;
err = mtd_write(mtd, addr, size, &written, buf);
if (!err && written != size)
err = -EIO;
if (err)
pr_err("error: write failed at %#llx\n", addr);
return err;
}
EXPORT_SYMBOL_GPL(mtdtest_write);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("MTD function test helpers");
MODULE_AUTHOR("Akinobu Mita");
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*/
#ifndef _SH_CSS_FIRMWARE_H_
#define _SH_CSS_FIRMWARE_H_
#include <system_local.h>
#include <ia_css_err.h>
#include <ia_css_acc_types.h>
/* This is for the firmware loaded from user space */
struct sh_css_fw_bi_file_h {
char version[64]; /* branch tag + week day + time */
int binary_nr; /* Number of binaries */
unsigned int h_size; /* sizeof(struct sh_css_fw_bi_file_h) */
};
extern struct ia_css_fw_info sh_css_sp_fw;
extern struct ia_css_blob_descr *sh_css_blob_info;
extern unsigned int sh_css_num_binaries;
char
*sh_css_get_fw_version(void);
struct device;
bool
sh_css_check_firmware_version(struct device *dev, const char *fw_data);
int
sh_css_load_firmware(struct device *dev, const char *fw_data,
unsigned int fw_size);
void sh_css_unload_firmware(void);
ia_css_ptr sh_css_load_blob(const unsigned char *blob, unsigned int size);
int
sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi,
struct ia_css_blob_descr *bd, unsigned int i);
#endif /* _SH_CSS_FIRMWARE_H_ */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* fireworks.c - a part of driver for Fireworks based devices
*
* Copyright (c) 2009-2010 Clemens Ladisch
* Copyright (c) 2013-2014 Takashi Sakamoto
*/
/*
* Fireworks is a board module which Echo Audio produced. This module consists
* of three chipsets:
* - Communication chipset for IEEE1394 PHY/Link and IEC 61883-1/6
* - DSP or/and FPGA for signal processing
* - Flash Memory to store firmwares
*/
#include "fireworks.h"
MODULE_DESCRIPTION("Echo Fireworks driver");
MODULE_AUTHOR("Takashi Sakamoto <[email protected]>");
MODULE_LICENSE("GPL");
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
unsigned int snd_efw_resp_buf_size = 1024;
bool snd_efw_resp_buf_debug = false;
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "card index");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "enable Fireworks sound card");
module_param_named(resp_buf_size, snd_efw_resp_buf_size, uint, 0444);
MODULE_PARM_DESC(resp_buf_size,
"response buffer size (max 4096, default 1024)");
module_param_named(resp_buf_debug, snd_efw_resp_buf_debug, bool, 0444);
MODULE_PARM_DESC(resp_buf_debug, "store all responses to buffer");
static DEFINE_MUTEX(devices_mutex);
static DECLARE_BITMAP(devices_used, SNDRV_CARDS);
#define VENDOR_LOUD 0x000ff2
#define MODEL_MACKIE_400F 0x00400f
#define MODEL_MACKIE_1200F 0x01200f
#define VENDOR_ECHO 0x001486
#define MODEL_ECHO_AUDIOFIRE_12 0x00af12
#define MODEL_ECHO_AUDIOFIRE_12HD 0x0af12d
#define MODEL_ECHO_AUDIOFIRE_12_APPLE 0x0af12a
/* This is applied for AudioFire8 (until 2009 July) */
#define MODEL_ECHO_AUDIOFIRE_8 0x000af8
#define MODEL_ECHO_AUDIOFIRE_2 0x000af2
#define MODEL_ECHO_AUDIOFIRE_4 0x000af4
/* AudioFire9 is applied for AudioFire8(since 2009 July) and AudioFirePre8 */
#define MODEL_ECHO_AUDIOFIRE_9 0x000af9
/* unknown as product */
#define MODEL_ECHO_FIREWORKS_8 0x0000f8
#define MODEL_ECHO_FIREWORKS_HDMI 0x00afd1
#define VENDOR_GIBSON 0x00075b
/* for Robot Interface Pack of Dark Fire, Dusk Tiger, Les Paul Standard 2010 */
#define MODEL_GIBSON_RIP 0x00afb2
/* unknown as product */
#define MODEL_GIBSON_GOLDTOP 0x00afb9
/* part of hardware capability flags */
#define FLAG_RESP_ADDR_CHANGABLE 0
static int
get_hardware_info(struct snd_efw *efw)
{
struct fw_device *fw_dev = fw_parent_device(efw->unit);
struct snd_efw_hwinfo *hwinfo;
char version[12] = {0};
int err;
hwinfo = kzalloc(sizeof(struct snd_efw_hwinfo), GFP_KERNEL);
if (hwinfo == NULL)
return -ENOMEM;
err = snd_efw_command_get_hwinfo(efw, hwinfo);
if (err < 0)
goto end;
/* firmware version for communication chipset */
snprintf(version, sizeof(version), "%u.%u",
(hwinfo->arm_version >> 24) & 0xff,
(hwinfo->arm_version >> 16) & 0xff);
efw->firmware_version = hwinfo->arm_version;
strcpy(efw->card->driver, "Fireworks");
strcpy(efw->card->shortname, hwinfo->model_name);
strcpy(efw->card->mixername, hwinfo->model_name);
scnprintf(efw->card->longname, sizeof(efw->card->longname),
"%s %s v%s, GUID %08x%08x at %s, S%d",
hwinfo->vendor_name, hwinfo->model_name, version,
hwinfo->guid_hi, hwinfo->guid_lo,
dev_name(&efw->unit->device), 100 << fw_dev->max_speed);
if (hwinfo->flags & BIT(FLAG_RESP_ADDR_CHANGABLE))
efw->resp_addr_changable = true;
efw->supported_sampling_rate = 0;
if ((hwinfo->min_sample_rate <= 22050)
&& (22050 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_22050;
if ((hwinfo->min_sample_rate <= 32000)
&& (32000 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_32000;
if ((hwinfo->min_sample_rate <= 44100)
&& (44100 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_44100;
if ((hwinfo->min_sample_rate <= 48000)
&& (48000 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_48000;
if ((hwinfo->min_sample_rate <= 88200)
&& (88200 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_88200;
if ((hwinfo->min_sample_rate <= 96000)
&& (96000 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_96000;
if ((hwinfo->min_sample_rate <= 176400)
&& (176400 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_176400;
if ((hwinfo->min_sample_rate <= 192000)
&& (192000 <= hwinfo->max_sample_rate))
efw->supported_sampling_rate |= SNDRV_PCM_RATE_192000;
/* the number of MIDI ports, not of MIDI conformant data channels */
if (hwinfo->midi_out_ports > SND_EFW_MAX_MIDI_OUT_PORTS ||
hwinfo->midi_in_ports > SND_EFW_MAX_MIDI_IN_PORTS) {
err = -EIO;
goto end;
}
efw->midi_out_ports = hwinfo->midi_out_ports;
efw->midi_in_ports = hwinfo->midi_in_ports;
if (hwinfo->amdtp_tx_pcm_channels > AM824_MAX_CHANNELS_FOR_PCM ||
hwinfo->amdtp_tx_pcm_channels_2x > AM824_MAX_CHANNELS_FOR_PCM ||
hwinfo->amdtp_tx_pcm_channels_4x > AM824_MAX_CHANNELS_FOR_PCM ||
hwinfo->amdtp_rx_pcm_channels > AM824_MAX_CHANNELS_FOR_PCM ||
hwinfo->amdtp_rx_pcm_channels_2x > AM824_MAX_CHANNELS_FOR_PCM ||
hwinfo->amdtp_rx_pcm_channels_4x > AM824_MAX_CHANNELS_FOR_PCM) {
err = -ENOSYS;
goto end;
}
efw->pcm_capture_channels[0] = hwinfo->amdtp_tx_pcm_channels;
efw->pcm_capture_channels[1] = hwinfo->amdtp_tx_pcm_channels_2x;
efw->pcm_capture_channels[2] = hwinfo->amdtp_tx_pcm_channels_4x;
efw->pcm_playback_channels[0] = hwinfo->amdtp_rx_pcm_channels;
efw->pcm_playback_channels[1] = hwinfo->amdtp_rx_pcm_channels_2x;
efw->pcm_playback_channels[2] = hwinfo->amdtp_rx_pcm_channels_4x;
/* Hardware metering. */
if (hwinfo->phys_in_grp_count > HWINFO_MAX_CAPS_GROUPS ||
hwinfo->phys_out_grp_count > HWINFO_MAX_CAPS_GROUPS) {
err = -EIO;
goto end;
}
efw->phys_in = hwinfo->phys_in;
efw->phys_out = hwinfo->phys_out;
efw->phys_in_grp_count = hwinfo->phys_in_grp_count;
efw->phys_out_grp_count = hwinfo->phys_out_grp_count;
memcpy(&efw->phys_in_grps, hwinfo->phys_in_grps,
sizeof(struct snd_efw_phys_grp) * hwinfo->phys_in_grp_count);
memcpy(&efw->phys_out_grps, hwinfo->phys_out_grps,
sizeof(struct snd_efw_phys_grp) * hwinfo->phys_out_grp_count);
/* AudioFire8 (since 2009) and AudioFirePre8 */
if (hwinfo->type == MODEL_ECHO_AUDIOFIRE_9)
efw->is_af9 = true;
/* These models uses the same firmware. */
if (hwinfo->type == MODEL_ECHO_AUDIOFIRE_2 ||
hwinfo->type == MODEL_ECHO_AUDIOFIRE_4 ||
hwinfo->type == MODEL_ECHO_AUDIOFIRE_9 ||
hwinfo->type == MODEL_GIBSON_RIP ||
hwinfo->type == MODEL_GIBSON_GOLDTOP)
efw->is_fireworks3 = true;
end:
kfree(hwinfo);
return err;
}
static void
efw_card_free(struct snd_card *card)
{
struct snd_efw *efw = card->private_data;
mutex_lock(&devices_mutex);
clear_bit(efw->card_index, devices_used);
mutex_unlock(&devices_mutex);
snd_efw_stream_destroy_duplex(efw);
snd_efw_transaction_remove_instance(efw);
mutex_destroy(&efw->mutex);
fw_unit_put(efw->unit);
}
static int efw_probe(struct fw_unit *unit, const struct ieee1394_device_id *entry)
{
unsigned int card_index;
struct snd_card *card;
struct snd_efw *efw;
int err;
// check registered cards.
mutex_lock(&devices_mutex);
for (card_index = 0; card_index < SNDRV_CARDS; ++card_index) {
if (!test_bit(card_index, devices_used) && enable[card_index])
break;
}
if (card_index >= SNDRV_CARDS) {
mutex_unlock(&devices_mutex);
return -ENOENT;
}
err = snd_card_new(&unit->device, index[card_index], id[card_index], THIS_MODULE,
sizeof(*efw), &card);
if (err < 0) {
mutex_unlock(&devices_mutex);
return err;
}
card->private_free = efw_card_free;
set_bit(card_index, devices_used);
mutex_unlock(&devices_mutex);
efw = card->private_data;
efw->unit = fw_unit_get(unit);
dev_set_drvdata(&unit->device, efw);
efw->card = card;
efw->card_index = card_index;
mutex_init(&efw->mutex);
spin_lock_init(&efw->lock);
init_waitqueue_head(&efw->hwdep_wait);
// prepare response buffer.
snd_efw_resp_buf_size = clamp(snd_efw_resp_buf_size, SND_EFW_RESPONSE_MAXIMUM_BYTES, 4096U);
efw->resp_buf = devm_kzalloc(&card->card_dev, snd_efw_resp_buf_size, GFP_KERNEL);
if (!efw->resp_buf) {
err = -ENOMEM;
goto error;
}
efw->pull_ptr = efw->push_ptr = efw->resp_buf;
snd_efw_transaction_add_instance(efw);
err = get_hardware_info(efw);
if (err < 0)
goto error;
err = snd_efw_stream_init_duplex(efw);
if (err < 0)
goto error;
snd_efw_proc_init(efw);
if (efw->midi_out_ports || efw->midi_in_ports) {
err = snd_efw_create_midi_devices(efw);
if (err < 0)
goto error;
}
err = snd_efw_create_pcm_devices(efw);
if (err < 0)
goto error;
err = snd_efw_create_hwdep_device(efw);
if (err < 0)
goto error;
err = snd_card_register(card);
if (err < 0)
goto error;
return 0;
error:
snd_card_free(card);
return err;
}
static void efw_update(struct fw_unit *unit)
{
struct snd_efw *efw = dev_get_drvdata(&unit->device);
snd_efw_transaction_bus_reset(efw->unit);
mutex_lock(&efw->mutex);
snd_efw_stream_update_duplex(efw);
mutex_unlock(&efw->mutex);
}
static void efw_remove(struct fw_unit *unit)
{
struct snd_efw *efw = dev_get_drvdata(&unit->device);
// Block till all of ALSA character devices are released.
snd_card_free(efw->card);
}
#define SPECIFIER_1394TA 0x00a02d
#define VERSION_EFW 0x010000
#define SND_EFW_DEV_ENTRY(vendor, model) \
{ \
.match_flags = IEEE1394_MATCH_VENDOR_ID | \
IEEE1394_MATCH_MODEL_ID | \
IEEE1394_MATCH_SPECIFIER_ID | \
IEEE1394_MATCH_VERSION, \
.vendor_id = vendor,\
.model_id = model, \
.specifier_id = SPECIFIER_1394TA, \
.version = VERSION_EFW, \
}
static const struct ieee1394_device_id efw_id_table[] = {
SND_EFW_DEV_ENTRY(VENDOR_LOUD, MODEL_MACKIE_400F),
SND_EFW_DEV_ENTRY(VENDOR_LOUD, MODEL_MACKIE_1200F),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_8),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_12),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_12HD),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_12_APPLE),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_2),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_4),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_AUDIOFIRE_9),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_FIREWORKS_8),
SND_EFW_DEV_ENTRY(VENDOR_ECHO, MODEL_ECHO_FIREWORKS_HDMI),
SND_EFW_DEV_ENTRY(VENDOR_GIBSON, MODEL_GIBSON_RIP),
SND_EFW_DEV_ENTRY(VENDOR_GIBSON, MODEL_GIBSON_GOLDTOP),
{}
};
MODULE_DEVICE_TABLE(ieee1394, efw_id_table);
static struct fw_driver efw_driver = {
.driver = {
.owner = THIS_MODULE,
.name = KBUILD_MODNAME,
.bus = &fw_bus_type,
},
.probe = efw_probe,
.update = efw_update,
.remove = efw_remove,
.id_table = efw_id_table,
};
static int __init snd_efw_init(void)
{
int err;
err = snd_efw_transaction_register();
if (err < 0)
goto end;
err = driver_register(&efw_driver.driver);
if (err < 0)
snd_efw_transaction_unregister();
end:
return err;
}
static void __exit snd_efw_exit(void)
{
snd_efw_transaction_unregister();
driver_unregister(&efw_driver.driver);
}
module_init(snd_efw_init);
module_exit(snd_efw_exit);
|
// SPDX-License-Identifier: GPL-2.0 AND MIT
/*
* Copyright © 2022 Intel Corporation
*/
#include <uapi/drm/xe_drm.h>
#include <kunit/test.h>
#include <kunit/visibility.h>
#include "tests/xe_kunit_helpers.h"
#include "tests/xe_pci_test.h"
#include "xe_pci.h"
#include "xe_pm.h"
static bool p2p_enabled(struct dma_buf_test_params *params)
{
return IS_ENABLED(CONFIG_PCI_P2PDMA) && params->attach_ops &&
params->attach_ops->allow_peer2peer;
}
static bool is_dynamic(struct dma_buf_test_params *params)
{
return IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY) && params->attach_ops &&
params->attach_ops->move_notify;
}
static void check_residency(struct kunit *test, struct xe_bo *exported,
struct xe_bo *imported, struct dma_buf *dmabuf)
{
struct dma_buf_test_params *params = to_dma_buf_test_params(test->priv);
u32 mem_type;
int ret;
xe_bo_assert_held(exported);
xe_bo_assert_held(imported);
mem_type = XE_PL_VRAM0;
if (!(params->mem_mask & XE_BO_FLAG_VRAM0))
/* No VRAM allowed */
mem_type = XE_PL_TT;
else if (params->force_different_devices && !p2p_enabled(params))
/* No P2P */
mem_type = XE_PL_TT;
else if (params->force_different_devices && !is_dynamic(params) &&
(params->mem_mask & XE_BO_FLAG_SYSTEM))
/* Pin migrated to TT */
mem_type = XE_PL_TT;
if (!xe_bo_is_mem_type(exported, mem_type)) {
KUNIT_FAIL(test, "Exported bo was not in expected memory type.\n");
return;
}
if (xe_bo_is_pinned(exported))
return;
/*
* Evict exporter. Note that the gem object dma_buf member isn't
* set from xe_gem_prime_export(), and it's needed for the move_notify()
* functionality, so hack that up here. Evicting the exported bo will
* evict also the imported bo through the move_notify() functionality if
* importer is on a different device. If they're on the same device,
* the exporter and the importer should be the same bo.
*/
swap(exported->ttm.base.dma_buf, dmabuf);
ret = xe_bo_evict(exported, true);
swap(exported->ttm.base.dma_buf, dmabuf);
if (ret) {
if (ret != -EINTR && ret != -ERESTARTSYS)
KUNIT_FAIL(test, "Evicting exporter failed with err=%d.\n",
ret);
return;
}
/* Verify that also importer has been evicted to SYSTEM */
if (exported != imported && !xe_bo_is_mem_type(imported, XE_PL_SYSTEM)) {
KUNIT_FAIL(test, "Importer wasn't properly evicted.\n");
return;
}
/* Re-validate the importer. This should move also exporter in. */
ret = xe_bo_validate(imported, NULL, false);
if (ret) {
if (ret != -EINTR && ret != -ERESTARTSYS)
KUNIT_FAIL(test, "Validating importer failed with err=%d.\n",
ret);
return;
}
/*
* If on different devices, the exporter is kept in system if
* possible, saving a migration step as the transfer is just
* likely as fast from system memory.
*/
if (params->mem_mask & XE_BO_FLAG_SYSTEM)
KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, XE_PL_TT));
else
KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, mem_type));
if (params->force_different_devices)
KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(imported, XE_PL_TT));
else
KUNIT_EXPECT_TRUE(test, exported == imported);
}
static void xe_test_dmabuf_import_same_driver(struct xe_device *xe)
{
struct kunit *test = kunit_get_current_test();
struct dma_buf_test_params *params = to_dma_buf_test_params(test->priv);
struct drm_gem_object *import;
struct dma_buf *dmabuf;
struct xe_bo *bo;
size_t size;
/* No VRAM on this device? */
if (!ttm_manager_type(&xe->ttm, XE_PL_VRAM0) &&
(params->mem_mask & XE_BO_FLAG_VRAM0))
return;
size = PAGE_SIZE;
if ((params->mem_mask & XE_BO_FLAG_VRAM0) &&
xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
size = SZ_64K;
kunit_info(test, "running %s\n", __func__);
bo = xe_bo_create_user(xe, NULL, NULL, size, DRM_XE_GEM_CPU_CACHING_WC,
params->mem_mask);
if (IS_ERR(bo)) {
KUNIT_FAIL(test, "xe_bo_create() failed with err=%ld\n",
PTR_ERR(bo));
return;
}
dmabuf = xe_gem_prime_export(&bo->ttm.base, 0);
if (IS_ERR(dmabuf)) {
KUNIT_FAIL(test, "xe_gem_prime_export() failed with err=%ld\n",
PTR_ERR(dmabuf));
goto out;
}
import = xe_gem_prime_import(&xe->drm, dmabuf);
if (!IS_ERR(import)) {
struct xe_bo *import_bo = gem_to_xe_bo(import);
/*
* Did import succeed when it shouldn't due to lack of p2p support?
*/
if (params->force_different_devices &&
!p2p_enabled(params) &&
!(params->mem_mask & XE_BO_FLAG_SYSTEM)) {
KUNIT_FAIL(test,
"xe_gem_prime_import() succeeded when it shouldn't have\n");
} else {
int err;
/* Is everything where we expect it to be? */
xe_bo_lock(import_bo, false);
err = xe_bo_validate(import_bo, NULL, false);
/* Pinning in VRAM is not allowed. */
if (!is_dynamic(params) &&
params->force_different_devices &&
!(params->mem_mask & XE_BO_FLAG_SYSTEM))
KUNIT_EXPECT_EQ(test, err, -EINVAL);
/* Otherwise only expect interrupts or success. */
else if (err && err != -EINTR && err != -ERESTARTSYS)
KUNIT_EXPECT_TRUE(test, !err || err == -EINTR ||
err == -ERESTARTSYS);
if (!err)
check_residency(test, bo, import_bo, dmabuf);
xe_bo_unlock(import_bo);
}
drm_gem_object_put(import);
} else if (PTR_ERR(import) != -EOPNOTSUPP) {
/* Unexpected error code. */
KUNIT_FAIL(test,
"xe_gem_prime_import failed with the wrong err=%ld\n",
PTR_ERR(import));
} else if (!params->force_different_devices ||
p2p_enabled(params) ||
(params->mem_mask & XE_BO_FLAG_SYSTEM)) {
/* Shouldn't fail if we can reuse same bo, use p2p or use system */
KUNIT_FAIL(test, "dynamic p2p attachment failed with err=%ld\n",
PTR_ERR(import));
}
dma_buf_put(dmabuf);
out:
drm_gem_object_put(&bo->ttm.base);
}
static const struct dma_buf_attach_ops nop2p_attach_ops = {
.allow_peer2peer = false,
.move_notify = xe_dma_buf_move_notify
};
/*
* We test the implementation with bos of different residency and with
* importers with different capabilities; some lacking p2p support and some
* lacking dynamic capabilities (attach_ops == NULL). We also fake
* different devices avoiding the import shortcut that just reuses the same
* gem object.
*/
static const struct dma_buf_test_params test_params[] = {
{.mem_mask = XE_BO_FLAG_VRAM0,
.attach_ops = &xe_dma_buf_attach_ops},
{.mem_mask = XE_BO_FLAG_VRAM0,
.attach_ops = &xe_dma_buf_attach_ops,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_VRAM0,
.attach_ops = &nop2p_attach_ops},
{.mem_mask = XE_BO_FLAG_VRAM0,
.attach_ops = &nop2p_attach_ops,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_VRAM0},
{.mem_mask = XE_BO_FLAG_VRAM0,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_SYSTEM,
.attach_ops = &xe_dma_buf_attach_ops},
{.mem_mask = XE_BO_FLAG_SYSTEM,
.attach_ops = &xe_dma_buf_attach_ops,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_SYSTEM,
.attach_ops = &nop2p_attach_ops},
{.mem_mask = XE_BO_FLAG_SYSTEM,
.attach_ops = &nop2p_attach_ops,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_SYSTEM},
{.mem_mask = XE_BO_FLAG_SYSTEM,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_SYSTEM | XE_BO_FLAG_VRAM0,
.attach_ops = &xe_dma_buf_attach_ops},
{.mem_mask = XE_BO_FLAG_SYSTEM | XE_BO_FLAG_VRAM0,
.attach_ops = &xe_dma_buf_attach_ops,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_SYSTEM | XE_BO_FLAG_VRAM0,
.attach_ops = &nop2p_attach_ops},
{.mem_mask = XE_BO_FLAG_SYSTEM | XE_BO_FLAG_VRAM0,
.attach_ops = &nop2p_attach_ops,
.force_different_devices = true},
{.mem_mask = XE_BO_FLAG_SYSTEM | XE_BO_FLAG_VRAM0},
{.mem_mask = XE_BO_FLAG_SYSTEM | XE_BO_FLAG_VRAM0,
.force_different_devices = true},
{}
};
static int dma_buf_run_device(struct xe_device *xe)
{
const struct dma_buf_test_params *params;
struct kunit *test = kunit_get_current_test();
xe_pm_runtime_get(xe);
for (params = test_params; params->mem_mask; ++params) {
struct dma_buf_test_params p = *params;
p.base.id = XE_TEST_LIVE_DMA_BUF;
test->priv = &p;
xe_test_dmabuf_import_same_driver(xe);
}
xe_pm_runtime_put(xe);
/* A non-zero return would halt iteration over driver devices */
return 0;
}
static void xe_dma_buf_kunit(struct kunit *test)
{
struct xe_device *xe = test->priv;
dma_buf_run_device(xe);
}
static struct kunit_case xe_dma_buf_tests[] = {
KUNIT_CASE_PARAM(xe_dma_buf_kunit, xe_pci_live_device_gen_param),
{}
};
VISIBLE_IF_KUNIT
struct kunit_suite xe_dma_buf_test_suite = {
.name = "xe_dma_buf",
.test_cases = xe_dma_buf_tests,
.init = xe_kunit_helper_xe_device_live_test_init,
};
EXPORT_SYMBOL_IF_KUNIT(xe_dma_buf_test_suite);
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra20_i2s.c - Tegra20 I2S driver
*
* Author: Stephen Warren <[email protected]>
* Copyright (C) 2010,2012 - NVIDIA, Inc.
*
* Based on code copyright/by:
*
* Copyright (c) 2009-2010, NVIDIA Corporation.
* Scott Peterson <[email protected]>
*
* Copyright (C) 2010 Google, Inc.
* Iliyan Malchev <[email protected]>
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra20_i2s.h"
#define DRV_NAME "tegra20-i2s"
static __maybe_unused int tegra20_i2s_runtime_suspend(struct device *dev)
{
struct tegra20_i2s *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
clk_disable_unprepare(i2s->clk_i2s);
return 0;
}
static __maybe_unused int tegra20_i2s_runtime_resume(struct device *dev)
{
struct tegra20_i2s *i2s = dev_get_drvdata(dev);
int ret;
ret = reset_control_assert(i2s->reset);
if (ret)
return ret;
ret = clk_prepare_enable(i2s->clk_i2s);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
usleep_range(10, 100);
ret = reset_control_deassert(i2s->reset);
if (ret)
goto disable_clocks;
regcache_cache_only(i2s->regmap, false);
regcache_mark_dirty(i2s->regmap);
ret = regcache_sync(i2s->regmap);
if (ret)
goto disable_clocks;
return 0;
disable_clocks:
clk_disable_unprepare(i2s->clk_i2s);
return ret;
}
static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask = 0, val = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
mask |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
val |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
break;
case SND_SOC_DAIFMT_BC_FC:
break;
default:
return -EINVAL;
}
mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
TEGRA20_I2S_CTRL_LRCK_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_DSP_B:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
val |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
break;
case SND_SOC_DAIFMT_I2S:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
return 0;
}
static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val;
int ret, sample_size, srate, i2sclock, bitcnt;
mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
val = TEGRA20_I2S_CTRL_BIT_SIZE_16;
sample_size = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val = TEGRA20_I2S_CTRL_BIT_SIZE_24;
sample_size = 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
val = TEGRA20_I2S_CTRL_BIT_SIZE_32;
sample_size = 32;
break;
default:
return -EINVAL;
}
mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
srate = params_rate(params);
/* Final "* 2" required by Tegra hardware */
i2sclock = srate * params_channels(params) * sample_size * 2;
ret = clk_set_rate(i2s->clk_i2s, i2sclock);
if (ret) {
dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
return ret;
}
bitcnt = (i2sclock / (2 * srate)) - 1;
if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
return -EINVAL;
val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
if (i2sclock % (2 * srate))
val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);
regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
return 0;
}
static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO1_ENABLE,
TEGRA20_I2S_CTRL_FIFO1_ENABLE);
}
static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0);
}
static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO2_ENABLE,
TEGRA20_I2S_CTRL_FIFO2_ENABLE);
}
static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0);
}
static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra20_i2s_start_playback(i2s);
else
tegra20_i2s_start_capture(i2s);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra20_i2s_stop_playback(i2s);
else
tegra20_i2s_stop_capture(i2s);
break;
default:
return -EINVAL;
}
return 0;
}
static int tegra20_i2s_probe(struct snd_soc_dai *dai)
{
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
&i2s->capture_dma_data);
return 0;
}
static const unsigned int tegra20_i2s_rates[] = {
8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000
};
static int tegra20_i2s_filter_rates(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_interval *r = hw_param_interval(params, rule->var);
struct snd_soc_dai *dai = rule->private;
struct tegra20_i2s *i2s = dev_get_drvdata(dai->dev);
struct clk *parent = clk_get_parent(i2s->clk_i2s);
unsigned long i, parent_rate, valid_rates = 0;
parent_rate = clk_get_rate(parent);
if (!parent_rate) {
dev_err(dai->dev, "Can't get parent clock rate\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(tegra20_i2s_rates); i++) {
if (parent_rate % (tegra20_i2s_rates[i] * 128) == 0)
valid_rates |= BIT(i);
}
/*
* At least one rate must be valid, otherwise the parent clock isn't
* audio PLL. Nothing should be filtered in this case.
*/
if (!valid_rates)
valid_rates = BIT(ARRAY_SIZE(tegra20_i2s_rates)) - 1;
return snd_interval_list(r, ARRAY_SIZE(tegra20_i2s_rates),
tegra20_i2s_rates, valid_rates);
}
static int tegra20_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
return 0;
return snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
tegra20_i2s_filter_rates, dai,
SNDRV_PCM_HW_PARAM_RATE, -1);
}
static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
.probe = tegra20_i2s_probe,
.set_fmt = tegra20_i2s_set_fmt,
.hw_params = tegra20_i2s_hw_params,
.trigger = tegra20_i2s_trigger,
.startup = tegra20_i2s_startup,
};
static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tegra20_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver tegra20_i2s_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_I2S_CTRL:
case TEGRA20_I2S_STATUS:
case TEGRA20_I2S_TIMING:
case TEGRA20_I2S_FIFO_SCR:
case TEGRA20_I2S_PCM_CTRL:
case TEGRA20_I2S_NW_CTRL:
case TEGRA20_I2S_TDM_CTRL:
case TEGRA20_I2S_TDM_TX_RX_CTRL:
case TEGRA20_I2S_FIFO1:
case TEGRA20_I2S_FIFO2:
return true;
default:
return false;
}
}
static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_I2S_STATUS:
case TEGRA20_I2S_FIFO_SCR:
case TEGRA20_I2S_FIFO1:
case TEGRA20_I2S_FIFO2:
return true;
default:
return false;
}
}
static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_I2S_FIFO1:
case TEGRA20_I2S_FIFO2:
return true;
default:
return false;
}
}
static const struct regmap_config tegra20_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA20_I2S_FIFO2,
.writeable_reg = tegra20_i2s_wr_rd_reg,
.readable_reg = tegra20_i2s_wr_rd_reg,
.volatile_reg = tegra20_i2s_volatile_reg,
.precious_reg = tegra20_i2s_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static int tegra20_i2s_platform_probe(struct platform_device *pdev)
{
struct tegra20_i2s *i2s;
struct resource *mem;
void __iomem *regs;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
if (!i2s) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, i2s);
i2s->dai = tegra20_i2s_dai_template;
i2s->dai.name = dev_name(&pdev->dev);
i2s->reset = devm_reset_control_get_exclusive(&pdev->dev, "i2s");
if (IS_ERR(i2s->reset)) {
dev_err(&pdev->dev, "Can't retrieve i2s reset\n");
return PTR_ERR(i2s->reset);
}
i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(i2s->clk_i2s)) {
dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
ret = PTR_ERR(i2s->clk_i2s);
goto err;
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
goto err;
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra20_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
ret = PTR_ERR(i2s->regmap);
goto err;
}
i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 4;
i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->playback_dma_data.maxburst = 4;
pm_runtime_enable(&pdev->dev);
ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component,
&i2s->dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
ret = -ENOMEM;
goto err_pm_disable;
}
ret = tegra_pcm_platform_register(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
goto err_unregister_component;
}
return 0;
err_unregister_component:
snd_soc_unregister_component(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err:
return ret;
}
static void tegra20_i2s_platform_remove(struct platform_device *pdev)
{
tegra_pcm_platform_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static const struct of_device_id tegra20_i2s_of_match[] = {
{ .compatible = "nvidia,tegra20-i2s", },
{},
};
static const struct dev_pm_ops tegra20_i2s_pm_ops = {
SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
tegra20_i2s_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra20_i2s_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = tegra20_i2s_of_match,
.pm = &tegra20_i2s_pm_ops,
},
.probe = tegra20_i2s_platform_probe,
.remove = tegra20_i2s_platform_remove,
};
module_platform_driver(tegra20_i2s_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
|
/***********************license start***************
* Author: Cavium Networks
*
* Contact: [email protected]
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/*
* Functions for SPI initialization, configuration,
* and monitoring.
*/
#ifndef __CVMX_HELPER_SPI_H__
#define __CVMX_HELPER_SPI_H__
/**
* Probe a SPI interface and determine the number of ports
* connected to it. The SPI interface should still be down after
* this call.
*
* @interface: Interface to probe
*
* Returns Number of ports on the interface. Zero to disable.
*/
extern int __cvmx_helper_spi_probe(int interface);
extern int __cvmx_helper_spi_enumerate(int interface);
/**
* Bringup and enable a SPI interface. After this call packet I/O
* should be fully functional. This is called with IPD enabled but
* PKO disabled.
*
* @interface: Interface to bring up
*
* Returns Zero on success, negative on failure
*/
extern int __cvmx_helper_spi_enable(int interface);
/**
* Return the link state of an IPD/PKO port as returned by
* auto negotiation. The result of this function may not match
* Octeon's link config if auto negotiation has changed since
* the last call to cvmx_helper_link_set().
*
* @ipd_port: IPD/PKO port to query
*
* Returns Link state
*/
extern union cvmx_helper_link_info __cvmx_helper_spi_link_get(int ipd_port);
/**
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get().
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state
*
* Returns Zero on success, negative on failure
*/
extern int __cvmx_helper_spi_link_set(int ipd_port,
union cvmx_helper_link_info link_info);
#endif
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _NAMESPACE_H_
#define _NAMESPACE_H_
#ifdef __KERNEL__
#include <linux/cleanup.h>
#include <linux/err.h>
struct mnt_namespace;
struct fs_struct;
struct user_namespace;
struct ns_common;
extern struct mnt_namespace *copy_mnt_ns(unsigned long, struct mnt_namespace *,
struct user_namespace *, struct fs_struct *);
extern void put_mnt_ns(struct mnt_namespace *ns);
DEFINE_FREE(put_mnt_ns, struct mnt_namespace *, if (!IS_ERR_OR_NULL(_T)) put_mnt_ns(_T))
extern struct ns_common *from_mnt_ns(struct mnt_namespace *);
extern const struct file_operations proc_mounts_operations;
extern const struct file_operations proc_mountinfo_operations;
extern const struct file_operations proc_mountstats_operations;
#endif
#endif
|
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2012-2014, 2018-2021 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
#ifndef __VENDOR_CMD_INTEL_H__
#define __VENDOR_CMD_INTEL_H__
#define INTEL_OUI 0x001735
/**
* enum iwl_mvm_vendor_cmd - supported vendor commands
* @IWL_MVM_VENDOR_CMD_GET_CSME_CONN_INFO: reports CSME connection info.
* @IWL_MVM_VENDOR_CMD_HOST_GET_OWNERSHIP: asks for ownership on the device.
* This is useful when the CSME firmware owns the device and the kernel
* wants to use it. In case the CSME firmware has no connection active the
* kernel will manage on its own to get ownership of the device.
* When the CSME firmware has an active connection, the user space
* involvement is required. The kernel will assert the RFKILL signal with
* the "device not owned" reason so that nobody can touch the device. Then
* the user space can run the following flow to be able to get connected
* to the very same AP the CSME firmware is currently connected to:
*
* 1) The user space (NetworkManager) boots and sees that the device is
* in RFKILL because the host doesn't own the device
* 2) The user space asks the kernel what AP the CSME firmware is
* connected to (with %IWL_MVM_VENDOR_CMD_GET_CSME_CONN_INFO)
* 3) The user space checks if it has a profile that matches the reply
* from the CSME firmware
* 4) The user space installs a network to the wpa_supplicant with a
* specific BSSID and a specific frequency
* 5) The user space prevents any type of full scan
* 6) The user space asks iwlmei to request ownership on the device (with
* this command)
* 7) iwlmei requests ownership from the CSME firmware
* 8) The CSME firmware grants ownership
* 9) iwlmei tells iwlwifi to lift the RFKILL
* 10) RFKILL OFF is reported to user space
* 11) The host boots the device, loads the firwmare, and connects to a
* specific BSSID without scanning including IP as fast as it can
* 12) The host reports to the CSME firmware that there is a connection
* 13) The TCP connection is preserved and the host has connectivity
*
* @IWL_MVM_VENDOR_CMD_ROAMING_FORBIDDEN_EVENT: notifies if roaming is allowed.
* It contains a &IWL_MVM_VENDOR_ATTR_ROAMING_FORBIDDEN and a
* &IWL_MVM_VENDOR_ATTR_VIF_ADDR attributes.
*/
enum iwl_mvm_vendor_cmd {
IWL_MVM_VENDOR_CMD_GET_CSME_CONN_INFO = 0x2d,
IWL_MVM_VENDOR_CMD_HOST_GET_OWNERSHIP = 0x30,
IWL_MVM_VENDOR_CMD_ROAMING_FORBIDDEN_EVENT = 0x32,
};
enum iwl_vendor_auth_akm_mode {
IWL_VENDOR_AUTH_OPEN,
IWL_VENDOR_AUTH_RSNA = 0x6,
IWL_VENDOR_AUTH_RSNA_PSK,
IWL_VENDOR_AUTH_SAE = 0x9,
IWL_VENDOR_AUTH_MAX,
};
/**
* enum iwl_mvm_vendor_attr - attributes used in vendor commands
* @__IWL_MVM_VENDOR_ATTR_INVALID: attribute 0 is invalid
* @IWL_MVM_VENDOR_ATTR_VIF_ADDR: interface MAC address
* @IWL_MVM_VENDOR_ATTR_ADDR: MAC address
* @IWL_MVM_VENDOR_ATTR_SSID: SSID (binary attribute, 0..32 octets)
* @IWL_MVM_VENDOR_ATTR_STA_CIPHER: the cipher to use for the station with the
* mac address specified in &IWL_MVM_VENDOR_ATTR_ADDR.
* @IWL_MVM_VENDOR_ATTR_ROAMING_FORBIDDEN: u8 attribute. Indicates whether
* roaming is forbidden or not. Value 1 means roaming is forbidden,
* 0 mean roaming is allowed.
* @IWL_MVM_VENDOR_ATTR_AUTH_MODE: u32 attribute. Authentication mode type
* as specified in &enum iwl_vendor_auth_akm_mode.
* @IWL_MVM_VENDOR_ATTR_CHANNEL_NUM: u8 attribute. Contains channel number.
* @IWL_MVM_VENDOR_ATTR_BAND: u8 attribute.
* 0 for 2.4 GHz band, 1 for 5.2GHz band and 2 for 6GHz band.
* @IWL_MVM_VENDOR_ATTR_COLLOC_CHANNEL: u32 attribute. Channel number of
* collocated AP. Relevant for 6GHz AP info.
* @IWL_MVM_VENDOR_ATTR_COLLOC_ADDR: MAC address of a collocated AP.
* Relevant for 6GHz AP info.
*
* @NUM_IWL_MVM_VENDOR_ATTR: number of vendor attributes
* @MAX_IWL_MVM_VENDOR_ATTR: highest vendor attribute number
*/
enum iwl_mvm_vendor_attr {
__IWL_MVM_VENDOR_ATTR_INVALID = 0x00,
IWL_MVM_VENDOR_ATTR_VIF_ADDR = 0x02,
IWL_MVM_VENDOR_ATTR_ADDR = 0x0a,
IWL_MVM_VENDOR_ATTR_SSID = 0x3d,
IWL_MVM_VENDOR_ATTR_STA_CIPHER = 0x51,
IWL_MVM_VENDOR_ATTR_ROAMING_FORBIDDEN = 0x64,
IWL_MVM_VENDOR_ATTR_AUTH_MODE = 0x65,
IWL_MVM_VENDOR_ATTR_CHANNEL_NUM = 0x66,
IWL_MVM_VENDOR_ATTR_BAND = 0x69,
IWL_MVM_VENDOR_ATTR_COLLOC_CHANNEL = 0x70,
IWL_MVM_VENDOR_ATTR_COLLOC_ADDR = 0x71,
NUM_IWL_MVM_VENDOR_ATTR,
MAX_IWL_MVM_VENDOR_ATTR = NUM_IWL_MVM_VENDOR_ATTR - 1,
};
#endif /* __VENDOR_CMD_INTEL_H__ */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include "dsi_phy.h"
#include "dsi.xml.h"
#include "dsi_phy_14nm.xml.h"
#define PHY_14NM_CKLN_IDX 4
/*
* DSI PLL 14nm - clock diagram (eg: DSI0):
*
* dsi0n1_postdiv_clk
* |
* |
* +----+ | +----+
* dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
* +----+ | +----+
* | dsi0n1_postdivby2_clk
* | +----+ |
* o---| /2 |--o--|\
* | +----+ | \ +----+
* | | |--| n2 |-- dsi0pll
* o--------------| / +----+
* |/
*/
#define POLL_MAX_READS 15
#define POLL_TIMEOUT_US 1000
#define VCO_REF_CLK_RATE 19200000
#define VCO_MIN_RATE 1300000000UL
#define VCO_MAX_RATE 2600000000UL
struct dsi_pll_config {
u64 vco_current_rate;
u32 ssc_en; /* SSC enable/disable */
/* fixed params */
u32 plllock_cnt;
u32 ssc_center;
u32 ssc_adj_period;
u32 ssc_spread;
u32 ssc_freq;
/* calculated */
u32 dec_start;
u32 div_frac_start;
u32 ssc_period;
u32 ssc_step_size;
u32 plllock_cmp;
u32 pll_vco_div_ref;
u32 pll_vco_count;
u32 pll_kvco_div_ref;
u32 pll_kvco_count;
};
struct pll_14nm_cached_state {
unsigned long vco_rate;
u8 n2postdiv;
u8 n1postdiv;
};
struct dsi_pll_14nm {
struct clk_hw clk_hw;
struct msm_dsi_phy *phy;
/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock;
struct pll_14nm_cached_state cached_state;
struct dsi_pll_14nm *slave;
};
#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw)
/*
* Private struct for N1/N2 post-divider clocks. These clocks are similar to
* the generic clk_divider class of clocks. The only difference is that it
* also sets the slave DSI PLL's post-dividers if in bonded DSI mode
*/
struct dsi_pll_14nm_postdiv {
struct clk_hw hw;
/* divider params */
u8 shift;
u8 width;
u8 flags; /* same flags as used by clk_divider struct */
struct dsi_pll_14nm *pll;
};
#define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw)
/*
* Global list of private DSI PLL struct pointers. We need this for bonded DSI
* mode, where the master PLL's clk_ops needs access the slave's private data
*/
static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];
static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
u32 nb_tries, u32 timeout_us)
{
bool pll_locked = false, pll_ready = false;
void __iomem *base = pll_14nm->phy->pll_base;
u32 tries, val;
tries = nb_tries;
while (tries--) {
val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
pll_locked = !!(val & BIT(5));
if (pll_locked)
break;
udelay(timeout_us);
}
if (!pll_locked)
goto out;
tries = nb_tries;
while (tries--) {
val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
pll_ready = !!(val & BIT(0));
if (pll_ready)
break;
udelay(timeout_us);
}
out:
DBG("DSI PLL is %slocked, %sready", pll_locked ? "" : "*not* ", pll_ready ? "" : "*not* ");
return pll_locked && pll_ready;
}
static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
{
/* fixed input */
pconf->plllock_cnt = 1;
/*
* SSC is enabled by default. We might need DT props for configuring
* some SSC params like PPM and center/down spread etc.
*/
pconf->ssc_en = 1;
pconf->ssc_center = 0; /* down spread by default */
pconf->ssc_spread = 5; /* PPM / 1000 */
pconf->ssc_freq = 31500; /* default recommended */
pconf->ssc_adj_period = 37;
}
#define CEIL(x, y) (((x) + ((y) - 1)) / (y))
static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
u32 period, ssc_period;
u32 ref, rem;
u64 step_size;
DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
ssc_period = pconf->ssc_freq / 500;
period = (u32)VCO_REF_CLK_RATE / 1000;
ssc_period = CEIL(period, ssc_period);
ssc_period -= 1;
pconf->ssc_period = ssc_period;
DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq,
pconf->ssc_spread, pconf->ssc_period);
step_size = (u32)pconf->vco_current_rate;
ref = VCO_REF_CLK_RATE;
ref /= 1000;
step_size = div_u64(step_size, ref);
step_size <<= 20;
step_size = div_u64(step_size, 1000);
step_size *= pconf->ssc_spread;
step_size = div_u64(step_size, 1000);
step_size *= (pconf->ssc_adj_period + 1);
rem = 0;
step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
if (rem)
step_size++;
DBG("step_size=%lld", step_size);
step_size &= 0x0ffff; /* take lower 16 bits */
pconf->ssc_step_size = step_size;
}
static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
u64 multiplier = BIT(20);
u64 dec_start_multiple, dec_start, pll_comp_val;
u32 duration, div_frac_start;
u64 vco_clk_rate = pconf->vco_current_rate;
u64 fref = VCO_REF_CLK_RATE;
DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
pconf->dec_start = (u32)dec_start;
pconf->div_frac_start = div_frac_start;
if (pconf->plllock_cnt == 0)
duration = 1024;
else if (pconf->plllock_cnt == 1)
duration = 256;
else if (pconf->plllock_cnt == 2)
duration = 128;
else
duration = 32;
pll_comp_val = duration * dec_start_multiple;
pll_comp_val = div_u64(pll_comp_val, multiplier);
do_div(pll_comp_val, 10);
pconf->plllock_cmp = (u32)pll_comp_val;
}
static u32 pll_14nm_kvco_slop(u32 vrate)
{
u32 slop = 0;
if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL)
slop = 600;
else if (vrate > 1800000000UL && vrate < 2300000000UL)
slop = 400;
else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE)
slop = 280;
return slop;
}
static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
u64 vco_clk_rate = pconf->vco_current_rate;
u64 fref = VCO_REF_CLK_RATE;
u32 vco_measure_time = 5;
u32 kvco_measure_time = 5;
u64 data;
u32 cnt;
data = fref * vco_measure_time;
do_div(data, 1000000);
data &= 0x03ff; /* 10 bits */
data -= 2;
pconf->pll_vco_div_ref = data;
data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
data *= vco_measure_time;
do_div(data, 10);
pconf->pll_vco_count = data;
data = fref * kvco_measure_time;
do_div(data, 1000000);
data &= 0x03ff; /* 10 bits */
data -= 1;
pconf->pll_kvco_div_ref = data;
cnt = pll_14nm_kvco_slop(vco_clk_rate);
cnt *= 2;
cnt /= 100;
cnt *= kvco_measure_time;
pconf->pll_kvco_count = cnt;
}
static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{
void __iomem *base = pll->phy->pll_base;
u8 data;
data = pconf->ssc_adj_period;
data &= 0x0ff;
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1);
data = (pconf->ssc_adj_period >> 8);
data &= 0x03;
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2);
data = pconf->ssc_period;
data &= 0x0ff;
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1);
data = (pconf->ssc_period >> 8);
data &= 0x0ff;
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2);
data = pconf->ssc_step_size;
data &= 0x0ff;
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1);
data = (pconf->ssc_step_size >> 8);
data &= 0x0ff;
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2);
data = (pconf->ssc_center & 0x01);
data <<= 1;
data |= 0x01; /* enable */
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER);
wmb(); /* make sure register committed */
}
static void pll_db_commit_common(struct dsi_pll_14nm *pll,
struct dsi_pll_config *pconf)
{
void __iomem *base = pll->phy->pll_base;
u8 data;
/* confgiure the non frequency dependent pll registers */
data = 0;
writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET);
writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN);
writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL);
/* bandgap_timer */
writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2);
/* pll_wakeup_timer */
writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5);
data = pconf->pll_vco_div_ref & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1);
data = (pconf->pll_vco_div_ref >> 8) & 0x3;
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2);
data = pconf->pll_kvco_div_ref & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1);
data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2);
writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1);
writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM);
writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM);
writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR);
writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET);
writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET);
writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET);
writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1);
writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM);
writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL);
}
static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
{
void __iomem *cmn_base = pll_14nm->phy->base;
/* de assert pll start and apply pll sw reset */
/* stop pll */
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
/* pll sw reset */
writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
udelay(10);
wmb(); /* make sure register committed */
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
wmb(); /* make sure register committed */
}
static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
struct dsi_pll_config *pconf)
{
void __iomem *base = pll->phy->pll_base;
void __iomem *cmn_base = pll->phy->base;
u8 data;
DBG("DSI%d PLL", pll->phy->id);
writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
pll_db_commit_common(pll, pconf);
pll_14nm_software_reset(pll);
/* Use the /2 path in Mux */
writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1);
data = 0xff; /* data, clk, pll normal operation */
writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0);
/* configure the frequency dependent pll registers */
data = pconf->dec_start;
writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START);
data = pconf->div_frac_start & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1);
data = (pconf->div_frac_start >> 8) & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2);
data = (pconf->div_frac_start >> 16) & 0xf;
writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3);
data = pconf->plllock_cmp & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1);
data = (pconf->plllock_cmp >> 8) & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2);
data = (pconf->plllock_cmp >> 16) & 0x3;
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3);
data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN);
data = pconf->pll_vco_count & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1);
data = (pconf->pll_vco_count >> 8) & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2);
data = pconf->pll_kvco_count & 0xff;
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1);
data = (pconf->pll_kvco_count >> 8) & 0x3;
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2);
/*
* High nibble configures the post divider internal to the VCO. It's
* fixed to divide by 1 for now.
*
* 0: divided by 1
* 1: divided by 2
* 2: divided by 4
* 3: divided by 8
*/
writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV);
if (pconf->ssc_en)
pll_db_commit_ssc(pll, pconf);
wmb(); /* make sure register committed */
}
/*
* VCO clock Callbacks
*/
static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
struct dsi_pll_config conf;
DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
parent_rate);
dsi_pll_14nm_config_init(&conf);
conf.vco_current_rate = rate;
pll_14nm_dec_frac_calc(pll_14nm, &conf);
if (conf.ssc_en)
pll_14nm_ssc_calc(pll_14nm, &conf);
pll_14nm_calc_vco_count(pll_14nm, &conf);
/* commit the slave DSI PLL registers if we're master. Note that we
* don't lock the slave PLL. We just ensure that the PLL/PHY registers
* of the master and slave are identical
*/
if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
pll_db_commit_14nm(pll_14nm_slave, &conf);
}
pll_db_commit_14nm(pll_14nm, &conf);
return 0;
}
static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
void __iomem *base = pll_14nm->phy->pll_base;
u64 vco_rate, multiplier = BIT(20);
u32 div_frac_start;
u32 dec_start;
u64 ref_clk = parent_rate;
dec_start = readl(base + REG_DSI_14nm_PHY_PLL_DEC_START);
dec_start &= 0x0ff;
DBG("dec_start = %x", dec_start);
div_frac_start = (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
& 0xf) << 16;
div_frac_start |= (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
& 0xff) << 8;
div_frac_start |= readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
& 0xff;
DBG("div_frac_start = %x", div_frac_start);
vco_rate = ref_clk * dec_start;
vco_rate += ((ref_clk * div_frac_start) / multiplier);
/*
* Recalculating the rate from dec_start and frac_start doesn't end up
* the rate we originally set. Convert the freq to KHz, round it up and
* convert it back to MHz.
*/
vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000;
DBG("returning vco rate = %lu", (unsigned long)vco_rate);
return (unsigned long)vco_rate;
}
static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
void __iomem *base = pll_14nm->phy->pll_base;
void __iomem *cmn_base = pll_14nm->phy->base;
bool locked;
DBG("");
if (unlikely(pll_14nm->phy->pll_on))
return 0;
if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1);
writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
POLL_TIMEOUT_US);
if (unlikely(!locked)) {
DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n");
return -EINVAL;
}
DBG("DSI PLL lock success");
pll_14nm->phy->pll_on = true;
return 0;
}
static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
void __iomem *cmn_base = pll_14nm->phy->base;
DBG("");
if (unlikely(!pll_14nm->phy->pll_on))
return;
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
pll_14nm->phy->pll_on = false;
}
static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
if (rate < pll_14nm->phy->cfg->min_pll_rate)
return pll_14nm->phy->cfg->min_pll_rate;
else if (rate > pll_14nm->phy->cfg->max_pll_rate)
return pll_14nm->phy->cfg->max_pll_rate;
else
return rate;
}
static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
.round_rate = dsi_pll_14nm_clk_round_rate,
.set_rate = dsi_pll_14nm_vco_set_rate,
.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
.prepare = dsi_pll_14nm_vco_prepare,
.unprepare = dsi_pll_14nm_vco_unprepare,
};
/*
* N1 and N2 post-divider clock callbacks
*/
#define div_mask(width) ((1 << (width)) - 1)
static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
void __iomem *base = pll_14nm->phy->base;
u8 shift = postdiv->shift;
u8 width = postdiv->width;
u32 val;
DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
val &= div_mask(width);
return divider_recalc_rate(hw, parent_rate, val, NULL,
postdiv->flags, width);
}
static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *prate)
{
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate);
return divider_round_rate(hw, rate, prate, NULL,
postdiv->width,
postdiv->flags);
}
static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
void __iomem *base = pll_14nm->phy->base;
spinlock_t *lock = &pll_14nm->postdiv_lock;
u8 shift = postdiv->shift;
u8 width = postdiv->width;
unsigned int value;
unsigned long flags = 0;
u32 val;
DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate,
parent_rate);
value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
postdiv->flags);
spin_lock_irqsave(lock, flags);
val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
val &= ~(div_mask(width) << shift);
val |= value << shift;
writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
/* If we're master in bonded DSI mode, then the slave PLL's post-dividers
* follow the master's post dividers
*/
if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
void __iomem *slave_base = pll_14nm_slave->phy->base;
writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
}
spin_unlock_irqrestore(lock, flags);
return 0;
}
static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
.recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,
.round_rate = dsi_pll_14nm_postdiv_round_rate,
.set_rate = dsi_pll_14nm_postdiv_set_rate,
};
/*
* PLL Callbacks
*/
static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
void __iomem *cmn_base = pll_14nm->phy->base;
u32 data;
data = readl(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
cached_state->n1postdiv = data & 0xf;
cached_state->n2postdiv = (data >> 4) & 0xf;
DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id,
cached_state->n1postdiv, cached_state->n2postdiv);
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
}
static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
void __iomem *cmn_base = pll_14nm->phy->base;
u32 data;
int ret;
ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
cached_state->vco_rate, 0);
if (ret) {
DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
cached_state->n1postdiv, cached_state->n2postdiv);
writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
/* also restore post-dividers for slave DSI PLL */
if (phy->usecase == MSM_DSI_PHY_MASTER) {
struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
void __iomem *slave_base = pll_14nm_slave->phy->base;
writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
}
return 0;
}
static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
void __iomem *base = phy->pll_base;
u32 clkbuflr_en, bandgap = 0;
switch (phy->usecase) {
case MSM_DSI_PHY_STANDALONE:
clkbuflr_en = 0x1;
break;
case MSM_DSI_PHY_MASTER:
clkbuflr_en = 0x3;
pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX];
break;
case MSM_DSI_PHY_SLAVE:
clkbuflr_en = 0x0;
bandgap = 0x3;
break;
default:
return -EINVAL;
}
writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN);
if (bandgap)
writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP);
return 0;
}
static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
const char *name,
const struct clk_hw *parent_hw,
unsigned long flags,
u8 shift)
{
struct dsi_pll_14nm_postdiv *pll_postdiv;
struct device *dev = &pll_14nm->phy->pdev->dev;
struct clk_init_data postdiv_init = {
.parent_hws = (const struct clk_hw *[]) { parent_hw },
.num_parents = 1,
.name = name,
.flags = flags,
.ops = &clk_ops_dsi_pll_14nm_postdiv,
};
int ret;
pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
if (!pll_postdiv)
return ERR_PTR(-ENOMEM);
pll_postdiv->pll = pll_14nm;
pll_postdiv->shift = shift;
/* both N1 and N2 postdividers are 4 bits wide */
pll_postdiv->width = 4;
/* range of each divider is from 1 to 15 */
pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
pll_postdiv->hw.init = &postdiv_init;
ret = devm_clk_hw_register(dev, &pll_postdiv->hw);
if (ret)
return ERR_PTR(ret);
return &pll_postdiv->hw;
}
static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
{
char clk_name[32];
struct clk_init_data vco_init = {
.parent_data = &(const struct clk_parent_data) {
.fw_name = "ref",
},
.num_parents = 1,
.name = clk_name,
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_ops_dsi_pll_14nm_vco,
};
struct device *dev = &pll_14nm->phy->pdev->dev;
struct clk_hw *hw, *n1_postdiv, *n1_postdivby2;
int ret;
DBG("DSI%d", pll_14nm->phy->id);
snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id);
pll_14nm->clk_hw.init = &vco_init;
ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
if (ret)
return ret;
snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
/* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name,
&pll_14nm->clk_hw, CLK_SET_RATE_PARENT, 0);
if (IS_ERR(n1_postdiv))
return PTR_ERR(n1_postdiv);
snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id);
/* DSI Byte clock = VCO_CLK / N1 / 8 */
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
n1_postdiv, CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw))
return PTR_ERR(hw);
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
/*
* Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
* on the way. Don't let it set parent.
*/
n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev,
clk_name, n1_postdiv, 0, 1, 2);
if (IS_ERR(n1_postdivby2))
return PTR_ERR(n1_postdivby2);
snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id);
/* DSI pixel clock = VCO_CLK / N1 / 2 / N2
* This is the output of N2 post-divider, bits 4-7 in
* REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
*/
hw = pll_14nm_postdiv_register(pll_14nm, clk_name, n1_postdivby2,
0, 4);
if (IS_ERR(hw))
return PTR_ERR(hw);
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
}
static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
struct dsi_pll_14nm *pll_14nm;
int ret;
if (!pdev)
return -ENODEV;
pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
if (!pll_14nm)
return -ENOMEM;
DBG("PLL%d", phy->id);
pll_14nm_list[phy->id] = pll_14nm;
spin_lock_init(&pll_14nm->postdiv_lock);
pll_14nm->phy = phy;
ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
}
phy->vco_hw = &pll_14nm->clk_hw;
return 0;
}
static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
struct msm_dsi_dphy_timing *timing,
int lane_idx)
{
void __iomem *base = phy->lane_base;
bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX);
u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail;
u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst;
u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly;
u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
timing->hs_halfbyte_en;
writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx));
writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly),
base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx));
writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0,
base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx));
writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0),
base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx));
}
static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_clk_request *clk_req)
{
struct msm_dsi_dphy_timing *timing = &phy->timing;
u32 data;
int i;
int ret;
void __iomem *base = phy->base;
void __iomem *lane_base = phy->lane_base;
u32 glbl_test_ctrl;
if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
DRM_DEV_ERROR(&phy->pdev->dev,
"%s: D-PHY timing calculation failed\n",
__func__);
return -EINVAL;
}
data = 0x1c;
if (phy->usecase != MSM_DSI_PHY_STANDALONE)
data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32);
writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
/* 4 data lanes + 1 clk lane configuration */
for (i = 0; i < 5; i++) {
writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i));
writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i));
writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06,
lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i));
writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f,
lane_base + REG_DSI_14nm_PHY_LN_CFG3(i));
writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i));
writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i));
writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i));
dsi_14nm_dphy_set_timing(phy, timing, i);
}
/* Make sure PLL is not start */
writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
wmb(); /* make sure everything is written before reset and enable */
/* reset digital block */
writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
wmb(); /* ensure reset is asserted */
udelay(100);
writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
glbl_test_ctrl = readl(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
else
glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
ret = dsi_14nm_set_usecase(phy);
if (ret) {
DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
__func__, ret);
return ret;
}
/* Remove power down from PLL and all lanes */
writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0);
return 0;
}
static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
{
writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0);
/* ensure that the phy is completely disabled */
wmb();
}
static const struct regulator_bulk_data dsi_phy_14nm_17mA_regulators[] = {
{ .supply = "vcca", .init_load_uA = 17000 },
};
static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = {
{ .supply = "vcca", .init_load_uA = 73400 },
};
const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_14nm_17mA_regulators,
.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
.save_pll_state = dsi_14nm_pll_save_state,
.restore_pll_state = dsi_14nm_pll_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x994400, 0x996400 },
.num_dsi_phy = 2,
};
const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_14nm_73p4mA_regulators,
.num_regulators = ARRAY_SIZE(dsi_phy_14nm_73p4mA_regulators),
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
.save_pll_state = dsi_14nm_pll_save_state,
.restore_pll_state = dsi_14nm_pll_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
};
const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_14nm_17mA_regulators,
.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
.save_pll_state = dsi_14nm_pll_save_state,
.restore_pll_state = dsi_14nm_pll_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
};
const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
.has_phy_lane = true,
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
.save_pll_state = dsi_14nm_pll_save_state,
.restore_pll_state = dsi_14nm_pll_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x5e94400 },
.num_dsi_phy = 1,
};
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lm3533-als.c -- LM3533 Ambient Light Sensor driver
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <[email protected]>
*/
#include <linux/atomic.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/mfd/lm3533.h>
#define LM3533_ALS_RESISTOR_MIN 1
#define LM3533_ALS_RESISTOR_MAX 127
#define LM3533_ALS_CHANNEL_CURRENT_MAX 2
#define LM3533_ALS_THRESH_MAX 3
#define LM3533_ALS_ZONE_MAX 4
#define LM3533_REG_ALS_RESISTOR_SELECT 0x30
#define LM3533_REG_ALS_CONF 0x31
#define LM3533_REG_ALS_ZONE_INFO 0x34
#define LM3533_REG_ALS_READ_ADC_RAW 0x37
#define LM3533_REG_ALS_READ_ADC_AVERAGE 0x38
#define LM3533_REG_ALS_BOUNDARY_BASE 0x50
#define LM3533_REG_ALS_TARGET_BASE 0x60
#define LM3533_ALS_ENABLE_MASK 0x01
#define LM3533_ALS_INPUT_MODE_MASK 0x02
#define LM3533_ALS_INT_ENABLE_MASK 0x01
#define LM3533_ALS_ZONE_SHIFT 2
#define LM3533_ALS_ZONE_MASK 0x1c
#define LM3533_ALS_FLAG_INT_ENABLED 1
struct lm3533_als {
struct lm3533 *lm3533;
struct platform_device *pdev;
unsigned long flags;
int irq;
atomic_t zone;
struct mutex thresh_mutex;
};
static int lm3533_als_get_adc(struct iio_dev *indio_dev, bool average,
int *adc)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
u8 val;
int ret;
if (average)
reg = LM3533_REG_ALS_READ_ADC_AVERAGE;
else
reg = LM3533_REG_ALS_READ_ADC_RAW;
ret = lm3533_read(als->lm3533, reg, &val);
if (ret) {
dev_err(&indio_dev->dev, "failed to read adc\n");
return ret;
}
*adc = val;
return 0;
}
static int _lm3533_als_get_zone(struct iio_dev *indio_dev, u8 *zone)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 val;
int ret;
ret = lm3533_read(als->lm3533, LM3533_REG_ALS_ZONE_INFO, &val);
if (ret) {
dev_err(&indio_dev->dev, "failed to read zone\n");
return ret;
}
val = (val & LM3533_ALS_ZONE_MASK) >> LM3533_ALS_ZONE_SHIFT;
*zone = min_t(u8, val, LM3533_ALS_ZONE_MAX);
return 0;
}
static int lm3533_als_get_zone(struct iio_dev *indio_dev, u8 *zone)
{
struct lm3533_als *als = iio_priv(indio_dev);
int ret;
if (test_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags)) {
*zone = atomic_read(&als->zone);
} else {
ret = _lm3533_als_get_zone(indio_dev, zone);
if (ret)
return ret;
}
return 0;
}
/*
* channel output channel 0..2
* zone zone 0..4
*/
static inline u8 lm3533_als_get_target_reg(unsigned channel, unsigned zone)
{
return LM3533_REG_ALS_TARGET_BASE + 5 * channel + zone;
}
static int lm3533_als_get_target(struct iio_dev *indio_dev, unsigned channel,
unsigned zone, u8 *val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
int ret;
if (channel > LM3533_ALS_CHANNEL_CURRENT_MAX)
return -EINVAL;
if (zone > LM3533_ALS_ZONE_MAX)
return -EINVAL;
reg = lm3533_als_get_target_reg(channel, zone);
ret = lm3533_read(als->lm3533, reg, val);
if (ret)
dev_err(&indio_dev->dev, "failed to get target current\n");
return ret;
}
static int lm3533_als_set_target(struct iio_dev *indio_dev, unsigned channel,
unsigned zone, u8 val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
int ret;
if (channel > LM3533_ALS_CHANNEL_CURRENT_MAX)
return -EINVAL;
if (zone > LM3533_ALS_ZONE_MAX)
return -EINVAL;
reg = lm3533_als_get_target_reg(channel, zone);
ret = lm3533_write(als->lm3533, reg, val);
if (ret)
dev_err(&indio_dev->dev, "failed to set target current\n");
return ret;
}
static int lm3533_als_get_current(struct iio_dev *indio_dev, unsigned channel,
int *val)
{
u8 zone;
u8 target;
int ret;
ret = lm3533_als_get_zone(indio_dev, &zone);
if (ret)
return ret;
ret = lm3533_als_get_target(indio_dev, channel, zone, &target);
if (ret)
return ret;
*val = target;
return 0;
}
static int lm3533_als_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
ret = lm3533_als_get_adc(indio_dev, false, val);
break;
case IIO_CURRENT:
ret = lm3533_als_get_current(indio_dev, chan->channel,
val);
break;
default:
return -EINVAL;
}
break;
case IIO_CHAN_INFO_AVERAGE_RAW:
ret = lm3533_als_get_adc(indio_dev, true, val);
break;
default:
return -EINVAL;
}
if (ret)
return ret;
return IIO_VAL_INT;
}
#define CHANNEL_CURRENT(_channel) \
{ \
.type = IIO_CURRENT, \
.channel = _channel, \
.indexed = true, \
.output = true, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
}
static const struct iio_chan_spec lm3533_als_channels[] = {
{
.type = IIO_LIGHT,
.channel = 0,
.indexed = true,
.info_mask_separate = BIT(IIO_CHAN_INFO_AVERAGE_RAW) |
BIT(IIO_CHAN_INFO_RAW),
},
CHANNEL_CURRENT(0),
CHANNEL_CURRENT(1),
CHANNEL_CURRENT(2),
};
static irqreturn_t lm3533_als_isr(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct lm3533_als *als = iio_priv(indio_dev);
u8 zone;
int ret;
/* Clear interrupt by reading the ALS zone register. */
ret = _lm3533_als_get_zone(indio_dev, &zone);
if (ret)
goto out;
atomic_set(&als->zone, zone);
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
out:
return IRQ_HANDLED;
}
static int lm3533_als_set_int_mode(struct iio_dev *indio_dev, int enable)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 mask = LM3533_ALS_INT_ENABLE_MASK;
u8 val;
int ret;
if (enable)
val = mask;
else
val = 0;
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, val, mask);
if (ret) {
dev_err(&indio_dev->dev, "failed to set int mode %d\n",
enable);
return ret;
}
return 0;
}
static int lm3533_als_get_int_mode(struct iio_dev *indio_dev, int *enable)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 mask = LM3533_ALS_INT_ENABLE_MASK;
u8 val;
int ret;
ret = lm3533_read(als->lm3533, LM3533_REG_ALS_ZONE_INFO, &val);
if (ret) {
dev_err(&indio_dev->dev, "failed to get int mode\n");
return ret;
}
*enable = !!(val & mask);
return 0;
}
static inline u8 lm3533_als_get_threshold_reg(unsigned nr, bool raising)
{
u8 offset = !raising;
return LM3533_REG_ALS_BOUNDARY_BASE + 2 * nr + offset;
}
static int lm3533_als_get_threshold(struct iio_dev *indio_dev, unsigned nr,
bool raising, u8 *val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
int ret;
if (nr > LM3533_ALS_THRESH_MAX)
return -EINVAL;
reg = lm3533_als_get_threshold_reg(nr, raising);
ret = lm3533_read(als->lm3533, reg, val);
if (ret)
dev_err(&indio_dev->dev, "failed to get threshold\n");
return ret;
}
static int lm3533_als_set_threshold(struct iio_dev *indio_dev, unsigned nr,
bool raising, u8 val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 val2;
u8 reg, reg2;
int ret;
if (nr > LM3533_ALS_THRESH_MAX)
return -EINVAL;
reg = lm3533_als_get_threshold_reg(nr, raising);
reg2 = lm3533_als_get_threshold_reg(nr, !raising);
mutex_lock(&als->thresh_mutex);
ret = lm3533_read(als->lm3533, reg2, &val2);
if (ret) {
dev_err(&indio_dev->dev, "failed to get threshold\n");
goto out;
}
/*
* This device does not allow negative hysteresis (in fact, it uses
* whichever value is smaller as the lower bound) so we need to make
* sure that thresh_falling <= thresh_raising.
*/
if ((raising && (val < val2)) || (!raising && (val > val2))) {
ret = -EINVAL;
goto out;
}
ret = lm3533_write(als->lm3533, reg, val);
if (ret) {
dev_err(&indio_dev->dev, "failed to set threshold\n");
goto out;
}
out:
mutex_unlock(&als->thresh_mutex);
return ret;
}
static int lm3533_als_get_hysteresis(struct iio_dev *indio_dev, unsigned nr,
u8 *val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 falling;
u8 raising;
int ret;
if (nr > LM3533_ALS_THRESH_MAX)
return -EINVAL;
mutex_lock(&als->thresh_mutex);
ret = lm3533_als_get_threshold(indio_dev, nr, false, &falling);
if (ret)
goto out;
ret = lm3533_als_get_threshold(indio_dev, nr, true, &raising);
if (ret)
goto out;
*val = raising - falling;
out:
mutex_unlock(&als->thresh_mutex);
return ret;
}
static ssize_t show_thresh_either_en(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als *als = iio_priv(indio_dev);
int enable;
int ret;
if (als->irq) {
ret = lm3533_als_get_int_mode(indio_dev, &enable);
if (ret)
return ret;
} else {
enable = 0;
}
return sysfs_emit(buf, "%u\n", enable);
}
static ssize_t store_thresh_either_en(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als *als = iio_priv(indio_dev);
unsigned long enable;
bool int_enabled;
u8 zone;
int ret;
if (!als->irq)
return -EBUSY;
if (kstrtoul(buf, 0, &enable))
return -EINVAL;
int_enabled = test_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
if (enable && !int_enabled) {
ret = lm3533_als_get_zone(indio_dev, &zone);
if (ret)
return ret;
atomic_set(&als->zone, zone);
set_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
}
ret = lm3533_als_set_int_mode(indio_dev, enable);
if (ret) {
if (!int_enabled)
clear_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
return ret;
}
if (!enable)
clear_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
return len;
}
static ssize_t show_zone(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
u8 zone;
int ret;
ret = lm3533_als_get_zone(indio_dev, &zone);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", zone);
}
enum lm3533_als_attribute_type {
LM3533_ATTR_TYPE_HYSTERESIS,
LM3533_ATTR_TYPE_TARGET,
LM3533_ATTR_TYPE_THRESH_FALLING,
LM3533_ATTR_TYPE_THRESH_RAISING,
};
struct lm3533_als_attribute {
struct device_attribute dev_attr;
enum lm3533_als_attribute_type type;
u8 val1;
u8 val2;
};
static inline struct lm3533_als_attribute *
to_lm3533_als_attr(struct device_attribute *attr)
{
return container_of(attr, struct lm3533_als_attribute, dev_attr);
}
static ssize_t show_als_attr(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als_attribute *als_attr = to_lm3533_als_attr(attr);
u8 val;
int ret;
switch (als_attr->type) {
case LM3533_ATTR_TYPE_HYSTERESIS:
ret = lm3533_als_get_hysteresis(indio_dev, als_attr->val1,
&val);
break;
case LM3533_ATTR_TYPE_TARGET:
ret = lm3533_als_get_target(indio_dev, als_attr->val1,
als_attr->val2, &val);
break;
case LM3533_ATTR_TYPE_THRESH_FALLING:
ret = lm3533_als_get_threshold(indio_dev, als_attr->val1,
false, &val);
break;
case LM3533_ATTR_TYPE_THRESH_RAISING:
ret = lm3533_als_get_threshold(indio_dev, als_attr->val1,
true, &val);
break;
default:
ret = -ENXIO;
}
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", val);
}
static ssize_t store_als_attr(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als_attribute *als_attr = to_lm3533_als_attr(attr);
u8 val;
int ret;
if (kstrtou8(buf, 0, &val))
return -EINVAL;
switch (als_attr->type) {
case LM3533_ATTR_TYPE_TARGET:
ret = lm3533_als_set_target(indio_dev, als_attr->val1,
als_attr->val2, val);
break;
case LM3533_ATTR_TYPE_THRESH_FALLING:
ret = lm3533_als_set_threshold(indio_dev, als_attr->val1,
false, val);
break;
case LM3533_ATTR_TYPE_THRESH_RAISING:
ret = lm3533_als_set_threshold(indio_dev, als_attr->val1,
true, val);
break;
default:
ret = -ENXIO;
}
if (ret)
return ret;
return len;
}
#define ALS_ATTR(_name, _mode, _show, _store, _type, _val1, _val2) \
{ .dev_attr = __ATTR(_name, _mode, _show, _store), \
.type = _type, \
.val1 = _val1, \
.val2 = _val2 }
#define LM3533_ALS_ATTR(_name, _mode, _show, _store, _type, _val1, _val2) \
struct lm3533_als_attribute lm3533_als_attr_##_name = \
ALS_ATTR(_name, _mode, _show, _store, _type, _val1, _val2)
#define ALS_TARGET_ATTR_RW(_channel, _zone) \
LM3533_ALS_ATTR(out_current##_channel##_current##_zone##_raw, \
S_IRUGO | S_IWUSR, \
show_als_attr, store_als_attr, \
LM3533_ATTR_TYPE_TARGET, _channel, _zone)
/*
* ALS output current values (ALS mapper targets)
*
* out_current[0-2]_current[0-4]_raw 0-255
*/
static ALS_TARGET_ATTR_RW(0, 0);
static ALS_TARGET_ATTR_RW(0, 1);
static ALS_TARGET_ATTR_RW(0, 2);
static ALS_TARGET_ATTR_RW(0, 3);
static ALS_TARGET_ATTR_RW(0, 4);
static ALS_TARGET_ATTR_RW(1, 0);
static ALS_TARGET_ATTR_RW(1, 1);
static ALS_TARGET_ATTR_RW(1, 2);
static ALS_TARGET_ATTR_RW(1, 3);
static ALS_TARGET_ATTR_RW(1, 4);
static ALS_TARGET_ATTR_RW(2, 0);
static ALS_TARGET_ATTR_RW(2, 1);
static ALS_TARGET_ATTR_RW(2, 2);
static ALS_TARGET_ATTR_RW(2, 3);
static ALS_TARGET_ATTR_RW(2, 4);
#define ALS_THRESH_FALLING_ATTR_RW(_nr) \
LM3533_ALS_ATTR(in_illuminance0_thresh##_nr##_falling_value, \
S_IRUGO | S_IWUSR, \
show_als_attr, store_als_attr, \
LM3533_ATTR_TYPE_THRESH_FALLING, _nr, 0)
#define ALS_THRESH_RAISING_ATTR_RW(_nr) \
LM3533_ALS_ATTR(in_illuminance0_thresh##_nr##_raising_value, \
S_IRUGO | S_IWUSR, \
show_als_attr, store_als_attr, \
LM3533_ATTR_TYPE_THRESH_RAISING, _nr, 0)
/*
* ALS Zone thresholds (boundaries)
*
* in_illuminance0_thresh[0-3]_falling_value 0-255
* in_illuminance0_thresh[0-3]_raising_value 0-255
*/
static ALS_THRESH_FALLING_ATTR_RW(0);
static ALS_THRESH_FALLING_ATTR_RW(1);
static ALS_THRESH_FALLING_ATTR_RW(2);
static ALS_THRESH_FALLING_ATTR_RW(3);
static ALS_THRESH_RAISING_ATTR_RW(0);
static ALS_THRESH_RAISING_ATTR_RW(1);
static ALS_THRESH_RAISING_ATTR_RW(2);
static ALS_THRESH_RAISING_ATTR_RW(3);
#define ALS_HYSTERESIS_ATTR_RO(_nr) \
LM3533_ALS_ATTR(in_illuminance0_thresh##_nr##_hysteresis, \
S_IRUGO, show_als_attr, NULL, \
LM3533_ATTR_TYPE_HYSTERESIS, _nr, 0)
/*
* ALS Zone threshold hysteresis
*
* threshY_hysteresis = threshY_raising - threshY_falling
*
* in_illuminance0_thresh[0-3]_hysteresis 0-255
* in_illuminance0_thresh[0-3]_hysteresis 0-255
*/
static ALS_HYSTERESIS_ATTR_RO(0);
static ALS_HYSTERESIS_ATTR_RO(1);
static ALS_HYSTERESIS_ATTR_RO(2);
static ALS_HYSTERESIS_ATTR_RO(3);
#define ILLUMINANCE_ATTR_RO(_name) \
DEVICE_ATTR(in_illuminance0_##_name, S_IRUGO, show_##_name, NULL)
#define ILLUMINANCE_ATTR_RW(_name) \
DEVICE_ATTR(in_illuminance0_##_name, S_IRUGO | S_IWUSR, \
show_##_name, store_##_name)
/*
* ALS Zone threshold-event enable
*
* in_illuminance0_thresh_either_en 0,1
*/
static ILLUMINANCE_ATTR_RW(thresh_either_en);
/*
* ALS Current Zone
*
* in_illuminance0_zone 0-4
*/
static ILLUMINANCE_ATTR_RO(zone);
static struct attribute *lm3533_als_event_attributes[] = {
&dev_attr_in_illuminance0_thresh_either_en.attr,
&lm3533_als_attr_in_illuminance0_thresh0_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh0_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh0_raising_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh1_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh1_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh1_raising_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh2_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh2_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh2_raising_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh3_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh3_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh3_raising_value.dev_attr.attr,
NULL
};
static const struct attribute_group lm3533_als_event_attribute_group = {
.attrs = lm3533_als_event_attributes
};
static struct attribute *lm3533_als_attributes[] = {
&dev_attr_in_illuminance0_zone.attr,
&lm3533_als_attr_out_current0_current0_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current1_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current2_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current3_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current4_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current0_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current1_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current2_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current3_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current4_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current0_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current1_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current2_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current3_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current4_raw.dev_attr.attr,
NULL
};
static const struct attribute_group lm3533_als_attribute_group = {
.attrs = lm3533_als_attributes
};
static int lm3533_als_set_input_mode(struct lm3533_als *als, bool pwm_mode)
{
u8 mask = LM3533_ALS_INPUT_MODE_MASK;
u8 val;
int ret;
if (pwm_mode)
val = mask; /* pwm input */
else
val = 0; /* analog input */
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, val, mask);
if (ret) {
dev_err(&als->pdev->dev, "failed to set input mode %d\n",
pwm_mode);
return ret;
}
return 0;
}
static int lm3533_als_set_resistor(struct lm3533_als *als, u8 val)
{
int ret;
if (val < LM3533_ALS_RESISTOR_MIN || val > LM3533_ALS_RESISTOR_MAX) {
dev_err(&als->pdev->dev, "invalid resistor value\n");
return -EINVAL;
}
ret = lm3533_write(als->lm3533, LM3533_REG_ALS_RESISTOR_SELECT, val);
if (ret) {
dev_err(&als->pdev->dev, "failed to set resistor\n");
return ret;
}
return 0;
}
static int lm3533_als_setup(struct lm3533_als *als,
const struct lm3533_als_platform_data *pdata)
{
int ret;
ret = lm3533_als_set_input_mode(als, pdata->pwm_mode);
if (ret)
return ret;
/* ALS input is always high impedance in PWM-mode. */
if (!pdata->pwm_mode) {
ret = lm3533_als_set_resistor(als, pdata->r_select);
if (ret)
return ret;
}
return 0;
}
static int lm3533_als_setup_irq(struct lm3533_als *als, void *dev)
{
u8 mask = LM3533_ALS_INT_ENABLE_MASK;
int ret;
/* Make sure interrupts are disabled. */
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, 0, mask);
if (ret) {
dev_err(&als->pdev->dev, "failed to disable interrupts\n");
return ret;
}
ret = request_threaded_irq(als->irq, NULL, lm3533_als_isr,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
dev_name(&als->pdev->dev), dev);
if (ret) {
dev_err(&als->pdev->dev, "failed to request irq %d\n",
als->irq);
return ret;
}
return 0;
}
static int lm3533_als_enable(struct lm3533_als *als)
{
u8 mask = LM3533_ALS_ENABLE_MASK;
int ret;
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, mask, mask);
if (ret)
dev_err(&als->pdev->dev, "failed to enable ALS\n");
return ret;
}
static int lm3533_als_disable(struct lm3533_als *als)
{
u8 mask = LM3533_ALS_ENABLE_MASK;
int ret;
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, 0, mask);
if (ret)
dev_err(&als->pdev->dev, "failed to disable ALS\n");
return ret;
}
static const struct iio_info lm3533_als_info = {
.attrs = &lm3533_als_attribute_group,
.event_attrs = &lm3533_als_event_attribute_group,
.read_raw = &lm3533_als_read_raw,
};
static int lm3533_als_probe(struct platform_device *pdev)
{
const struct lm3533_als_platform_data *pdata;
struct lm3533 *lm3533;
struct lm3533_als *als;
struct iio_dev *indio_dev;
int ret;
lm3533 = dev_get_drvdata(pdev->dev.parent);
if (!lm3533)
return -EINVAL;
pdata = dev_get_platdata(&pdev->dev);
if (!pdata) {
dev_err(&pdev->dev, "no platform data\n");
return -EINVAL;
}
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*als));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &lm3533_als_info;
indio_dev->channels = lm3533_als_channels;
indio_dev->num_channels = ARRAY_SIZE(lm3533_als_channels);
indio_dev->name = dev_name(&pdev->dev);
iio_device_set_parent(indio_dev, pdev->dev.parent);
indio_dev->modes = INDIO_DIRECT_MODE;
als = iio_priv(indio_dev);
als->lm3533 = lm3533;
als->pdev = pdev;
als->irq = lm3533->irq;
atomic_set(&als->zone, 0);
mutex_init(&als->thresh_mutex);
platform_set_drvdata(pdev, indio_dev);
if (als->irq) {
ret = lm3533_als_setup_irq(als, indio_dev);
if (ret)
return ret;
}
ret = lm3533_als_setup(als, pdata);
if (ret)
goto err_free_irq;
ret = lm3533_als_enable(als);
if (ret)
goto err_free_irq;
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&pdev->dev, "failed to register ALS\n");
goto err_disable;
}
return 0;
err_disable:
lm3533_als_disable(als);
err_free_irq:
if (als->irq)
free_irq(als->irq, indio_dev);
return ret;
}
static void lm3533_als_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct lm3533_als *als = iio_priv(indio_dev);
lm3533_als_set_int_mode(indio_dev, false);
iio_device_unregister(indio_dev);
lm3533_als_disable(als);
if (als->irq)
free_irq(als->irq, indio_dev);
}
static struct platform_driver lm3533_als_driver = {
.driver = {
.name = "lm3533-als",
},
.probe = lm3533_als_probe,
.remove = lm3533_als_remove,
};
module_platform_driver(lm3533_als_driver);
MODULE_AUTHOR("Johan Hovold <[email protected]>");
MODULE_DESCRIPTION("LM3533 Ambient Light Sensor driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lm3533-als");
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pps-ktimer.c -- kernel timer test client
*
* Copyright (C) 2005-2006 Rodolfo Giometti <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/time.h>
#include <linux/timer.h>
#include <linux/pps_kernel.h>
/*
* Global variables
*/
static struct pps_device *pps;
static struct timer_list ktimer;
/*
* The kernel timer
*/
static void pps_ktimer_event(struct timer_list *unused)
{
struct pps_event_time ts;
/* First of all we get the time stamp... */
pps_get_ts(&ts);
pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL);
mod_timer(&ktimer, jiffies + HZ);
}
/*
* The PPS info struct
*/
static struct pps_source_info pps_ktimer_info = {
.name = "ktimer",
.path = "",
.mode = PPS_CAPTUREASSERT | PPS_OFFSETASSERT |
PPS_ECHOASSERT |
PPS_CANWAIT | PPS_TSFMT_TSPEC,
.owner = THIS_MODULE,
};
/*
* Module staff
*/
static void __exit pps_ktimer_exit(void)
{
dev_info(pps->dev, "ktimer PPS source unregistered\n");
del_timer_sync(&ktimer);
pps_unregister_source(pps);
}
static int __init pps_ktimer_init(void)
{
pps = pps_register_source(&pps_ktimer_info,
PPS_CAPTUREASSERT | PPS_OFFSETASSERT);
if (IS_ERR(pps)) {
pr_err("cannot register PPS source\n");
return PTR_ERR(pps);
}
timer_setup(&ktimer, pps_ktimer_event, 0);
mod_timer(&ktimer, jiffies + HZ);
dev_info(pps->dev, "ktimer PPS source registered\n");
return 0;
}
module_init(pps_ktimer_init);
module_exit(pps_ktimer_exit);
MODULE_AUTHOR("Rodolfo Giometti <[email protected]>");
MODULE_DESCRIPTION("dummy PPS source by using a kernel timer (just for debug)");
MODULE_LICENSE("GPL");
|
// SPDX-License-Identifier: GPL-2.0
#include "../kernel/machine_kexec_reloc.c"
|
/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _I915_COMPONENT_H_
#define _I915_COMPONENT_H_
#include <drm/drm_audio_component.h>
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
I915_COMPONENT_PXP,
I915_COMPONENT_GSC_PROXY,
};
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
#define MAX_PORTS 9
/**
* struct i915_audio_component - Used for direct communication between i915 and hda drivers
*/
struct i915_audio_component {
/**
* @base: the drm_audio_component base class
*/
struct drm_audio_component base;
/**
* @aud_sample_rate: the array of audio sample rate per port
*/
int aud_sample_rate[MAX_PORTS];
};
#endif /* _I915_COMPONENT_H_ */
|
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _UAPI_SPARC_TERMIOS_H
#define _UAPI_SPARC_TERMIOS_H
#include <asm/ioctls.h>
#include <asm/termbits.h>
#if defined(__KERNEL__) || defined(__DEFINE_BSD_TERMIOS)
struct sgttyb {
char sg_ispeed;
char sg_ospeed;
char sg_erase;
char sg_kill;
short sg_flags;
};
struct tchars {
char t_intrc;
char t_quitc;
char t_startc;
char t_stopc;
char t_eofc;
char t_brkc;
};
struct ltchars {
char t_suspc;
char t_dsuspc;
char t_rprntc;
char t_flushc;
char t_werasc;
char t_lnextc;
};
#endif /* __KERNEL__ */
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
unsigned short ws_xpixel;
unsigned short ws_ypixel;
};
#define NCC 8
struct termio {
unsigned short c_iflag; /* input mode flags */
unsigned short c_oflag; /* output mode flags */
unsigned short c_cflag; /* control mode flags */
unsigned short c_lflag; /* local mode flags */
unsigned char c_line; /* line discipline */
unsigned char c_cc[NCC]; /* control characters */
};
#endif /* _UAPI_SPARC_TERMIOS_H */
|
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Wave5 series multi-standard codec IP - low level access functions
*
* Copyright (C) 2021-2023 CHIPS&MEDIA INC
*/
#include <linux/bug.h>
#include "wave5-vdi.h"
#include "wave5-vpu.h"
#include "wave5-regdefine.h"
#include <linux/delay.h>
static int wave5_vdi_allocate_common_memory(struct device *dev)
{
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
if (!vpu_dev->common_mem.vaddr) {
int ret;
if (vpu_dev->product_code == WAVE515_CODE)
vpu_dev->common_mem.size = WAVE515_SIZE_COMMON;
else
vpu_dev->common_mem.size = WAVE521_SIZE_COMMON;
ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vpu_dev->common_mem);
if (ret) {
dev_err(dev, "unable to allocate common buffer\n");
return ret;
}
}
dev_dbg(dev, "[VDI] common_mem: daddr=%pad size=%zu vaddr=0x%p\n",
&vpu_dev->common_mem.daddr, vpu_dev->common_mem.size, vpu_dev->common_mem.vaddr);
return 0;
}
int wave5_vdi_init(struct device *dev)
{
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
int ret;
ret = wave5_vdi_allocate_common_memory(dev);
if (ret < 0) {
dev_err(dev, "[VDI] failed to get vpu common buffer from driver\n");
return ret;
}
if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) {
WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev->product_code);
return -EOPNOTSUPP;
}
/* if BIT processor is not running. */
if (wave5_vdi_read_register(vpu_dev, W5_VCPU_CUR_PC) == 0) {
int i;
for (i = 0; i < 64; i++)
wave5_vdi_write_register(vpu_dev, (i * 4) + 0x100, 0x0);
}
dev_dbg(dev, "[VDI] driver initialized successfully\n");
return 0;
}
int wave5_vdi_release(struct device *dev)
{
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
vpu_dev->vdb_register = NULL;
wave5_vdi_free_dma_memory(vpu_dev, &vpu_dev->common_mem);
return 0;
}
void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data)
{
writel(data, vpu_dev->vdb_register + addr);
}
unsigned int wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr)
{
return readl(vpu_dev->vdb_register + addr);
}
int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
{
if (!vb || !vb->vaddr) {
dev_err(vpu_dev->dev, "%s: unable to clear unmapped buffer\n", __func__);
return -EINVAL;
}
memset(vb->vaddr, 0, vb->size);
return vb->size;
}
int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,
u8 *data, size_t len)
{
if (!vb || !vb->vaddr) {
dev_err(vpu_dev->dev, "%s: unable to write to unmapped buffer\n", __func__);
return -EINVAL;
}
if (offset > vb->size || len > vb->size || offset + len > vb->size) {
dev_err(vpu_dev->dev, "%s: buffer too small\n", __func__);
return -ENOSPC;
}
memcpy(vb->vaddr + offset, data, len);
return len;
}
int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
{
void *vaddr;
dma_addr_t daddr;
if (!vb->size) {
dev_err(vpu_dev->dev, "%s: requested size==0\n", __func__);
return -EINVAL;
}
vaddr = dma_alloc_coherent(vpu_dev->dev, vb->size, &daddr, GFP_KERNEL);
if (!vaddr)
return -ENOMEM;
vb->vaddr = vaddr;
vb->daddr = daddr;
return 0;
}
int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
{
if (vb->size == 0)
return -EINVAL;
if (!vb->vaddr)
dev_err(vpu_dev->dev, "%s: requested free of unmapped buffer\n", __func__);
else
dma_free_coherent(vpu_dev->dev, vb->size, vb->vaddr, vb->daddr);
memset(vb, 0, sizeof(*vb));
return 0;
}
int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count,
size_t size)
{
struct vpu_buf vb_buf;
int i, ret = 0;
vb_buf.size = size;
for (i = 0; i < count; i++) {
if (array[i].size == size)
continue;
if (array[i].size != 0)
wave5_vdi_free_dma_memory(vpu_dev, &array[i]);
ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_buf);
if (ret)
return -ENOMEM;
array[i] = vb_buf;
}
for (i = count; i < MAX_REG_FRAME; i++)
wave5_vdi_free_dma_memory(vpu_dev, &array[i]);
return 0;
}
void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev)
{
struct vpu_buf *vb = &vpu_dev->sram_buf;
dma_addr_t daddr;
void *vaddr;
size_t size;
if (!vpu_dev->sram_pool || vb->vaddr)
return;
size = min_t(size_t, vpu_dev->sram_size, gen_pool_avail(vpu_dev->sram_pool));
vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, size, &daddr);
if (vaddr) {
vb->vaddr = vaddr;
vb->daddr = daddr;
vb->size = size;
}
dev_dbg(vpu_dev->dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n",
__func__, &vb->daddr, vb->size, vb->vaddr);
}
void wave5_vdi_free_sram(struct vpu_device *vpu_dev)
{
struct vpu_buf *vb = &vpu_dev->sram_buf;
if (!vb->size || !vb->vaddr)
return;
gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr, vb->size);
memset(vb, 0, sizeof(*vb));
}
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Common CPM code
*
* Author: Scott Wood <[email protected]>
*
* Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
*
* Some parts derived from commproc.c/cpm2_common.c, which is:
* Copyright (c) 1997 Dan error_act ([email protected])
* Copyright (c) 1999-2001 Dan Malek <[email protected]>
* Copyright (c) 2000 MontaVista Software, Inc ([email protected])
* 2006 (c) MontaVista Software, Inc.
* Vitaly Bordug <[email protected]>
*/
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/export.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <asm/udbg.h>
#include <asm/io.h>
#include <asm/cpm.h>
#include <asm/fixmap.h>
#include <soc/fsl/qe/qe.h>
#include <mm/mmu_decl.h>
#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
#include <linux/gpio/legacy-of-mm-gpiochip.h>
#endif
static int __init cpm_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
if (!np)
np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
if (!np)
return -ENODEV;
cpm_muram_init();
of_node_put(np);
return 0;
}
subsys_initcall(cpm_init);
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc;
static u8 __iomem *cpm_udbg_txbuf;
static void udbg_putc_cpm(char c)
{
if (c == '\n')
udbg_putc_cpm('\r');
while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
;
out_8(cpm_udbg_txbuf, c);
out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
}
void __init udbg_init_cpm(void)
{
#ifdef CONFIG_PPC_8xx
mmu_mapin_immr();
cpm_udbg_txdesc = (u32 __iomem __force *)
(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
VIRT_IMMR_BASE);
cpm_udbg_txbuf = (u8 __iomem __force *)
(in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
VIRT_IMMR_BASE);
#else
cpm_udbg_txdesc = (u32 __iomem __force *)
CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
#endif
if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
#endif
udbg_putc = udbg_putc_cpm;
}
}
#endif
#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
struct cpm2_ioports {
u32 dir, par, sor, odr, dat;
u32 res[3];
};
struct cpm2_gpio32_chip {
struct of_mm_gpio_chip mm_gc;
spinlock_t lock;
/* shadowed data register to clear/set bits safely */
u32 cpdata;
};
static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
{
struct cpm2_gpio32_chip *cpm2_gc =
container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
struct cpm2_ioports __iomem *iop = mm_gc->regs;
cpm2_gc->cpdata = in_be32(&iop->dat);
}
static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm2_ioports __iomem *iop = mm_gc->regs;
u32 pin_mask;
pin_mask = 1 << (31 - gpio);
return !!(in_be32(&iop->dat) & pin_mask);
}
static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
int value)
{
struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm2_ioports __iomem *iop = mm_gc->regs;
if (value)
cpm2_gc->cpdata |= pin_mask;
else
cpm2_gc->cpdata &= ~pin_mask;
out_be32(&iop->dat, cpm2_gc->cpdata);
}
static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm2_gc->lock, flags);
__cpm2_gpio32_set(mm_gc, pin_mask, value);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
}
static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
struct cpm2_ioports __iomem *iop = mm_gc->regs;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm2_gc->lock, flags);
setbits32(&iop->dir, pin_mask);
__cpm2_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
return 0;
}
static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
struct cpm2_ioports __iomem *iop = mm_gc->regs;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm2_gc->lock, flags);
clrbits32(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
return 0;
}
int cpm2_gpiochip_add32(struct device *dev)
{
struct device_node *np = dev->of_node;
struct cpm2_gpio32_chip *cpm2_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
if (!cpm2_gc)
return -ENOMEM;
spin_lock_init(&cpm2_gc->lock);
mm_gc = &cpm2_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = cpm2_gpio32_save_regs;
gc->ngpio = 32;
gc->direction_input = cpm2_gpio32_dir_in;
gc->direction_output = cpm2_gpio32_dir_out;
gc->get = cpm2_gpio32_get;
gc->set = cpm2_gpio32_set;
gc->parent = dev;
gc->owner = THIS_MODULE;
return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
}
#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* Broadcom Blutonium firmware driver
*
* Copyright (C) 2003 Maxim Krasnyansky <[email protected]>
* Copyright (C) 2003 Marcel Holtmann <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/usb.h>
#include <net/bluetooth/bluetooth.h>
#define VERSION "1.2"
static const struct usb_device_id bcm203x_table[] = {
/* Broadcom Blutonium (BCM2033) */
{ USB_DEVICE(0x0a5c, 0x2033) },
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, bcm203x_table);
#define BCM203X_ERROR 0
#define BCM203X_RESET 1
#define BCM203X_LOAD_MINIDRV 2
#define BCM203X_SELECT_MEMORY 3
#define BCM203X_CHECK_MEMORY 4
#define BCM203X_LOAD_FIRMWARE 5
#define BCM203X_CHECK_FIRMWARE 6
#define BCM203X_IN_EP 0x81
#define BCM203X_OUT_EP 0x02
struct bcm203x_data {
struct usb_device *udev;
unsigned long state;
struct work_struct work;
atomic_t shutdown;
struct urb *urb;
unsigned char *buffer;
unsigned char *fw_data;
unsigned int fw_size;
unsigned int fw_sent;
};
static void bcm203x_complete(struct urb *urb)
{
struct bcm203x_data *data = urb->context;
struct usb_device *udev = urb->dev;
int len;
BT_DBG("udev %p urb %p", udev, urb);
if (urb->status) {
BT_ERR("URB failed with status %d", urb->status);
data->state = BCM203X_ERROR;
return;
}
switch (data->state) {
case BCM203X_LOAD_MINIDRV:
memcpy(data->buffer, "#", 1);
usb_fill_bulk_urb(urb, udev, usb_sndbulkpipe(udev, BCM203X_OUT_EP),
data->buffer, 1, bcm203x_complete, data);
data->state = BCM203X_SELECT_MEMORY;
/* use workqueue to have a small delay */
schedule_work(&data->work);
break;
case BCM203X_SELECT_MEMORY:
usb_fill_int_urb(urb, udev, usb_rcvintpipe(udev, BCM203X_IN_EP),
data->buffer, 32, bcm203x_complete, data, 1);
data->state = BCM203X_CHECK_MEMORY;
if (usb_submit_urb(data->urb, GFP_ATOMIC) < 0)
BT_ERR("Can't submit URB");
break;
case BCM203X_CHECK_MEMORY:
if (data->buffer[0] != '#') {
BT_ERR("Memory select failed");
data->state = BCM203X_ERROR;
break;
}
data->state = BCM203X_LOAD_FIRMWARE;
fallthrough;
case BCM203X_LOAD_FIRMWARE:
if (data->fw_sent == data->fw_size) {
usb_fill_int_urb(urb, udev, usb_rcvintpipe(udev, BCM203X_IN_EP),
data->buffer, 32, bcm203x_complete, data, 1);
data->state = BCM203X_CHECK_FIRMWARE;
} else {
len = min_t(uint, data->fw_size - data->fw_sent, 4096);
usb_fill_bulk_urb(urb, udev, usb_sndbulkpipe(udev, BCM203X_OUT_EP),
data->fw_data + data->fw_sent, len, bcm203x_complete, data);
data->fw_sent += len;
}
if (usb_submit_urb(data->urb, GFP_ATOMIC) < 0)
BT_ERR("Can't submit URB");
break;
case BCM203X_CHECK_FIRMWARE:
if (data->buffer[0] != '.') {
BT_ERR("Firmware loading failed");
data->state = BCM203X_ERROR;
break;
}
data->state = BCM203X_RESET;
break;
}
}
static void bcm203x_work(struct work_struct *work)
{
struct bcm203x_data *data =
container_of(work, struct bcm203x_data, work);
if (atomic_read(&data->shutdown))
return;
if (usb_submit_urb(data->urb, GFP_KERNEL) < 0)
BT_ERR("Can't submit URB");
}
static int bcm203x_probe(struct usb_interface *intf, const struct usb_device_id *id)
{
const struct firmware *firmware;
struct usb_device *udev = interface_to_usbdev(intf);
struct bcm203x_data *data;
int size;
BT_DBG("intf %p id %p", intf, id);
if (intf->cur_altsetting->desc.bInterfaceNumber != 0)
return -ENODEV;
data = devm_kzalloc(&intf->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->udev = udev;
data->state = BCM203X_LOAD_MINIDRV;
data->urb = usb_alloc_urb(0, GFP_KERNEL);
if (!data->urb)
return -ENOMEM;
if (request_firmware(&firmware, "BCM2033-MD.hex", &udev->dev) < 0) {
BT_ERR("Mini driver request failed");
usb_free_urb(data->urb);
return -EIO;
}
BT_DBG("minidrv data %p size %zu", firmware->data, firmware->size);
size = max_t(uint, firmware->size, 4096);
data->buffer = kmalloc(size, GFP_KERNEL);
if (!data->buffer) {
BT_ERR("Can't allocate memory for mini driver");
release_firmware(firmware);
usb_free_urb(data->urb);
return -ENOMEM;
}
memcpy(data->buffer, firmware->data, firmware->size);
usb_fill_bulk_urb(data->urb, udev, usb_sndbulkpipe(udev, BCM203X_OUT_EP),
data->buffer, firmware->size, bcm203x_complete, data);
release_firmware(firmware);
if (request_firmware(&firmware, "BCM2033-FW.bin", &udev->dev) < 0) {
BT_ERR("Firmware request failed");
usb_free_urb(data->urb);
kfree(data->buffer);
return -EIO;
}
BT_DBG("firmware data %p size %zu", firmware->data, firmware->size);
data->fw_data = kmemdup(firmware->data, firmware->size, GFP_KERNEL);
if (!data->fw_data) {
BT_ERR("Can't allocate memory for firmware image");
release_firmware(firmware);
usb_free_urb(data->urb);
kfree(data->buffer);
return -ENOMEM;
}
data->fw_size = firmware->size;
data->fw_sent = 0;
release_firmware(firmware);
INIT_WORK(&data->work, bcm203x_work);
usb_set_intfdata(intf, data);
/* use workqueue to have a small delay */
schedule_work(&data->work);
return 0;
}
static void bcm203x_disconnect(struct usb_interface *intf)
{
struct bcm203x_data *data = usb_get_intfdata(intf);
BT_DBG("intf %p", intf);
atomic_inc(&data->shutdown);
cancel_work_sync(&data->work);
usb_kill_urb(data->urb);
usb_set_intfdata(intf, NULL);
usb_free_urb(data->urb);
kfree(data->fw_data);
kfree(data->buffer);
}
static struct usb_driver bcm203x_driver = {
.name = "bcm203x",
.probe = bcm203x_probe,
.disconnect = bcm203x_disconnect,
.id_table = bcm203x_table,
.disable_hub_initiated_lpm = 1,
};
module_usb_driver(bcm203x_driver);
MODULE_AUTHOR("Marcel Holtmann <[email protected]>");
MODULE_DESCRIPTION("Broadcom Blutonium firmware driver ver " VERSION);
MODULE_VERSION(VERSION);
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("BCM2033-MD.hex");
MODULE_FIRMWARE("BCM2033-FW.bin");
|
/* SPDX-License-Identifier: ISC */
#ifndef __MT7603_H
#define __MT7603_H
#include <linux/interrupt.h>
#include <linux/ktime.h>
#include "../mt76.h"
#include "regs.h"
#define MT7603_MAX_INTERFACES 4
#define MT7603_WTBL_SIZE 128
#define MT7603_WTBL_RESERVED (MT7603_WTBL_SIZE - 1)
#define MT7603_WTBL_STA (MT7603_WTBL_RESERVED - MT7603_MAX_INTERFACES)
#define MT7603_RATE_RETRY 2
#define MT7603_MCU_RX_RING_SIZE 64
#define MT7603_RX_RING_SIZE 128
#define MT7603_TX_RING_SIZE 256
#define MT7603_PSD_RING_SIZE 128
#define MT7603_FIRMWARE_E1 "mt7603_e1.bin"
#define MT7603_FIRMWARE_E2 "mt7603_e2.bin"
#define MT7628_FIRMWARE_E1 "mt7628_e1.bin"
#define MT7628_FIRMWARE_E2 "mt7628_e2.bin"
#define MT7603_EEPROM_SIZE 1024
#define MT_AGG_SIZE_LIMIT(_n) (((_n) + 1) * 4)
#define MT7603_PRE_TBTT_TIME 5000 /* ms */
#define MT7603_WATCHDOG_TIME 100 /* ms */
#define MT7603_WATCHDOG_TIMEOUT 10 /* number of checks */
#define MT7603_EDCCA_BLOCK_TH 10
#define MT7603_CFEND_RATE_DEFAULT 0x69 /* chip default (24M) */
#define MT7603_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
struct mt7603_vif;
struct mt7603_sta;
enum {
MT7603_REV_E1 = 0x00,
MT7603_REV_E2 = 0x10,
MT7628_REV_E1 = 0x8a00,
};
enum mt7603_bw {
MT_BW_20,
MT_BW_40,
MT_BW_80,
};
struct mt7603_rate_set {
struct ieee80211_tx_rate probe_rate;
struct ieee80211_tx_rate rates[4];
};
struct mt7603_sta {
struct mt76_wcid wcid; /* must be first */
struct mt7603_vif *vif;
u32 tx_airtime_ac[4];
struct sk_buff_head psq;
struct ieee80211_tx_rate rates[4];
struct mt7603_rate_set rateset[2];
u32 rate_set_tsf;
u8 rate_count;
u8 n_rates;
u8 rate_probe;
u8 smps;
u8 ps;
};
struct mt7603_vif {
struct mt7603_sta sta; /* must be first */
u8 idx;
};
enum mt7603_reset_cause {
RESET_CAUSE_TX_HANG,
RESET_CAUSE_TX_BUSY,
RESET_CAUSE_RX_BUSY,
RESET_CAUSE_BEACON_STUCK,
RESET_CAUSE_RX_PSE_BUSY,
RESET_CAUSE_MCU_HANG,
RESET_CAUSE_RESET_FAILED,
__RESET_CAUSE_MAX
};
struct mt7603_dev {
union { /* must be first */
struct mt76_dev mt76;
struct mt76_phy mphy;
};
const struct mt76_bus_ops *bus_ops;
u32 rxfilter;
struct mt7603_sta global_sta;
u32 agc0, agc3;
u32 false_cca_ofdm, false_cca_cck;
unsigned long last_cca_adj;
u32 ampdu_ref;
u32 rx_ampdu_ts;
u8 rssi_offset[3];
u8 slottime;
s16 coverage_class;
s8 tx_power_limit;
ktime_t ed_time;
spinlock_t ps_lock;
u8 mcu_running;
u8 ed_monitor_enabled;
u8 ed_monitor;
s8 ed_trigger;
u8 ed_strict_mode;
u8 ed_strong_signal;
bool dynamic_sensitivity;
s8 sensitivity;
u8 sensitivity_limit;
u8 beacon_check;
u8 tx_hang_check;
u8 tx_dma_check;
u8 rx_dma_check;
u8 rx_pse_check;
u8 mcu_hang;
enum mt7603_reset_cause cur_reset_cause;
u16 tx_dma_idx[4];
u16 rx_dma_idx;
u32 reset_test;
unsigned int reset_cause[__RESET_CAUSE_MAX];
};
extern const struct mt76_driver_ops mt7603_drv_ops;
extern const struct ieee80211_ops mt7603_ops;
extern struct pci_driver mt7603_pci_driver;
extern struct platform_driver mt76_wmac_driver;
static inline bool is_mt7603(struct mt7603_dev *dev)
{
return mt76xx_chip(dev) == 0x7603;
}
static inline bool is_mt7628(struct mt7603_dev *dev)
{
return mt76xx_chip(dev) == 0x7628;
}
/* need offset to prevent conflict with ampdu_ack_len */
#define MT_RATE_DRIVER_DATA_OFFSET 4
u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr);
irqreturn_t mt7603_irq_handler(int irq, void *dev_instance);
int mt7603_register_device(struct mt7603_dev *dev);
void mt7603_unregister_device(struct mt7603_dev *dev);
int mt7603_eeprom_init(struct mt7603_dev *dev);
int mt7603_dma_init(struct mt7603_dev *dev);
void mt7603_dma_cleanup(struct mt7603_dev *dev);
int mt7603_mcu_init(struct mt7603_dev *dev);
void mt7603_init_debugfs(struct mt7603_dev *dev);
static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask)
{
mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
}
static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask)
{
mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
}
void mt7603_mac_reset_counters(struct mt7603_dev *dev);
void mt7603_mac_dma_start(struct mt7603_dev *dev);
void mt7603_mac_start(struct mt7603_dev *dev);
void mt7603_mac_stop(struct mt7603_dev *dev);
void mt7603_mac_work(struct work_struct *work);
void mt7603_mac_set_timing(struct mt7603_dev *dev);
void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval);
int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb);
void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data);
void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid);
void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
int ba_size);
void mt7603_mac_sta_poll(struct mt7603_dev *dev);
void mt7603_pse_client_reset(struct mt7603_dev *dev);
int mt7603_set_channel(struct mt76_phy *mphy);
int mt7603_mcu_set_channel(struct mt7603_dev *dev);
int mt7603_mcu_set_eeprom(struct mt7603_dev *dev);
void mt7603_mcu_exit(struct mt7603_dev *dev);
void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
const u8 *mac_addr);
void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);
void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta);
void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
struct ieee80211_tx_rate *probe_rate,
struct ieee80211_tx_rate *rates);
int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
struct ieee80211_key_conf *key);
void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
bool enabled);
void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
bool enabled);
void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort);
int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
enum mt76_txq_id qid, struct mt76_wcid *wcid,
struct ieee80211_sta *sta,
struct mt76_tx_info *tx_info);
void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
struct sk_buff *skb, u32 *info);
void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
struct ieee80211_sta *sta);
int mt7603_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, enum mt76_sta_event ev);
void mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
struct ieee80211_sta *sta);
void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t);
void mt7603_update_channel(struct mt76_phy *mphy);
void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val);
void mt7603_cca_stats_reset(struct mt7603_dev *dev);
void mt7603_init_edcca(struct mt7603_dev *dev);
#endif
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Linux device driver for PCI based Prism54
*
* Copyright (c) 2006, Michael Wu <[email protected]>
* Copyright (c) 2008, Christian Lamparter <[email protected]>
*
* Based on the islsm (softmac prism54) driver, which is:
* Copyright 2004-2006 Jean-Baptiste Note <[email protected]>, et al.
*/
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <linux/module.h>
#include <net/mac80211.h>
#include "p54.h"
#include "lmac.h"
#include "p54pci.h"
MODULE_AUTHOR("Michael Wu <[email protected]>");
MODULE_DESCRIPTION("Prism54 PCI wireless driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("prism54pci");
MODULE_FIRMWARE("isl3886pci");
static const struct pci_device_id p54p_table[] = {
/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
{ PCI_DEVICE(0x1260, 0x3890) },
/* 3COM 3CRWE154G72 Wireless LAN adapter */
{ PCI_DEVICE(0x10b7, 0x6001) },
/* Intersil PRISM Indigo Wireless LAN adapter */
{ PCI_DEVICE(0x1260, 0x3877) },
/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
{ PCI_DEVICE(0x1260, 0x3886) },
/* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
{ PCI_DEVICE(0x1260, 0xffff) },
{ },
};
MODULE_DEVICE_TABLE(pci, p54p_table);
static int p54p_upload_firmware(struct ieee80211_hw *dev)
{
struct p54p_priv *priv = dev->priv;
__le32 reg;
int err;
__le32 *data;
u32 remains, left, device_addr;
P54P_WRITE(int_enable, cpu_to_le32(0));
P54P_READ(int_enable);
udelay(10);
reg = P54P_READ(ctrl_stat);
reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
P54P_WRITE(ctrl_stat, reg);
P54P_READ(ctrl_stat);
udelay(10);
reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
P54P_WRITE(ctrl_stat, reg);
wmb();
udelay(10);
reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
P54P_WRITE(ctrl_stat, reg);
wmb();
/* wait for the firmware to reset properly */
mdelay(10);
err = p54_parse_firmware(dev, priv->firmware);
if (err)
return err;
if (priv->common.fw_interface != FW_LM86) {
dev_err(&priv->pdev->dev, "wrong firmware, "
"please get a LM86(PCI) firmware a try again.\n");
return -EINVAL;
}
data = (__le32 *) priv->firmware->data;
remains = priv->firmware->size;
device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
while (remains) {
u32 i = 0;
left = min((u32)0x1000, remains);
P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
P54P_READ(int_enable);
device_addr += 0x1000;
while (i < left) {
P54P_WRITE(direct_mem_win[i], *data++);
i += sizeof(u32);
}
remains -= left;
P54P_READ(int_enable);
}
reg = P54P_READ(ctrl_stat);
reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
P54P_WRITE(ctrl_stat, reg);
P54P_READ(ctrl_stat);
udelay(10);
reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
P54P_WRITE(ctrl_stat, reg);
wmb();
udelay(10);
reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
P54P_WRITE(ctrl_stat, reg);
wmb();
udelay(10);
/* wait for the firmware to boot properly */
mdelay(100);
return 0;
}
static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
int ring_index, struct p54p_desc *ring, u32 ring_limit,
struct sk_buff **rx_buf, u32 index)
{
struct p54p_priv *priv = dev->priv;
struct p54p_ring_control *ring_control = priv->ring_control;
u32 limit, idx, i;
idx = le32_to_cpu(ring_control->host_idx[ring_index]);
limit = idx;
limit -= index;
limit = ring_limit - limit;
i = idx % ring_limit;
while (limit-- > 1) {
struct p54p_desc *desc = &ring[i];
if (!desc->host_addr) {
struct sk_buff *skb;
dma_addr_t mapping;
skb = dev_alloc_skb(priv->common.rx_mtu + 32);
if (!skb)
break;
mapping = dma_map_single(&priv->pdev->dev,
skb_tail_pointer(skb),
priv->common.rx_mtu + 32,
DMA_FROM_DEVICE);
if (dma_mapping_error(&priv->pdev->dev, mapping)) {
dev_kfree_skb_any(skb);
dev_err(&priv->pdev->dev,
"RX DMA Mapping error\n");
break;
}
desc->host_addr = cpu_to_le32(mapping);
desc->device_addr = 0; // FIXME: necessary?
desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
desc->flags = 0;
rx_buf[i] = skb;
}
i++;
idx++;
i %= ring_limit;
}
wmb();
ring_control->host_idx[ring_index] = cpu_to_le32(idx);
}
static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
int ring_index, struct p54p_desc *ring, u32 ring_limit,
struct sk_buff **rx_buf)
{
struct p54p_priv *priv = dev->priv;
struct p54p_ring_control *ring_control = priv->ring_control;
struct p54p_desc *desc;
u32 idx, i;
i = (*index) % ring_limit;
(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
idx %= ring_limit;
while (i != idx) {
u16 len;
struct sk_buff *skb;
dma_addr_t dma_addr;
desc = &ring[i];
len = le16_to_cpu(desc->len);
skb = rx_buf[i];
if (!skb) {
i++;
i %= ring_limit;
continue;
}
if (unlikely(len > priv->common.rx_mtu)) {
if (net_ratelimit())
dev_err(&priv->pdev->dev, "rx'd frame size "
"exceeds length threshold.\n");
len = priv->common.rx_mtu;
}
dma_addr = le32_to_cpu(desc->host_addr);
dma_sync_single_for_cpu(&priv->pdev->dev, dma_addr,
priv->common.rx_mtu + 32,
DMA_FROM_DEVICE);
skb_put(skb, len);
if (p54_rx(dev, skb)) {
dma_unmap_single(&priv->pdev->dev, dma_addr,
priv->common.rx_mtu + 32,
DMA_FROM_DEVICE);
rx_buf[i] = NULL;
desc->host_addr = cpu_to_le32(0);
} else {
skb_trim(skb, 0);
dma_sync_single_for_device(&priv->pdev->dev, dma_addr,
priv->common.rx_mtu + 32,
DMA_FROM_DEVICE);
desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
}
i++;
i %= ring_limit;
}
p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
}
static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
int ring_index, struct p54p_desc *ring, u32 ring_limit,
struct sk_buff **tx_buf)
{
struct p54p_priv *priv = dev->priv;
struct p54p_ring_control *ring_control = priv->ring_control;
struct p54p_desc *desc;
struct sk_buff *skb;
u32 idx, i;
i = (*index) % ring_limit;
(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
idx %= ring_limit;
while (i != idx) {
desc = &ring[i];
skb = tx_buf[i];
tx_buf[i] = NULL;
dma_unmap_single(&priv->pdev->dev,
le32_to_cpu(desc->host_addr),
le16_to_cpu(desc->len), DMA_TO_DEVICE);
desc->host_addr = 0;
desc->device_addr = 0;
desc->len = 0;
desc->flags = 0;
if (skb && FREE_AFTER_TX(skb))
p54_free_skb(dev, skb);
i++;
i %= ring_limit;
}
}
static void p54p_tasklet(struct tasklet_struct *t)
{
struct p54p_priv *priv = from_tasklet(priv, t, tasklet);
struct ieee80211_hw *dev = pci_get_drvdata(priv->pdev);
struct p54p_ring_control *ring_control = priv->ring_control;
p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
ARRAY_SIZE(ring_control->tx_mgmt),
priv->tx_buf_mgmt);
p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
ARRAY_SIZE(ring_control->tx_data),
priv->tx_buf_data);
p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
wmb();
P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
}
static irqreturn_t p54p_interrupt(int irq, void *dev_id)
{
struct ieee80211_hw *dev = dev_id;
struct p54p_priv *priv = dev->priv;
__le32 reg;
reg = P54P_READ(int_ident);
if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
goto out;
}
P54P_WRITE(int_ack, reg);
reg &= P54P_READ(int_enable);
if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
tasklet_schedule(&priv->tasklet);
else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
complete(&priv->boot_comp);
out:
return reg ? IRQ_HANDLED : IRQ_NONE;
}
static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
unsigned long flags;
struct p54p_priv *priv = dev->priv;
struct p54p_ring_control *ring_control = priv->ring_control;
struct p54p_desc *desc;
dma_addr_t mapping;
u32 idx, i;
__le32 device_addr;
spin_lock_irqsave(&priv->lock, flags);
idx = le32_to_cpu(ring_control->host_idx[1]);
i = idx % ARRAY_SIZE(ring_control->tx_data);
device_addr = ((struct p54_hdr *)skb->data)->req_id;
mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
DMA_TO_DEVICE);
if (dma_mapping_error(&priv->pdev->dev, mapping)) {
spin_unlock_irqrestore(&priv->lock, flags);
p54_free_skb(dev, skb);
dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
return ;
}
priv->tx_buf_data[i] = skb;
desc = &ring_control->tx_data[i];
desc->host_addr = cpu_to_le32(mapping);
desc->device_addr = device_addr;
desc->len = cpu_to_le16(skb->len);
desc->flags = 0;
wmb();
ring_control->host_idx[1] = cpu_to_le32(idx + 1);
spin_unlock_irqrestore(&priv->lock, flags);
P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
P54P_READ(dev_int);
}
static void p54p_stop(struct ieee80211_hw *dev)
{
struct p54p_priv *priv = dev->priv;
struct p54p_ring_control *ring_control = priv->ring_control;
unsigned int i;
struct p54p_desc *desc;
P54P_WRITE(int_enable, cpu_to_le32(0));
P54P_READ(int_enable);
udelay(10);
free_irq(priv->pdev->irq, dev);
tasklet_kill(&priv->tasklet);
P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
desc = &ring_control->rx_data[i];
if (desc->host_addr)
dma_unmap_single(&priv->pdev->dev,
le32_to_cpu(desc->host_addr),
priv->common.rx_mtu + 32,
DMA_FROM_DEVICE);
kfree_skb(priv->rx_buf_data[i]);
priv->rx_buf_data[i] = NULL;
}
for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
desc = &ring_control->rx_mgmt[i];
if (desc->host_addr)
dma_unmap_single(&priv->pdev->dev,
le32_to_cpu(desc->host_addr),
priv->common.rx_mtu + 32,
DMA_FROM_DEVICE);
kfree_skb(priv->rx_buf_mgmt[i]);
priv->rx_buf_mgmt[i] = NULL;
}
for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
desc = &ring_control->tx_data[i];
if (desc->host_addr)
dma_unmap_single(&priv->pdev->dev,
le32_to_cpu(desc->host_addr),
le16_to_cpu(desc->len),
DMA_TO_DEVICE);
p54_free_skb(dev, priv->tx_buf_data[i]);
priv->tx_buf_data[i] = NULL;
}
for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
desc = &ring_control->tx_mgmt[i];
if (desc->host_addr)
dma_unmap_single(&priv->pdev->dev,
le32_to_cpu(desc->host_addr),
le16_to_cpu(desc->len),
DMA_TO_DEVICE);
p54_free_skb(dev, priv->tx_buf_mgmt[i]);
priv->tx_buf_mgmt[i] = NULL;
}
memset(ring_control, 0, sizeof(*ring_control));
}
static int p54p_open(struct ieee80211_hw *dev)
{
struct p54p_priv *priv = dev->priv;
int err;
long time_left;
init_completion(&priv->boot_comp);
err = request_irq(priv->pdev->irq, p54p_interrupt,
IRQF_SHARED, "p54pci", dev);
if (err) {
dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
return err;
}
memset(priv->ring_control, 0, sizeof(*priv->ring_control));
err = p54p_upload_firmware(dev);
if (err) {
free_irq(priv->pdev->irq, dev);
return err;
}
priv->rx_idx_data = priv->tx_idx_data = 0;
priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
P54P_READ(ring_control_base);
wmb();
udelay(10);
P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
P54P_READ(int_enable);
wmb();
udelay(10);
P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
P54P_READ(dev_int);
time_left = wait_for_completion_interruptible_timeout(
&priv->boot_comp, HZ);
if (time_left <= 0) {
wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
p54p_stop(dev);
return time_left ? -ERESTARTSYS : -ETIMEDOUT;
}
P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
P54P_READ(int_enable);
wmb();
udelay(10);
P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
P54P_READ(dev_int);
wmb();
udelay(10);
return 0;
}
static void p54p_firmware_step2(const struct firmware *fw,
void *context)
{
struct p54p_priv *priv = context;
struct ieee80211_hw *dev = priv->common.hw;
struct pci_dev *pdev = priv->pdev;
int err;
if (!fw) {
dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
err = -ENOENT;
goto out;
}
priv->firmware = fw;
err = p54p_open(dev);
if (err)
goto out;
err = p54_read_eeprom(dev);
p54p_stop(dev);
if (err)
goto out;
err = p54_register_common(dev, &pdev->dev);
if (err)
goto out;
out:
complete(&priv->fw_loaded);
if (err) {
struct device *parent = pdev->dev.parent;
if (parent)
device_lock(parent);
/*
* This will indirectly result in a call to p54p_remove.
* Hence, we don't need to bother with freeing any
* allocated ressources at all.
*/
device_release_driver(&pdev->dev);
if (parent)
device_unlock(parent);
}
pci_dev_put(pdev);
}
static int p54p_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct p54p_priv *priv;
struct ieee80211_hw *dev;
unsigned long mem_addr, mem_len;
int err;
pci_dev_get(pdev);
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "Cannot enable new PCI device\n");
goto err_put;
}
mem_addr = pci_resource_start(pdev, 0);
mem_len = pci_resource_len(pdev, 0);
if (mem_len < sizeof(struct p54p_csr)) {
dev_err(&pdev->dev, "Too short PCI resources\n");
err = -ENODEV;
goto err_disable_dev;
}
err = pci_request_regions(pdev, "p54pci");
if (err) {
dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
goto err_disable_dev;
}
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (!err)
err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (err) {
dev_err(&pdev->dev, "No suitable DMA available\n");
goto err_free_reg;
}
pci_set_master(pdev);
pci_try_set_mwi(pdev);
pci_write_config_byte(pdev, 0x40, 0);
pci_write_config_byte(pdev, 0x41, 0);
dev = p54_init_common(sizeof(*priv));
if (!dev) {
dev_err(&pdev->dev, "ieee80211 alloc failed\n");
err = -ENOMEM;
goto err_free_reg;
}
priv = dev->priv;
priv->pdev = pdev;
init_completion(&priv->fw_loaded);
SET_IEEE80211_DEV(dev, &pdev->dev);
pci_set_drvdata(pdev, dev);
priv->map = ioremap(mem_addr, mem_len);
if (!priv->map) {
dev_err(&pdev->dev, "Cannot map device memory\n");
err = -ENOMEM;
goto err_free_dev;
}
priv->ring_control = dma_alloc_coherent(&pdev->dev,
sizeof(*priv->ring_control),
&priv->ring_control_dma, GFP_KERNEL);
if (!priv->ring_control) {
dev_err(&pdev->dev, "Cannot allocate rings\n");
err = -ENOMEM;
goto err_iounmap;
}
priv->common.open = p54p_open;
priv->common.stop = p54p_stop;
priv->common.tx = p54p_tx;
spin_lock_init(&priv->lock);
tasklet_setup(&priv->tasklet, p54p_tasklet);
err = request_firmware_nowait(THIS_MODULE, 1, "isl3886pci",
&priv->pdev->dev, GFP_KERNEL,
priv, p54p_firmware_step2);
if (!err)
return 0;
dma_free_coherent(&pdev->dev, sizeof(*priv->ring_control),
priv->ring_control, priv->ring_control_dma);
err_iounmap:
iounmap(priv->map);
err_free_dev:
p54_free_common(dev);
err_free_reg:
pci_release_regions(pdev);
err_disable_dev:
pci_disable_device(pdev);
err_put:
pci_dev_put(pdev);
return err;
}
static void p54p_remove(struct pci_dev *pdev)
{
struct ieee80211_hw *dev = pci_get_drvdata(pdev);
struct p54p_priv *priv;
if (!dev)
return;
priv = dev->priv;
wait_for_completion(&priv->fw_loaded);
p54_unregister_common(dev);
release_firmware(priv->firmware);
dma_free_coherent(&pdev->dev, sizeof(*priv->ring_control),
priv->ring_control, priv->ring_control_dma);
iounmap(priv->map);
pci_release_regions(pdev);
pci_disable_device(pdev);
p54_free_common(dev);
}
#ifdef CONFIG_PM_SLEEP
static int p54p_suspend(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
pci_save_state(pdev);
pci_set_power_state(pdev, PCI_D3hot);
pci_disable_device(pdev);
return 0;
}
static int p54p_resume(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
int err;
err = pci_reenable_device(pdev);
if (err)
return err;
return pci_set_power_state(pdev, PCI_D0);
}
static SIMPLE_DEV_PM_OPS(p54pci_pm_ops, p54p_suspend, p54p_resume);
#define P54P_PM_OPS (&p54pci_pm_ops)
#else
#define P54P_PM_OPS (NULL)
#endif /* CONFIG_PM_SLEEP */
static struct pci_driver p54p_driver = {
.name = "p54pci",
.id_table = p54p_table,
.probe = p54p_probe,
.remove = p54p_remove,
.driver.pm = P54P_PM_OPS,
};
module_pci_driver(p54p_driver);
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* OmniVision OV96xx Camera Header File
*
* Copyright (C) 2009 Marek Vasut <[email protected]>
*/
#ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__
#define __DRIVERS_MEDIA_VIDEO_OV9640_H__
/* Register definitions */
#define OV9640_GAIN 0x00
#define OV9640_BLUE 0x01
#define OV9640_RED 0x02
#define OV9640_VFER 0x03
#define OV9640_COM1 0x04
#define OV9640_BAVE 0x05
#define OV9640_GEAVE 0x06
#define OV9640_RSID 0x07
#define OV9640_RAVE 0x08
#define OV9640_COM2 0x09
#define OV9640_PID 0x0a
#define OV9640_VER 0x0b
#define OV9640_COM3 0x0c
#define OV9640_COM4 0x0d
#define OV9640_COM5 0x0e
#define OV9640_COM6 0x0f
#define OV9640_AECH 0x10
#define OV9640_CLKRC 0x11
#define OV9640_COM7 0x12
#define OV9640_COM8 0x13
#define OV9640_COM9 0x14
#define OV9640_COM10 0x15
/* 0x16 - RESERVED */
#define OV9640_HSTART 0x17
#define OV9640_HSTOP 0x18
#define OV9640_VSTART 0x19
#define OV9640_VSTOP 0x1a
#define OV9640_PSHFT 0x1b
#define OV9640_MIDH 0x1c
#define OV9640_MIDL 0x1d
#define OV9640_MVFP 0x1e
#define OV9640_LAEC 0x1f
#define OV9640_BOS 0x20
#define OV9640_GBOS 0x21
#define OV9640_GROS 0x22
#define OV9640_ROS 0x23
#define OV9640_AEW 0x24
#define OV9640_AEB 0x25
#define OV9640_VPT 0x26
#define OV9640_BBIAS 0x27
#define OV9640_GBBIAS 0x28
/* 0x29 - RESERVED */
#define OV9640_EXHCH 0x2a
#define OV9640_EXHCL 0x2b
#define OV9640_RBIAS 0x2c
#define OV9640_ADVFL 0x2d
#define OV9640_ADVFH 0x2e
#define OV9640_YAVE 0x2f
#define OV9640_HSYST 0x30
#define OV9640_HSYEN 0x31
#define OV9640_HREF 0x32
#define OV9640_CHLF 0x33
#define OV9640_ARBLM 0x34
/* 0x35..0x36 - RESERVED */
#define OV9640_ADC 0x37
#define OV9640_ACOM 0x38
#define OV9640_OFON 0x39
#define OV9640_TSLB 0x3a
#define OV9640_COM11 0x3b
#define OV9640_COM12 0x3c
#define OV9640_COM13 0x3d
#define OV9640_COM14 0x3e
#define OV9640_EDGE 0x3f
#define OV9640_COM15 0x40
#define OV9640_COM16 0x41
#define OV9640_COM17 0x42
/* 0x43..0x4e - RESERVED */
#define OV9640_MTX1 0x4f
#define OV9640_MTX2 0x50
#define OV9640_MTX3 0x51
#define OV9640_MTX4 0x52
#define OV9640_MTX5 0x53
#define OV9640_MTX6 0x54
#define OV9640_MTX7 0x55
#define OV9640_MTX8 0x56
#define OV9640_MTX9 0x57
#define OV9640_MTXS 0x58
/* 0x59..0x61 - RESERVED */
#define OV9640_LCC1 0x62
#define OV9640_LCC2 0x63
#define OV9640_LCC3 0x64
#define OV9640_LCC4 0x65
#define OV9640_LCC5 0x66
#define OV9640_MANU 0x67
#define OV9640_MANV 0x68
#define OV9640_HV 0x69
#define OV9640_MBD 0x6a
#define OV9640_DBLV 0x6b
#define OV9640_GSP 0x6c /* ... till 0x7b */
#define OV9640_GST 0x7c /* ... till 0x8a */
#define OV9640_CLKRC_DPLL_EN 0x80
#define OV9640_CLKRC_DIRECT 0x40
#define OV9640_CLKRC_DIV(x) ((x) & 0x3f)
#define OV9640_PSHFT_VAL(x) ((x) & 0xff)
#define OV9640_ACOM_2X_ANALOG 0x80
#define OV9640_ACOM_RSVD 0x12
#define OV9640_MVFP_V 0x10
#define OV9640_MVFP_H 0x20
#define OV9640_COM1_HREF_NOSKIP 0x00
#define OV9640_COM1_HREF_2SKIP 0x04
#define OV9640_COM1_HREF_3SKIP 0x08
#define OV9640_COM1_QQFMT 0x20
#define OV9640_COM2_SSM 0x10
#define OV9640_COM3_VP 0x04
#define OV9640_COM4_QQ_VP 0x80
#define OV9640_COM4_RSVD 0x40
#define OV9640_COM5_SYSCLK 0x80
#define OV9640_COM5_LONGEXP 0x01
#define OV9640_COM6_OPT_BLC 0x40
#define OV9640_COM6_ADBLC_BIAS 0x08
#define OV9640_COM6_FMT_RST 0x82
#define OV9640_COM6_ADBLC_OPTEN 0x01
#define OV9640_COM7_RAW_RGB 0x01
#define OV9640_COM7_RGB 0x04
#define OV9640_COM7_QCIF 0x08
#define OV9640_COM7_QVGA 0x10
#define OV9640_COM7_CIF 0x20
#define OV9640_COM7_VGA 0x40
#define OV9640_COM7_SCCB_RESET 0x80
#define OV9640_TSLB_YVYU_YUYV 0x04
#define OV9640_TSLB_YUYV_UYVY 0x08
#define OV9640_COM12_YUV_AVG 0x04
#define OV9640_COM12_RSVD 0x40
#define OV9640_COM13_GAMMA_NONE 0x00
#define OV9640_COM13_GAMMA_Y 0x40
#define OV9640_COM13_GAMMA_RAW 0x80
#define OV9640_COM13_RGB_AVG 0x20
#define OV9640_COM13_MATRIX_EN 0x10
#define OV9640_COM13_Y_DELAY_EN 0x08
#define OV9640_COM13_YUV_DLY(x) ((x) & 0x07)
#define OV9640_COM15_OR_00FF 0x00
#define OV9640_COM15_OR_01FE 0x40
#define OV9640_COM15_OR_10F0 0xc0
#define OV9640_COM15_RGB_NORM 0x00
#define OV9640_COM15_RGB_565 0x10
#define OV9640_COM15_RGB_555 0x30
#define OV9640_COM16_RB_AVG 0x01
/* IDs */
#define OV9640_V2 0x9648
#define OV9640_V3 0x9649
#define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF))
/* supported resolutions */
enum {
W_QQCIF = 88,
W_QQVGA = 160,
W_QCIF = 176,
W_QVGA = 320,
W_CIF = 352,
W_VGA = 640,
W_SXGA = 1280
};
#define H_SXGA 960
/* Misc. structures */
struct ov9640_reg_alt {
u8 com7;
u8 com12;
u8 com13;
u8 com15;
};
struct ov9640_reg {
u8 reg;
u8 val;
};
struct ov9640_priv {
struct v4l2_subdev subdev;
struct v4l2_ctrl_handler hdl;
struct clk *clk;
struct gpio_desc *gpio_power;
struct gpio_desc *gpio_reset;
int model;
int revision;
};
#endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */
|
// SPDX-License-Identifier: GPL-2.0
/*
* 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
*
* Copyright (C) 2016 Intel Corporation
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/rational.h>
#include <linux/dmaengine.h>
#include <linux/dma/dw.h>
#include "8250_dwlib.h"
#define PCI_DEVICE_ID_INTEL_QRK_UARTx 0x0936
#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
#define PCI_DEVICE_ID_INTEL_EHL_UART0 0x4b96
#define PCI_DEVICE_ID_INTEL_EHL_UART1 0x4b97
#define PCI_DEVICE_ID_INTEL_EHL_UART2 0x4b98
#define PCI_DEVICE_ID_INTEL_EHL_UART3 0x4b99
#define PCI_DEVICE_ID_INTEL_EHL_UART4 0x4b9a
#define PCI_DEVICE_ID_INTEL_EHL_UART5 0x4b9b
#define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
#define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
/* Intel LPSS specific registers */
#define BYT_PRV_CLK 0x800
#define BYT_PRV_CLK_EN BIT(0)
#define BYT_PRV_CLK_M_VAL_SHIFT 1
#define BYT_PRV_CLK_N_VAL_SHIFT 16
#define BYT_PRV_CLK_UPDATE BIT(31)
#define BYT_TX_OVF_INT 0x820
#define BYT_TX_OVF_INT_MASK BIT(1)
struct lpss8250;
struct lpss8250_board {
unsigned long freq;
unsigned int base_baud;
int (*setup)(struct lpss8250 *, struct uart_port *p);
void (*exit)(struct lpss8250 *);
};
struct lpss8250 {
struct dw8250_port_data data;
struct lpss8250_board *board;
/* DMA parameters */
struct dw_dma_chip dma_chip;
struct dw_dma_slave dma_param;
u8 dma_maxburst;
};
static inline struct lpss8250 *to_lpss8250(struct dw8250_port_data *data)
{
return container_of(data, struct lpss8250, data);
}
static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
const struct ktermios *old)
{
unsigned int baud = tty_termios_baud_rate(termios);
struct lpss8250 *lpss = to_lpss8250(p->private_data);
unsigned long fref = lpss->board->freq, fuart = baud * 16;
unsigned long w = BIT(15) - 1;
unsigned long m, n;
u32 reg;
/* Gracefully handle the B0 case: fall back to B9600 */
fuart = fuart ? fuart : 9600 * 16;
/* Get Fuart closer to Fref */
fuart *= rounddown_pow_of_two(fref / fuart);
/*
* For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
* dividers must be adjusted.
*
* uartclk = (m / n) * 100 MHz, where m <= n
*/
rational_best_approximation(fuart, fref, w, w, &m, &n);
p->uartclk = fuart;
/* Reset the clock */
reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
writel(reg, p->membase + BYT_PRV_CLK);
reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
writel(reg, p->membase + BYT_PRV_CLK);
dw8250_do_set_termios(p, termios, old);
}
static unsigned int byt_get_mctrl(struct uart_port *port)
{
unsigned int ret = serial8250_do_get_mctrl(port);
/* Force DCD and DSR signals to permanently be reported as active */
ret |= TIOCM_CAR | TIOCM_DSR;
return ret;
}
static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
struct dw_dma_slave *param = &lpss->dma_param;
struct pci_dev *pdev = to_pci_dev(port->dev);
struct pci_dev *dma_dev;
switch (pdev->device) {
case PCI_DEVICE_ID_INTEL_BYT_UART1:
case PCI_DEVICE_ID_INTEL_BSW_UART1:
case PCI_DEVICE_ID_INTEL_BDW_UART1:
param->src_id = 3;
param->dst_id = 2;
break;
case PCI_DEVICE_ID_INTEL_BYT_UART2:
case PCI_DEVICE_ID_INTEL_BSW_UART2:
case PCI_DEVICE_ID_INTEL_BDW_UART2:
param->src_id = 5;
param->dst_id = 4;
break;
default:
return -EINVAL;
}
dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
param->dma_dev = &dma_dev->dev;
param->m_master = 0;
param->p_master = 1;
lpss->dma_maxburst = 16;
port->set_termios = byt_set_termios;
port->get_mctrl = byt_get_mctrl;
/* Disable TX counter interrupts */
writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
return 0;
}
static void byt_serial_exit(struct lpss8250 *lpss)
{
struct dw_dma_slave *param = &lpss->dma_param;
/* Paired with pci_get_slot() in the byt_serial_setup() above */
put_device(param->dma_dev);
}
static int ehl_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
struct uart_8250_dma *dma = &lpss->data.dma;
struct uart_8250_port *up = up_to_u8250p(port);
/*
* This simply makes the checks in the 8250_port to try the DMA
* channel request which in turn uses the magic of ACPI tables
* parsing (see drivers/dma/acpi-dma.c for the details) and
* matching with the registered General Purpose DMA controllers.
*/
up->dma = dma;
lpss->dma_maxburst = 16;
port->set_termios = dw8250_do_set_termios;
return 0;
}
static void ehl_serial_exit(struct lpss8250 *lpss)
{
struct uart_8250_port *up = serial8250_get_port(lpss->data.line);
up->dma = NULL;
}
#ifdef CONFIG_SERIAL_8250_DMA
static const struct dw_dma_platform_data qrk_serial_dma_pdata = {
.nr_channels = 2,
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
.chan_priority = CHAN_PRIORITY_ASCENDING,
.block_size = 4095,
.nr_masters = 1,
.data_width = {4},
.multi_block = {0},
};
static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port)
{
struct uart_8250_dma *dma = &lpss->data.dma;
struct dw_dma_chip *chip = &lpss->dma_chip;
struct dw_dma_slave *param = &lpss->dma_param;
struct pci_dev *pdev = to_pci_dev(port->dev);
int ret;
chip->pdata = &qrk_serial_dma_pdata;
chip->dev = &pdev->dev;
chip->id = pdev->devfn;
chip->irq = pci_irq_vector(pdev, 0);
chip->regs = pci_ioremap_bar(pdev, 1);
if (!chip->regs)
return;
/* Falling back to PIO mode if DMA probing fails */
ret = dw_dma_probe(chip);
if (ret)
return;
pci_try_set_mwi(pdev);
/* Special DMA address for UART */
dma->rx_dma_addr = 0xfffff000;
dma->tx_dma_addr = 0xfffff000;
param->dma_dev = &pdev->dev;
param->src_id = 0;
param->dst_id = 1;
param->hs_polarity = true;
lpss->dma_maxburst = 8;
}
static void qrk_serial_exit_dma(struct lpss8250 *lpss)
{
struct dw_dma_chip *chip = &lpss->dma_chip;
struct dw_dma_slave *param = &lpss->dma_param;
if (!param->dma_dev)
return;
dw_dma_remove(chip);
pci_iounmap(to_pci_dev(chip->dev), chip->regs);
}
#else /* CONFIG_SERIAL_8250_DMA */
static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port) {}
static void qrk_serial_exit_dma(struct lpss8250 *lpss) {}
#endif /* !CONFIG_SERIAL_8250_DMA */
static int qrk_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
qrk_serial_setup_dma(lpss, port);
return 0;
}
static void qrk_serial_exit(struct lpss8250 *lpss)
{
qrk_serial_exit_dma(lpss);
}
static bool lpss8250_dma_filter(struct dma_chan *chan, void *param)
{
struct dw_dma_slave *dws = param;
if (dws->dma_dev != chan->device->dev)
return false;
chan->private = dws;
return true;
}
static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port)
{
struct uart_8250_dma *dma = &lpss->data.dma;
struct dw_dma_slave *rx_param, *tx_param;
struct device *dev = port->port.dev;
if (!lpss->dma_param.dma_dev) {
dma = port->dma;
if (dma)
goto out_configuration_only;
return 0;
}
rx_param = devm_kmemdup(dev, &lpss->dma_param, sizeof(*rx_param), GFP_KERNEL);
if (!rx_param)
return -ENOMEM;
tx_param = devm_kmemdup(dev, &lpss->dma_param, sizeof(*tx_param), GFP_KERNEL);
if (!tx_param)
return -ENOMEM;
dma->fn = lpss8250_dma_filter;
dma->rx_param = rx_param;
dma->tx_param = tx_param;
port->dma = dma;
out_configuration_only:
dma->rxconf.src_maxburst = lpss->dma_maxburst;
dma->txconf.dst_maxburst = lpss->dma_maxburst;
return 0;
}
static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port uart;
struct lpss8250 *lpss;
int ret;
ret = pcim_enable_device(pdev);
if (ret)
return ret;
pci_set_master(pdev);
lpss = devm_kzalloc(&pdev->dev, sizeof(*lpss), GFP_KERNEL);
if (!lpss)
return -ENOMEM;
ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
if (ret < 0)
return ret;
lpss->board = (struct lpss8250_board *)id->driver_data;
memset(&uart, 0, sizeof(struct uart_8250_port));
uart.port.dev = &pdev->dev;
uart.port.irq = pci_irq_vector(pdev, 0);
uart.port.private_data = &lpss->data;
uart.port.type = PORT_16550A;
uart.port.iotype = UPIO_MEM32;
uart.port.regshift = 2;
uart.port.uartclk = lpss->board->base_baud * 16;
uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
uart.port.mapbase = pci_resource_start(pdev, 0);
uart.port.membase = pcim_iomap(pdev, 0, 0);
if (!uart.port.membase)
return -ENOMEM;
ret = lpss->board->setup(lpss, &uart.port);
if (ret)
return ret;
dw8250_setup_port(&uart.port);
ret = lpss8250_dma_setup(lpss, &uart);
if (ret)
goto err_exit;
ret = serial8250_register_8250_port(&uart);
if (ret < 0)
goto err_exit;
lpss->data.line = ret;
pci_set_drvdata(pdev, lpss);
return 0;
err_exit:
lpss->board->exit(lpss);
pci_free_irq_vectors(pdev);
return ret;
}
static void lpss8250_remove(struct pci_dev *pdev)
{
struct lpss8250 *lpss = pci_get_drvdata(pdev);
serial8250_unregister_port(lpss->data.line);
lpss->board->exit(lpss);
pci_free_irq_vectors(pdev);
}
static const struct lpss8250_board byt_board = {
.freq = 100000000,
.base_baud = 2764800,
.setup = byt_serial_setup,
.exit = byt_serial_exit,
};
static const struct lpss8250_board ehl_board = {
.freq = 200000000,
.base_baud = 12500000,
.setup = ehl_serial_setup,
.exit = ehl_serial_exit,
};
static const struct lpss8250_board qrk_board = {
.freq = 44236800,
.base_baud = 2764800,
.setup = qrk_serial_setup,
.exit = qrk_serial_exit,
};
static const struct pci_device_id pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, QRK_UARTx, &qrk_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART0, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART1, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART2, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART3, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART4, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART5, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, BYT_UART1, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BYT_UART2, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BSW_UART1, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BSW_UART2, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BDW_UART1, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BDW_UART2, &byt_board) },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);
static struct pci_driver lpss8250_pci_driver = {
.name = "8250_lpss",
.id_table = pci_ids,
.probe = lpss8250_probe,
.remove = lpss8250_remove,
};
module_pci_driver(lpss8250_pci_driver);
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel LPSS UART driver");
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "core_types.h"
#ifndef __DCN20_FPU_H__
#define __DCN20_FPU_H__
void dcn20_populate_dml_writeback_from_context(struct dc *dc,
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes);
void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt, int i);
void dcn20_calculate_dlg_params(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel);
int dcn20_populate_dml_pipes_from_context(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
bool fast_validate);
void dcn20_calculate_wm(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int *out_pipe_cnt,
int *pipe_split_from,
int vlevel,
bool fast_validate);
void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks);
void dcn20_update_bounding_box(struct dc *dc,
struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table *max_clocks,
unsigned int *uclk_states,
unsigned int num_states);
void dcn20_patch_bounding_box(struct dc *dc,
struct _vcs_dpi_soc_bounding_box_st *bb);
bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
bool fast_validate, display_e2e_pipe_params_st *pipes);
void dcn20_fpu_set_wm_ranges(int i,
struct pp_smu_wm_range_sets *ranges,
struct _vcs_dpi_soc_bounding_box_st *loaded_bb);
void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
int vlevel,
int max_mpc_comb,
int pipe_idx,
bool is_validating_bw);
int dcn21_populate_dml_pipes_from_context(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
bool fast_validate);
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool
fast_validate, display_e2e_pipe_params_st *pipes);
void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes);
#endif /* __DCN20_FPU_H__ */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Ash Charles, Gumstix, Inc.
*/
/*
* TobiDuo expansion board is manufactured by Gumstix Inc.
*/
/dts-v1/;
#include "omap3-overo.dtsi"
#include "omap3-overo-tobiduo-common.dtsi"
/ {
model = "OMAP35xx Gumstix Overo on TobiDuo";
compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
};
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NETGEAR ReadyNAS 102
*
* Copyright (C) 2013, Arnaud EBALARD <[email protected]>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"
/ {
model = "NETGEAR ReadyNAS 102";
compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
serial@12000 {
status = "okay";
};
/* eSATA interface */
sata@a0000 {
nr-ports = <1>;
status = "okay";
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
usb@50000 {
status = "okay";
};
i2c@11000 {
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
isl12057: rtc@68 {
compatible = "isil,isl12057";
reg = <0x68>;
wakeup-source;
};
g762: g762@3e {
compatible = "gmt,g762";
reg = <0x3e>;
clocks = <&g762_clk>; /* input clock */
fan_gear_mode = <0>;
fan_startv = <1>;
pwm_polarity = <0>;
};
};
};
};
clocks {
g762_clk: g762-oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <8192>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&power_led_pin
&sata1_led_pin
&sata2_led_pin
&backup_led_pin>;
pinctrl-names = "default";
blue-power-led {
label = "rn102:blue:pwr";
gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
blue-sata1-led {
label = "rn102:blue:sata1";
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
default-state = "on";
};
blue-sata2-led {
label = "rn102:blue:sata2";
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
default-state = "on";
};
blue-backup-led {
label = "rn102:blue:backup";
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&power_button_pin
&reset_button_pin
&backup_button_pin>;
pinctrl-names = "default";
power-button {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
};
reset-button {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
backup-button {
label = "Backup Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
pinctrl-0 = <&poweroff>;
pinctrl-names = "default";
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
};
};
&pciec {
status = "okay";
/* Connected to Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to FL1009 USB 3.0 controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
};
&pinctrl {
power_led_pin: power-led-pin {
marvell,pins = "mpp57";
marvell,function = "gpio";
};
sata1_led_pin: sata1-led-pin {
marvell,pins = "mpp15";
marvell,function = "gpio";
};
sata2_led_pin: sata2-led-pin {
marvell,pins = "mpp14";
marvell,function = "gpio";
};
backup_led_pin: backup-led-pin {
marvell,pins = "mpp56";
marvell,function = "gpio";
};
backup_button_pin: backup-button-pin {
marvell,pins = "mpp58";
marvell,function = "gpio";
};
power_button_pin: power-button-pin {
marvell,pins = "mpp62";
marvell,function = "gpio";
};
reset_button_pin: reset-button-pin {
marvell,pins = "mpp6";
marvell,function = "gpio";
};
poweroff: poweroff {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
/* Use Hardware BCH ECC */
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */
read-only;
};
partition@180000 {
label = "u-boot-env";
reg = <0x180000 0x20000>; /* 128KB */
read-only;
};
partition@200000 {
label = "uImage";
reg = <0x0200000 0x600000>; /* 6MB */
};
partition@800000 {
label = "minirootfs";
reg = <0x0800000 0x400000>; /* 4MB */
};
/* Last MB is for the BBT, i.e. not writable */
partition@c00000 {
label = "ubifs";
reg = <0x0c00000 0x7400000>; /* 116MB */
};
};
};
};
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* i2c_adap_pxa.c
*
* I2C adapter for the PXA I2C bus access.
*
* Copyright (C) 2002 Intrinsyc Software Inc.
* Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
*
* History:
* Apr 2002: Initial version [CS]
* Jun 2002: Properly separated algo/adap [FB]
* Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
* Jan 2003: added limited signal handling [Kai-Uwe Bloem]
* Sep 2004: Major rework to ensure efficient bus handling [RMK]
* Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
* Feb 2005: Rework slave mode handling [RMK]
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/platform_data/i2c-pxa.h>
#include <linux/property.h>
#include <linux/slab.h>
/* I2C register field definitions */
#define IBMR_SDAS (1 << 0)
#define IBMR_SCLS (1 << 1)
#define ICR_START (1 << 0) /* start bit */
#define ICR_STOP (1 << 1) /* stop bit */
#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
#define ICR_TB (1 << 3) /* transfer byte bit */
#define ICR_MA (1 << 4) /* master abort */
#define ICR_SCLE (1 << 5) /* master clock enable */
#define ICR_IUE (1 << 6) /* unit enable */
#define ICR_GCD (1 << 7) /* general call disable */
#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
#define ICR_BEIE (1 << 10) /* enable bus error ints */
#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ICR_FM (1 << 15) /* fast mode */
#define ICR_HS (1 << 16) /* High Speed mode */
#define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
#define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
#define ISR_RWM (1 << 0) /* read/write mode */
#define ISR_ACKNAK (1 << 1) /* ack/nak status */
#define ISR_UB (1 << 2) /* unit busy */
#define ISR_IBB (1 << 3) /* bus busy */
#define ISR_SSD (1 << 4) /* slave stop detected */
#define ISR_ALD (1 << 5) /* arbitration loss detected */
#define ISR_ITE (1 << 6) /* tx buffer empty */
#define ISR_IRF (1 << 7) /* rx buffer full */
#define ISR_GCAD (1 << 8) /* general call address detected */
#define ISR_SAD (1 << 9) /* slave address detected */
#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
#define ILCR_SLV_SHIFT 0
#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
#define ILCR_FLV_SHIFT 9
#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
#define ILCR_HLVL_SHIFT 18
#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
#define ILCR_HLVH_SHIFT 27
#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
#define IWCR_CNT_SHIFT 0
#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
#define IWCR_HS_CNT1_SHIFT 5
#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
#define IWCR_HS_CNT2_SHIFT 10
#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
/* need a longer timeout if we're dealing with the fact we may well be
* looking at a multi-master environment
*/
#define DEF_TIMEOUT 32
#define NO_SLAVE (-ENXIO)
#define BUS_ERROR (-EREMOTEIO)
#define XFER_NAKED (-ECONNREFUSED)
#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
/* ICR initialize bit values
*
* 15 FM 0 (100 kHz operation)
* 14 UR 0 (No unit reset)
* 13 SADIE 0 (Disables the unit from interrupting on slave addresses
* matching its slave address)
* 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
* in master mode)
* 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
* 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
* 9 IRFIE 1 (Enable interrupts from full buffer received)
* 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
* 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
* 6 IUE 0 (Disable unit until we change settings)
* 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
* 4 MA 0 (Only send stop with the ICR stop bit)
* 3 TB 0 (We are not transmitting a byte initially)
* 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
* 1 STOP 0 (Do not send a STOP)
* 0 START 0 (Do not send a START)
*/
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
/* I2C status register init values
*
* 10 BED 1 (Clear bus error detected)
* 9 SAD 1 (Clear slave address detected)
* 7 IRF 1 (Clear IDBR Receive Full)
* 6 ITE 1 (Clear IDBR Transmit Empty)
* 5 ALD 1 (Clear Arbitration Loss Detected)
* 4 SSD 1 (Clear Slave Stop Detected)
*/
#define I2C_ISR_INIT 0x7FF /* status register init */
struct pxa_reg_layout {
u32 ibmr;
u32 idbr;
u32 icr;
u32 isr;
u32 isar;
u32 ilcr;
u32 iwcr;
u32 fm;
u32 hs;
};
enum pxa_i2c_types {
REGS_PXA2XX,
REGS_PXA3XX,
REGS_CE4100,
REGS_PXA910,
REGS_A3700,
};
/* I2C register layout definitions */
static struct pxa_reg_layout pxa_reg_layout[] = {
[REGS_PXA2XX] = {
.ibmr = 0x00,
.idbr = 0x08,
.icr = 0x10,
.isr = 0x18,
.isar = 0x20,
.fm = ICR_FM,
.hs = ICR_HS,
},
[REGS_PXA3XX] = {
.ibmr = 0x00,
.idbr = 0x04,
.icr = 0x08,
.isr = 0x0c,
.isar = 0x10,
.fm = ICR_FM,
.hs = ICR_HS,
},
[REGS_CE4100] = {
.ibmr = 0x14,
.idbr = 0x0c,
.icr = 0x00,
.isr = 0x04,
/* no isar register */
.fm = ICR_FM,
.hs = ICR_HS,
},
[REGS_PXA910] = {
.ibmr = 0x00,
.idbr = 0x08,
.icr = 0x10,
.isr = 0x18,
.isar = 0x20,
.ilcr = 0x28,
.iwcr = 0x30,
.fm = ICR_FM,
.hs = ICR_HS,
},
[REGS_A3700] = {
.ibmr = 0x00,
.idbr = 0x04,
.icr = 0x08,
.isr = 0x0c,
.isar = 0x10,
.fm = ICR_A3700_FM,
.hs = ICR_A3700_HS,
},
};
static const struct of_device_id i2c_pxa_dt_ids[] = {
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
{ .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
{}
};
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
static const struct platform_device_id i2c_pxa_id_table[] = {
{ "pxa2xx-i2c", REGS_PXA2XX },
{ "pxa3xx-pwri2c", REGS_PXA3XX },
{ "ce4100-i2c", REGS_CE4100 },
{ "pxa910-i2c", REGS_PXA910 },
{ "armada-3700-i2c", REGS_A3700 },
{ }
};
MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
struct pxa_i2c {
spinlock_t lock;
wait_queue_head_t wait;
struct i2c_msg *msg;
unsigned int msg_num;
unsigned int msg_idx;
unsigned int msg_ptr;
unsigned int slave_addr;
unsigned int req_slave_addr;
struct i2c_adapter adap;
struct clk *clk;
#ifdef CONFIG_I2C_PXA_SLAVE
struct i2c_client *slave;
#endif
unsigned int irqlogidx;
u32 isrlog[32];
u32 icrlog[32];
void __iomem *reg_base;
void __iomem *reg_ibmr;
void __iomem *reg_idbr;
void __iomem *reg_icr;
void __iomem *reg_isr;
void __iomem *reg_isar;
void __iomem *reg_ilcr;
void __iomem *reg_iwcr;
unsigned long iobase;
unsigned long iosize;
int irq;
unsigned int use_pio :1;
unsigned int fast_mode :1;
unsigned int high_mode:1;
unsigned char master_code;
unsigned long rate;
bool highmode_enter;
u32 fm_mask;
u32 hs_mask;
struct i2c_bus_recovery_info recovery;
struct pinctrl *pinctrl;
struct pinctrl_state *pinctrl_default;
struct pinctrl_state *pinctrl_recovery;
};
#define _IBMR(i2c) ((i2c)->reg_ibmr)
#define _IDBR(i2c) ((i2c)->reg_idbr)
#define _ICR(i2c) ((i2c)->reg_icr)
#define _ISR(i2c) ((i2c)->reg_isr)
#define _ISAR(i2c) ((i2c)->reg_isar)
#define _ILCR(i2c) ((i2c)->reg_ilcr)
#define _IWCR(i2c) ((i2c)->reg_iwcr)
/*
* I2C Slave mode address
*/
#define I2C_PXA_SLAVE_ADDR 0x1
#ifdef DEBUG
struct bits {
u32 mask;
const char *set;
const char *unset;
};
#define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
static inline void
decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
{
printk("%s %08x:", prefix, val);
while (num--) {
const char *str = val & bits->mask ? bits->set : bits->unset;
if (str)
pr_cont(" %s", str);
bits++;
}
pr_cont("\n");
}
static const struct bits isr_bits[] = {
PXA_BIT(ISR_RWM, "RX", "TX"),
PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
PXA_BIT(ISR_UB, "Bsy", "Rdy"),
PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
PXA_BIT(ISR_SSD, "SlaveStop", NULL),
PXA_BIT(ISR_ALD, "ALD", NULL),
PXA_BIT(ISR_ITE, "TxEmpty", NULL),
PXA_BIT(ISR_IRF, "RxFull", NULL),
PXA_BIT(ISR_GCAD, "GenCall", NULL),
PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
PXA_BIT(ISR_BED, "BusErr", NULL),
};
static void decode_ISR(unsigned int val)
{
decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
}
#ifdef CONFIG_I2C_PXA_SLAVE
static const struct bits icr_bits[] = {
PXA_BIT(ICR_START, "START", NULL),
PXA_BIT(ICR_STOP, "STOP", NULL),
PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
PXA_BIT(ICR_TB, "TB", NULL),
PXA_BIT(ICR_MA, "MA", NULL),
PXA_BIT(ICR_SCLE, "SCLE", "scle"),
PXA_BIT(ICR_IUE, "IUE", "iue"),
PXA_BIT(ICR_GCD, "GCD", NULL),
PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
PXA_BIT(ICR_BEIE, "BEIE", NULL),
PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
PXA_BIT(ICR_SADIE, "SADIE", NULL),
PXA_BIT(ICR_UR, "UR", "ur"),
};
static void decode_ICR(unsigned int val)
{
decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
}
#endif
static unsigned int i2c_debug = DEBUG;
static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
{
dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
}
#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
{
unsigned int i;
struct device *dev = &i2c->adap.dev;
dev_err(dev, "slave_0x%x error: %s\n",
i2c->req_slave_addr >> 1, why);
dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
readl(_ISR(i2c)));
dev_err(dev, "log:");
for (i = 0; i < i2c->irqlogidx; i++)
pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
pr_cont("\n");
}
#else /* ifdef DEBUG */
#define i2c_debug 0
#define show_state(i2c) do { } while (0)
#define decode_ISR(val) do { } while (0)
#define decode_ICR(val) do { } while (0)
#define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
#endif /* ifdef DEBUG / else */
static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
{
return !(readl(_ICR(i2c)) & ICR_SCLE);
}
static void i2c_pxa_abort(struct pxa_i2c *i2c)
{
int i = 250;
if (i2c_pxa_is_slavemode(i2c)) {
dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
return;
}
while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
unsigned long icr = readl(_ICR(i2c));
icr &= ~ICR_START;
icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
writel(icr, _ICR(i2c));
show_state(i2c);
mdelay(1);
i --;
}
writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
_ICR(i2c));
}
static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
{
int timeout = DEF_TIMEOUT;
u32 isr;
while (1) {
isr = readl(_ISR(i2c));
if (!(isr & (ISR_IBB | ISR_UB)))
return 0;
if (isr & ISR_SAD)
timeout += 4;
if (!timeout--)
break;
msleep(2);
show_state(i2c);
}
show_state(i2c);
return I2C_RETRY;
}
static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
{
unsigned long timeout = jiffies + HZ*4;
while (time_before(jiffies, timeout)) {
if (i2c_debug > 1)
dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
if (readl(_ISR(i2c)) & ISR_SAD) {
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
goto out;
}
/* wait for unit and bus being not busy, and we also do a
* quick check of the i2c lines themselves to ensure they've
* gone high...
*/
if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
return 1;
}
msleep(1);
}
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
out:
return 0;
}
static int i2c_pxa_set_master(struct pxa_i2c *i2c)
{
if (i2c_debug)
dev_dbg(&i2c->adap.dev, "setting to bus master\n");
if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
if (!i2c_pxa_wait_master(i2c)) {
dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
return I2C_RETRY;
}
}
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
return 0;
}
#ifdef CONFIG_I2C_PXA_SLAVE
static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
{
unsigned long timeout = jiffies + HZ*1;
/* wait for stop */
show_state(i2c);
while (time_before(jiffies, timeout)) {
if (i2c_debug > 1)
dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
(readl(_ISR(i2c)) & ISR_SAD) != 0 ||
(readl(_ICR(i2c)) & ICR_SCLE) == 0) {
if (i2c_debug > 1)
dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
return 1;
}
msleep(1);
}
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
return 0;
}
/*
* clear the hold on the bus, and take of anything else
* that has been configured
*/
static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
{
show_state(i2c);
if (errcode < 0) {
udelay(100); /* simple delay */
} else {
/* we need to wait for the stop condition to end */
/* if we where in stop, then clear... */
if (readl(_ICR(i2c)) & ICR_STOP) {
udelay(100);
writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
}
if (!i2c_pxa_wait_slave(i2c)) {
dev_err(&i2c->adap.dev, "%s: wait timedout\n",
__func__);
return;
}
}
writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
if (i2c_debug) {
dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
decode_ICR(readl(_ICR(i2c)));
}
}
#else
#define i2c_pxa_set_slave(i2c, err) do { } while (0)
#endif
static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
{
/* reset according to 9.8 */
writel(ICR_UR, _ICR(i2c));
writel(I2C_ISR_INIT, _ISR(i2c));
writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
#endif
i2c_pxa_set_slave(i2c, 0);
}
static void i2c_pxa_enable(struct pxa_i2c *i2c)
{
/* enable unit */
writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
udelay(100);
}
static void i2c_pxa_reset(struct pxa_i2c *i2c)
{
pr_debug("Resetting I2C Controller Unit\n");
/* abort any transfer currently under way */
i2c_pxa_abort(i2c);
i2c_pxa_do_reset(i2c);
i2c_pxa_enable(i2c);
}
#ifdef CONFIG_I2C_PXA_SLAVE
/*
* PXA I2C Slave mode
*/
static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
{
if (isr & ISR_BED) {
/* what should we do here? */
} else {
u8 byte = 0;
if (i2c->slave != NULL)
i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
&byte);
writel(byte, _IDBR(i2c));
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
}
}
static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
{
u8 byte = readl(_IDBR(i2c));
if (i2c->slave != NULL)
i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
}
static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
{
int timeout;
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
(isr & ISR_RWM) ? 'r' : 't');
if (i2c->slave != NULL) {
if (isr & ISR_RWM) {
u8 byte = 0;
i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
&byte);
writel(byte, _IDBR(i2c));
} else {
i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
NULL);
}
}
/*
* slave could interrupt in the middle of us generating a
* start condition... if this happens, we'd better back off
* and stop holding the poor thing up
*/
writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
timeout = 0x10000;
while (1) {
if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
break;
timeout--;
if (timeout <= 0) {
dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
break;
}
}
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
}
static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
{
if (i2c_debug > 2)
dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
if (i2c->slave != NULL)
i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
if (i2c_debug > 2)
dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
/*
* If we have a master-mode message waiting,
* kick it off now that the slave has completed.
*/
if (i2c->msg)
i2c_pxa_master_complete(i2c, I2C_RETRY);
}
static int i2c_pxa_slave_reg(struct i2c_client *slave)
{
struct pxa_i2c *i2c = slave->adapter->algo_data;
if (i2c->slave)
return -EBUSY;
if (!i2c->reg_isar)
return -EAFNOSUPPORT;
i2c->slave = slave;
i2c->slave_addr = slave->addr;
writel(i2c->slave_addr, _ISAR(i2c));
return 0;
}
static int i2c_pxa_slave_unreg(struct i2c_client *slave)
{
struct pxa_i2c *i2c = slave->adapter->algo_data;
WARN_ON(!i2c->slave);
i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
writel(i2c->slave_addr, _ISAR(i2c));
i2c->slave = NULL;
return 0;
}
#else
static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
{
if (isr & ISR_BED) {
/* what should we do here? */
} else {
writel(0, _IDBR(i2c));
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
}
}
static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
{
writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
}
static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
{
int timeout;
/*
* slave could interrupt in the middle of us generating a
* start condition... if this happens, we'd better back off
* and stop holding the poor thing up
*/
writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
timeout = 0x10000;
while (1) {
if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
break;
timeout--;
if (timeout <= 0) {
dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
break;
}
}
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
}
static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
{
if (i2c->msg)
i2c_pxa_master_complete(i2c, I2C_RETRY);
}
#endif
/*
* PXA I2C Master mode
*/
static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
{
u32 icr;
/*
* Step 1: target slave address into IDBR
*/
i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
writel(i2c->req_slave_addr, _IDBR(i2c));
/*
* Step 2: initiate the write.
*/
icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
writel(icr | ICR_START | ICR_TB, _ICR(i2c));
}
static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
{
u32 icr;
/* Clear the START, STOP, ACK, TB and MA flags */
icr = readl(_ICR(i2c));
icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
writel(icr, _ICR(i2c));
}
/*
* PXA I2C send master code
* 1. Load master code to IDBR and send it.
* Note for HS mode, set ICR [GPIOEN].
* 2. Wait until win arbitration.
*/
static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
{
u32 icr;
long time_left;
spin_lock_irq(&i2c->lock);
i2c->highmode_enter = true;
writel(i2c->master_code, _IDBR(i2c));
icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
writel(icr, _ICR(i2c));
spin_unlock_irq(&i2c->lock);
time_left = wait_event_timeout(i2c->wait,
i2c->highmode_enter == false, HZ * 1);
i2c->highmode_enter = false;
return (time_left == 0) ? I2C_RETRY : 0;
}
/*
* i2c_pxa_master_complete - complete the message and wake up.
*/
static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
{
i2c->msg_ptr = 0;
i2c->msg = NULL;
i2c->msg_idx ++;
i2c->msg_num = 0;
if (ret)
i2c->msg_idx = ret;
if (!i2c->use_pio)
wake_up(&i2c->wait);
}
static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
{
u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
again:
/*
* If ISR_ALD is set, we lost arbitration.
*/
if (isr & ISR_ALD) {
/*
* Do we need to do anything here? The PXA docs
* are vague about what happens.
*/
i2c_pxa_scream_blue_murder(i2c, "ALD set");
/*
* We ignore this error. We seem to see spurious ALDs
* for seemingly no reason. If we handle them as I think
* they should, we end up causing an I2C error, which
* is painful for some systems.
*/
return; /* ignore */
}
if ((isr & ISR_BED) &&
(!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
(isr & ISR_ACKNAK)))) {
int ret = BUS_ERROR;
/*
* I2C bus error - either the device NAK'd us, or
* something more serious happened. If we were NAK'd
* on the initial address phase, we can retry.
*/
if (isr & ISR_ACKNAK) {
if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
ret = NO_SLAVE;
else
ret = XFER_NAKED;
}
i2c_pxa_master_complete(i2c, ret);
} else if (isr & ISR_RWM) {
/*
* Read mode. We have just sent the address byte, and
* now we must initiate the transfer.
*/
if (i2c->msg_ptr == i2c->msg->len - 1 &&
i2c->msg_idx == i2c->msg_num - 1)
icr |= ICR_STOP | ICR_ACKNAK;
icr |= ICR_ALDIE | ICR_TB;
} else if (i2c->msg_ptr < i2c->msg->len) {
/*
* Write mode. Write the next data byte.
*/
writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
icr |= ICR_ALDIE | ICR_TB;
/*
* If this is the last byte of the last message or last byte
* of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
*/
if ((i2c->msg_ptr == i2c->msg->len) &&
((i2c->msg->flags & I2C_M_STOP) ||
(i2c->msg_idx == i2c->msg_num - 1)))
icr |= ICR_STOP;
} else if (i2c->msg_idx < i2c->msg_num - 1) {
/*
* Next segment of the message.
*/
i2c->msg_ptr = 0;
i2c->msg_idx ++;
i2c->msg++;
/*
* If we aren't doing a repeated start and address,
* go back and try to send the next byte. Note that
* we do not support switching the R/W direction here.
*/
if (i2c->msg->flags & I2C_M_NOSTART)
goto again;
/*
* Write the next address.
*/
i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
writel(i2c->req_slave_addr, _IDBR(i2c));
/*
* And trigger a repeated start, and send the byte.
*/
icr &= ~ICR_ALDIE;
icr |= ICR_START | ICR_TB;
} else {
if (i2c->msg->len == 0)
icr |= ICR_MA;
i2c_pxa_master_complete(i2c, 0);
}
i2c->icrlog[i2c->irqlogidx-1] = icr;
writel(icr, _ICR(i2c));
show_state(i2c);
}
static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
{
u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
/*
* Read the byte.
*/
i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
if (i2c->msg_ptr < i2c->msg->len) {
/*
* If this is the last byte of the last
* message, send a STOP.
*/
if (i2c->msg_ptr == i2c->msg->len - 1)
icr |= ICR_STOP | ICR_ACKNAK;
icr |= ICR_ALDIE | ICR_TB;
} else {
i2c_pxa_master_complete(i2c, 0);
}
i2c->icrlog[i2c->irqlogidx-1] = icr;
writel(icr, _ICR(i2c));
}
#define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
ISR_SAD | ISR_BED)
static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
{
struct pxa_i2c *i2c = dev_id;
u32 isr = readl(_ISR(i2c));
if (!(isr & VALID_INT_SOURCE))
return IRQ_NONE;
if (i2c_debug > 2 && 0) {
dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
__func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
decode_ISR(isr);
}
if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
i2c->isrlog[i2c->irqlogidx++] = isr;
show_state(i2c);
/*
* Always clear all pending IRQs.
*/
writel(isr & VALID_INT_SOURCE, _ISR(i2c));
if (isr & ISR_SAD)
i2c_pxa_slave_start(i2c, isr);
if (isr & ISR_SSD)
i2c_pxa_slave_stop(i2c);
if (i2c_pxa_is_slavemode(i2c)) {
if (isr & ISR_ITE)
i2c_pxa_slave_txempty(i2c, isr);
if (isr & ISR_IRF)
i2c_pxa_slave_rxfull(i2c, isr);
} else if (i2c->msg && (!i2c->highmode_enter)) {
if (isr & ISR_ITE)
i2c_pxa_irq_txempty(i2c, isr);
if (isr & ISR_IRF)
i2c_pxa_irq_rxfull(i2c, isr);
} else if ((isr & ISR_ITE) && i2c->highmode_enter) {
i2c->highmode_enter = false;
wake_up(&i2c->wait);
} else {
i2c_pxa_scream_blue_murder(i2c, "spurious irq");
}
return IRQ_HANDLED;
}
/*
* We are protected by the adapter bus mutex.
*/
static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
{
long time_left;
int ret;
/*
* Wait for the bus to become free.
*/
ret = i2c_pxa_wait_bus_not_busy(i2c);
if (ret) {
dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
i2c_recover_bus(&i2c->adap);
goto out;
}
/*
* Set master mode.
*/
ret = i2c_pxa_set_master(i2c);
if (ret) {
dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
goto out;
}
if (i2c->high_mode) {
ret = i2c_pxa_send_mastercode(i2c);
if (ret) {
dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
goto out;
}
}
spin_lock_irq(&i2c->lock);
i2c->msg = msg;
i2c->msg_num = num;
i2c->msg_idx = 0;
i2c->msg_ptr = 0;
i2c->irqlogidx = 0;
i2c_pxa_start_message(i2c);
spin_unlock_irq(&i2c->lock);
/*
* The rest of the processing occurs in the interrupt handler.
*/
time_left = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
i2c_pxa_stop_message(i2c);
/*
* We place the return code in i2c->msg_idx.
*/
ret = i2c->msg_idx;
if (!time_left && i2c->msg_num) {
i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
i2c_recover_bus(&i2c->adap);
ret = I2C_RETRY;
}
out:
return ret;
}
static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
struct i2c_msg *msgs, int num,
int (*xfer)(struct pxa_i2c *,
struct i2c_msg *, int num))
{
int ret, i;
for (i = 0; ; ) {
ret = xfer(i2c, msgs, num);
if (ret != I2C_RETRY && ret != NO_SLAVE)
goto out;
if (++i >= i2c->adap.retries)
break;
if (i2c_debug)
dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
udelay(100);
}
if (ret != NO_SLAVE)
i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
ret = -EREMOTEIO;
out:
i2c_pxa_set_slave(i2c, ret);
return ret;
}
static int i2c_pxa_xfer(struct i2c_adapter *adap,
struct i2c_msg msgs[], int num)
{
struct pxa_i2c *i2c = adap->algo_data;
return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
}
static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
}
static const struct i2c_algorithm i2c_pxa_algorithm = {
.master_xfer = i2c_pxa_xfer,
.functionality = i2c_pxa_functionality,
#ifdef CONFIG_I2C_PXA_SLAVE
.reg_slave = i2c_pxa_slave_reg,
.unreg_slave = i2c_pxa_slave_unreg,
#endif
};
/* Non-interrupt mode support */
static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
{
/* make timeout the same as for interrupt based functions */
long timeout = 2 * DEF_TIMEOUT;
/*
* Wait for the bus to become free.
*/
while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
udelay(1000);
if (timeout < 0) {
show_state(i2c);
dev_err(&i2c->adap.dev,
"i2c_pxa: timeout waiting for bus free (set_master)\n");
return I2C_RETRY;
}
/*
* Set master mode.
*/
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
return 0;
}
static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
struct i2c_msg *msg, int num)
{
unsigned long timeout = 500000; /* 5 seconds */
int ret = 0;
ret = i2c_pxa_pio_set_master(i2c);
if (ret)
goto out;
i2c->msg = msg;
i2c->msg_num = num;
i2c->msg_idx = 0;
i2c->msg_ptr = 0;
i2c->irqlogidx = 0;
i2c_pxa_start_message(i2c);
while (i2c->msg_num > 0 && --timeout) {
i2c_pxa_handler(0, i2c);
udelay(10);
}
i2c_pxa_stop_message(i2c);
/*
* We place the return code in i2c->msg_idx.
*/
ret = i2c->msg_idx;
out:
if (timeout == 0) {
i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
ret = I2C_RETRY;
}
return ret;
}
static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
struct i2c_msg msgs[], int num)
{
struct pxa_i2c *i2c = adap->algo_data;
/* If the I2C controller is disabled we need to reset it
(probably due to a suspend/resume destroying state). We do
this here as we can then avoid worrying about resuming the
controller before its users. */
if (!(readl(_ICR(i2c)) & ICR_IUE))
i2c_pxa_reset(i2c);
return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
}
static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
.master_xfer = i2c_pxa_pio_xfer,
.functionality = i2c_pxa_functionality,
#ifdef CONFIG_I2C_PXA_SLAVE
.reg_slave = i2c_pxa_slave_reg,
.unreg_slave = i2c_pxa_slave_unreg,
#endif
};
static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
enum pxa_i2c_types *i2c_types)
{
struct device_node *np = pdev->dev.of_node;
if (!pdev->dev.of_node)
return 1;
/* For device tree we always use the dynamic or alias-assigned ID */
i2c->adap.nr = -1;
i2c->use_pio = of_property_read_bool(np, "mrvl,i2c-polling");
i2c->fast_mode = of_property_read_bool(np, "mrvl,i2c-fast-mode");
*i2c_types = (enum pxa_i2c_types)device_get_match_data(&pdev->dev);
return 0;
}
static int i2c_pxa_probe_pdata(struct platform_device *pdev,
struct pxa_i2c *i2c,
enum pxa_i2c_types *i2c_types)
{
struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
const struct platform_device_id *id = platform_get_device_id(pdev);
*i2c_types = id->driver_data;
if (plat) {
i2c->use_pio = plat->use_pio;
i2c->fast_mode = plat->fast_mode;
i2c->high_mode = plat->high_mode;
i2c->master_code = plat->master_code;
if (!i2c->master_code)
i2c->master_code = 0xe;
i2c->rate = plat->rate;
}
return 0;
}
static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
{
struct pxa_i2c *i2c = adap->algo_data;
u32 ibmr = readl(_IBMR(i2c));
/*
* Program the GPIOs to reflect the current I2C bus state while
* we transition to recovery; this avoids glitching the bus.
*/
gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
}
static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
{
struct pxa_i2c *i2c = adap->algo_data;
u32 isr;
/*
* The bus should now be free. Clear up the I2C controller before
* handing control of the bus back to avoid the bus changing state.
*/
isr = readl(_ISR(i2c));
if (isr & (ISR_UB | ISR_IBB)) {
dev_dbg(&i2c->adap.dev,
"recovery: resetting controller, ISR=0x%08x\n", isr);
i2c_pxa_do_reset(i2c);
}
WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
readl(_IBMR(i2c)), readl(_ISR(i2c)));
i2c_pxa_enable(i2c);
}
static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
{
struct i2c_bus_recovery_info *bri = &i2c->recovery;
struct device *dev = i2c->adap.dev.parent;
/*
* When slave mode is enabled, we are not the only master on the bus.
* Bus recovery can only be performed when we are the master, which
* we can't be certain of. Therefore, when slave mode is enabled, do
* not configure bus recovery.
*/
if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
return 0;
i2c->pinctrl = devm_pinctrl_get(dev);
if (PTR_ERR(i2c->pinctrl) == -ENODEV)
i2c->pinctrl = NULL;
if (IS_ERR(i2c->pinctrl))
return PTR_ERR(i2c->pinctrl);
if (!i2c->pinctrl)
return 0;
i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
PINCTRL_STATE_DEFAULT);
i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) {
dev_info(dev, "missing pinmux recovery information: %ld %ld\n",
PTR_ERR(i2c->pinctrl_default),
PTR_ERR(i2c->pinctrl_recovery));
return 0;
}
/*
* Claiming GPIOs can influence the pinmux state, and may glitch the
* I2C bus. Do this carefully.
*/
bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER))
return -EPROBE_DEFER;
if (IS_ERR(bri->scl_gpiod)) {
dev_info(dev, "missing scl gpio recovery information: %pe\n",
bri->scl_gpiod);
return 0;
}
/*
* We have SCL. Pull SCL low and wait a bit so that SDA glitches
* have no effect.
*/
gpiod_direction_output(bri->scl_gpiod, 0);
udelay(10);
bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN);
/* Wait a bit in case of a SDA glitch, and then release SCL. */
udelay(10);
gpiod_direction_output(bri->scl_gpiod, 1);
if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER))
return -EPROBE_DEFER;
if (IS_ERR(bri->sda_gpiod)) {
dev_info(dev, "missing sda gpio recovery information: %pe\n",
bri->sda_gpiod);
return 0;
}
bri->prepare_recovery = i2c_pxa_prepare_recovery;
bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
bri->recover_bus = i2c_generic_scl_recovery;
i2c->adap.bus_recovery_info = bri;
/*
* Claiming GPIOs can change the pinmux state, which confuses the
* pinctrl since pinctrl's idea of the current setting is unaffected
* by the pinmux change caused by claiming the GPIO. Work around that
* by switching pinctrl to the GPIO state here. We do it this way to
* avoid glitching the I2C bus.
*/
pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
}
static int i2c_pxa_probe(struct platform_device *dev)
{
struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
enum pxa_i2c_types i2c_type;
struct pxa_i2c *i2c;
struct resource *res;
int ret, irq;
i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
if (!i2c)
return -ENOMEM;
/* Default adapter num to device id; i2c_pxa_probe_dt can override. */
i2c->adap.nr = dev->id;
i2c->adap.owner = THIS_MODULE;
i2c->adap.retries = 5;
i2c->adap.algo_data = i2c;
i2c->adap.dev.parent = &dev->dev;
#ifdef CONFIG_OF
i2c->adap.dev.of_node = dev->dev.of_node;
#endif
i2c->reg_base = devm_platform_get_and_ioremap_resource(dev, 0, &res);
if (IS_ERR(i2c->reg_base))
return PTR_ERR(i2c->reg_base);
irq = platform_get_irq(dev, 0);
if (irq < 0)
return irq;
ret = i2c_pxa_init_recovery(i2c);
if (ret)
return ret;
ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
if (ret > 0)
ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
if (ret < 0)
return ret;
spin_lock_init(&i2c->lock);
init_waitqueue_head(&i2c->wait);
strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
i2c->clk = devm_clk_get(&dev->dev, NULL);
if (IS_ERR(i2c->clk))
return dev_err_probe(&dev->dev, PTR_ERR(i2c->clk),
"failed to get the clk\n");
i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
if (i2c_type != REGS_CE4100)
i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
if (i2c_type == REGS_PXA910) {
i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
}
i2c->iobase = res->start;
i2c->iosize = resource_size(res);
i2c->irq = irq;
i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
i2c->highmode_enter = false;
if (plat) {
i2c->adap.class = plat->class;
}
if (i2c->high_mode) {
if (i2c->rate) {
clk_set_rate(i2c->clk, i2c->rate);
pr_info("i2c: <%s> set rate to %ld\n",
i2c->adap.name, clk_get_rate(i2c->clk));
} else
pr_warn("i2c: <%s> clock rate not set\n",
i2c->adap.name);
}
clk_prepare_enable(i2c->clk);
if (i2c->use_pio) {
i2c->adap.algo = &i2c_pxa_pio_algorithm;
} else {
i2c->adap.algo = &i2c_pxa_algorithm;
ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
IRQF_SHARED | IRQF_NO_SUSPEND,
dev_name(&dev->dev), i2c);
if (ret) {
dev_err(&dev->dev, "failed to request irq: %d\n", ret);
goto ereqirq;
}
}
i2c_pxa_reset(i2c);
ret = i2c_add_numbered_adapter(&i2c->adap);
if (ret < 0)
goto ereqirq;
platform_set_drvdata(dev, i2c);
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
i2c->slave_addr);
#else
dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
#endif
return 0;
ereqirq:
clk_disable_unprepare(i2c->clk);
return ret;
}
static void i2c_pxa_remove(struct platform_device *dev)
{
struct pxa_i2c *i2c = platform_get_drvdata(dev);
i2c_del_adapter(&i2c->adap);
clk_disable_unprepare(i2c->clk);
}
static int i2c_pxa_suspend_noirq(struct device *dev)
{
struct pxa_i2c *i2c = dev_get_drvdata(dev);
clk_disable(i2c->clk);
return 0;
}
static int i2c_pxa_resume_noirq(struct device *dev)
{
struct pxa_i2c *i2c = dev_get_drvdata(dev);
clk_enable(i2c->clk);
i2c_pxa_reset(i2c);
return 0;
}
static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
.suspend_noirq = i2c_pxa_suspend_noirq,
.resume_noirq = i2c_pxa_resume_noirq,
};
static struct platform_driver i2c_pxa_driver = {
.probe = i2c_pxa_probe,
.remove = i2c_pxa_remove,
.driver = {
.name = "pxa2xx-i2c",
.pm = pm_sleep_ptr(&i2c_pxa_dev_pm_ops),
.of_match_table = i2c_pxa_dt_ids,
},
.id_table = i2c_pxa_id_table,
};
static int __init i2c_adap_pxa_init(void)
{
return platform_driver_register(&i2c_pxa_driver);
}
static void __exit i2c_adap_pxa_exit(void)
{
platform_driver_unregister(&i2c_pxa_driver);
}
MODULE_DESCRIPTION("Intel PXA2XX I2C adapter");
MODULE_LICENSE("GPL");
subsys_initcall(i2c_adap_pxa_init);
module_exit(i2c_adap_pxa_exit);
|
// SPDX-License-Identifier: GPL-2.0-only
/*******************************************************************************
PTP 1588 clock using the STMMAC.
Copyright (C) 2013 Vayavya Labs Pvt Ltd
Author: Rayagond Kokatanur <[email protected]>
*******************************************************************************/
#include "stmmac.h"
#include "stmmac_ptp.h"
/**
* stmmac_adjust_freq
*
* @ptp: pointer to ptp_clock_info structure
* @scaled_ppm: desired period change in scaled parts per million
*
* Description: this function will adjust the frequency of hardware clock.
*
* Scaled parts per million is ppm with a 16-bit binary fractional field.
*/
static int stmmac_adjust_freq(struct ptp_clock_info *ptp, long scaled_ppm)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
unsigned long flags;
u32 addend;
addend = adjust_by_scaled_ppm(priv->default_addend, scaled_ppm);
write_lock_irqsave(&priv->ptp_lock, flags);
stmmac_config_addend(priv, priv->ptpaddr, addend);
write_unlock_irqrestore(&priv->ptp_lock, flags);
return 0;
}
/**
* stmmac_adjust_time
*
* @ptp: pointer to ptp_clock_info structure
* @delta: desired change in nanoseconds
*
* Description: this function will shift/adjust the hardware clock time.
*/
static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
unsigned long flags;
u32 sec, nsec;
u32 quotient, reminder;
int neg_adj = 0;
bool xmac, est_rst = false;
int ret;
xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
if (delta < 0) {
neg_adj = 1;
delta = -delta;
}
quotient = div_u64_rem(delta, 1000000000ULL, &reminder);
sec = quotient;
nsec = reminder;
/* If EST is enabled, disabled it before adjust ptp time. */
if (priv->est && priv->est->enable) {
est_rst = true;
mutex_lock(&priv->est_lock);
priv->est->enable = false;
stmmac_est_configure(priv, priv, priv->est,
priv->plat->clk_ptp_rate);
mutex_unlock(&priv->est_lock);
}
write_lock_irqsave(&priv->ptp_lock, flags);
stmmac_adjust_systime(priv, priv->ptpaddr, sec, nsec, neg_adj, xmac);
write_unlock_irqrestore(&priv->ptp_lock, flags);
/* Calculate new basetime and re-configured EST after PTP time adjust. */
if (est_rst) {
struct timespec64 current_time, time;
ktime_t current_time_ns, basetime;
u64 cycle_time;
mutex_lock(&priv->est_lock);
priv->ptp_clock_ops.gettime64(&priv->ptp_clock_ops, ¤t_time);
current_time_ns = timespec64_to_ktime(current_time);
time.tv_nsec = priv->est->btr_reserve[0];
time.tv_sec = priv->est->btr_reserve[1];
basetime = timespec64_to_ktime(time);
cycle_time = (u64)priv->est->ctr[1] * NSEC_PER_SEC +
priv->est->ctr[0];
time = stmmac_calc_tas_basetime(basetime,
current_time_ns,
cycle_time);
priv->est->btr[0] = (u32)time.tv_nsec;
priv->est->btr[1] = (u32)time.tv_sec;
priv->est->enable = true;
ret = stmmac_est_configure(priv, priv, priv->est,
priv->plat->clk_ptp_rate);
mutex_unlock(&priv->est_lock);
if (ret)
netdev_err(priv->dev, "failed to configure EST\n");
}
return 0;
}
/**
* stmmac_get_time
*
* @ptp: pointer to ptp_clock_info structure
* @ts: pointer to hold time/result
*
* Description: this function will read the current time from the
* hardware clock and store it in @ts.
*/
static int stmmac_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
unsigned long flags;
u64 ns = 0;
read_lock_irqsave(&priv->ptp_lock, flags);
stmmac_get_systime(priv, priv->ptpaddr, &ns);
read_unlock_irqrestore(&priv->ptp_lock, flags);
*ts = ns_to_timespec64(ns);
return 0;
}
/**
* stmmac_set_time
*
* @ptp: pointer to ptp_clock_info structure
* @ts: time value to set
*
* Description: this function will set the current time on the
* hardware clock.
*/
static int stmmac_set_time(struct ptp_clock_info *ptp,
const struct timespec64 *ts)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
unsigned long flags;
write_lock_irqsave(&priv->ptp_lock, flags);
stmmac_init_systime(priv, priv->ptpaddr, ts->tv_sec, ts->tv_nsec);
write_unlock_irqrestore(&priv->ptp_lock, flags);
return 0;
}
static int stmmac_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
void __iomem *ptpaddr = priv->ptpaddr;
struct stmmac_pps_cfg *cfg;
int ret = -EOPNOTSUPP;
unsigned long flags;
u32 acr_value;
switch (rq->type) {
case PTP_CLK_REQ_PEROUT:
/* Reject requests with unsupported flags */
if (rq->perout.flags)
return -EOPNOTSUPP;
cfg = &priv->pps[rq->perout.index];
cfg->start.tv_sec = rq->perout.start.sec;
cfg->start.tv_nsec = rq->perout.start.nsec;
cfg->period.tv_sec = rq->perout.period.sec;
cfg->period.tv_nsec = rq->perout.period.nsec;
write_lock_irqsave(&priv->ptp_lock, flags);
ret = stmmac_flex_pps_config(priv, priv->ioaddr,
rq->perout.index, cfg, on,
priv->sub_second_inc,
priv->systime_flags);
write_unlock_irqrestore(&priv->ptp_lock, flags);
break;
case PTP_CLK_REQ_EXTTS: {
u8 channel;
mutex_lock(&priv->aux_ts_lock);
acr_value = readl(ptpaddr + PTP_ACR);
channel = ilog2(FIELD_GET(PTP_ACR_MASK, acr_value));
acr_value &= ~PTP_ACR_MASK;
if (on) {
if (FIELD_GET(PTP_ACR_MASK, acr_value)) {
netdev_err(priv->dev,
"Cannot enable auxiliary snapshot %d as auxiliary snapshot %d is already enabled",
rq->extts.index, channel);
mutex_unlock(&priv->aux_ts_lock);
return -EBUSY;
}
priv->plat->flags |= STMMAC_FLAG_EXT_SNAPSHOT_EN;
/* Enable External snapshot trigger */
acr_value |= PTP_ACR_ATSEN(rq->extts.index);
acr_value |= PTP_ACR_ATSFC;
} else {
priv->plat->flags &= ~STMMAC_FLAG_EXT_SNAPSHOT_EN;
}
netdev_dbg(priv->dev, "Auxiliary Snapshot %d %s.\n",
rq->extts.index, on ? "enabled" : "disabled");
writel(acr_value, ptpaddr + PTP_ACR);
mutex_unlock(&priv->aux_ts_lock);
/* wait for auxts fifo clear to finish */
ret = readl_poll_timeout(ptpaddr + PTP_ACR, acr_value,
!(acr_value & PTP_ACR_ATSFC),
10, 10000);
break;
}
default:
break;
}
return ret;
}
/**
* stmmac_get_syncdevicetime
* @device: current device time
* @system: system counter value read synchronously with device time
* @ctx: context provided by timekeeping code
* Description: Read device and system clock simultaneously and return the
* corrected clock values in ns.
**/
static int stmmac_get_syncdevicetime(ktime_t *device,
struct system_counterval_t *system,
void *ctx)
{
struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
if (priv->plat->crosststamp)
return priv->plat->crosststamp(device, system, ctx);
else
return -EOPNOTSUPP;
}
static int stmmac_getcrosststamp(struct ptp_clock_info *ptp,
struct system_device_crosststamp *xtstamp)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
return get_device_system_crosststamp(stmmac_get_syncdevicetime,
priv, NULL, xtstamp);
}
/* structure describing a PTP hardware clock */
const struct ptp_clock_info stmmac_ptp_clock_ops = {
.owner = THIS_MODULE,
.name = "stmmac ptp",
.max_adj = 62500000,
.n_alarm = 0,
.n_ext_ts = 0, /* will be overwritten in stmmac_ptp_register */
.n_per_out = 0, /* will be overwritten in stmmac_ptp_register */
.n_pins = 0,
.pps = 0,
.adjfine = stmmac_adjust_freq,
.adjtime = stmmac_adjust_time,
.gettime64 = stmmac_get_time,
.settime64 = stmmac_set_time,
.enable = stmmac_enable,
.getcrosststamp = stmmac_getcrosststamp,
};
/* structure describing a PTP hardware clock */
const struct ptp_clock_info dwmac1000_ptp_clock_ops = {
.owner = THIS_MODULE,
.name = "stmmac ptp",
.max_adj = 62500000,
.n_alarm = 0,
.n_ext_ts = 1,
.n_per_out = 0,
.n_pins = 0,
.pps = 0,
.adjfine = stmmac_adjust_freq,
.adjtime = stmmac_adjust_time,
.gettime64 = stmmac_get_time,
.settime64 = stmmac_set_time,
.enable = dwmac1000_ptp_enable,
.getcrosststamp = stmmac_getcrosststamp,
};
/**
* stmmac_ptp_register
* @priv: driver private structure
* Description: this function will register the ptp clock driver
* to kernel. It also does some house keeping work.
*/
void stmmac_ptp_register(struct stmmac_priv *priv)
{
int i;
for (i = 0; i < priv->dma_cap.pps_out_num; i++) {
if (i >= STMMAC_PPS_MAX)
break;
priv->pps[i].available = true;
}
/* Calculate the clock domain crossing (CDC) error if necessary */
priv->plat->cdc_error_adj = 0;
if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate)
priv->plat->cdc_error_adj = (2 * NSEC_PER_SEC) / priv->plat->clk_ptp_rate;
/* Update the ptp clock parameters based on feature discovery, when
* available
*/
if (priv->dma_cap.pps_out_num)
priv->ptp_clock_ops.n_per_out = priv->dma_cap.pps_out_num;
if (priv->dma_cap.aux_snapshot_n)
priv->ptp_clock_ops.n_ext_ts = priv->dma_cap.aux_snapshot_n;
if (priv->plat->ptp_max_adj)
priv->ptp_clock_ops.max_adj = priv->plat->ptp_max_adj;
rwlock_init(&priv->ptp_lock);
mutex_init(&priv->aux_ts_lock);
priv->ptp_clock = ptp_clock_register(&priv->ptp_clock_ops,
priv->device);
if (IS_ERR(priv->ptp_clock)) {
netdev_err(priv->dev, "ptp_clock_register failed\n");
priv->ptp_clock = NULL;
} else if (priv->ptp_clock)
netdev_info(priv->dev, "registered PTP clock\n");
}
/**
* stmmac_ptp_unregister
* @priv: driver private structure
* Description: this function will remove/unregister the ptp clock driver
* from the kernel.
*/
void stmmac_ptp_unregister(struct stmmac_priv *priv)
{
if (priv->ptp_clock) {
ptp_clock_unregister(priv->ptp_clock);
priv->ptp_clock = NULL;
pr_debug("Removed PTP HW clock successfully on %s\n",
priv->dev->name);
}
mutex_destroy(&priv->aux_ts_lock);
}
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_INIT_H
#define MPI30_INIT_H 1
struct mpi3_scsi_io_cdb_eedp32 {
u8 cdb[20];
__be32 primary_reference_tag;
__le16 primary_application_tag;
__le16 primary_application_tag_mask;
__le32 transfer_length;
};
union mpi3_scsi_io_cdb_union {
u8 cdb32[32];
struct mpi3_scsi_io_cdb_eedp32 eedp32;
struct mpi3_sge_common sge;
};
struct mpi3_scsi_io_request {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 change_count;
__le16 dev_handle;
__le32 flags;
__le32 skip_count;
__le32 data_length;
u8 lun[8];
union mpi3_scsi_io_cdb_union cdb;
union mpi3_sge_union sgl[4];
};
#define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
#define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40)
#define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
#define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
#define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
#define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ACAQ (0x04000000)
#define MPI3_SCSIIO_FLAGS_CMDPRI_MASK (0x00f00000)
#define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT (20)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000c0000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER (0x00000000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE (0x00040000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ (0x00080000)
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK (0x00030000)
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_MASK (0x000000f0)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING (0x00000010)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE (0x00000020)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_PROD_SPECIFIC (0x00000080)
#define MPI3_SCSIIO_METASGL_INDEX (3)
struct mpi3_scsi_io_reply {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
u8 scsi_status;
u8 scsi_state;
__le16 dev_handle;
__le32 transfer_count;
__le32 sense_count;
__le32 response_data;
__le16 task_tag;
__le16 scsi_status_qualifier;
__le32 eedp_error_offset;
__le16 eedp_observed_app_tag;
__le16 eedp_observed_guard;
__le32 eedp_observed_ref_tag;
__le64 sense_data_buffer_address;
};
#define MPI3_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID (0x01)
#define MPI3_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID (0x02)
#define MPI3_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID (0x04)
#define MPI3_SCSI_STATUS_GOOD (0x00)
#define MPI3_SCSI_STATUS_CHECK_CONDITION (0x02)
#define MPI3_SCSI_STATUS_CONDITION_MET (0x04)
#define MPI3_SCSI_STATUS_BUSY (0x08)
#define MPI3_SCSI_STATUS_INTERMEDIATE (0x10)
#define MPI3_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
#define MPI3_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
#define MPI3_SCSI_STATUS_COMMAND_TERMINATED (0x22)
#define MPI3_SCSI_STATUS_TASK_SET_FULL (0x28)
#define MPI3_SCSI_STATUS_ACA_ACTIVE (0x30)
#define MPI3_SCSI_STATUS_TASK_ABORTED (0x40)
#define MPI3_SCSI_STATE_SENSE_MASK (0x03)
#define MPI3_SCSI_STATE_SENSE_VALID (0x00)
#define MPI3_SCSI_STATE_SENSE_FAILED (0x01)
#define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY (0x02)
#define MPI3_SCSI_STATE_SENSE_NOT_AVAILABLE (0x03)
#define MPI3_SCSI_STATE_NO_SCSI_STATUS (0x04)
#define MPI3_SCSI_STATE_TERMINATED (0x08)
#define MPI3_SCSI_STATE_RESPONSE_DATA_VALID (0x10)
#define MPI3_SCSI_RSP_RESPONSECODE_MASK (0x000000ff)
#define MPI3_SCSI_RSP_RESPONSECODE_SHIFT (0)
#define MPI3_SCSI_RSP_ARI2_MASK (0x0000ff00)
#define MPI3_SCSI_RSP_ARI2_SHIFT (8)
#define MPI3_SCSI_RSP_ARI1_MASK (0x00ff0000)
#define MPI3_SCSI_RSP_ARI1_SHIFT (16)
#define MPI3_SCSI_RSP_ARI0_MASK (0xff000000)
#define MPI3_SCSI_RSP_ARI0_SHIFT (24)
#define MPI3_SCSI_TASKTAG_UNKNOWN (0xffff)
#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02)
#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a)
#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00)
#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a)
#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81)
#endif
|
// SPDX-License-Identifier: GPL-2.0
/* Converted from tools/testing/selftests/bpf/verifier/regalloc.c */
#include <linux/bpf.h>
#include <bpf/bpf_helpers.h>
#include "bpf_misc.h"
#define MAX_ENTRIES 11
struct test_val {
unsigned int index;
int foo[MAX_ENTRIES];
};
struct {
__uint(type, BPF_MAP_TYPE_HASH);
__uint(max_entries, 1);
__type(key, long long);
__type(value, struct test_val);
} map_hash_48b SEC(".maps");
SEC("tracepoint")
__description("regalloc basic")
__success __flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_basic(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r0 s> 20 goto l0_%=; \
if r2 s< 0 goto l0_%=; \
r7 += r0; \
r7 += r2; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc negative")
__failure __msg("invalid access to map value, value_size=48 off=48 size=1")
__naked void regalloc_negative(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r0 s> 24 goto l0_%=; \
if r2 s< 0 goto l0_%=; \
r7 += r0; \
r7 += r2; \
r0 = *(u8*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc src_reg mark")
__success __flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_src_reg_mark(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r0 s> 20 goto l0_%=; \
r3 = 0; \
if r3 s>= r2 goto l0_%=; \
r7 += r0; \
r7 += r2; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc src_reg negative")
__failure __msg("invalid access to map value, value_size=48 off=44 size=8")
__flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_src_reg_negative(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r0 s> 22 goto l0_%=; \
r3 = 0; \
if r3 s>= r2 goto l0_%=; \
r7 += r0; \
r7 += r2; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc and spill")
__success __flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_and_spill(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r0 s> 20 goto l0_%=; \
/* r0 has upper bound that should propagate into r2 */\
*(u64*)(r10 - 8) = r2; /* spill r2 */ \
r0 = 0; \
r2 = 0; /* clear r0 and r2 */\
r3 = *(u64*)(r10 - 8); /* fill r3 */ \
if r0 s>= r3 goto l0_%=; \
/* r3 has lower and upper bounds */ \
r7 += r3; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc and spill negative")
__failure __msg("invalid access to map value, value_size=48 off=48 size=8")
__flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_and_spill_negative(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r0 s> 48 goto l0_%=; \
/* r0 has upper bound that should propagate into r2 */\
*(u64*)(r10 - 8) = r2; /* spill r2 */ \
r0 = 0; \
r2 = 0; /* clear r0 and r2 */\
r3 = *(u64*)(r10 - 8); /* fill r3 */\
if r0 s>= r3 goto l0_%=; \
/* r3 has lower and upper bounds */ \
r7 += r3; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc three regs")
__success __flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_three_regs(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r2 = r0; \
r4 = r2; \
if r0 s> 12 goto l0_%=; \
if r2 s< 0 goto l0_%=; \
r7 += r0; \
r7 += r2; \
r7 += r4; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
SEC("tracepoint")
__description("regalloc after call")
__success __flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_after_call(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r8 = r0; \
r9 = r0; \
call regalloc_after_call__1; \
if r8 s> 20 goto l0_%=; \
if r9 s< 0 goto l0_%=; \
r7 += r8; \
r7 += r9; \
r0 = *(u64*)(r7 + 0); \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
static __naked __noinline __attribute__((used))
void regalloc_after_call__1(void)
{
asm volatile (" \
r0 = 0; \
exit; \
" ::: __clobber_all);
}
SEC("tracepoint")
__description("regalloc in callee")
__success __flag(BPF_F_ANY_ALIGNMENT)
__naked void regalloc_in_callee(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
if r0 == 0 goto l0_%=; \
r7 = r0; \
call %[bpf_get_prandom_u32]; \
r1 = r0; \
r2 = r0; \
r3 = r7; \
call regalloc_in_callee__1; \
l0_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
static __naked __noinline __attribute__((used))
void regalloc_in_callee__1(void)
{
asm volatile (" \
if r1 s> 20 goto l0_%=; \
if r2 s< 0 goto l0_%=; \
r3 += r1; \
r3 += r2; \
r0 = *(u64*)(r3 + 0); \
exit; \
l0_%=: r0 = 0; \
exit; \
" ::: __clobber_all);
}
SEC("tracepoint")
__description("regalloc, spill, JEQ")
__success
__naked void regalloc_spill_jeq(void)
{
asm volatile (" \
r6 = r1; \
r1 = 0; \
*(u64*)(r10 - 8) = r1; \
r2 = r10; \
r2 += -8; \
r1 = %[map_hash_48b] ll; \
call %[bpf_map_lookup_elem]; \
*(u64*)(r10 - 8) = r0; /* spill r0 */ \
if r0 == 0 goto l0_%=; \
l0_%=: /* The verifier will walk the rest twice with r0 == 0 and r0 == map_value */\
call %[bpf_get_prandom_u32]; \
r2 = r0; \
if r2 == 20 goto l1_%=; \
l1_%=: /* The verifier will walk the rest two more times with r0 == 20 and r0 == unknown */\
r3 = *(u64*)(r10 - 8); /* fill r3 with map_value */\
if r3 == 0 goto l2_%=; /* skip ldx if map_value == NULL */\
/* Buggy verifier will think that r3 == 20 here */\
r0 = *(u64*)(r3 + 0); /* read from map_value */\
l2_%=: exit; \
" :
: __imm(bpf_get_prandom_u32),
__imm(bpf_map_lookup_elem),
__imm_addr(map_hash_48b)
: __clobber_all);
}
char _license[] SEC("license") = "GPL";
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ */
#ifndef BQ25980_CHARGER_H
#define BQ25980_CHARGER_H
#define BQ25980_MANUFACTURER "Texas Instruments"
#define BQ25980_BATOVP 0x0
#define BQ25980_BATOVP_ALM 0x1
#define BQ25980_BATOCP 0x2
#define BQ25980_BATOCP_ALM 0x3
#define BQ25980_BATUCP_ALM 0x4
#define BQ25980_CHRGR_CTRL_1 0x5
#define BQ25980_BUSOVP 0x6
#define BQ25980_BUSOVP_ALM 0x7
#define BQ25980_BUSOCP 0x8
#define BQ25980_BUSOCP_ALM 0x9
#define BQ25980_TEMP_CONTROL 0xA
#define BQ25980_TDIE_ALM 0xB
#define BQ25980_TSBUS_FLT 0xC
#define BQ25980_TSBAT_FLG 0xD
#define BQ25980_VAC_CONTROL 0xE
#define BQ25980_CHRGR_CTRL_2 0xF
#define BQ25980_CHRGR_CTRL_3 0x10
#define BQ25980_CHRGR_CTRL_4 0x11
#define BQ25980_CHRGR_CTRL_5 0x12
#define BQ25980_STAT1 0x13
#define BQ25980_STAT2 0x14
#define BQ25980_STAT3 0x15
#define BQ25980_STAT4 0x16
#define BQ25980_STAT5 0x17
#define BQ25980_FLAG1 0x18
#define BQ25980_FLAG2 0x19
#define BQ25980_FLAG3 0x1A
#define BQ25980_FLAG4 0x1B
#define BQ25980_FLAG5 0x1C
#define BQ25980_MASK1 0x1D
#define BQ25980_MASK2 0x1E
#define BQ25980_MASK3 0x1F
#define BQ25980_MASK4 0x20
#define BQ25980_MASK5 0x21
#define BQ25980_DEVICE_INFO 0x22
#define BQ25980_ADC_CONTROL1 0x23
#define BQ25980_ADC_CONTROL2 0x24
#define BQ25980_IBUS_ADC_MSB 0x25
#define BQ25980_IBUS_ADC_LSB 0x26
#define BQ25980_VBUS_ADC_MSB 0x27
#define BQ25980_VBUS_ADC_LSB 0x28
#define BQ25980_VAC1_ADC_MSB 0x29
#define BQ25980_VAC1_ADC_LSB 0x2A
#define BQ25980_VAC2_ADC_MSB 0x2B
#define BQ25980_VAC2_ADC_LSB 0x2C
#define BQ25980_VOUT_ADC_MSB 0x2D
#define BQ25980_VOUT_ADC_LSB 0x2E
#define BQ25980_VBAT_ADC_MSB 0x2F
#define BQ25980_VBAT_ADC_LSB 0x30
#define BQ25980_IBAT_ADC_MSB 0x31
#define BQ25980_IBAT_ADC_LSB 0x32
#define BQ25980_TSBUS_ADC_MSB 0x33
#define BQ25980_TSBUS_ADC_LSB 0x34
#define BQ25980_TSBAT_ADC_MSB 0x35
#define BQ25980_TSBAT_ADC_LSB 0x36
#define BQ25980_TDIE_ADC_MSB 0x37
#define BQ25980_TDIE_ADC_LSB 0x38
#define BQ25980_DEGLITCH_TIME 0x39
#define BQ25980_CHRGR_CTRL_6 0x3A
#define BQ25980_BUSOCP_STEP_uA 250000
#define BQ25980_BUSOCP_OFFSET_uA 1000000
#define BQ25980_BUSOCP_DFLT_uA 4250000
#define BQ25975_BUSOCP_DFLT_uA 4250000
#define BQ25960_BUSOCP_DFLT_uA 3250000
#define BQ25980_BUSOCP_MIN_uA 1000000
#define BQ25980_BUSOCP_SC_MAX_uA 5750000
#define BQ25975_BUSOCP_SC_MAX_uA 5750000
#define BQ25960_BUSOCP_SC_MAX_uA 3750000
#define BQ25980_BUSOCP_BYP_MAX_uA 8500000
#define BQ25975_BUSOCP_BYP_MAX_uA 8500000
#define BQ25960_BUSOCP_BYP_MAX_uA 5750000
#define BQ25980_BUSOVP_SC_STEP_uV 100000
#define BQ25975_BUSOVP_SC_STEP_uV 50000
#define BQ25960_BUSOVP_SC_STEP_uV 50000
#define BQ25980_BUSOVP_SC_OFFSET_uV 14000000
#define BQ25975_BUSOVP_SC_OFFSET_uV 7000000
#define BQ25960_BUSOVP_SC_OFFSET_uV 7000000
#define BQ25980_BUSOVP_BYP_STEP_uV 50000
#define BQ25975_BUSOVP_BYP_STEP_uV 25000
#define BQ25960_BUSOVP_BYP_STEP_uV 25000
#define BQ25980_BUSOVP_BYP_OFFSET_uV 7000000
#define BQ25975_BUSOVP_BYP_OFFSET_uV 3500000
#define BQ25960_BUSOVP_BYP_OFFSET_uV 3500000
#define BQ25980_BUSOVP_DFLT_uV 17800000
#define BQ25980_BUSOVP_BYPASS_DFLT_uV 8900000
#define BQ25975_BUSOVP_DFLT_uV 8900000
#define BQ25975_BUSOVP_BYPASS_DFLT_uV 4450000
#define BQ25960_BUSOVP_DFLT_uV 8900000
#define BQ25980_BUSOVP_SC_MIN_uV 14000000
#define BQ25975_BUSOVP_SC_MIN_uV 7000000
#define BQ25960_BUSOVP_SC_MIN_uV 7000000
#define BQ25980_BUSOVP_BYP_MIN_uV 7000000
#define BQ25975_BUSOVP_BYP_MIN_uV 3500000
#define BQ25960_BUSOVP_BYP_MIN_uV 3500000
#define BQ25980_BUSOVP_SC_MAX_uV 22000000
#define BQ25975_BUSOVP_SC_MAX_uV 12750000
#define BQ25960_BUSOVP_SC_MAX_uV 12750000
#define BQ25980_BUSOVP_BYP_MAX_uV 12750000
#define BQ25975_BUSOVP_BYP_MAX_uV 6500000
#define BQ25960_BUSOVP_BYP_MAX_uV 6500000
#define BQ25980_BATOVP_STEP_uV 20000
#define BQ25975_BATOVP_STEP_uV 10000
#define BQ25960_BATOVP_STEP_uV 10000
#define BQ25980_BATOVP_OFFSET_uV 7000000
#define BQ25975_BATOVP_OFFSET_uV 3500000
#define BQ25960_BATOVP_OFFSET_uV 3500000
#define BQ25980_BATOVP_DFLT_uV 14000000
#define BQ25975_BATOVP_DFLT_uV 8900000
#define BQ25960_BATOVP_DFLT_uV 8900000
#define BQ25980_BATOVP_MIN_uV 7000000
#define BQ25975_BATOVP_MIN_uV 3500000
#define BQ25960_BATOVP_MIN_uV 3500000
#define BQ25980_BATOVP_MAX_uV 9540000
#define BQ25975_BATOVP_MAX_uV 4770000
#define BQ25960_BATOVP_MAX_uV 4770000
#define BQ25980_BATOCP_STEP_uA 100000
#define BQ25980_BATOCP_MASK GENMASK(6, 0)
#define BQ25980_BATOCP_DFLT_uA 8100000
#define BQ25960_BATOCP_DFLT_uA 6100000
#define BQ25980_BATOCP_MIN_uA 2000000
#define BQ25980_BATOCP_MAX_uA 11000000
#define BQ25975_BATOCP_MAX_uA 11000000
#define BQ25960_BATOCP_MAX_uA 7000000
#define BQ25980_ENABLE_HIZ 0xff
#define BQ25980_DISABLE_HIZ 0x0
#define BQ25980_EN_BYPASS BIT(3)
#define BQ25980_STAT1_OVP_MASK (BIT(6) | BIT(5) | BIT(0))
#define BQ25980_STAT3_OVP_MASK (BIT(7) | BIT(6))
#define BQ25980_STAT1_OCP_MASK BIT(3)
#define BQ25980_STAT2_OCP_MASK (BIT(6) | BIT(1))
#define BQ25980_STAT4_TFLT_MASK GENMASK(5, 1)
#define BQ25980_WD_STAT BIT(0)
#define BQ25980_PRESENT_MASK GENMASK(4, 2)
#define BQ25980_CHG_EN BIT(4)
#define BQ25980_EN_HIZ BIT(6)
#define BQ25980_ADC_EN BIT(7)
#define BQ25980_ADC_VOLT_STEP_uV 1000
#define BQ25980_ADC_CURR_STEP_uA 1000
#define BQ25980_ADC_POLARITY_BIT BIT(7)
#define BQ25980_WATCHDOG_MASK GENMASK(4, 3)
#define BQ25980_WATCHDOG_DIS BIT(2)
#define BQ25980_WATCHDOG_MAX 300000
#define BQ25980_WATCHDOG_MIN 0
#define BQ25980_NUM_WD_VAL 4
#endif /* BQ25980_CHARGER_H */
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Yangtao Li <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_nm.h"
#include "ccu-sun50i-a100-r.h"
static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
"iosc", "pll-periph0" };
static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
{ .index = 3, .shift = 0, .width = 5 },
};
static struct ccu_div r_cpus_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 24,
.width = 2,
.var_predivs = cpus_r_apb2_predivs,
.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
},
.common = {
.reg = 0x000,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("cpus",
cpus_r_apb2_parents,
&ccu_div_ops,
0),
},
};
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
static struct ccu_div r_apb1_clk = {
.div = _SUNXI_CCU_DIV(0, 2),
.common = {
.reg = 0x00c,
.hw.init = CLK_HW_INIT("r-apb1",
"r-ahb",
&ccu_div_ops,
0),
},
};
static struct ccu_div r_apb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 24,
.width = 2,
.var_predivs = cpus_r_apb2_predivs,
.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
},
.common = {
.reg = 0x010,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("r-apb2",
cpus_r_apb2_parents,
&ccu_div_ops,
0),
},
};
static const struct clk_parent_data clk_parent_r_apb1[] = {
{ .hw = &r_apb1_clk.common.hw },
};
static const struct clk_parent_data clk_parent_r_apb2[] = {
{ .hw = &r_apb2_clk.common.hw },
};
static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
0x11c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
0x12c, BIT(0), 0);
static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
"iosc" };
static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,
0x130, 24, 2, 0);
static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm",
clk_parent_r_apb1, 0x13c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1,
0x17c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,
0x18c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,
0x19c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,
0x19c, BIT(1), 0);
static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
r_apb1_ir_rx_parents, 0x1c0,
0, 5, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx",
clk_parent_r_apb1, 0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
0x20c, BIT(0), 0);
static struct ccu_common *sun50i_a100_r_ccu_clks[] = {
&r_cpus_clk.common,
&r_apb1_clk.common,
&r_apb2_clk.common,
&r_apb1_timer_clk.common,
&r_apb1_twd_clk.common,
&r_apb1_pwm_clk.common,
&r_apb1_bus_pwm_clk.common,
&r_apb1_ppu_clk.common,
&r_apb2_uart_clk.common,
&r_apb2_i2c0_clk.common,
&r_apb2_i2c1_clk.common,
&r_apb1_ir_rx_clk.common,
&r_apb1_bus_ir_rx_clk.common,
&r_ahb_bus_rtc_clk.common,
};
static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
.hws = {
[CLK_R_CPUS] = &r_cpus_clk.common.hw,
[CLK_R_AHB] = &r_ahb_clk.hw,
[CLK_R_APB1] = &r_apb1_clk.common.hw,
[CLK_R_APB2] = &r_apb2_clk.common.hw,
[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
[CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw,
[CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw,
[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
[CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw,
[CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw,
[CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
[CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
[CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
},
.num = CLK_NUMBER,
};
static const struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
[RST_R_APB1_PPU] = { 0x17c, BIT(16) },
[RST_R_APB2_UART] = { 0x18c, BIT(16) },
[RST_R_APB2_I2C0] = { 0x19c, BIT(16) },
[RST_R_APB2_I2C1] = { 0x19c, BIT(17) },
[RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
[RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
};
static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = {
.ccu_clks = sun50i_a100_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a100_r_ccu_clks),
.hw_clks = &sun50i_a100_r_hw_clks,
.resets = sun50i_a100_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_a100_r_ccu_resets),
};
static int sun50i_a100_r_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a100_r_ccu_desc);
}
static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-r-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a100_r_ccu_ids);
static struct platform_driver sun50i_a100_r_ccu_driver = {
.probe = sun50i_a100_r_ccu_probe,
.driver = {
.name = "sun50i-a100-r-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_a100_r_ccu_ids,
},
};
module_platform_driver(sun50i_a100_r_ccu_driver);
MODULE_IMPORT_NS("SUNXI_CCU");
MODULE_DESCRIPTION("Support for the Allwinner A100 PRCM CCU");
MODULE_LICENSE("GPL");
|
/*
* Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __CHIOCTL_H__
#define __CHIOCTL_H__
/*
* Ioctl commands specific to this driver.
*/
enum {
CHELSIO_GETMTUTAB = 1029,
CHELSIO_SETMTUTAB = 1030,
CHELSIO_SET_PM = 1032,
CHELSIO_GET_PM = 1033,
CHELSIO_GET_MEM = 1038,
CHELSIO_LOAD_FW = 1041,
CHELSIO_SET_TRACE_FILTER = 1044,
CHELSIO_SET_QSET_PARAMS = 1045,
CHELSIO_GET_QSET_PARAMS = 1046,
CHELSIO_SET_QSET_NUM = 1047,
CHELSIO_GET_QSET_NUM = 1048,
};
struct ch_reg {
uint32_t cmd;
uint32_t addr;
uint32_t val;
};
struct ch_cntxt {
uint32_t cmd;
uint32_t cntxt_type;
uint32_t cntxt_id;
uint32_t data[4];
};
/* context types */
enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
struct ch_desc {
uint32_t cmd;
uint32_t queue_num;
uint32_t idx;
uint32_t size;
uint8_t data[128];
};
struct ch_mem_range {
uint32_t cmd;
uint32_t mem_id;
uint32_t addr;
uint32_t len;
uint32_t version;
uint8_t buf[];
};
struct ch_qset_params {
uint32_t cmd;
uint32_t qset_idx;
int32_t txq_size[3];
int32_t rspq_size;
int32_t fl_size[2];
int32_t intr_lat;
int32_t polling;
int32_t lro;
int32_t cong_thres;
int32_t vector;
int32_t qnum;
};
struct ch_pktsched_params {
uint32_t cmd;
uint8_t sched;
uint8_t idx;
uint8_t min;
uint8_t max;
uint8_t binding;
};
#ifndef TCB_SIZE
# define TCB_SIZE 128
#endif
/* TCB size in 32-bit words */
#define TCB_WORDS (TCB_SIZE / 4)
enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */
struct ch_mtus {
uint32_t cmd;
uint32_t nmtus;
uint16_t mtus[NMTUS];
};
struct ch_pm {
uint32_t cmd;
uint32_t tx_pg_sz;
uint32_t tx_num_pg;
uint32_t rx_pg_sz;
uint32_t rx_num_pg;
uint32_t pm_total;
};
struct ch_tcam {
uint32_t cmd;
uint32_t tcam_size;
uint32_t nservers;
uint32_t nroutes;
uint32_t nfilters;
};
struct ch_tcb {
uint32_t cmd;
uint32_t tcb_index;
uint32_t tcb_data[TCB_WORDS];
};
struct ch_tcam_word {
uint32_t cmd;
uint32_t addr;
uint32_t buf[3];
};
struct ch_trace {
uint32_t cmd;
uint32_t sip;
uint32_t sip_mask;
uint32_t dip;
uint32_t dip_mask;
uint16_t sport;
uint16_t sport_mask;
uint16_t dport;
uint16_t dport_mask;
uint32_t vlan:12;
uint32_t vlan_mask:12;
uint32_t intf:4;
uint32_t intf_mask:4;
uint8_t proto;
uint8_t proto_mask;
uint8_t invert_match:1;
uint8_t config_tx:1;
uint8_t config_rx:1;
uint8_t trace_tx:1;
uint8_t trace_rx:1;
};
#define SIOCCHIOCTL SIOCDEVPRIVATE
#endif
|
// SPDX-License-Identifier: GPL-2.0
/*
* Keystone 2 Kepler/Hawking EVM device tree
*
* Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "keystone.dtsi"
#include "keystone-k2hk.dtsi"
/ {
compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dsp_common_memory: dsp-common-memory@81f800000 {
compatible = "shared-dma-pool";
reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
reusable;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led-debug-1-1 {
label = "keystone:green:debug1";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
};
led-debug-1-2 {
label = "keystone:red:debug1";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
};
led-debug-2 {
label = "keystone:blue:debug2";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
};
led-debug-3 {
label = "keystone:blue:debug3";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
};
};
};
&soc0 {
clocks {
refclksys: refclksys {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <122880000>;
clock-output-names = "refclk-sys";
};
refclkpass: refclkpass {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <122880000>;
clock-output-names = "refclk-pass";
};
refclkarm: refclkarm {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "refclk-arm";
};
refclkddr3a: refclkddr3a {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "refclk-ddr3a";
};
refclkddr3b: refclkddr3b {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "refclk-ddr3b";
};
};
};
&usb_phy {
status = "okay";
};
&keystone_usb0 {
status = "okay";
};
&usb0 {
dr_mode = "host";
};
&aemif {
cs0 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <0>;
/* all timings in nanoseconds */
ti,cs-min-turnaround-ns = <12>;
ti,cs-read-hold-ns = <6>;
ti,cs-read-strobe-ns = <23>;
ti,cs-read-setup-ns = <9>;
ti,cs-write-hold-ns = <8>;
ti,cs-write-strobe-ns = <23>;
ti,cs-write-setup-ns = <8>;
nand@0,0 {
compatible = "ti,keystone-nand","ti,davinci-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x4000000
1 0 0x0000100>;
ti,davinci-chipselect = <0>;
ti,davinci-mask-ale = <0x2000>;
ti,davinci-mask-cle = <0x4000>;
ti,davinci-mask-chipsel = <0>;
nand-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
nand-on-flash-bbt;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "params";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "ubifs";
reg = <0x180000 0x1fe80000>;
};
};
};
};
&i2c0 {
eeprom@50 {
compatible = "atmel,24c1024";
reg = <0x50>;
};
};
&spi0 {
nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <54000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "misc";
reg = <0x80000 0xf80000>;
};
};
};
&mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&dsp0 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp1 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp2 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp3 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp4 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp5 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp6 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp7 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
|
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2020 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_
#define ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_
/*
*****************************************
* ARC_FARM_ARC0_ACP_ENG
* (Prototype: ARC_ACP_ENG)
*****************************************
*/
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0 0x4E8F000
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_1 0x4E8F004
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_2 0x4E8F008
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_3 0x4E8F00C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_4 0x4E8F010
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_5 0x4E8F014
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_6 0x4E8F018
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_7 0x4E8F01C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_8 0x4E8F020
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_9 0x4E8F024
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_10 0x4E8F028
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_11 0x4E8F02C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_12 0x4E8F030
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_13 0x4E8F034
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_14 0x4E8F038
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_15 0x4E8F03C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_16 0x4E8F040
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_17 0x4E8F044
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_18 0x4E8F048
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_19 0x4E8F04C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_20 0x4E8F050
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_21 0x4E8F054
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_22 0x4E8F058
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_23 0x4E8F05C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_24 0x4E8F060
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_25 0x4E8F064
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_26 0x4E8F068
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_27 0x4E8F06C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_28 0x4E8F070
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_29 0x4E8F074
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_30 0x4E8F078
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_31 0x4E8F07C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_32 0x4E8F080
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_33 0x4E8F084
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_34 0x4E8F088
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_35 0x4E8F08C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_36 0x4E8F090
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_37 0x4E8F094
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_38 0x4E8F098
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_39 0x4E8F09C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_40 0x4E8F0A0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_41 0x4E8F0A4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_42 0x4E8F0A8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_43 0x4E8F0AC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_44 0x4E8F0B0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_45 0x4E8F0B4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_46 0x4E8F0B8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_47 0x4E8F0BC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_48 0x4E8F0C0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_49 0x4E8F0C4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_50 0x4E8F0C8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_51 0x4E8F0CC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_52 0x4E8F0D0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_53 0x4E8F0D4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_54 0x4E8F0D8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_55 0x4E8F0DC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_56 0x4E8F0E0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_57 0x4E8F0E4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_58 0x4E8F0E8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_59 0x4E8F0EC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_60 0x4E8F0F0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_61 0x4E8F0F4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_62 0x4E8F0F8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_63 0x4E8F0FC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_0 0x4E8F100
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_1 0x4E8F104
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_2 0x4E8F108
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_3 0x4E8F10C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_4 0x4E8F110
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_5 0x4E8F114
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_6 0x4E8F118
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_7 0x4E8F11C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_8 0x4E8F120
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_9 0x4E8F124
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_10 0x4E8F128
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_11 0x4E8F12C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_12 0x4E8F130
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_13 0x4E8F134
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_14 0x4E8F138
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_15 0x4E8F13C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_16 0x4E8F140
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_17 0x4E8F144
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_18 0x4E8F148
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_19 0x4E8F14C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_20 0x4E8F150
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_21 0x4E8F154
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_22 0x4E8F158
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_23 0x4E8F15C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_24 0x4E8F160
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_25 0x4E8F164
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_26 0x4E8F168
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_27 0x4E8F16C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_28 0x4E8F170
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_29 0x4E8F174
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_30 0x4E8F178
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_31 0x4E8F17C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_32 0x4E8F180
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_33 0x4E8F184
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_34 0x4E8F188
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_35 0x4E8F18C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_36 0x4E8F190
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_37 0x4E8F194
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_38 0x4E8F198
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_39 0x4E8F19C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_40 0x4E8F1A0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_41 0x4E8F1A4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_42 0x4E8F1A8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_43 0x4E8F1AC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_44 0x4E8F1B0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_45 0x4E8F1B4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_46 0x4E8F1B8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_47 0x4E8F1BC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_48 0x4E8F1C0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_49 0x4E8F1C4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_50 0x4E8F1C8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_51 0x4E8F1CC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_52 0x4E8F1D0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_53 0x4E8F1D4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_54 0x4E8F1D8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_55 0x4E8F1DC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_56 0x4E8F1E0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_57 0x4E8F1E4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_58 0x4E8F1E8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_59 0x4E8F1EC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_60 0x4E8F1F0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_61 0x4E8F1F4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_62 0x4E8F1F8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_63 0x4E8F1FC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_0 0x4E8F200
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_1 0x4E8F204
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_2 0x4E8F208
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_3 0x4E8F20C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_4 0x4E8F210
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_5 0x4E8F214
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_6 0x4E8F218
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_7 0x4E8F21C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_8 0x4E8F220
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_9 0x4E8F224
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_10 0x4E8F228
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_11 0x4E8F22C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_12 0x4E8F230
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_13 0x4E8F234
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_14 0x4E8F238
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_15 0x4E8F23C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_16 0x4E8F240
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_17 0x4E8F244
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_18 0x4E8F248
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_19 0x4E8F24C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_20 0x4E8F250
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_21 0x4E8F254
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_22 0x4E8F258
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_23 0x4E8F25C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_24 0x4E8F260
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_25 0x4E8F264
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_26 0x4E8F268
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_27 0x4E8F26C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_28 0x4E8F270
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_29 0x4E8F274
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_30 0x4E8F278
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_31 0x4E8F27C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_32 0x4E8F280
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_33 0x4E8F284
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_34 0x4E8F288
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_35 0x4E8F28C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_36 0x4E8F290
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_37 0x4E8F294
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_38 0x4E8F298
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_39 0x4E8F29C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_40 0x4E8F2A0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_41 0x4E8F2A4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_42 0x4E8F2A8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_43 0x4E8F2AC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_44 0x4E8F2B0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_45 0x4E8F2B4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_46 0x4E8F2B8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_47 0x4E8F2BC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_48 0x4E8F2C0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_49 0x4E8F2C4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_50 0x4E8F2C8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_51 0x4E8F2CC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_52 0x4E8F2D0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_53 0x4E8F2D4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_54 0x4E8F2D8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_55 0x4E8F2DC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_56 0x4E8F2E0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_57 0x4E8F2E4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_58 0x4E8F2E8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_59 0x4E8F2EC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_60 0x4E8F2F0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_61 0x4E8F2F4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_62 0x4E8F2F8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_63 0x4E8F2FC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_0 0x4E8F300
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_1 0x4E8F304
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_2 0x4E8F308
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_3 0x4E8F30C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_4 0x4E8F310
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_5 0x4E8F314
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_6 0x4E8F318
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_7 0x4E8F31C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_8 0x4E8F320
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_9 0x4E8F324
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_10 0x4E8F328
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_11 0x4E8F32C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_12 0x4E8F330
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_13 0x4E8F334
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_14 0x4E8F338
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_15 0x4E8F33C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_16 0x4E8F340
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_17 0x4E8F344
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_18 0x4E8F348
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_19 0x4E8F34C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_20 0x4E8F350
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_21 0x4E8F354
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_22 0x4E8F358
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_23 0x4E8F35C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_24 0x4E8F360
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_25 0x4E8F364
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_26 0x4E8F368
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_27 0x4E8F36C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_28 0x4E8F370
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_29 0x4E8F374
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_30 0x4E8F378
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_31 0x4E8F37C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_32 0x4E8F380
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_33 0x4E8F384
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_34 0x4E8F388
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_35 0x4E8F38C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_36 0x4E8F390
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_37 0x4E8F394
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_38 0x4E8F398
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_39 0x4E8F39C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_40 0x4E8F3A0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_41 0x4E8F3A4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_42 0x4E8F3A8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_43 0x4E8F3AC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_44 0x4E8F3B0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_45 0x4E8F3B4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_46 0x4E8F3B8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_47 0x4E8F3BC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_48 0x4E8F3C0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_49 0x4E8F3C4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_50 0x4E8F3C8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_51 0x4E8F3CC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_52 0x4E8F3D0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_53 0x4E8F3D4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_54 0x4E8F3D8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_55 0x4E8F3DC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_56 0x4E8F3E0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_57 0x4E8F3E4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_58 0x4E8F3E8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_59 0x4E8F3EC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_60 0x4E8F3F0
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_61 0x4E8F3F4
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_62 0x4E8F3F8
#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_63 0x4E8F3FC
#define mmARC_FARM_ARC0_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x4E8F400
#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x4E8F404
#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x4E8F408
#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x4E8F40C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x4E8F410
#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x4E8F414
#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x4E8F418
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x4E8F41C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x4E8F420
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x4E8F424
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x4E8F428
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x4E8F42C
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x4E8F430
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x4E8F434
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x4E8F438
#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG 0x4E8F43C
#endif /* ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ */
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* HD-Audio helpers to sync with i915 driver
*/
#ifndef __SOUND_HDA_I915_H
#define __SOUND_HDA_I915_H
#include "hda_component.h"
#ifdef CONFIG_SND_HDA_I915
void snd_hdac_i915_set_bclk(struct hdac_bus *bus);
int snd_hdac_i915_init(struct hdac_bus *bus);
#else
static inline void snd_hdac_i915_set_bclk(struct hdac_bus *bus)
{
}
static inline int snd_hdac_i915_init(struct hdac_bus *bus)
{
return -ENODEV;
}
#endif
static inline int snd_hdac_i915_exit(struct hdac_bus *bus)
{
return snd_hdac_acomp_exit(bus);
}
#endif /* __SOUND_HDA_I915_H */
|
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. */
#include <linux/cleanup.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pm_domain.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/soc/qcom/smd-rpm.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#define domain_to_rpmpd(domain) container_of(domain, struct rpmpd, pd)
static struct qcom_smd_rpm *rpmpd_smd_rpm;
/* Resource types:
* RPMPD_X is X encoded as a little-endian, lower-case, ASCII string */
#define RPMPD_SMPA 0x61706d73
#define RPMPD_LDOA 0x616f646c
#define RPMPD_SMPB 0x62706d73
#define RPMPD_LDOB 0x626f646c
#define RPMPD_RWCX 0x78637772
#define RPMPD_RWMX 0x786d7772
#define RPMPD_RWLC 0x636c7772
#define RPMPD_RWLM 0x6d6c7772
#define RPMPD_RWSC 0x63737772
#define RPMPD_RWSM 0x6d737772
#define RPMPD_RWGX 0x78677772
/* Operation Keys */
#define KEY_CORNER 0x6e726f63 /* corn */
#define KEY_ENABLE 0x6e657773 /* swen */
#define KEY_FLOOR_CORNER 0x636676 /* vfc */
#define KEY_FLOOR_LEVEL 0x6c6676 /* vfl */
#define KEY_LEVEL 0x6c766c76 /* vlvl */
#define MAX_CORNER_RPMPD_STATE 6
struct rpmpd_req {
__le32 key;
__le32 nbytes;
__le32 value;
};
struct rpmpd {
struct generic_pm_domain pd;
struct generic_pm_domain *parent;
struct rpmpd *peer;
const bool active_only;
unsigned int corner;
bool enabled;
const int res_type;
const int res_id;
unsigned int max_state;
__le32 key;
bool state_synced;
};
struct rpmpd_desc {
struct rpmpd **rpmpds;
size_t num_pds;
unsigned int max_state;
};
static DEFINE_MUTEX(rpmpd_lock);
/* CX */
static struct rpmpd cx_rwcx0_lvl_ao;
static struct rpmpd cx_rwcx0_lvl = {
.pd = { .name = "cx", },
.peer = &cx_rwcx0_lvl_ao,
.res_type = RPMPD_RWCX,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd cx_rwcx0_lvl_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_rwcx0_lvl,
.active_only = true,
.res_type = RPMPD_RWCX,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd cx_s1a_corner_ao;
static struct rpmpd cx_s1a_corner = {
.pd = { .name = "cx", },
.peer = &cx_s1a_corner_ao,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_CORNER,
};
static struct rpmpd cx_s1a_corner_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_s1a_corner,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_CORNER,
};
static struct rpmpd cx_s1a_lvl_ao;
static struct rpmpd cx_s1a_lvl = {
.pd = { .name = "cx", },
.peer = &cx_s1a_lvl_ao,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_LEVEL,
};
static struct rpmpd cx_s1a_lvl_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_s1a_lvl,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_LEVEL,
};
static struct rpmpd cx_s2a_corner_ao;
static struct rpmpd cx_s2a_corner = {
.pd = { .name = "cx", },
.peer = &cx_s2a_corner_ao,
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd cx_s2a_corner_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_s2a_corner,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd cx_s2a_lvl_ao;
static struct rpmpd cx_s2a_lvl = {
.pd = { .name = "cx", },
.peer = &cx_s2a_lvl_ao,
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_LEVEL,
};
static struct rpmpd cx_s2a_lvl_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_s2a_lvl,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_LEVEL,
};
static struct rpmpd cx_s3a_lvl_ao;
static struct rpmpd cx_s3a_lvl = {
.pd = { .name = "cx", },
.peer = &cx_s3a_lvl_ao,
.res_type = RPMPD_SMPA,
.res_id = 3,
.key = KEY_LEVEL,
};
static struct rpmpd cx_s3a_lvl_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_s3a_lvl,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 3,
.key = KEY_LEVEL,
};
static struct rpmpd cx_rwcx0_vfl = {
.pd = { .name = "cx_vfl", },
.res_type = RPMPD_RWCX,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd cx_rwsc2_vfl = {
.pd = { .name = "cx_vfl", },
.res_type = RPMPD_RWSC,
.res_id = 2,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd cx_s1a_vfc = {
.pd = { .name = "cx_vfc", },
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_FLOOR_CORNER,
};
static struct rpmpd cx_s1a_vfl = {
.pd = { .name = "cx_vfl", },
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd cx_s2a_vfc = {
.pd = { .name = "cx_vfc", },
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_FLOOR_CORNER,
};
static struct rpmpd cx_s2a_vfl = {
.pd = { .name = "cx_vfl", },
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd cx_s3a_vfl = {
.pd = { .name = "cx_vfl", },
.res_type = RPMPD_SMPA,
.res_id = 3,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd cx_s2b_corner_ao;
static struct rpmpd cx_s2b_corner = {
.pd = { .name = "cx", },
.peer = &cx_s2b_corner_ao,
.res_type = RPMPD_SMPB,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd cx_s2b_corner_ao = {
.pd = { .name = "cx_ao", },
.peer = &cx_s2b_corner,
.active_only = true,
.res_type = RPMPD_SMPB,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd cx_s2b_vfc = {
.pd = { .name = "cx_vfc", },
.res_type = RPMPD_SMPB,
.res_id = 2,
.key = KEY_FLOOR_CORNER,
};
/* G(F)X */
static struct rpmpd gfx_s7a_corner = {
.pd = { .name = "gfx", },
.res_type = RPMPD_SMPA,
.res_id = 7,
.key = KEY_CORNER,
};
static struct rpmpd gfx_s7a_vfc = {
.pd = { .name = "gfx_vfc", },
.res_type = RPMPD_SMPA,
.res_id = 7,
.key = KEY_FLOOR_CORNER,
};
static struct rpmpd gfx_s2b_corner = {
.pd = { .name = "gfx", },
.res_type = RPMPD_SMPB,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd gfx_s2b_vfc = {
.pd = { .name = "gfx_vfc", },
.res_type = RPMPD_SMPB,
.res_id = 2,
.key = KEY_FLOOR_CORNER,
};
static struct rpmpd gfx_s4b_corner = {
.pd = { .name = "gfx", },
.res_type = RPMPD_SMPB,
.res_id = 4,
.key = KEY_CORNER,
};
static struct rpmpd gfx_s4b_vfc = {
.pd = { .name = "gfx_vfc", },
.res_type = RPMPD_SMPB,
.res_id = 4,
.key = KEY_FLOOR_CORNER,
};
static struct rpmpd mx_rwmx0_lvl;
static struct rpmpd gx_rwgx0_lvl_ao;
static struct rpmpd gx_rwgx0_lvl = {
.pd = { .name = "gx", },
.peer = &gx_rwgx0_lvl_ao,
.res_type = RPMPD_RWGX,
.parent = &mx_rwmx0_lvl.pd,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd mx_rwmx0_lvl_ao;
static struct rpmpd gx_rwgx0_lvl_ao = {
.pd = { .name = "gx_ao", },
.peer = &gx_rwgx0_lvl,
.parent = &mx_rwmx0_lvl_ao.pd,
.active_only = true,
.res_type = RPMPD_RWGX,
.res_id = 0,
.key = KEY_LEVEL,
};
/* MX */
static struct rpmpd mx_l2a_lvl_ao;
static struct rpmpd mx_l2a_lvl = {
.pd = { .name = "mx", },
.peer = &mx_l2a_lvl_ao,
.res_type = RPMPD_LDOA,
.res_id = 2,
.key = KEY_LEVEL,
};
static struct rpmpd mx_l2a_lvl_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_l2a_lvl,
.active_only = true,
.res_type = RPMPD_LDOA,
.res_id = 2,
.key = KEY_LEVEL,
};
static struct rpmpd mx_l3a_corner_ao;
static struct rpmpd mx_l3a_corner = {
.pd = { .name = "mx", },
.peer = &mx_l3a_corner_ao,
.res_type = RPMPD_LDOA,
.res_id = 3,
.key = KEY_CORNER,
};
static struct rpmpd mx_l3a_corner_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_l3a_corner,
.active_only = true,
.res_type = RPMPD_LDOA,
.res_id = 3,
.key = KEY_CORNER,
};
static struct rpmpd mx_l3a_lvl_ao;
static struct rpmpd mx_l3a_lvl = {
.pd = { .name = "mx", },
.peer = &mx_l3a_lvl_ao,
.res_type = RPMPD_LDOA,
.res_id = 3,
.key = KEY_LEVEL,
};
static struct rpmpd mx_l3a_lvl_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_l3a_lvl,
.active_only = true,
.res_type = RPMPD_LDOA,
.res_id = 3,
.key = KEY_LEVEL,
};
static struct rpmpd mx_l12a_lvl_ao;
static struct rpmpd mx_l12a_lvl = {
.pd = { .name = "mx", },
.peer = &mx_l12a_lvl_ao,
.res_type = RPMPD_LDOA,
.res_id = 12,
.key = KEY_LEVEL,
};
static struct rpmpd mx_l12a_lvl_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_l12a_lvl,
.active_only = true,
.res_type = RPMPD_LDOA,
.res_id = 12,
.key = KEY_LEVEL,
};
static struct rpmpd mx_s2a_corner_ao;
static struct rpmpd mx_s2a_corner = {
.pd = { .name = "mx", },
.peer = &mx_s2a_corner_ao,
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd mx_s2a_corner_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_s2a_corner,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 2,
.key = KEY_CORNER,
};
static struct rpmpd mx_rwmx0_lvl_ao;
static struct rpmpd mx_rwmx0_lvl = {
.pd = { .name = "mx", },
.peer = &mx_rwmx0_lvl_ao,
.res_type = RPMPD_RWMX,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd mx_rwmx0_lvl_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_rwmx0_lvl,
.active_only = true,
.res_type = RPMPD_RWMX,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd mx_s6a_lvl_ao;
static struct rpmpd mx_s6a_lvl = {
.pd = { .name = "mx", },
.peer = &mx_s6a_lvl_ao,
.res_type = RPMPD_SMPA,
.res_id = 6,
.key = KEY_LEVEL,
};
static struct rpmpd mx_s6a_lvl_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_s6a_lvl,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 6,
.key = KEY_LEVEL,
};
static struct rpmpd mx_s7a_lvl_ao;
static struct rpmpd mx_s7a_lvl = {
.pd = { .name = "mx", },
.peer = &mx_s7a_lvl_ao,
.res_type = RPMPD_SMPA,
.res_id = 7,
.key = KEY_LEVEL,
};
static struct rpmpd mx_s7a_lvl_ao = {
.pd = { .name = "mx_ao", },
.peer = &mx_s7a_lvl,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 7,
.key = KEY_LEVEL,
};
static struct rpmpd mx_l12a_vfl = {
.pd = { .name = "mx_vfl", },
.res_type = RPMPD_LDOA,
.res_id = 12,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd mx_rwmx0_vfl = {
.pd = { .name = "mx_vfl", },
.res_type = RPMPD_RWMX,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd mx_rwsm6_vfl = {
.pd = { .name = "mx_vfl", },
.res_type = RPMPD_RWSM,
.res_id = 6,
.key = KEY_FLOOR_LEVEL,
};
/* MD */
static struct rpmpd md_s1a_corner_ao;
static struct rpmpd md_s1a_corner = {
.pd = { .name = "md", },
.peer = &md_s1a_corner_ao,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_CORNER,
};
static struct rpmpd md_s1a_corner_ao = {
.pd = { .name = "md_ao", },
.peer = &md_s1a_corner,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_CORNER,
};
static struct rpmpd md_s1a_lvl_ao;
static struct rpmpd md_s1a_lvl = {
.pd = { .name = "md", },
.peer = &md_s1a_lvl_ao,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_LEVEL,
};
static struct rpmpd md_s1a_lvl_ao = {
.pd = { .name = "md_ao", },
.peer = &md_s1a_lvl,
.active_only = true,
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_LEVEL,
};
static struct rpmpd md_s1a_vfc = {
.pd = { .name = "md_vfc", },
.res_type = RPMPD_SMPA,
.res_id = 1,
.key = KEY_FLOOR_CORNER,
};
/* LPI_CX */
static struct rpmpd lpi_cx_rwlc0_lvl = {
.pd = { .name = "lpi_cx", },
.res_type = RPMPD_RWLC,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd lpi_cx_rwlc0_vfl = {
.pd = { .name = "lpi_cx_vfl", },
.res_type = RPMPD_RWLC,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
/* LPI_MX */
static struct rpmpd lpi_mx_rwlm0_lvl = {
.pd = { .name = "lpi_mx", },
.res_type = RPMPD_RWLM,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd lpi_mx_rwlm0_vfl = {
.pd = { .name = "lpi_mx_vfl", },
.res_type = RPMPD_RWLM,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
/* SSC_CX */
static struct rpmpd ssc_cx_l26a_corner = {
.pd = { .name = "ssc_cx", },
.res_type = RPMPD_LDOA,
.res_id = 26,
.key = KEY_CORNER,
};
static struct rpmpd ssc_cx_rwlc0_lvl = {
.pd = { .name = "ssc_cx", },
.res_type = RPMPD_RWLC,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd ssc_cx_rwsc0_lvl = {
.pd = { .name = "ssc_cx", },
.res_type = RPMPD_RWSC,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd ssc_cx_l26a_vfc = {
.pd = { .name = "ssc_cx_vfc", },
.res_type = RPMPD_LDOA,
.res_id = 26,
.key = KEY_FLOOR_CORNER,
};
static struct rpmpd ssc_cx_rwlc0_vfl = {
.pd = { .name = "ssc_cx_vfl", },
.res_type = RPMPD_RWLC,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd ssc_cx_rwsc0_vfl = {
.pd = { .name = "ssc_cx_vfl", },
.res_type = RPMPD_RWSC,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
/* SSC_MX */
static struct rpmpd ssc_mx_rwlm0_lvl = {
.pd = { .name = "ssc_mx", },
.res_type = RPMPD_RWLM,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd ssc_mx_rwsm0_lvl = {
.pd = { .name = "ssc_mx", },
.res_type = RPMPD_RWSM,
.res_id = 0,
.key = KEY_LEVEL,
};
static struct rpmpd ssc_mx_rwlm0_vfl = {
.pd = { .name = "ssc_mx_vfl", },
.res_type = RPMPD_RWLM,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd ssc_mx_rwsm0_vfl = {
.pd = { .name = "ssc_mx_vfl", },
.res_type = RPMPD_RWSM,
.res_id = 0,
.key = KEY_FLOOR_LEVEL,
};
static struct rpmpd *mdm9607_rpmpds[] = {
[MDM9607_VDDCX] = &cx_s3a_lvl,
[MDM9607_VDDCX_AO] = &cx_s3a_lvl_ao,
[MDM9607_VDDCX_VFL] = &cx_s3a_vfl,
[MDM9607_VDDMX] = &mx_l12a_lvl,
[MDM9607_VDDMX_AO] = &mx_l12a_lvl_ao,
[MDM9607_VDDMX_VFL] = &mx_l12a_vfl,
};
static const struct rpmpd_desc mdm9607_desc = {
.rpmpds = mdm9607_rpmpds,
.num_pds = ARRAY_SIZE(mdm9607_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO,
};
static struct rpmpd *msm8226_rpmpds[] = {
[MSM8226_VDDCX] = &cx_s1a_corner,
[MSM8226_VDDCX_AO] = &cx_s1a_corner_ao,
[MSM8226_VDDCX_VFC] = &cx_s1a_vfc,
};
static const struct rpmpd_desc msm8226_desc = {
.rpmpds = msm8226_rpmpds,
.num_pds = ARRAY_SIZE(msm8226_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8939_rpmpds[] = {
[MSM8939_VDDMDCX] = &md_s1a_corner,
[MSM8939_VDDMDCX_AO] = &md_s1a_corner_ao,
[MSM8939_VDDMDCX_VFC] = &md_s1a_vfc,
[MSM8939_VDDCX] = &cx_s2a_corner,
[MSM8939_VDDCX_AO] = &cx_s2a_corner_ao,
[MSM8939_VDDCX_VFC] = &cx_s2a_vfc,
[MSM8939_VDDMX] = &mx_l3a_corner,
[MSM8939_VDDMX_AO] = &mx_l3a_corner_ao,
};
static const struct rpmpd_desc msm8939_desc = {
.rpmpds = msm8939_rpmpds,
.num_pds = ARRAY_SIZE(msm8939_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8916_rpmpds[] = {
[MSM8916_VDDCX] = &cx_s1a_corner,
[MSM8916_VDDCX_AO] = &cx_s1a_corner_ao,
[MSM8916_VDDCX_VFC] = &cx_s1a_vfc,
[MSM8916_VDDMX] = &mx_l3a_corner,
[MSM8916_VDDMX_AO] = &mx_l3a_corner_ao,
};
static const struct rpmpd_desc msm8916_desc = {
.rpmpds = msm8916_rpmpds,
.num_pds = ARRAY_SIZE(msm8916_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8917_rpmpds[] = {
[MSM8917_VDDCX] = &cx_s2a_lvl,
[MSM8917_VDDCX_AO] = &cx_s2a_lvl_ao,
[MSM8917_VDDCX_VFL] = &cx_s2a_vfl,
[MSM8917_VDDMX] = &mx_l3a_lvl,
[MSM8917_VDDMX_AO] = &mx_l3a_lvl_ao,
};
static const struct rpmpd_desc msm8917_desc = {
.rpmpds = msm8917_rpmpds,
.num_pds = ARRAY_SIZE(msm8917_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO,
};
static struct rpmpd *msm8953_rpmpds[] = {
[MSM8953_VDDMD] = &md_s1a_lvl,
[MSM8953_VDDMD_AO] = &md_s1a_lvl_ao,
[MSM8953_VDDCX] = &cx_s2a_lvl,
[MSM8953_VDDCX_AO] = &cx_s2a_lvl_ao,
[MSM8953_VDDCX_VFL] = &cx_s2a_vfl,
[MSM8953_VDDMX] = &mx_s7a_lvl,
[MSM8953_VDDMX_AO] = &mx_s7a_lvl_ao,
};
static const struct rpmpd_desc msm8953_desc = {
.rpmpds = msm8953_rpmpds,
.num_pds = ARRAY_SIZE(msm8953_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO,
};
static struct rpmpd *msm8974_rpmpds[] = {
[MSM8974_VDDCX] = &cx_s2b_corner,
[MSM8974_VDDCX_AO] = &cx_s2b_corner_ao,
[MSM8974_VDDCX_VFC] = &cx_s2b_vfc,
[MSM8974_VDDGFX] = &gfx_s4b_corner,
[MSM8974_VDDGFX_VFC] = &gfx_s4b_vfc,
};
static const struct rpmpd_desc msm8974_desc = {
.rpmpds = msm8974_rpmpds,
.num_pds = ARRAY_SIZE(msm8974_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8974pro_pma8084_rpmpds[] = {
[MSM8974_VDDCX] = &cx_s2a_corner,
[MSM8974_VDDCX_AO] = &cx_s2a_corner_ao,
[MSM8974_VDDCX_VFC] = &cx_s2a_vfc,
[MSM8974_VDDGFX] = &gfx_s7a_corner,
[MSM8974_VDDGFX_VFC] = &gfx_s7a_vfc,
};
static const struct rpmpd_desc msm8974pro_pma8084_desc = {
.rpmpds = msm8974pro_pma8084_rpmpds,
.num_pds = ARRAY_SIZE(msm8974pro_pma8084_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8976_rpmpds[] = {
[MSM8976_VDDCX] = &cx_s2a_lvl,
[MSM8976_VDDCX_AO] = &cx_s2a_lvl_ao,
[MSM8976_VDDCX_VFL] = &cx_rwsc2_vfl,
[MSM8976_VDDMX] = &mx_s6a_lvl,
[MSM8976_VDDMX_AO] = &mx_s6a_lvl_ao,
[MSM8976_VDDMX_VFL] = &mx_rwsm6_vfl,
};
static const struct rpmpd_desc msm8976_desc = {
.rpmpds = msm8976_rpmpds,
.num_pds = ARRAY_SIZE(msm8976_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO_HIGH,
};
static struct rpmpd *msm8994_rpmpds[] = {
[MSM8994_VDDCX] = &cx_s1a_corner,
[MSM8994_VDDCX_AO] = &cx_s1a_corner_ao,
[MSM8994_VDDCX_VFC] = &cx_s1a_vfc,
[MSM8994_VDDMX] = &mx_s2a_corner,
[MSM8994_VDDMX_AO] = &mx_s2a_corner_ao,
/* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */
[MSM8994_VDDGFX] = &gfx_s2b_corner,
[MSM8994_VDDGFX_VFC] = &gfx_s2b_vfc,
};
static const struct rpmpd_desc msm8994_desc = {
.rpmpds = msm8994_rpmpds,
.num_pds = ARRAY_SIZE(msm8994_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8996_rpmpds[] = {
[MSM8996_VDDCX] = &cx_s1a_corner,
[MSM8996_VDDCX_AO] = &cx_s1a_corner_ao,
[MSM8996_VDDCX_VFC] = &cx_s1a_vfc,
[MSM8996_VDDMX] = &mx_s2a_corner,
[MSM8996_VDDMX_AO] = &mx_s2a_corner_ao,
[MSM8996_VDDSSCX] = &ssc_cx_l26a_corner,
[MSM8996_VDDSSCX_VFC] = &ssc_cx_l26a_vfc,
};
static const struct rpmpd_desc msm8996_desc = {
.rpmpds = msm8996_rpmpds,
.num_pds = ARRAY_SIZE(msm8996_rpmpds),
.max_state = MAX_CORNER_RPMPD_STATE,
};
static struct rpmpd *msm8998_rpmpds[] = {
[MSM8998_VDDCX] = &cx_rwcx0_lvl,
[MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao,
[MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl,
[MSM8998_VDDMX] = &mx_rwmx0_lvl,
[MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl,
[MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl,
[MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl,
[MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl,
[MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl,
};
static const struct rpmpd_desc msm8998_desc = {
.rpmpds = msm8998_rpmpds,
.num_pds = ARRAY_SIZE(msm8998_rpmpds),
.max_state = RPM_SMD_LEVEL_BINNING,
};
static struct rpmpd *qcs404_rpmpds[] = {
[QCS404_VDDMX] = &mx_rwmx0_lvl,
[QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[QCS404_VDDMX_VFL] = &mx_rwmx0_vfl,
[QCS404_LPICX] = &lpi_cx_rwlc0_lvl,
[QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl,
[QCS404_LPIMX] = &lpi_mx_rwlm0_lvl,
[QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl,
};
static const struct rpmpd_desc qcs404_desc = {
.rpmpds = qcs404_rpmpds,
.num_pds = ARRAY_SIZE(qcs404_rpmpds),
.max_state = RPM_SMD_LEVEL_BINNING,
};
static struct rpmpd *qm215_rpmpds[] = {
[QM215_VDDCX] = &cx_s1a_lvl,
[QM215_VDDCX_AO] = &cx_s1a_lvl_ao,
[QM215_VDDCX_VFL] = &cx_s1a_vfl,
[QM215_VDDMX] = &mx_l2a_lvl,
[QM215_VDDMX_AO] = &mx_l2a_lvl_ao,
};
static const struct rpmpd_desc qm215_desc = {
.rpmpds = qm215_rpmpds,
.num_pds = ARRAY_SIZE(qm215_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO,
};
static struct rpmpd *sdm660_rpmpds[] = {
[SDM660_VDDCX] = &cx_rwcx0_lvl,
[SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao,
[SDM660_VDDCX_VFL] = &cx_rwcx0_vfl,
[SDM660_VDDMX] = &mx_rwmx0_lvl,
[SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[SDM660_VDDMX_VFL] = &mx_rwmx0_vfl,
[SDM660_SSCCX] = &ssc_cx_rwlc0_lvl,
[SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl,
[SDM660_SSCMX] = &ssc_mx_rwlm0_lvl,
[SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl,
};
static const struct rpmpd_desc sdm660_desc = {
.rpmpds = sdm660_rpmpds,
.num_pds = ARRAY_SIZE(sdm660_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO,
};
static struct rpmpd *sm6115_rpmpds[] = {
[SM6115_VDDCX] = &cx_rwcx0_lvl,
[SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao,
[SM6115_VDDCX_VFL] = &cx_rwcx0_vfl,
[SM6115_VDDMX] = &mx_rwmx0_lvl,
[SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[SM6115_VDDMX_VFL] = &mx_rwmx0_vfl,
[SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl,
[SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl,
};
static const struct rpmpd_desc sm6115_desc = {
.rpmpds = sm6115_rpmpds,
.num_pds = ARRAY_SIZE(sm6115_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO_NO_CPR,
};
static struct rpmpd *sm6125_rpmpds[] = {
[SM6125_VDDCX] = &cx_rwcx0_lvl,
[SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao,
[SM6125_VDDCX_VFL] = &cx_rwcx0_vfl,
[SM6125_VDDMX] = &mx_rwmx0_lvl,
[SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[SM6125_VDDMX_VFL] = &mx_rwmx0_vfl,
};
static const struct rpmpd_desc sm6125_desc = {
.rpmpds = sm6125_rpmpds,
.num_pds = ARRAY_SIZE(sm6125_rpmpds),
.max_state = RPM_SMD_LEVEL_BINNING,
};
static struct rpmpd *sm6375_rpmpds[] = {
[SM6375_VDDCX] = &cx_rwcx0_lvl,
[SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao,
[SM6375_VDDCX_VFL] = &cx_rwcx0_vfl,
[SM6375_VDDMX] = &mx_rwmx0_lvl,
[SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[SM6375_VDDMX_VFL] = &mx_rwmx0_vfl,
[SM6375_VDDGX] = &gx_rwgx0_lvl,
[SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao,
[SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl,
[SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl,
};
static const struct rpmpd_desc sm6375_desc = {
.rpmpds = sm6375_rpmpds,
.num_pds = ARRAY_SIZE(sm6375_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO_NO_CPR,
};
static struct rpmpd *qcm2290_rpmpds[] = {
[QCM2290_VDDCX] = &cx_rwcx0_lvl,
[QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao,
[QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl,
[QCM2290_VDDMX] = &mx_rwmx0_lvl,
[QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao,
[QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl,
[QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl,
[QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl,
};
static const struct rpmpd_desc qcm2290_desc = {
.rpmpds = qcm2290_rpmpds,
.num_pds = ARRAY_SIZE(qcm2290_rpmpds),
.max_state = RPM_SMD_LEVEL_TURBO_NO_CPR,
};
static const struct of_device_id rpmpd_match_table[] = {
{ .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc },
{ .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc },
{ .compatible = "qcom,msm8909-rpmpd", .data = &msm8916_desc },
{ .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc },
{ .compatible = "qcom,msm8917-rpmpd", .data = &msm8917_desc },
{ .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc },
{ .compatible = "qcom,msm8953-rpmpd", .data = &msm8953_desc },
{ .compatible = "qcom,msm8974-rpmpd", .data = &msm8974_desc },
{ .compatible = "qcom,msm8974pro-pma8084-rpmpd", .data = &msm8974pro_pma8084_desc },
{ .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc },
{ .compatible = "qcom,msm8994-rpmpd", .data = &msm8994_desc },
{ .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc },
{ .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc },
{ .compatible = "qcom,qcm2290-rpmpd", .data = &qcm2290_desc },
{ .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc },
{ .compatible = "qcom,qm215-rpmpd", .data = &qm215_desc },
{ .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc },
{ .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc },
{ .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc },
{ .compatible = "qcom,sm6375-rpmpd", .data = &sm6375_desc },
{ }
};
MODULE_DEVICE_TABLE(of, rpmpd_match_table);
static int rpmpd_send_enable(struct rpmpd *pd, bool enable)
{
struct rpmpd_req req = {
.key = KEY_ENABLE,
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(enable),
};
return qcom_rpm_smd_write(rpmpd_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
pd->res_type, pd->res_id, &req, sizeof(req));
}
static int rpmpd_send_corner(struct rpmpd *pd, int state, unsigned int corner)
{
struct rpmpd_req req = {
.key = pd->key,
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(corner),
};
return qcom_rpm_smd_write(rpmpd_smd_rpm, state, pd->res_type, pd->res_id,
&req, sizeof(req));
};
static void to_active_sleep(struct rpmpd *pd, unsigned int corner,
unsigned int *active, unsigned int *sleep)
{
*active = corner;
if (pd->active_only)
*sleep = 0;
else
*sleep = *active;
}
static int rpmpd_aggregate_corner(struct rpmpd *pd)
{
int ret;
struct rpmpd *peer = pd->peer;
unsigned int active_corner, sleep_corner;
unsigned int this_active_corner = 0, this_sleep_corner = 0;
unsigned int peer_active_corner = 0, peer_sleep_corner = 0;
/* Clamp to the highest corner/level if sync_state isn't done yet */
if (!pd->state_synced)
this_active_corner = this_sleep_corner = pd->max_state - 1;
else
to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner);
if (peer && peer->enabled)
to_active_sleep(peer, peer->corner, &peer_active_corner,
&peer_sleep_corner);
active_corner = max(this_active_corner, peer_active_corner);
ret = rpmpd_send_corner(pd, QCOM_SMD_RPM_ACTIVE_STATE, active_corner);
if (ret)
return ret;
sleep_corner = max(this_sleep_corner, peer_sleep_corner);
return rpmpd_send_corner(pd, QCOM_SMD_RPM_SLEEP_STATE, sleep_corner);
}
static int rpmpd_power_on(struct generic_pm_domain *domain)
{
int ret;
struct rpmpd *pd = domain_to_rpmpd(domain);
guard(mutex)(&rpmpd_lock);
ret = rpmpd_send_enable(pd, true);
if (ret)
return ret;
pd->enabled = true;
if (pd->corner)
ret = rpmpd_aggregate_corner(pd);
return ret;
}
static int rpmpd_power_off(struct generic_pm_domain *domain)
{
int ret;
struct rpmpd *pd = domain_to_rpmpd(domain);
mutex_lock(&rpmpd_lock);
ret = rpmpd_send_enable(pd, false);
if (!ret)
pd->enabled = false;
mutex_unlock(&rpmpd_lock);
return ret;
}
static int rpmpd_set_performance(struct generic_pm_domain *domain,
unsigned int state)
{
struct rpmpd *pd = domain_to_rpmpd(domain);
if (state > pd->max_state)
state = pd->max_state;
guard(mutex)(&rpmpd_lock);
pd->corner = state;
/* Always send updates for vfc and vfl */
if (!pd->enabled && pd->key != cpu_to_le32(KEY_FLOOR_CORNER) &&
pd->key != cpu_to_le32(KEY_FLOOR_LEVEL))
return 0;
return rpmpd_aggregate_corner(pd);
}
static int rpmpd_probe(struct platform_device *pdev)
{
int i;
size_t num;
struct genpd_onecell_data *data;
struct rpmpd **rpmpds;
const struct rpmpd_desc *desc;
rpmpd_smd_rpm = dev_get_drvdata(pdev->dev.parent);
if (!rpmpd_smd_rpm) {
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
return -ENODEV;
}
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
rpmpds = desc->rpmpds;
num = desc->num_pds;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->domains = devm_kcalloc(&pdev->dev, num, sizeof(*data->domains),
GFP_KERNEL);
if (!data->domains)
return -ENOMEM;
data->num_domains = num;
for (i = 0; i < num; i++) {
if (!rpmpds[i]) {
dev_warn(&pdev->dev, "rpmpds[] with empty entry at index=%d\n",
i);
continue;
}
rpmpds[i]->max_state = desc->max_state;
rpmpds[i]->pd.power_off = rpmpd_power_off;
rpmpds[i]->pd.power_on = rpmpd_power_on;
rpmpds[i]->pd.set_performance_state = rpmpd_set_performance;
rpmpds[i]->pd.flags = GENPD_FLAG_ACTIVE_WAKEUP;
pm_genpd_init(&rpmpds[i]->pd, NULL, true);
data->domains[i] = &rpmpds[i]->pd;
}
/* Add subdomains */
for (i = 0; i < num; i++) {
if (!rpmpds[i])
continue;
if (rpmpds[i]->parent)
pm_genpd_add_subdomain(rpmpds[i]->parent, &rpmpds[i]->pd);
}
return of_genpd_add_provider_onecell(pdev->dev.of_node, data);
}
static void rpmpd_sync_state(struct device *dev)
{
const struct rpmpd_desc *desc = of_device_get_match_data(dev);
struct rpmpd **rpmpds = desc->rpmpds;
struct rpmpd *pd;
unsigned int i;
int ret;
mutex_lock(&rpmpd_lock);
for (i = 0; i < desc->num_pds; i++) {
pd = rpmpds[i];
if (!pd)
continue;
pd->state_synced = true;
if (!pd->enabled)
pd->corner = 0;
ret = rpmpd_aggregate_corner(pd);
if (ret)
dev_err(dev, "failed to sync %s: %d\n", pd->pd.name, ret);
}
mutex_unlock(&rpmpd_lock);
}
static struct platform_driver rpmpd_driver = {
.driver = {
.name = "qcom-rpmpd",
.of_match_table = rpmpd_match_table,
.suppress_bind_attrs = true,
.sync_state = rpmpd_sync_state,
},
.probe = rpmpd_probe,
};
static int __init rpmpd_init(void)
{
return platform_driver_register(&rpmpd_driver);
}
core_initcall(rpmpd_init);
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. RPM Power Domain Driver");
MODULE_LICENSE("GPL v2");
|
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2020 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
#ifndef GAUDI_MASKS_H_
#define GAUDI_MASKS_H_
#include "asic_reg/gaudi_regs.h"
/* Useful masks for bits in various registers */
#define PCI_DMA_QMAN_ENABLE (\
(FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
#define QMAN_EXTERNAL_MAKE_TRUSTED (\
(FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
#define QMAN_INTERNAL_MAKE_TRUSTED (\
(FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
#define HBM_DMA_QMAN_ENABLE (\
(FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
(FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
#define QMAN_MME_ENABLE (\
(FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
(FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
(FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
#define QMAN_TPC_ENABLE (\
(FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
(FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
(FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
#define NIC_QMAN_ENABLE (\
(FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF)))
#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\
(FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
(FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
(FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
(FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\
(FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
(FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
(FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
#define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
#define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
#define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
/* RESET registers configuration */
#define CFG_RST_L_PSOC_MASK BIT_MASK(0)
#define CFG_RST_L_PCIE_MASK BIT_MASK(1)
#define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2)
#define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3)
#define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4)
#define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5)
#define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6)
#define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7)
#define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8)
#define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9)
#define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10)
#define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11)
#define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12)
#define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13)
#define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14)
#define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15)
#define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16)
#define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17)
#define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18)
#define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19)
#define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20)
#define CFG_RST_L_IF_1_MASK BIT_MASK(21)
#define CFG_RST_L_IF_0_MASK BIT_MASK(22)
#define CFG_RST_L_IF_2_MASK BIT_MASK(23)
#define CFG_RST_L_IF_3_MASK BIT_MASK(24)
#define CFG_RST_L_IF_MASK GENMASK(24, 21)
#define CFG_RST_L_TPC_0_MASK BIT_MASK(25)
#define CFG_RST_L_TPC_1_MASK BIT_MASK(26)
#define CFG_RST_L_TPC_2_MASK BIT_MASK(27)
#define CFG_RST_L_TPC_3_MASK BIT_MASK(28)
#define CFG_RST_L_TPC_4_MASK BIT_MASK(29)
#define CFG_RST_L_TPC_5_MASK BIT_MASK(30)
#define CFG_RST_L_TPC_6_MASK BIT_MASK(31)
#define CFG_RST_L_TPC_MASK GENMASK(31, 25)
#define CFG_RST_H_TPC_7_MASK BIT_MASK(0)
#define CFG_RST_H_MME_0_MASK BIT_MASK(1)
#define CFG_RST_H_MME_1_MASK BIT_MASK(2)
#define CFG_RST_H_MME_2_MASK BIT_MASK(3)
#define CFG_RST_H_MME_3_MASK BIT_MASK(4)
#define CFG_RST_H_MME_MASK GENMASK(4, 1)
#define CFG_RST_H_HBM_0_MASK BIT_MASK(5)
#define CFG_RST_H_HBM_1_MASK BIT_MASK(6)
#define CFG_RST_H_HBM_2_MASK BIT_MASK(7)
#define CFG_RST_H_HBM_3_MASK BIT_MASK(8)
#define CFG_RST_H_HBM_MASK GENMASK(8, 5)
#define CFG_RST_H_NIC_0_MASK BIT_MASK(9)
#define CFG_RST_H_NIC_1_MASK BIT_MASK(10)
#define CFG_RST_H_NIC_2_MASK BIT_MASK(11)
#define CFG_RST_H_NIC_3_MASK BIT_MASK(12)
#define CFG_RST_H_NIC_4_MASK BIT_MASK(13)
#define CFG_RST_H_NIC_MASK GENMASK(13, 9)
#define CFG_RST_H_SM_0_MASK BIT_MASK(14)
#define CFG_RST_H_SM_1_MASK BIT_MASK(15)
#define CFG_RST_H_SM_2_MASK BIT_MASK(16)
#define CFG_RST_H_SM_3_MASK BIT_MASK(17)
#define CFG_RST_H_SM_MASK GENMASK(17, 14)
#define CFG_RST_H_DMA_0_MASK BIT_MASK(18)
#define CFG_RST_H_DMA_1_MASK BIT_MASK(19)
#define CFG_RST_H_DMA_MASK GENMASK(19, 18)
#define CFG_RST_H_CPU_MASK BIT_MASK(20)
#define CFG_RST_H_MMU_MASK BIT_MASK(21)
#define UNIT_RST_L_PSOC_SHIFT 0
#define UNIT_RST_L_PCIE_SHIFT 1
#define UNIT_RST_L_PCIE_IF_SHIFT 2
#define UNIT_RST_L_HBM_S_PLL_SHIFT 3
#define UNIT_RST_L_TPC_S_PLL_SHIFT 4
#define UNIT_RST_L_MME_S_PLL_SHIFT 5
#define UNIT_RST_L_CPU_PLL_SHIFT 6
#define UNIT_RST_L_PCIE_PLL_SHIFT 7
#define UNIT_RST_L_NIC_S_PLL_SHIFT 8
#define UNIT_RST_L_HBM_N_PLL_SHIFT 9
#define UNIT_RST_L_TPC_N_PLL_SHIFT 10
#define UNIT_RST_L_MME_N_PLL_SHIFT 11
#define UNIT_RST_L_NIC_N_PLL_SHIFT 12
#define UNIT_RST_L_DMA_W_PLL_SHIFT 13
#define UNIT_RST_L_SIF_W_PLL_SHIFT 14
#define UNIT_RST_L_MESH_W_PLL_SHIFT 15
#define UNIT_RST_L_SRAM_W_PLL_SHIFT 16
#define UNIT_RST_L_DMA_E_PLL_SHIFT 17
#define UNIT_RST_L_SIF_E_PLL_SHIFT 18
#define UNIT_RST_L_MESH_E_PLL_SHIFT 19
#define UNIT_RST_L_SRAM_E_PLL_SHIFT 20
#define UNIT_RST_L_TPC_0_SHIFT 21
#define UNIT_RST_L_TPC_1_SHIFT 22
#define UNIT_RST_L_TPC_2_SHIFT 23
#define UNIT_RST_L_TPC_3_SHIFT 24
#define UNIT_RST_L_TPC_4_SHIFT 25
#define UNIT_RST_L_TPC_5_SHIFT 26
#define UNIT_RST_L_TPC_6_SHIFT 27
#define UNIT_RST_L_TPC_7_SHIFT 28
#define UNIT_RST_L_MME_0_SHIFT 29
#define UNIT_RST_L_MME_1_SHIFT 30
#define UNIT_RST_L_MME_2_SHIFT 31
#define UNIT_RST_H_MME_3_SHIFT 0
#define UNIT_RST_H_HBM_0_SHIFT 1
#define UNIT_RST_H_HBM_1_SHIFT 2
#define UNIT_RST_H_HBM_2_SHIFT 3
#define UNIT_RST_H_HBM_3_SHIFT 4
#define UNIT_RST_H_NIC_0_SHIFT 5
#define UNIT_RST_H_NIC_1_SHIFT 6
#define UNIT_RST_H_NIC_2_SHIFT 7
#define UNIT_RST_H_NIC_3_SHIFT 8
#define UNIT_RST_H_NIC_4_SHIFT 9
#define UNIT_RST_H_SM_0_SHIFT 10
#define UNIT_RST_H_SM_1_SHIFT 11
#define UNIT_RST_H_SM_2_SHIFT 12
#define UNIT_RST_H_SM_3_SHIFT 13
#define UNIT_RST_H_IF_0_SHIFT 14
#define UNIT_RST_H_IF_1_SHIFT 15
#define UNIT_RST_H_IF_2_SHIFT 16
#define UNIT_RST_H_IF_3_SHIFT 17
#define UNIT_RST_H_DMA_0_SHIFT 18
#define UNIT_RST_H_DMA_1_SHIFT 19
#define UNIT_RST_H_CPU_SHIFT 20
#define UNIT_RST_H_MMU_SHIFT 21
#define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \
(1 << UNIT_RST_H_HBM_1_SHIFT) | \
(1 << UNIT_RST_H_HBM_2_SHIFT) | \
(1 << UNIT_RST_H_HBM_3_SHIFT))
#define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \
(1 << UNIT_RST_H_NIC_1_SHIFT) | \
(1 << UNIT_RST_H_NIC_2_SHIFT) | \
(1 << UNIT_RST_H_NIC_3_SHIFT) | \
(1 << UNIT_RST_H_NIC_4_SHIFT))
#define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \
(1 << UNIT_RST_H_SM_1_SHIFT) | \
(1 << UNIT_RST_H_SM_2_SHIFT) | \
(1 << UNIT_RST_H_SM_3_SHIFT))
#define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \
(1 << UNIT_RST_H_MME_1_SHIFT) | \
(1 << UNIT_RST_H_MME_2_SHIFT))
#define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT)
#define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \
(1 << UNIT_RST_L_IF_1_SHIFT) | \
(1 << UNIT_RST_L_IF_2_SHIFT) | \
(1 << UNIT_RST_L_IF_3_SHIFT))
#define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \
(1 << UNIT_RST_L_TPC_1_SHIFT) | \
(1 << UNIT_RST_L_TPC_2_SHIFT) | \
(1 << UNIT_RST_L_TPC_3_SHIFT) | \
(1 << UNIT_RST_L_TPC_4_SHIFT) | \
(1 << UNIT_RST_L_TPC_5_SHIFT) | \
(1 << UNIT_RST_L_TPC_6_SHIFT) | \
(1 << UNIT_RST_L_TPC_7_SHIFT))
/* CPU_CA53_CFG_ARM_RST_CONTROL */
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30
#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8
#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100
#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12
#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000
#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16
#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000
#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20
#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000
#define CPU_RESET_ASSERT (\
1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
#define CPU_RESET_CORE0_DEASSERT (\
1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\
1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\
1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\
1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
/* QM_IDLE_MASK is valid for all engines QM idle check */
#define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
DMA0_QM_GLBL_STS0_CP_IDLE_MASK)
/* CGM_IDLE_MASK is valid for all engines CGM idle check */
#define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK
#define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \
(1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \
(1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \
(1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \
(1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \
(1 << TPC0_CFG_STATUS_QM_RDY_SHIFT))
#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000
#define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \
MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \
MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK)
#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \
((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \
(((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK))
#define IS_DMA_IDLE(dma_core_sts0) \
!(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK)
#define IS_TPC_IDLE(tpc_cfg_sts) \
(((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK)
#define IS_MME_IDLE(mme_arch_sts) \
(((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
enum axi_id {
AXI_ID_MME,
AXI_ID_TPC,
AXI_ID_DMA,
AXI_ID_NIC, /* Local NIC */
AXI_ID_PCI,
AXI_ID_CPU,
AXI_ID_PSOC,
AXI_ID_MMU,
AXI_ID_NIC_FT /* Feed-Through NIC */
};
/* RAZWI initiator ID is built from the location in the chip and the AXI ID */
#define RAZWI_INITIATOR_AXI_ID_SHIFT 20
#define RAZWI_INITIATOR_AXI_ID_MASK 0xF
#define RAZWI_INITIATOR_X_SHIFT 24
#define RAZWI_INITIATOR_X_MASK 0xF
#define RAZWI_INITIATOR_Y_SHIFT 28
#define RAZWI_INITIATOR_Y_MASK 0x7
#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \
(((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \
RAZWI_INITIATOR_AXI_ID_SHIFT)
#define RAZWI_INITIATOR_ID_X_Y(x, y) \
((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
(((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1)
#define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1)
#define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1)
#define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1)
#define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1)
#define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1)
#define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1)
#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \
RAZWI_INITIATOR_ID_X_Y(8, 1)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4)
#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4)
#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6)
#define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6)
#define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6)
#define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6)
#define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6)
#define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6)
#define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6)
#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6)
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1
#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2
#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00
/* STLB_CACHE_INV */
#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8
#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
#define MME_ACC_ACC_STALL_R_SHIFT 0
#define MME_SBAB_SB_STALL_R_SHIFT 0
#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700
#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000
#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0
#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0
/* DMA_IF_HBM_CRED_EN */
#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0
#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1
#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1
#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2
#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0
#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0
#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0
#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0
#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0
#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0
#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0
#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0
/* MMU_UP_PAGE_ERROR_CAPTURE */
#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
/* MMU_UP_ACCESS_ERROR_CAPTURE */
#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
#define QM_ARB_ERR_MSG_EN_MASK (\
QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\
QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\
QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)
#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT 0
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK 0x1
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_SHIFT 1
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK 0x1FE
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT 0
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK 0xFF
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_SHIFT 8
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK 0xFF00
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_SHIFT 16
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK 0x10000
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_SHIFT 17
#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK 0xFFFE0000
#define TPC0_QM_CP_STS_0_FENCE_ID_SHIFT 20
#define TPC0_QM_CP_STS_0_FENCE_ID_MASK 0x300000
#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_SHIFT 22
#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK 0x400000
#endif /* GAUDI_MASKS_H_ */
|
// SPDX-License-Identifier: GPL-2.0+
/*
* XRS700x tag format handling
* Copyright (c) 2008-2009 Marvell Semiconductor
* Copyright (c) 2020 NovaTech LLC
*/
#include <linux/bitops.h>
#include "tag.h"
#define XRS700X_NAME "xrs700x"
static struct sk_buff *xrs700x_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct dsa_port *partner, *dp = dsa_user_to_port(dev);
u8 *trailer;
trailer = skb_put(skb, 1);
trailer[0] = BIT(dp->index);
if (dp->hsr_dev)
dsa_hsr_foreach_port(partner, dp->ds, dp->hsr_dev)
if (partner != dp)
trailer[0] |= BIT(partner->index);
return skb;
}
static struct sk_buff *xrs700x_rcv(struct sk_buff *skb, struct net_device *dev)
{
int source_port;
u8 *trailer;
trailer = skb_tail_pointer(skb) - 1;
source_port = ffs((int)trailer[0]) - 1;
if (source_port < 0)
return NULL;
skb->dev = dsa_conduit_find_user(dev, 0, source_port);
if (!skb->dev)
return NULL;
if (pskb_trim_rcsum(skb, skb->len - 1))
return NULL;
/* Frame is forwarded by hardware, don't forward in software. */
dsa_default_offload_fwd_mark(skb);
return skb;
}
static const struct dsa_device_ops xrs700x_netdev_ops = {
.name = XRS700X_NAME,
.proto = DSA_TAG_PROTO_XRS700X,
.xmit = xrs700x_xmit,
.rcv = xrs700x_rcv,
.needed_tailroom = 1,
};
MODULE_DESCRIPTION("DSA tag driver for XRS700x switches");
MODULE_LICENSE("GPL");
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_XRS700X, XRS700X_NAME);
module_dsa_tag_driver(xrs700x_netdev_ops);
|
/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _gc_9_0_SH_MASK_HEADER
#define _gc_9_0_SH_MASK_HEADER
//GCEA_EDC_CNT
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
// addressBlock: gc_cppdec2
//CPF_EDC_TAG_CNT
#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
//CPF_EDC_ROQ_CNT
#define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT 0x0
#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT 0x2
#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK 0x00000003L
#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK 0x0000000CL
//CPG_EDC_TAG_CNT
#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
//CPG_EDC_DMA_CNT
#define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT 0x0
#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x2
#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x4
#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK 0x00000003L
#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x0000000CL
#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x00000030L
//CPC_EDC_SCRATCH_CNT
#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0
#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2
#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L
#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL
//CPC_EDC_UCODE_CNT
#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0
#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2
#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L
#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL
//DC_EDC_STATE_CNT
#define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT 0x0
#define DC_EDC_STATE_CNT__COUNT_ME1_MASK 0x00000003L
//DC_EDC_CSINVOC_CNT
#define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT 0x0
#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK 0x00000003L
//DC_EDC_RESTORE_CNT
#define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT 0x0
#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK 0x00000003L
// addressBlock: gc_grbmdec
//GRBM_CNTL
#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
//GRBM_SKEW_CNTL
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
//GRBM_STATUS2
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
//GRBM_PWR_CNTL
#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
//GRBM_STATUS
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
//GRBM_STATUS_SE0
#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
//GRBM_STATUS_SE1
#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
//GRBM_SOFT_RESET
#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
//GRBM_CGTT_CLK_CNTL
#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
//GRBM_GFX_CLKEN_CNTL
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
//GRBM_WAIT_IDLE_CLOCKS
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
//GRBM_STATUS_SE2
#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
//GRBM_STATUS_SE3
#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
//GRBM_READ_ERROR
#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
//GRBM_READ_ERROR2
#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
//GRBM_INT_CNTL
#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
//GRBM_TRAP_OP
#define GRBM_TRAP_OP__RW__SHIFT 0x0
#define GRBM_TRAP_OP__RW_MASK 0x00000001L
//GRBM_TRAP_ADDR
#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
//GRBM_TRAP_ADDR_MSK
#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
//GRBM_TRAP_WD
#define GRBM_TRAP_WD__DATA__SHIFT 0x0
#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
//GRBM_TRAP_WD_MSK
#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
//GRBM_DSM_BYPASS
#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
//GRBM_WRITE_ERROR
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
//GRBM_IOV_ERROR
#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
//GRBM_CHIP_REVISION
#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
//GRBM_GFX_CNTL
#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
//GRBM_RSMU_CFG
#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11
#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L
//GRBM_IH_CREDIT
#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
//GRBM_PWR_CNTL2
#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
//GRBM_UTCL2_INVAL_RANGE_START
#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
//GRBM_UTCL2_INVAL_RANGE_END
#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
//GRBM_RSMU_READ_ERROR
#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
//GRBM_CHICKEN_BITS
#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
//GRBM_NOWHERE
#define GRBM_NOWHERE__DATA__SHIFT 0x0
#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG1
#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG2
#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG3
#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG4
#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG5
#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG6
#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
//GRBM_SCRATCH_REG7
#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
// addressBlock: gc_cpdec
//CP_CPC_STATUS
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
//CP_CPC_BUSY_STAT
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
//CP_CPC_STALLED_STAT1
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
//CP_CPF_STATUS
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
//CP_CPF_BUSY_STAT
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
//CP_CPF_STALLED_STAT1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
//CP_CPC_GRBM_FREE_COUNT
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
//CP_MEC_CNTL
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
//CP_MEC_ME1_HEADER_DUMP
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_MEC_ME2_HEADER_DUMP
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_CPC_SCRATCH_INDEX
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
//CP_CPC_SCRATCH_DATA
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
//CP_CPF_GRBM_FREE_COUNT
#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
//CP_CPC_HALT_HYST_COUNT
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
//CP_PRT_LOD_STATS_CNTL0
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL
//CP_PRT_LOD_STATS_CNTL1
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL
//CP_PRT_LOD_STATS_CNTL2
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL
//CP_PRT_LOD_STATS_CNTL3
#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2
#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12
#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13
#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17
#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c
#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL
#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L
#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L
#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L
#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L
#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L
//CP_CE_COMPARE_COUNT
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
//CP_CE_DE_COUNT
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_DE_CE_COUNT
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_DE_LAST_INVAL_COUNT
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
//CP_DE_DE_COUNT
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_STALLED_STAT3
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
//CP_STALLED_STAT1
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
//CP_STALLED_STAT2
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
//CP_BUSY_STAT
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
//CP_STAT
#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
#define CP_STAT__DC_BUSY__SHIFT 0xd
#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
#define CP_STAT__PFP_BUSY__SHIFT 0xf
#define CP_STAT__MEQ_BUSY__SHIFT 0x10
#define CP_STAT__ME_BUSY__SHIFT 0x11
#define CP_STAT__QUERY_BUSY__SHIFT 0x12
#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
#define CP_STAT__DMA_BUSY__SHIFT 0x16
#define CP_STAT__RCIU_BUSY__SHIFT 0x17
#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
#define CP_STAT__CE_BUSY__SHIFT 0x1a
#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
#define CP_STAT__CP_BUSY__SHIFT 0x1f
#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
#define CP_STAT__DC_BUSY_MASK 0x00002000L
#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
#define CP_STAT__PFP_BUSY_MASK 0x00008000L
#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
#define CP_STAT__ME_BUSY_MASK 0x00020000L
#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
#define CP_STAT__DMA_BUSY_MASK 0x00400000L
#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
#define CP_STAT__CE_BUSY_MASK 0x04000000L
#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
#define CP_STAT__CP_BUSY_MASK 0x80000000L
//CP_ME_HEADER_DUMP
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_PFP_HEADER_DUMP
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_GRBM_FREE_COUNT
#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
//CP_CE_HEADER_DUMP
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
//CP_PFP_INSTR_PNTR
#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_ME_INSTR_PNTR
#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_CE_INSTR_PNTR
#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_MEC1_INSTR_PNTR
#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_MEC2_INSTR_PNTR
#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
//CP_CSF_STAT
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
//CP_ME_CNTL
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
//CP_CNTX_STAT
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
//CP_ME_PREEMPTION
#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
//CP_ROQ_THRESHOLDS
#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
//CP_MEQ_STQ_THRESHOLD
#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
//CP_RB2_RPTR
#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB1_RPTR
#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB0_RPTR
#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB_RPTR
#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
//CP_RB_WPTR_DELAY
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
//CP_RB_WPTR_POLL_CNTL
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
//CP_ROQ1_THRESHOLDS
#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
//CP_ROQ2_THRESHOLDS
#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
//CP_STQ_THRESHOLDS
#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
//CP_QUEUE_THRESHOLDS
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
//CP_MEQ_THRESHOLDS
#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
//CP_ROQ_AVAIL
#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
//CP_STQ_AVAIL
#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
//CP_ROQ2_AVAIL
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
//CP_MEQ_AVAIL
#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
//CP_CMD_INDEX
#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
//CP_CMD_DATA
#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
//CP_ROQ_RB_STAT
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
//CP_ROQ_IB1_STAT
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
//CP_ROQ_IB2_STAT
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
//CP_STQ_STAT
#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
//CP_STQ_WR_STAT
#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
//CP_MEQ_STAT
#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
//CP_CEQ1_AVAIL
#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
//CP_CEQ2_AVAIL
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
//CP_CE_ROQ_RB_STAT
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
//CP_CE_ROQ_IB1_STAT
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
//CP_CE_ROQ_IB2_STAT
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
//CP_INT_STAT_DEBUG
#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L
#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
// addressBlock: gc_padec
//VGT_VTX_VECT_EJECT_REG
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
//VGT_DMA_DATA_FIFO_DEPTH
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
//VGT_DMA_REQ_FIFO_DEPTH
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
//VGT_DRAW_INIT_FIFO_DEPTH
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
//VGT_LAST_COPY_STATE
#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
//VGT_CACHE_INVALIDATION
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
//VGT_RESET_DEBUG
#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L
#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L
#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L
//VGT_STRMOUT_DELAY
#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
//VGT_FIFO_DEPTHS
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
//VGT_GS_VERTEX_REUSE
#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
//VGT_MC_LAT_CNTL
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
//IA_CNTL_STATUS
#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
//VGT_CNTL_STATUS
#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
//WD_CNTL_STATUS
#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
//CC_GC_PRIM_CONFIG
#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
//GC_USER_PRIM_CONFIG
#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
//WD_QOS
#define WD_QOS__DRAW_STALL__SHIFT 0x0
#define WD_QOS__DRAW_STALL_MASK 0x00000001L
//WD_UTCL1_CNTL
#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
//WD_UTCL1_STATUS
#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//IA_UTCL1_CNTL
#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
//IA_UTCL1_STATUS
#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//VGT_SYS_CONFIG
#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
//VGT_VS_MAX_WAVE_ID
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
//VGT_GS_MAX_WAVE_ID
#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
//GFX_PIPE_CONTROL
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
//CC_GC_SHADER_ARRAY_CONFIG
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
//GC_USER_SHADER_ARRAY_CONFIG
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
//VGT_DMA_PRIMITIVE_TYPE
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
//VGT_DMA_CONTROL
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
//VGT_DMA_LS_HS_CONFIG
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
//WD_BUF_RESOURCE_1
#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
//WD_BUF_RESOURCE_2
#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
//PA_CL_CNTL_STATUS
#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
//PA_CL_ENHANCE
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L
#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
//PA_CL_RESET_DEBUG
#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L
//PA_SU_CNTL_STATUS
#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
//PA_SC_FIFO_DEPTH_CNTL
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
//PA_SC_TRAP_SCREEN_HV_LOCK
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
//PA_SC_FORCE_EOV_MAX_CNTS
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
//PA_SC_BINNER_EVENT_CNTL_0
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_1
#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_2
#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_3
#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
//PA_SC_BINNER_TIMEOUT_COUNTER
#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
//PA_SC_BINNER_PERF_CNTL_0
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
//PA_SC_BINNER_PERF_CNTL_1
#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
//PA_SC_BINNER_PERF_CNTL_2
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
//PA_SC_BINNER_PERF_CNTL_3
#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
//PA_SC_FIFO_SIZE
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
//PA_SC_IF_FIFO_SIZE
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
//PA_SC_PKR_WAVE_TABLE_CNTL
#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
//PA_UTCL1_CNTL1
#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//PA_UTCL1_CNTL2
#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
//PA_SIDEBAND_REQUEST_DELAYS
#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
//PA_SC_ENHANCE
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
//PA_SC_ENHANCE_1
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc
#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L
#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L
//PA_SC_DSM_CNTL
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
//PA_SC_TILE_STEERING_CREST_OVERRIDE
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
// addressBlock: gc_sqdec
//SQ_CONFIG
#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0
#define SQ_CONFIG__UNUSED__SHIFT 0x1
#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L
#define SQ_CONFIG__UNUSED_MASK 0x0000007EL
#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L
#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L
#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L
#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
//SQC_CONFIG
#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
//LDS_CONFIG
#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
//SQ_RANDOM_WAVE_PRI
#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
//SQ_REG_CREDITS
#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
//SQ_FIFO_SIZES
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
//SQ_DSM_CNTL
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
//SQ_DSM_CNTL2
#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
//SQ_RUNTIME_CONFIG
#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
//SH_MEM_BASES
#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
//SH_MEM_CONFIG
#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
//CC_GC_SHADER_RATE_CONFIG
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
//GC_USER_SHADER_RATE_CONFIG
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
//SQ_INTERRUPT_AUTO_MASK
#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
//SQ_INTERRUPT_MSG_CTRL
#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
//SQ_UTCL1_CNTL1
#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//SQ_UTCL1_CNTL2
#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
//SQ_UTCL1_STATUS
#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
//SQ_SHADER_TBA_LO
#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
//SQ_SHADER_TBA_HI
#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
//SQ_SHADER_TMA_LO
#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
//SQ_SHADER_TMA_HI
#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
//SQC_DSM_CNTL
#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
//SQC_DSM_CNTLA
#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
//SQC_DSM_CNTLB
#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
//SQC_DSM_CNTL2
#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
//SQC_DSM_CNTL2A
#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
//SQC_DSM_CNTL2B
#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
//SQC_EDC_FUE_CNTL
#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
//SQC_EDC_CNT2
#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12
#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14
#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16
#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a
#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c
#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L
#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L
#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L
//SQC_EDC_CNT3
#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12
#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14
#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16
#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L
#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
//SQ_REG_TIMESTAMP
#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
//SQ_CMD_TIMESTAMP
#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
//SQ_IND_INDEX
#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
#define SQ_IND_INDEX__INDEX__SHIFT 0x10
#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
//SQ_IND_DATA
#define SQ_IND_DATA__DATA__SHIFT 0x0
#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
//SQ_CMD
#define SQ_CMD__CMD__SHIFT 0x0
#define SQ_CMD__MODE__SHIFT 0x4
#define SQ_CMD__CHECK_VMID__SHIFT 0x7
#define SQ_CMD__DATA__SHIFT 0x8
#define SQ_CMD__WAVE_ID__SHIFT 0x10
#define SQ_CMD__SIMD_ID__SHIFT 0x14
#define SQ_CMD__QUEUE_ID__SHIFT 0x18
#define SQ_CMD__VM_ID__SHIFT 0x1c
#define SQ_CMD__CMD_MASK 0x00000007L
#define SQ_CMD__MODE_MASK 0x00000070L
#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
#define SQ_CMD__DATA_MASK 0x00000F00L
#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
#define SQ_CMD__SIMD_ID_MASK 0x00300000L
#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
#define SQ_CMD__VM_ID_MASK 0xF0000000L
//SQ_TIME_HI
#define SQ_TIME_HI__TIME__SHIFT 0x0
#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
//SQ_TIME_LO
#define SQ_TIME_LO__TIME__SHIFT 0x0
#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
//SQ_DS_0
#define SQ_DS_0__OFFSET0__SHIFT 0x0
#define SQ_DS_0__OFFSET1__SHIFT 0x8
#define SQ_DS_0__GDS__SHIFT 0x10
#define SQ_DS_0__OP__SHIFT 0x11
#define SQ_DS_0__ENCODING__SHIFT 0x1a
#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
#define SQ_DS_0__GDS_MASK 0x00010000L
#define SQ_DS_0__OP_MASK 0x01FE0000L
#define SQ_DS_0__ENCODING_MASK 0xFC000000L
//SQ_DS_1
#define SQ_DS_1__ADDR__SHIFT 0x0
#define SQ_DS_1__DATA0__SHIFT 0x8
#define SQ_DS_1__DATA1__SHIFT 0x10
#define SQ_DS_1__VDST__SHIFT 0x18
#define SQ_DS_1__ADDR_MASK 0x000000FFL
#define SQ_DS_1__DATA0_MASK 0x0000FF00L
#define SQ_DS_1__DATA1_MASK 0x00FF0000L
#define SQ_DS_1__VDST_MASK 0xFF000000L
//SQ_EXP_0
#define SQ_EXP_0__EN__SHIFT 0x0
#define SQ_EXP_0__TGT__SHIFT 0x4
#define SQ_EXP_0__COMPR__SHIFT 0xa
#define SQ_EXP_0__DONE__SHIFT 0xb
#define SQ_EXP_0__VM__SHIFT 0xc
#define SQ_EXP_0__ENCODING__SHIFT 0x1a
#define SQ_EXP_0__EN_MASK 0x0000000FL
#define SQ_EXP_0__TGT_MASK 0x000003F0L
#define SQ_EXP_0__COMPR_MASK 0x00000400L
#define SQ_EXP_0__DONE_MASK 0x00000800L
#define SQ_EXP_0__VM_MASK 0x00001000L
#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
//SQ_EXP_1
#define SQ_EXP_1__VSRC0__SHIFT 0x0
#define SQ_EXP_1__VSRC1__SHIFT 0x8
#define SQ_EXP_1__VSRC2__SHIFT 0x10
#define SQ_EXP_1__VSRC3__SHIFT 0x18
#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
//SQ_FLAT_0
#define SQ_FLAT_0__OFFSET__SHIFT 0x0
#define SQ_FLAT_0__LDS__SHIFT 0xd
#define SQ_FLAT_0__SEG__SHIFT 0xe
#define SQ_FLAT_0__GLC__SHIFT 0x10
#define SQ_FLAT_0__SLC__SHIFT 0x11
#define SQ_FLAT_0__OP__SHIFT 0x12
#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
#define SQ_FLAT_0__LDS_MASK 0x00002000L
#define SQ_FLAT_0__SEG_MASK 0x0000C000L
#define SQ_FLAT_0__GLC_MASK 0x00010000L
#define SQ_FLAT_0__SLC_MASK 0x00020000L
#define SQ_FLAT_0__OP_MASK 0x01FC0000L
#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
//SQ_FLAT_1
#define SQ_FLAT_1__ADDR__SHIFT 0x0
#define SQ_FLAT_1__DATA__SHIFT 0x8
#define SQ_FLAT_1__SADDR__SHIFT 0x10
#define SQ_FLAT_1__NV__SHIFT 0x17
#define SQ_FLAT_1__VDST__SHIFT 0x18
#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
#define SQ_FLAT_1__NV_MASK 0x00800000L
#define SQ_FLAT_1__VDST_MASK 0xFF000000L
//SQ_GLBL_0
#define SQ_GLBL_0__OFFSET__SHIFT 0x0
#define SQ_GLBL_0__LDS__SHIFT 0xd
#define SQ_GLBL_0__SEG__SHIFT 0xe
#define SQ_GLBL_0__GLC__SHIFT 0x10
#define SQ_GLBL_0__SLC__SHIFT 0x11
#define SQ_GLBL_0__OP__SHIFT 0x12
#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
#define SQ_GLBL_0__LDS_MASK 0x00002000L
#define SQ_GLBL_0__SEG_MASK 0x0000C000L
#define SQ_GLBL_0__GLC_MASK 0x00010000L
#define SQ_GLBL_0__SLC_MASK 0x00020000L
#define SQ_GLBL_0__OP_MASK 0x01FC0000L
#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
//SQ_GLBL_1
#define SQ_GLBL_1__ADDR__SHIFT 0x0
#define SQ_GLBL_1__DATA__SHIFT 0x8
#define SQ_GLBL_1__SADDR__SHIFT 0x10
#define SQ_GLBL_1__NV__SHIFT 0x17
#define SQ_GLBL_1__VDST__SHIFT 0x18
#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
#define SQ_GLBL_1__NV_MASK 0x00800000L
#define SQ_GLBL_1__VDST_MASK 0xFF000000L
//SQ_INST
#define SQ_INST__ENCODING__SHIFT 0x0
#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
//SQ_MIMG_0
#define SQ_MIMG_0__OPM__SHIFT 0x0
#define SQ_MIMG_0__DMASK__SHIFT 0x8
#define SQ_MIMG_0__UNORM__SHIFT 0xc
#define SQ_MIMG_0__GLC__SHIFT 0xd
#define SQ_MIMG_0__DA__SHIFT 0xe
#define SQ_MIMG_0__A16__SHIFT 0xf
#define SQ_MIMG_0__TFE__SHIFT 0x10
#define SQ_MIMG_0__LWE__SHIFT 0x11
#define SQ_MIMG_0__OP__SHIFT 0x12
#define SQ_MIMG_0__SLC__SHIFT 0x19
#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
#define SQ_MIMG_0__OPM_MASK 0x00000001L
#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
#define SQ_MIMG_0__UNORM_MASK 0x00001000L
#define SQ_MIMG_0__GLC_MASK 0x00002000L
#define SQ_MIMG_0__DA_MASK 0x00004000L
#define SQ_MIMG_0__A16_MASK 0x00008000L
#define SQ_MIMG_0__TFE_MASK 0x00010000L
#define SQ_MIMG_0__LWE_MASK 0x00020000L
#define SQ_MIMG_0__OP_MASK 0x01FC0000L
#define SQ_MIMG_0__SLC_MASK 0x02000000L
#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
//SQ_MIMG_1
#define SQ_MIMG_1__VADDR__SHIFT 0x0
#define SQ_MIMG_1__VDATA__SHIFT 0x8
#define SQ_MIMG_1__SRSRC__SHIFT 0x10
#define SQ_MIMG_1__SSAMP__SHIFT 0x15
#define SQ_MIMG_1__D16__SHIFT 0x1f
#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
#define SQ_MIMG_1__D16_MASK 0x80000000L
//SQ_MTBUF_0
#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
#define SQ_MTBUF_0__GLC__SHIFT 0xe
#define SQ_MTBUF_0__OP__SHIFT 0xf
#define SQ_MTBUF_0__DFMT__SHIFT 0x13
#define SQ_MTBUF_0__NFMT__SHIFT 0x17
#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
#define SQ_MTBUF_0__GLC_MASK 0x00004000L
#define SQ_MTBUF_0__OP_MASK 0x00078000L
#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
//SQ_MTBUF_1
#define SQ_MTBUF_1__VADDR__SHIFT 0x0
#define SQ_MTBUF_1__VDATA__SHIFT 0x8
#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
#define SQ_MTBUF_1__SLC__SHIFT 0x16
#define SQ_MTBUF_1__TFE__SHIFT 0x17
#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
#define SQ_MTBUF_1__SLC_MASK 0x00400000L
#define SQ_MTBUF_1__TFE_MASK 0x00800000L
#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
//SQ_MUBUF_0
#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
#define SQ_MUBUF_0__GLC__SHIFT 0xe
#define SQ_MUBUF_0__LDS__SHIFT 0x10
#define SQ_MUBUF_0__SLC__SHIFT 0x11
#define SQ_MUBUF_0__OP__SHIFT 0x12
#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
#define SQ_MUBUF_0__GLC_MASK 0x00004000L
#define SQ_MUBUF_0__LDS_MASK 0x00010000L
#define SQ_MUBUF_0__SLC_MASK 0x00020000L
#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
//SQ_MUBUF_1
#define SQ_MUBUF_1__VADDR__SHIFT 0x0
#define SQ_MUBUF_1__VDATA__SHIFT 0x8
#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
#define SQ_MUBUF_1__TFE__SHIFT 0x17
#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
#define SQ_MUBUF_1__TFE_MASK 0x00800000L
#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
//SQ_SCRATCH_0
#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
#define SQ_SCRATCH_0__LDS__SHIFT 0xd
#define SQ_SCRATCH_0__SEG__SHIFT 0xe
#define SQ_SCRATCH_0__GLC__SHIFT 0x10
#define SQ_SCRATCH_0__SLC__SHIFT 0x11
#define SQ_SCRATCH_0__OP__SHIFT 0x12
#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
//SQ_SCRATCH_1
#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
#define SQ_SCRATCH_1__DATA__SHIFT 0x8
#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
#define SQ_SCRATCH_1__NV__SHIFT 0x17
#define SQ_SCRATCH_1__VDST__SHIFT 0x18
#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
#define SQ_SCRATCH_1__NV_MASK 0x00800000L
#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
//SQ_SMEM_0
#define SQ_SMEM_0__SBASE__SHIFT 0x0
#define SQ_SMEM_0__SDATA__SHIFT 0x6
#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
#define SQ_SMEM_0__NV__SHIFT 0xf
#define SQ_SMEM_0__GLC__SHIFT 0x10
#define SQ_SMEM_0__IMM__SHIFT 0x11
#define SQ_SMEM_0__OP__SHIFT 0x12
#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
#define SQ_SMEM_0__NV_MASK 0x00008000L
#define SQ_SMEM_0__GLC_MASK 0x00010000L
#define SQ_SMEM_0__IMM_MASK 0x00020000L
#define SQ_SMEM_0__OP_MASK 0x03FC0000L
#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
//SQ_SMEM_1
#define SQ_SMEM_1__OFFSET__SHIFT 0x0
#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
//SQ_SOP1
#define SQ_SOP1__SSRC0__SHIFT 0x0
#define SQ_SOP1__OP__SHIFT 0x8
#define SQ_SOP1__SDST__SHIFT 0x10
#define SQ_SOP1__ENCODING__SHIFT 0x17
#define SQ_SOP1__SSRC0_MASK 0x000000FFL
#define SQ_SOP1__OP_MASK 0x0000FF00L
#define SQ_SOP1__SDST_MASK 0x007F0000L
#define SQ_SOP1__ENCODING_MASK 0xFF800000L
//SQ_SOP2
#define SQ_SOP2__SSRC0__SHIFT 0x0
#define SQ_SOP2__SSRC1__SHIFT 0x8
#define SQ_SOP2__SDST__SHIFT 0x10
#define SQ_SOP2__OP__SHIFT 0x17
#define SQ_SOP2__ENCODING__SHIFT 0x1e
#define SQ_SOP2__SSRC0_MASK 0x000000FFL
#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
#define SQ_SOP2__SDST_MASK 0x007F0000L
#define SQ_SOP2__OP_MASK 0x3F800000L
#define SQ_SOP2__ENCODING_MASK 0xC0000000L
//SQ_SOPC
#define SQ_SOPC__SSRC0__SHIFT 0x0
#define SQ_SOPC__SSRC1__SHIFT 0x8
#define SQ_SOPC__OP__SHIFT 0x10
#define SQ_SOPC__ENCODING__SHIFT 0x17
#define SQ_SOPC__SSRC0_MASK 0x000000FFL
#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
#define SQ_SOPC__OP_MASK 0x007F0000L
#define SQ_SOPC__ENCODING_MASK 0xFF800000L
//SQ_SOPK
#define SQ_SOPK__SIMM16__SHIFT 0x0
#define SQ_SOPK__SDST__SHIFT 0x10
#define SQ_SOPK__OP__SHIFT 0x17
#define SQ_SOPK__ENCODING__SHIFT 0x1c
#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
#define SQ_SOPK__SDST_MASK 0x007F0000L
#define SQ_SOPK__OP_MASK 0x0F800000L
#define SQ_SOPK__ENCODING_MASK 0xF0000000L
//SQ_SOPP
#define SQ_SOPP__SIMM16__SHIFT 0x0
#define SQ_SOPP__OP__SHIFT 0x10
#define SQ_SOPP__ENCODING__SHIFT 0x17
#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
#define SQ_SOPP__OP_MASK 0x007F0000L
#define SQ_SOPP__ENCODING_MASK 0xFF800000L
//SQ_VINTRP
#define SQ_VINTRP__VSRC__SHIFT 0x0
#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
#define SQ_VINTRP__ATTR__SHIFT 0xa
#define SQ_VINTRP__OP__SHIFT 0x10
#define SQ_VINTRP__VDST__SHIFT 0x12
#define SQ_VINTRP__ENCODING__SHIFT 0x1a
#define SQ_VINTRP__VSRC_MASK 0x000000FFL
#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
#define SQ_VINTRP__OP_MASK 0x00030000L
#define SQ_VINTRP__VDST_MASK 0x03FC0000L
#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
//SQ_VOP1
#define SQ_VOP1__SRC0__SHIFT 0x0
#define SQ_VOP1__OP__SHIFT 0x9
#define SQ_VOP1__VDST__SHIFT 0x11
#define SQ_VOP1__ENCODING__SHIFT 0x19
#define SQ_VOP1__SRC0_MASK 0x000001FFL
#define SQ_VOP1__OP_MASK 0x0001FE00L
#define SQ_VOP1__VDST_MASK 0x01FE0000L
#define SQ_VOP1__ENCODING_MASK 0xFE000000L
//SQ_VOP2
#define SQ_VOP2__SRC0__SHIFT 0x0
#define SQ_VOP2__VSRC1__SHIFT 0x9
#define SQ_VOP2__VDST__SHIFT 0x11
#define SQ_VOP2__OP__SHIFT 0x19
#define SQ_VOP2__ENCODING__SHIFT 0x1f
#define SQ_VOP2__SRC0_MASK 0x000001FFL
#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
#define SQ_VOP2__VDST_MASK 0x01FE0000L
#define SQ_VOP2__OP_MASK 0x7E000000L
#define SQ_VOP2__ENCODING_MASK 0x80000000L
//SQ_VOP3P_0
#define SQ_VOP3P_0__VDST__SHIFT 0x0
#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
#define SQ_VOP3P_0__OP__SHIFT 0x10
#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
#define SQ_VOP3P_0__OP_MASK 0x007F0000L
#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
//SQ_VOP3P_1
#define SQ_VOP3P_1__SRC0__SHIFT 0x0
#define SQ_VOP3P_1__SRC1__SHIFT 0x9
#define SQ_VOP3P_1__SRC2__SHIFT 0x12
#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
#define SQ_VOP3P_1__NEG__SHIFT 0x1d
#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
//SQ_VOP3_0
#define SQ_VOP3_0__VDST__SHIFT 0x0
#define SQ_VOP3_0__ABS__SHIFT 0x8
#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
#define SQ_VOP3_0__CLAMP__SHIFT 0xf
#define SQ_VOP3_0__OP__SHIFT 0x10
#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
#define SQ_VOP3_0__VDST_MASK 0x000000FFL
#define SQ_VOP3_0__ABS_MASK 0x00000700L
#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
#define SQ_VOP3_0__OP_MASK 0x03FF0000L
#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
//SQ_VOP3_0_SDST_ENC
#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
//SQ_VOP3_1
#define SQ_VOP3_1__SRC0__SHIFT 0x0
#define SQ_VOP3_1__SRC1__SHIFT 0x9
#define SQ_VOP3_1__SRC2__SHIFT 0x12
#define SQ_VOP3_1__OMOD__SHIFT 0x1b
#define SQ_VOP3_1__NEG__SHIFT 0x1d
#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
#define SQ_VOP3_1__OMOD_MASK 0x18000000L
#define SQ_VOP3_1__NEG_MASK 0xE0000000L
//SQ_VOPC
#define SQ_VOPC__SRC0__SHIFT 0x0
#define SQ_VOPC__VSRC1__SHIFT 0x9
#define SQ_VOPC__OP__SHIFT 0x11
#define SQ_VOPC__ENCODING__SHIFT 0x19
#define SQ_VOPC__SRC0_MASK 0x000001FFL
#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
#define SQ_VOPC__OP_MASK 0x01FE0000L
#define SQ_VOPC__ENCODING_MASK 0xFE000000L
//SQ_VOP_DPP
#define SQ_VOP_DPP__SRC0__SHIFT 0x0
#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
//SQ_VOP_SDWA
#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_SDWA__S0__SHIFT 0x17
#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
#define SQ_VOP_SDWA__S1__SHIFT 0x1f
#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
#define SQ_VOP_SDWA__S0_MASK 0x00800000L
#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
#define SQ_VOP_SDWA__S1_MASK 0x80000000L
//SQ_VOP_SDWA_SDST_ENC
#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
//SQ_LB_CTR_CTRL
#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
//SQ_LB_DATA0
#define SQ_LB_DATA0__DATA__SHIFT 0x0
#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
//SQ_LB_DATA1
#define SQ_LB_DATA1__DATA__SHIFT 0x0
#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
//SQ_LB_DATA2
#define SQ_LB_DATA2__DATA__SHIFT 0x0
#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
//SQ_LB_DATA3
#define SQ_LB_DATA3__DATA__SHIFT 0x0
#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
//SQ_LB_CTR_SEL
#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
//SQ_LB_CTR0_CU
#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
//SQ_LB_CTR1_CU
#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
//SQ_LB_CTR2_CU
#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
//SQ_LB_CTR3_CU
#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
//SQC_EDC_CNT
#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
//SQ_EDC_SEC_CNT
#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
//SQ_EDC_DED_CNT
#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
//SQ_EDC_INFO
#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
//SQ_EDC_CNT
#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
//SQ_EDC_FUE_CNTL
#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_WORD_CMN
#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
//SQ_THREAD_TRACE_WORD_EVENT
#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
//SQ_THREAD_TRACE_WORD_INST
#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_WORD_ISSUE
#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
//SQ_THREAD_TRACE_WORD_MISC
#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
//SQ_THREAD_TRACE_WORD_REG_1_OF_2
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_WORD_REG_2_OF_2
#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_WORD_WAVE
#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
//SQ_THREAD_TRACE_WORD_WAVE_START
#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
//SQ_WREXEC_EXEC_HI
#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
//SQ_WREXEC_EXEC_LO
#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
//SQ_BUF_RSRC_WORD0
#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
//SQ_BUF_RSRC_WORD1
#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
//SQ_BUF_RSRC_WORD2
#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
//SQ_BUF_RSRC_WORD3
#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
//SQ_IMG_RSRC_WORD0
#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
//SQ_IMG_RSRC_WORD1
#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
//SQ_IMG_RSRC_WORD2
#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
//SQ_IMG_RSRC_WORD3
#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
//SQ_IMG_RSRC_WORD4
#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
//SQ_IMG_RSRC_WORD5
#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
//SQ_IMG_RSRC_WORD6
#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
//SQ_IMG_RSRC_WORD7
#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
//SQ_IMG_SAMP_WORD0
#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
//SQ_IMG_SAMP_WORD1
#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
//SQ_IMG_SAMP_WORD2
#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
//SQ_IMG_SAMP_WORD3
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
//SQ_FLAT_SCRATCH_WORD0
#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
//SQ_FLAT_SCRATCH_WORD1
#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
//SQ_M0_GPR_IDX_WORD
#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
//SQC_ICACHE_UTCL1_CNTL1
#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//SQC_ICACHE_UTCL1_CNTL2
#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
//SQC_DCACHE_UTCL1_CNTL1
#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//SQC_DCACHE_UTCL1_CNTL2
#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
//SQC_ICACHE_UTCL1_STATUS
#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
//SQC_DCACHE_UTCL1_STATUS
#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
// addressBlock: gc_shsdec
//SX_DEBUG_BUSY
#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L
#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L
#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L
#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L
#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L
#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L
#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L
#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L
#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L
#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L
#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L
#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L
#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L
#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L
#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L
#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L
#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L
#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L
#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L
#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L
#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L
#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L
#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L
#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L
#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L
#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L
//SX_DEBUG_BUSY_2
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x19
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x1c
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x1d
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x1e
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x1f
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x00000001L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x00000002L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x00000004L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x00000008L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x00000010L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x00000020L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x00000040L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000080L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000100L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000200L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000400L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000800L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00001000L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00002000L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00004000L
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00008000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00010000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00020000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00040000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00080000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00100000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00200000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00400000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00800000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x01000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x02000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x04000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x08000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x10000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x20000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x40000000L
#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x80000000L
//SX_DEBUG_BUSY_3
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x19
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x1c
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x1d
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x1e
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x1f
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x00000001L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x00000002L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x00000004L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x00000008L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x00000010L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x00000020L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x00000040L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000080L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000100L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000200L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000400L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000800L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00001000L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00002000L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00004000L
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00008000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00010000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00020000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00040000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00080000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00100000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00200000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00400000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00800000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x01000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x02000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x04000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x08000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x10000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x20000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x40000000L
#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x80000000L
//SX_DEBUG_BUSY_4
#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT 0x1
#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT 0x2
#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT 0x5
#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT 0x6
#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT 0x9
#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT 0xa
#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT 0xd
#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT 0xe
#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT 0x13
#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT 0x16
#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT 0x19
#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT 0x1c
#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x1d
#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x1e
#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x1f
#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK 0x00000001L
#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK 0x00000002L
#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK 0x00000004L
#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK 0x00000008L
#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK 0x00000010L
#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK 0x00000020L
#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK 0x00000040L
#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK 0x00000080L
#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK 0x00000100L
#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK 0x00000200L
#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK 0x00000400L
#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK 0x00000800L
#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK 0x00001000L
#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK 0x00002000L
#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK 0x00004000L
#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK 0x00008000L
#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK 0x00010000L
#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK 0x00020000L
#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK 0x00040000L
#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK 0x00080000L
#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK 0x00100000L
#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK 0x00200000L
#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK 0x00400000L
#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK 0x00800000L
#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK 0x01000000L
#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK 0x02000000L
#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK 0x04000000L
#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK 0x08000000L
#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK 0x10000000L
#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK 0x20000000L
#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x40000000L
#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK 0x80000000L
//SX_DEBUG_BUSY_5
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x0
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x1
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x2
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT 0x3
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x4
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0x5
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT 0x6
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT 0x7
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT 0x8
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT 0x9
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT 0xa
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT 0xb
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0xc
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT 0xd
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT 0xe
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT 0xf
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x10
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT 0x11
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x12
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x13
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x14
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x15
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x16
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x17
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT 0x18
#define SX_DEBUG_BUSY_5__RESERVED__SHIFT 0x19
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000001L
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000002L
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000004L
#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK 0x00000008L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000010L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000020L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000040L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK 0x00000080L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK 0x00000100L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK 0x00000200L
#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK 0x00000400L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK 0x00000800L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00001000L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK 0x00002000L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK 0x00004000L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK 0x00008000L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK 0x00010000L
#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK 0x00020000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK 0x00040000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x00080000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK 0x00100000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK 0x00200000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK 0x00400000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK 0x00800000L
#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK 0x01000000L
#define SX_DEBUG_BUSY_5__RESERVED_MASK 0xFE000000L
//SX_DEBUG_1
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
#define SX_DEBUG_1__PC_CFG__SHIFT 0xd
#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L
#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
//SPI_PS_MAX_WAVE_ID
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
//SPI_START_PHASE
#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
//SPI_GFX_CNTL
#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
//SPI_DEBUG_READ
#define SPI_DEBUG_READ__DATA__SHIFT 0x0
#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL
//SPI_DSM_CNTL
#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
//SPI_DSM_CNTL2
#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
//SPI_EDC_CNT
#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
//SPI_DEBUG_BUSY
#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L
#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L
#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L
#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L
#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L
#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L
#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L
#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L
#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L
#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L
#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L
#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L
#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L
#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L
#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L
#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L
#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00010000L
#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00020000L
#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00040000L
#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00080000L
#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L
#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00200000L
#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00400000L
#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00800000L
//SPI_CONFIG_PS_CU_EN
#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
//SPI_WF_LIFETIME_CNTL
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
//SPI_WF_LIFETIME_LIMIT_0
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_1
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_2
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_3
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_4
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_5
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_6
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_7
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_8
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_LIMIT_9
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_0
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_1
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_2
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_3
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_4
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_5
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_6
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_7
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_8
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_9
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_10
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_11
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_12
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_13
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_14
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_15
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_16
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_17
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_18
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_19
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_STATUS_20
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
//SPI_WF_LIFETIME_DEBUG
#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL
#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L
//SPI_LB_CTR_CTRL
#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
//SPI_LB_CU_MASK
#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
//SPI_LB_DATA_REG
#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
//SPI_PG_ENABLE_STATIC_CU_MASK
#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
//SPI_GDS_CREDITS
#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
//SPI_SX_EXPORT_BUFFER_SIZES
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
//SPI_SX_SCOREBOARD_BUFFER_SIZES
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
//SPI_CSQ_WF_ACTIVE_STATUS
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
//SPI_CSQ_WF_ACTIVE_COUNT_0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_1
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_2
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_3
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_4
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_5
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_6
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_7
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
//SPI_LB_DATA_WAVES
#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
//SPI_LB_DATA_PERCU_WAVE_HSGS
#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
//SPI_LB_DATA_PERCU_WAVE_VSPS
#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
//SPI_LB_DATA_PERCU_WAVE_CS
#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
//SPIS_DEBUG_READ
#define SPIS_DEBUG_READ__DATA__SHIFT 0x0
#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL
//BCI_DEBUG_READ
#define BCI_DEBUG_READ__DATA__SHIFT 0x0
#define BCI_DEBUG_READ__DATA_MASK 0xFFFFFFL
//SPI_P0_TRAP_SCREEN_PSBA_LO
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P0_TRAP_SCREEN_PSBA_HI
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
//SPI_P0_TRAP_SCREEN_PSMA_LO
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P0_TRAP_SCREEN_PSMA_HI
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
//SPI_P0_TRAP_SCREEN_GPR_MIN
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
//SPI_P1_TRAP_SCREEN_PSBA_LO
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P1_TRAP_SCREEN_PSBA_HI
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
//SPI_P1_TRAP_SCREEN_PSMA_LO
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_P1_TRAP_SCREEN_PSMA_HI
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
//SPI_P1_TRAP_SCREEN_GPR_MIN
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
// addressBlock: gc_tpdec
//TD_CNTL
#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
//TD_STATUS
#define TD_STATUS__BUSY__SHIFT 0x1f
#define TD_STATUS__BUSY_MASK 0x80000000L
//TD_DSM_CNTL
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
//TD_DSM_CNTL2
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
//TD_SCRATCH
#define TD_SCRATCH__SCRATCH__SHIFT 0x0
#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
//TA_CNTL
#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
//TA_CNTL_AUX
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
//TA_RESERVED_010C
#define TA_RESERVED_010C__Unused__SHIFT 0x0
#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
//TA_STATUS
#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
#define TA_STATUS__IN_BUSY__SHIFT 0x18
#define TA_STATUS__FG_BUSY__SHIFT 0x19
#define TA_STATUS__LA_BUSY__SHIFT 0x1a
#define TA_STATUS__FL_BUSY__SHIFT 0x1b
#define TA_STATUS__TA_BUSY__SHIFT 0x1c
#define TA_STATUS__FA_BUSY__SHIFT 0x1d
#define TA_STATUS__AL_BUSY__SHIFT 0x1e
#define TA_STATUS__BUSY__SHIFT 0x1f
#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
#define TA_STATUS__IN_BUSY_MASK 0x01000000L
#define TA_STATUS__FG_BUSY_MASK 0x02000000L
#define TA_STATUS__LA_BUSY_MASK 0x04000000L
#define TA_STATUS__FL_BUSY_MASK 0x08000000L
#define TA_STATUS__TA_BUSY_MASK 0x10000000L
#define TA_STATUS__FA_BUSY_MASK 0x20000000L
#define TA_STATUS__AL_BUSY_MASK 0x40000000L
#define TA_STATUS__BUSY_MASK 0x80000000L
//TA_SCRATCH
#define TA_SCRATCH__SCRATCH__SHIFT 0x0
#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
// addressBlock: gc_gdsdec
//GDS_CONFIG
#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
//GDS_CNTL_STATUS
#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
//GDS_ENHANCE2
#define GDS_ENHANCE2__MISC__SHIFT 0x0
#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
//GDS_PROTECTION_FAULT
#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
//GDS_VM_PROTECTION_FAULT
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
//GDS_EDC_CNT
#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
//GDS_EDC_GRBM_CNT
#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
//GDS_EDC_OA_DED
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
//GDS_DSM_CNTL
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
//GDS_EDC_OA_PHY_CNT
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
//GDS_EDC_OA_PIPE_CNT
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
//GDS_DSM_CNTL2
#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
//GDS_WD_GDS_CSB
#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
// addressBlock: gc_rbdec
//DB_DEBUG
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
//DB_DEBUG2
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
#define DB_DEBUG2__RESERVED__SHIFT 0x10
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
#define DB_DEBUG2__RESERVED_MASK 0x00010000L
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
//DB_DEBUG3
#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
//DB_DEBUG4
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L
//DB_CREDIT_LIMIT
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
//DB_WATERMARKS
#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
//DB_SUBTILE_CONTROL
#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
//DB_FREE_CACHELINES
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
//DB_FIFO_DEPTH1
#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
//DB_FIFO_DEPTH2
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
//DB_EXCEPTION_CONTROL
#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
//DB_RING_CONTROL
#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
//DB_MEM_ARB_WATERMARKS
#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
//DB_RMI_CACHE_POLICY
#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
//DB_DFSM_CONFIG
#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
//DB_DFSM_WATERMARK
#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
//DB_DFSM_TILES_IN_FLIGHT
#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
//DB_DFSM_PRIMS_IN_FLIGHT
#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
//DB_DFSM_WATCHDOG
#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
//DB_DFSM_FLUSH_ENABLE
#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
//DB_DFSM_FLUSH_AUX_EVENT
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
//CC_RB_REDUNDANCY
#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
//CC_RB_BACKEND_DISABLE
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
//GB_ADDR_CONFIG
#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
//GB_BACKEND_MAP
#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
//GB_GPU_ID
#define GB_GPU_ID__GPU_ID__SHIFT 0x0
#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
//CC_RB_DAISY_CHAIN
#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
//GB_ADDR_CONFIG_READ
#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
//GB_TILE_MODE0
#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE1
#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE2
#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE3
#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE4
#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE5
#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE6
#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE7
#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE8
#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE9
#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE10
#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE11
#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE12
#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE13
#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE14
#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE15
#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE16
#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE17
#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE18
#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE19
#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE20
#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE21
#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE22
#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE23
#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE24
#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE25
#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE26
#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE27
#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE28
#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE29
#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE30
#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
//GB_TILE_MODE31
#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
//GB_MACROTILE_MODE0
#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE1
#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE2
#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE3
#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE4
#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE5
#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE6
#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE7
#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE8
#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE9
#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE10
#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE11
#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE12
#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE13
#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE14
#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
//GB_MACROTILE_MODE15
#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
//CB_HW_CONTROL
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
//CB_HW_CONTROL_1
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
//CB_HW_CONTROL_2
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
//CB_HW_CONTROL_3
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
//CB_HW_MEM_ARBITER_RD
#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
//CB_HW_MEM_ARBITER_WR
#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
//CB_DCC_CONFIG
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
//GC_USER_RB_REDUNDANCY
#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
//GC_USER_RB_BACKEND_DISABLE
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
// addressBlock: gc_rmi_rmidec
//RMI_GENERAL_CNTL
#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
//RMI_GENERAL_CNTL1
#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
//RMI_GENERAL_STATUS
#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
//RMI_SUBBLOCK_STATUS0
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
//RMI_SUBBLOCK_STATUS1
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
//RMI_SUBBLOCK_STATUS2
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
//RMI_SUBBLOCK_STATUS3
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
//RMI_XBAR_CONFIG
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
//RMI_PROBE_POP_LOGIC_CNTL
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
//RMI_UTC_XNACK_N_MISC_CNTL
#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
//RMI_DEMUX_CNTL
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
//RMI_UTCL1_CNTL1
#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//RMI_UTCL1_CNTL2
#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
//RMI_UTC_UNIT_CONFIG
//RMI_TCIW_FORMATTER0_CNTL
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
//RMI_TCIW_FORMATTER1_CNTL
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
//RMI_SCOREBOARD_CNTL
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
//RMI_SCOREBOARD_STATUS0
#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
//RMI_SCOREBOARD_STATUS1
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
//RMI_SCOREBOARD_STATUS2
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
//RMI_XBAR_ARBITER_CONFIG
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
//RMI_XBAR_ARBITER_CONFIG_1
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
//RMI_CLOCK_CNTRL
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
//RMI_UTCL1_STATUS
#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
//RMI_XNACK_DEBUG
#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0
#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL
//RMI_SPARE
#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
//RMI_SPARE_1
#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
//RMI_SPARE_2
#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
// addressBlock: gc_utcl2_atcl2dec
//ATC_L2_CNTL
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
//ATC_L2_CNTL2
#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
//ATC_L2_CACHE_DATA0
#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
//ATC_L2_CACHE_DATA1
#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
//ATC_L2_CACHE_DATA2
#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
//ATC_L2_CNTL3
#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
//ATC_L2_STATUS
#define ATC_L2_STATUS__BUSY__SHIFT 0x0
#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
//ATC_L2_STATUS2
#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
//ATC_L2_MISC_CG
#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
//ATC_L2_MEM_POWER_LS
#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
//ATC_L2_CGTT_CLK_CTRL
#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
// addressBlock: gc_utcl2_vml2pfdec
//VM_L2_CNTL
#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
//VM_L2_CNTL2
#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
//VM_L2_CNTL3
#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
//VM_L2_STATUS
#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
//VM_DUMMY_PAGE_FAULT_CNTL
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
//VM_DUMMY_PAGE_FAULT_ADDR_LO32
#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
//VM_DUMMY_PAGE_FAULT_ADDR_HI32
#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
//VM_L2_PROTECTION_FAULT_CNTL
#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
//VM_L2_PROTECTION_FAULT_CNTL2
#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
//VM_L2_PROTECTION_FAULT_MM_CNTL3
#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_MM_CNTL4
#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_STATUS
#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d
#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e
#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L
#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L
//VM_L2_PROTECTION_FAULT_ADDR_LO32
#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_ADDR_HI32
#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
//VM_L2_CNTL4
#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
//VM_L2_MM_GROUP_RT_CLASSES
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
//VM_L2_BANK_SELECT_RESERVED_CID
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
//VM_L2_BANK_SELECT_RESERVED_CID2
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
//VM_L2_CACHE_PARITY_CNTL
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
//VM_L2_CGTT_CLK_CTRL
#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
//VM_L2_MEM_ECC_INDEX
#define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
#define VM_L2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
//VM_L2_WALKER_MEM_ECC_INDEX
#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0
#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
//VM_L2_MEM_ECC_CNT
#define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc
#define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe
#define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L
#define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L
//VM_L2_WALKER_MEM_ECC_CNT
#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc
#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe
#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L
#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L
// addressBlock: gc_utcl2_vml2vcdec
//VM_CONTEXT0_CNTL
#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT1_CNTL
#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT2_CNTL
#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT3_CNTL
#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT4_CNTL
#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT5_CNTL
#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT6_CNTL
#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT7_CNTL
#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT8_CNTL
#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT9_CNTL
#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT10_CNTL
#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT11_CNTL
#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT12_CNTL
#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT13_CNTL
#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT14_CNTL
#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXT15_CNTL
#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
//VM_CONTEXTS_DISABLE
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
//VM_INVALIDATE_ENG0_SEM
#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG1_SEM
#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG2_SEM
#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG3_SEM
#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG4_SEM
#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG5_SEM
#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG6_SEM
#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG7_SEM
#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG8_SEM
#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG9_SEM
#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG10_SEM
#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG11_SEM
#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG12_SEM
#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG13_SEM
#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG14_SEM
#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG15_SEM
#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG16_SEM
#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG17_SEM
#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
//VM_INVALIDATE_ENG0_REQ
#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG1_REQ
#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG2_REQ
#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG3_REQ
#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG4_REQ
#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG5_REQ
#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG6_REQ
#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG7_REQ
#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG8_REQ
#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG9_REQ
#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG10_REQ
#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG11_REQ
#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG12_REQ
#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG13_REQ
#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG14_REQ
#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG15_REQ
#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG16_REQ
#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG17_REQ
#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
//VM_INVALIDATE_ENG0_ACK
#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG1_ACK
#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG2_ACK
#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG3_ACK
#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG4_ACK
#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG5_ACK
#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG6_ACK
#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG7_ACK
#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG8_ACK
#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG9_ACK
#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG10_ACK
#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG11_ACK
#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG12_ACK
#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG13_ACK
#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG14_ACK
#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG15_ACK
#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG16_ACK
#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG17_ACK
#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
// addressBlock: gc_utcl2_vmsharedpfdec
//MC_VM_NB_MMIOBASE
#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
//MC_VM_NB_MMIOLIMIT
#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
//MC_VM_NB_PCI_CTRL
#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
//MC_VM_NB_PCI_ARB
#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
//MC_VM_NB_TOP_OF_DRAM_SLOT1
#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
//MC_VM_NB_LOWER_TOP_OF_DRAM2
#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
//MC_VM_NB_UPPER_TOP_OF_DRAM2
#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
//MC_VM_FB_OFFSET
#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
//MC_VM_STEERING
#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
//MC_SHARED_VIRT_RESET_REQ
#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
//MC_MEM_POWER_LS
#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
//MC_VM_CACHEABLE_DRAM_ADDRESS_START
#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
//MC_VM_CACHEABLE_DRAM_ADDRESS_END
#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
//MC_VM_APT_CNTL
#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
//MC_VM_LOCAL_HBM_ADDRESS_START
#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
//MC_VM_LOCAL_HBM_ADDRESS_END
#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
// addressBlock: gc_utcl2_vmsharedvcdec
//MC_VM_FB_LOCATION_BASE
#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
//MC_VM_FB_LOCATION_TOP
#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
//MC_VM_AGP_TOP
#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
//MC_VM_AGP_BOT
#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
//MC_VM_AGP_BASE
#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
//MC_VM_SYSTEM_APERTURE_LOW_ADDR
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
//MC_VM_MX_L1_TLB_CNTL
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
// addressBlock: gc_tcdec
//TCP_INVALIDATE
#define TCP_INVALIDATE__START__SHIFT 0x0
#define TCP_INVALIDATE__START_MASK 0x00000001L
//TCP_STATUS
#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
#define TCP_STATUS__READ_BUSY__SHIFT 0x6
#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
#define TCP_STATUS__VM_BUSY__SHIFT 0x8
#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
//TCP_CNTL
#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
#define TCP_CNTL__L1_SIZE__SHIFT 0x2
#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e
#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL
#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L
#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L
#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L
#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L
#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L
//TCP_CHAN_STEER_LO
#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL
#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L
#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L
#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L
#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L
#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L
#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L
#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L
//TCP_CHAN_STEER_HI
#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL
#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L
#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L
#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L
#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L
#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L
#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L
#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L
//TCP_ADDR_CONFIG
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
#define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb
#define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc
#define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
#define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L
#define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L
#define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L
//TCP_CREDIT
#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL
#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L
#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L
//TCP_BUFFER_ADDR_HASH_CNTL
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
//TCP_EDC_CNT
#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL
#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L
#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L
//TC_CFG_L1_LOAD_POLICY0
#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
//TC_CFG_L1_LOAD_POLICY1
#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
//TC_CFG_L1_STORE_POLICY
#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L
#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L
#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L
#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L
#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L
#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L
#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L
#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L
#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L
#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L
#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L
#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L
#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L
#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L
#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L
#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L
#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L
#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L
#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L
#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L
#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L
#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L
#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L
#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L
#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L
#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L
//TC_CFG_L2_LOAD_POLICY0
#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
//TC_CFG_L2_LOAD_POLICY1
#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
//TC_CFG_L2_STORE_POLICY0
#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L
#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL
#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L
#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L
#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L
#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L
#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L
#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L
//TC_CFG_L2_STORE_POLICY1
#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L
#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL
#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L
#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L
#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L
#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L
#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L
#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L
//TC_CFG_L2_ATOMIC_POLICY
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L
//TC_CFG_L1_VOLATILE
#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL
//TC_CFG_L2_VOLATILE
#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
//TCI_STATUS
#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
//TCI_CNTL_1
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
//TCI_CNTL_2
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
//TCC_CTRL
#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
#define TCC_CTRL__RATE__SHIFT 0x2
#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15
#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
#define TCC_CTRL__RATE_MASK 0x0000000CL
#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L
#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L
#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L
#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L
#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L
//TCC_CTRL2
#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
//TCC_EDC_CNT
#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0
#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2
#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4
#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6
#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8
#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa
#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc
#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe
#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10
#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12
#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14
#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16
#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18
#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a
#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c
#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e
#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L
#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL
#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L
#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L
#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L
#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L
#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L
#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L
#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L
#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L
#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L
#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L
#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L
#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L
#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L
#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L
//TCC_EDC_CNT2
#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0
#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2
#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4
#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6
#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8
#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT 0xa
#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT 0xc
#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L
#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL
#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L
#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L
#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L
#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK 0x00000C00L
#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK 0x00003000L
//TCC_REDUNDANCY
#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L
#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L
//TCC_EXE_DISABLE
#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L
//TCC_DSM_CNTL
#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3
#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12
#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15
#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18
#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b
#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L
#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L
#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L
#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L
#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L
#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L
#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L
#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L
#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
//TCC_DSM_CNTLA
#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3
#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6
#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9
#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12
#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15
#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18
#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b
#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L
#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L
#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L
#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L
#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L
#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L
#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L
#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L
#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
//TCC_DSM_CNTL2
#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0
#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11
#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12
#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14
#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15
#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17
#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L
#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L
#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L
#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L
#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
//TCC_DSM_CNTL2A
#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0
#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2
#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3
#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5
#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6
#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8
#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9
#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb
#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe
#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf
#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11
#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12
#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14
#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15
#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17
#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b
#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d
#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L
#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L
#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L
#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L
#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L
#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L
#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L
#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L
#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L
#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L
#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L
#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L
#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L
//TCC_DSM_CNTL2B
#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2
#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
//TCC_WBINVL2
#define TCC_WBINVL2__DONE__SHIFT 0x4
#define TCC_WBINVL2__DONE_MASK 0x00000010L
//TCC_SOFT_RESET
#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
//TCA_CTRL
#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4
#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5
#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6
#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7
#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL
#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L
#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L
#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L
#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L
//TCA_BURST_MASK
#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0
#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
//TCA_BURST_CTRL
#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0
#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3
#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4
#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5
#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6
#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7
#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8
#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9
#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb
#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc
#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd
#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe
#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L
#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L
#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L
#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L
#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L
#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L
#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L
#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L
#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L
#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L
#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L
#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L
#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L
//TCA_DSM_CNTL
#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3
#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L
#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
//TCA_DSM_CNTL2
#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0
#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2
#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3
#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5
#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L
#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L
#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L
#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
//TCA_EDC_CNT
#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0
#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2
#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L
#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL
// addressBlock: gc_shdec
//SPI_SHADER_PGM_RSRC3_PS
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L
//SPI_SHADER_PGM_LO_PS
#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_HI_PS
#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
//SPI_SHADER_PGM_RSRC1_PS
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L
#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
//SPI_SHADER_PGM_RSRC2_PS
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L
//SPI_SHADER_USER_DATA_PS_0
#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_1
#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_2
#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_3
#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_4
#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_5
#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_6
#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_7
#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_8
#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_9
#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_10
#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_11
#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_12
#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_13
#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_14
#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_15
#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_16
#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_17
#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_18
#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_19
#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_20
#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_21
#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_22
#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_23
#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_24
#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_25
#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_26
#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_27
#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_28
#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_29
#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_30
#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_31
#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC3_VS
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L
//SPI_SHADER_LATE_ALLOC_VS
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
//SPI_SHADER_PGM_LO_VS
#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_HI_VS
#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
//SPI_SHADER_PGM_RSRC1_VS
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L
#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
//SPI_SHADER_PGM_RSRC2_VS
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L
//SPI_SHADER_USER_DATA_VS_0
#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_1
#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_2
#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_3
#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_4
#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_5
#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_6
#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_7
#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_8
#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_9
#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_10
#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_11
#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_12
#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_13
#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_14
#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_15
#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_16
#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_17
#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_18
#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_19
#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_20
#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_21
#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_22
#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_23
#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_24
#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_25
#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_26
#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_27
#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_28
#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_29
#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_30
#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_31
#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC2_GS_VS
#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
//SPI_SHADER_PGM_RSRC4_GS
#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L
//SPI_SHADER_USER_DATA_ADDR_LO_GS
#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ADDR_HI_GS
#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_LO_ES
#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_HI_ES
#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
//SPI_SHADER_PGM_RSRC3_GS
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L
//SPI_SHADER_PGM_LO_GS
#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_HI_GS
#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
//SPI_SHADER_PGM_RSRC1_GS
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L
#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
//SPI_SHADER_PGM_RSRC2_GS
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L
//SPI_SHADER_USER_DATA_ES_0
#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_1
#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_2
#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_3
#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_4
#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_5
#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_6
#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_7
#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_8
#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_9
#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_10
#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_11
#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_12
#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_13
#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_14
#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_15
#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_16
#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_17
#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_18
#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_19
#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_20
#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_21
#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_22
#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_23
#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_24
#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_25
#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_26
#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_27
#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_28
#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_29
#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_30
#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ES_31
#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC4_HS
#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
//SPI_SHADER_USER_DATA_ADDR_LO_HS
#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ADDR_HI_HS
#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_LO_LS
#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_HI_LS
#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
//SPI_SHADER_PGM_RSRC3_HS
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L
#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
//SPI_SHADER_PGM_LO_HS
#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
//SPI_SHADER_PGM_HI_HS
#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
//SPI_SHADER_PGM_RSRC1_HS
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L
#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
//SPI_SHADER_PGM_RSRC2_HS
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L
#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L
#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L
//SPI_SHADER_USER_DATA_LS_0
#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_1
#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_2
#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_3
#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_4
#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_5
#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_6
#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_7
#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_8
#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_9
#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_10
#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_11
#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_12
#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_13
#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_14
#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_15
#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_16
#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_17
#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_18
#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_19
#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_20
#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_21
#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_22
#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_23
#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_24
#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_25
#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_26
#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_27
#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_28
#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_29
#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_30
#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_LS_31
#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_0
#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_1
#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_2
#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_3
#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_4
#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_5
#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_6
#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_7
#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_8
#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_9
#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_10
#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_11
#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_12
#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_13
#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_14
#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_15
#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_16
#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_17
#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_18
#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_19
#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_20
#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_21
#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_22
#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_23
#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_24
#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_25
#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_26
#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_27
#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_28
#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_29
#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_30
#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_COMMON_31
#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL
//COMPUTE_DISPATCH_INITIATOR
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
//COMPUTE_DIM_X
#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
//COMPUTE_DIM_Y
#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
//COMPUTE_DIM_Z
#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
//COMPUTE_START_X
#define COMPUTE_START_X__START__SHIFT 0x0
#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
//COMPUTE_START_Y
#define COMPUTE_START_Y__START__SHIFT 0x0
#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
//COMPUTE_START_Z
#define COMPUTE_START_Z__START__SHIFT 0x0
#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
//COMPUTE_NUM_THREAD_X
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
//COMPUTE_NUM_THREAD_Y
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
//COMPUTE_NUM_THREAD_Z
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
//COMPUTE_PIPELINESTAT_ENABLE
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
//COMPUTE_PERFCOUNT_ENABLE
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
//COMPUTE_PGM_LO
#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
//COMPUTE_PGM_HI
#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
//COMPUTE_DISPATCH_PKT_ADDR_LO
#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
//COMPUTE_DISPATCH_PKT_ADDR_HI
#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
//COMPUTE_DISPATCH_SCRATCH_BASE_LO
#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
//COMPUTE_DISPATCH_SCRATCH_BASE_HI
#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
//COMPUTE_PGM_RSRC1
#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L
#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L
#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
//COMPUTE_PGM_RSRC2
#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f
#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L
//COMPUTE_VMID
#define COMPUTE_VMID__DATA__SHIFT 0x0
#define COMPUTE_VMID__DATA_MASK 0x0000000FL
//COMPUTE_RESOURCE_LIMITS
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L
//COMPUTE_STATIC_THREAD_MGMT_SE0
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L
//COMPUTE_STATIC_THREAD_MGMT_SE1
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L
//COMPUTE_TMPRING_SIZE
#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
//COMPUTE_STATIC_THREAD_MGMT_SE2
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L
//COMPUTE_STATIC_THREAD_MGMT_SE3
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L
//COMPUTE_RESTART_X
#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
//COMPUTE_RESTART_Y
#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
//COMPUTE_RESTART_Z
#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
//COMPUTE_THREAD_TRACE_ENABLE
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
//COMPUTE_MISC_RESERVED
#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L
#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L
#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
//COMPUTE_DISPATCH_ID
#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
//COMPUTE_THREADGROUP_ID
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
//COMPUTE_RELAUNCH
#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
//COMPUTE_WAVE_RESTORE_ADDR_LO
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
//COMPUTE_WAVE_RESTORE_ADDR_HI
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
//COMPUTE_USER_DATA_0
#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_1
#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_2
#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_3
#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_4
#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_5
#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_6
#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_7
#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_8
#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_9
#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_10
#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_11
#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_12
#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_13
#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_14
#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
//COMPUTE_USER_DATA_15
#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
//COMPUTE_NOWHERE
#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
// addressBlock: gc_cppdec
//CP_DFY_CNTL
#define CP_DFY_CNTL__POLICY__SHIFT 0x0
#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a
#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
#define CP_DFY_CNTL__MODE__SHIFT 0x1d
#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
#define CP_DFY_CNTL__POLICY_MASK 0x00000001L
#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL
#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L
#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L
#define CP_DFY_CNTL__MODE_MASK 0x60000000L
#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L
//CP_DFY_STAT
#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
#define CP_DFY_STAT__BUSY__SHIFT 0x1f
#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL
#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L
#define CP_DFY_STAT__BUSY_MASK 0x80000000L
//CP_DFY_ADDR_HI
#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
//CP_DFY_ADDR_LO
#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L
//CP_DFY_DATA_0
#define CP_DFY_DATA_0__DATA__SHIFT 0x0
#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_1
#define CP_DFY_DATA_1__DATA__SHIFT 0x0
#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_2
#define CP_DFY_DATA_2__DATA__SHIFT 0x0
#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_3
#define CP_DFY_DATA_3__DATA__SHIFT 0x0
#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_4
#define CP_DFY_DATA_4__DATA__SHIFT 0x0
#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_5
#define CP_DFY_DATA_5__DATA__SHIFT 0x0
#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_6
#define CP_DFY_DATA_6__DATA__SHIFT 0x0
#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_7
#define CP_DFY_DATA_7__DATA__SHIFT 0x0
#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_8
#define CP_DFY_DATA_8__DATA__SHIFT 0x0
#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_9
#define CP_DFY_DATA_9__DATA__SHIFT 0x0
#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_10
#define CP_DFY_DATA_10__DATA__SHIFT 0x0
#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_11
#define CP_DFY_DATA_11__DATA__SHIFT 0x0
#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_12
#define CP_DFY_DATA_12__DATA__SHIFT 0x0
#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_13
#define CP_DFY_DATA_13__DATA__SHIFT 0x0
#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_14
#define CP_DFY_DATA_14__DATA__SHIFT 0x0
#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL
//CP_DFY_DATA_15
#define CP_DFY_DATA_15__DATA__SHIFT 0x0
#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL
//CP_DFY_CMD
#define CP_DFY_CMD__OFFSET__SHIFT 0x0
#define CP_DFY_CMD__SIZE__SHIFT 0x10
#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL
#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L
//CP_EOPQ_WAIT_TIME
#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
//CP_CPC_MGCG_SYNC_CNTL
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
//CPC_INT_INFO
#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
#define CPC_INT_INFO__TYPE__SHIFT 0x10
#define CPC_INT_INFO__VMID__SHIFT 0x14
#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
#define CPC_INT_INFO__TYPE_MASK 0x00010000L
#define CPC_INT_INFO__VMID_MASK 0x00F00000L
#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
//CP_VIRT_STATUS
#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
//CPC_INT_ADDR
#define CPC_INT_ADDR__ADDR__SHIFT 0x0
#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
//CPC_INT_PASID
#define CPC_INT_PASID__PASID__SHIFT 0x0
#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
//CP_GFX_ERROR
#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0
#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5
#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6
#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L
#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L
#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
//CPG_UTCL1_CNTL
#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
//CPC_UTCL1_CNTL
#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
//CPF_UTCL1_CNTL
#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
//CP_AQL_SMM_STATUS
#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
//CP_RB0_BASE
#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
//CP_RB_BASE
#define CP_RB_BASE__RB_BASE__SHIFT 0x0
#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
//CP_RB0_CNTL
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
//CP_RB_CNTL
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L
#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
//CP_RB_RPTR_WR
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
//CP_RB0_RPTR_ADDR
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
//CP_RB_RPTR_ADDR
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
//CP_RB0_RPTR_ADDR_HI
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
//CP_RB_RPTR_ADDR_HI
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
//CP_RB0_BUFSZ_MASK
#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
//CP_RB_BUFSZ_MASK
#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
//CP_RB_WPTR_POLL_ADDR_LO
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
//CP_RB_WPTR_POLL_ADDR_HI
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
//GC_PRIV_MODE
//CP_INT_CNTL
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_INT_STATUS
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
//CP_DEVICE_ID
#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
//CP_ME0_PIPE_PRIORITY_CNTS
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
//CP_RING_PRIORITY_CNTS
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
//CP_ME0_PIPE0_PRIORITY
#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_RING0_PRIORITY
#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME0_PIPE1_PRIORITY
#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_RING1_PRIORITY
#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME0_PIPE2_PRIORITY
#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_RING2_PRIORITY
#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_FATAL_ERROR
#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
//CP_RB_VMID
#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
//CP_ME0_PIPE0_VMID
#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
//CP_ME0_PIPE1_VMID
#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
//CP_RB0_WPTR
#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
//CP_RB_WPTR
#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
//CP_RB0_WPTR_HI
#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
//CP_RB_WPTR_HI
#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
//CP_RB1_WPTR
#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
//CP_RB1_WPTR_HI
#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
//CP_RB2_WPTR
#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
//CP_RB_DOORBELL_CONTROL
#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_RANGE_LOWER
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
//CP_RB_DOORBELL_RANGE_UPPER
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
//CP_MEC_DOORBELL_RANGE_LOWER
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
//CP_MEC_DOORBELL_RANGE_UPPER
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
//CPG_UTCL1_ERROR
#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
//CPC_UTCL1_ERROR
#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
//CP_RB1_BASE
#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
//CP_RB1_CNTL
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
//CP_RB1_RPTR_ADDR
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
//CP_RB1_RPTR_ADDR_HI
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
//CP_RB2_BASE
#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
//CP_RB2_CNTL
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
//CP_RB2_RPTR_ADDR
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
//CP_RB2_RPTR_ADDR_HI
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
//CP_RB0_ACTIVE
#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
//CP_RB_ACTIVE
#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
//CP_INT_CNTL_RING0
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_INT_CNTL_RING1
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_INT_CNTL_RING2
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_INT_STATUS_RING0
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
//CP_INT_STATUS_RING1
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
//CP_INT_STATUS_RING2
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
//CP_PWR_CNTL
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
//CP_MEM_SLP_CNTL
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
//CP_ECC_FIRSTOCCURRENCE
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
//CP_ECC_FIRSTOCCURRENCE_RING0
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
//CP_ECC_FIRSTOCCURRENCE_RING1
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
//CP_ECC_FIRSTOCCURRENCE_RING2
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
//GB_EDC_MODE
#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11
#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L
#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
//CP_CPF_DEBUG
//CP_PQ_WPTR_POLL_CNTL
#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
//CP_PQ_WPTR_POLL_CNTL1
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
//CP_ME1_PIPE0_INT_CNTL
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME1_PIPE1_INT_CNTL
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME1_PIPE2_INT_CNTL
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME1_PIPE3_INT_CNTL
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME2_PIPE0_INT_CNTL
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME2_PIPE1_INT_CNTL
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME2_PIPE2_INT_CNTL
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME2_PIPE3_INT_CNTL
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CP_ME1_PIPE0_INT_STATUS
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME1_PIPE1_INT_STATUS
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME1_PIPE2_INT_STATUS
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME1_PIPE3_INT_STATUS
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME2_PIPE0_INT_STATUS
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME2_PIPE1_INT_STATUS
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME2_PIPE2_INT_STATUS
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME2_PIPE3_INT_STATUS
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_ME1_INT_STAT_DEBUG
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
//CP_ME2_INT_STAT_DEBUG
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
//CC_GC_EDC_CONFIG
#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
//CP_ME1_PIPE_PRIORITY_CNTS
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
//CP_ME1_PIPE0_PRIORITY
#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME1_PIPE1_PRIORITY
#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME1_PIPE2_PRIORITY
#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME1_PIPE3_PRIORITY
#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME2_PIPE_PRIORITY_CNTS
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
//CP_ME2_PIPE0_PRIORITY
#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME2_PIPE1_PRIORITY
#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME2_PIPE2_PRIORITY
#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_ME2_PIPE3_PRIORITY
#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
//CP_CE_PRGRM_CNTR_START
#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL
//CP_PFP_PRGRM_CNTR_START
#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL
//CP_ME_PRGRM_CNTR_START
#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL
//CP_MEC1_PRGRM_CNTR_START
#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
//CP_MEC2_PRGRM_CNTR_START
#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
//CP_CE_INTR_ROUTINE_START
#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL
//CP_PFP_INTR_ROUTINE_START
#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL
//CP_ME_INTR_ROUTINE_START
#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL
//CP_MEC1_INTR_ROUTINE_START
#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
//CP_MEC2_INTR_ROUTINE_START
#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
//CP_CONTEXT_CNTL
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
//CP_MAX_CONTEXT
#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
//CP_IQ_WAIT_TIME1
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
//CP_IQ_WAIT_TIME2
#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
//CP_RB0_BASE_HI
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
//CP_RB1_BASE_HI
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
//CP_VMID_RESET
#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
//CPC_INT_CNTL
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
//CPC_INT_STATUS
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
//CP_VMID_PREEMPT
#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
//CPC_INT_CNTX_ID
#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
//CP_PQ_STATUS
#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
//CP_CPC_IC_BASE_LO
#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
//CP_CPC_IC_BASE_HI
#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
//CP_CPC_IC_BASE_CNTL
#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L
//CP_CPC_IC_OP_CNTL
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
//CP_MEC1_F32_INT_DIS
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
//CP_MEC2_F32_INT_DIS
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
//CP_VMID_STATUS
#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
// addressBlock: gc_cppdec2
//CP_RB_DOORBELL_CONTROL_SCH_0
#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_1
#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_2
#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_3
#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_4
#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_5
#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_6
#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CONTROL_SCH_7
#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L
#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L
//CP_RB_DOORBELL_CLEAR
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
//CP_GFX_MQD_CONTROL
#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
//CP_GFX_MQD_BASE_ADDR
#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
//CP_GFX_MQD_BASE_ADDR_HI
#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
//CP_RB_STATUS
#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
//CPG_UTCL1_STATUS
#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//CPC_UTCL1_STATUS
#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//CPF_UTCL1_STATUS
#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
//CP_SD_CNTL
#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
#define CP_SD_CNTL__WD_EN__SHIFT 0x5
#define CP_SD_CNTL__IA_EN__SHIFT 0x6
#define CP_SD_CNTL__PA_EN__SHIFT 0x7
#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
#define CP_SD_CNTL__EA_EN__SHIFT 0x9
#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
#define CP_SD_CNTL__WD_EN_MASK 0x00000020L
#define CP_SD_CNTL__IA_EN_MASK 0x00000040L
#define CP_SD_CNTL__PA_EN_MASK 0x00000080L
#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
//CP_SOFT_RESET_CNTL
#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
//CP_CPC_GFX_CNTL
#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
// addressBlock: gc_spipdec
//SPI_ARB_PRIORITY
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
//SPI_ARB_CYCLES_0
#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
//SPI_ARB_CYCLES_1
#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
//SPI_CDBG_SYS_GFX
#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x0001L
#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x0002L
#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x0004L
#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x0008L
#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x0010L
#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x0020L
#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x0040L
//SPI_CDBG_SYS_HP3D
#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x0001L
#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x0002L
#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x0004L
#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x0008L
#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x0010L
#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x0020L
//SPI_CDBG_SYS_CS0
#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL
#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L
#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L
#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L
//SPI_CDBG_SYS_CS1
#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0x000000FFL
#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0x0000FF00L
#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0x00FF0000L
#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xFF000000L
//SPI_WCL_PIPE_PERCENT_GFX
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
//SPI_WCL_PIPE_PERCENT_HP3D
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
//SPI_WCL_PIPE_PERCENT_CS0
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS1
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS2
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS3
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS4
#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS5
#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS6
#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
//SPI_WCL_PIPE_PERCENT_CS7
#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
//SPI_GDBG_WAVE_CNTL
#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L
#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL
//SPI_GDBG_TRAP_CONFIG
#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L
#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL
#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L
#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L
#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L
#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L
#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L
#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L
//SPI_GDBG_TRAP_MASK
#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL
#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L
//SPI_GDBG_WAVE_CNTL2
#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10
#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL
#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L
//SPI_GDBG_WAVE_CNTL3
#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1
#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2
#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3
#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4
#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5
#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6
#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7
#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8
#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9
#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb
#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc
#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd
#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c
#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L
#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L
#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L
#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L
#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L
#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L
#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L
#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L
//SPI_GDBG_TRAP_DATA0
#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL
//SPI_GDBG_TRAP_DATA1
#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL
//SPI_RESET_DEBUG
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x01L
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x02L
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x04L
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x08L
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10L
//SPI_COMPUTE_QUEUE_RESET
#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
//SPI_RESOURCE_RESERVE_CU_0
#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_1
#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_2
#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_3
#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_4
#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_5
#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_6
#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_7
#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_8
#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_9
#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_EN_CU_0
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_1
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_2
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_3
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_4
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_5
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_6
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_7
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_8
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_9
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_CU_10
#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_11
#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_EN_CU_10
#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_11
#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_CU_12
#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_13
#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_14
#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_CU_15
#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
//SPI_RESOURCE_RESERVE_EN_CU_12
#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_13
#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_14
#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_RESOURCE_RESERVE_EN_CU_15
#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
//SPI_COMPUTE_WF_CTX_SAVE
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
//SPI_ARB_CNTL_0
#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
// addressBlock: gc_cpphqddec
//CP_HQD_GFX_CONTROL
#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
//CP_HQD_GFX_STATUS
#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
//CP_HPD_ROQ_OFFSETS
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L
//CP_HPD_STATUS0
#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
//CP_HPD_UTCL1_CNTL
#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
//CP_HPD_UTCL1_ERROR
#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
//CP_HPD_UTCL1_ERROR_ADDR
#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
//CP_MQD_BASE_ADDR
#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
//CP_MQD_BASE_ADDR_HI
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
//CP_HQD_ACTIVE
#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
//CP_HQD_VMID
#define CP_HQD_VMID__VMID__SHIFT 0x0
#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
#define CP_HQD_VMID__VQID__SHIFT 0x10
#define CP_HQD_VMID__VMID_MASK 0x0000000FL
#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
//CP_HQD_PERSISTENT_STATE
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
//CP_HQD_PIPE_PRIORITY
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
//CP_HQD_QUEUE_PRIORITY
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
//CP_HQD_QUANTUM
#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
//CP_HQD_PQ_BASE
#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
//CP_HQD_PQ_BASE_HI
#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
//CP_HQD_PQ_RPTR
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
//CP_HQD_PQ_RPTR_REPORT_ADDR
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
//CP_HQD_PQ_WPTR_POLL_ADDR
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
//CP_HQD_PQ_WPTR_POLL_ADDR_HI
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
//CP_HQD_PQ_DOORBELL_CONTROL
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
//CP_HQD_PQ_CONTROL
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10
#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L
#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L
#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
//CP_HQD_IB_BASE_ADDR
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
//CP_HQD_IB_BASE_ADDR_HI
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
//CP_HQD_IB_RPTR
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
//CP_HQD_IB_CONTROL
#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L
#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
//CP_HQD_IQ_TIMER
#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19
#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L
#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L
#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
//CP_HQD_IQ_RPTR
#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
//CP_HQD_DEQUEUE_REQUEST
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
//CP_HQD_DMA_OFFLOAD
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
//CP_HQD_OFFLOAD
#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
//CP_HQD_SEMA_CMD
#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
//CP_HQD_MSG_TYPE
#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
//CP_HQD_ATOMIC0_PREOP_LO
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
//CP_HQD_ATOMIC0_PREOP_HI
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
//CP_HQD_ATOMIC1_PREOP_LO
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
//CP_HQD_ATOMIC1_PREOP_HI
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
//CP_HQD_HQ_SCHEDULER0
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
//CP_HQD_HQ_STATUS0
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
//CP_HQD_HQ_CONTROL0
#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
//CP_HQD_HQ_SCHEDULER1
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
//CP_MQD_CONTROL
#define CP_MQD_CONTROL__VMID__SHIFT 0x0
#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
//CP_HQD_HQ_STATUS1
#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
//CP_HQD_HQ_CONTROL1
#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
//CP_HQD_EOP_BASE_ADDR
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
//CP_HQD_EOP_BASE_ADDR_HI
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
//CP_HQD_EOP_CONTROL
#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
//CP_HQD_EOP_RPTR
#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
//CP_HQD_EOP_WPTR
#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
//CP_HQD_EOP_EVENTS
#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
//CP_HQD_CTX_SAVE_BASE_ADDR_LO
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
//CP_HQD_CTX_SAVE_BASE_ADDR_HI
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_HQD_CTX_SAVE_CONTROL
#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L
#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
//CP_HQD_CNTL_STACK_OFFSET
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
//CP_HQD_CNTL_STACK_SIZE
#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
//CP_HQD_WG_STATE_OFFSET
#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
//CP_HQD_CTX_SAVE_SIZE
#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
//CP_HQD_GDS_RESOURCE_STATE
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
//CP_HQD_ERROR
#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
//CP_HQD_EOP_WPTR_MEM
#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
//CP_HQD_AQL_CONTROL
#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
//CP_HQD_PQ_WPTR_LO
#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
//CP_HQD_PQ_WPTR_HI
#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
// addressBlock: gc_didtdec
//DIDT_IND_INDEX
#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
//DIDT_IND_DATA
#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
// addressBlock: gc_gccacdec
//GC_CAC_CTRL_1
#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
//GC_CAC_CTRL_2
#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2
#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL
//GC_CAC_CGTT_CLK_CTRL
#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
//GC_CAC_AGGR_LOWER
#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_AGGR_UPPER
#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
//GC_CAC_SOFT_CTRL
#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1
#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL
//GC_DIDT_CTRL0
#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
//GC_DIDT_CTRL1
#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
//GC_DIDT_CTRL2
#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe
#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a
#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f
#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L
#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L
#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L
//GC_DIDT_WEIGHT
#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
//GC_DIDT_WEIGHT_1
#define GC_DIDT_WEIGHT_1__DBR_WEIGHT__SHIFT 0x0
#define GC_DIDT_WEIGHT_1__DBR_WEIGHT_MASK 0x000000FFL
//GC_EDC_CTRL
#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa
#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L
//GC_EDC_THRESHOLD
#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
//GC_EDC_STATUS
#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0
#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3
#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L
#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L
//GC_EDC_OVERFLOW
#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11
#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12
#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L
#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L
//GC_EDC_ROLLING_POWER_DELTA
#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
//GC_DIDT_DROOP_CTRL
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf
#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L
#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L
#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L
//GC_EDC_DROOP_CTRL
#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0
#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1
#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf
#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14
#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15
#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L
#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL
#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L
#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L
#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L
//GC_CAC_IND_INDEX
#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
//GC_CAC_IND_DATA
#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
//SE_CAC_CGTT_CLK_CTRL
#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
//SE_CAC_IND_INDEX
#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
//SE_CAC_IND_DATA
#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
// addressBlock: gc_tcpdec
//TCP_WATCH0_ADDR_H
#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
//TCP_WATCH0_ADDR_L
#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//TCP_WATCH0_CNTL
#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L
#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
//TCP_WATCH1_ADDR_H
#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
//TCP_WATCH1_ADDR_L
#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//TCP_WATCH1_CNTL
#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L
#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
//TCP_WATCH2_ADDR_H
#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
//TCP_WATCH2_ADDR_L
#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//TCP_WATCH2_CNTL
#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L
#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
//TCP_WATCH3_ADDR_H
#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
//TCP_WATCH3_ADDR_L
#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
//TCP_WATCH3_CNTL
#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L
#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
//TCP_GATCL1_CNTL
#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L
#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L
#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L
#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//TCP_ATC_EDC_GATCL1_CNT
#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL
//TCP_GATCL1_DSM_CNTL
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L
#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L
//TCP_CNTL2
#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL
//TCP_UTCL1_CNTL1
#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//TCP_UTCL1_CNTL2
#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0
#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
//TCP_UTCL1_STATUS
#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
//TCP_PERFCOUNTER_FILTER
#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb
#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf
#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14
#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16
#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19
#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a
#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b
#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L
#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L
#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L
#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L
#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L
#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L
#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L
#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L
#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L
//TCP_PERFCOUNTER_FILTER_EN
#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8
#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9
#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb
#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L
#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L
#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L
#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L
// addressBlock: gc_gdspdec
//GDS_VMID0_BASE
#define GDS_VMID0_BASE__BASE__SHIFT 0x0
#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID0_SIZE
#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID1_BASE
#define GDS_VMID1_BASE__BASE__SHIFT 0x0
#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID1_SIZE
#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID2_BASE
#define GDS_VMID2_BASE__BASE__SHIFT 0x0
#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID2_SIZE
#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID3_BASE
#define GDS_VMID3_BASE__BASE__SHIFT 0x0
#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID3_SIZE
#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID4_BASE
#define GDS_VMID4_BASE__BASE__SHIFT 0x0
#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID4_SIZE
#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID5_BASE
#define GDS_VMID5_BASE__BASE__SHIFT 0x0
#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID5_SIZE
#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID6_BASE
#define GDS_VMID6_BASE__BASE__SHIFT 0x0
#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID6_SIZE
#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID7_BASE
#define GDS_VMID7_BASE__BASE__SHIFT 0x0
#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID7_SIZE
#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID8_BASE
#define GDS_VMID8_BASE__BASE__SHIFT 0x0
#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID8_SIZE
#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID9_BASE
#define GDS_VMID9_BASE__BASE__SHIFT 0x0
#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID9_SIZE
#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID10_BASE
#define GDS_VMID10_BASE__BASE__SHIFT 0x0
#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID10_SIZE
#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID11_BASE
#define GDS_VMID11_BASE__BASE__SHIFT 0x0
#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID11_SIZE
#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID12_BASE
#define GDS_VMID12_BASE__BASE__SHIFT 0x0
#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID12_SIZE
#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID13_BASE
#define GDS_VMID13_BASE__BASE__SHIFT 0x0
#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID13_SIZE
#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID14_BASE
#define GDS_VMID14_BASE__BASE__SHIFT 0x0
#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID14_SIZE
#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_VMID15_BASE
#define GDS_VMID15_BASE__BASE__SHIFT 0x0
#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
//GDS_VMID15_SIZE
#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
//GDS_GWS_VMID0
#define GDS_GWS_VMID0__BASE__SHIFT 0x0
#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID1
#define GDS_GWS_VMID1__BASE__SHIFT 0x0
#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID2
#define GDS_GWS_VMID2__BASE__SHIFT 0x0
#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID3
#define GDS_GWS_VMID3__BASE__SHIFT 0x0
#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID4
#define GDS_GWS_VMID4__BASE__SHIFT 0x0
#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID5
#define GDS_GWS_VMID5__BASE__SHIFT 0x0
#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID6
#define GDS_GWS_VMID6__BASE__SHIFT 0x0
#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID7
#define GDS_GWS_VMID7__BASE__SHIFT 0x0
#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID8
#define GDS_GWS_VMID8__BASE__SHIFT 0x0
#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID9
#define GDS_GWS_VMID9__BASE__SHIFT 0x0
#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID10
#define GDS_GWS_VMID10__BASE__SHIFT 0x0
#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID11
#define GDS_GWS_VMID11__BASE__SHIFT 0x0
#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID12
#define GDS_GWS_VMID12__BASE__SHIFT 0x0
#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID13
#define GDS_GWS_VMID13__BASE__SHIFT 0x0
#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID14
#define GDS_GWS_VMID14__BASE__SHIFT 0x0
#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
//GDS_GWS_VMID15
#define GDS_GWS_VMID15__BASE__SHIFT 0x0
#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
//GDS_OA_VMID0
#define GDS_OA_VMID0__MASK__SHIFT 0x0
#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID1
#define GDS_OA_VMID1__MASK__SHIFT 0x0
#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID2
#define GDS_OA_VMID2__MASK__SHIFT 0x0
#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID3
#define GDS_OA_VMID3__MASK__SHIFT 0x0
#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID4
#define GDS_OA_VMID4__MASK__SHIFT 0x0
#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID5
#define GDS_OA_VMID5__MASK__SHIFT 0x0
#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID6
#define GDS_OA_VMID6__MASK__SHIFT 0x0
#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID7
#define GDS_OA_VMID7__MASK__SHIFT 0x0
#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID8
#define GDS_OA_VMID8__MASK__SHIFT 0x0
#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID9
#define GDS_OA_VMID9__MASK__SHIFT 0x0
#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID10
#define GDS_OA_VMID10__MASK__SHIFT 0x0
#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID11
#define GDS_OA_VMID11__MASK__SHIFT 0x0
#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID12
#define GDS_OA_VMID12__MASK__SHIFT 0x0
#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID13
#define GDS_OA_VMID13__MASK__SHIFT 0x0
#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID14
#define GDS_OA_VMID14__MASK__SHIFT 0x0
#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
//GDS_OA_VMID15
#define GDS_OA_VMID15__MASK__SHIFT 0x0
#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
//GDS_GWS_RESET0
#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
//GDS_GWS_RESET1
#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
//GDS_GWS_RESOURCE_RESET
#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
//GDS_COMPUTE_MAX_WAVE_ID
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
//GDS_OA_RESET_MASK
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
//GDS_OA_RESET
#define GDS_OA_RESET__RESET__SHIFT 0x0
#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
#define GDS_OA_RESET__RESET_MASK 0x00000001L
#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
//GDS_ENHANCE
#define GDS_ENHANCE__MISC__SHIFT 0x0
#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12
#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13
#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14
#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
#define GDS_ENHANCE__UNUSED__SHIFT 0x16
#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L
#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L
#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L
#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L
//GDS_OA_CGPG_RESTORE
#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
//GDS_CS_CTXSW_STATUS
#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
//GDS_CS_CTXSW_CNT0
#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_CS_CTXSW_CNT1
#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_CS_CTXSW_CNT2
#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_CS_CTXSW_CNT3
#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_GFX_CTXSW_STATUS
#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
//GDS_VS_CTXSW_CNT0
#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_VS_CTXSW_CNT1
#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_VS_CTXSW_CNT2
#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_VS_CTXSW_CNT3
#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS0_CTXSW_CNT0
#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS0_CTXSW_CNT1
#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS0_CTXSW_CNT2
#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS0_CTXSW_CNT3
#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS1_CTXSW_CNT0
#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS1_CTXSW_CNT1
#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS1_CTXSW_CNT2
#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS1_CTXSW_CNT3
#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS2_CTXSW_CNT0
#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS2_CTXSW_CNT1
#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS2_CTXSW_CNT2
#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS2_CTXSW_CNT3
#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS3_CTXSW_CNT0
#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS3_CTXSW_CNT1
#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS3_CTXSW_CNT2
#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS3_CTXSW_CNT3
#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS4_CTXSW_CNT0
#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS4_CTXSW_CNT1
#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS4_CTXSW_CNT2
#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS4_CTXSW_CNT3
#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS5_CTXSW_CNT0
#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS5_CTXSW_CNT1
#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS5_CTXSW_CNT2
#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS5_CTXSW_CNT3
#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS6_CTXSW_CNT0
#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS6_CTXSW_CNT1
#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS6_CTXSW_CNT2
#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS6_CTXSW_CNT3
#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_PS7_CTXSW_CNT0
#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_PS7_CTXSW_CNT1
#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_PS7_CTXSW_CNT2
#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_PS7_CTXSW_CNT3
#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
//GDS_GS_CTXSW_CNT0
#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
//GDS_GS_CTXSW_CNT1
#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
//GDS_GS_CTXSW_CNT2
#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
//GDS_GS_CTXSW_CNT3
#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
// addressBlock: gc_rasdec
//RAS_SIGNATURE_CONTROL
#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L
//RAS_SIGNATURE_MASK
#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL
//RAS_SX_SIGNATURE0
#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SX_SIGNATURE1
#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SX_SIGNATURE2
#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SX_SIGNATURE3
#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_DB_SIGNATURE0
#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_PA_SIGNATURE0
#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_VGT_SIGNATURE0
#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SQ_SIGNATURE0
#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE0
#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE1
#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE2
#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE3
#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE4
#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE5
#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE6
#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SC_SIGNATURE7
#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_IA_SIGNATURE0
#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_IA_SIGNATURE1
#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SPI_SIGNATURE0
#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_SPI_SIGNATURE1
#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_TA_SIGNATURE0
#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_TD_SIGNATURE0
#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_CB_SIGNATURE0
#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_BCI_SIGNATURE0
#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_BCI_SIGNATURE1
#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
//RAS_TA_SIGNATURE1
#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
// addressBlock: gc_gfxdec0
//DB_RENDER_CONTROL
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
//DB_COUNT_CONTROL
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
//DB_DEPTH_VIEW
#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
//DB_RENDER_OVERRIDE
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
//DB_RENDER_OVERRIDE2
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
//DB_HTILE_DATA_BASE
#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
//DB_HTILE_DATA_BASE_HI
#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
//DB_DEPTH_SIZE
#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0
#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10
#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL
#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L
//DB_DEPTH_BOUNDS_MIN
#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
//DB_DEPTH_BOUNDS_MAX
#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
//DB_STENCIL_CLEAR
#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
//DB_DEPTH_CLEAR
#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
//PA_SC_SCREEN_SCISSOR_TL
#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
//PA_SC_SCREEN_SCISSOR_BR
#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
//DB_Z_INFO
#define DB_Z_INFO__FORMAT__SHIFT 0x0
#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
#define DB_Z_INFO__SW_MODE__SHIFT 0x4
#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd
#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf
#define DB_Z_INFO__MAXMIP__SHIFT 0x10
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
#define DB_Z_INFO__FORMAT_MASK 0x00000003L
#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L
#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
//DB_STENCIL_INFO
#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd
#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
//DB_Z_READ_BASE
#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
//DB_Z_READ_BASE_HI
#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
//DB_STENCIL_READ_BASE
#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
//DB_STENCIL_READ_BASE_HI
#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
//DB_Z_WRITE_BASE
#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
//DB_Z_WRITE_BASE_HI
#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
//DB_STENCIL_WRITE_BASE
#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
//DB_STENCIL_WRITE_BASE_HI
#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
//DB_DFSM_CONTROL
#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
//DB_Z_INFO2
#define DB_Z_INFO2__EPITCH__SHIFT 0x0
#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
//DB_STENCIL_INFO2
#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0
#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL
//TA_BC_BASE_ADDR
#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
//TA_BC_BASE_ADDR_HI
#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
//COHER_DEST_BASE_HI_0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
//COHER_DEST_BASE_HI_1
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
//COHER_DEST_BASE_HI_2
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
//COHER_DEST_BASE_HI_3
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
//COHER_DEST_BASE_2
#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
//COHER_DEST_BASE_3
#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
//PA_SC_WINDOW_OFFSET
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
//PA_SC_WINDOW_SCISSOR_TL
#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_WINDOW_SCISSOR_BR
#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_RULE
#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
//PA_SC_CLIPRECT_0_TL
#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_0_BR
#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_1_TL
#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_1_BR
#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_2_TL
#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_2_BR
#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_3_TL
#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
//PA_SC_CLIPRECT_3_BR
#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_EDGERULE
#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
//PA_SU_HARDWARE_SCREEN_OFFSET
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
//CB_TARGET_MASK
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
//CB_SHADER_MASK
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
//PA_SC_GENERIC_SCISSOR_TL
#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_GENERIC_SCISSOR_BR
#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
//COHER_DEST_BASE_0
#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
//COHER_DEST_BASE_1
#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
//PA_SC_VPORT_SCISSOR_0_TL
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_0_BR
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_1_TL
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_1_BR
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_2_TL
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_2_BR
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_3_TL
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_3_BR
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_4_TL
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_4_BR
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_5_TL
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_5_BR
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_6_TL
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_6_BR
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_7_TL
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_7_BR
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_8_TL
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_8_BR
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_9_TL
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_9_BR
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_10_TL
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_10_BR
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_11_TL
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_11_BR
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_12_TL
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_12_BR
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_13_TL
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_13_BR
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_14_TL
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_14_BR
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_SCISSOR_15_TL
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
//PA_SC_VPORT_SCISSOR_15_BR
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
//PA_SC_VPORT_ZMIN_0
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_0
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_1
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_1
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_2
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_2
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_3
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_3
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_4
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_4
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_5
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_5
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_6
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_6
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_7
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_7
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_8
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_8
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_9
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_9
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_10
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_10
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_11
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_11
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_12
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_12
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_13
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_13
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_14
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_14
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_15
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_15
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
//PA_SC_RASTER_CONFIG
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L
#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L
//PA_SC_RASTER_CONFIG_1
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L
//PA_SC_SCREEN_EXTENT_CONTROL
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
//PA_SC_TILE_STEERING_OVERRIDE
#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
//CP_PERFMON_CNTX_CNTL
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
//CP_PIPEID
#define CP_PIPEID__PIPE_ID__SHIFT 0x0
#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
//CP_RINGID
#define CP_RINGID__RINGID__SHIFT 0x0
#define CP_RINGID__RINGID_MASK 0x00000003L
//CP_VMID
#define CP_VMID__VMID__SHIFT 0x0
#define CP_VMID__VMID_MASK 0x0000000FL
//PA_SC_RIGHT_VERT_GRID
#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
//PA_SC_LEFT_VERT_GRID
#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
//PA_SC_HORIZ_GRID
#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
//VGT_MULTI_PRIM_IB_RESET_INDX
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
//CB_BLEND_RED
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
//CB_BLEND_GREEN
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
//CB_BLEND_BLUE
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
//CB_BLEND_ALPHA
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
//CB_DCC_CONTROL
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
//DB_STENCIL_CONTROL
#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
//DB_STENCILREFMASK
#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
//DB_STENCILREFMASK_BF
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
//PA_CL_VPORT_XSCALE
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_1
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_1
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_1
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_1
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_1
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_1
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_2
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_2
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_2
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_2
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_2
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_2
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_3
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_3
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_3
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_3
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_3
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_3
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_4
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_4
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_4
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_4
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_4
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_4
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_5
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_5
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_5
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_5
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_5
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_5
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_6
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_6
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_6
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_6
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_6
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_6
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_7
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_7
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_7
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_7
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_7
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_7
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_8
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_8
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_8
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_8
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_8
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_8
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_9
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_9
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_9
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_9
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_9
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_9
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_10
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_10
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_10
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_10
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_10
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_10
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_11
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_11
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_11
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_11
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_11
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_11
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_12
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_12
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_12
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_12
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_12
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_12
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_13
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_13
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_13
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_13
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_13
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_13
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_14
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_14
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_14
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_14
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_14
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_14
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_15
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_15
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_15
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_15
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_15
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_15
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
//PA_CL_UCP_0_X
#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_0_Y
#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_0_Z
#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_0_W
#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_1_X
#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_1_Y
#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_1_Z
#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_1_W
#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_2_X
#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_2_Y
#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_2_Z
#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_2_W
#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_3_X
#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_3_Y
#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_3_Z
#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_3_W
#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_4_X
#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_4_Y
#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_4_Z
#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_4_W
#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_5_X
#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_5_Y
#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_5_Z
#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_UCP_5_W
#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
//SPI_PS_INPUT_CNTL_0
#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_1
#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_2
#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_3
#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_4
#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_5
#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_6
#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_7
#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_8
#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_9
#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_10
#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_11
#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_12
#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_13
#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_14
#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_15
#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_16
#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_17
#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_18
#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_19
#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_20
#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_21
#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_22
#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_23
#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_24
#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_25
#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_26
#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_27
#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_28
#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_29
#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_30
#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
//SPI_PS_INPUT_CNTL_31
#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
//SPI_VS_OUT_CONFIG
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
//SPI_PS_INPUT_ENA
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
//SPI_PS_INPUT_ADDR
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
//SPI_INTERP_CONTROL_0
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
//SPI_PS_IN_CONTROL
#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
//SPI_BARYC_CNTL
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
//SPI_TMPRING_SIZE
#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
//SPI_SHADER_POS_FORMAT
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
//SPI_SHADER_Z_FORMAT
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
//SPI_SHADER_COL_FORMAT
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
//SX_PS_DOWNCONVERT
#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
//SX_BLEND_OPT_EPSILON
#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
//SX_BLEND_OPT_CONTROL
#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
//SX_MRT0_BLEND_OPT
#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT1_BLEND_OPT
#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT2_BLEND_OPT
#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT3_BLEND_OPT
#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT4_BLEND_OPT
#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT5_BLEND_OPT
#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT6_BLEND_OPT
#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//SX_MRT7_BLEND_OPT
#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
//CB_BLEND0_CONTROL
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND1_CONTROL
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND2_CONTROL
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND3_CONTROL
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND4_CONTROL
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND5_CONTROL
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND6_CONTROL
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_BLEND7_CONTROL
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
//CB_MRT0_EPITCH
#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT1_EPITCH
#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT2_EPITCH
#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT3_EPITCH
#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT4_EPITCH
#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT5_EPITCH
#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT6_EPITCH
#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL
//CB_MRT7_EPITCH
#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0
#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL
//CS_COPY_STATE
#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
//GFX_COPY_STATE
#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
//PA_CL_POINT_X_RAD
#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_POINT_Y_RAD
#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_POINT_SIZE
#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_POINT_CULL_RAD
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
//VGT_DMA_BASE_HI
#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
//VGT_DMA_BASE
#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
//VGT_DRAW_INITIATOR
#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
//VGT_IMMED_DATA
#define VGT_IMMED_DATA__DATA__SHIFT 0x0
#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
//VGT_EVENT_ADDRESS_REG
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
//DB_DEPTH_CONTROL
#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
//DB_EQAA
#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
//CB_COLOR_CONTROL
#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
//DB_SHADER_CONTROL
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
//PA_CL_CLIP_CNTL
#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
//PA_SU_SC_MODE_CNTL
#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
//PA_CL_VTE_CNTL
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
//PA_CL_VS_OUT_CNTL
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L
//PA_CL_NANINF_CNTL
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
//PA_SU_LINE_STIPPLE_CNTL
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
//PA_SU_LINE_STIPPLE_SCALE
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
//PA_SU_PRIM_FILTER_CNTL
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
//PA_SU_SMALL_PRIM_FILTER_CNTL
#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
//PA_CL_OBJPRIM_ID_CNTL
#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2
#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L
//PA_CL_NGG_CNTL
#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
//PA_SU_OVER_RASTERIZATION_CNTL
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
//PA_SU_POINT_SIZE
#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
//PA_SU_POINT_MINMAX
#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
//PA_SU_LINE_CNTL
#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
//PA_SC_LINE_STIPPLE
#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
//VGT_OUTPUT_PATH_CNTL
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
//VGT_HOS_CNTL
#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
//VGT_HOS_MAX_TESS_LEVEL
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
//VGT_HOS_MIN_TESS_LEVEL
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
//VGT_HOS_REUSE_DEPTH
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
//VGT_GROUP_PRIM_TYPE
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
//VGT_GROUP_FIRST_DECR
#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
//VGT_GROUP_DECR
#define VGT_GROUP_DECR__DECR__SHIFT 0x0
#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
//VGT_GROUP_VECT_0_CNTL
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
//VGT_GROUP_VECT_1_CNTL
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
//VGT_GROUP_VECT_0_FMT_CNTL
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
//VGT_GROUP_VECT_1_FMT_CNTL
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
//VGT_GS_MODE
#define VGT_GS_MODE__MODE__SHIFT 0x0
#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
#define VGT_GS_MODE__MODE_MASK 0x00000007L
#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L
#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L
#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
//VGT_GS_ONCHIP_CNTL
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
//PA_SC_MODE_CNTL_0
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
//PA_SC_MODE_CNTL_1
#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
//VGT_ENHANCE
#define VGT_ENHANCE__MISC__SHIFT 0x0
#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
//VGT_GS_PER_ES
#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
//VGT_ES_PER_GS
#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
//VGT_GS_PER_VS
#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
//VGT_GSVS_RING_OFFSET_1
#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
//VGT_GSVS_RING_OFFSET_2
#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
//VGT_GSVS_RING_OFFSET_3
#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
//VGT_GS_OUT_PRIM_TYPE
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
//IA_ENHANCE
#define IA_ENHANCE__MISC__SHIFT 0x0
#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
//VGT_DMA_SIZE
#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
//VGT_DMA_MAX_SIZE
#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
//VGT_DMA_INDEX_TYPE
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L
#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
//WD_ENHANCE
#define WD_ENHANCE__MISC__SHIFT 0x0
#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
//VGT_PRIMITIVEID_EN
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
//VGT_DMA_NUM_INSTANCES
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
//VGT_PRIMITIVEID_RESET
#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
//VGT_EVENT_INITIATOR
#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
//VGT_GS_MAX_PRIMS_PER_SUBGROUP
#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0
#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL
//VGT_DRAW_PAYLOAD_CNTL
#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2
#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3
#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
//VGT_INSTANCE_STEP_RATE_0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
//VGT_INSTANCE_STEP_RATE_1
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
//VGT_ESGS_RING_ITEMSIZE
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
//VGT_GSVS_RING_ITEMSIZE
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
//VGT_REUSE_OFF
#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
//VGT_VTX_CNT_EN
#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
//DB_HTILE_SURFACE
#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13
#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L
#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L
//DB_SRESULTS_COMPARE_STATE0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
//DB_SRESULTS_COMPARE_STATE1
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
//DB_PRELOAD_CONTROL
#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
//VGT_STRMOUT_BUFFER_SIZE_0
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_0
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_0
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_SIZE_1
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_1
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_1
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_SIZE_2
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_2
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_2
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_SIZE_3
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_3
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_3
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
//VGT_GS_MAX_VERT_OUT
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
//VGT_TESS_DISTRIBUTION
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
//VGT_SHADER_STAGES_EN
#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L
//VGT_LS_HS_CONFIG
#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
//VGT_GS_VERT_ITEMSIZE
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
//VGT_GS_VERT_ITEMSIZE_1
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
//VGT_GS_VERT_ITEMSIZE_2
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
//VGT_GS_VERT_ITEMSIZE_3
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
//VGT_TF_PARAM
#define VGT_TF_PARAM__TYPE__SHIFT 0x0
#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L
#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
//DB_ALPHA_TO_MASK
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
//VGT_DISPATCH_DRAW_INDEX
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
//PA_SU_POLY_OFFSET_DB_FMT_CNTL
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
//PA_SU_POLY_OFFSET_CLAMP
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
//PA_SU_POLY_OFFSET_FRONT_SCALE
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
//PA_SU_POLY_OFFSET_FRONT_OFFSET
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
//PA_SU_POLY_OFFSET_BACK_SCALE
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
//PA_SU_POLY_OFFSET_BACK_OFFSET
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
//VGT_GS_INSTANCE_CNT
#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
//VGT_STRMOUT_CONFIG
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
//VGT_STRMOUT_BUFFER_CONFIG
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
//VGT_DMA_EVENT_INITIATOR
#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
//PA_SC_CENTROID_PRIORITY_0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
//PA_SC_CENTROID_PRIORITY_1
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
//PA_SC_LINE_CNTL
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
//PA_SC_AA_CONFIG
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
//PA_SU_VTX_CNTL
#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
//PA_CL_GB_VERT_CLIP_ADJ
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_GB_VERT_DISC_ADJ
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_GB_HORZ_CLIP_ADJ
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_CL_GB_HORZ_DISC_ADJ
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
//PA_SC_AA_MASK_X0Y0_X1Y0
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
//PA_SC_AA_MASK_X0Y1_X1Y1
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
//PA_SC_SHADER_CONTROL
#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
//PA_SC_BINNER_CNTL_0
#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
//PA_SC_BINNER_CNTL_1
#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
//PA_SC_NGG_MODE_CNTL
#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
//VGT_VERTEX_REUSE_BLOCK_CNTL
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
//VGT_OUT_DEALLOC_CNTL
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
//CB_COLOR0_BASE
#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR0_BASE_EXT
#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR0_ATTRIB2
#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR0_VIEW
#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR0_INFO
#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR0_ATTRIB
#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR0_DCC_CONTROL
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR0_CMASK
#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR0_CMASK_BASE_EXT
#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR0_FMASK
#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR0_FMASK_BASE_EXT
#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR0_CLEAR_WORD0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR0_CLEAR_WORD1
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR0_DCC_BASE
#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR0_DCC_BASE_EXT
#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR1_BASE
#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR1_BASE_EXT
#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR1_ATTRIB2
#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR1_VIEW
#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR1_INFO
#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR1_ATTRIB
#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR1_DCC_CONTROL
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR1_CMASK
#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR1_CMASK_BASE_EXT
#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR1_FMASK
#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR1_FMASK_BASE_EXT
#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR1_CLEAR_WORD0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR1_CLEAR_WORD1
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR1_DCC_BASE
#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR1_DCC_BASE_EXT
#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR2_BASE
#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR2_BASE_EXT
#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR2_ATTRIB2
#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR2_VIEW
#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR2_INFO
#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR2_ATTRIB
#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR2_DCC_CONTROL
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR2_CMASK
#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR2_CMASK_BASE_EXT
#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR2_FMASK
#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR2_FMASK_BASE_EXT
#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR2_CLEAR_WORD0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR2_CLEAR_WORD1
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR2_DCC_BASE
#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR2_DCC_BASE_EXT
#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR3_BASE
#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR3_BASE_EXT
#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR3_ATTRIB2
#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR3_VIEW
#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR3_INFO
#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR3_ATTRIB
#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR3_DCC_CONTROL
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR3_CMASK
#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR3_CMASK_BASE_EXT
#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR3_FMASK
#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR3_FMASK_BASE_EXT
#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR3_CLEAR_WORD0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR3_CLEAR_WORD1
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR3_DCC_BASE
#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR3_DCC_BASE_EXT
#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR4_BASE
#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR4_BASE_EXT
#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR4_ATTRIB2
#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR4_VIEW
#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR4_INFO
#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR4_ATTRIB
#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR4_DCC_CONTROL
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR4_CMASK
#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR4_CMASK_BASE_EXT
#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR4_FMASK
#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR4_FMASK_BASE_EXT
#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR4_CLEAR_WORD0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR4_CLEAR_WORD1
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR4_DCC_BASE
#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR4_DCC_BASE_EXT
#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR5_BASE
#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR5_BASE_EXT
#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR5_ATTRIB2
#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR5_VIEW
#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR5_INFO
#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR5_ATTRIB
#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR5_DCC_CONTROL
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR5_CMASK
#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR5_CMASK_BASE_EXT
#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR5_FMASK
#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR5_FMASK_BASE_EXT
#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR5_CLEAR_WORD0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR5_CLEAR_WORD1
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR5_DCC_BASE
#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR5_DCC_BASE_EXT
#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR6_BASE
#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR6_BASE_EXT
#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR6_ATTRIB2
#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR6_VIEW
#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR6_INFO
#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR6_ATTRIB
#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR6_DCC_CONTROL
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR6_CMASK
#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR6_CMASK_BASE_EXT
#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR6_FMASK
#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR6_FMASK_BASE_EXT
#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR6_CLEAR_WORD0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR6_CLEAR_WORD1
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR6_DCC_BASE
#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR6_DCC_BASE_EXT
#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR7_BASE
#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR7_BASE_EXT
#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR7_ATTRIB2
#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
//CB_COLOR7_VIEW
#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18
#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL
#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L
#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L
//CB_COLOR7_INFO
#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
//CB_COLOR7_ATTRIB
#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0
#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e
#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L
#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
//CB_COLOR7_DCC_CONTROL
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
//CB_COLOR7_CMASK
#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR7_CMASK_BASE_EXT
#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR7_FMASK
#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR7_FMASK_BASE_EXT
#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
//CB_COLOR7_CLEAR_WORD0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
//CB_COLOR7_CLEAR_WORD1
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
//CB_COLOR7_DCC_BASE
#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
//CB_COLOR7_DCC_BASE_EXT
#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
// addressBlock: gc_gfxudec
//CP_EOP_DONE_ADDR_LO
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
//CP_EOP_DONE_ADDR_HI
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_EOP_DONE_DATA_LO
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
//CP_EOP_DONE_DATA_HI
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
//CP_EOP_LAST_FENCE_LO
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
//CP_EOP_LAST_FENCE_HI
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
//CP_STREAM_OUT_ADDR_LO
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
//CP_STREAM_OUT_ADDR_HI
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
//CP_NUM_PRIM_WRITTEN_COUNT0_LO
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT0_HI
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT0_LO
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT0_HI
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT1_LO
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT1_HI
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT1_LO
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT1_HI
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT2_LO
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT2_HI
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT2_LO
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT2_HI
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT3_LO
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT3_HI
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT3_LO
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT3_HI
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
//CP_PIPE_STATS_ADDR_LO
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
//CP_PIPE_STATS_ADDR_HI
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
//CP_VGT_IAVERT_COUNT_LO
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_IAVERT_COUNT_HI
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
//CP_VGT_IAPRIM_COUNT_LO
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_IAPRIM_COUNT_HI
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
//CP_VGT_GSPRIM_COUNT_LO
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_GSPRIM_COUNT_HI
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
//CP_VGT_VSINVOC_COUNT_LO
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_VSINVOC_COUNT_HI
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
//CP_VGT_GSINVOC_COUNT_LO
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_GSINVOC_COUNT_HI
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
//CP_VGT_HSINVOC_COUNT_LO
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_HSINVOC_COUNT_HI
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
//CP_VGT_DSINVOC_COUNT_LO
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_DSINVOC_COUNT_HI
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
//CP_PA_CINVOC_COUNT_LO
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
//CP_PA_CINVOC_COUNT_HI
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
//CP_PA_CPRIM_COUNT_LO
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
//CP_PA_CPRIM_COUNT_HI
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT0_LO
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT0_HI
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT1_LO
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT1_HI
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
//CP_VGT_CSINVOC_COUNT_LO
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
//CP_VGT_CSINVOC_COUNT_HI
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
//CP_PIPE_STATS_CONTROL
#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L
//CP_STREAM_OUT_CONTROL
#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L
//CP_STRMOUT_CNTL
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
//SCRATCH_REG0
#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
//SCRATCH_REG1
#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
//SCRATCH_REG2
#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
//SCRATCH_REG3
#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
//SCRATCH_REG4
#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
//SCRATCH_REG5
#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
//SCRATCH_REG6
#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
//SCRATCH_REG7
#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
//CP_APPEND_DATA_HI
#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
//CP_APPEND_LAST_CS_FENCE_HI
#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
//CP_APPEND_LAST_PS_FENCE_HI
#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
//SCRATCH_UMSK
#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
//SCRATCH_ADDR
#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
//CP_PFP_ATOMIC_PREOP_LO
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
//CP_PFP_ATOMIC_PREOP_HI
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC0_PREOP_LO
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC0_PREOP_HI
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC1_PREOP_LO
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC1_PREOP_HI
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
//CP_APPEND_ADDR_LO
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
//CP_APPEND_ADDR_HI
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L
#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
//CP_APPEND_DATA_LO
#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
//CP_APPEND_LAST_CS_FENCE_LO
#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
//CP_APPEND_LAST_PS_FENCE_LO
#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
//CP_ATOMIC_PREOP_LO
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
//CP_ME_ATOMIC_PREOP_LO
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
//CP_ATOMIC_PREOP_HI
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
//CP_ME_ATOMIC_PREOP_HI
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
//CP_GDS_ATOMIC0_PREOP_LO
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
//CP_ME_GDS_ATOMIC0_PREOP_LO
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
//CP_GDS_ATOMIC0_PREOP_HI
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
//CP_ME_GDS_ATOMIC0_PREOP_HI
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
//CP_GDS_ATOMIC1_PREOP_LO
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
//CP_ME_GDS_ATOMIC1_PREOP_LO
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
//CP_GDS_ATOMIC1_PREOP_HI
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
//CP_ME_GDS_ATOMIC1_PREOP_HI
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
//CP_ME_MC_WADDR_LO
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
//CP_ME_MC_WADDR_HI
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L
//CP_ME_MC_WDATA_LO
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
//CP_ME_MC_WDATA_HI
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
//CP_ME_MC_RADDR_LO
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
//CP_ME_MC_RADDR_HI
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L
//CP_SEM_WAIT_TIMER
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
//CP_SIG_SEM_ADDR_LO
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
//CP_SIG_SEM_ADDR_HI
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
//CP_WAIT_REG_MEM_TIMEOUT
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
//CP_WAIT_SEM_ADDR_LO
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
//CP_WAIT_SEM_ADDR_HI
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
//CP_DMA_PFP_CONTROL
#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
//CP_DMA_ME_CONTROL
#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
//CP_COHER_BASE_HI
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
//CP_COHER_START_DELAY
#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
//CP_COHER_CNTL
#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
//CP_COHER_SIZE
#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
//CP_COHER_BASE
#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
//CP_COHER_STATUS
#define CP_COHER_STATUS__MEID__SHIFT 0x18
#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
#define CP_COHER_STATUS__MEID_MASK 0x03000000L
#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
//CP_DMA_ME_SRC_ADDR
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
//CP_DMA_ME_SRC_ADDR_HI
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
//CP_DMA_ME_DST_ADDR
#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
//CP_DMA_ME_DST_ADDR_HI
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
//CP_DMA_ME_COMMAND
#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
//CP_DMA_PFP_SRC_ADDR
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
//CP_DMA_PFP_SRC_ADDR_HI
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
//CP_DMA_PFP_DST_ADDR
#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
//CP_DMA_PFP_DST_ADDR_HI
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
//CP_DMA_PFP_COMMAND
#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
//CP_DMA_CNTL
#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L
#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
//CP_DMA_READ_TAGS
#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
//CP_COHER_SIZE_HI
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
//CP_PFP_IB_CONTROL
#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
//CP_PFP_LOAD_CONTROL
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
//CP_SCRATCH_INDEX
#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
//CP_SCRATCH_DATA
#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
//CP_RB_OFFSET
#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
//CP_IB1_OFFSET
#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
//CP_IB2_OFFSET
#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
//CP_IB1_PREAMBLE_BEGIN
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL
//CP_IB1_PREAMBLE_END
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL
//CP_IB2_PREAMBLE_BEGIN
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
//CP_IB2_PREAMBLE_END
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
//CP_CE_IB1_OFFSET
#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
//CP_CE_IB2_OFFSET
#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
//CP_CE_COUNTER
#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
//CP_CE_RB_OFFSET
#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
//CP_CE_INIT_CMD_BUFSZ
#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
//CP_CE_IB1_CMD_BUFSZ
#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
//CP_CE_IB2_CMD_BUFSZ
#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
//CP_IB1_CMD_BUFSZ
#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
//CP_IB2_CMD_BUFSZ
#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
//CP_ST_CMD_BUFSZ
#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
//CP_CE_INIT_BASE_LO
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
//CP_CE_INIT_BASE_HI
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
//CP_CE_INIT_BUFSZ
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
//CP_CE_IB1_BASE_LO
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
//CP_CE_IB1_BASE_HI
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
//CP_CE_IB1_BUFSZ
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
//CP_CE_IB2_BASE_LO
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
//CP_CE_IB2_BASE_HI
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
//CP_CE_IB2_BUFSZ
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
//CP_IB1_BASE_LO
#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
//CP_IB1_BASE_HI
#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
//CP_IB1_BUFSZ
#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
//CP_IB2_BASE_LO
#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
//CP_IB2_BASE_HI
#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
//CP_IB2_BUFSZ
#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
//CP_ST_BASE_LO
#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
//CP_ST_BASE_HI
#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
//CP_ST_BUFSZ
#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
//CP_EOP_DONE_EVENT_CNTL
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L
#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L
#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
//CP_EOP_DONE_DATA_CNTL
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
//CP_EOP_DONE_CNTX_ID
#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
//CP_PFP_COMPLETION_STATUS
#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
//CP_CE_COMPLETION_STATUS
#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
//CP_PRED_NOT_VISIBLE
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
//CP_PFP_METADATA_BASE_ADDR
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
//CP_PFP_METADATA_BASE_ADDR_HI
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_CE_METADATA_BASE_ADDR
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
//CP_CE_METADATA_BASE_ADDR_HI
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_DRAW_INDX_INDR_ADDR
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
//CP_DRAW_INDX_INDR_ADDR_HI
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_DISPATCH_INDR_ADDR
#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
//CP_DISPATCH_INDR_ADDR_HI
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_INDEX_BASE_ADDR
#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
//CP_INDEX_BASE_ADDR_HI
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_INDEX_TYPE
#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
//CP_GDS_BKUP_ADDR
#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
//CP_GDS_BKUP_ADDR_HI
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
//CP_SAMPLE_STATUS
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
//CP_ME_COHER_CNTL
#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
//CP_ME_COHER_SIZE
#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
//CP_ME_COHER_SIZE_HI
#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
//CP_ME_COHER_BASE
#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
//CP_ME_COHER_BASE_HI
#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
//CP_ME_COHER_STATUS
#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
//RLC_GPM_PERF_COUNT_0
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L
#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
//RLC_GPM_PERF_COUNT_1
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L
#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
//GRBM_GFX_INDEX
#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L
#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
//VGT_GSVS_RING_SIZE
#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
//VGT_PRIMITIVE_TYPE
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
//VGT_INDEX_TYPE
#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
//VGT_MAX_VTX_INDX
#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
//VGT_MIN_VTX_INDX
#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
//VGT_INDX_OFFSET
#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
//VGT_MULTI_PRIM_IB_RESET_EN
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
//VGT_NUM_INDICES
#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
//VGT_NUM_INSTANCES
#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
//VGT_TF_RING_SIZE
#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
//VGT_HS_OFFCHIP_PARAM
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
//VGT_TF_MEMORY_BASE
#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
//VGT_TF_MEMORY_BASE_HI
#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
//WD_POS_BUF_BASE
#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
//WD_POS_BUF_BASE_HI
#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
//WD_CNTL_SB_BUF_BASE
#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
//WD_CNTL_SB_BUF_BASE_HI
#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
//WD_INDEX_BUF_BASE
#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
//WD_INDEX_BUF_BASE_HI
#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
//IA_MULTI_VGT_PARAM
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15
#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16
#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
//VGT_INSTANCE_BASE_ID
#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
//PA_SU_LINE_STIPPLE_VALUE
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
//PA_SC_LINE_STIPPLE_STATE
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
//PA_SC_SCREEN_EXTENT_MIN_0
#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
//PA_SC_SCREEN_EXTENT_MAX_0
#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
//PA_SC_SCREEN_EXTENT_MIN_1
#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
//PA_SC_SCREEN_EXTENT_MAX_1
#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
//PA_SC_P3D_TRAP_SCREEN_HV_EN
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
//PA_SC_P3D_TRAP_SCREEN_H
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
//PA_SC_P3D_TRAP_SCREEN_V
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
//PA_SC_P3D_TRAP_SCREEN_COUNT
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
//PA_SC_HP3D_TRAP_SCREEN_HV_EN
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
//PA_SC_HP3D_TRAP_SCREEN_H
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
//PA_SC_HP3D_TRAP_SCREEN_V
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
//PA_SC_HP3D_TRAP_SCREEN_COUNT
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
//PA_SC_TRAP_SCREEN_HV_EN
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
//PA_SC_TRAP_SCREEN_H
#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
//PA_SC_TRAP_SCREEN_V
#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
//PA_SC_TRAP_SCREEN_OCCURRENCE
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
//PA_SC_TRAP_SCREEN_COUNT
#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
//SQ_THREAD_TRACE_BASE
#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_SIZE
#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL
//SQ_THREAD_TRACE_MASK
#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL
#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L
#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
//SQ_THREAD_TRACE_TOKEN_MASK
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
//SQ_THREAD_TRACE_PERF_MASK
#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL
#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L
//SQ_THREAD_TRACE_CTRL
#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
//SQ_THREAD_TRACE_MODE
#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a
#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L
#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L
#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L
#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L
#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
//SQ_THREAD_TRACE_BASE2
#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL
//SQ_THREAD_TRACE_TOKEN_MASK2
#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_WPTR
#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL
#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L
//SQ_THREAD_TRACE_STATUS
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c
#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L
#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L
#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
//SQ_THREAD_TRACE_HIWATER
#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
//SQ_THREAD_TRACE_CNTR
#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_0
#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_1
#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_2
#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_3
#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
//SQC_CACHES
#define SQC_CACHES__TARGET_INST__SHIFT 0x0
#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
#define SQC_CACHES__INVALIDATE__SHIFT 0x2
#define SQC_CACHES__WRITEBACK__SHIFT 0x3
#define SQC_CACHES__VOL__SHIFT 0x4
#define SQC_CACHES__COMPLETE__SHIFT 0x10
#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
#define SQC_CACHES__VOL_MASK 0x00000010L
#define SQC_CACHES__COMPLETE_MASK 0x00010000L
//SQC_WRITEBACK
#define SQC_WRITEBACK__DWB__SHIFT 0x0
#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
#define SQC_WRITEBACK__DWB_MASK 0x00000001L
#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
//TA_CS_BC_BASE_ADDR
#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
//TA_CS_BC_BASE_ADDR_HI
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
//DB_OCCLUSION_COUNT0_LOW
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
//DB_OCCLUSION_COUNT0_HI
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
//DB_OCCLUSION_COUNT1_LOW
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
//DB_OCCLUSION_COUNT1_HI
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
//DB_OCCLUSION_COUNT2_LOW
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
//DB_OCCLUSION_COUNT2_HI
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
//DB_OCCLUSION_COUNT3_LOW
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
//DB_OCCLUSION_COUNT3_HI
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
//DB_ZPASS_COUNT_LOW
#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
//DB_ZPASS_COUNT_HI
#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
//GDS_RD_ADDR
#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
//GDS_RD_DATA
#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
//GDS_RD_BURST_ADDR
#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
//GDS_RD_BURST_COUNT
#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
//GDS_RD_BURST_DATA
#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
//GDS_WR_ADDR
#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
//GDS_WR_DATA
#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
//GDS_WR_BURST_ADDR
#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
//GDS_WR_BURST_DATA
#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
//GDS_WRITE_COMPLETE
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
//GDS_ATOM_CNTL
#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
//GDS_ATOM_COMPLETE
#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
//GDS_ATOM_BASE
#define GDS_ATOM_BASE__BASE__SHIFT 0x0
#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
//GDS_ATOM_SIZE
#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
//GDS_ATOM_OFFSET0
#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
//GDS_ATOM_OFFSET1
#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
//GDS_ATOM_DST
#define GDS_ATOM_DST__DST__SHIFT 0x0
#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
//GDS_ATOM_OP
#define GDS_ATOM_OP__OP__SHIFT 0x0
#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
#define GDS_ATOM_OP__OP_MASK 0x000000FFL
#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
//GDS_ATOM_SRC0
#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_SRC0_U
#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_SRC1
#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_SRC1_U
#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_READ0
#define GDS_ATOM_READ0__DATA__SHIFT 0x0
#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_READ0_U
#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_READ1
#define GDS_ATOM_READ1__DATA__SHIFT 0x0
#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
//GDS_ATOM_READ1_U
#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
//GDS_GWS_RESOURCE_CNTL
#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
//GDS_GWS_RESOURCE
#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c
#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d
#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e
#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f
#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL
#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L
#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L
#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L
#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L
#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L
//GDS_GWS_RESOURCE_CNT
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
//GDS_OA_CNTL
#define GDS_OA_CNTL__INDEX__SHIFT 0x0
#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
//GDS_OA_COUNTER
#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
//GDS_OA_ADDRESS
#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L
#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L
#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L
#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
//GDS_OA_INCDEC
#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
//GDS_OA_RING_SIZE
#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
//SPI_CONFIG_CNTL
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
//SPI_CONFIG_CNTL_1
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L
//SPI_CONFIG_CNTL_2
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
// addressBlock: gc_perfddec
//CPG_PERFCOUNTER1_LO
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CPG_PERFCOUNTER1_HI
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CPG_PERFCOUNTER0_LO
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CPG_PERFCOUNTER0_HI
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CPC_PERFCOUNTER1_LO
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CPC_PERFCOUNTER1_HI
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CPC_PERFCOUNTER0_LO
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CPC_PERFCOUNTER0_HI
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CPF_PERFCOUNTER1_LO
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CPF_PERFCOUNTER1_HI
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CPF_PERFCOUNTER0_LO
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CPF_PERFCOUNTER0_HI
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CPF_LATENCY_STATS_DATA
#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
//CPG_LATENCY_STATS_DATA
#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
//CPC_LATENCY_STATS_DATA
#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
//GRBM_PERFCOUNTER0_LO
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GRBM_PERFCOUNTER0_HI
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GRBM_PERFCOUNTER1_LO
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GRBM_PERFCOUNTER1_HI
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GRBM_SE0_PERFCOUNTER_LO
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GRBM_SE0_PERFCOUNTER_HI
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GRBM_SE1_PERFCOUNTER_LO
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GRBM_SE1_PERFCOUNTER_HI
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GRBM_SE2_PERFCOUNTER_LO
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GRBM_SE2_PERFCOUNTER_HI
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GRBM_SE3_PERFCOUNTER_LO
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GRBM_SE3_PERFCOUNTER_HI
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER0_LO
#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER0_HI
#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER1_LO
#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER1_HI
#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER2_LO
#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER2_HI
#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER3_LO
#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//WD_PERFCOUNTER3_HI
#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER0_LO
#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER0_HI
#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER1_LO
#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER1_HI
#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER2_LO
#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER2_HI
#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER3_LO
#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//IA_PERFCOUNTER3_HI
#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER0_LO
#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER0_HI
#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER1_LO
#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER1_HI
#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER2_LO
#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER2_HI
#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER3_LO
#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//VGT_PERFCOUNTER3_HI
#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SU_PERFCOUNTER0_LO
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SU_PERFCOUNTER0_HI
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
//PA_SU_PERFCOUNTER1_LO
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SU_PERFCOUNTER1_HI
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
//PA_SU_PERFCOUNTER2_LO
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SU_PERFCOUNTER2_HI
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
//PA_SU_PERFCOUNTER3_LO
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SU_PERFCOUNTER3_HI
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
//PA_SC_PERFCOUNTER0_LO
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER0_HI
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER1_LO
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER1_HI
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER2_LO
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER2_HI
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER3_LO
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER3_HI
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER4_LO
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER4_HI
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER5_LO
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER5_HI
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER6_LO
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER6_HI
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER7_LO
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//PA_SC_PERFCOUNTER7_HI
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER0_HI
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER0_LO
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER1_HI
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER1_LO
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER2_HI
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER2_LO
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER3_HI
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER3_LO
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER4_HI
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER4_LO
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER5_HI
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SPI_PERFCOUNTER5_LO
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER0_LO
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER0_HI
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER1_LO
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER1_HI
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER2_LO
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER2_HI
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER3_LO
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER3_HI
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER4_LO
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER4_HI
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER5_LO
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER5_HI
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER6_LO
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER6_HI
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER7_LO
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER7_HI
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER8_LO
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER8_HI
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER9_LO
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER9_HI
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER10_LO
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER10_HI
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER11_LO
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER11_HI
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER12_LO
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER12_HI
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER13_LO
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER13_HI
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER14_LO
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER14_HI
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER15_LO
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SQ_PERFCOUNTER15_HI
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER0_LO
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER0_HI
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER1_LO
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER1_HI
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER2_LO
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER2_HI
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER3_LO
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//SX_PERFCOUNTER3_HI
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER0_LO
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER0_HI
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER1_LO
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER1_HI
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER2_LO
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER2_HI
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER3_LO
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//GDS_PERFCOUNTER3_HI
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TA_PERFCOUNTER0_LO
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TA_PERFCOUNTER0_HI
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TA_PERFCOUNTER1_LO
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TA_PERFCOUNTER1_HI
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TD_PERFCOUNTER0_LO
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TD_PERFCOUNTER0_HI
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TD_PERFCOUNTER1_LO
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TD_PERFCOUNTER1_HI
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER0_LO
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER0_HI
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER1_LO
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER1_HI
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER2_LO
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER2_HI
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER3_LO
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCP_PERFCOUNTER3_HI
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER0_LO
#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER0_HI
#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER1_LO
#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER1_HI
#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER2_LO
#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER2_HI
#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER3_LO
#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCC_PERFCOUNTER3_HI
#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER0_LO
#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER0_HI
#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER1_LO
#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER1_HI
#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER2_LO
#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER2_HI
#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER3_LO
#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//TCA_PERFCOUNTER3_HI
#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER0_LO
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER0_HI
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER1_LO
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER1_HI
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER2_LO
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER2_HI
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER3_LO
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//CB_PERFCOUNTER3_HI
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER0_LO
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER0_HI
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER1_LO
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER1_HI
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER2_LO
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER2_HI
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER3_LO
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//DB_PERFCOUNTER3_HI
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//RLC_PERFCOUNTER0_LO
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//RLC_PERFCOUNTER0_HI
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//RLC_PERFCOUNTER1_LO
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//RLC_PERFCOUNTER1_HI
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER0_LO
#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER0_HI
#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER1_LO
#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER1_HI
#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER2_LO
#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER2_HI
#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER3_LO
#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
//RMI_PERFCOUNTER3_HI
#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
// addressBlock: gc_utcl2_atcl2pfcntrdec
//ATC_L2_PERFCOUNTER_LO
#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
//ATC_L2_PERFCOUNTER_HI
#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
// addressBlock: gc_utcl2_vml2prdec
//MC_VM_L2_PERFCOUNTER_LO
#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
//MC_VM_L2_PERFCOUNTER_HI
#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
// addressBlock: gc_perfsdec
//CPG_PERFCOUNTER1_SELECT
#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
//CPG_PERFCOUNTER0_SELECT1
#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
//CPG_PERFCOUNTER0_SELECT
#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
//CPC_PERFCOUNTER1_SELECT
#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
//CPC_PERFCOUNTER0_SELECT1
#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
//CPF_PERFCOUNTER1_SELECT
#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
//CPF_PERFCOUNTER0_SELECT1
#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
//CPF_PERFCOUNTER0_SELECT
#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
//CP_PERFMON_CNTL
#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
//CPC_PERFCOUNTER0_SELECT
#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
//CPF_TC_PERF_COUNTER_WINDOW_SELECT
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
//CPG_TC_PERF_COUNTER_WINDOW_SELECT
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
//CPF_LATENCY_STATS_SELECT
#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
//CPG_LATENCY_STATS_SELECT
#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
//CPC_LATENCY_STATS_SELECT
#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L
#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
//CP_DRAW_OBJECT
#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
//CP_DRAW_OBJECT_COUNTER
#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
//CP_DRAW_WINDOW_MASK_HI
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
//CP_DRAW_WINDOW_HI
#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
//CP_DRAW_WINDOW_LO
#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
//CP_DRAW_WINDOW_CNTL
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
//GRBM_PERFCOUNTER0_SELECT
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
//GRBM_PERFCOUNTER1_SELECT
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
//GRBM_SE0_PERFCOUNTER_SELECT
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
//GRBM_SE1_PERFCOUNTER_SELECT
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
//GRBM_SE2_PERFCOUNTER_SELECT
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
//GRBM_SE3_PERFCOUNTER_SELECT
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
//WD_PERFCOUNTER0_SELECT
#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//WD_PERFCOUNTER1_SELECT
#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//WD_PERFCOUNTER2_SELECT
#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//WD_PERFCOUNTER3_SELECT
#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//IA_PERFCOUNTER0_SELECT
#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//IA_PERFCOUNTER1_SELECT
#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//IA_PERFCOUNTER2_SELECT
#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//IA_PERFCOUNTER3_SELECT
#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//IA_PERFCOUNTER0_SELECT1
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//VGT_PERFCOUNTER0_SELECT
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//VGT_PERFCOUNTER1_SELECT
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//VGT_PERFCOUNTER2_SELECT
#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//VGT_PERFCOUNTER3_SELECT
#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//VGT_PERFCOUNTER0_SELECT1
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//VGT_PERFCOUNTER1_SELECT1
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
//VGT_PERFCOUNTER_SEID_MASK
#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL
//PA_SU_PERFCOUNTER0_SELECT
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
//PA_SU_PERFCOUNTER0_SELECT1
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
//PA_SU_PERFCOUNTER1_SELECT
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
//PA_SU_PERFCOUNTER1_SELECT1
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
//PA_SU_PERFCOUNTER2_SELECT
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
//PA_SU_PERFCOUNTER3_SELECT
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
//PA_SC_PERFCOUNTER0_SELECT
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
//PA_SC_PERFCOUNTER0_SELECT1
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
//PA_SC_PERFCOUNTER1_SELECT
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
//PA_SC_PERFCOUNTER2_SELECT
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
//PA_SC_PERFCOUNTER3_SELECT
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
//PA_SC_PERFCOUNTER4_SELECT
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
//PA_SC_PERFCOUNTER5_SELECT
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
//PA_SC_PERFCOUNTER6_SELECT
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
//PA_SC_PERFCOUNTER7_SELECT
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
//SPI_PERFCOUNTER0_SELECT
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//SPI_PERFCOUNTER1_SELECT
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//SPI_PERFCOUNTER2_SELECT
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//SPI_PERFCOUNTER3_SELECT
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//SPI_PERFCOUNTER0_SELECT1
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SPI_PERFCOUNTER1_SELECT1
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SPI_PERFCOUNTER2_SELECT1
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SPI_PERFCOUNTER3_SELECT1
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
//SPI_PERFCOUNTER4_SELECT
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL
//SPI_PERFCOUNTER5_SELECT
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL
//SPI_PERFCOUNTER_BINS
#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
//SQ_PERFCOUNTER0_SELECT
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER1_SELECT
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER2_SELECT
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER3_SELECT
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER4_SELECT
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER5_SELECT
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER6_SELECT
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER7_SELECT
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER8_SELECT
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER9_SELECT
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER10_SELECT
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER11_SELECT
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER12_SELECT
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER13_SELECT
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER14_SELECT
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER15_SELECT
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
//SQ_PERFCOUNTER_CTRL
#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
//SQ_PERFCOUNTER_MASK
#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL
#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L
//SQ_PERFCOUNTER_CTRL2
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
//SX_PERFCOUNTER0_SELECT
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
//SX_PERFCOUNTER1_SELECT
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
//SX_PERFCOUNTER2_SELECT
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
//SX_PERFCOUNTER3_SELECT
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
//SX_PERFCOUNTER0_SELECT1
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
//SX_PERFCOUNTER1_SELECT1
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
//GDS_PERFCOUNTER0_SELECT
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
//GDS_PERFCOUNTER1_SELECT
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
//GDS_PERFCOUNTER2_SELECT
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
//GDS_PERFCOUNTER3_SELECT
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
//GDS_PERFCOUNTER0_SELECT1
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
//TA_PERFCOUNTER0_SELECT
#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//TA_PERFCOUNTER0_SELECT1
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//TA_PERFCOUNTER1_SELECT
#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//TD_PERFCOUNTER0_SELECT
#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//TD_PERFCOUNTER0_SELECT1
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//TD_PERFCOUNTER1_SELECT
#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//TCP_PERFCOUNTER0_SELECT
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//TCP_PERFCOUNTER0_SELECT1
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//TCP_PERFCOUNTER1_SELECT
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//TCP_PERFCOUNTER1_SELECT1
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
//TCP_PERFCOUNTER2_SELECT
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//TCP_PERFCOUNTER3_SELECT
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//TCC_PERFCOUNTER0_SELECT
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//TCC_PERFCOUNTER0_SELECT1
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
//TCC_PERFCOUNTER1_SELECT
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//TCC_PERFCOUNTER1_SELECT1
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
//TCC_PERFCOUNTER2_SELECT
#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//TCC_PERFCOUNTER3_SELECT
#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//TCA_PERFCOUNTER0_SELECT
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//TCA_PERFCOUNTER0_SELECT1
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
//TCA_PERFCOUNTER1_SELECT
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//TCA_PERFCOUNTER1_SELECT1
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
//TCA_PERFCOUNTER2_SELECT
#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//TCA_PERFCOUNTER3_SELECT
#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//CB_PERFCOUNTER_FILTER
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
//CB_PERFCOUNTER0_SELECT
#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//CB_PERFCOUNTER0_SELECT1
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//CB_PERFCOUNTER1_SELECT
#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//CB_PERFCOUNTER2_SELECT
#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//CB_PERFCOUNTER3_SELECT
#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//DB_PERFCOUNTER0_SELECT
#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//DB_PERFCOUNTER0_SELECT1
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//DB_PERFCOUNTER1_SELECT
#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//DB_PERFCOUNTER1_SELECT1
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
//DB_PERFCOUNTER2_SELECT
#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//DB_PERFCOUNTER3_SELECT
#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//RLC_SPM_PERFMON_CNTL
#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
//RLC_SPM_PERFMON_RING_BASE_LO
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
//RLC_SPM_PERFMON_RING_BASE_HI
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
//RLC_SPM_PERFMON_RING_SIZE
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
//RLC_SPM_PERFMON_SEGMENT_SIZE
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
//RLC_SPM_SE_MUXSEL_ADDR
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
//RLC_SPM_SE_MUXSEL_DATA
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_CB_PERFMON_SAMPLE_DELAY
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_DB_PERFMON_SAMPLE_DELAY
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_PA_PERFMON_SAMPLE_DELAY
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_IA_PERFMON_SAMPLE_DELAY
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_SC_PERFMON_SAMPLE_DELAY
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_TA_PERFMON_SAMPLE_DELAY
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_TD_PERFMON_SAMPLE_DELAY
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_SX_PERFMON_SAMPLE_DELAY
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_GLOBAL_MUXSEL_ADDR
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
//RLC_SPM_GLOBAL_MUXSEL_DATA
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
//RLC_SPM_RING_RDPTR
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
//RLC_SPM_SEGMENT_THRESHOLD
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL
//RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
//RLC_PERFMON_CLK_CNTL
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
//RLC_PERFMON_CNTL
#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
//RLC_PERFCOUNTER0_SELECT
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
//RLC_PERFCOUNTER1_SELECT
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
//RLC_GPU_IOV_PERF_CNT_CNTL
#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
//RLC_GPU_IOV_PERF_CNT_WR_ADDR
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
//RLC_GPU_IOV_PERF_CNT_WR_DATA
#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL
//RLC_GPU_IOV_PERF_CNT_RD_ADDR
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
//RLC_GPU_IOV_PERF_CNT_RD_DATA
#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL
//RMI_PERFCOUNTER0_SELECT
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
//RMI_PERFCOUNTER0_SELECT1
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
//RMI_PERFCOUNTER1_SELECT
#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
//RMI_PERFCOUNTER2_SELECT
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
//RMI_PERFCOUNTER2_SELECT1
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
//RMI_PERFCOUNTER3_SELECT
#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
//RMI_PERF_COUNTER_CNTL
#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
// addressBlock: gc_utcl2_atcl2pfcntldec
//ATC_L2_PERFCOUNTER0_CFG
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
//ATC_L2_PERFCOUNTER1_CFG
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
//ATC_L2_PERFCOUNTER_RSLT_CNTL
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
// addressBlock: gc_utcl2_vml2pldec
//MC_VM_L2_PERFCOUNTER0_CFG
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER1_CFG
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER2_CFG
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER3_CFG
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER4_CFG
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER5_CFG
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER6_CFG
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER7_CFG
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
// addressBlock: gc_rlcpdec
//RLC_CNTL
#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
#define RLC_CNTL__RESERVED__SHIFT 0x4
#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
//RLC_STAT
#define RLC_STAT__RLC_BUSY__SHIFT 0x0
#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3
#define RLC_STAT__MC_BUSY__SHIFT 0x4
#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
#define RLC_STAT__RESERVED__SHIFT 0x8
#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L
#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L
#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L
#define RLC_STAT__MC_BUSY_MASK 0x00000010L
#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
//RLC_SAFE_MODE
#define RLC_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
//RLC_MEM_SLP_CNTL
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
//SMU_RLC_RESPONSE
#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
//RLC_RLCV_SAFE_MODE
#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
//RLC_SMU_SAFE_MODE
#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L
#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL
#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L
#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L
#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
//RLC_RLCV_COMMAND
#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
//RLC_REFCLOCK_TIMESTAMP_LSB
#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
//RLC_REFCLOCK_TIMESTAMP_MSB
#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
//RLC_GPM_TIMER_INT_0
#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
//RLC_GPM_TIMER_INT_1
#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
//RLC_GPM_TIMER_INT_2
#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
//RLC_GPM_TIMER_CTRL
#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4
#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L
//RLC_LB_CNTR_MAX
#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL
//RLC_GPM_TIMER_STAT
#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4
#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L
//RLC_GPM_TIMER_INT_3
#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
//RLC_SERDES_WR_NONCU_MASTER_MASK_1
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L
//RLC_SERDES_NONCU_MASTER_BUSY_1
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0
#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10
#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11
#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12
#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17
#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18
#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL
#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L
#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L
//RLC_INT_STAT
#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
#define RLC_INT_STAT__RESERVED__SHIFT 0x9
#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
//RLC_LB_CNTL
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L
#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L
//RLC_MGCG_CTRL
#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
//RLC_LB_CNTR_INIT
#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL
//RLC_LOAD_BALANCE_CNTR
#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
//RLC_JUMP_TABLE_RESTORE
#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
//RLC_PG_DELAY_2
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L
//RLC_GPU_CLOCK_COUNT_LSB
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_MSB
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
//RLC_CAPTURE_GPU_CLOCK_COUNT
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
//RLC_UCODE_CNTL
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
//RLC_GPM_THREAD_RESET
#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
//RLC_GPM_CP_DMA_COMPLETE_T0
#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
//RLC_GPM_CP_DMA_COMPLETE_T1
#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
//RLC_FIREWALL_VIOLATION
#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0
#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL
//RLC_GPM_STAT
#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
#define RLC_GPM_STAT__RESERVED__SHIFT 0x17
#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L
#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L
#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L
#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L
#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
//RLC_GPU_CLOCK_32_RES_SEL
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
//RLC_GPU_CLOCK_32
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
//RLC_PG_CNTL
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L
#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L
//RLC_GPM_THREAD_PRIORITY
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
//RLC_GPM_THREAD_ENABLE
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
//RLC_CGTT_MGCG_OVERRIDE
#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0
#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8
#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L
#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L
//RLC_CGCG_CGLS_CTRL
#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
//RLC_CGCG_RAMP_CTRL
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
//RLC_DYN_PG_STATUS
#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
//RLC_DYN_PG_REQUEST
#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL
//RLC_PG_DELAY
#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
//RLC_CU_STATUS
#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
//RLC_LB_INIT_CU_MASK
#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL
//RLC_LB_ALWAYS_ACTIVE_CU_MASK
#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL
//RLC_LB_PARAMS
#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
//RLC_THREAD1_DELAY
#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL
#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L
//RLC_PG_ALWAYS_ON_CU_MASK
#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL
//RLC_MAX_PG_CU
#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL
#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L
//RLC_AUTO_PG_CTRL
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
//RLC_SMU_GRBM_REG_SAVE_CTRL
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL
//RLC_SERDES_RD_MASTER_INDEX
#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc
#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd
#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11
#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13
#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL
#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L
#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L
#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L
#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L
//RLC_SERDES_RD_DATA_0
#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
//RLC_SERDES_RD_DATA_1
#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
//RLC_SERDES_RD_DATA_2
#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
//RLC_SERDES_WR_CU_MASTER_MASK
#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL
//RLC_SERDES_WR_NONCU_MASTER_MASK
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19
#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L
#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L
//RLC_SERDES_WR_CTRL
#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL
#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L
#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L
#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L
#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L
#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L
#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L
//RLC_SERDES_WR_DATA
#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL
//RLC_SERDES_CU_MASTER_BUSY
#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL
//RLC_SERDES_NONCU_MASTER_BUSY
#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18
#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19
#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a
#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L
#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L
#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L
#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L
#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L
#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L
//RLC_GPM_GENERAL_0
#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_1
#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_2
#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_3
#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_4
#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_5
#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_6
#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_7
#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_SCRATCH_ADDR
#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
//RLC_GPM_SCRATCH_DATA
#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
//RLC_STATIC_PG_STATUS
#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
//RLC_SPM_MC_CNTL
#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5
#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8
#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L
#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L
#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L
#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L
//RLC_SPM_INT_CNTL
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
//RLC_SPM_INT_STATUS
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
//RLC_SMU_MESSAGE
#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL
//RLC_GPM_LOG_SIZE
#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
//RLC_PG_DELAY_3
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
//RLC_GPR_REG1
#define RLC_GPR_REG1__DATA__SHIFT 0x0
#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
//RLC_GPR_REG2
#define RLC_GPR_REG2__DATA__SHIFT 0x0
#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_LOG_CONT
#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
//RLC_GPM_INT_DISABLE_TH0
#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
//RLC_GPM_INT_DISABLE_TH1
#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL
//RLC_GPM_INT_FORCE_TH0
#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
//RLC_GPM_INT_FORCE_TH1
#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL
//RLC_SRM_CNTL
#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
//RLC_SRM_ARAM_ADDR
#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
//RLC_SRM_ARAM_DATA
#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_DRAM_ADDR
#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
//RLC_SRM_DRAM_DATA
#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_GPM_COMMAND
#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L
#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
//RLC_SRM_GPM_COMMAND_STATUS
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
//RLC_SRM_RLCV_COMMAND
#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
//RLC_SRM_RLCV_COMMAND_STATUS
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
//RLC_SRM_INDEX_CNTL_ADDR_0
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_1
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_2
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_3
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_4
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_5
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_6
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_7
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
//RLC_SRM_INDEX_CNTL_DATA_0
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_1
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_2
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_3
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_4
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_5
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_6
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_7
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
//RLC_SRM_STAT
#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
//RLC_SRM_GPM_ABORT
#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
//RLC_CSIB_ADDR_LO
#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
//RLC_CSIB_ADDR_HI
#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
//RLC_CSIB_LENGTH
#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
//RLC_SMU_COMMAND
#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL
//RLC_CP_SCHEDULERS
#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
//RLC_SMU_ARGUMENT_1
#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL
//RLC_SMU_ARGUMENT_2
#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_8
#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_9
#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_10
#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_11
#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_GENERAL_12
#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_UTCL1_CNTL_0
#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
//RLC_GPM_UTCL1_CNTL_1
#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
//RLC_GPM_UTCL1_CNTL_2
#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
//RLC_SPM_UTCL1_CNTL
#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
//RLC_UTCL1_STATUS_2
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
//RLC_LB_THR_CONFIG_2
#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0
#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL
//RLC_LB_THR_CONFIG_3
#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0
#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL
//RLC_LB_THR_CONFIG_4
#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0
#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL
//RLC_SPM_UTCL1_ERROR_1
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
//RLC_SPM_UTCL1_ERROR_2
#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
//RLC_GPM_UTCL1_TH0_ERROR_1
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
//RLC_LB_THR_CONFIG_1
#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0
#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL
//RLC_GPM_UTCL1_TH0_ERROR_2
#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
//RLC_GPM_UTCL1_TH1_ERROR_1
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
//RLC_GPM_UTCL1_TH1_ERROR_2
#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
//RLC_GPM_UTCL1_TH2_ERROR_1
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
//RLC_GPM_UTCL1_TH2_ERROR_2
#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
//RLC_CGCG_CGLS_CTRL_3D
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c
#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d
#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L
#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L
#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L
//RLC_CGCG_RAMP_CTRL_3D
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L
//RLC_SEMAPHORE_0
#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
//RLC_SEMAPHORE_1
#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
//RLC_CP_EOF_INT
#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
//RLC_CP_EOF_INT_CNT
#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
//RLC_SPARE_INT
#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
//RLC_PREWALKER_UTCL1_CNTL
#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
//RLC_PREWALKER_UTCL1_TRIG
#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
//RLC_PREWALKER_UTCL1_ADDR_LSB
#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
//RLC_PREWALKER_UTCL1_ADDR_MSB
#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
//RLC_PREWALKER_UTCL1_SIZE_LSB
#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
//RLC_PREWALKER_UTCL1_SIZE_MSB
#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
//RLC_DSM_TRIG
//RLC_UTCL1_STATUS
#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
//RLC_R2I_CNTL_0
#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
//RLC_R2I_CNTL_1
#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
//RLC_R2I_CNTL_2
#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
//RLC_R2I_CNTL_3
#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
//RLC_UTCL2_CNTL
#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1
#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL
//RLC_LBPW_CU_STAT
#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0
#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10
#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL
#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L
//RLC_DS_CNTL
#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0
#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1
#define RLC_DS_CNTL__RESRVED__SHIFT 0x2
#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10
#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11
#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12
#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L
#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L
#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL
#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L
#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L
#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L
//RLC_RLCV_SPARE_INT
#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
// addressBlock: gc_pwrdec
//CGTS_SM_CTRL_REG
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L
//CGTS_RD_CTRL_REG
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL
#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L
//CGTS_RD_REG
#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL
//CGTS_TCC_DISABLE
#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
//CGTS_USER_TCC_DISABLE
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
//CGTS_CU0_SP0_CTRL_REG
#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU0_LDS_SQ_CTRL_REG
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU0_TA_SQC_CTRL_REG
#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU0_SP1_CTRL_REG
#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU0_TD_TCP_CTRL_REG
#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU1_SP0_CTRL_REG
#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU1_LDS_SQ_CTRL_REG
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU1_TA_SQC_CTRL_REG
#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU1_SP1_CTRL_REG
#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU1_TD_TCP_CTRL_REG
#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU2_SP0_CTRL_REG
#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU2_LDS_SQ_CTRL_REG
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU2_TA_SQC_CTRL_REG
#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU2_SP1_CTRL_REG
#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU2_TD_TCP_CTRL_REG
#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU3_SP0_CTRL_REG
#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU3_LDS_SQ_CTRL_REG
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU3_TA_SQC_CTRL_REG
#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU3_SP1_CTRL_REG
#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU3_TD_TCP_CTRL_REG
#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU4_SP0_CTRL_REG
#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU4_LDS_SQ_CTRL_REG
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU4_TA_SQC_CTRL_REG
#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU4_SP1_CTRL_REG
#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU4_TD_TCP_CTRL_REG
#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU5_SP0_CTRL_REG
#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU5_LDS_SQ_CTRL_REG
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU5_TA_SQC_CTRL_REG
#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU5_SP1_CTRL_REG
#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU5_TD_TCP_CTRL_REG
#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU6_SP0_CTRL_REG
#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU6_LDS_SQ_CTRL_REG
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU6_TA_SQC_CTRL_REG
#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU6_SP1_CTRL_REG
#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU6_TD_TCP_CTRL_REG
#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU7_SP0_CTRL_REG
#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU7_LDS_SQ_CTRL_REG
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU7_TA_SQC_CTRL_REG
#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU7_SP1_CTRL_REG
#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU7_TD_TCP_CTRL_REG
#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU8_SP0_CTRL_REG
#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU8_LDS_SQ_CTRL_REG
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU8_TA_SQC_CTRL_REG
#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU8_SP1_CTRL_REG
#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU8_TD_TCP_CTRL_REG
#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU9_SP0_CTRL_REG
#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU9_LDS_SQ_CTRL_REG
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU9_TA_SQC_CTRL_REG
#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU9_SP1_CTRL_REG
#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU9_TD_TCP_CTRL_REG
#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU10_SP0_CTRL_REG
#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU10_LDS_SQ_CTRL_REG
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU10_TA_SQC_CTRL_REG
#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU10_SP1_CTRL_REG
#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU10_TD_TCP_CTRL_REG
#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU11_SP0_CTRL_REG
#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU11_LDS_SQ_CTRL_REG
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU11_TA_SQC_CTRL_REG
#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU11_SP1_CTRL_REG
#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU11_TD_TCP_CTRL_REG
#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU12_SP0_CTRL_REG
#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU12_LDS_SQ_CTRL_REG
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU12_TA_SQC_CTRL_REG
#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU12_SP1_CTRL_REG
#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU12_TD_TCP_CTRL_REG
#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU13_SP0_CTRL_REG
#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU13_LDS_SQ_CTRL_REG
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU13_TA_SQC_CTRL_REG
#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU13_SP1_CTRL_REG
#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU13_TD_TCP_CTRL_REG
#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU14_SP0_CTRL_REG
#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU14_LDS_SQ_CTRL_REG
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU14_TA_SQC_CTRL_REG
#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
//CGTS_CU14_SP1_CTRL_REG
#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU14_TD_TCP_CTRL_REG
#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU15_SP0_CTRL_REG
#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL
#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L
#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU15_LDS_SQ_CTRL_REG
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU15_TA_SQC_CTRL_REG
#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU15_SP1_CTRL_REG
#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL
#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L
#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU15_TD_TCP_CTRL_REG
#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
//CGTS_CU0_TCPI_CTRL_REG
#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU1_TCPI_CTRL_REG
#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU2_TCPI_CTRL_REG
#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU3_TCPI_CTRL_REG
#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU4_TCPI_CTRL_REG
#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU5_TCPI_CTRL_REG
#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU6_TCPI_CTRL_REG
#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU7_TCPI_CTRL_REG
#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU8_TCPI_CTRL_REG
#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU9_TCPI_CTRL_REG
#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU10_TCPI_CTRL_REG
#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU11_TCPI_CTRL_REG
#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU12_TCPI_CTRL_REG
#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU13_TCPI_CTRL_REG
#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU14_TCPI_CTRL_REG
#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTS_CU15_TCPI_CTRL_REG
#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
//CGTT_SPI_CLK_CTRL
#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_PC_CLK_CTRL
#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_BCI_CLK_CTRL
#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_VGT_CLK_CTRL
#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x10
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_IA_CLK_CTRL
#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_WD_CLK_CTRL
#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x10
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_PA_CLK_CTRL
#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x17
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x00800000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
//CGTT_SC_CLK_CTRL0
#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
//CGTT_SC_CLK_CTRL1
#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
//CGTT_SQ_CLK_CTRL
#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//CGTT_SQG_CLK_CTRL
#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
//SQ_ALU_CLK_CTRL
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
//SQ_TEX_CLK_CTRL
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
//SQ_LDS_CLK_CTRL
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
//SQ_POWER_THROTTLE
#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL
#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L
#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L
//SQ_POWER_THROTTLE2
#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
//CGTT_SX_CLK_CTRL0
#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_SX_CLK_CTRL1
#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SX_CLK_CTRL1__DBG_EN_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_SX_CLK_CTRL2
#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SX_CLK_CTRL2__DBG_EN_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_SX_CLK_CTRL3
#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SX_CLK_CTRL3__DBG_EN_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_SX_CLK_CTRL4
#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_SX_CLK_CTRL4__DBG_EN_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
//TD_CGTT_CTRL
#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//TA_CGTT_CTRL
#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_TCPI_CLK_CTRL
#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_TCI_CLK_CTRL
#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_GDS_CLK_CTRL
#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//DB_CGTT_CLK_CTRL_0
#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
//CB_CGTT_SCLK_CTRL
#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//TCC_CGTT_SCLK_CTRL
#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//TCA_CGTT_SCLK_CTRL
#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_CP_CLK_CTRL
#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
//CGTT_CPF_CLK_CTRL
#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
//CGTT_CPC_CLK_CTRL
#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
//CGTT_RLC_CLK_CTRL
#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
//RLC_GFX_RM_CNTL
#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
//RMI_CGTT_SCLK_CTRL
#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//CGTT_TCPF_CLK_CTRL
#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
// addressBlock: gc_ea_pwrdec
//GCEA_CGTT_CLK_CTRL
#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
// addressBlock: gc_utcl2_vmsharedhvdec
//MC_VM_FB_SIZE_OFFSET_VF0
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF1
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF2
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF3
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF4
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF5
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF6
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF7
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF8
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF9
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF10
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF11
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF12
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF13
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF14
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
//MC_VM_FB_SIZE_OFFSET_VF15
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
//VM_IOMMU_MMIO_CNTRL_1
#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
//MC_VM_MARC_BASE_LO_0
#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
//MC_VM_MARC_BASE_LO_1
#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
//MC_VM_MARC_BASE_LO_2
#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
//MC_VM_MARC_BASE_LO_3
#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
//MC_VM_MARC_BASE_HI_0
#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
//MC_VM_MARC_BASE_HI_1
#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
//MC_VM_MARC_BASE_HI_2
#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
//MC_VM_MARC_BASE_HI_3
#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
//MC_VM_MARC_RELOC_LO_0
#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
//MC_VM_MARC_RELOC_LO_1
#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
//MC_VM_MARC_RELOC_LO_2
#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
//MC_VM_MARC_RELOC_LO_3
#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
//MC_VM_MARC_RELOC_HI_0
#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
//MC_VM_MARC_RELOC_HI_1
#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
//MC_VM_MARC_RELOC_HI_2
#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
//MC_VM_MARC_RELOC_HI_3
#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
//MC_VM_MARC_LEN_LO_0
#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
//MC_VM_MARC_LEN_LO_1
#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
//MC_VM_MARC_LEN_LO_2
#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
//MC_VM_MARC_LEN_LO_3
#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
//MC_VM_MARC_LEN_HI_0
#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
//MC_VM_MARC_LEN_HI_1
#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
//MC_VM_MARC_LEN_HI_2
#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
//MC_VM_MARC_LEN_HI_3
#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
//VM_IOMMU_CONTROL_REGISTER
#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
//VM_PCIE_ATS_CNTL
#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_0
#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_1
#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_2
#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_3
#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_4
#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_5
#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_6
#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_7
#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_8
#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_9
#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_10
#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_11
#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_12
#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_13
#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_14
#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
//VM_PCIE_ATS_CNTL_VF_15
#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
//UTCL2_CGTT_CLK_CTRL
#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
// addressBlock: gc_hypdec
//CP_HYP_PFP_UCODE_ADDR
#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
//CP_PFP_UCODE_ADDR
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
//CP_HYP_PFP_UCODE_DATA
#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_PFP_UCODE_DATA
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_HYP_ME_UCODE_ADDR
#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL
//CP_ME_RAM_RADDR
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL
//CP_ME_RAM_WADDR
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL
//CP_HYP_ME_UCODE_DATA
#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_ME_RAM_DATA
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
//CP_CE_UCODE_ADDR
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
//CP_HYP_CE_UCODE_ADDR
#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
//CP_CE_UCODE_DATA
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_HYP_CE_UCODE_DATA
#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_HYP_MEC1_UCODE_ADDR
#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
//CP_MEC_ME1_UCODE_ADDR
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
//CP_HYP_MEC1_UCODE_DATA
#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_MEC_ME1_UCODE_DATA
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_HYP_MEC2_UCODE_ADDR
#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
//CP_MEC_ME2_UCODE_ADDR
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
//CP_HYP_MEC2_UCODE_DATA
#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//CP_MEC_ME2_UCODE_DATA
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//RLC_GPM_UCODE_ADDR
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
//RLC_GPM_UCODE_DATA
#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//GRBM_GFX_INDEX_SR_SELECT
#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
//GRBM_GFX_INDEX_SR_DATA
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8
#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L
#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
//GRBM_GFX_CNTL_SR_SELECT
#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
//GRBM_GFX_CNTL_SR_DATA
#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
//GRBM_CAM_INDEX
#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
//GRBM_HYP_CAM_INDEX
#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
//GRBM_CAM_DATA
#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
//GRBM_HYP_CAM_DATA
#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
//RLC_GPU_IOV_VF_ENABLE
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
//RLC_GPU_IOV_CFG_REG6
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
//RLC_GPU_IOV_CFG_REG8
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
//RLC_RLCV_TIMER_INT_0
#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
//RLC_RLCV_TIMER_CTRL
#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1
#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL
//RLC_RLCV_TIMER_STAT
#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1
#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL
//RLC_GPU_IOV_VF_DOORBELL_STATUS
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
//RLC_GPU_IOV_VF_MASK
#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL
#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L
//RLC_HYP_SEMAPHORE_2
#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
//RLC_HYP_SEMAPHORE_3
#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
//RLC_CLK_CNTL
#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1
#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2
#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L
#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L
#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL
//RLC_GPU_IOV_SCH_BLOCK
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
//RLC_GPU_IOV_CFG_REG1
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
//RLC_GPU_IOV_CFG_REG2
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
//RLC_GPU_IOV_VM_BUSY_STATUS
#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_SCH_0
#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_ACTIVE_FCN_ID
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
//RLC_GPU_IOV_SCH_3
#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_SCH_1
#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_SCH_2
#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_UCODE_ADDR
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
//RLC_GPU_IOV_UCODE_DATA
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_SCRATCH_ADDR
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
//RLC_GPU_IOV_SCRATCH_DATA
#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_F32_CNTL
#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL
//RLC_GPU_IOV_F32_RESET
#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL
//RLC_GPU_IOV_SDMA0_STATUS
#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL
#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L
#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L
//RLC_GPU_IOV_SDMA1_STATUS
#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL
#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L
#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L
//RLC_GPU_IOV_SMU_RESPONSE
#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_VIRT_RESET_REQ
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
//RLC_GPU_IOV_RLC_RESPONSE
#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_INT_DISABLE
#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_INT_FORCE
#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA0_BUSY_STATUS
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA1_BUSY_STATUS
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
// addressBlock: gccacind
//GC_CAC_CNTL
#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f
#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L
//GC_CAC_OVR_SEL
#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
//GC_CAC_OVR_VAL
#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
//GC_CAC_WEIGHT_BCI_0
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CB_0
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CB_1
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CBR_0
#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CBR_1
#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CP_0
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CP_1
#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_DB_0
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_DB_1
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_DBR_0
#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_DBR_1
#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_GDS_0
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_GDS_1
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_IA_0
#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_LDS_0
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_LDS_1
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_PA_0
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_PC_0
#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SC_0
#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SPI_0
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SPI_1
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SPI_2
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SQ_0
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SQ_1
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SQ_2
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SQ_3
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SQ_4
#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0
#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SX_0
#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_SXRB_0
#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TA_0
#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TCC_0
#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TCC_1
#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TCC_2
#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TCP_0
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TCP_1
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TCP_2
#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TD_0
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TD_1
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_TD_2
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_VGT_0
#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_VGT_1
#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_WD_0
#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10
#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_0
#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_1
#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_2
#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_3
#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_4
#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_5
#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_6
#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_CU_7
#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT 0x0
#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT 0x10
#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK 0xFFFF0000L
//GC_CAC_ACC_BCI0
#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CB0
#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CB1
#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CB2
#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CB3
#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CBR0
#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CBR1
#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CBR2
#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CBR3
#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CP0
#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CP1
#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CP2
#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DB0
#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DB1
#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DB2
#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DB3
#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DBR0
#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DBR1
#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DBR2
#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_DBR3
#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_GDS0
#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_GDS1
#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_GDS2
#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_GDS3
#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_IA0
#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_LDS0
#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_LDS1
#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_LDS2
#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_LDS3
#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_PA0
#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_PA1
#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_PC0
#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SC0
#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SPI0
#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SPI1
#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SPI2
#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SPI3
#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SPI4
#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SPI5
#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_WEIGHT_UTCL2_ATCL2_0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
//GC_CAC_ACC_EA0
#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_EA1
#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_EA2
#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_EA3
#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL20
#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_OVRD_EA
#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
//GC_CAC_OVRD_UTCL2_ATCL2
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
//GC_CAC_WEIGHT_EA_0
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_EA_1
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_RMI_0
#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10
#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L
//GC_CAC_ACC_RMI0
#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_OVRD_RMI
#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_WEIGHT_UTCL2_ATCL2_1
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
//GC_CAC_ACC_UTCL2_ATCL21
#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL22
#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL23
#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_EA4
#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_EA5
#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_WEIGHT_EA_2
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
//GC_CAC_ACC_SQ0_LOWER
#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ0_UPPER
#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ1_LOWER
#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ1_UPPER
#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ2_LOWER
#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ2_UPPER
#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ3_LOWER
#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ3_UPPER
#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ4_LOWER
#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ4_UPPER
#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ5_LOWER
#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ5_UPPER
#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ6_LOWER
#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ6_UPPER
#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ7_LOWER
#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ7_UPPER
#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SQ8_LOWER
#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SQ8_UPPER
#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8
#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L
//GC_CAC_ACC_SX0
#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SXRB0
#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_SXRB1
#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TA0
#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCC0
#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCC1
#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCC2
#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCC3
#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCC4
#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCP0
#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCP1
#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCP2
#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCP3
#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TCP4
#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TD0
#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TD1
#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TD2
#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TD3
#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TD4
#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_TD5
#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_VGT0
#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_VGT1
#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_VGT2
#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_WD0
#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU0
#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU1
#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU2
#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU3
#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU4
#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU5
#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU6
#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU7
#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU8
#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU9
#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU10
#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU11
#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU12
#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU13
#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU14
#define GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_CU15
#define GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_OVRD_BCI
#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
//GC_CAC_OVRD_CB
#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
//GC_CAC_OVRD_CBR
#define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT 0x4
#define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK 0x0000000FL
#define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK 0x000000F0L
//GC_CAC_OVRD_CP
#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
//GC_CAC_OVRD_DB
#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
//GC_CAC_OVRD_DBR
#define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT 0x4
#define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK 0x0000000FL
#define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK 0x000000F0L
//GC_CAC_OVRD_GDS
#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
//GC_CAC_OVRD_IA
#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_LDS
#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
//GC_CAC_OVRD_PA
#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
//GC_CAC_OVRD_PC
#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_SC
#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_SPI
#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
//GC_CAC_OVRD_CU
#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_SQ
#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9
#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL
#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L
//GC_CAC_OVRD_SX
#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_SXRB
#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_TA
#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_OVRD_TCC
#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5
#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL
#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L
//GC_CAC_OVRD_TCP
#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
//GC_CAC_OVRD_TD
#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6
#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL
#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L
//GC_CAC_OVRD_VGT
#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3
#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L
#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L
//GC_CAC_OVRD_WD
#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1
#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L
#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L
//GC_CAC_ACC_BCI1
#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_WEIGHT_UTCL2_ATCL2_2
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_1
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_2
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_3
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_4
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_VML2_0
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_VML2_1
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_VML2_2
#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L
//GC_CAC_ACC_UTCL2_ATCL24
#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER0
#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER1
#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER2
#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER3
#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER4
#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER5
#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER6
#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER7
#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER8
#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER9
#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML20
#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML21
#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML22
#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML23
#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML24
#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_OVRD_UTCL2_ROUTER
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
//GC_CAC_OVRD_UTCL2_VML2
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
//GC_CAC_WEIGHT_UTCL2_WALKER_0
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_WALKER_1
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_WALKER_2
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L
//GC_CAC_ACC_UTCL2_WALKER0
#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER1
#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER2
#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER3
#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER4
#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
//GC_CAC_OVRD_UTCL2_WALKER
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
// addressBlock: secacind
//SE_CAC_CNTL
#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f
#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L
//SE_CAC_OVR_SEL
#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
//SE_CAC_OVR_VAL
#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
// addressBlock: sqind
//SQ_DEBUG_STS_GLOBAL
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004
#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010
//SQ_DEBUG_STS_LOCAL
#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18
#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19
#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a
#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L
#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L
#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L
#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L
#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L
#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
//SQ_WAVE_STATUS
#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L
#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L
#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L
#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
//SQ_WAVE_TRAPSTS
#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L
#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
//SQ_WAVE_HW_ID
#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL
#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L
#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L
#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L
#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L
#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L
#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L
//SQ_WAVE_GPR_ALLOC
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
//SQ_WAVE_LDS_ALLOC
#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
//SQ_WAVE_IB_STS
#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L
#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
//SQ_WAVE_PC_LO
#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
//SQ_WAVE_PC_HI
#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
//SQ_WAVE_INST_DW0
#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
//SQ_WAVE_INST_DW1
#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL
//SQ_WAVE_IB_DBG0
#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f
#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L
#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L
#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L
#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L
#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L
#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L
#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L
#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L
//SQ_WAVE_IB_DBG1
#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L
#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L
#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L
#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L
#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
//SQ_WAVE_FLUSH_IB
#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP0
#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP1
#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP2
#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP3
#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP4
#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP5
#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP6
#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP7
#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP8
#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP9
#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP10
#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP11
#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP12
#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP13
#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP14
#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_TTMP15
#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
//SQ_WAVE_M0
#define SQ_WAVE_M0__M0__SHIFT 0x0
#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
//SQ_WAVE_EXEC_LO
#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
//SQ_WAVE_EXEC_HI
#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
//SQ_INTERRUPT_WORD_AUTO_CTXID
#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0
#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1
#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2
#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3
#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4
#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5
#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6
#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7
#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L
#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L
//SQ_INTERRUPT_WORD_AUTO_HI
#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8
#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L
#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L
//SQ_INTERRUPT_WORD_AUTO_LO
#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0
#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1
#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3
#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4
#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5
#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6
#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7
#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L
#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L
#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L
#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L
#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L
#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L
#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L
#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L
#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L
//SQ_INTERRUPT_WORD_CMN_CTXID
#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L
#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L
//SQ_INTERRUPT_WORD_CMN_HI
#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8
#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L
#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L
//SQ_INTERRUPT_WORD_WAVE_CTXID
#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0
#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc
#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd
#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe
#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12
#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14
#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL
#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L
#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L
#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L
#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L
#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L
#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L
#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L
//SQ_INTERRUPT_WORD_WAVE_HI
#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0
#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4
#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8
#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL
#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L
#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L
#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L
//SQ_INTERRUPT_WORD_WAVE_LO
#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0
#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19
#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e
#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL
#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L
#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L
#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L
#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L
// addressBlock: didtind
//DIDT_SQ_CTRL0
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L
//DIDT_SQ_CTRL1
#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
//DIDT_SQ_CTRL2
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L
//DIDT_SQ_STALL_CTRL
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
//DIDT_SQ_TUNING_CTRL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
//DIDT_SQ_CTRL3
#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
//DIDT_SQ_STALL_PATTERN_1_2
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_SQ_STALL_PATTERN_3_4
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_SQ_STALL_PATTERN_5_6
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_SQ_STALL_PATTERN_7
#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_SQ_WEIGHT0_3
#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
//DIDT_SQ_WEIGHT4_7
#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
//DIDT_SQ_WEIGHT8_11
#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
//DIDT_SQ_EDC_CTRL
#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17
#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
//DIDT_SQ_EDC_THRESHOLD
#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
//DIDT_SQ_EDC_STALL_PATTERN_1_2
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_SQ_EDC_STALL_PATTERN_3_4
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_SQ_EDC_STALL_PATTERN_5_6
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_SQ_EDC_STALL_PATTERN_7
#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_SQ_EDC_STATUS
#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
//DIDT_SQ_EDC_STALL_DELAY_1
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x8
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x18
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x000000FFL
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x0000FF00L
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x00FF0000L
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0xFF000000L
//DIDT_SQ_EDC_STALL_DELAY_2
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x8
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x18
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x000000FFL
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x0000FF00L
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x00FF0000L
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0xFF000000L
//DIDT_SQ_EDC_STALL_DELAY_3
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x8
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT 0x18
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x000000FFL
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x0000FF00L
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x00FF0000L
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK 0xFF000000L
//DIDT_SQ_EDC_STALL_DELAY_4
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT 0x0
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT 0x8
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT 0x10
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT 0x18
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK 0x000000FFL
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK 0x0000FF00L
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK 0x00FF0000L
#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK 0xFF000000L
//DIDT_SQ_EDC_OVERFLOW
#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
//DIDT_SQ_EDC_ROLLING_POWER_DELTA
#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
//DIDT_DB_CTRL0
#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b
#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L
//DIDT_DB_CTRL1
#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
//DIDT_DB_CTRL2
#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L
//DIDT_DB_STALL_CTRL
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
//DIDT_DB_TUNING_CTRL
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
//DIDT_DB_STALL_AUTO_RELEASE_CTRL
#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
//DIDT_DB_CTRL3
#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
//DIDT_DB_STALL_PATTERN_1_2
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_DB_STALL_PATTERN_3_4
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_DB_STALL_PATTERN_5_6
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_DB_STALL_PATTERN_7
#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_DB_WEIGHT0_3
#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
//DIDT_DB_WEIGHT4_7
#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
//DIDT_DB_WEIGHT8_11
#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
//DIDT_DB_EDC_CTRL
#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17
#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
//DIDT_DB_EDC_THRESHOLD
#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
//DIDT_DB_EDC_STALL_PATTERN_1_2
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_DB_EDC_STALL_PATTERN_3_4
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_DB_EDC_STALL_PATTERN_5_6
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_DB_EDC_STALL_PATTERN_7
#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_DB_EDC_STATUS
#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
//DIDT_DB_EDC_STALL_DELAY_1
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x6
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xc
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0x12
#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000003FL
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000FC0L
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x0003F000L
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x00FC0000L
#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
//DIDT_DB_EDC_OVERFLOW
#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
//DIDT_DB_EDC_ROLLING_POWER_DELTA
#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
//DIDT_TD_CTRL0
#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b
#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L
//DIDT_TD_CTRL1
#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
//DIDT_TD_CTRL2
#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L
//DIDT_TD_STALL_CTRL
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
//DIDT_TD_TUNING_CTRL
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
//DIDT_TD_STALL_AUTO_RELEASE_CTRL
#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
//DIDT_TD_CTRL3
#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
//DIDT_TD_STALL_PATTERN_1_2
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_TD_STALL_PATTERN_3_4
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_TD_STALL_PATTERN_5_6
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_TD_STALL_PATTERN_7
#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_TD_WEIGHT0_3
#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
//DIDT_TD_WEIGHT4_7
#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
//DIDT_TD_WEIGHT8_11
#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
//DIDT_TD_EDC_CTRL
#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17
#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
//DIDT_TD_EDC_THRESHOLD
#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
//DIDT_TD_EDC_STALL_PATTERN_1_2
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_TD_EDC_STALL_PATTERN_3_4
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_TD_EDC_STALL_PATTERN_5_6
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_TD_EDC_STALL_PATTERN_7
#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_TD_EDC_STATUS
#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
//DIDT_TD_EDC_STALL_DELAY_1
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x8
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0x10
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x18
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x000000FFL
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x0000FF00L
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x00FF0000L
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0xFF000000L
//DIDT_TD_EDC_STALL_DELAY_2
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x8
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0x10
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x18
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x000000FFL
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x0000FF00L
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x00FF0000L
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0xFF000000L
//DIDT_TD_EDC_STALL_DELAY_3
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x8
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0x10
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT 0x18
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x000000FFL
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x0000FF00L
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x00FF0000L
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK 0xFF000000L
//DIDT_TD_EDC_STALL_DELAY_4
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT 0x0
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT 0x8
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14__SHIFT 0x10
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15__SHIFT 0x18
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK 0x000000FFL
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK 0x0000FF00L
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14_MASK 0x00FF0000L
#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15_MASK 0xFF000000L
//DIDT_TD_EDC_OVERFLOW
#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
//DIDT_TD_EDC_ROLLING_POWER_DELTA
#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
//DIDT_TCP_CTRL0
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L
//DIDT_TCP_CTRL1
#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
//DIDT_TCP_CTRL2
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L
//DIDT_TCP_STALL_CTRL
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
//DIDT_TCP_TUNING_CTRL
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
//DIDT_TCP_CTRL3
#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
//DIDT_TCP_STALL_PATTERN_1_2
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_TCP_STALL_PATTERN_3_4
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_TCP_STALL_PATTERN_5_6
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_TCP_STALL_PATTERN_7
#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_TCP_WEIGHT0_3
#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
//DIDT_TCP_WEIGHT4_7
#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
//DIDT_TCP_WEIGHT8_11
#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
//DIDT_TCP_EDC_CTRL
#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17
#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
//DIDT_TCP_EDC_THRESHOLD
#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
//DIDT_TCP_EDC_STALL_PATTERN_1_2
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_TCP_EDC_STALL_PATTERN_3_4
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_TCP_EDC_STALL_PATTERN_5_6
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_TCP_EDC_STALL_PATTERN_7
#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_TCP_EDC_STATUS
#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
//DIDT_TCP_EDC_STALL_DELAY_1
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x8
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x18
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x000000FFL
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x0000FF00L
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x00FF0000L
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0xFF000000L
//DIDT_TCP_EDC_STALL_DELAY_2
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x8
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x18
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x000000FFL
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x0000FF00L
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x00FF0000L
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0xFF000000L
//DIDT_TCP_EDC_STALL_DELAY_3
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x8
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT 0x18
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x000000FFL
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x0000FF00L
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x00FF0000L
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK 0xFF000000L
//DIDT_TCP_EDC_STALL_DELAY_4
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT 0x0
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT 0x8
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14__SHIFT 0x10
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15__SHIFT 0x18
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK 0x000000FFL
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK 0x0000FF00L
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14_MASK 0x00FF0000L
#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15_MASK 0xFF000000L
//DIDT_TCP_EDC_OVERFLOW
#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
//DIDT_TCP_EDC_ROLLING_POWER_DELTA
#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
//DIDT_DBR_CTRL0
#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b
#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L
//DIDT_DBR_CTRL1
#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL
#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L
//DIDT_DBR_CTRL2
#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L
#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L
#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L
//DIDT_DBR_STALL_CTRL
#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18
#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
//DIDT_DBR_TUNING_CTRL
#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
//DIDT_DBR_STALL_AUTO_RELEASE_CTRL
#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
//DIDT_DBR_CTRL3
#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2
#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
//DIDT_DBR_STALL_PATTERN_1_2
#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_DBR_STALL_PATTERN_3_4
#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_DBR_STALL_PATTERN_5_6
#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_DBR_STALL_PATTERN_7
#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_DBR_WEIGHT0_3
#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
//DIDT_DBR_WEIGHT4_7
#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
//DIDT_DBR_WEIGHT8_11
#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
//DIDT_DBR_EDC_CTRL
#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0
#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17
#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L
#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
//DIDT_DBR_EDC_THRESHOLD
#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
//DIDT_DBR_EDC_STALL_PATTERN_1_2
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
//DIDT_DBR_EDC_STALL_PATTERN_3_4
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
//DIDT_DBR_EDC_STALL_PATTERN_5_6
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
//DIDT_DBR_EDC_STALL_PATTERN_7
#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
//DIDT_DBR_EDC_STATUS
#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4
#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L
//DIDT_DBR_EDC_STALL_DELAY_1
#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0
#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1__SHIFT 0x3
#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6
#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000007L
#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1_MASK 0x00000038L
#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L
//DIDT_DBR_EDC_OVERFLOW
#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
//DIDT_DBR_EDC_ROLLING_POWER_DELTA
#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
//DIDT_SQ_STALL_EVENT_COUNTER
#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
//DIDT_DB_STALL_EVENT_COUNTER
#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
//DIDT_TD_STALL_EVENT_COUNTER
#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
//DIDT_TCP_STALL_EVENT_COUNTER
#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
//DIDT_DBR_STALL_EVENT_COUNTER
#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
//TA_EDC_CNT
#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0
#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2
#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT 0x4
#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT 0x6
#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT 0x8
#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT 0xa
#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L
#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL
#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK 0x00000030L
#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK 0x000000C0L
#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK 0x00000300L
#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK 0x00000C00L
//TCI_EDC_CNT
#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT 0x0
#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK 0x00000003L
//TCP_EDC_CNT_NEW
#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0
#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2
#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4
#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6
#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT 0x8
#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xa
#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xc
#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT 0xe
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x10
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x12
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x14
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x16
#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L
#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL
#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L
#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L
#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK 0x00000300L
#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00000C00L
#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x00003000L
#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK 0x0000C000L
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x00030000L
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x000C0000L
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x00300000L
#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x00C00000L
//TD_EDC_CNT
#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0
#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2
#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4
#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6
#define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT 0x8
#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L
#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL
#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L
#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L
#define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK 0x00000300L
#endif
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-msm.h"
#define REG_BASE 0x100000
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
{ \
.grp = PINCTRL_PINGROUP("gpio"#id, gpio##id##_pins, \
(unsigned int)ARRAY_SIZE(gpio##id##_pins)), \
.ctl_reg = REG_BASE + REG_SIZE * id, \
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.egpio_enable = 12, \
.egpio_present = 11, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10 \
}, \
.nfuncs = 11, \
}
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.grp = PINCTRL_PINGROUP(#pg_name, pg_name##_pins, \
(unsigned int)ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
.oe_bit = -1, \
.in_bit = -1, \
.out_bit = -1, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
static const struct pinctrl_pin_desc sdx75_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
PINCTRL_PIN(110, "GPIO_110"),
PINCTRL_PIN(111, "GPIO_111"),
PINCTRL_PIN(112, "GPIO_112"),
PINCTRL_PIN(113, "GPIO_113"),
PINCTRL_PIN(114, "GPIO_114"),
PINCTRL_PIN(115, "GPIO_115"),
PINCTRL_PIN(116, "GPIO_116"),
PINCTRL_PIN(117, "GPIO_117"),
PINCTRL_PIN(118, "GPIO_118"),
PINCTRL_PIN(119, "GPIO_119"),
PINCTRL_PIN(120, "GPIO_120"),
PINCTRL_PIN(121, "GPIO_121"),
PINCTRL_PIN(122, "GPIO_122"),
PINCTRL_PIN(123, "GPIO_123"),
PINCTRL_PIN(124, "GPIO_124"),
PINCTRL_PIN(125, "GPIO_125"),
PINCTRL_PIN(126, "GPIO_126"),
PINCTRL_PIN(127, "GPIO_127"),
PINCTRL_PIN(128, "GPIO_128"),
PINCTRL_PIN(129, "GPIO_129"),
PINCTRL_PIN(130, "GPIO_130"),
PINCTRL_PIN(131, "GPIO_131"),
PINCTRL_PIN(132, "GPIO_132"),
PINCTRL_PIN(133, "SDC1_RCLK"),
PINCTRL_PIN(134, "SDC1_CLK"),
PINCTRL_PIN(135, "SDC1_CMD"),
PINCTRL_PIN(136, "SDC1_DATA"),
PINCTRL_PIN(137, "SDC2_CLK"),
PINCTRL_PIN(138, "SDC2_CMD"),
PINCTRL_PIN(139, "SDC2_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = {pin}
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
DECLARE_MSM_GPIO_PINS(54);
DECLARE_MSM_GPIO_PINS(55);
DECLARE_MSM_GPIO_PINS(56);
DECLARE_MSM_GPIO_PINS(57);
DECLARE_MSM_GPIO_PINS(58);
DECLARE_MSM_GPIO_PINS(59);
DECLARE_MSM_GPIO_PINS(60);
DECLARE_MSM_GPIO_PINS(61);
DECLARE_MSM_GPIO_PINS(62);
DECLARE_MSM_GPIO_PINS(63);
DECLARE_MSM_GPIO_PINS(64);
DECLARE_MSM_GPIO_PINS(65);
DECLARE_MSM_GPIO_PINS(66);
DECLARE_MSM_GPIO_PINS(67);
DECLARE_MSM_GPIO_PINS(68);
DECLARE_MSM_GPIO_PINS(69);
DECLARE_MSM_GPIO_PINS(70);
DECLARE_MSM_GPIO_PINS(71);
DECLARE_MSM_GPIO_PINS(72);
DECLARE_MSM_GPIO_PINS(73);
DECLARE_MSM_GPIO_PINS(74);
DECLARE_MSM_GPIO_PINS(75);
DECLARE_MSM_GPIO_PINS(76);
DECLARE_MSM_GPIO_PINS(77);
DECLARE_MSM_GPIO_PINS(78);
DECLARE_MSM_GPIO_PINS(79);
DECLARE_MSM_GPIO_PINS(80);
DECLARE_MSM_GPIO_PINS(81);
DECLARE_MSM_GPIO_PINS(82);
DECLARE_MSM_GPIO_PINS(83);
DECLARE_MSM_GPIO_PINS(84);
DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
DECLARE_MSM_GPIO_PINS(88);
DECLARE_MSM_GPIO_PINS(89);
DECLARE_MSM_GPIO_PINS(90);
DECLARE_MSM_GPIO_PINS(91);
DECLARE_MSM_GPIO_PINS(92);
DECLARE_MSM_GPIO_PINS(93);
DECLARE_MSM_GPIO_PINS(94);
DECLARE_MSM_GPIO_PINS(95);
DECLARE_MSM_GPIO_PINS(96);
DECLARE_MSM_GPIO_PINS(97);
DECLARE_MSM_GPIO_PINS(98);
DECLARE_MSM_GPIO_PINS(99);
DECLARE_MSM_GPIO_PINS(100);
DECLARE_MSM_GPIO_PINS(101);
DECLARE_MSM_GPIO_PINS(102);
DECLARE_MSM_GPIO_PINS(103);
DECLARE_MSM_GPIO_PINS(104);
DECLARE_MSM_GPIO_PINS(105);
DECLARE_MSM_GPIO_PINS(106);
DECLARE_MSM_GPIO_PINS(107);
DECLARE_MSM_GPIO_PINS(108);
DECLARE_MSM_GPIO_PINS(109);
DECLARE_MSM_GPIO_PINS(110);
DECLARE_MSM_GPIO_PINS(111);
DECLARE_MSM_GPIO_PINS(112);
DECLARE_MSM_GPIO_PINS(113);
DECLARE_MSM_GPIO_PINS(114);
DECLARE_MSM_GPIO_PINS(115);
DECLARE_MSM_GPIO_PINS(116);
DECLARE_MSM_GPIO_PINS(117);
DECLARE_MSM_GPIO_PINS(118);
DECLARE_MSM_GPIO_PINS(119);
DECLARE_MSM_GPIO_PINS(120);
DECLARE_MSM_GPIO_PINS(121);
DECLARE_MSM_GPIO_PINS(122);
DECLARE_MSM_GPIO_PINS(123);
DECLARE_MSM_GPIO_PINS(124);
DECLARE_MSM_GPIO_PINS(125);
DECLARE_MSM_GPIO_PINS(126);
DECLARE_MSM_GPIO_PINS(127);
DECLARE_MSM_GPIO_PINS(128);
DECLARE_MSM_GPIO_PINS(129);
DECLARE_MSM_GPIO_PINS(130);
DECLARE_MSM_GPIO_PINS(131);
DECLARE_MSM_GPIO_PINS(132);
static const unsigned int sdc1_rclk_pins[] = {133};
static const unsigned int sdc1_clk_pins[] = {134};
static const unsigned int sdc1_cmd_pins[] = {135};
static const unsigned int sdc1_data_pins[] = {136};
static const unsigned int sdc2_clk_pins[] = {137};
static const unsigned int sdc2_cmd_pins[] = {138};
static const unsigned int sdc2_data_pins[] = {139};
enum sdx75_functions {
msm_mux_adsp_ext,
msm_mux_atest_char,
msm_mux_audio_ref_clk,
msm_mux_bimc_dte,
msm_mux_char_exec,
msm_mux_coex_uart2,
msm_mux_coex_uart,
msm_mux_cri_trng,
msm_mux_cri_trng0,
msm_mux_cri_trng1,
msm_mux_dbg_out_clk,
msm_mux_ddr_bist,
msm_mux_ddr_pxi0,
msm_mux_ebi0_wrcdc,
msm_mux_ebi2_a,
msm_mux_ebi2_lcd,
msm_mux_ebi2_lcd_te,
msm_mux_emac0_mcg,
msm_mux_emac0_ptp,
msm_mux_emac1_mcg,
msm_mux_emac1_ptp,
msm_mux_emac_cdc,
msm_mux_emac_pps_in,
msm_mux_eth0_mdc,
msm_mux_eth0_mdio,
msm_mux_eth1_mdc,
msm_mux_eth1_mdio,
msm_mux_ext_dbg,
msm_mux_gcc_125_clk,
msm_mux_gcc_gp1_clk,
msm_mux_gcc_gp2_clk,
msm_mux_gcc_gp3_clk,
msm_mux_gcc_plltest,
msm_mux_gpio,
msm_mux_i2s_mclk,
msm_mux_jitter_bist,
msm_mux_ldo_en,
msm_mux_ldo_update,
msm_mux_m_voc,
msm_mux_mgpi_clk,
msm_mux_native_char,
msm_mux_native_tsens,
msm_mux_native_tsense,
msm_mux_nav_dr_sync,
msm_mux_nav_gpio,
msm_mux_pa_indicator,
msm_mux_pci_e,
msm_mux_pcie0_clkreq_n,
msm_mux_pcie1_clkreq_n,
msm_mux_pcie2_clkreq_n,
msm_mux_pll_bist_sync,
msm_mux_pll_clk_aux,
msm_mux_pll_ref_clk,
msm_mux_pri_mi2s,
msm_mux_prng_rosc,
msm_mux_qdss_cti,
msm_mux_qdss_gpio,
msm_mux_qlink0_b_en,
msm_mux_qlink0_b_req,
msm_mux_qlink0_l_en,
msm_mux_qlink0_l_req,
msm_mux_qlink0_wmss,
msm_mux_qlink1_l_en,
msm_mux_qlink1_l_req,
msm_mux_qlink1_wmss,
msm_mux_qup_se0,
msm_mux_qup_se1_l2_mira,
msm_mux_qup_se1_l2_mirb,
msm_mux_qup_se1_l3_mira,
msm_mux_qup_se1_l3_mirb,
msm_mux_qup_se2,
msm_mux_qup_se3,
msm_mux_qup_se4,
msm_mux_qup_se5,
msm_mux_qup_se6,
msm_mux_qup_se7,
msm_mux_qup_se8,
msm_mux_rgmii_rx_ctl,
msm_mux_rgmii_rxc,
msm_mux_rgmii_rxd,
msm_mux_rgmii_tx_ctl,
msm_mux_rgmii_txc,
msm_mux_rgmii_txd,
msm_mux_sd_card,
msm_mux_sdc1_tb,
msm_mux_sdc2_tb_trig,
msm_mux_sec_mi2s,
msm_mux_sgmii_phy_intr0_n,
msm_mux_sgmii_phy_intr1_n,
msm_mux_spmi_coex,
msm_mux_spmi_vgi,
msm_mux_tgu_ch0_trigout,
msm_mux_tmess_prng0,
msm_mux_tmess_prng1,
msm_mux_tmess_prng2,
msm_mux_tmess_prng3,
msm_mux_tri_mi2s,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
msm_mux_uim1_reset,
msm_mux_uim2_clk,
msm_mux_uim2_data,
msm_mux_uim2_present,
msm_mux_uim2_reset,
msm_mux_usb2phy_ac_en,
msm_mux_vsense_trigger_mirnat,
msm_mux__,
};
static const char *const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
"gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
"gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
"gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
"gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
"gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
"gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62",
"gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
"gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76",
"gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
"gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
"gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111",
"gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118",
"gpio119", "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
"gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132",
};
static const char *const adsp_ext_groups[] = {
"gpio59", "gpio68",
};
static const char *const atest_char_groups[] = {
"gpio24", "gpio25", "gpio26", "gpio41", "gpio63",
};
static const char *const audio_ref_clk_groups[] = {
"gpio126",
};
static const char *const bimc_dte_groups[] = {
"gpio14", "gpio15", "gpio61", "gpio59",
};
static const char *const char_exec_groups[] = {
"gpio6", "gpio7",
};
static const char *const coex_uart2_groups[] = {
"gpio48", "gpio49", "gpio90", "gpio91",
};
static const char *const coex_uart_groups[] = {
"gpio46", "gpio47",
};
static const char *const cri_trng_groups[] = {
"gpio36",
};
static const char *const cri_trng0_groups[] = {
"gpio31",
};
static const char *const cri_trng1_groups[] = {
"gpio32",
};
static const char *const dbg_out_clk_groups[] = {
"gpio26",
};
static const char *const ddr_bist_groups[] = {
"gpio46", "gpio47", "gpio48", "gpio49",
};
static const char *const ddr_pxi0_groups[] = {
"gpio45", "gpio46",
};
static const char *const ebi0_wrcdc_groups[] = {
"gpio0", "gpio2",
};
static const char *const ebi2_a_groups[] = {
"gpio100",
};
static const char *const ebi2_lcd_groups[] = {
"gpio99", "gpio101",
};
static const char *const ebi2_lcd_te_groups[] = {
"gpio98",
};
static const char *const emac0_mcg_groups[] = {
"gpio83", "gpio84", "gpio85", "gpio89",
};
static const char *const emac0_ptp_groups[] = {
"gpio35", "gpio83", "gpio84", "gpio85", "gpio89", "gpio119", "gpio123",
};
static const char *const emac1_mcg_groups[] = {
"gpio90", "gpio92", "gpio93", "gpio122",
};
static const char *const emac1_ptp_groups[] = {
"gpio112", "gpio113", "gpio114", "gpio115",
};
static const char *const emac_cdc_groups[] = {
"gpio38", "gpio39",
};
static const char *const emac_pps_in_groups[] = {
"gpio127",
};
static const char *const eth0_mdc_groups[] = {
"gpio94",
};
static const char *const eth0_mdio_groups[] = {
"gpio95",
};
static const char *const eth1_mdc_groups[] = {
"gpio106",
};
static const char *const eth1_mdio_groups[] = {
"gpio107",
};
static const char *const ext_dbg_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15",
};
static const char *const gcc_125_clk_groups[] = {
"gpio25",
};
static const char *const gcc_gp1_clk_groups[] = {
"gpio39",
};
static const char *const gcc_gp2_clk_groups[] = {
"gpio40",
};
static const char *const gcc_gp3_clk_groups[] = {
"gpio41",
};
static const char *const gcc_plltest_groups[] = {
"gpio81", "gpio82",
};
static const char *const i2s_mclk_groups[] = {
"gpio74",
};
static const char *const jitter_bist_groups[] = {
"gpio41",
};
static const char *const ldo_en_groups[] = {
"gpio8",
};
static const char *const ldo_update_groups[] = {
"gpio62",
};
static const char *const m_voc_groups[] = {
"gpio62", "gpio63", "gpio64", "gpio65", "gpio71",
};
static const char *const mgpi_clk_groups[] = {
"gpio39", "gpio40",
};
static const char *const native_char_groups[] = {
"gpio29", "gpio33", "gpio57", "gpio66", "gpio67",
};
static const char *const native_tsens_groups[] = {
"gpio38",
};
static const char *const native_tsense_groups[] = {
"gpio64", "gpio76",
};
static const char *const nav_dr_sync_groups[] = {
"gpio36",
};
static const char *const nav_gpio_groups[] = {
"gpio35", "gpio36", "gpio104",
};
static const char *const pa_indicator_groups[] = {
"gpio58",
};
static const char *const pci_e_groups[] = {
"gpio42",
};
static const char *const pcie0_clkreq_n_groups[] = {
"gpio43",
};
static const char *const pcie1_clkreq_n_groups[] = {
"gpio124",
};
static const char *const pcie2_clkreq_n_groups[] = {
"gpio121",
};
static const char *const pll_bist_sync_groups[] = {
"gpio38",
};
static const char *const pll_clk_aux_groups[] = {
"gpio40",
};
static const char *const pll_ref_clk_groups[] = {
"gpio37",
};
static const char *const pri_mi2s_groups[] = {
"gpio16", "gpio17", "gpio18", "gpio19",
};
static const char *const prng_rosc_groups[] = {
"gpio27", "gpio36", "gpio37", "gpio38",
};
static const char *const qdss_cti_groups[] = {
"gpio16", "gpio17", "gpio52", "gpio53", "gpio56",
"gpio57", "gpio59", "gpio60", "gpio78", "gpio79",
};
static const char *const qdss_gpio_groups[] = {
"gpio82", "gpio83", "gpio84", "gpio85", "gpio94",
"gpio95", "gpio96", "gpio97", "gpio110", "gpio111",
"gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
"gpio117", "gpio118", "gpio119",
};
static const char *const qlink0_b_en_groups[] = {
"gpio40",
};
static const char *const qlink0_b_req_groups[] = {
"gpio41",
};
static const char *const qlink0_l_en_groups[] = {
"gpio37",
};
static const char *const qlink0_l_req_groups[] = {
"gpio38",
};
static const char *const qlink0_wmss_groups[] = {
"gpio39",
};
static const char *const qlink1_l_en_groups[] = {
"gpio26",
};
static const char *const qlink1_l_req_groups[] = {
"gpio27",
};
static const char *const qlink1_wmss_groups[] = {
"gpio28",
};
static const char *const qup_se0_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11",
};
static const char *const qup_se1_l2_mira_groups[] = {
"gpio12",
};
static const char *const qup_se1_l2_mirb_groups[] = {
"gpio16",
};
static const char *const qup_se1_l3_mira_groups[] = {
"gpio13",
};
static const char *const qup_se1_l3_mirb_groups[] = {
"gpio17",
};
static const char *const qup_se2_groups[] = {
"gpio14", "gpio15", "gpio16", "gpio17",
};
static const char *const qup_se3_groups[] = {
"gpio52", "gpio53", "gpio54", "gpio55",
};
static const char *const qup_se4_groups[] = {
"gpio64", "gpio65",
};
static const char *const qup_se5_groups[] = {
"gpio110", "gpio111",
};
static const char *const qup_se6_groups[] = {
"gpio112", "gpio113", "gpio114", "gpio115",
};
static const char *const qup_se7_groups[] = {
"gpio116", "gpio117", "gpio118", "gpio119",
};
static const char *const qup_se8_groups[] = {
"gpio124", "gpio125",
};
static const char *const rgmii_rx_ctl_groups[] = {
"gpio93",
};
static const char *const rgmii_rxc_groups[] = {
"gpio88",
};
static const char *const rgmii_rxd_groups[] = {
"gpio89", "gpio90", "gpio91", "gpio92",
};
static const char *const rgmii_tx_ctl_groups[] = {
"gpio87",
};
static const char *const rgmii_txc_groups[] = {
"gpio82",
};
static const char *const rgmii_txd_groups[] = {
"gpio83", "gpio84", "gpio85", "gpio86",
};
static const char *const sd_card_groups[] = {
"gpio105",
};
static const char *const sdc1_tb_groups[] = {
"gpio84", "gpio130",
};
static const char *const sdc2_tb_trig_groups[] = {
"gpio129",
};
static const char *const sec_mi2s_groups[] = {
"gpio20", "gpio21", "gpio22", "gpio23",
};
static const char *const sgmii_phy_intr0_n_groups[] = {
"gpio97",
};
static const char *const sgmii_phy_intr1_n_groups[] = {
"gpio109",
};
static const char *const spmi_coex_groups[] = {
"gpio48", "gpio49",
};
static const char *const spmi_vgi_groups[] = {
"gpio50", "gpio51",
};
static const char *const tgu_ch0_trigout_groups[] = {
"gpio55",
};
static const char *const tmess_prng0_groups[] = {
"gpio28",
};
static const char *const tmess_prng1_groups[] = {
"gpio29",
};
static const char *const tmess_prng2_groups[] = {
"gpio30",
};
static const char *const tmess_prng3_groups[] = {
"gpio31",
};
static const char *const tri_mi2s_groups[] = {
"gpio98", "gpio99", "gpio100", "gpio101",
};
static const char *const uim1_clk_groups[] = {
"gpio7",
};
static const char *const uim1_data_groups[] = {
"gpio4",
};
static const char *const uim1_present_groups[] = {
"gpio5",
};
static const char *const uim1_reset_groups[] = {
"gpio6",
};
static const char *const uim2_clk_groups[] = {
"gpio3",
};
static const char *const uim2_data_groups[] = {
"gpio0",
};
static const char *const uim2_present_groups[] = {
"gpio1",
};
static const char *const uim2_reset_groups[] = {
"gpio2",
};
static const char *const usb2phy_ac_en_groups[] = {
"gpio80",
};
static const char *const vsense_trigger_mirnat_groups[] = {
"gpio37",
};
static const struct pinfunction sdx75_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(audio_ref_clk),
MSM_PIN_FUNCTION(bimc_dte),
MSM_PIN_FUNCTION(char_exec),
MSM_PIN_FUNCTION(coex_uart2),
MSM_PIN_FUNCTION(coex_uart),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out_clk),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ebi0_wrcdc),
MSM_PIN_FUNCTION(ebi2_a),
MSM_PIN_FUNCTION(ebi2_lcd),
MSM_PIN_FUNCTION(ebi2_lcd_te),
MSM_PIN_FUNCTION(emac0_mcg),
MSM_PIN_FUNCTION(emac0_ptp),
MSM_PIN_FUNCTION(emac1_mcg),
MSM_PIN_FUNCTION(emac1_ptp),
MSM_PIN_FUNCTION(emac_cdc),
MSM_PIN_FUNCTION(emac_pps_in),
MSM_PIN_FUNCTION(eth0_mdc),
MSM_PIN_FUNCTION(eth0_mdio),
MSM_PIN_FUNCTION(eth1_mdc),
MSM_PIN_FUNCTION(eth1_mdio),
MSM_PIN_FUNCTION(ext_dbg),
MSM_PIN_FUNCTION(gcc_125_clk),
MSM_PIN_FUNCTION(gcc_gp1_clk),
MSM_PIN_FUNCTION(gcc_gp2_clk),
MSM_PIN_FUNCTION(gcc_gp3_clk),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(i2s_mclk),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mgpi_clk),
MSM_PIN_FUNCTION(native_char),
MSM_PIN_FUNCTION(native_tsens),
MSM_PIN_FUNCTION(native_tsense),
MSM_PIN_FUNCTION(nav_dr_sync),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e),
MSM_PIN_FUNCTION(pcie0_clkreq_n),
MSM_PIN_FUNCTION(pcie1_clkreq_n),
MSM_PIN_FUNCTION(pcie2_clkreq_n),
MSM_PIN_FUNCTION(pll_bist_sync),
MSM_PIN_FUNCTION(pll_clk_aux),
MSM_PIN_FUNCTION(pll_ref_clk),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink0_b_en),
MSM_PIN_FUNCTION(qlink0_b_req),
MSM_PIN_FUNCTION(qlink0_l_en),
MSM_PIN_FUNCTION(qlink0_l_req),
MSM_PIN_FUNCTION(qlink1_l_en),
MSM_PIN_FUNCTION(qlink1_l_req),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qup_se0),
MSM_PIN_FUNCTION(qup_se1_l2_mira),
MSM_PIN_FUNCTION(qup_se1_l2_mirb),
MSM_PIN_FUNCTION(qup_se1_l3_mira),
MSM_PIN_FUNCTION(qup_se1_l3_mirb),
MSM_PIN_FUNCTION(qup_se2),
MSM_PIN_FUNCTION(qup_se3),
MSM_PIN_FUNCTION(qup_se4),
MSM_PIN_FUNCTION(qup_se5),
MSM_PIN_FUNCTION(qup_se6),
MSM_PIN_FUNCTION(qup_se7),
MSM_PIN_FUNCTION(qup_se8),
MSM_PIN_FUNCTION(rgmii_rx_ctl),
MSM_PIN_FUNCTION(rgmii_rxc),
MSM_PIN_FUNCTION(rgmii_rxd),
MSM_PIN_FUNCTION(rgmii_tx_ctl),
MSM_PIN_FUNCTION(rgmii_txc),
MSM_PIN_FUNCTION(rgmii_txd),
MSM_PIN_FUNCTION(sd_card),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sdc2_tb_trig),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sgmii_phy_intr0_n),
MSM_PIN_FUNCTION(sgmii_phy_intr1_n),
MSM_PIN_FUNCTION(spmi_coex),
MSM_PIN_FUNCTION(spmi_vgi),
MSM_PIN_FUNCTION(tgu_ch0_trigout),
MSM_PIN_FUNCTION(tmess_prng0),
MSM_PIN_FUNCTION(tmess_prng1),
MSM_PIN_FUNCTION(tmess_prng2),
MSM_PIN_FUNCTION(tmess_prng3),
MSM_PIN_FUNCTION(tri_mi2s),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb2phy_ac_en),
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
};
static const struct msm_pingroup sdx75_groups[] = {
[0] = PINGROUP(0, uim2_data, ebi0_wrcdc, _, _, _, _, _, _, _, _),
[1] = PINGROUP(1, uim2_present, _, _, _, _, _, _, _, _, _),
[2] = PINGROUP(2, uim2_reset, ebi0_wrcdc, _, _, _, _, _, _, _, _),
[3] = PINGROUP(3, uim2_clk, _, _, _, _, _, _, _, _, _),
[4] = PINGROUP(4, uim1_data, _, _, _, _, _, _, _, _, _),
[5] = PINGROUP(5, uim1_present, _, _, _, _, _, _, _, _, _),
[6] = PINGROUP(6, uim1_reset, char_exec, _, _, _, _, _, _, _, _),
[7] = PINGROUP(7, uim1_clk, char_exec, _, _, _, _, _, _, _, _),
[8] = PINGROUP(8, qup_se0, ldo_en, _, _, _, _, _, _, _, _),
[9] = PINGROUP(9, qup_se0, _, _, _, _, _, _, _, _, _),
[10] = PINGROUP(10, qup_se0, _, _, _, _, _, _, _, _, _),
[11] = PINGROUP(11, qup_se0, _, _, _, _, _, _, _, _, _),
[12] = PINGROUP(12, qup_se1_l2_mira, ext_dbg, _, _, _, _, _, _, _, _),
[13] = PINGROUP(13, qup_se1_l3_mira, ext_dbg, _, _, _, _, _, _, _, _),
[14] = PINGROUP(14, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _),
[15] = PINGROUP(15, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _),
[16] = PINGROUP(16, pri_mi2s, qup_se2, qup_se1_l2_mirb, qdss_cti, qdss_cti, _, _, _, _, _),
[17] = PINGROUP(17, pri_mi2s, qup_se2, qup_se1_l3_mirb, qdss_cti, qdss_cti, _, _, _, _, _),
[18] = PINGROUP(18, pri_mi2s, _, _, _, _, _, _, _, _, _),
[19] = PINGROUP(19, pri_mi2s, _, _, _, _, _, _, _, _, _),
[20] = PINGROUP(20, sec_mi2s, _, _, _, _, _, _, _, _, _),
[21] = PINGROUP(21, sec_mi2s, _, _, _, _, _, _, _, _, _),
[22] = PINGROUP(22, sec_mi2s, _, _, _, _, _, _, _, _, _),
[23] = PINGROUP(23, sec_mi2s, _, _, _, _, _, _, _, _, _),
[24] = PINGROUP(24, _, atest_char, _, _, _, _, _, _, _, _),
[25] = PINGROUP(25, gcc_125_clk, _, atest_char, _, _, _, _, _, _, _),
[26] = PINGROUP(26, _, _, qlink1_l_en, dbg_out_clk, atest_char, _, _, _, _, _),
[27] = PINGROUP(27, _, _, qlink1_l_req, prng_rosc, _, _, _, _, _, _),
[28] = PINGROUP(28, _, qlink1_wmss, tmess_prng0, _, _, _, _, _, _, _),
[29] = PINGROUP(29, _, _, _, native_char, tmess_prng1, _, _, _, _, _),
[30] = PINGROUP(30, _, _, _, tmess_prng2, _, _, _, _, _, _),
[31] = PINGROUP(31, _, _, cri_trng0, _, tmess_prng3, _, _, _, _, _),
[32] = PINGROUP(32, _, _, cri_trng1, _, _, _, _, _, _, _),
[33] = PINGROUP(33, _, _, native_char, _, _, _, _, _, _, _),
[34] = PINGROUP(34, _, _, _, _, _, _, _, _, _, _),
[35] = PINGROUP(35, nav_gpio, emac0_ptp, emac0_ptp, _, _, _, _, _, _, _),
[36] = PINGROUP(36, nav_gpio, nav_dr_sync, nav_gpio, cri_trng, prng_rosc, _, _, _, _, _),
[37] = PINGROUP(37, qlink0_l_en, _, pll_ref_clk, prng_rosc, vsense_trigger_mirnat, _, _, _, _, _),
[38] = PINGROUP(38, qlink0_l_req, _, pll_bist_sync, prng_rosc, _, emac_cdc, _, native_tsens, _, _),
[39] = PINGROUP(39, qlink0_wmss, _, mgpi_clk, gcc_gp1_clk, _, emac_cdc, _, _, _, _),
[40] = PINGROUP(40, qlink0_b_en, _, mgpi_clk, pll_clk_aux, gcc_gp2_clk, _, _, _, _, _),
[41] = PINGROUP(41, qlink0_b_req, _, jitter_bist, gcc_gp3_clk, _, _, atest_char, _, _, _),
[42] = PINGROUP(42, pci_e, _, _, _, _, _, _, _, _, _),
[43] = PINGROUP(43, pcie0_clkreq_n, _, _, _, _, _, _, _, _, _),
[44] = PINGROUP(44, _, _, _, _, _, _, _, _, _, _),
[45] = PINGROUP(45, ddr_pxi0, _, _, _, _, _, _, _, _, _),
[46] = PINGROUP(46, coex_uart, ddr_bist, ddr_pxi0, _, _, _, _, _, _, _),
[47] = PINGROUP(47, coex_uart, ddr_bist, _, _, _, _, _, _, _, _),
[48] = PINGROUP(48, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _),
[49] = PINGROUP(49, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _),
[50] = PINGROUP(50, spmi_vgi, _, _, _, _, _, _, _, _, _),
[51] = PINGROUP(51, spmi_vgi, _, _, _, _, _, _, _, _, _),
[52] = PINGROUP(52, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
[53] = PINGROUP(53, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
[54] = PINGROUP(54, qup_se3, _, _, _, _, _, _, _, _, _),
[55] = PINGROUP(55, qup_se3, tgu_ch0_trigout, _, _, _, _, _, _, _, _),
[56] = PINGROUP(56, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _),
[57] = PINGROUP(57, qdss_cti, qdss_cti, _, native_char, _, _, _, _, _, _),
[58] = PINGROUP(58, _, pa_indicator, _, _, _, _, _, _, _, _),
[59] = PINGROUP(59, adsp_ext, qdss_cti, _, bimc_dte, _, _, _, _, _, _),
[60] = PINGROUP(60, qdss_cti, _, _, _, _, _, _, _, _, _),
[61] = PINGROUP(61, _, bimc_dte, _, _, _, _, _, _, _, _),
[62] = PINGROUP(62, m_voc, ldo_update, _, _, _, _, _, _, _, _),
[63] = PINGROUP(63, m_voc, _, atest_char, _, _, _, _, _, _, _),
[64] = PINGROUP(64, qup_se4, m_voc, _, native_tsense, _, _, _, _, _, _),
[65] = PINGROUP(65, qup_se4, m_voc, _, _, _, _, _, _, _, _),
[66] = PINGROUP(66, _, native_char, _, _, _, _, _, _, _, _),
[67] = PINGROUP(67, _, native_char, _, _, _, _, _, _, _, _),
[68] = PINGROUP(68, adsp_ext, _, _, _, _, _, _, _, _, _),
[69] = PINGROUP(69, _, _, _, _, _, _, _, _, _, _),
[70] = PINGROUP(70, _, _, _, _, _, _, _, _, _, _),
[71] = PINGROUP(71, m_voc, _, _, _, _, _, _, _, _, _),
[72] = PINGROUP(72, _, _, _, _, _, _, _, _, _, _),
[73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _),
[74] = PINGROUP(74, i2s_mclk, _, _, _, _, _, _, _, _, _),
[75] = PINGROUP(75, _, _, _, _, _, _, _, _, _, _),
[76] = PINGROUP(76, native_tsense, _, _, _, _, _, _, _, _, _),
[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _, _),
[78] = PINGROUP(78, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _),
[79] = PINGROUP(79, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _),
[80] = PINGROUP(80, usb2phy_ac_en, _, _, _, _, _, _, _, _, _),
[81] = PINGROUP(81, gcc_plltest, _, _, _, _, _, _, _, _, _),
[82] = PINGROUP(82, rgmii_txc, gcc_plltest, qdss_gpio, _, _, _, _, _, _, _),
[83] = PINGROUP(83, rgmii_txd, emac0_ptp, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _),
[84] = PINGROUP(84, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, sdc1_tb, _, _, _, _),
[85] = PINGROUP(85, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _, _),
[86] = PINGROUP(86, rgmii_txd, _, _, _, _, _, _, _, _, _),
[87] = PINGROUP(87, rgmii_tx_ctl, _, _, _, _, _, _, _, _, _),
[88] = PINGROUP(88, rgmii_rxc, _, _, _, _, _, _, _, _, _),
[89] = PINGROUP(89, rgmii_rxd, emac0_ptp, emac0_ptp, emac0_mcg, _, _, _, _, _, _),
[90] = PINGROUP(90, rgmii_rxd, coex_uart2, emac1_mcg, _, _, _, _, _, _, _),
[91] = PINGROUP(91, rgmii_rxd, coex_uart2, _, _, _, _, _, _, _, _),
[92] = PINGROUP(92, rgmii_rxd, emac1_mcg, _, _, _, _, _, _, _, _),
[93] = PINGROUP(93, rgmii_rx_ctl, emac1_mcg, _, _, _, _, _, _, _, _),
[94] = PINGROUP(94, eth0_mdc, qdss_gpio, _, _, _, _, _, _, _, _),
[95] = PINGROUP(95, eth0_mdio, qdss_gpio, _, _, _, _, _, _, _, _),
[96] = PINGROUP(96, qdss_gpio, _, _, _, _, _, _, _, _, _),
[97] = PINGROUP(97, sgmii_phy_intr0_n, _, qdss_gpio, _, _, _, _, _, _, _),
[98] = PINGROUP(98, tri_mi2s, ebi2_lcd_te, _, _, _, _, _, _, _, _),
[99] = PINGROUP(99, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _),
[100] = PINGROUP(100, tri_mi2s, ebi2_a, _, _, _, _, _, _, _, _),
[101] = PINGROUP(101, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _),
[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _),
[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _),
[104] = PINGROUP(104, nav_gpio, _, _, _, _, _, _, _, _, _),
[105] = PINGROUP(105, sd_card, _, _, _, _, _, _, _, _, _),
[106] = PINGROUP(106, eth1_mdc, _, _, _, _, _, _, _, _, _),
[107] = PINGROUP(107, eth1_mdio, _, _, _, _, _, _, _, _, _),
[108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _),
[109] = PINGROUP(109, sgmii_phy_intr1_n, _, _, _, _, _, _, _, _, _),
[110] = PINGROUP(110, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _),
[111] = PINGROUP(111, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _),
[112] = PINGROUP(112, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _),
[113] = PINGROUP(113, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _),
[114] = PINGROUP(114, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _),
[115] = PINGROUP(115, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _),
[116] = PINGROUP(116, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _),
[117] = PINGROUP(117, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _),
[118] = PINGROUP(118, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _),
[119] = PINGROUP(119, qup_se7, emac0_ptp, qdss_gpio, _, _, _, _, _, _, _),
[120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _),
[121] = PINGROUP(121, pcie2_clkreq_n, _, _, _, _, _, _, _, _, _),
[122] = PINGROUP(122, emac1_mcg, _, _, _, _, _, _, _, _, _),
[123] = PINGROUP(123, emac0_ptp, emac0_ptp, emac0_ptp, emac0_ptp, _, _, _, _, _, _),
[124] = PINGROUP(124, pcie1_clkreq_n, qup_se8, _, _, _, _, _, _, _, _),
[125] = PINGROUP(125, qup_se8, _, _, _, _, _, _, _, _, _),
[126] = PINGROUP(126, audio_ref_clk, _, _, _, _, _, _, _, _, _),
[127] = PINGROUP(127, emac_pps_in, _, _, _, _, _, _, _, _, _),
[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _),
[129] = PINGROUP(129, sdc2_tb_trig, _, _, _, _, _, _, _, _, _),
[130] = PINGROUP(130, sdc1_tb, _, _, _, _, _, _, _, _, _),
[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _),
[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _),
[133] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x19a000, 16, 0),
[134] = SDC_QDSD_PINGROUP(sdc1_clk, 0x19a000, 14, 6),
[135] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x19a000, 11, 3),
[136] = SDC_QDSD_PINGROUP(sdc1_data, 0x19a000, 9, 0),
[137] = SDC_QDSD_PINGROUP(sdc2_clk, 0x19b000, 14, 6),
[138] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x19b000, 11, 3),
[139] = SDC_QDSD_PINGROUP(sdc2_data, 0x19b000, 9, 0),
};
static const struct msm_gpio_wakeirq_map sdx75_pdc_map[] = {
{ 1, 57 }, { 2, 91 }, {5, 52 }, { 6, 109 }, { 9, 129 }, { 11, 62 },
{ 13, 84 }, { 15, 87 }, { 17, 88 }, { 18, 89 }, { 19, 90 }, { 20, 92 },
{ 21, 93 }, { 22, 94 }, { 23, 95 }, { 25, 96 }, { 27, 97 }, { 35, 58 },
{ 36, 53 }, { 38, 98 }, { 39, 99 }, { 40, 100 }, { 41, 101 }, { 42, 54 },
{ 43, 56 }, { 44, 71 }, { 46, 60 }, { 47, 61 }, { 49, 47 }, { 50, 126 },
{ 51, 55 }, { 52, 102 }, { 53, 141 }, { 54, 104 }, { 55, 105 }, { 56, 106 },
{ 57, 107 }, { 59, 108 }, { 60, 110 }, { 62, 111 }, { 63, 112 }, { 64, 113 },
{ 65, 114 }, { 67, 115 }, { 68, 116 }, { 69, 117 }, { 70, 118 }, { 71, 119 },
{ 72, 120 }, { 75, 121 }, { 76, 122 }, { 78, 123 }, { 79, 124 }, { 80, 125 },
{ 81, 50 }, { 85, 127 }, { 87, 128 }, { 91, 130 }, { 92, 131 }, { 93, 132 },
{ 94, 133 }, { 95, 134 }, { 97, 135 }, { 98, 136 }, { 101, 64 }, { 103, 51 },
{ 105, 65 }, { 106, 66 }, { 107, 67 }, { 108, 68 }, { 109, 69 }, { 111, 70 },
{ 113, 59 }, { 115, 72 }, { 116, 73 }, { 117, 74 }, { 118, 75 }, { 119, 76 },
{ 120, 77 }, { 121, 78 }, { 123, 79 }, { 124, 80 }, { 125, 63 }, { 127, 81 },
{ 128, 82 }, { 129, 83 }, { 130, 85 }, { 132, 86 },
};
static const struct msm_pinctrl_soc_data sdx75_pinctrl = {
.pins = sdx75_pins,
.npins = ARRAY_SIZE(sdx75_pins),
.functions = sdx75_functions,
.nfunctions = ARRAY_SIZE(sdx75_functions),
.groups = sdx75_groups,
.ngroups = ARRAY_SIZE(sdx75_groups),
.ngpios = 133,
.wakeirq_map = sdx75_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sdx75_pdc_map),
};
static const struct of_device_id sdx75_pinctrl_of_match[] = {
{ .compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl },
{ }
};
MODULE_DEVICE_TABLE(of, sdx75_pinctrl_of_match);
static int sdx75_pinctrl_probe(struct platform_device *pdev)
{
const struct msm_pinctrl_soc_data *pinctrl_data;
pinctrl_data = of_device_get_match_data(&pdev->dev);
if (!pinctrl_data)
return -EINVAL;
return msm_pinctrl_probe(pdev, pinctrl_data);
}
static struct platform_driver sdx75_pinctrl_driver = {
.driver = {
.name = "sdx75-tlmm",
.of_match_table = sdx75_pinctrl_of_match,
},
.probe = sdx75_pinctrl_probe,
.remove = msm_pinctrl_remove,
};
static int __init sdx75_pinctrl_init(void)
{
return platform_driver_register(&sdx75_pinctrl_driver);
}
arch_initcall(sdx75_pinctrl_init);
static void __exit sdx75_pinctrl_exit(void)
{
platform_driver_unregister(&sdx75_pinctrl_driver);
}
module_exit(sdx75_pinctrl_exit);
MODULE_DESCRIPTION("QTI sdx75 pinctrl driver");
MODULE_LICENSE("GPL");
|
/*
* Copyright 2015 Hans de Goede <[email protected]>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a33.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A33 Tablet";
compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
|
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree file for Globalscale MOCHAbin
* Copyright (C) 2019 Globalscale technologies, Inc.
* Copyright (C) 2021 Sartura Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"
/ {
model = "Globalscale MOCHAbin";
compatible = "globalscale,mochabin", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &swport1;
ethernet4 = &swport2;
ethernet5 = &swport3;
ethernet6 = &swport4;
};
/* SFP+ 10G */
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
};
/* SFP 1G */
sfp_eth2: sfp-eth2 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c0>;
los-gpios = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
};
};
/* microUSB UART console */
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
/* eMMC */
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
non-removable;
/delete-property/ marvell,xenon-phy-slow-mode;
no-1-8-v;
};
&cp0_pinctrl {
cp0_uart0_pins: cp0-uart0-pins {
marvell,pins = "mpp6", "mpp7";
marvell,function = "uart0";
};
cp0_spi0_pins: cp0-spi0-pins {
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
marvell,function = "spi0";
};
cp0_spi1_pins: cp0-spi1-pins {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp0_i2c0_pins: cp0-i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c1";
};
pca9554_int_pins: pca9554-int-pins {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
cp0_rgmii1_pins: cp0-rgmii1-pins {
marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
is31_sdb_pins: is31-sdb-pins {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = "mpp9";
marvell,function = "gpio";
};
cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {
marvell,pins = "mpp5";
marvell,function = "pcie1";
};
cp0_switch_pins: cp0-switch-pins {
marvell,pins = "mpp0", "mpp1";
marvell,function = "gpio";
};
cp0_phy_pins: cp0-phy-pins {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
};
/* mikroBUS UART */
&cp0_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_uart0_pins>;
};
/* mikroBUS SPI */
&cp0_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
};
/* SPI-NOR */
&cp0_spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x3e0000>;
read-only;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
/* mikroBUS, 1G SFP and GPIO expander */
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
sfp_gpio: pca9554@39 {
compatible = "nxp,pca9554";
pinctrl-names = "default";
pinctrl-0 = <&pca9554_int_pins>;
reg = <0x39>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
/*
* IO0_0: SFP+_TX_FAULT
* IO0_1: SFP+_TX_DISABLE
* IO0_2: SFP+_PRSNT
* IO0_3: SFP+_LOSS
* IO0_4: SFP_TX_FAULT
* IO0_5: SFP_TX_DISABLE
* IO0_6: SFP_PRSNT
* IO0_7: SFP_LOSS
*/
};
};
/* IS31FL3199, mini-PCIe and 10G SFP+ */
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
clock-frequency = <100000>;
leds@64 {
compatible = "issi,is31fl3199";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&is31_sdb_pins>;
shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
reg = <0x64>;
led1_red: led@1 {
label = "red:led1";
reg = <1>;
led-max-microamp = <20000>;
};
led1_green: led@2 {
label = "green:led1";
reg = <2>;
};
led1_blue: led@3 {
label = "blue:led1";
reg = <3>;
};
led2_red: led@4 {
label = "red:led2";
reg = <4>;
};
led2_green: led@5 {
label = "green:led2";
reg = <5>;
};
led2_blue: led@6 {
label = "blue:led2";
reg = <6>;
};
led3_red: led@7 {
label = "red:led3";
reg = <7>;
};
led3_green: led@8 {
label = "green:led3";
reg = <8>;
};
led3_blue: led@9 {
label = "blue:led3";
reg = <9>;
};
};
};
&cp0_mdio {
status = "okay";
/* 88E1512 PHY */
eth2phy: ethernet-phy@1 {
reg = <1>;
sfp = <&sfp_eth2>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_phy_pins>;
reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
};
/* 88E6141 Topaz switch */
switch: ethernet-switch@3 {
compatible = "marvell,mv88e6085";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_switch_pins>;
reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
swport1: ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
swport2: ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
swport3: ethernet-port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
swport4: ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
swphy1: ethernet-phy@17 {
reg = <17>;
};
swphy2: ethernet-phy@18 {
reg = <18>;
};
swphy3: ethernet-phy@19 {
reg = <19>;
};
swphy4: ethernet-phy@20 {
reg = <20>;
};
};
};
};
&cp0_ethernet {
status = "okay";
};
/* 10G SFP+ */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-r";
phys = <&cp0_comphy4 0>;
managed = "in-band-status";
sfp = <&sfp_eth0>;
};
/* Topaz switch uplink */
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy0 1>;
fixed-link {
speed = <2500>;
full-duplex;
};
};
/* 1G SFP or 1G RJ45 */
&cp0_eth2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_rgmii1_pins>;
phy = <ð2phy>;
phy-mode = "rgmii-id";
};
&cp0_utmi {
status = "okay";
};
/* SMSC USB5434B hub */
&cp0_usb3_0 {
status = "okay";
phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
phy-names = "cp0-usb3h0-comphy", "utmi";
};
/* miniPCI-E USB */
&cp0_usb3_1 {
status = "okay";
};
&cp0_sata0 {
status = "okay";
/* 7 + 12 SATA connector (J24) */
sata-port@0 {
phys = <&cp0_comphy2 0>;
};
/* M.2-2250 B-key (J39) */
sata-port@1 {
phys = <&cp0_comphy3 1>;
};
};
/* miniPCI-E (J5) */
&cp0_pcie2 {
status = "okay";
pinctrl-names = "default", "clkreq";
pinctrl-0 = <&cp0_pcie_reset_pins>;
pinctrl-1 = <&cp0_pcie_clkreq_pins>;
phys = <&cp0_comphy5 2>;
phy-names = "cp0-pcie2-x1-phy";
reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;
};
|
// SPDX-License-Identifier: GPL-2.0
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include <linux/bpf.h>
#include <linux/stddef.h>
#include <linux/pkt_cls.h>
#include <linux/if_ether.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/ipv6.h>
#include <bpf/bpf_helpers.h>
#include <bpf/bpf_endian.h>
#ifndef ctx_ptr
# define ctx_ptr(field) (void *)(long)(field)
#endif
#define ip4_src 0xac100164 /* 172.16.1.100 */
#define ip4_dst 0xac100264 /* 172.16.2.100 */
#define ip6_src { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x01, 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe }
#define ip6_dst { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x02, 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe }
#ifndef v6_equal
# define v6_equal(a, b) (a.s6_addr32[0] == b.s6_addr32[0] && \
a.s6_addr32[1] == b.s6_addr32[1] && \
a.s6_addr32[2] == b.s6_addr32[2] && \
a.s6_addr32[3] == b.s6_addr32[3])
#endif
volatile const __u32 IFINDEX_SRC;
volatile const __u32 IFINDEX_DST;
static __always_inline bool is_remote_ep_v4(struct __sk_buff *skb,
__be32 addr)
{
void *data_end = ctx_ptr(skb->data_end);
void *data = ctx_ptr(skb->data);
struct iphdr *ip4h;
if (data + sizeof(struct ethhdr) > data_end)
return false;
ip4h = (struct iphdr *)(data + sizeof(struct ethhdr));
if ((void *)(ip4h + 1) > data_end)
return false;
return ip4h->daddr == addr;
}
static __always_inline bool is_remote_ep_v6(struct __sk_buff *skb,
struct in6_addr addr)
{
void *data_end = ctx_ptr(skb->data_end);
void *data = ctx_ptr(skb->data);
struct ipv6hdr *ip6h;
if (data + sizeof(struct ethhdr) > data_end)
return false;
ip6h = (struct ipv6hdr *)(data + sizeof(struct ethhdr));
if ((void *)(ip6h + 1) > data_end)
return false;
return v6_equal(ip6h->daddr, addr);
}
SEC("tc")
int tc_chk(struct __sk_buff *skb)
{
void *data_end = ctx_ptr(skb->data_end);
void *data = ctx_ptr(skb->data);
__u32 *raw = data;
if (data + sizeof(struct ethhdr) > data_end)
return TC_ACT_SHOT;
return !raw[0] && !raw[1] && !raw[2] ? TC_ACT_SHOT : TC_ACT_OK;
}
SEC("tc")
int tc_dst(struct __sk_buff *skb)
{
__u8 zero[ETH_ALEN * 2];
bool redirect = false;
switch (skb->protocol) {
case __bpf_constant_htons(ETH_P_IP):
redirect = is_remote_ep_v4(skb, __bpf_constant_htonl(ip4_src));
break;
case __bpf_constant_htons(ETH_P_IPV6):
redirect = is_remote_ep_v6(skb, (struct in6_addr){{ip6_src}});
break;
}
if (!redirect)
return TC_ACT_OK;
__builtin_memset(&zero, 0, sizeof(zero));
if (bpf_skb_store_bytes(skb, 0, &zero, sizeof(zero), 0) < 0)
return TC_ACT_SHOT;
return bpf_redirect_neigh(IFINDEX_SRC, NULL, 0, 0);
}
SEC("tc")
int tc_src(struct __sk_buff *skb)
{
__u8 zero[ETH_ALEN * 2];
bool redirect = false;
switch (skb->protocol) {
case __bpf_constant_htons(ETH_P_IP):
redirect = is_remote_ep_v4(skb, __bpf_constant_htonl(ip4_dst));
break;
case __bpf_constant_htons(ETH_P_IPV6):
redirect = is_remote_ep_v6(skb, (struct in6_addr){{ip6_dst}});
break;
}
if (!redirect)
return TC_ACT_OK;
__builtin_memset(&zero, 0, sizeof(zero));
if (bpf_skb_store_bytes(skb, 0, &zero, sizeof(zero), 0) < 0)
return TC_ACT_SHOT;
return bpf_redirect_neigh(IFINDEX_DST, NULL, 0, 0);
}
char __license[] SEC("license") = "GPL";
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Intel CE6230 DVB USB driver
*
* Copyright (C) 2009 Antti Palosaari <[email protected]>
*/
#include "ce6230.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
static int ce6230_ctrl_msg(struct dvb_usb_device *d, struct usb_req *req)
{
int ret;
unsigned int pipe;
u8 request;
u8 requesttype;
u16 value;
u16 index;
u8 *buf;
request = req->cmd;
value = req->value;
index = req->index;
switch (req->cmd) {
case I2C_READ:
case DEMOD_READ:
case REG_READ:
requesttype = (USB_TYPE_VENDOR | USB_DIR_IN);
break;
case I2C_WRITE:
case DEMOD_WRITE:
case REG_WRITE:
requesttype = (USB_TYPE_VENDOR | USB_DIR_OUT);
break;
default:
dev_err(&d->udev->dev, "%s: unknown command=%02x\n",
KBUILD_MODNAME, req->cmd);
ret = -EINVAL;
goto error;
}
buf = kmalloc(req->data_len, GFP_KERNEL);
if (!buf) {
ret = -ENOMEM;
goto error;
}
if (requesttype == (USB_TYPE_VENDOR | USB_DIR_OUT)) {
/* write */
memcpy(buf, req->data, req->data_len);
pipe = usb_sndctrlpipe(d->udev, 0);
} else {
/* read */
pipe = usb_rcvctrlpipe(d->udev, 0);
}
msleep(1); /* avoid I2C errors */
ret = usb_control_msg(d->udev, pipe, request, requesttype, value, index,
buf, req->data_len, CE6230_USB_TIMEOUT);
dvb_usb_dbg_usb_control_msg(d->udev, request, requesttype, value, index,
buf, req->data_len);
if (ret < 0)
dev_err(&d->udev->dev, "%s: usb_control_msg() failed=%d\n",
KBUILD_MODNAME, ret);
else
ret = 0;
/* read request, copy returned data to return buf */
if (!ret && requesttype == (USB_TYPE_VENDOR | USB_DIR_IN))
memcpy(req->data, buf, req->data_len);
kfree(buf);
error:
return ret;
}
/* I2C */
static struct zl10353_config ce6230_zl10353_config;
static int ce6230_i2c_master_xfer(struct i2c_adapter *adap,
struct i2c_msg msg[], int num)
{
struct dvb_usb_device *d = i2c_get_adapdata(adap);
int ret = 0, i = 0;
struct usb_req req;
if (num > 2)
return -EOPNOTSUPP;
memset(&req, 0, sizeof(req));
if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
return -EAGAIN;
while (i < num) {
if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) {
if (msg[i].addr ==
ce6230_zl10353_config.demod_address) {
if (msg[i].len < 1) {
i = -EOPNOTSUPP;
break;
}
req.cmd = DEMOD_READ;
req.value = msg[i].addr >> 1;
req.index = msg[i].buf[0];
req.data_len = msg[i+1].len;
req.data = &msg[i+1].buf[0];
ret = ce6230_ctrl_msg(d, &req);
} else {
dev_err(&d->udev->dev, "%s: I2C read not " \
"implemented\n",
KBUILD_MODNAME);
ret = -EOPNOTSUPP;
}
i += 2;
} else {
if (msg[i].addr ==
ce6230_zl10353_config.demod_address) {
if (msg[i].len < 1) {
i = -EOPNOTSUPP;
break;
}
req.cmd = DEMOD_WRITE;
req.value = msg[i].addr >> 1;
req.index = msg[i].buf[0];
req.data_len = msg[i].len-1;
req.data = &msg[i].buf[1];
ret = ce6230_ctrl_msg(d, &req);
} else {
req.cmd = I2C_WRITE;
req.value = 0x2000 + (msg[i].addr >> 1);
req.index = 0x0000;
req.data_len = msg[i].len;
req.data = &msg[i].buf[0];
ret = ce6230_ctrl_msg(d, &req);
}
i += 1;
}
if (ret)
break;
}
mutex_unlock(&d->i2c_mutex);
return ret ? ret : i;
}
static u32 ce6230_i2c_functionality(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static struct i2c_algorithm ce6230_i2c_algorithm = {
.master_xfer = ce6230_i2c_master_xfer,
.functionality = ce6230_i2c_functionality,
};
/* Callbacks for DVB USB */
static struct zl10353_config ce6230_zl10353_config = {
.demod_address = 0x1e,
.adc_clock = 450000,
.if2 = 45700,
.no_tuner = 1,
.parallel_ts = 1,
.clock_ctl_1 = 0x34,
.pll_0 = 0x0e,
};
static int ce6230_zl10353_frontend_attach(struct dvb_usb_adapter *adap)
{
struct dvb_usb_device *d = adap_to_d(adap);
dev_dbg(&d->udev->dev, "%s:\n", __func__);
adap->fe[0] = dvb_attach(zl10353_attach, &ce6230_zl10353_config,
&d->i2c_adap);
if (adap->fe[0] == NULL)
return -ENODEV;
return 0;
}
static struct mxl5005s_config ce6230_mxl5003s_config = {
.i2c_address = 0xc6,
.if_freq = IF_FREQ_4570000HZ,
.xtal_freq = CRYSTAL_FREQ_16000000HZ,
.agc_mode = MXL_SINGLE_AGC,
.tracking_filter = MXL_TF_DEFAULT,
.rssi_enable = MXL_RSSI_ENABLE,
.cap_select = MXL_CAP_SEL_ENABLE,
.div_out = MXL_DIV_OUT_4,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM,
.top = MXL5005S_TOP_25P2,
.mod_mode = MXL_DIGITAL_MODE,
.if_mode = MXL_ZERO_IF,
.AgcMasterByte = 0x00,
};
static int ce6230_mxl5003s_tuner_attach(struct dvb_usb_adapter *adap)
{
struct dvb_usb_device *d = adap_to_d(adap);
int ret;
dev_dbg(&d->udev->dev, "%s:\n", __func__);
ret = dvb_attach(mxl5005s_attach, adap->fe[0], &d->i2c_adap,
&ce6230_mxl5003s_config) == NULL ? -ENODEV : 0;
return ret;
}
static int ce6230_power_ctrl(struct dvb_usb_device *d, int onoff)
{
int ret;
dev_dbg(&d->udev->dev, "%s: onoff=%d\n", __func__, onoff);
/* InterfaceNumber 1 / AlternateSetting 0 idle
InterfaceNumber 1 / AlternateSetting 1 streaming */
ret = usb_set_interface(d->udev, 1, onoff);
if (ret)
dev_err(&d->udev->dev, "%s: usb_set_interface() failed=%d\n",
KBUILD_MODNAME, ret);
return ret;
}
/* DVB USB Driver stuff */
static struct dvb_usb_device_properties ce6230_props = {
.driver_name = KBUILD_MODNAME,
.owner = THIS_MODULE,
.adapter_nr = adapter_nr,
.bInterfaceNumber = 1,
.i2c_algo = &ce6230_i2c_algorithm,
.power_ctrl = ce6230_power_ctrl,
.frontend_attach = ce6230_zl10353_frontend_attach,
.tuner_attach = ce6230_mxl5003s_tuner_attach,
.num_adapters = 1,
.adapter = {
{
.stream = {
.type = USB_BULK,
.count = 6,
.endpoint = 0x82,
.u = {
.bulk = {
.buffersize = (16 * 512),
}
}
},
}
},
};
static const struct usb_device_id ce6230_id_table[] = {
{ DVB_USB_DEVICE(USB_VID_INTEL, USB_PID_INTEL_CE9500,
&ce6230_props, "Intel CE9500 reference design", NULL) },
{ DVB_USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A310,
&ce6230_props, "AVerMedia A310 USB 2.0 DVB-T tuner", NULL) },
{ }
};
MODULE_DEVICE_TABLE(usb, ce6230_id_table);
static struct usb_driver ce6230_usb_driver = {
.name = KBUILD_MODNAME,
.id_table = ce6230_id_table,
.probe = dvb_usbv2_probe,
.disconnect = dvb_usbv2_disconnect,
.suspend = dvb_usbv2_suspend,
.resume = dvb_usbv2_resume,
.reset_resume = dvb_usbv2_reset_resume,
.no_dynamic_id = 1,
.soft_unbind = 1,
};
module_usb_driver(ce6230_usb_driver);
MODULE_AUTHOR("Antti Palosaari <[email protected]>");
MODULE_DESCRIPTION("Intel CE6230 driver");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DDK750_MODE_H__
#define DDK750_MODE_H__
#include "ddk750_chip.h"
enum spolarity {
POS = 0, /* positive */
NEG, /* negative */
};
struct mode_parameter {
/* Horizontal timing. */
unsigned long horizontal_total;
unsigned long horizontal_display_end;
unsigned long horizontal_sync_start;
unsigned long horizontal_sync_width;
enum spolarity horizontal_sync_polarity;
/* Vertical timing. */
unsigned long vertical_total;
unsigned long vertical_display_end;
unsigned long vertical_sync_start;
unsigned long vertical_sync_height;
enum spolarity vertical_sync_polarity;
/* Refresh timing. */
unsigned long pixel_clock;
unsigned long horizontal_frequency;
unsigned long vertical_frequency;
/* Clock Phase. This clock phase only applies to Panel. */
enum spolarity clock_phase_polarity;
};
int ddk750_set_mode_timing(struct mode_parameter *parm, enum clock_type clock);
#endif
|
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <linux/debugfs.h>
#include <linux/kernel.h>
#include <linux/seq_file.h>
#include <linux/version.h>
#include "dr_types.h"
#define DR_DBG_PTR_TO_ID(p) ((u64)(uintptr_t)(p) & 0xFFFFFFFFULL)
enum dr_dump_rec_type {
DR_DUMP_REC_TYPE_DOMAIN = 3000,
DR_DUMP_REC_TYPE_DOMAIN_INFO_FLEX_PARSER = 3001,
DR_DUMP_REC_TYPE_DOMAIN_INFO_DEV_ATTR = 3002,
DR_DUMP_REC_TYPE_DOMAIN_INFO_VPORT = 3003,
DR_DUMP_REC_TYPE_DOMAIN_INFO_CAPS = 3004,
DR_DUMP_REC_TYPE_DOMAIN_SEND_RING = 3005,
DR_DUMP_REC_TYPE_TABLE = 3100,
DR_DUMP_REC_TYPE_TABLE_RX = 3101,
DR_DUMP_REC_TYPE_TABLE_TX = 3102,
DR_DUMP_REC_TYPE_MATCHER = 3200,
DR_DUMP_REC_TYPE_MATCHER_MASK_DEPRECATED = 3201,
DR_DUMP_REC_TYPE_MATCHER_RX = 3202,
DR_DUMP_REC_TYPE_MATCHER_TX = 3203,
DR_DUMP_REC_TYPE_MATCHER_BUILDER = 3204,
DR_DUMP_REC_TYPE_MATCHER_MASK = 3205,
DR_DUMP_REC_TYPE_RULE = 3300,
DR_DUMP_REC_TYPE_RULE_RX_ENTRY_V0 = 3301,
DR_DUMP_REC_TYPE_RULE_TX_ENTRY_V0 = 3302,
DR_DUMP_REC_TYPE_RULE_RX_ENTRY_V1 = 3303,
DR_DUMP_REC_TYPE_RULE_TX_ENTRY_V1 = 3304,
DR_DUMP_REC_TYPE_ACTION_ENCAP_L2 = 3400,
DR_DUMP_REC_TYPE_ACTION_ENCAP_L3 = 3401,
DR_DUMP_REC_TYPE_ACTION_MODIFY_HDR = 3402,
DR_DUMP_REC_TYPE_ACTION_DROP = 3403,
DR_DUMP_REC_TYPE_ACTION_QP = 3404,
DR_DUMP_REC_TYPE_ACTION_FT = 3405,
DR_DUMP_REC_TYPE_ACTION_CTR = 3406,
DR_DUMP_REC_TYPE_ACTION_TAG = 3407,
DR_DUMP_REC_TYPE_ACTION_VPORT = 3408,
DR_DUMP_REC_TYPE_ACTION_DECAP_L2 = 3409,
DR_DUMP_REC_TYPE_ACTION_DECAP_L3 = 3410,
DR_DUMP_REC_TYPE_ACTION_DEVX_TIR = 3411,
DR_DUMP_REC_TYPE_ACTION_PUSH_VLAN = 3412,
DR_DUMP_REC_TYPE_ACTION_POP_VLAN = 3413,
DR_DUMP_REC_TYPE_ACTION_SAMPLER = 3415,
DR_DUMP_REC_TYPE_ACTION_INSERT_HDR = 3420,
DR_DUMP_REC_TYPE_ACTION_REMOVE_HDR = 3421,
DR_DUMP_REC_TYPE_ACTION_MATCH_RANGE = 3425,
};
static struct mlx5dr_dbg_dump_buff *
mlx5dr_dbg_dump_data_init_new_buff(struct mlx5dr_dbg_dump_data *dump_data)
{
struct mlx5dr_dbg_dump_buff *new_buff;
new_buff = kzalloc(sizeof(*new_buff), GFP_KERNEL);
if (!new_buff)
return NULL;
new_buff->buff = kvzalloc(MLX5DR_DEBUG_DUMP_BUFF_SIZE, GFP_KERNEL);
if (!new_buff->buff) {
kfree(new_buff);
return NULL;
}
INIT_LIST_HEAD(&new_buff->node);
list_add_tail(&new_buff->node, &dump_data->buff_list);
return new_buff;
}
static struct mlx5dr_dbg_dump_data *
mlx5dr_dbg_create_dump_data(void)
{
struct mlx5dr_dbg_dump_data *dump_data;
dump_data = kzalloc(sizeof(*dump_data), GFP_KERNEL);
if (!dump_data)
return NULL;
INIT_LIST_HEAD(&dump_data->buff_list);
if (!mlx5dr_dbg_dump_data_init_new_buff(dump_data)) {
kfree(dump_data);
return NULL;
}
return dump_data;
}
static void
mlx5dr_dbg_destroy_dump_data(struct mlx5dr_dbg_dump_data *dump_data)
{
struct mlx5dr_dbg_dump_buff *dump_buff, *tmp_buff;
if (!dump_data)
return;
list_for_each_entry_safe(dump_buff, tmp_buff, &dump_data->buff_list, node) {
kvfree(dump_buff->buff);
list_del(&dump_buff->node);
kfree(dump_buff);
}
kfree(dump_data);
}
static int
mlx5dr_dbg_dump_data_print(struct seq_file *file, char *str, u32 size)
{
struct mlx5dr_domain *dmn = file->private;
struct mlx5dr_dbg_dump_data *dump_data;
struct mlx5dr_dbg_dump_buff *buff;
u32 buff_capacity, write_size;
int remain_size, ret;
if (size >= MLX5DR_DEBUG_DUMP_BUFF_SIZE)
return -EINVAL;
dump_data = dmn->dump_info.dump_data;
buff = list_last_entry(&dump_data->buff_list,
struct mlx5dr_dbg_dump_buff, node);
buff_capacity = (MLX5DR_DEBUG_DUMP_BUFF_SIZE - 1) - buff->index;
remain_size = buff_capacity - size;
write_size = (remain_size > 0) ? size : buff_capacity;
if (likely(write_size)) {
ret = snprintf(buff->buff + buff->index, write_size + 1, "%s", str);
if (ret < 0)
return ret;
buff->index += write_size;
}
if (remain_size < 0) {
remain_size *= -1;
buff = mlx5dr_dbg_dump_data_init_new_buff(dump_data);
if (!buff)
return -ENOMEM;
ret = snprintf(buff->buff, remain_size + 1, "%s", str + write_size);
if (ret < 0)
return ret;
buff->index += remain_size;
}
return 0;
}
void mlx5dr_dbg_tbl_add(struct mlx5dr_table *tbl)
{
mutex_lock(&tbl->dmn->dump_info.dbg_mutex);
list_add_tail(&tbl->dbg_node, &tbl->dmn->dbg_tbl_list);
mutex_unlock(&tbl->dmn->dump_info.dbg_mutex);
}
void mlx5dr_dbg_tbl_del(struct mlx5dr_table *tbl)
{
mutex_lock(&tbl->dmn->dump_info.dbg_mutex);
list_del(&tbl->dbg_node);
mutex_unlock(&tbl->dmn->dump_info.dbg_mutex);
}
void mlx5dr_dbg_rule_add(struct mlx5dr_rule *rule)
{
struct mlx5dr_domain *dmn = rule->matcher->tbl->dmn;
mutex_lock(&dmn->dump_info.dbg_mutex);
list_add_tail(&rule->dbg_node, &rule->matcher->dbg_rule_list);
mutex_unlock(&dmn->dump_info.dbg_mutex);
}
void mlx5dr_dbg_rule_del(struct mlx5dr_rule *rule)
{
struct mlx5dr_domain *dmn = rule->matcher->tbl->dmn;
mutex_lock(&dmn->dump_info.dbg_mutex);
list_del(&rule->dbg_node);
mutex_unlock(&dmn->dump_info.dbg_mutex);
}
static u64 dr_dump_icm_to_idx(u64 icm_addr)
{
return (icm_addr >> 6) & 0xffffffff;
}
#define DR_HEX_SIZE 256
static void
dr_dump_hex_print(char hex[DR_HEX_SIZE], char *src, u32 size)
{
if (WARN_ON_ONCE(DR_HEX_SIZE < 2 * size + 1))
size = DR_HEX_SIZE / 2 - 1; /* truncate */
bin2hex(hex, src, size);
hex[2 * size] = 0; /* NULL-terminate */
}
static int
dr_dump_rule_action_mem(struct seq_file *file, char *buff, const u64 rule_id,
struct mlx5dr_rule_action_member *action_mem)
{
struct mlx5dr_action *action = action_mem->action;
const u64 action_id = DR_DBG_PTR_TO_ID(action);
u64 hit_tbl_ptr, miss_tbl_ptr;
u32 hit_tbl_id, miss_tbl_id;
int ret;
switch (action->action_type) {
case DR_ACTION_TYP_DROP:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx\n",
DR_DUMP_REC_TYPE_ACTION_DROP, action_id,
rule_id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_FT:
if (action->dest_tbl->is_fw_tbl)
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_FT, action_id,
rule_id, action->dest_tbl->fw_tbl.id,
-1);
else
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%llx\n",
DR_DUMP_REC_TYPE_ACTION_FT, action_id,
rule_id, action->dest_tbl->tbl->table_id,
DR_DBG_PTR_TO_ID(action->dest_tbl->tbl));
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_CTR:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_CTR, action_id, rule_id,
action->ctr->ctr_id + action->ctr->offset);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_TAG:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_TAG, action_id, rule_id,
action->flow_tag->flow_tag);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_MODIFY_HDR:
{
struct mlx5dr_ptrn_obj *ptrn = action->rewrite->ptrn;
struct mlx5dr_arg_obj *arg = action->rewrite->arg;
u8 *rewrite_data = action->rewrite->data;
bool ptrn_arg;
int i;
ptrn_arg = !action->rewrite->single_action_opt && ptrn && arg;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,%d,0x%x,0x%x,0x%x",
DR_DUMP_REC_TYPE_ACTION_MODIFY_HDR, action_id,
rule_id, action->rewrite->index,
action->rewrite->single_action_opt,
ptrn_arg ? action->rewrite->num_of_actions : 0,
ptrn_arg ? ptrn->index : 0,
ptrn_arg ? mlx5dr_arg_get_obj_id(arg) : 0);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (ptrn_arg) {
for (i = 0; i < action->rewrite->num_of_actions; i++) {
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
",0x%016llx",
be64_to_cpu(((__be64 *)rewrite_data)[i]));
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
}
}
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, "\n");
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
}
case DR_ACTION_TYP_VPORT:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_VPORT, action_id, rule_id,
action->vport->caps->num);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_TNL_L2_TO_L2:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx\n",
DR_DUMP_REC_TYPE_ACTION_DECAP_L2, action_id,
rule_id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_TNL_L3_TO_L2:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_DECAP_L3, action_id,
rule_id,
(action->rewrite->ptrn && action->rewrite->arg) ?
mlx5dr_arg_get_obj_id(action->rewrite->arg) :
action->rewrite->index);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_L2_TO_TNL_L2:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_ENCAP_L2, action_id,
rule_id, action->reformat->id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_L2_TO_TNL_L3:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_ENCAP_L3, action_id,
rule_id, action->reformat->id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_POP_VLAN:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx\n",
DR_DUMP_REC_TYPE_ACTION_POP_VLAN, action_id,
rule_id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_PUSH_VLAN:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_PUSH_VLAN, action_id,
rule_id, action->push_vlan->vlan_hdr);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_INSERT_HDR:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%x,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_INSERT_HDR, action_id,
rule_id, action->reformat->id,
action->reformat->param_0,
action->reformat->param_1);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_REMOVE_HDR:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%x,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_REMOVE_HDR, action_id,
rule_id, action->reformat->id,
action->reformat->param_0,
action->reformat->param_1);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_SAMPLER:
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%x,0x%x,0x%llx,0x%llx\n",
DR_DUMP_REC_TYPE_ACTION_SAMPLER, action_id,
rule_id, 0, 0, action->sampler->sampler_id,
action->sampler->rx_icm_addr,
action->sampler->tx_icm_addr);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
case DR_ACTION_TYP_RANGE:
if (action->range->hit_tbl_action->dest_tbl->is_fw_tbl) {
hit_tbl_id = action->range->hit_tbl_action->dest_tbl->fw_tbl.id;
hit_tbl_ptr = 0;
} else {
hit_tbl_id = action->range->hit_tbl_action->dest_tbl->tbl->table_id;
hit_tbl_ptr =
DR_DBG_PTR_TO_ID(action->range->hit_tbl_action->dest_tbl->tbl);
}
if (action->range->miss_tbl_action->dest_tbl->is_fw_tbl) {
miss_tbl_id = action->range->miss_tbl_action->dest_tbl->fw_tbl.id;
miss_tbl_ptr = 0;
} else {
miss_tbl_id = action->range->miss_tbl_action->dest_tbl->tbl->table_id;
miss_tbl_ptr =
DR_DBG_PTR_TO_ID(action->range->miss_tbl_action->dest_tbl->tbl);
}
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%llx,0x%x,0x%llx,0x%x\n",
DR_DUMP_REC_TYPE_ACTION_MATCH_RANGE, action_id,
rule_id, hit_tbl_id, hit_tbl_ptr, miss_tbl_id,
miss_tbl_ptr, action->range->definer_id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
break;
default:
return 0;
}
return 0;
}
static int
dr_dump_rule_mem(struct seq_file *file, char *buff, struct mlx5dr_ste *ste,
bool is_rx, const u64 rule_id, u8 format_ver)
{
char hw_ste_dump[DR_HEX_SIZE];
u32 mem_rec_type;
int ret;
if (format_ver == MLX5_STEERING_FORMAT_CONNECTX_5) {
mem_rec_type = is_rx ? DR_DUMP_REC_TYPE_RULE_RX_ENTRY_V0 :
DR_DUMP_REC_TYPE_RULE_TX_ENTRY_V0;
} else {
mem_rec_type = is_rx ? DR_DUMP_REC_TYPE_RULE_RX_ENTRY_V1 :
DR_DUMP_REC_TYPE_RULE_TX_ENTRY_V1;
}
dr_dump_hex_print(hw_ste_dump, (char *)mlx5dr_ste_get_hw_ste(ste),
DR_STE_SIZE_REDUCED);
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,%s\n", mem_rec_type,
dr_dump_icm_to_idx(mlx5dr_ste_get_icm_addr(ste)),
rule_id, hw_ste_dump);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
return 0;
}
static int
dr_dump_rule_rx_tx(struct seq_file *file, char *buff,
struct mlx5dr_rule_rx_tx *rule_rx_tx,
bool is_rx, const u64 rule_id, u8 format_ver)
{
struct mlx5dr_ste *ste_arr[DR_RULE_MAX_STES + DR_ACTION_MAX_STES];
struct mlx5dr_ste *curr_ste = rule_rx_tx->last_rule_ste;
int ret, i;
if (mlx5dr_rule_get_reverse_rule_members(ste_arr, curr_ste, &i))
return 0;
while (i--) {
ret = dr_dump_rule_mem(file, buff, ste_arr[i], is_rx, rule_id,
format_ver);
if (ret < 0)
return ret;
}
return 0;
}
static noinline_for_stack int
dr_dump_rule(struct seq_file *file, struct mlx5dr_rule *rule)
{
struct mlx5dr_rule_action_member *action_mem;
const u64 rule_id = DR_DBG_PTR_TO_ID(rule);
char buff[MLX5DR_DEBUG_DUMP_BUFF_LENGTH];
struct mlx5dr_rule_rx_tx *rx = &rule->rx;
struct mlx5dr_rule_rx_tx *tx = &rule->tx;
u8 format_ver;
int ret;
format_ver = rule->matcher->tbl->dmn->info.caps.sw_format_ver;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx\n", DR_DUMP_REC_TYPE_RULE,
rule_id, DR_DBG_PTR_TO_ID(rule->matcher));
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (rx->nic_matcher) {
ret = dr_dump_rule_rx_tx(file, buff, rx, true, rule_id, format_ver);
if (ret < 0)
return ret;
}
if (tx->nic_matcher) {
ret = dr_dump_rule_rx_tx(file, buff, tx, false, rule_id, format_ver);
if (ret < 0)
return ret;
}
list_for_each_entry(action_mem, &rule->rule_actions_list, list) {
ret = dr_dump_rule_action_mem(file, buff, rule_id, action_mem);
if (ret < 0)
return ret;
}
return 0;
}
static int
dr_dump_matcher_mask(struct seq_file *file, char *buff,
struct mlx5dr_match_param *mask,
u8 criteria, const u64 matcher_id)
{
char dump[DR_HEX_SIZE];
int ret;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, "%d,0x%llx,",
DR_DUMP_REC_TYPE_MATCHER_MASK, matcher_id);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (criteria & DR_MATCHER_CRITERIA_OUTER) {
dr_dump_hex_print(dump, (char *)&mask->outer, sizeof(mask->outer));
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%s,", dump);
} else {
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, ",");
}
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (criteria & DR_MATCHER_CRITERIA_INNER) {
dr_dump_hex_print(dump, (char *)&mask->inner, sizeof(mask->inner));
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%s,", dump);
} else {
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, ",");
}
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (criteria & DR_MATCHER_CRITERIA_MISC) {
dr_dump_hex_print(dump, (char *)&mask->misc, sizeof(mask->misc));
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%s,", dump);
} else {
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, ",");
}
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (criteria & DR_MATCHER_CRITERIA_MISC2) {
dr_dump_hex_print(dump, (char *)&mask->misc2, sizeof(mask->misc2));
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%s,", dump);
} else {
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, ",");
}
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (criteria & DR_MATCHER_CRITERIA_MISC3) {
dr_dump_hex_print(dump, (char *)&mask->misc3, sizeof(mask->misc3));
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%s\n", dump);
} else {
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH, ",\n");
}
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
return 0;
}
static int
dr_dump_matcher_builder(struct seq_file *file, char *buff,
struct mlx5dr_ste_build *builder,
u32 index, bool is_rx, const u64 matcher_id)
{
int ret;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,%d,%d,0x%x\n",
DR_DUMP_REC_TYPE_MATCHER_BUILDER, matcher_id, index,
is_rx, builder->lu_type);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
return 0;
}
static int
dr_dump_matcher_rx_tx(struct seq_file *file, char *buff, bool is_rx,
struct mlx5dr_matcher_rx_tx *matcher_rx_tx,
const u64 matcher_id)
{
enum dr_dump_rec_type rec_type;
u64 s_icm_addr, e_icm_addr;
int i, ret;
rec_type = is_rx ? DR_DUMP_REC_TYPE_MATCHER_RX :
DR_DUMP_REC_TYPE_MATCHER_TX;
s_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(matcher_rx_tx->s_htbl->chunk);
e_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(matcher_rx_tx->e_anchor->chunk);
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,%d,0x%llx,0x%llx\n",
rec_type, DR_DBG_PTR_TO_ID(matcher_rx_tx),
matcher_id, matcher_rx_tx->num_of_builders,
dr_dump_icm_to_idx(s_icm_addr),
dr_dump_icm_to_idx(e_icm_addr));
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
for (i = 0; i < matcher_rx_tx->num_of_builders; i++) {
ret = dr_dump_matcher_builder(file, buff,
&matcher_rx_tx->ste_builder[i],
i, is_rx, matcher_id);
if (ret < 0)
return ret;
}
return 0;
}
static noinline_for_stack int
dr_dump_matcher(struct seq_file *file, struct mlx5dr_matcher *matcher)
{
struct mlx5dr_matcher_rx_tx *rx = &matcher->rx;
struct mlx5dr_matcher_rx_tx *tx = &matcher->tx;
char buff[MLX5DR_DEBUG_DUMP_BUFF_LENGTH];
u64 matcher_id;
int ret;
matcher_id = DR_DBG_PTR_TO_ID(matcher);
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,%d\n", DR_DUMP_REC_TYPE_MATCHER,
matcher_id, DR_DBG_PTR_TO_ID(matcher->tbl),
matcher->prio);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
ret = dr_dump_matcher_mask(file, buff, &matcher->mask,
matcher->match_criteria, matcher_id);
if (ret < 0)
return ret;
if (rx->nic_tbl) {
ret = dr_dump_matcher_rx_tx(file, buff, true, rx, matcher_id);
if (ret < 0)
return ret;
}
if (tx->nic_tbl) {
ret = dr_dump_matcher_rx_tx(file, buff, false, tx, matcher_id);
if (ret < 0)
return ret;
}
return 0;
}
static int
dr_dump_matcher_all(struct seq_file *file, struct mlx5dr_matcher *matcher)
{
struct mlx5dr_rule *rule;
int ret;
ret = dr_dump_matcher(file, matcher);
if (ret < 0)
return ret;
list_for_each_entry(rule, &matcher->dbg_rule_list, dbg_node) {
ret = dr_dump_rule(file, rule);
if (ret < 0)
return ret;
}
return 0;
}
static int
dr_dump_table_rx_tx(struct seq_file *file, char *buff, bool is_rx,
struct mlx5dr_table_rx_tx *table_rx_tx,
const u64 table_id)
{
enum dr_dump_rec_type rec_type;
u64 s_icm_addr;
int ret;
rec_type = is_rx ? DR_DUMP_REC_TYPE_TABLE_RX :
DR_DUMP_REC_TYPE_TABLE_TX;
s_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(table_rx_tx->s_anchor->chunk);
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx\n", rec_type, table_id,
dr_dump_icm_to_idx(s_icm_addr));
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
return 0;
}
static noinline_for_stack int
dr_dump_table(struct seq_file *file, struct mlx5dr_table *table)
{
struct mlx5dr_table_rx_tx *rx = &table->rx;
struct mlx5dr_table_rx_tx *tx = &table->tx;
char buff[MLX5DR_DEBUG_DUMP_BUFF_LENGTH];
int ret;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,%d,%d\n", DR_DUMP_REC_TYPE_TABLE,
DR_DBG_PTR_TO_ID(table), DR_DBG_PTR_TO_ID(table->dmn),
table->table_type, table->level);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
if (rx->nic_dmn) {
ret = dr_dump_table_rx_tx(file, buff, true, rx,
DR_DBG_PTR_TO_ID(table));
if (ret < 0)
return ret;
}
if (tx->nic_dmn) {
ret = dr_dump_table_rx_tx(file, buff, false, tx,
DR_DBG_PTR_TO_ID(table));
if (ret < 0)
return ret;
}
return 0;
}
static int dr_dump_table_all(struct seq_file *file, struct mlx5dr_table *tbl)
{
struct mlx5dr_matcher *matcher;
int ret;
ret = dr_dump_table(file, tbl);
if (ret < 0)
return ret;
list_for_each_entry(matcher, &tbl->matcher_list, list_node) {
ret = dr_dump_matcher_all(file, matcher);
if (ret < 0)
return ret;
}
return 0;
}
static int
dr_dump_send_ring(struct seq_file *file, char *buff,
struct mlx5dr_send_ring *ring,
const u64 domain_id)
{
int ret;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%llx,0x%x,0x%x\n",
DR_DUMP_REC_TYPE_DOMAIN_SEND_RING,
DR_DBG_PTR_TO_ID(ring), domain_id,
ring->cq->mcq.cqn, ring->qp->qpn);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
return 0;
}
static int
dr_dump_domain_info_flex_parser(struct seq_file *file,
char *buff,
const char *flex_parser_name,
const u8 flex_parser_value,
const u64 domain_id)
{
int ret;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,%s,0x%x\n",
DR_DUMP_REC_TYPE_DOMAIN_INFO_FLEX_PARSER, domain_id,
flex_parser_name, flex_parser_value);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
return 0;
}
static int
dr_dump_domain_info_caps(struct seq_file *file, char *buff,
struct mlx5dr_cmd_caps *caps,
const u64 domain_id)
{
struct mlx5dr_cmd_vport_cap *vport_caps;
unsigned long i, vports_num;
int ret;
xa_for_each(&caps->vports.vports_caps_xa, vports_num, vport_caps)
; /* count the number of vports in xarray */
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,0x%x,0x%llx,0x%llx,0x%x,%lu,%d\n",
DR_DUMP_REC_TYPE_DOMAIN_INFO_CAPS, domain_id, caps->gvmi,
caps->nic_rx_drop_address, caps->nic_tx_drop_address,
caps->flex_protocols, vports_num, caps->eswitch_manager);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
xa_for_each(&caps->vports.vports_caps_xa, i, vport_caps) {
vport_caps = xa_load(&caps->vports.vports_caps_xa, i);
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,%lu,0x%x,0x%llx,0x%llx\n",
DR_DUMP_REC_TYPE_DOMAIN_INFO_VPORT,
domain_id, i, vport_caps->vport_gvmi,
vport_caps->icm_address_rx,
vport_caps->icm_address_tx);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
}
return 0;
}
static int
dr_dump_domain_info(struct seq_file *file, char *buff,
struct mlx5dr_domain_info *info,
const u64 domain_id)
{
int ret;
ret = dr_dump_domain_info_caps(file, buff, &info->caps, domain_id);
if (ret < 0)
return ret;
ret = dr_dump_domain_info_flex_parser(file, buff, "icmp_dw0",
info->caps.flex_parser_id_icmp_dw0,
domain_id);
if (ret < 0)
return ret;
ret = dr_dump_domain_info_flex_parser(file, buff, "icmp_dw1",
info->caps.flex_parser_id_icmp_dw1,
domain_id);
if (ret < 0)
return ret;
ret = dr_dump_domain_info_flex_parser(file, buff, "icmpv6_dw0",
info->caps.flex_parser_id_icmpv6_dw0,
domain_id);
if (ret < 0)
return ret;
ret = dr_dump_domain_info_flex_parser(file, buff, "icmpv6_dw1",
info->caps.flex_parser_id_icmpv6_dw1,
domain_id);
if (ret < 0)
return ret;
return 0;
}
static noinline_for_stack int
dr_dump_domain(struct seq_file *file, struct mlx5dr_domain *dmn)
{
char buff[MLX5DR_DEBUG_DUMP_BUFF_LENGTH];
u64 domain_id = DR_DBG_PTR_TO_ID(dmn);
int ret;
ret = snprintf(buff, MLX5DR_DEBUG_DUMP_BUFF_LENGTH,
"%d,0x%llx,%d,0%x,%d,%u.%u.%u,%s,%d,%u,%u,%u\n",
DR_DUMP_REC_TYPE_DOMAIN,
domain_id, dmn->type, dmn->info.caps.gvmi,
dmn->info.supp_sw_steering,
/* package version */
LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
LINUX_VERSION_SUBLEVEL,
pci_name(dmn->mdev->pdev),
0, /* domain flags */
dmn->num_buddies[DR_ICM_TYPE_STE],
dmn->num_buddies[DR_ICM_TYPE_MODIFY_ACTION],
dmn->num_buddies[DR_ICM_TYPE_MODIFY_HDR_PTRN]);
if (ret < 0)
return ret;
ret = mlx5dr_dbg_dump_data_print(file, buff, ret);
if (ret)
return ret;
ret = dr_dump_domain_info(file, buff, &dmn->info, domain_id);
if (ret < 0)
return ret;
if (dmn->info.supp_sw_steering) {
ret = dr_dump_send_ring(file, buff, dmn->send_ring, domain_id);
if (ret < 0)
return ret;
}
return 0;
}
static int dr_dump_domain_all(struct seq_file *file, struct mlx5dr_domain *dmn)
{
struct mlx5dr_table *tbl;
int ret;
mutex_lock(&dmn->dump_info.dbg_mutex);
mlx5dr_domain_lock(dmn);
ret = dr_dump_domain(file, dmn);
if (ret < 0)
goto unlock_mutex;
list_for_each_entry(tbl, &dmn->dbg_tbl_list, dbg_node) {
ret = dr_dump_table_all(file, tbl);
if (ret < 0)
break;
}
unlock_mutex:
mlx5dr_domain_unlock(dmn);
mutex_unlock(&dmn->dump_info.dbg_mutex);
return ret;
}
static void *
dr_dump_start(struct seq_file *file, loff_t *pos)
{
struct mlx5dr_domain *dmn = file->private;
struct mlx5dr_dbg_dump_data *dump_data;
if (atomic_read(&dmn->dump_info.state) != MLX5DR_DEBUG_DUMP_STATE_FREE) {
mlx5_core_warn(dmn->mdev, "Dump already in progress\n");
return ERR_PTR(-EBUSY);
}
atomic_set(&dmn->dump_info.state, MLX5DR_DEBUG_DUMP_STATE_IN_PROGRESS);
dump_data = dmn->dump_info.dump_data;
if (dump_data) {
return seq_list_start(&dump_data->buff_list, *pos);
} else if (*pos == 0) {
dump_data = mlx5dr_dbg_create_dump_data();
if (!dump_data)
goto exit;
dmn->dump_info.dump_data = dump_data;
if (dr_dump_domain_all(file, dmn)) {
mlx5dr_dbg_destroy_dump_data(dump_data);
dmn->dump_info.dump_data = NULL;
goto exit;
}
return seq_list_start(&dump_data->buff_list, *pos);
}
exit:
atomic_set(&dmn->dump_info.state, MLX5DR_DEBUG_DUMP_STATE_FREE);
return NULL;
}
static void *
dr_dump_next(struct seq_file *file, void *v, loff_t *pos)
{
struct mlx5dr_domain *dmn = file->private;
struct mlx5dr_dbg_dump_data *dump_data;
dump_data = dmn->dump_info.dump_data;
return seq_list_next(v, &dump_data->buff_list, pos);
}
static void
dr_dump_stop(struct seq_file *file, void *v)
{
struct mlx5dr_domain *dmn = file->private;
struct mlx5dr_dbg_dump_data *dump_data;
if (v && IS_ERR(v))
return;
if (!v) {
dump_data = dmn->dump_info.dump_data;
if (dump_data) {
mlx5dr_dbg_destroy_dump_data(dump_data);
dmn->dump_info.dump_data = NULL;
}
}
atomic_set(&dmn->dump_info.state, MLX5DR_DEBUG_DUMP_STATE_FREE);
}
static int
dr_dump_show(struct seq_file *file, void *v)
{
struct mlx5dr_dbg_dump_buff *entry;
entry = list_entry(v, struct mlx5dr_dbg_dump_buff, node);
seq_printf(file, "%s", entry->buff);
return 0;
}
static const struct seq_operations dr_dump_sops = {
.start = dr_dump_start,
.next = dr_dump_next,
.stop = dr_dump_stop,
.show = dr_dump_show,
};
DEFINE_SEQ_ATTRIBUTE(dr_dump);
void mlx5dr_dbg_init_dump(struct mlx5dr_domain *dmn)
{
struct mlx5_core_dev *dev = dmn->mdev;
char file_name[128];
if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
mlx5_core_warn(dev,
"Steering dump is not supported for NIC RX/TX domains\n");
return;
}
dmn->dump_info.steering_debugfs =
debugfs_create_dir("steering", mlx5_debugfs_get_dev_root(dev));
dmn->dump_info.fdb_debugfs =
debugfs_create_dir("fdb", dmn->dump_info.steering_debugfs);
sprintf(file_name, "dmn_%p", dmn);
debugfs_create_file(file_name, 0444, dmn->dump_info.fdb_debugfs,
dmn, &dr_dump_fops);
INIT_LIST_HEAD(&dmn->dbg_tbl_list);
mutex_init(&dmn->dump_info.dbg_mutex);
}
void mlx5dr_dbg_uninit_dump(struct mlx5dr_domain *dmn)
{
debugfs_remove_recursive(dmn->dump_info.steering_debugfs);
mutex_destroy(&dmn->dump_info.dbg_mutex);
}
|
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP
*
* (C) Copyright 2014 - 2021, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <2>;
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x20000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <600>;
min-residency-us = <10000>;
};
};
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <1199999988>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp01 {
opp-hz = /bits/ 64 <599999994>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp02 {
opp-hz = /bits/ 64 <399999996>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp03 {
opp-hz = /bits/ 64 <299999997>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rproc_0_fw_image: memory@3ed00000 {
no-map;
reg = <0x0 0x3ed00000 0x0 0x40000>;
};
rproc_1_fw_image: memory@3ef00000 {
no-map;
reg = <0x0 0x3ef00000 0x0 0x40000>;
};
};
zynqmp_ipi: zynqmp-ipi {
bootph-all;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
xlnx,ipi-id = <0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
compatible = "xlnx,zynqmp-ipi-dest-mailbox";
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
<0x0 0xff990ea0 0x0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <4>;
};
};
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
bootph-all;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
method = "smc";
bootph-all;
zynqmp_power: power-management {
bootph-all;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
mbox-names = "tx", "rx";
};
soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
/* efuse access */
efuse_dna: efuse-dna@c {
reg = <0xc 0xc>;
};
efuse_usr0: efuse-usr0@20 {
reg = <0x20 0x4>;
};
efuse_usr1: efuse-usr1@24 {
reg = <0x24 0x4>;
};
efuse_usr2: efuse-usr2@28 {
reg = <0x28 0x4>;
};
efuse_usr3: efuse-usr3@2c {
reg = <0x2c 0x4>;
};
efuse_usr4: efuse-usr4@30 {
reg = <0x30 0x4>;
};
efuse_usr5: efuse-usr5@34 {
reg = <0x34 0x4>;
};
efuse_usr6: efuse-usr6@38 {
reg = <0x38 0x4>;
};
efuse_usr7: efuse-usr7@3c {
reg = <0x3c 0x4>;
};
efuse_miscusr: efuse-miscusr@40 {
reg = <0x40 0x4>;
};
efuse_chash: efuse-chash@50 {
reg = <0x50 0x4>;
};
efuse_pufmisc: efuse-pufmisc@54 {
reg = <0x54 0x4>;
};
efuse_sec: efuse-sec@58 {
reg = <0x58 0x4>;
};
efuse_spkid: efuse-spkid@5c {
reg = <0x5c 0x4>;
};
efuse_aeskey: efuse-aeskey@60 {
reg = <0x60 0x20>;
};
efuse_ppk0hash: efuse-ppk0hash@a0 {
reg = <0xa0 0x30>;
};
efuse_ppk1hash: efuse-ppk1hash@d0 {
reg = <0xd0 0x30>;
};
efuse_pufuser: efuse-pufuser@100 {
reg = <0x100 0x7F>;
};
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
xlnx_aes: zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
pinctrl0: pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
status = "disabled";
};
modepin_gpio: gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <2>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
fpga_full: fpga-region {
compatible = "fpga-region";
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
rproc_lockstep: remoteproc@ffe00000 {
compatible = "xlnx,zynqmp-r5fss";
xlnx,cluster-mode = <1>;
xlnx,tcm-mode = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
<0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
<0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
<0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
r5f@0 {
compatible = "xlnx,zynqmp-r5f";
reg = <0x0 0x0 0x0 0x10000>,
<0x0 0x20000 0x0 0x10000>,
<0x0 0x10000 0x0 0x10000>,
<0x0 0x30000 0x0 0x10000>;
reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
power-domains = <&zynqmp_firmware PD_RPU_0>,
<&zynqmp_firmware PD_R5_0_ATCM>,
<&zynqmp_firmware PD_R5_0_BTCM>,
<&zynqmp_firmware PD_R5_1_ATCM>,
<&zynqmp_firmware PD_R5_1_BTCM>;
memory-region = <&rproc_0_fw_image>;
};
r5f@1 {
compatible = "xlnx,zynqmp-r5f";
reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
reg-names = "atcm0", "btcm0";
power-domains = <&zynqmp_firmware PD_RPU_1>,
<&zynqmp_firmware PD_R5_1_ATCM>,
<&zynqmp_firmware PD_R5_1_BTCM>;
memory-region = <&rproc_1_fw_image>;
};
};
rproc_split: remoteproc-split@ffe00000 {
status = "disabled";
compatible = "xlnx,zynqmp-r5fss";
xlnx,cluster-mode = <0>;
xlnx,tcm-mode = <0>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
<0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
<0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
<0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
r5f@0 {
compatible = "xlnx,zynqmp-r5f";
reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
reg-names = "atcm0", "btcm0";
power-domains = <&zynqmp_firmware PD_RPU_0>,
<&zynqmp_firmware PD_R5_0_ATCM>,
<&zynqmp_firmware PD_R5_0_BTCM>;
memory-region = <&rproc_0_fw_image>;
};
r5f@1 {
compatible = "xlnx,zynqmp-r5f";
reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
reg-names = "atcm0", "btcm0";
power-domains = <&zynqmp_firmware PD_RPU_1>,
<&zynqmp_firmware PD_R5_1_ATCM>,
<&zynqmp_firmware PD_R5_1_BTCM>;
memory-region = <&rproc_1_fw_image>;
};
};
ams {
compatible = "iio-hwmon";
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
};
tsens_apu: thermal-sensor-apu {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&xilinx_ams 7>;
io-channel-names = "sensor-channel";
};
tsens_rpu: thermal-sensor-rpu {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&xilinx_ams 8>;
io-channel-names = "sensor-channel";
};
tsens_pl: thermal-sensor-pl {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&xilinx_ams 20>;
io-channel-names = "sensor-channel";
};
thermal-zones {
apu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tsens_apu>;
trips {
apu_passive: passive {
temperature = <93000>;
hysteresis = <3500>;
type = "passive";
};
apu_critical: critical {
temperature = <96500>;
hysteresis = <3500>;
type = "critical";
};
};
cooling-maps {
map {
trip = <&apu_passive>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
rpu-thermal {
polling-delay = <10000>;
thermal-sensors = <&tsens_rpu>;
trips {
critical {
temperature = <96500>;
hysteresis = <3500>;
type = "critical";
};
};
};
pl-thermal {
polling-delay = <10000>;
thermal-sensors = <&tsens_pl>;
trips {
critical {
temperature = <96500>;
hysteresis = <3500>;
type = "critical";
};
};
};
};
amba: axi {
compatible = "simple-bus";
bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
can0: can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
can1: can@ff070000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff070000 0x0 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
status = "disabled";
reg = <0x0 0xfd6e0000 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
};
};
cpu0_debug: debug@fec10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xfec10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};
cpu1_debug: debug@fed10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xfed10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
};
cpu2_debug: debug@fee10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xfee10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
};
cpu3_debug: debug@fef10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0xfef10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
};
/* GDMA */
fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14e8>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan2: dma-controller@fd510000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14e9>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan3: dma-controller@fd520000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14ea>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan4: dma-controller@fd530000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14eb>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan5: dma-controller@fd540000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14ec>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan6: dma-controller@fd550000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14ed>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan7: dma-controller@fd560000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14ee>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan8: dma-controller@fd570000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
/* iommus = <&smmu 0x14ef>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x0 0x10000>,
<0x0 0xf9020000 0x0 0x20000>,
<0x0 0xf9040000 0x0 0x20000>,
<0x0 0xf9060000 0x0 0x20000>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
/* LPDDMA default allows only secured access. inorder to enable
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.
*/
lpd_dma_chan1: dma-controller@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan2: dma-controller@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan3: dma-controller@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan4: dma-controller@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan5: dma-controller@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan6: dma-controller@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan7: dma-controller@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan8: dma-controller@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
mc: memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
nand0: nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
status = "disabled";
reg = <0x0 0xff100000 0x0 0x1000>;
clock-names = "controller", "bus";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* iommus = <&smmu 0x872>; */
power-domains = <&zynqmp_firmware PD_NAND>;
};
gem0: ethernet@ff0b0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/* iommus = <&smmu 0x874>; */
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
reset-names = "gem0_rst";
};
gem1: ethernet@ff0c0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/* iommus = <&smmu 0x875>; */
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
};
gem2: ethernet@ff0d0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/* iommus = <&smmu 0x876>; */
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
reset-names = "gem2_rst";
};
gem3: ethernet@ff0e0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/* iommus = <&smmu 0x877>; */
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "gem3_rst";
};
gpio: gpio@ff0a0000 {
compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
gpio-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
power-domains = <&zynqmp_firmware PD_GPIO>;
};
i2c0: i2c@ff020000 {
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&zynqmp_firmware PD_I2C_0>;
};
i2c1: i2c@ff030000 {
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&zynqmp_firmware PD_I2C_1>;
};
ocm: memory-controller@ff960000 {
compatible = "xlnx,zynqmp-ocmc-1.0";
reg = <0x0 0xff960000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
pcie: pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
msi-controller;
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
interrupt-names = "misc", "dummy", "intx",
"msi1", "msi0";
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
<0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
/* iommus = <&smmu 0x4d0>; */
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
qspi: spi@ff0f0000 {
bootph-all;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
num-cs = <1>;
reg = <0x0 0xff0f0000 0x0 0x1000>,
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
/* iommus = <&smmu 0x873>; */
power-domains = <&zynqmp_firmware PD_QSPI>;
};
psgtr: phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr-v1.1";
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>;
reg-names = "serdes", "siou";
#phy-cells = <4>;
};
rtc: rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "disabled";
reg = <0x0 0xffa60000 0x0 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "sec";
calibration = <0x7FFF>;
};
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
};
sdhci0: mmc@ff160000 {
bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
/* iommus = <&smmu 0x870>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
};
sdhci1: mmc@ff170000 {
bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
/* iommus = <&smmu 0x871>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
};
smmu: iommu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
#iommu-cells = <1>;
status = "disabled";
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
};
spi0: spi@ff040000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff040000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&zynqmp_firmware PD_SPI_0>;
};
spi1: spi@ff050000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff050000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&zynqmp_firmware PD_SPI_1>;
};
ttc0: timer@ff110000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_0>;
};
ttc1: timer@ff120000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_1>;
};
ttc2: timer@ff130000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_2>;
};
ttc3: timer@ff140000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&zynqmp_firmware PD_TTC_3>;
};
uart0: serial@ff000000 {
bootph-all;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&zynqmp_firmware PD_UART_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_UART0>;
};
uart1: serial@ff010000 {
bootph-all;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&zynqmp_firmware PD_UART_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_UART1>;
};
usb0: usb@ff9d0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
ranges;
dwc3_0: usb@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "host", "peripheral", "otg", "wakeup";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ref";
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
};
};
usb1: usb@ff9e0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_1: usb@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "host", "peripheral", "otg", "wakeup";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ref";
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
};
};
watchdog0: watchdog@fd4d0000 {
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <60>;
reset-on-timeout;
};
lpd_watchdog: watchdog@ff150000 {
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xff150000 0x0 0x1000>;
timeout-sec = <10>;
};
xilinx_ams: ams@ffa50000 {
compatible = "xlnx,zynqmp-ams";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xffa50000 0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
ranges = <0 0 0xffa50800 0x800>;
ams_ps: ams-ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "disabled";
reg = <0x0 0x400>;
};
ams_pl: ams-pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;
};
};
zynqmp_dpdma: dma-controller@fd4c0000 {
compatible = "xlnx,zynqmp-dpdma";
status = "disabled";
reg = <0x0 0xfd4c0000 0x0 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
/* iommus = <&smmu 0xce4>; */
#dma-cells = <1>;
};
zynqmp_dpsub: display@fd4a0000 {
bootph-all;
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,
<0x0 0xfd4aa000 0x0 0x1000>,
<0x0 0xfd4ab000 0x0 0x1000>,
<0x0 0xfd4ac000 0x0 0x1000>;
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* iommus = <&smmu 0xce3>; */
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
dma-names = "vid0", "vid1", "vid2", "gfx0";
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
};
port@5 {
reg = <5>;
};
};
};
};
};
|
// SPDX-License-Identifier: GPL-2.0
/*
* Implement the manual drop-all-pagecache function
*/
#include <linux/pagemap.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/writeback.h>
#include <linux/sysctl.h>
#include <linux/gfp.h>
#include <linux/swap.h>
#include "internal.h"
/* A global variable is a bit ugly, but it keeps the code simple */
int sysctl_drop_caches;
static void drop_pagecache_sb(struct super_block *sb, void *unused)
{
struct inode *inode, *toput_inode = NULL;
spin_lock(&sb->s_inode_list_lock);
list_for_each_entry(inode, &sb->s_inodes, i_sb_list) {
spin_lock(&inode->i_lock);
/*
* We must skip inodes in unusual state. We may also skip
* inodes without pages but we deliberately won't in case
* we need to reschedule to avoid softlockups.
*/
if ((inode->i_state & (I_FREEING|I_WILL_FREE|I_NEW)) ||
(mapping_empty(inode->i_mapping) && !need_resched())) {
spin_unlock(&inode->i_lock);
continue;
}
__iget(inode);
spin_unlock(&inode->i_lock);
spin_unlock(&sb->s_inode_list_lock);
invalidate_mapping_pages(inode->i_mapping, 0, -1);
iput(toput_inode);
toput_inode = inode;
cond_resched();
spin_lock(&sb->s_inode_list_lock);
}
spin_unlock(&sb->s_inode_list_lock);
iput(toput_inode);
}
int drop_caches_sysctl_handler(const struct ctl_table *table, int write,
void *buffer, size_t *length, loff_t *ppos)
{
int ret;
ret = proc_dointvec_minmax(table, write, buffer, length, ppos);
if (ret)
return ret;
if (write) {
static int stfu;
if (sysctl_drop_caches & 1) {
lru_add_drain_all();
iterate_supers(drop_pagecache_sb, NULL);
count_vm_event(DROP_PAGECACHE);
}
if (sysctl_drop_caches & 2) {
drop_slab();
count_vm_event(DROP_SLAB);
}
if (!stfu) {
pr_info("%s (%d): drop_caches: %d\n",
current->comm, task_pid_nr(current),
sysctl_drop_caches);
}
stfu |= sysctl_drop_caches & 4;
}
return 0;
}
|
/*
* Copyright 2009 Jerome Glisse.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
*/
/*
* Authors:
* Jerome Glisse <[email protected]>
* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
* Dave Airlie
*/
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/dma-buf.h>
#include <drm/drm_drv.h>
#include <drm/amdgpu_drm.h>
#include <drm/drm_cache.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_vram_mgr.h"
#include "amdgpu_vm.h"
/**
* DOC: amdgpu_object
*
* This defines the interfaces to operate on an &amdgpu_bo buffer object which
* represents memory used by driver (VRAM, system memory, etc.). The driver
* provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
* to create/destroy/set buffer object which are then managed by the kernel TTM
* memory manager.
* The interfaces are also used internally by kernel clients, including gfx,
* uvd, etc. for kernel managed allocations used by the GPU.
*
*/
static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
{
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
amdgpu_bo_kunmap(bo);
if (bo->tbo.base.import_attach)
drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
drm_gem_object_release(&bo->tbo.base);
amdgpu_bo_unref(&bo->parent);
kvfree(bo);
}
static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
{
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
struct amdgpu_bo_user *ubo;
ubo = to_amdgpu_bo_user(bo);
kfree(ubo->metadata);
amdgpu_bo_destroy(tbo);
}
/**
* amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
* @bo: buffer object to be checked
*
* Uses destroy function associated with the object to determine if this is
* an &amdgpu_bo.
*
* Returns:
* true if the object belongs to &amdgpu_bo, false if not.
*/
bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
{
if (bo->destroy == &amdgpu_bo_destroy ||
bo->destroy == &amdgpu_bo_user_destroy)
return true;
return false;
}
/**
* amdgpu_bo_placement_from_domain - set buffer's placement
* @abo: &amdgpu_bo buffer object whose placement is to be set
* @domain: requested domain
*
* Sets buffer's placement according to requested domain and the buffer's
* flags.
*/
void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct ttm_placement *placement = &abo->placement;
struct ttm_place *places = abo->placements;
u64 flags = abo->flags;
u32 c = 0;
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
if (adev->gmc.mem_partitions && mem_id >= 0) {
places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn;
/*
* memory partition range lpfn is inclusive start + size - 1
* TTM place lpfn is exclusive start + size
*/
places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1;
} else {
places[c].fpfn = 0;
places[c].lpfn = 0;
}
places[c].mem_type = TTM_PL_VRAM;
places[c].flags = 0;
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
else
places[c].flags |= TTM_PL_FLAG_TOPDOWN;
if (abo->tbo.type == ttm_bo_type_kernel &&
flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = AMDGPU_PL_DOORBELL;
places[c].flags = 0;
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_GTT) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type =
abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
AMDGPU_PL_PREEMPT : TTM_PL_TT;
places[c].flags = 0;
/*
* When GTT is just an alternative to VRAM make sure that we
* only use it as fallback and still try to fill up VRAM first.
*/
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
!(adev->flags & AMD_IS_APU))
places[c].flags |= TTM_PL_FLAG_FALLBACK;
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_CPU) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = TTM_PL_SYSTEM;
places[c].flags = 0;
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_GDS) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = AMDGPU_PL_GDS;
places[c].flags = 0;
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_GWS) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = AMDGPU_PL_GWS;
places[c].flags = 0;
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_OA) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = AMDGPU_PL_OA;
places[c].flags = 0;
c++;
}
if (!c) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = TTM_PL_SYSTEM;
places[c].flags = 0;
c++;
}
BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
placement->num_placement = c;
placement->placement = places;
}
/**
* amdgpu_bo_create_reserved - create reserved BO for kernel use
*
* @adev: amdgpu device object
* @size: size for the new BO
* @align: alignment for the new BO
* @domain: where to place it
* @bo_ptr: used to initialize BOs in structures
* @gpu_addr: GPU addr of the pinned BO
* @cpu_addr: optional CPU address mapping
*
* Allocates and pins a BO for kernel internal use, and returns it still
* reserved.
*
* Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
*
* Returns:
* 0 on success, negative error code otherwise.
*/
int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
unsigned long size, int align,
u32 domain, struct amdgpu_bo **bo_ptr,
u64 *gpu_addr, void **cpu_addr)
{
struct amdgpu_bo_param bp;
bool free = false;
int r;
if (!size) {
amdgpu_bo_unref(bo_ptr);
return 0;
}
memset(&bp, 0, sizeof(bp));
bp.size = size;
bp.byte_align = align;
bp.domain = domain;
bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
if (!*bo_ptr) {
r = amdgpu_bo_create(adev, &bp, bo_ptr);
if (r) {
dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
r);
return r;
}
free = true;
}
r = amdgpu_bo_reserve(*bo_ptr, false);
if (r) {
dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
goto error_free;
}
r = amdgpu_bo_pin(*bo_ptr, domain);
if (r) {
dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
goto error_unreserve;
}
r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
if (r) {
dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
goto error_unpin;
}
if (gpu_addr)
*gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
if (cpu_addr) {
r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
if (r) {
dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
goto error_unpin;
}
}
return 0;
error_unpin:
amdgpu_bo_unpin(*bo_ptr);
error_unreserve:
amdgpu_bo_unreserve(*bo_ptr);
error_free:
if (free)
amdgpu_bo_unref(bo_ptr);
return r;
}
/**
* amdgpu_bo_create_kernel - create BO for kernel use
*
* @adev: amdgpu device object
* @size: size for the new BO
* @align: alignment for the new BO
* @domain: where to place it
* @bo_ptr: used to initialize BOs in structures
* @gpu_addr: GPU addr of the pinned BO
* @cpu_addr: optional CPU address mapping
*
* Allocates and pins a BO for kernel internal use.
*
* Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
*
* Returns:
* 0 on success, negative error code otherwise.
*/
int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
unsigned long size, int align,
u32 domain, struct amdgpu_bo **bo_ptr,
u64 *gpu_addr, void **cpu_addr)
{
int r;
r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
gpu_addr, cpu_addr);
if (r)
return r;
if (*bo_ptr)
amdgpu_bo_unreserve(*bo_ptr);
return 0;
}
/**
* amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
*
* @adev: amdgpu device object
* @offset: offset of the BO
* @size: size of the BO
* @bo_ptr: used to initialize BOs in structures
* @cpu_addr: optional CPU address mapping
*
* Creates a kernel BO at a specific offset in VRAM.
*
* Returns:
* 0 on success, negative error code otherwise.
*/
int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
uint64_t offset, uint64_t size,
struct amdgpu_bo **bo_ptr, void **cpu_addr)
{
struct ttm_operation_ctx ctx = { false, false };
unsigned int i;
int r;
offset &= PAGE_MASK;
size = ALIGN(size, PAGE_SIZE);
r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL,
cpu_addr);
if (r)
return r;
if ((*bo_ptr) == NULL)
return 0;
/*
* Remove the original mem node and create a new one at the request
* position.
*/
if (cpu_addr)
amdgpu_bo_kunmap(*bo_ptr);
ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
}
r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
&(*bo_ptr)->tbo.resource, &ctx);
if (r)
goto error;
if (cpu_addr) {
r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
if (r)
goto error;
}
amdgpu_bo_unreserve(*bo_ptr);
return 0;
error:
amdgpu_bo_unreserve(*bo_ptr);
amdgpu_bo_unref(bo_ptr);
return r;
}
/**
* amdgpu_bo_free_kernel - free BO for kernel use
*
* @bo: amdgpu BO to free
* @gpu_addr: pointer to where the BO's GPU memory space address was stored
* @cpu_addr: pointer to where the BO's CPU memory space address was stored
*
* unmaps and unpin a BO for kernel internal use.
*/
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr)
{
if (*bo == NULL)
return;
WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
if (cpu_addr)
amdgpu_bo_kunmap(*bo);
amdgpu_bo_unpin(*bo);
amdgpu_bo_unreserve(*bo);
}
amdgpu_bo_unref(bo);
if (gpu_addr)
*gpu_addr = 0;
if (cpu_addr)
*cpu_addr = NULL;
}
/* Validate bo size is bit bigger than the request domain */
static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
unsigned long size, u32 domain)
{
struct ttm_resource_manager *man = NULL;
/*
* If GTT is part of requested domains the check must succeed to
* allow fall back to GTT.
*/
if (domain & AMDGPU_GEM_DOMAIN_GTT)
man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
else if (domain & AMDGPU_GEM_DOMAIN_VRAM)
man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
else
return true;
if (!man) {
if (domain & AMDGPU_GEM_DOMAIN_GTT)
WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
return false;
}
/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */
if (size < man->size)
return true;
DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size);
return false;
}
bool amdgpu_bo_support_uswc(u64 bo_flags)
{
#ifdef CONFIG_X86_32
/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
* See https://bugs.freedesktop.org/show_bug.cgi?id=84627
*/
return false;
#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
/* Don't try to enable write-combining when it can't work, or things
* may be slow
* See https://bugs.freedesktop.org/show_bug.cgi?id=88758
*/
#ifndef CONFIG_COMPILE_TEST
#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
thanks to write-combining
#endif
if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
"better performance thanks to write-combining\n");
return false;
#else
/* For architectures that don't support WC memory,
* mask out the WC flag from the BO
*/
if (!drm_arch_can_wc_memory())
return false;
return true;
#endif
}
/**
* amdgpu_bo_create - create an &amdgpu_bo buffer object
* @adev: amdgpu device object
* @bp: parameters to be used for the buffer object
* @bo_ptr: pointer to the buffer object pointer
*
* Creates an &amdgpu_bo buffer object.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_create(struct amdgpu_device *adev,
struct amdgpu_bo_param *bp,
struct amdgpu_bo **bo_ptr)
{
struct ttm_operation_ctx ctx = {
.interruptible = (bp->type != ttm_bo_type_kernel),
.no_wait_gpu = bp->no_wait_gpu,
/* We opt to avoid OOM on system pages allocations */
.gfp_retry_mayfail = true,
.allow_res_evict = bp->type != ttm_bo_type_kernel,
.resv = bp->resv
};
struct amdgpu_bo *bo;
unsigned long page_align, size = bp->size;
int r;
/* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
/* GWS and OA don't need any alignment. */
page_align = bp->byte_align;
size <<= PAGE_SHIFT;
} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
/* Both size and alignment must be a multiple of 4. */
page_align = ALIGN(bp->byte_align, 4);
size = ALIGN(size, 4) << PAGE_SHIFT;
} else {
/* Memory should be aligned at least to a page size. */
page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
size = ALIGN(size, PAGE_SIZE);
}
if (!amdgpu_bo_validate_size(adev, size, bp->domain))
return -ENOMEM;
BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
*bo_ptr = NULL;
bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
if (bo == NULL)
return -ENOMEM;
drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
bo->tbo.base.funcs = &amdgpu_gem_object_funcs;
bo->vm_bo = NULL;
bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
bp->domain;
bo->allowed_domains = bo->preferred_domains;
if (bp->type != ttm_bo_type_kernel &&
!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&
bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
bo->flags = bp->flags;
if (adev->gmc.mem_partitions)
/* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */
bo->xcp_id = bp->xcp_id_plus1 - 1;
else
/* For GPUs without spatial partitioning */
bo->xcp_id = 0;
if (!amdgpu_bo_support_uswc(bo->flags))
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bo->tbo.bdev = &adev->mman.bdev;
if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
AMDGPU_GEM_DOMAIN_GDS))
amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
else
amdgpu_bo_placement_from_domain(bo, bp->domain);
if (bp->type == ttm_bo_type_kernel)
bo->tbo.priority = 2;
else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE))
bo->tbo.priority = 1;
if (!bp->destroy)
bp->destroy = &amdgpu_bo_destroy;
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
&bo->placement, page_align, &ctx, NULL,
bp->resv, bp->destroy);
if (unlikely(r != 0))
return r;
if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
amdgpu_res_cpu_visible(adev, bo->tbo.resource))
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
ctx.bytes_moved);
else
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.resource->mem_type == TTM_PL_VRAM) {
struct dma_fence *fence;
r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
if (unlikely(r))
goto fail_unreserve;
dma_resv_add_fence(bo->tbo.base.resv, fence,
DMA_RESV_USAGE_KERNEL);
dma_fence_put(fence);
}
if (!bp->resv)
amdgpu_bo_unreserve(bo);
*bo_ptr = bo;
trace_amdgpu_bo_create(bo);
/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
if (bp->type == ttm_bo_type_device)
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
return 0;
fail_unreserve:
if (!bp->resv)
dma_resv_unlock(bo->tbo.base.resv);
amdgpu_bo_unref(&bo);
return r;
}
/**
* amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
* @adev: amdgpu device object
* @bp: parameters to be used for the buffer object
* @ubo_ptr: pointer to the buffer object pointer
*
* Create a BO to be used by user application;
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo_param *bp,
struct amdgpu_bo_user **ubo_ptr)
{
struct amdgpu_bo *bo_ptr;
int r;
bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
bp->destroy = &amdgpu_bo_user_destroy;
r = amdgpu_bo_create(adev, bp, &bo_ptr);
if (r)
return r;
*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
return r;
}
/**
* amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
* @adev: amdgpu device object
* @bp: parameters to be used for the buffer object
* @vmbo_ptr: pointer to the buffer object pointer
*
* Create a BO to be for GPUVM.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_create_vm(struct amdgpu_device *adev,
struct amdgpu_bo_param *bp,
struct amdgpu_bo_vm **vmbo_ptr)
{
struct amdgpu_bo *bo_ptr;
int r;
/* bo_ptr_size will be determined by the caller and it depends on
* num of amdgpu_vm_pt entries.
*/
BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
r = amdgpu_bo_create(adev, bp, &bo_ptr);
if (r)
return r;
*vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
return r;
}
/**
* amdgpu_bo_kmap - map an &amdgpu_bo buffer object
* @bo: &amdgpu_bo buffer object to be mapped
* @ptr: kernel virtual address to be returned
*
* Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
* amdgpu_bo_kptr() to get the kernel virtual address.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
{
void *kptr;
long r;
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
return -EPERM;
r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
false, MAX_SCHEDULE_TIMEOUT);
if (r < 0)
return r;
kptr = amdgpu_bo_kptr(bo);
if (kptr) {
if (ptr)
*ptr = kptr;
return 0;
}
r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
if (r)
return r;
if (ptr)
*ptr = amdgpu_bo_kptr(bo);
return 0;
}
/**
* amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
* @bo: &amdgpu_bo buffer object
*
* Calls ttm_kmap_obj_virtual() to get the kernel virtual address
*
* Returns:
* the virtual address of a buffer object area.
*/
void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
{
bool is_iomem;
return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
}
/**
* amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
* @bo: &amdgpu_bo buffer object to be unmapped
*
* Unmaps a kernel map set up by amdgpu_bo_kmap().
*/
void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
{
if (bo->kmap.bo)
ttm_bo_kunmap(&bo->kmap);
}
/**
* amdgpu_bo_ref - reference an &amdgpu_bo buffer object
* @bo: &amdgpu_bo buffer object
*
* References the contained &ttm_buffer_object.
*
* Returns:
* a refcounted pointer to the &amdgpu_bo buffer object.
*/
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
{
if (bo == NULL)
return NULL;
drm_gem_object_get(&bo->tbo.base);
return bo;
}
/**
* amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
* @bo: &amdgpu_bo buffer object
*
* Unreferences the contained &ttm_buffer_object and clear the pointer
*/
void amdgpu_bo_unref(struct amdgpu_bo **bo)
{
if ((*bo) == NULL)
return;
drm_gem_object_put(&(*bo)->tbo.base);
*bo = NULL;
}
/**
* amdgpu_bo_pin - pin an &amdgpu_bo buffer object
* @bo: &amdgpu_bo buffer object to be pinned
* @domain: domain to be pinned to
*
* Pins the buffer object according to requested domain. If the memory is
* unbound gart memory, binds the pages into gart table. Adjusts pin_count and
* pin_size accordingly.
*
* Pinning means to lock pages in memory along with keeping them at a fixed
* offset. It is required when a buffer can not be moved, for example, when
* a display buffer is being scanned out.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct ttm_operation_ctx ctx = { false, false };
int r, i;
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
return -EPERM;
/* Check domain to be pinned to against preferred domains */
if (bo->preferred_domains & domain)
domain = bo->preferred_domains & domain;
/* A shared bo cannot be migrated to VRAM */
if (bo->tbo.base.import_attach) {
if (domain & AMDGPU_GEM_DOMAIN_GTT)
domain = AMDGPU_GEM_DOMAIN_GTT;
else
return -EINVAL;
}
if (bo->tbo.pin_count) {
uint32_t mem_type = bo->tbo.resource->mem_type;
uint32_t mem_flags = bo->tbo.resource->placement;
if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
return -EINVAL;
if ((mem_type == TTM_PL_VRAM) &&
(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
!(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
return -EINVAL;
ttm_bo_pin(&bo->tbo);
return 0;
}
/* This assumes only APU display buffers are pinned with (VRAM|GTT).
* See function amdgpu_display_supported_domains()
*/
domain = amdgpu_bo_get_preferred_domain(adev, domain);
if (bo->tbo.base.import_attach)
dma_buf_pin(bo->tbo.base.import_attach);
/* force to pin into visible video ram */
if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
amdgpu_bo_placement_from_domain(bo, domain);
for (i = 0; i < bo->placement.num_placement; i++) {
if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &&
bo->placements[i].mem_type == TTM_PL_VRAM)
bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
}
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (unlikely(r)) {
dev_err(adev->dev, "%p pin failed\n", bo);
goto error;
}
ttm_bo_pin(&bo->tbo);
if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
&adev->visible_pin_size);
} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
}
error:
return r;
}
/**
* amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
* @bo: &amdgpu_bo buffer object to be unpinned
*
* Decreases the pin_count, and clears the flags if pin_count reaches 0.
* Changes placement and pin size accordingly.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
void amdgpu_bo_unpin(struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
ttm_bo_unpin(&bo->tbo);
if (bo->tbo.pin_count)
return;
if (bo->tbo.base.import_attach)
dma_buf_unpin(bo->tbo.base.import_attach);
if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
&adev->visible_pin_size);
} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
}
}
static const char * const amdgpu_vram_names[] = {
"UNKNOWN",
"GDDR1",
"DDR2",
"GDDR3",
"GDDR4",
"GDDR5",
"HBM",
"DDR3",
"DDR4",
"GDDR6",
"DDR5",
"LPDDR4",
"LPDDR5"
};
/**
* amdgpu_bo_init - initialize memory manager
* @adev: amdgpu device object
*
* Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_init(struct amdgpu_device *adev)
{
/* On A+A platform, VRAM can be mapped as WB */
if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
/* reserve PAT memory space to WC for VRAM */
int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
adev->gmc.aper_size);
if (r) {
DRM_ERROR("Unable to set WC memtype for the aperture base\n");
return r;
}
/* Add an MTRR for the VRAM */
adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
adev->gmc.aper_size);
}
DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
adev->gmc.mc_vram_size >> 20,
(unsigned long long)adev->gmc.aper_size >> 20);
DRM_INFO("RAM width %dbits %s\n",
adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
return amdgpu_ttm_init(adev);
}
/**
* amdgpu_bo_fini - tear down memory manager
* @adev: amdgpu device object
*
* Reverses amdgpu_bo_init() to tear down memory manager.
*/
void amdgpu_bo_fini(struct amdgpu_device *adev)
{
int idx;
amdgpu_ttm_fini(adev);
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
arch_phys_wc_del(adev->gmc.vram_mtrr);
arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
}
drm_dev_exit(idx);
}
}
/**
* amdgpu_bo_set_tiling_flags - set tiling flags
* @bo: &amdgpu_bo buffer object
* @tiling_flags: new flags
*
* Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
* kernel driver to set the tiling flags on a buffer.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_bo_user *ubo;
BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
if (adev->family <= AMDGPU_FAMILY_CZ &&
AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
return -EINVAL;
ubo = to_amdgpu_bo_user(bo);
ubo->tiling_flags = tiling_flags;
return 0;
}
/**
* amdgpu_bo_get_tiling_flags - get tiling flags
* @bo: &amdgpu_bo buffer object
* @tiling_flags: returned flags
*
* Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
* set the tiling flags on a buffer.
*/
void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
{
struct amdgpu_bo_user *ubo;
BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
dma_resv_assert_held(bo->tbo.base.resv);
ubo = to_amdgpu_bo_user(bo);
if (tiling_flags)
*tiling_flags = ubo->tiling_flags;
}
/**
* amdgpu_bo_set_metadata - set metadata
* @bo: &amdgpu_bo buffer object
* @metadata: new metadata
* @metadata_size: size of the new metadata
* @flags: flags of the new metadata
*
* Sets buffer object's metadata, its size and flags.
* Used via GEM ioctl.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata,
u32 metadata_size, uint64_t flags)
{
struct amdgpu_bo_user *ubo;
void *buffer;
BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
ubo = to_amdgpu_bo_user(bo);
if (!metadata_size) {
if (ubo->metadata_size) {
kfree(ubo->metadata);
ubo->metadata = NULL;
ubo->metadata_size = 0;
}
return 0;
}
if (metadata == NULL)
return -EINVAL;
buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
if (buffer == NULL)
return -ENOMEM;
kfree(ubo->metadata);
ubo->metadata_flags = flags;
ubo->metadata = buffer;
ubo->metadata_size = metadata_size;
return 0;
}
/**
* amdgpu_bo_get_metadata - get metadata
* @bo: &amdgpu_bo buffer object
* @buffer: returned metadata
* @buffer_size: size of the buffer
* @metadata_size: size of the returned metadata
* @flags: flags of the returned metadata
*
* Gets buffer object's metadata, its size and flags. buffer_size shall not be
* less than metadata_size.
* Used via GEM ioctl.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
size_t buffer_size, uint32_t *metadata_size,
uint64_t *flags)
{
struct amdgpu_bo_user *ubo;
if (!buffer && !metadata_size)
return -EINVAL;
BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
ubo = to_amdgpu_bo_user(bo);
if (metadata_size)
*metadata_size = ubo->metadata_size;
if (buffer) {
if (buffer_size < ubo->metadata_size)
return -EINVAL;
if (ubo->metadata_size)
memcpy(buffer, ubo->metadata, ubo->metadata_size);
}
if (flags)
*flags = ubo->metadata_flags;
return 0;
}
/**
* amdgpu_bo_move_notify - notification about a memory move
* @bo: pointer to a buffer object
* @evict: if this move is evicting the buffer from the graphics address space
* @new_mem: new resource for backing the BO
*
* Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
* bookkeeping.
* TTM driver callback which is called when ttm moves a buffer.
*/
void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
bool evict,
struct ttm_resource *new_mem)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_resource *old_mem = bo->resource;
struct amdgpu_bo *abo;
if (!amdgpu_bo_is_amdgpu_bo(bo))
return;
abo = ttm_to_amdgpu_bo(bo);
amdgpu_vm_bo_invalidate(adev, abo, evict);
amdgpu_bo_kunmap(abo);
if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
old_mem && old_mem->mem_type != TTM_PL_SYSTEM)
dma_buf_move_notify(abo->tbo.base.dma_buf);
/* move_notify is called before move happens */
trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1,
old_mem ? old_mem->mem_type : -1);
}
void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
struct amdgpu_mem_stats *stats,
unsigned int sz)
{
const unsigned int domain_to_pl[] = {
[ilog2(AMDGPU_GEM_DOMAIN_CPU)] = TTM_PL_SYSTEM,
[ilog2(AMDGPU_GEM_DOMAIN_GTT)] = TTM_PL_TT,
[ilog2(AMDGPU_GEM_DOMAIN_VRAM)] = TTM_PL_VRAM,
[ilog2(AMDGPU_GEM_DOMAIN_GDS)] = AMDGPU_PL_GDS,
[ilog2(AMDGPU_GEM_DOMAIN_GWS)] = AMDGPU_PL_GWS,
[ilog2(AMDGPU_GEM_DOMAIN_OA)] = AMDGPU_PL_OA,
[ilog2(AMDGPU_GEM_DOMAIN_DOORBELL)] = AMDGPU_PL_DOORBELL,
};
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct ttm_resource *res = bo->tbo.resource;
struct drm_gem_object *obj = &bo->tbo.base;
uint64_t size = amdgpu_bo_size(bo);
unsigned int type;
if (!res) {
/*
* If no backing store use one of the preferred domain for basic
* stats. We take the MSB since that should give a reasonable
* view.
*/
BUILD_BUG_ON(TTM_PL_VRAM < TTM_PL_TT ||
TTM_PL_VRAM < TTM_PL_SYSTEM);
type = fls(bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK);
if (!type)
return;
type--;
if (drm_WARN_ON_ONCE(&adev->ddev,
type >= ARRAY_SIZE(domain_to_pl)))
return;
type = domain_to_pl[type];
} else {
type = res->mem_type;
}
if (drm_WARN_ON_ONCE(&adev->ddev, type >= sz))
return;
/* DRM stats common fields: */
if (drm_gem_object_is_shared_for_memory_stats(obj))
stats[type].drm.shared += size;
else
stats[type].drm.private += size;
if (res) {
stats[type].drm.resident += size;
if (!dma_resv_test_signaled(obj->resv, DMA_RESV_USAGE_BOOKKEEP))
stats[type].drm.active += size;
else if (bo->flags & AMDGPU_GEM_CREATE_DISCARDABLE)
stats[type].drm.purgeable += size;
}
/* amdgpu specific stats: */
if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) {
stats[TTM_PL_VRAM].requested += size;
if (type != TTM_PL_VRAM)
stats[TTM_PL_VRAM].evicted += size;
} else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) {
stats[TTM_PL_TT].requested += size;
}
}
/**
* amdgpu_bo_release_notify - notification about a BO being released
* @bo: pointer to a buffer object
*
* Wipes VRAM buffers whose contents should not be leaked before the
* memory is released.
*/
void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct dma_fence *fence = NULL;
struct amdgpu_bo *abo;
int r;
if (!amdgpu_bo_is_amdgpu_bo(bo))
return;
abo = ttm_to_amdgpu_bo(bo);
WARN_ON(abo->vm_bo);
if (abo->kfd_bo)
amdgpu_amdkfd_release_notify(abo);
/* We only remove the fence if the resv has individualized. */
WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
&& bo->base.resv != &bo->base._resv);
if (bo->base.resv == &bo->base._resv)
amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
!(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
return;
if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
return;
r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true);
if (!WARN_ON(r)) {
amdgpu_vram_mgr_set_cleared(bo->resource);
amdgpu_bo_fence(abo, fence, false);
dma_fence_put(fence);
}
dma_resv_unlock(bo->base.resv);
}
/**
* amdgpu_bo_fault_reserve_notify - notification about a memory fault
* @bo: pointer to a buffer object
*
* Notifies the driver we are taking a fault on this BO and have reserved it,
* also performs bookkeeping.
* TTM driver callback for dealing with vm faults.
*
* Returns:
* 0 for success or a negative error code on failure.
*/
vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false, false };
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
int r;
/* Remember that this BO was accessed by the CPU */
abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
if (amdgpu_res_cpu_visible(adev, bo->resource))
return 0;
/* Can't move a pinned BO to visible VRAM */
if (abo->tbo.pin_count > 0)
return VM_FAULT_SIGBUS;
/* hurrah the memory is not visible ! */
atomic64_inc(&adev->num_vram_cpu_page_faults);
amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
AMDGPU_GEM_DOMAIN_GTT);
/* Avoid costly evictions; only set GTT as a busy placement */
abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
r = ttm_bo_validate(bo, &abo->placement, &ctx);
if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
return VM_FAULT_NOPAGE;
else if (unlikely(r))
return VM_FAULT_SIGBUS;
/* this should never happen */
if (bo->resource->mem_type == TTM_PL_VRAM &&
!amdgpu_res_cpu_visible(adev, bo->resource))
return VM_FAULT_SIGBUS;
ttm_bo_move_to_lru_tail_unlocked(bo);
return 0;
}
/**
* amdgpu_bo_fence - add fence to buffer object
*
* @bo: buffer object in question
* @fence: fence to add
* @shared: true if fence should be added shared
*
*/
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
bool shared)
{
struct dma_resv *resv = bo->tbo.base.resv;
int r;
r = dma_resv_reserve_fences(resv, 1);
if (r) {
/* As last resort on OOM we block for the fence */
dma_fence_wait(fence, false);
return;
}
dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :
DMA_RESV_USAGE_WRITE);
}
/**
* amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
*
* @adev: amdgpu device pointer
* @resv: reservation object to sync to
* @sync_mode: synchronization mode
* @owner: fence owner
* @intr: Whether the wait is interruptible
*
* Extract the fences from the reservation object and waits for them to finish.
*
* Returns:
* 0 on success, errno otherwise.
*/
int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
enum amdgpu_sync_mode sync_mode, void *owner,
bool intr)
{
struct amdgpu_sync sync;
int r;
amdgpu_sync_create(&sync);
amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
r = amdgpu_sync_wait(&sync, intr);
amdgpu_sync_free(&sync);
return r;
}
/**
* amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
* @bo: buffer object to wait for
* @owner: fence owner
* @intr: Whether the wait is interruptible
*
* Wrapper to wait for fences in a BO.
* Returns:
* 0 on success, errno otherwise.
*/
int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
AMDGPU_SYNC_NE_OWNER, owner, intr);
}
/**
* amdgpu_bo_gpu_offset - return GPU offset of bo
* @bo: amdgpu object for which we query the offset
*
* Note: object should either be pinned or reserved when calling this
* function, it might be useful to add check for this for debugging.
*
* Returns:
* current GPU offset of the object.
*/
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
{
WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
!bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
!(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
return amdgpu_bo_gpu_offset_no_check(bo);
}
/**
* amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
* @bo: amdgpu object for which we query the offset
*
* Returns:
* current GPU offset of the object without raising warnings.
*/
u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
if (bo->tbo.resource->mem_type == TTM_PL_TT)
offset = amdgpu_gmc_agp_addr(&bo->tbo);
if (offset == AMDGPU_BO_INVALID_OFFSET)
offset = (bo->tbo.resource->start << PAGE_SHIFT) +
amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
return amdgpu_gmc_sign_extend(offset);
}
/**
* amdgpu_bo_get_preferred_domain - get preferred domain
* @adev: amdgpu device object
* @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
*
* Returns:
* Which of the allowed domains is preferred for allocating the BO.
*/
uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
uint32_t domain)
{
if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
domain = AMDGPU_GEM_DOMAIN_VRAM;
if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
domain = AMDGPU_GEM_DOMAIN_GTT;
}
return domain;
}
#if defined(CONFIG_DEBUG_FS)
#define amdgpu_bo_print_flag(m, bo, flag) \
do { \
if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
seq_printf((m), " " #flag); \
} \
} while (0)
/**
* amdgpu_bo_print_info - print BO info in debugfs file
*
* @id: Index or Id of the BO
* @bo: Requested BO for printing info
* @m: debugfs file
*
* Print BO information in debugfs file
*
* Returns:
* Size of the BO in bytes.
*/
u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct dma_buf_attachment *attachment;
struct dma_buf *dma_buf;
const char *placement;
unsigned int pin_count;
u64 size;
if (dma_resv_trylock(bo->tbo.base.resv)) {
if (!bo->tbo.resource) {
placement = "NONE";
} else {
switch (bo->tbo.resource->mem_type) {
case TTM_PL_VRAM:
if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
placement = "VRAM VISIBLE";
else
placement = "VRAM";
break;
case TTM_PL_TT:
placement = "GTT";
break;
case AMDGPU_PL_GDS:
placement = "GDS";
break;
case AMDGPU_PL_GWS:
placement = "GWS";
break;
case AMDGPU_PL_OA:
placement = "OA";
break;
case AMDGPU_PL_PREEMPT:
placement = "PREEMPTIBLE";
break;
case AMDGPU_PL_DOORBELL:
placement = "DOORBELL";
break;
case TTM_PL_SYSTEM:
default:
placement = "CPU";
break;
}
}
dma_resv_unlock(bo->tbo.base.resv);
} else {
placement = "UNKNOWN";
}
size = amdgpu_bo_size(bo);
seq_printf(m, "\t\t0x%08x: %12lld byte %s",
id, size, placement);
pin_count = READ_ONCE(bo->tbo.pin_count);
if (pin_count)
seq_printf(m, " pin count %d", pin_count);
dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
attachment = READ_ONCE(bo->tbo.base.import_attach);
if (attachment)
seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino);
else if (dma_buf)
seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino);
amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
seq_puts(m, "\n");
return size;
}
#endif
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2003 Sistina Software
* Copyright (C) 2004-2008 Red Hat, Inc. All rights reserved.
*
* This file is released under the LGPL.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/vmalloc.h>
#include <linux/dm-io.h>
#include <linux/dm-dirty-log.h>
#include <linux/device-mapper.h>
#define DM_MSG_PREFIX "dirty region log"
static LIST_HEAD(_log_types);
static DEFINE_SPINLOCK(_lock);
static struct dm_dirty_log_type *__find_dirty_log_type(const char *name)
{
struct dm_dirty_log_type *log_type;
list_for_each_entry(log_type, &_log_types, list)
if (!strcmp(name, log_type->name))
return log_type;
return NULL;
}
static struct dm_dirty_log_type *_get_dirty_log_type(const char *name)
{
struct dm_dirty_log_type *log_type;
spin_lock(&_lock);
log_type = __find_dirty_log_type(name);
if (log_type && !try_module_get(log_type->module))
log_type = NULL;
spin_unlock(&_lock);
return log_type;
}
/*
* get_type
* @type_name
*
* Attempt to retrieve the dm_dirty_log_type by name. If not already
* available, attempt to load the appropriate module.
*
* Log modules are named "dm-log-" followed by the 'type_name'.
* Modules may contain multiple types.
* This function will first try the module "dm-log-<type_name>",
* then truncate 'type_name' on the last '-' and try again.
*
* For example, if type_name was "clustered-disk", it would search
* 'dm-log-clustered-disk' then 'dm-log-clustered'.
*
* Returns: dirty_log_type* on success, NULL on failure
*/
static struct dm_dirty_log_type *get_type(const char *type_name)
{
char *p, *type_name_dup;
struct dm_dirty_log_type *log_type;
if (!type_name)
return NULL;
log_type = _get_dirty_log_type(type_name);
if (log_type)
return log_type;
type_name_dup = kstrdup(type_name, GFP_KERNEL);
if (!type_name_dup) {
DMWARN("No memory left to attempt log module load for \"%s\"",
type_name);
return NULL;
}
while (request_module("dm-log-%s", type_name_dup) ||
!(log_type = _get_dirty_log_type(type_name))) {
p = strrchr(type_name_dup, '-');
if (!p)
break;
p[0] = '\0';
}
if (!log_type)
DMWARN("Module for logging type \"%s\" not found.", type_name);
kfree(type_name_dup);
return log_type;
}
static void put_type(struct dm_dirty_log_type *type)
{
if (!type)
return;
spin_lock(&_lock);
if (!__find_dirty_log_type(type->name))
goto out;
module_put(type->module);
out:
spin_unlock(&_lock);
}
int dm_dirty_log_type_register(struct dm_dirty_log_type *type)
{
int r = 0;
spin_lock(&_lock);
if (!__find_dirty_log_type(type->name))
list_add(&type->list, &_log_types);
else
r = -EEXIST;
spin_unlock(&_lock);
return r;
}
EXPORT_SYMBOL(dm_dirty_log_type_register);
int dm_dirty_log_type_unregister(struct dm_dirty_log_type *type)
{
spin_lock(&_lock);
if (!__find_dirty_log_type(type->name)) {
spin_unlock(&_lock);
return -EINVAL;
}
list_del(&type->list);
spin_unlock(&_lock);
return 0;
}
EXPORT_SYMBOL(dm_dirty_log_type_unregister);
struct dm_dirty_log *dm_dirty_log_create(const char *type_name,
struct dm_target *ti,
int (*flush_callback_fn)(struct dm_target *ti),
unsigned int argc, char **argv)
{
struct dm_dirty_log_type *type;
struct dm_dirty_log *log;
log = kmalloc(sizeof(*log), GFP_KERNEL);
if (!log)
return NULL;
type = get_type(type_name);
if (!type) {
kfree(log);
return NULL;
}
log->flush_callback_fn = flush_callback_fn;
log->type = type;
if (type->ctr(log, ti, argc, argv)) {
kfree(log);
put_type(type);
return NULL;
}
return log;
}
EXPORT_SYMBOL(dm_dirty_log_create);
void dm_dirty_log_destroy(struct dm_dirty_log *log)
{
log->type->dtr(log);
put_type(log->type);
kfree(log);
}
EXPORT_SYMBOL(dm_dirty_log_destroy);
/*
*---------------------------------------------------------------
* Persistent and core logs share a lot of their implementation.
* FIXME: need a reload method to be called from a resume
*---------------------------------------------------------------
*/
/*
* Magic for persistent mirrors: "MiRr"
*/
#define MIRROR_MAGIC 0x4D695272
/*
* The on-disk version of the metadata.
*/
#define MIRROR_DISK_VERSION 2
#define LOG_OFFSET 2
struct log_header_disk {
__le32 magic;
/*
* Simple, incrementing version. no backward
* compatibility.
*/
__le32 version;
__le64 nr_regions;
} __packed;
struct log_header_core {
uint32_t magic;
uint32_t version;
uint64_t nr_regions;
};
struct log_c {
struct dm_target *ti;
int touched_dirtied;
int touched_cleaned;
int flush_failed;
uint32_t region_size;
unsigned int region_count;
region_t sync_count;
unsigned int bitset_uint32_count;
uint32_t *clean_bits;
uint32_t *sync_bits;
uint32_t *recovering_bits; /* FIXME: this seems excessive */
int sync_search;
/* Resync flag */
enum sync {
DEFAULTSYNC, /* Synchronize if necessary */
NOSYNC, /* Devices known to be already in sync */
FORCESYNC, /* Force a sync to happen */
} sync;
struct dm_io_request io_req;
/*
* Disk log fields
*/
int log_dev_failed;
int log_dev_flush_failed;
struct dm_dev *log_dev;
struct log_header_core header;
struct dm_io_region header_location;
struct log_header_disk *disk_header;
};
/*
* The touched member needs to be updated every time we access
* one of the bitsets.
*/
static inline int log_test_bit(uint32_t *bs, unsigned int bit)
{
return test_bit_le(bit, bs) ? 1 : 0;
}
static inline void log_set_bit(struct log_c *l,
uint32_t *bs, unsigned int bit)
{
__set_bit_le(bit, bs);
l->touched_cleaned = 1;
}
static inline void log_clear_bit(struct log_c *l,
uint32_t *bs, unsigned int bit)
{
__clear_bit_le(bit, bs);
l->touched_dirtied = 1;
}
/*
*---------------------------------------------------------------
* Header IO
*--------------------------------------------------------------
*/
static void header_to_disk(struct log_header_core *core, struct log_header_disk *disk)
{
disk->magic = cpu_to_le32(core->magic);
disk->version = cpu_to_le32(core->version);
disk->nr_regions = cpu_to_le64(core->nr_regions);
}
static void header_from_disk(struct log_header_core *core, struct log_header_disk *disk)
{
core->magic = le32_to_cpu(disk->magic);
core->version = le32_to_cpu(disk->version);
core->nr_regions = le64_to_cpu(disk->nr_regions);
}
static int rw_header(struct log_c *lc, enum req_op op)
{
lc->io_req.bi_opf = op;
return dm_io(&lc->io_req, 1, &lc->header_location, NULL, IOPRIO_DEFAULT);
}
static int flush_header(struct log_c *lc)
{
struct dm_io_region null_location = {
.bdev = lc->header_location.bdev,
.sector = 0,
.count = 0,
};
lc->io_req.bi_opf = REQ_OP_WRITE | REQ_PREFLUSH;
return dm_io(&lc->io_req, 1, &null_location, NULL, IOPRIO_DEFAULT);
}
static int read_header(struct log_c *log)
{
int r;
r = rw_header(log, REQ_OP_READ);
if (r)
return r;
header_from_disk(&log->header, log->disk_header);
/* New log required? */
if (log->sync != DEFAULTSYNC || log->header.magic != MIRROR_MAGIC) {
log->header.magic = MIRROR_MAGIC;
log->header.version = MIRROR_DISK_VERSION;
log->header.nr_regions = 0;
}
#ifdef __LITTLE_ENDIAN
if (log->header.version == 1)
log->header.version = 2;
#endif
if (log->header.version != MIRROR_DISK_VERSION) {
DMWARN("incompatible disk log version");
return -EINVAL;
}
return 0;
}
static int _check_region_size(struct dm_target *ti, uint32_t region_size)
{
if (region_size < 2 || region_size > ti->len)
return 0;
if (!is_power_of_2(region_size))
return 0;
return 1;
}
/*
*--------------------------------------------------------------
* core log constructor/destructor
*
* argv contains region_size followed optionally by [no]sync
*--------------------------------------------------------------
*/
#define BYTE_SHIFT 3
static int create_log_context(struct dm_dirty_log *log, struct dm_target *ti,
unsigned int argc, char **argv,
struct dm_dev *dev)
{
enum sync sync = DEFAULTSYNC;
struct log_c *lc;
uint32_t region_size;
unsigned int region_count;
size_t bitset_size, buf_size;
int r;
char dummy;
if (argc < 1 || argc > 2) {
DMWARN("wrong number of arguments to dirty region log");
return -EINVAL;
}
if (argc > 1) {
if (!strcmp(argv[1], "sync"))
sync = FORCESYNC;
else if (!strcmp(argv[1], "nosync"))
sync = NOSYNC;
else {
DMWARN("unrecognised sync argument to dirty region log: %s", argv[1]);
return -EINVAL;
}
}
if (sscanf(argv[0], "%u%c", ®ion_size, &dummy) != 1 ||
!_check_region_size(ti, region_size)) {
DMWARN("invalid region size %s", argv[0]);
return -EINVAL;
}
region_count = dm_sector_div_up(ti->len, region_size);
lc = kmalloc(sizeof(*lc), GFP_KERNEL);
if (!lc) {
DMWARN("couldn't allocate core log");
return -ENOMEM;
}
lc->ti = ti;
lc->touched_dirtied = 0;
lc->touched_cleaned = 0;
lc->flush_failed = 0;
lc->region_size = region_size;
lc->region_count = region_count;
lc->sync = sync;
/*
* Work out how many "unsigned long"s we need to hold the bitset.
*/
bitset_size = dm_round_up(region_count, BITS_PER_LONG);
bitset_size >>= BYTE_SHIFT;
lc->bitset_uint32_count = bitset_size / sizeof(*lc->clean_bits);
/*
* Disk log?
*/
if (!dev) {
lc->clean_bits = vmalloc(bitset_size);
if (!lc->clean_bits) {
DMWARN("couldn't allocate clean bitset");
kfree(lc);
return -ENOMEM;
}
lc->disk_header = NULL;
} else {
lc->log_dev = dev;
lc->log_dev_failed = 0;
lc->log_dev_flush_failed = 0;
lc->header_location.bdev = lc->log_dev->bdev;
lc->header_location.sector = 0;
/*
* Buffer holds both header and bitset.
*/
buf_size =
dm_round_up((LOG_OFFSET << SECTOR_SHIFT) + bitset_size,
bdev_logical_block_size(lc->header_location.bdev));
if (buf_size > bdev_nr_bytes(dev->bdev)) {
DMWARN("log device %s too small: need %llu bytes",
dev->name, (unsigned long long)buf_size);
kfree(lc);
return -EINVAL;
}
lc->header_location.count = buf_size >> SECTOR_SHIFT;
lc->io_req.mem.type = DM_IO_VMA;
lc->io_req.notify.fn = NULL;
lc->io_req.client = dm_io_client_create();
if (IS_ERR(lc->io_req.client)) {
r = PTR_ERR(lc->io_req.client);
DMWARN("couldn't allocate disk io client");
kfree(lc);
return r;
}
lc->disk_header = vmalloc(buf_size);
if (!lc->disk_header) {
DMWARN("couldn't allocate disk log buffer");
dm_io_client_destroy(lc->io_req.client);
kfree(lc);
return -ENOMEM;
}
lc->io_req.mem.ptr.vma = lc->disk_header;
lc->clean_bits = (void *)lc->disk_header +
(LOG_OFFSET << SECTOR_SHIFT);
}
memset(lc->clean_bits, -1, bitset_size);
lc->sync_bits = vmalloc(bitset_size);
if (!lc->sync_bits) {
DMWARN("couldn't allocate sync bitset");
if (!dev)
vfree(lc->clean_bits);
else
dm_io_client_destroy(lc->io_req.client);
vfree(lc->disk_header);
kfree(lc);
return -ENOMEM;
}
memset(lc->sync_bits, (sync == NOSYNC) ? -1 : 0, bitset_size);
lc->sync_count = (sync == NOSYNC) ? region_count : 0;
lc->recovering_bits = vzalloc(bitset_size);
if (!lc->recovering_bits) {
DMWARN("couldn't allocate sync bitset");
vfree(lc->sync_bits);
if (!dev)
vfree(lc->clean_bits);
else
dm_io_client_destroy(lc->io_req.client);
vfree(lc->disk_header);
kfree(lc);
return -ENOMEM;
}
lc->sync_search = 0;
log->context = lc;
return 0;
}
static int core_ctr(struct dm_dirty_log *log, struct dm_target *ti,
unsigned int argc, char **argv)
{
return create_log_context(log, ti, argc, argv, NULL);
}
static void destroy_log_context(struct log_c *lc)
{
vfree(lc->sync_bits);
vfree(lc->recovering_bits);
kfree(lc);
}
static void core_dtr(struct dm_dirty_log *log)
{
struct log_c *lc = log->context;
vfree(lc->clean_bits);
destroy_log_context(lc);
}
/*
*---------------------------------------------------------------------
* disk log constructor/destructor
*
* argv contains log_device region_size followed optionally by [no]sync
*---------------------------------------------------------------------
*/
static int disk_ctr(struct dm_dirty_log *log, struct dm_target *ti,
unsigned int argc, char **argv)
{
int r;
struct dm_dev *dev;
if (argc < 2 || argc > 3) {
DMWARN("wrong number of arguments to disk dirty region log");
return -EINVAL;
}
r = dm_get_device(ti, argv[0], dm_table_get_mode(ti->table), &dev);
if (r)
return r;
r = create_log_context(log, ti, argc - 1, argv + 1, dev);
if (r) {
dm_put_device(ti, dev);
return r;
}
return 0;
}
static void disk_dtr(struct dm_dirty_log *log)
{
struct log_c *lc = log->context;
dm_put_device(lc->ti, lc->log_dev);
vfree(lc->disk_header);
dm_io_client_destroy(lc->io_req.client);
destroy_log_context(lc);
}
static void fail_log_device(struct log_c *lc)
{
if (lc->log_dev_failed)
return;
lc->log_dev_failed = 1;
dm_table_event(lc->ti->table);
}
static int disk_resume(struct dm_dirty_log *log)
{
int r;
unsigned int i;
struct log_c *lc = log->context;
size_t size = lc->bitset_uint32_count * sizeof(uint32_t);
/* read the disk header */
r = read_header(lc);
if (r) {
DMWARN("%s: Failed to read header on dirty region log device",
lc->log_dev->name);
fail_log_device(lc);
/*
* If the log device cannot be read, we must assume
* all regions are out-of-sync. If we simply return
* here, the state will be uninitialized and could
* lead us to return 'in-sync' status for regions
* that are actually 'out-of-sync'.
*/
lc->header.nr_regions = 0;
}
/* set or clear any new bits -- device has grown */
if (lc->sync == NOSYNC)
for (i = lc->header.nr_regions; i < lc->region_count; i++)
/* FIXME: amazingly inefficient */
log_set_bit(lc, lc->clean_bits, i);
else
for (i = lc->header.nr_regions; i < lc->region_count; i++)
/* FIXME: amazingly inefficient */
log_clear_bit(lc, lc->clean_bits, i);
/* clear any old bits -- device has shrunk */
for (i = lc->region_count; i % BITS_PER_LONG; i++)
log_clear_bit(lc, lc->clean_bits, i);
/* copy clean across to sync */
memcpy(lc->sync_bits, lc->clean_bits, size);
lc->sync_count = memweight(lc->clean_bits,
lc->bitset_uint32_count * sizeof(uint32_t));
lc->sync_search = 0;
/* set the correct number of regions in the header */
lc->header.nr_regions = lc->region_count;
header_to_disk(&lc->header, lc->disk_header);
/* write the new header */
r = rw_header(lc, REQ_OP_WRITE);
if (!r) {
r = flush_header(lc);
if (r)
lc->log_dev_flush_failed = 1;
}
if (r) {
DMWARN("%s: Failed to write header on dirty region log device",
lc->log_dev->name);
fail_log_device(lc);
}
return r;
}
static uint32_t core_get_region_size(struct dm_dirty_log *log)
{
struct log_c *lc = log->context;
return lc->region_size;
}
static int core_resume(struct dm_dirty_log *log)
{
struct log_c *lc = log->context;
lc->sync_search = 0;
return 0;
}
static int core_is_clean(struct dm_dirty_log *log, region_t region)
{
struct log_c *lc = log->context;
return log_test_bit(lc->clean_bits, region);
}
static int core_in_sync(struct dm_dirty_log *log, region_t region, int block)
{
struct log_c *lc = log->context;
return log_test_bit(lc->sync_bits, region);
}
static int core_flush(struct dm_dirty_log *log)
{
/* no op */
return 0;
}
static int disk_flush(struct dm_dirty_log *log)
{
int r, i;
struct log_c *lc = log->context;
/* only write if the log has changed */
if (!lc->touched_cleaned && !lc->touched_dirtied)
return 0;
if (lc->touched_cleaned && log->flush_callback_fn &&
log->flush_callback_fn(lc->ti)) {
/*
* At this point it is impossible to determine which
* regions are clean and which are dirty (without
* re-reading the log off disk). So mark all of them
* dirty.
*/
lc->flush_failed = 1;
for (i = 0; i < lc->region_count; i++)
log_clear_bit(lc, lc->clean_bits, i);
}
r = rw_header(lc, REQ_OP_WRITE);
if (r)
fail_log_device(lc);
else {
if (lc->touched_dirtied) {
r = flush_header(lc);
if (r) {
lc->log_dev_flush_failed = 1;
fail_log_device(lc);
} else
lc->touched_dirtied = 0;
}
lc->touched_cleaned = 0;
}
return r;
}
static void core_mark_region(struct dm_dirty_log *log, region_t region)
{
struct log_c *lc = log->context;
log_clear_bit(lc, lc->clean_bits, region);
}
static void core_clear_region(struct dm_dirty_log *log, region_t region)
{
struct log_c *lc = log->context;
if (likely(!lc->flush_failed))
log_set_bit(lc, lc->clean_bits, region);
}
static int core_get_resync_work(struct dm_dirty_log *log, region_t *region)
{
struct log_c *lc = log->context;
if (lc->sync_search >= lc->region_count)
return 0;
do {
*region = find_next_zero_bit_le(lc->sync_bits,
lc->region_count,
lc->sync_search);
lc->sync_search = *region + 1;
if (*region >= lc->region_count)
return 0;
} while (log_test_bit(lc->recovering_bits, *region));
log_set_bit(lc, lc->recovering_bits, *region);
return 1;
}
static void core_set_region_sync(struct dm_dirty_log *log, region_t region,
int in_sync)
{
struct log_c *lc = log->context;
log_clear_bit(lc, lc->recovering_bits, region);
if (in_sync) {
log_set_bit(lc, lc->sync_bits, region);
lc->sync_count++;
} else if (log_test_bit(lc->sync_bits, region)) {
lc->sync_count--;
log_clear_bit(lc, lc->sync_bits, region);
}
}
static region_t core_get_sync_count(struct dm_dirty_log *log)
{
struct log_c *lc = log->context;
return lc->sync_count;
}
#define DMEMIT_SYNC \
do { \
if (lc->sync != DEFAULTSYNC) \
DMEMIT("%ssync ", lc->sync == NOSYNC ? "no" : ""); \
} while (0)
static int core_status(struct dm_dirty_log *log, status_type_t status,
char *result, unsigned int maxlen)
{
int sz = 0;
struct log_c *lc = log->context;
switch (status) {
case STATUSTYPE_INFO:
DMEMIT("1 %s", log->type->name);
break;
case STATUSTYPE_TABLE:
DMEMIT("%s %u %u ", log->type->name,
lc->sync == DEFAULTSYNC ? 1 : 2, lc->region_size);
DMEMIT_SYNC;
break;
case STATUSTYPE_IMA:
*result = '\0';
break;
}
return sz;
}
static int disk_status(struct dm_dirty_log *log, status_type_t status,
char *result, unsigned int maxlen)
{
int sz = 0;
struct log_c *lc = log->context;
switch (status) {
case STATUSTYPE_INFO:
DMEMIT("3 %s %s %c", log->type->name, lc->log_dev->name,
lc->log_dev_flush_failed ? 'F' :
lc->log_dev_failed ? 'D' :
'A');
break;
case STATUSTYPE_TABLE:
DMEMIT("%s %u %s %u ", log->type->name,
lc->sync == DEFAULTSYNC ? 2 : 3, lc->log_dev->name,
lc->region_size);
DMEMIT_SYNC;
break;
case STATUSTYPE_IMA:
*result = '\0';
break;
}
return sz;
}
static struct dm_dirty_log_type _core_type = {
.name = "core",
.module = THIS_MODULE,
.ctr = core_ctr,
.dtr = core_dtr,
.resume = core_resume,
.get_region_size = core_get_region_size,
.is_clean = core_is_clean,
.in_sync = core_in_sync,
.flush = core_flush,
.mark_region = core_mark_region,
.clear_region = core_clear_region,
.get_resync_work = core_get_resync_work,
.set_region_sync = core_set_region_sync,
.get_sync_count = core_get_sync_count,
.status = core_status,
};
static struct dm_dirty_log_type _disk_type = {
.name = "disk",
.module = THIS_MODULE,
.ctr = disk_ctr,
.dtr = disk_dtr,
.postsuspend = disk_flush,
.resume = disk_resume,
.get_region_size = core_get_region_size,
.is_clean = core_is_clean,
.in_sync = core_in_sync,
.flush = disk_flush,
.mark_region = core_mark_region,
.clear_region = core_clear_region,
.get_resync_work = core_get_resync_work,
.set_region_sync = core_set_region_sync,
.get_sync_count = core_get_sync_count,
.status = disk_status,
};
static int __init dm_dirty_log_init(void)
{
int r;
r = dm_dirty_log_type_register(&_core_type);
if (r)
DMWARN("couldn't register core log");
r = dm_dirty_log_type_register(&_disk_type);
if (r) {
DMWARN("couldn't register disk type");
dm_dirty_log_type_unregister(&_core_type);
}
return r;
}
static void __exit dm_dirty_log_exit(void)
{
dm_dirty_log_type_unregister(&_disk_type);
dm_dirty_log_type_unregister(&_core_type);
}
module_init(dm_dirty_log_init);
module_exit(dm_dirty_log_exit);
MODULE_DESCRIPTION(DM_NAME " dirty region log");
MODULE_AUTHOR("Joe Thornber, Heinz Mauelshagen <[email protected]>");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* rt1318-sdw.h -- RT1318 SDCA ALSA SoC audio driver header
*
* Copyright(c) 2022 Realtek Semiconductor Corp.
*/
#ifndef __RT1318_SDW_H__
#define __RT1318_SDW_H__
#include <linux/regmap.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <sound/soc.h>
/* imp-defined registers */
#define RT1318_SAPU_SM 0x3203
#define R1318_TCON 0xc203
#define R1318_TCON_RELATED_1 0xc206
#define R1318_SPK_TEMPERATRUE_PROTECTION_0 0xdb00
#define R1318_SPK_TEMPERATRUE_PROTECTION_L_4 0xdb08
#define R1318_SPK_TEMPERATRUE_PROTECTION_R_4 0xdd08
#define R1318_SPK_TEMPERATRUE_PROTECTION_L_6 0xdb12
#define R1318_SPK_TEMPERATRUE_PROTECTION_R_6 0xdd12
#define RT1318_INIT_RECIPROCAL_REG_L_24 0xdbb5
#define RT1318_INIT_RECIPROCAL_REG_L_23_16 0xdbb6
#define RT1318_INIT_RECIPROCAL_REG_L_15_8 0xdbb7
#define RT1318_INIT_RECIPROCAL_REG_L_7_0 0xdbb8
#define RT1318_INIT_RECIPROCAL_REG_R_24 0xddb5
#define RT1318_INIT_RECIPROCAL_REG_R_23_16 0xddb6
#define RT1318_INIT_RECIPROCAL_REG_R_15_8 0xddb7
#define RT1318_INIT_RECIPROCAL_REG_R_7_0 0xddb8
#define RT1318_INIT_R0_RECIPROCAL_SYN_L_24 0xdbc5
#define RT1318_INIT_R0_RECIPROCAL_SYN_L_23_16 0xdbc6
#define RT1318_INIT_R0_RECIPROCAL_SYN_L_15_8 0xdbc7
#define RT1318_INIT_R0_RECIPROCAL_SYN_L_7_0 0xdbc8
#define RT1318_INIT_R0_RECIPROCAL_SYN_R_24 0xddc5
#define RT1318_INIT_R0_RECIPROCAL_SYN_R_23_16 0xddc6
#define RT1318_INIT_R0_RECIPROCAL_SYN_R_15_8 0xddc7
#define RT1318_INIT_R0_RECIPROCAL_SYN_R_7_0 0xddc8
#define RT1318_R0_COMPARE_FLAG_L 0xdb35
#define RT1318_R0_COMPARE_FLAG_R 0xdd35
#define RT1318_STP_INITIAL_RS_TEMP_H 0xdd93
#define RT1318_STP_INITIAL_RS_TEMP_L 0xdd94
/* RT1318 SDCA Control - function number */
#define FUNC_NUM_SMART_AMP 0x04
/* RT1318 SDCA entity */
#define RT1318_SDCA_ENT_PDE23 0x31
#define RT1318_SDCA_ENT_XU24 0x24
#define RT1318_SDCA_ENT_FU21 0x03
#define RT1318_SDCA_ENT_UDMPU21 0x02
#define RT1318_SDCA_ENT_CS21 0x21
#define RT1318_SDCA_ENT_SAPU 0x29
/* RT1318 SDCA control */
#define RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
#define RT1318_SDCA_CTL_REQ_POWER_STATE 0x01
#define RT1318_SDCA_CTL_FU_MUTE 0x01
#define RT1318_SDCA_CTL_FU_VOLUME 0x02
#define RT1318_SDCA_CTL_UDMPU_CLUSTER 0x10
#define RT1318_SDCA_CTL_SAPU_PROTECTION_MODE 0x10
#define RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11
/* RT1318 SDCA channel */
#define CH_L 0x01
#define CH_R 0x02
/* sample frequency index */
#define RT1318_SDCA_RATE_16000HZ 0x04
#define RT1318_SDCA_RATE_32000HZ 0x07
#define RT1318_SDCA_RATE_44100HZ 0x08
#define RT1318_SDCA_RATE_48000HZ 0x09
#define RT1318_SDCA_RATE_96000HZ 0x0b
#define RT1318_SDCA_RATE_192000HZ 0x0d
struct rt1318_sdw_priv {
struct snd_soc_component *component;
struct regmap *regmap;
struct sdw_slave *sdw_slave;
struct sdw_bus_params params;
bool hw_init;
bool first_hw_init;
};
#endif /* __RT1318_SDW_H__ */
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2001 Jean-Fredric Clere, Nikolas Zimmermann, Georg Acher
* Mark Cave-Ayland, Carlo E Prelz, Dick Streefland
* Copyright (c) 2002, 2003 Tuukka Toivonen
* Copyright (c) 2008 Erik Andrén
*
* P/N 861037: Sensor HDCS1000 ASIC STV0600
* P/N 861050-0010: Sensor HDCS1000 ASIC STV0600
* P/N 861050-0020: Sensor Photobit PB100 ASIC STV0600-1 - QuickCam Express
* P/N 861055: Sensor ST VV6410 ASIC STV0610 - LEGO cam
* P/N 861075-0040: Sensor HDCS1000 ASIC
* P/N 961179-0700: Sensor ST VV6410 ASIC STV0602 - Dexxa WebCam USB
* P/N 861040-0000: Sensor ST VV6410 ASIC STV0610 - QuickCam Web
*/
#ifndef STV06XX_SENSOR_H_
#define STV06XX_SENSOR_H_
#include "stv06xx.h"
#define IS_1020(sd) ((sd)->sensor == &stv06xx_sensor_hdcs1020)
extern const struct stv06xx_sensor stv06xx_sensor_vv6410;
extern const struct stv06xx_sensor stv06xx_sensor_hdcs1x00;
extern const struct stv06xx_sensor stv06xx_sensor_hdcs1020;
extern const struct stv06xx_sensor stv06xx_sensor_pb0100;
extern const struct stv06xx_sensor stv06xx_sensor_st6422;
struct stv06xx_sensor {
/* Defines the name of a sensor */
char name[32];
/* Sensor i2c address */
u8 i2c_addr;
/* Flush value*/
u8 i2c_flush;
/* length of an i2c word */
u8 i2c_len;
/* Isoc packet size (per mode) */
int min_packet_size[4];
int max_packet_size[4];
/* Probes if the sensor is connected */
int (*probe)(struct sd *sd);
/* Performs a initialization sequence */
int (*init)(struct sd *sd);
/* Initializes the controls */
int (*init_controls)(struct sd *sd);
/* Reads a sensor register */
int (*read_sensor)(struct sd *sd, const u8 address,
u8 *i2c_data, const u8 len);
/* Writes to a sensor register */
int (*write_sensor)(struct sd *sd, const u8 address,
u8 *i2c_data, const u8 len);
/* Instructs the sensor to start streaming */
int (*start)(struct sd *sd);
/* Instructs the sensor to stop streaming */
int (*stop)(struct sd *sd);
/* Instructs the sensor to dump all its contents */
int (*dump)(struct sd *sd);
};
#endif
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB10x platform initialisation
*
* Copyright (C) Abilis Systems 2012
*
* Author: Christian Ruppert <[email protected]>
*/
#include <linux/init.h>
#include <asm/mach_desc.h>
static const char *tb10x_compat[] __initdata = {
"abilis,arc-tb10x",
NULL,
};
MACHINE_START(TB10x, "tb10x")
.dt_compat = tb10x_compat,
MACHINE_END
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_PLATFORM_DATA_EMC2305__
#define __LINUX_PLATFORM_DATA_EMC2305__
#define EMC2305_PWM_MAX 5
/**
* struct emc2305_platform_data - EMC2305 driver platform data
* @max_state: maximum cooling state of the cooling device;
* @pwm_num: number of active channels;
* @pwm_separate: separate PWM settings for every channel;
* @pwm_min: array of minimum PWM per channel;
*/
struct emc2305_platform_data {
u8 max_state;
u8 pwm_num;
bool pwm_separate;
u8 pwm_min[EMC2305_PWM_MAX];
};
#endif
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*/
#ifndef __TAG_LOCAL_H_INCLUDED__
#define __TAG_LOCAL_H_INCLUDED__
#include "tag_global.h"
#define SH_CSS_MINIMUM_TAG_ID (-1)
#endif /* __TAG_LOCAL_H_INCLUDED__ */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Goodix Touchscreen firmware upload support
*
* Copyright (c) 2021 Hans de Goede <[email protected]>
*
* This is a rewrite of gt9xx_update.c from the Allwinner H3 BSP which is:
* Copyright (c) 2010 - 2012 Goodix Technology.
* Author: [email protected]
*/
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include "goodix.h"
#define GOODIX_FW_HEADER_LENGTH sizeof(struct goodix_fw_header)
#define GOODIX_FW_SECTION_LENGTH 0x2000
#define GOODIX_FW_DSP_LENGTH 0x1000
#define GOODIX_FW_UPLOAD_ADDRESS 0xc000
#define GOODIX_CFG_LOC_HAVE_KEY 7
#define GOODIX_CFG_LOC_DRVA_NUM 27
#define GOODIX_CFG_LOC_DRVB_NUM 28
#define GOODIX_CFG_LOC_SENS_NUM 29
struct goodix_fw_header {
u8 hw_info[4];
u8 pid[8];
u8 vid[2];
} __packed;
static u16 goodix_firmware_checksum(const u8 *data, int size)
{
u16 checksum = 0;
int i;
for (i = 0; i < size; i += 2)
checksum += (data[i] << 8) + data[i + 1];
return checksum;
}
static int goodix_firmware_verify(struct device *dev, const struct firmware *fw)
{
const struct goodix_fw_header *fw_header;
size_t expected_size;
const u8 *data;
u16 checksum;
char buf[9];
expected_size = GOODIX_FW_HEADER_LENGTH + 4 * GOODIX_FW_SECTION_LENGTH +
GOODIX_FW_DSP_LENGTH;
if (fw->size != expected_size) {
dev_err(dev, "Firmware has wrong size, expected %zu got %zu\n",
expected_size, fw->size);
return -EINVAL;
}
data = fw->data + GOODIX_FW_HEADER_LENGTH;
checksum = goodix_firmware_checksum(data, 4 * GOODIX_FW_SECTION_LENGTH);
if (checksum) {
dev_err(dev, "Main firmware checksum error\n");
return -EINVAL;
}
data += 4 * GOODIX_FW_SECTION_LENGTH;
checksum = goodix_firmware_checksum(data, GOODIX_FW_DSP_LENGTH);
if (checksum) {
dev_err(dev, "DSP firmware checksum error\n");
return -EINVAL;
}
fw_header = (const struct goodix_fw_header *)fw->data;
dev_info(dev, "Firmware hardware info %02x%02x%02x%02x\n",
fw_header->hw_info[0], fw_header->hw_info[1],
fw_header->hw_info[2], fw_header->hw_info[3]);
/* pid is a 8 byte buffer containing a string, weird I know */
memcpy(buf, fw_header->pid, 8);
buf[8] = 0;
dev_info(dev, "Firmware PID: %s VID: %02x%02x\n", buf,
fw_header->vid[0], fw_header->vid[1]);
return 0;
}
static int goodix_enter_upload_mode(struct i2c_client *client)
{
int tries, error;
u8 val;
tries = 200;
do {
error = goodix_i2c_write_u8(client,
GOODIX_REG_MISCTL_SWRST, 0x0c);
if (error)
return error;
error = goodix_i2c_read(client,
GOODIX_REG_MISCTL_SWRST, &val, 1);
if (error)
return error;
if (val == 0x0c)
break;
} while (--tries);
if (!tries) {
dev_err(&client->dev, "Error could not hold ss51 & dsp\n");
return -EIO;
}
/* DSP_CK and DSP_ALU_CK PowerOn */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_DSP_CTL, 0x00);
if (error)
return error;
/* Disable watchdog */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_TMR0_EN, 0x00);
if (error)
return error;
/* Clear cache enable */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_CACHE_EN, 0x00);
if (error)
return error;
/* Set boot from SRAM */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_BOOTCTL, 0x02);
if (error)
return error;
/* Software reboot */
error = goodix_i2c_write_u8(client,
GOODIX_REG_MISCTL_CPU_SWRST_PULSE, 0x01);
if (error)
return error;
/* Clear control flag */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_BOOTCTL, 0x00);
if (error)
return error;
/* Set scramble */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_BOOT_OPT, 0x00);
if (error)
return error;
/* Enable accessing code */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_MEM_CD_EN, 0x01);
if (error)
return error;
return 0;
}
static int goodix_start_firmware(struct i2c_client *client)
{
int error;
u8 val;
/* Init software watchdog */
error = goodix_i2c_write_u8(client, GOODIX_REG_SW_WDT, 0xaa);
if (error)
return error;
/* Release SS51 & DSP */
error = goodix_i2c_write_u8(client, GOODIX_REG_MISCTL_SWRST, 0x00);
if (error)
return error;
error = goodix_i2c_read(client, GOODIX_REG_SW_WDT, &val, 1);
if (error)
return error;
/* The value we've written to SW_WDT should have been cleared now */
if (val == 0xaa) {
dev_err(&client->dev, "Error SW_WDT reg not cleared on fw startup\n");
return -EIO;
}
/* Re-init software watchdog */
error = goodix_i2c_write_u8(client, GOODIX_REG_SW_WDT, 0xaa);
if (error)
return error;
return 0;
}
static int goodix_firmware_upload(struct goodix_ts_data *ts)
{
const struct firmware *fw;
char fw_name[64];
const u8 *data;
int error;
snprintf(fw_name, sizeof(fw_name), "goodix/%s", ts->firmware_name);
error = request_firmware(&fw, fw_name, &ts->client->dev);
if (error) {
dev_err(&ts->client->dev, "Firmware request error %d\n", error);
return error;
}
error = goodix_firmware_verify(&ts->client->dev, fw);
if (error)
goto release;
error = goodix_reset_no_int_sync(ts);
if (error)
goto release;
error = goodix_enter_upload_mode(ts->client);
if (error)
goto release;
/* Select SRAM bank 0 and upload section 1 & 2 */
error = goodix_i2c_write_u8(ts->client,
GOODIX_REG_MISCTL_SRAM_BANK, 0x00);
if (error)
goto release;
data = fw->data + GOODIX_FW_HEADER_LENGTH;
error = goodix_i2c_write(ts->client, GOODIX_FW_UPLOAD_ADDRESS,
data, 2 * GOODIX_FW_SECTION_LENGTH);
if (error)
goto release;
/* Select SRAM bank 1 and upload section 3 & 4 */
error = goodix_i2c_write_u8(ts->client,
GOODIX_REG_MISCTL_SRAM_BANK, 0x01);
if (error)
goto release;
data += 2 * GOODIX_FW_SECTION_LENGTH;
error = goodix_i2c_write(ts->client, GOODIX_FW_UPLOAD_ADDRESS,
data, 2 * GOODIX_FW_SECTION_LENGTH);
if (error)
goto release;
/* Select SRAM bank 2 and upload the DSP firmware */
error = goodix_i2c_write_u8(ts->client,
GOODIX_REG_MISCTL_SRAM_BANK, 0x02);
if (error)
goto release;
data += 2 * GOODIX_FW_SECTION_LENGTH;
error = goodix_i2c_write(ts->client, GOODIX_FW_UPLOAD_ADDRESS,
data, GOODIX_FW_DSP_LENGTH);
if (error)
goto release;
error = goodix_start_firmware(ts->client);
if (error)
goto release;
error = goodix_int_sync(ts);
release:
release_firmware(fw);
return error;
}
static int goodix_prepare_bak_ref(struct goodix_ts_data *ts)
{
u8 have_key, driver_num, sensor_num;
if (ts->bak_ref)
return 0; /* Already done */
have_key = (ts->config[GOODIX_CFG_LOC_HAVE_KEY] & 0x01);
driver_num = (ts->config[GOODIX_CFG_LOC_DRVA_NUM] & 0x1f) +
(ts->config[GOODIX_CFG_LOC_DRVB_NUM] & 0x1f);
if (have_key)
driver_num--;
sensor_num = (ts->config[GOODIX_CFG_LOC_SENS_NUM] & 0x0f) +
((ts->config[GOODIX_CFG_LOC_SENS_NUM] >> 4) & 0x0f);
dev_dbg(&ts->client->dev, "Drv %d Sen %d Key %d\n",
driver_num, sensor_num, have_key);
ts->bak_ref_len = (driver_num * (sensor_num - 2) + 2) * 2;
ts->bak_ref = devm_kzalloc(&ts->client->dev,
ts->bak_ref_len, GFP_KERNEL);
if (!ts->bak_ref)
return -ENOMEM;
/*
* The bak_ref array contains the backup of an array of (self/auto)
* calibration related values which the Android version of the driver
* stores on the filesystem so that it can be restored after reboot.
* The mainline kernel never writes directly to the filesystem like
* this, we always start will all the values which give a correction
* factor in approx. the -20 - +20 range (in 2s complement) set to 0.
*
* Note the touchscreen works fine without restoring the reference
* values after a reboot / power-cycle.
*
* The last 2 bytes are a 16 bits unsigned checksum which is expected
* to make the addition al all 16 bit unsigned values in the array add
* up to 1 (rather then the usual 0), so we must set the last byte to 1.
*/
ts->bak_ref[ts->bak_ref_len - 1] = 1;
return 0;
}
static int goodix_send_main_clock(struct goodix_ts_data *ts)
{
u32 main_clk = 54; /* Default main clock */
u8 checksum = 0;
int i;
device_property_read_u32(&ts->client->dev,
"goodix,main-clk", &main_clk);
for (i = 0; i < (GOODIX_MAIN_CLK_LEN - 1); i++) {
ts->main_clk[i] = main_clk;
checksum += main_clk;
}
/* The value of all bytes combines must be 0 */
ts->main_clk[GOODIX_MAIN_CLK_LEN - 1] = 256 - checksum;
return goodix_i2c_write(ts->client, GOODIX_REG_MAIN_CLK,
ts->main_clk, GOODIX_MAIN_CLK_LEN);
}
int goodix_firmware_check(struct goodix_ts_data *ts)
{
device_property_read_string(&ts->client->dev,
"firmware-name", &ts->firmware_name);
if (!ts->firmware_name)
return 0;
if (ts->irq_pin_access_method == IRQ_PIN_ACCESS_NONE) {
dev_err(&ts->client->dev, "Error no IRQ-pin access method, cannot upload fw.\n");
return -EINVAL;
}
dev_info(&ts->client->dev, "Touchscreen controller needs fw-upload\n");
ts->load_cfg_from_disk = true;
return goodix_firmware_upload(ts);
}
bool goodix_handle_fw_request(struct goodix_ts_data *ts)
{
int error;
u8 val;
error = goodix_i2c_read(ts->client, GOODIX_REG_REQUEST, &val, 1);
if (error)
return false;
switch (val) {
case GOODIX_RQST_RESPONDED:
/*
* If we read back our own last ack the IRQ was not for
* a request.
*/
return false;
case GOODIX_RQST_CONFIG:
error = goodix_send_cfg(ts, ts->config, ts->chip->config_len);
if (error)
return false;
break;
case GOODIX_RQST_BAK_REF:
error = goodix_prepare_bak_ref(ts);
if (error)
return false;
error = goodix_i2c_write(ts->client, GOODIX_REG_BAK_REF,
ts->bak_ref, ts->bak_ref_len);
if (error)
return false;
break;
case GOODIX_RQST_RESET:
error = goodix_firmware_upload(ts);
if (error)
return false;
break;
case GOODIX_RQST_MAIN_CLOCK:
error = goodix_send_main_clock(ts);
if (error)
return false;
break;
case GOODIX_RQST_UNKNOWN:
case GOODIX_RQST_IDLE:
break;
default:
dev_err_ratelimited(&ts->client->dev, "Unknown Request: 0x%02x\n", val);
}
/* Ack the request */
goodix_i2c_write_u8(ts->client,
GOODIX_REG_REQUEST, GOODIX_RQST_RESPONDED);
return true;
}
void goodix_save_bak_ref(struct goodix_ts_data *ts)
{
int error;
u8 val;
if (!ts->firmware_name)
return;
error = goodix_i2c_read(ts->client, GOODIX_REG_STATUS, &val, 1);
if (error)
return;
if (!(val & 0x80))
return;
error = goodix_i2c_read(ts->client, GOODIX_REG_BAK_REF,
ts->bak_ref, ts->bak_ref_len);
if (error) {
memset(ts->bak_ref, 0, ts->bak_ref_len);
ts->bak_ref[ts->bak_ref_len - 1] = 1;
}
}
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Stubs for PHY library functionality called by the core network stack.
* These are necessary because CONFIG_PHYLIB can be a module, and built-in
* code cannot directly call symbols exported by modules.
*/
#include <linux/phylib_stubs.h>
const struct phylib_stubs *phylib_stubs;
EXPORT_SYMBOL_GPL(phylib_stubs);
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* SImple Tiler Allocator (SiTA): 2D and 1D allocation(reservation) algorithm
*
* Authors: Ravi Ramachandra <[email protected]>,
* Lajos Molnar <[email protected]>
* Andy Gross <[email protected]>
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/bitmap.h>
#include <linux/slab.h>
#include "tcm.h"
static unsigned long mask[8];
/*
* pos position in bitmap
* w width in slots
* h height in slots
* map ptr to bitmap
* stride slots in a row
*/
static void free_slots(unsigned long pos, u16 w, u16 h,
unsigned long *map, u16 stride)
{
int i;
for (i = 0; i < h; i++, pos += stride)
bitmap_clear(map, pos, w);
}
/*
* w width in slots
* pos ptr to position
* map ptr to bitmap
* num_bits number of bits in bitmap
*/
static int r2l_b2t_1d(u16 w, unsigned long *pos, unsigned long *map,
size_t num_bits)
{
unsigned long search_count = 0;
unsigned long bit;
bool area_found = false;
*pos = num_bits - w;
while (search_count < num_bits) {
bit = find_next_bit(map, num_bits, *pos);
if (bit - *pos >= w) {
/* found a long enough free area */
bitmap_set(map, *pos, w);
area_found = true;
break;
}
search_count = num_bits - bit + w;
*pos = bit - w;
}
return (area_found) ? 0 : -ENOMEM;
}
/*
* w = width in slots
* h = height in slots
* a = align in slots (mask, 2^n-1, 0 is unaligned)
* offset = offset in bytes from 4KiB
* pos = position in bitmap for buffer
* map = bitmap ptr
* num_bits = size of bitmap
* stride = bits in one row of container
*/
static int l2r_t2b(u16 w, u16 h, u16 a, s16 offset,
unsigned long *pos, unsigned long slot_bytes,
unsigned long *map, size_t num_bits, size_t slot_stride)
{
int i;
unsigned long index;
bool area_free = false;
unsigned long slots_per_band = PAGE_SIZE / slot_bytes;
unsigned long bit_offset = (offset > 0) ? offset / slot_bytes : 0;
unsigned long curr_bit = bit_offset;
/* reset alignment to 1 if we are matching a specific offset */
/* adjust alignment - 1 to get to the format expected in bitmaps */
a = (offset > 0) ? 0 : a - 1;
/* FIXME Return error if slots_per_band > stride */
while (curr_bit < num_bits) {
*pos = bitmap_find_next_zero_area(map, num_bits, curr_bit, w,
a);
/* skip forward if we are not at right offset */
if (bit_offset > 0 && (*pos % slots_per_band != bit_offset)) {
curr_bit = ALIGN(*pos, slots_per_band) + bit_offset;
continue;
}
/* skip forward to next row if we overlap end of row */
if ((*pos % slot_stride) + w > slot_stride) {
curr_bit = ALIGN(*pos, slot_stride) + bit_offset;
continue;
}
/* TODO: Handle overlapping 4K boundaries */
/* break out of look if we will go past end of container */
if ((*pos + slot_stride * h) > num_bits)
break;
/* generate mask that represents out matching pattern */
bitmap_clear(mask, 0, slot_stride);
bitmap_set(mask, (*pos % BITS_PER_LONG), w);
/* assume the area is free until we find an overlap */
area_free = true;
/* check subsequent rows to see if complete area is free */
for (i = 1; i < h; i++) {
index = *pos / BITS_PER_LONG + i * 8;
if (bitmap_intersects(&map[index], mask,
(*pos % BITS_PER_LONG) + w)) {
area_free = false;
break;
}
}
if (area_free)
break;
/* go forward past this match */
if (bit_offset > 0)
curr_bit = ALIGN(*pos, slots_per_band) + bit_offset;
else
curr_bit = *pos + a + 1;
}
if (area_free) {
/* set area as in-use. iterate over rows */
for (i = 0, index = *pos; i < h; i++, index += slot_stride)
bitmap_set(map, index, w);
}
return (area_free) ? 0 : -ENOMEM;
}
static s32 sita_reserve_1d(struct tcm *tcm, u32 num_slots,
struct tcm_area *area)
{
unsigned long pos;
int ret;
spin_lock(&(tcm->lock));
ret = r2l_b2t_1d(num_slots, &pos, tcm->bitmap, tcm->map_size);
if (!ret) {
area->p0.x = pos % tcm->width;
area->p0.y = pos / tcm->width;
area->p1.x = (pos + num_slots - 1) % tcm->width;
area->p1.y = (pos + num_slots - 1) / tcm->width;
}
spin_unlock(&(tcm->lock));
return ret;
}
static s32 sita_reserve_2d(struct tcm *tcm, u16 h, u16 w, u16 align,
s16 offset, u16 slot_bytes,
struct tcm_area *area)
{
unsigned long pos;
int ret;
spin_lock(&(tcm->lock));
ret = l2r_t2b(w, h, align, offset, &pos, slot_bytes, tcm->bitmap,
tcm->map_size, tcm->width);
if (!ret) {
area->p0.x = pos % tcm->width;
area->p0.y = pos / tcm->width;
area->p1.x = area->p0.x + w - 1;
area->p1.y = area->p0.y + h - 1;
}
spin_unlock(&(tcm->lock));
return ret;
}
static void sita_deinit(struct tcm *tcm)
{
kfree(tcm);
}
static s32 sita_free(struct tcm *tcm, struct tcm_area *area)
{
unsigned long pos;
u16 w, h;
pos = area->p0.x + area->p0.y * tcm->width;
if (area->is2d) {
w = area->p1.x - area->p0.x + 1;
h = area->p1.y - area->p0.y + 1;
} else {
w = area->p1.x + area->p1.y * tcm->width - pos + 1;
h = 1;
}
spin_lock(&(tcm->lock));
free_slots(pos, w, h, tcm->bitmap, tcm->width);
spin_unlock(&(tcm->lock));
return 0;
}
struct tcm *sita_init(u16 width, u16 height)
{
struct tcm *tcm;
size_t map_size = BITS_TO_LONGS(width*height) * sizeof(unsigned long);
if (width == 0 || height == 0)
return NULL;
tcm = kzalloc(sizeof(*tcm) + map_size, GFP_KERNEL);
if (!tcm)
goto error;
/* Updating the pointers to SiTA implementation APIs */
tcm->height = height;
tcm->width = width;
tcm->reserve_2d = sita_reserve_2d;
tcm->reserve_1d = sita_reserve_1d;
tcm->free = sita_free;
tcm->deinit = sita_deinit;
spin_lock_init(&tcm->lock);
tcm->bitmap = (unsigned long *)(tcm + 1);
bitmap_clear(tcm->bitmap, 0, width*height);
tcm->map_size = width*height;
return tcm;
error:
return NULL;
}
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* The Virtual DVB test driver serves as a reference DVB driver and helps
* validate the existing APIs in the media subsystem. It can also aid
* developers working on userspace applications.
*
* Copyright (C) 2020 Daniel W. S. Almeida
*/
#ifndef VIDTV_COMMON_H
#define VIDTV_COMMON_H
#include <linux/types.h>
#define CLOCK_UNIT_90KHZ 90000
#define CLOCK_UNIT_27MHZ 27000000
#define VIDTV_SLEEP_USECS 10000
#define VIDTV_MAX_SLEEP_USECS (2 * VIDTV_SLEEP_USECS)
u32 vidtv_memcpy(void *to,
size_t to_offset,
size_t to_size,
const void *from,
size_t len);
u32 vidtv_memset(void *to,
size_t to_offset,
size_t to_size,
int c,
size_t len);
#endif // VIDTV_COMMON_H
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_SECCOMP_TYPES_H
#define _LINUX_SECCOMP_TYPES_H
#include <linux/types.h>
#ifdef CONFIG_SECCOMP
struct seccomp_filter;
/**
* struct seccomp - the state of a seccomp'ed process
*
* @mode: indicates one of the valid values above for controlled
* system calls available to a process.
* @filter_count: number of seccomp filters
* @filter: must always point to a valid seccomp-filter or NULL as it is
* accessed without locking during system call entry.
*
* @filter must only be accessed from the context of current as there
* is no read locking.
*/
struct seccomp {
int mode;
atomic_t filter_count;
struct seccomp_filter *filter;
};
#else
struct seccomp { };
struct seccomp_filter { };
#endif
#endif /* _LINUX_SECCOMP_TYPES_H */
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2019 Google LLC
*
* Device-tree for Krane sku0.
*
* SKU is a 8-bit value (0x00 == 0):
* - Bits 7..4: Panel ID: 0x0 (AUO)
* - Bits 3..0: SKU ID: 0x0 (default)
*/
/dts-v1/;
#include "mt8183-kukui-krane.dtsi"
/ {
model = "MediaTek krane sku0 board";
chassis-type = "tablet";
compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
};
&panel {
status = "okay";
compatible = "auo,kd101n80-45na";
};
|
// SPDX-License-Identifier: GPL-2.0
/*
* Huawei WMI laptop extras driver
*
* Copyright (C) 2018 Ayman Bagabas <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/input.h>
#include <linux/input/sparse-keymap.h>
#include <linux/leds.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/power_supply.h>
#include <linux/sysfs.h>
#include <linux/wmi.h>
#include <acpi/battery.h>
/*
* Huawei WMI GUIDs
*/
#define HWMI_METHOD_GUID "ABBC0F5B-8EA1-11D1-A000-C90629100000"
#define HWMI_EVENT_GUID "ABBC0F5C-8EA1-11D1-A000-C90629100000"
/* Legacy GUIDs */
#define WMI0_EXPENSIVE_GUID "39142400-C6A3-40fa-BADB-8A2652834100"
#define WMI0_EVENT_GUID "59142400-C6A3-40fa-BADB-8A2652834100"
/* HWMI commands */
enum {
BATTERY_THRESH_GET = 0x00001103, /* \GBTT */
BATTERY_THRESH_SET = 0x00001003, /* \SBTT */
FN_LOCK_GET = 0x00000604, /* \GFRS */
FN_LOCK_SET = 0x00000704, /* \SFRS */
MICMUTE_LED_SET = 0x00000b04, /* \SMLS */
};
union hwmi_arg {
u64 cmd;
u8 args[8];
};
struct quirk_entry {
bool battery_reset;
bool ec_micmute;
bool report_brightness;
};
static struct quirk_entry *quirks;
struct huawei_wmi_debug {
struct dentry *root;
u64 arg;
};
struct huawei_wmi {
bool battery_available;
bool fn_lock_available;
struct huawei_wmi_debug debug;
struct led_classdev cdev;
struct device *dev;
struct mutex wmi_lock;
};
static struct huawei_wmi *huawei_wmi;
static const struct key_entry huawei_wmi_keymap[] = {
{ KE_KEY, 0x281, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0x282, { KEY_BRIGHTNESSUP } },
{ KE_KEY, 0x284, { KEY_MUTE } },
{ KE_KEY, 0x285, { KEY_VOLUMEDOWN } },
{ KE_KEY, 0x286, { KEY_VOLUMEUP } },
{ KE_KEY, 0x287, { KEY_MICMUTE } },
{ KE_KEY, 0x289, { KEY_WLAN } },
// Huawei |M| key
{ KE_KEY, 0x28a, { KEY_CONFIG } },
// Keyboard backlit
{ KE_IGNORE, 0x293, { KEY_KBDILLUMTOGGLE } },
{ KE_IGNORE, 0x294, { KEY_KBDILLUMUP } },
{ KE_IGNORE, 0x295, { KEY_KBDILLUMUP } },
// Ignore Ambient Light Sensoring
{ KE_KEY, 0x2c1, { KEY_RESERVED } },
{ KE_END, 0 }
};
static int battery_reset = -1;
static int report_brightness = -1;
module_param(battery_reset, bint, 0444);
MODULE_PARM_DESC(battery_reset,
"Reset battery charge values to (0-0) before disabling it using (0-100)");
module_param(report_brightness, bint, 0444);
MODULE_PARM_DESC(report_brightness,
"Report brightness keys.");
/* Quirks */
static int __init dmi_matched(const struct dmi_system_id *dmi)
{
quirks = dmi->driver_data;
return 1;
}
static struct quirk_entry quirk_unknown = {
};
static struct quirk_entry quirk_battery_reset = {
.battery_reset = true,
};
static struct quirk_entry quirk_matebook_x = {
.ec_micmute = true,
.report_brightness = true,
};
static const struct dmi_system_id huawei_quirks[] = {
{
.callback = dmi_matched,
.ident = "Huawei MACH-WX9",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HUAWEI"),
DMI_MATCH(DMI_PRODUCT_NAME, "MACH-WX9"),
},
.driver_data = &quirk_battery_reset
},
{
.callback = dmi_matched,
.ident = "Huawei MateBook X",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HUAWEI"),
DMI_MATCH(DMI_PRODUCT_NAME, "HUAWEI MateBook X")
},
.driver_data = &quirk_matebook_x
},
{ }
};
/* Utils */
static int huawei_wmi_call(struct huawei_wmi *huawei,
struct acpi_buffer *in, struct acpi_buffer *out)
{
acpi_status status;
mutex_lock(&huawei->wmi_lock);
status = wmi_evaluate_method(HWMI_METHOD_GUID, 0, 1, in, out);
mutex_unlock(&huawei->wmi_lock);
if (ACPI_FAILURE(status)) {
dev_err(huawei->dev, "Failed to evaluate wmi method\n");
return -ENODEV;
}
return 0;
}
/* HWMI takes a 64 bit input and returns either a package with 2 buffers, one of
* 4 bytes and the other of 256 bytes, or one buffer of size 0x104 (260) bytes.
* The first 4 bytes are ignored, we ignore the first 4 bytes buffer if we got a
* package, or skip the first 4 if a buffer of 0x104 is used. The first byte of
* the remaining 0x100 sized buffer has the return status of every call. In case
* the return status is non-zero, we return -ENODEV but still copy the returned
* buffer to the given buffer parameter (buf).
*/
static int huawei_wmi_cmd(u64 arg, u8 *buf, size_t buflen)
{
struct huawei_wmi *huawei = huawei_wmi;
struct acpi_buffer out = { ACPI_ALLOCATE_BUFFER, NULL };
struct acpi_buffer in;
union acpi_object *obj;
size_t len;
int err, i;
in.length = sizeof(arg);
in.pointer = &arg;
/* Some models require calling HWMI twice to execute a command. We evaluate
* HWMI and if we get a non-zero return status we evaluate it again.
*/
for (i = 0; i < 2; i++) {
err = huawei_wmi_call(huawei, &in, &out);
if (err)
goto fail_cmd;
obj = out.pointer;
if (!obj) {
err = -EIO;
goto fail_cmd;
}
switch (obj->type) {
/* Models that implement both "legacy" and HWMI tend to return a 0x104
* sized buffer instead of a package of 0x4 and 0x100 buffers.
*/
case ACPI_TYPE_BUFFER:
if (obj->buffer.length == 0x104) {
// Skip the first 4 bytes.
obj->buffer.pointer += 4;
len = 0x100;
} else {
dev_err(huawei->dev, "Bad buffer length, got %d\n", obj->buffer.length);
err = -EIO;
goto fail_cmd;
}
break;
/* HWMI returns a package with 2 buffer elements, one of 4 bytes and the
* other is 256 bytes.
*/
case ACPI_TYPE_PACKAGE:
if (obj->package.count != 2) {
dev_err(huawei->dev, "Bad package count, got %d\n", obj->package.count);
err = -EIO;
goto fail_cmd;
}
obj = &obj->package.elements[1];
if (obj->type != ACPI_TYPE_BUFFER) {
dev_err(huawei->dev, "Bad package element type, got %d\n", obj->type);
err = -EIO;
goto fail_cmd;
}
len = obj->buffer.length;
break;
/* Shouldn't get here! */
default:
dev_err(huawei->dev, "Unexpected obj type, got: %d\n", obj->type);
err = -EIO;
goto fail_cmd;
}
if (!*obj->buffer.pointer)
break;
}
err = (*obj->buffer.pointer) ? -ENODEV : 0;
if (buf) {
len = min(buflen, len);
memcpy(buf, obj->buffer.pointer, len);
}
fail_cmd:
kfree(out.pointer);
return err;
}
/* LEDs */
static int huawei_wmi_micmute_led_set(struct led_classdev *led_cdev,
enum led_brightness brightness)
{
/* This is a workaround until the "legacy" interface is implemented. */
if (quirks && quirks->ec_micmute) {
char *acpi_method;
acpi_handle handle;
acpi_status status;
union acpi_object args[3];
struct acpi_object_list arg_list = {
.pointer = args,
.count = ARRAY_SIZE(args),
};
handle = ec_get_handle();
if (!handle)
return -ENODEV;
args[0].type = args[1].type = args[2].type = ACPI_TYPE_INTEGER;
args[1].integer.value = 0x04;
if (acpi_has_method(handle, "SPIN")) {
acpi_method = "SPIN";
args[0].integer.value = 0;
args[2].integer.value = brightness ? 1 : 0;
} else if (acpi_has_method(handle, "WPIN")) {
acpi_method = "WPIN";
args[0].integer.value = 1;
args[2].integer.value = brightness ? 0 : 1;
} else {
return -ENODEV;
}
status = acpi_evaluate_object(handle, acpi_method, &arg_list, NULL);
if (ACPI_FAILURE(status))
return -ENODEV;
return 0;
} else {
union hwmi_arg arg;
arg.cmd = MICMUTE_LED_SET;
arg.args[2] = brightness;
return huawei_wmi_cmd(arg.cmd, NULL, 0);
}
}
static void huawei_wmi_leds_setup(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
huawei->cdev.name = "platform::micmute";
huawei->cdev.max_brightness = 1;
huawei->cdev.brightness_set_blocking = &huawei_wmi_micmute_led_set;
huawei->cdev.default_trigger = "audio-micmute";
huawei->cdev.dev = dev;
huawei->cdev.flags = LED_CORE_SUSPENDRESUME;
devm_led_classdev_register(dev, &huawei->cdev);
}
/* Battery protection */
static int huawei_wmi_battery_get(int *start, int *end)
{
u8 ret[0x100];
int err, i;
err = huawei_wmi_cmd(BATTERY_THRESH_GET, ret, sizeof(ret));
if (err)
return err;
/* Find the last two non-zero values. Return status is ignored. */
i = ARRAY_SIZE(ret) - 1;
do {
if (start)
*start = ret[i-1];
if (end)
*end = ret[i];
} while (i > 2 && !ret[i--]);
return 0;
}
static int huawei_wmi_battery_set(int start, int end)
{
union hwmi_arg arg;
int err;
if (start < 0 || end < 0 || start > 100 || end > 100)
return -EINVAL;
arg.cmd = BATTERY_THRESH_SET;
arg.args[2] = start;
arg.args[3] = end;
/* This is an edge case were some models turn battery protection
* off without changing their thresholds values. We clear the
* values before turning off protection. Sometimes we need a sleep delay to
* make sure these values make their way to EC memory.
*/
if (quirks && quirks->battery_reset && start == 0 && end == 100) {
err = huawei_wmi_battery_set(0, 0);
if (err)
return err;
msleep(1000);
}
err = huawei_wmi_cmd(arg.cmd, NULL, 0);
return err;
}
static ssize_t charge_control_start_threshold_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
int err, start;
err = huawei_wmi_battery_get(&start, NULL);
if (err)
return err;
return sysfs_emit(buf, "%d\n", start);
}
static ssize_t charge_control_end_threshold_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
int err, end;
err = huawei_wmi_battery_get(NULL, &end);
if (err)
return err;
return sysfs_emit(buf, "%d\n", end);
}
static ssize_t charge_control_thresholds_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
int err, start, end;
err = huawei_wmi_battery_get(&start, &end);
if (err)
return err;
return sysfs_emit(buf, "%d %d\n", start, end);
}
static ssize_t charge_control_start_threshold_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int err, start, end;
err = huawei_wmi_battery_get(NULL, &end);
if (err)
return err;
if (sscanf(buf, "%d", &start) != 1)
return -EINVAL;
err = huawei_wmi_battery_set(start, end);
if (err)
return err;
return size;
}
static ssize_t charge_control_end_threshold_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int err, start, end;
err = huawei_wmi_battery_get(&start, NULL);
if (err)
return err;
if (sscanf(buf, "%d", &end) != 1)
return -EINVAL;
err = huawei_wmi_battery_set(start, end);
if (err)
return err;
return size;
}
static ssize_t charge_control_thresholds_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int err, start, end;
if (sscanf(buf, "%d %d", &start, &end) != 2)
return -EINVAL;
err = huawei_wmi_battery_set(start, end);
if (err)
return err;
return size;
}
static DEVICE_ATTR_RW(charge_control_start_threshold);
static DEVICE_ATTR_RW(charge_control_end_threshold);
static DEVICE_ATTR_RW(charge_control_thresholds);
static int huawei_wmi_battery_add(struct power_supply *battery, struct acpi_battery_hook *hook)
{
int err = 0;
err = device_create_file(&battery->dev, &dev_attr_charge_control_start_threshold);
if (err)
return err;
err = device_create_file(&battery->dev, &dev_attr_charge_control_end_threshold);
if (err)
device_remove_file(&battery->dev, &dev_attr_charge_control_start_threshold);
return err;
}
static int huawei_wmi_battery_remove(struct power_supply *battery, struct acpi_battery_hook *hook)
{
device_remove_file(&battery->dev, &dev_attr_charge_control_start_threshold);
device_remove_file(&battery->dev, &dev_attr_charge_control_end_threshold);
return 0;
}
static struct acpi_battery_hook huawei_wmi_battery_hook = {
.add_battery = huawei_wmi_battery_add,
.remove_battery = huawei_wmi_battery_remove,
.name = "Huawei Battery Extension"
};
static void huawei_wmi_battery_setup(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
huawei->battery_available = true;
if (huawei_wmi_battery_get(NULL, NULL)) {
huawei->battery_available = false;
return;
}
battery_hook_register(&huawei_wmi_battery_hook);
device_create_file(dev, &dev_attr_charge_control_thresholds);
}
static void huawei_wmi_battery_exit(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
if (huawei->battery_available) {
battery_hook_unregister(&huawei_wmi_battery_hook);
device_remove_file(dev, &dev_attr_charge_control_thresholds);
}
}
/* Fn lock */
static int huawei_wmi_fn_lock_get(int *on)
{
u8 ret[0x100] = { 0 };
int err, i;
err = huawei_wmi_cmd(FN_LOCK_GET, ret, 0x100);
if (err)
return err;
/* Find the first non-zero value. Return status is ignored. */
i = 1;
do {
if (on)
*on = ret[i] - 1; // -1 undefined, 0 off, 1 on.
} while (i < 0xff && !ret[i++]);
return 0;
}
static int huawei_wmi_fn_lock_set(int on)
{
union hwmi_arg arg;
arg.cmd = FN_LOCK_SET;
arg.args[2] = on + 1; // 0 undefined, 1 off, 2 on.
return huawei_wmi_cmd(arg.cmd, NULL, 0);
}
static ssize_t fn_lock_state_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
int err, on;
err = huawei_wmi_fn_lock_get(&on);
if (err)
return err;
return sysfs_emit(buf, "%d\n", on);
}
static ssize_t fn_lock_state_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int on, err;
if (kstrtoint(buf, 10, &on) ||
on < 0 || on > 1)
return -EINVAL;
err = huawei_wmi_fn_lock_set(on);
if (err)
return err;
return size;
}
static DEVICE_ATTR_RW(fn_lock_state);
static void huawei_wmi_fn_lock_setup(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
huawei->fn_lock_available = true;
if (huawei_wmi_fn_lock_get(NULL)) {
huawei->fn_lock_available = false;
return;
}
device_create_file(dev, &dev_attr_fn_lock_state);
}
static void huawei_wmi_fn_lock_exit(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
if (huawei->fn_lock_available)
device_remove_file(dev, &dev_attr_fn_lock_state);
}
/* debugfs */
static void huawei_wmi_debugfs_call_dump(struct seq_file *m, void *data,
union acpi_object *obj)
{
struct huawei_wmi *huawei = m->private;
int i;
switch (obj->type) {
case ACPI_TYPE_INTEGER:
seq_printf(m, "0x%llx", obj->integer.value);
break;
case ACPI_TYPE_STRING:
seq_printf(m, "\"%.*s\"", obj->string.length, obj->string.pointer);
break;
case ACPI_TYPE_BUFFER:
seq_puts(m, "{");
for (i = 0; i < obj->buffer.length; i++) {
seq_printf(m, "0x%02x", obj->buffer.pointer[i]);
if (i < obj->buffer.length - 1)
seq_puts(m, ",");
}
seq_puts(m, "}");
break;
case ACPI_TYPE_PACKAGE:
seq_puts(m, "[");
for (i = 0; i < obj->package.count; i++) {
huawei_wmi_debugfs_call_dump(m, huawei, &obj->package.elements[i]);
if (i < obj->package.count - 1)
seq_puts(m, ",");
}
seq_puts(m, "]");
break;
default:
dev_err(huawei->dev, "Unexpected obj type, got %d\n", obj->type);
return;
}
}
static int huawei_wmi_debugfs_call_show(struct seq_file *m, void *data)
{
struct huawei_wmi *huawei = m->private;
struct acpi_buffer out = { ACPI_ALLOCATE_BUFFER, NULL };
struct acpi_buffer in;
union acpi_object *obj;
int err;
in.length = sizeof(u64);
in.pointer = &huawei->debug.arg;
err = huawei_wmi_call(huawei, &in, &out);
if (err)
return err;
obj = out.pointer;
if (!obj) {
err = -EIO;
goto fail_debugfs_call;
}
huawei_wmi_debugfs_call_dump(m, huawei, obj);
fail_debugfs_call:
kfree(out.pointer);
return err;
}
DEFINE_SHOW_ATTRIBUTE(huawei_wmi_debugfs_call);
static void huawei_wmi_debugfs_setup(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
huawei->debug.root = debugfs_create_dir("huawei-wmi", NULL);
debugfs_create_x64("arg", 0644, huawei->debug.root,
&huawei->debug.arg);
debugfs_create_file("call", 0400,
huawei->debug.root, huawei, &huawei_wmi_debugfs_call_fops);
}
static void huawei_wmi_debugfs_exit(struct device *dev)
{
struct huawei_wmi *huawei = dev_get_drvdata(dev);
debugfs_remove_recursive(huawei->debug.root);
}
/* Input */
static void huawei_wmi_process_key(struct input_dev *idev, int code)
{
const struct key_entry *key;
/*
* WMI0 uses code 0x80 to indicate a hotkey event.
* The actual key is fetched from the method WQ00
* using WMI0_EXPENSIVE_GUID.
*/
if (code == 0x80) {
struct acpi_buffer response = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *obj;
acpi_status status;
status = wmi_query_block(WMI0_EXPENSIVE_GUID, 0, &response);
if (ACPI_FAILURE(status))
return;
obj = (union acpi_object *)response.pointer;
if (obj && obj->type == ACPI_TYPE_INTEGER)
code = obj->integer.value;
kfree(response.pointer);
}
key = sparse_keymap_entry_from_scancode(idev, code);
if (!key) {
dev_info(&idev->dev, "Unknown key pressed, code: 0x%04x\n", code);
return;
}
if (quirks && !quirks->report_brightness &&
(key->sw.code == KEY_BRIGHTNESSDOWN ||
key->sw.code == KEY_BRIGHTNESSUP))
return;
sparse_keymap_report_entry(idev, key, 1, true);
}
static void huawei_wmi_input_notify(union acpi_object *obj, void *context)
{
struct input_dev *idev = (struct input_dev *)context;
if (obj && obj->type == ACPI_TYPE_INTEGER)
huawei_wmi_process_key(idev, obj->integer.value);
else
dev_err(&idev->dev, "Bad response type\n");
}
static int huawei_wmi_input_setup(struct device *dev, const char *guid)
{
struct input_dev *idev;
acpi_status status;
int err;
idev = devm_input_allocate_device(dev);
if (!idev)
return -ENOMEM;
idev->name = "Huawei WMI hotkeys";
idev->phys = "wmi/input0";
idev->id.bustype = BUS_HOST;
idev->dev.parent = dev;
err = sparse_keymap_setup(idev, huawei_wmi_keymap, NULL);
if (err)
return err;
err = input_register_device(idev);
if (err)
return err;
status = wmi_install_notify_handler(guid, huawei_wmi_input_notify, idev);
if (ACPI_FAILURE(status))
return -EIO;
return 0;
}
static void huawei_wmi_input_exit(struct device *dev, const char *guid)
{
wmi_remove_notify_handler(guid);
}
/* Huawei driver */
static const struct wmi_device_id huawei_wmi_events_id_table[] = {
{ .guid_string = WMI0_EVENT_GUID },
{ .guid_string = HWMI_EVENT_GUID },
{ }
};
static int huawei_wmi_probe(struct platform_device *pdev)
{
const struct wmi_device_id *guid = huawei_wmi_events_id_table;
int err;
platform_set_drvdata(pdev, huawei_wmi);
huawei_wmi->dev = &pdev->dev;
while (*guid->guid_string) {
if (wmi_has_guid(guid->guid_string)) {
err = huawei_wmi_input_setup(&pdev->dev, guid->guid_string);
if (err) {
dev_err(&pdev->dev, "Failed to setup input on %s\n", guid->guid_string);
return err;
}
}
guid++;
}
if (wmi_has_guid(HWMI_METHOD_GUID)) {
mutex_init(&huawei_wmi->wmi_lock);
huawei_wmi_leds_setup(&pdev->dev);
huawei_wmi_fn_lock_setup(&pdev->dev);
huawei_wmi_battery_setup(&pdev->dev);
huawei_wmi_debugfs_setup(&pdev->dev);
}
return 0;
}
static void huawei_wmi_remove(struct platform_device *pdev)
{
const struct wmi_device_id *guid = huawei_wmi_events_id_table;
while (*guid->guid_string) {
if (wmi_has_guid(guid->guid_string))
huawei_wmi_input_exit(&pdev->dev, guid->guid_string);
guid++;
}
if (wmi_has_guid(HWMI_METHOD_GUID)) {
huawei_wmi_debugfs_exit(&pdev->dev);
huawei_wmi_battery_exit(&pdev->dev);
huawei_wmi_fn_lock_exit(&pdev->dev);
}
}
static struct platform_driver huawei_wmi_driver = {
.driver = {
.name = "huawei-wmi",
},
.probe = huawei_wmi_probe,
.remove = huawei_wmi_remove,
};
static __init int huawei_wmi_init(void)
{
struct platform_device *pdev;
int err;
huawei_wmi = kzalloc(sizeof(struct huawei_wmi), GFP_KERNEL);
if (!huawei_wmi)
return -ENOMEM;
quirks = &quirk_unknown;
dmi_check_system(huawei_quirks);
if (battery_reset != -1)
quirks->battery_reset = battery_reset;
if (report_brightness != -1)
quirks->report_brightness = report_brightness;
err = platform_driver_register(&huawei_wmi_driver);
if (err)
goto pdrv_err;
pdev = platform_device_register_simple("huawei-wmi", PLATFORM_DEVID_NONE, NULL, 0);
if (IS_ERR(pdev)) {
err = PTR_ERR(pdev);
goto pdev_err;
}
return 0;
pdev_err:
platform_driver_unregister(&huawei_wmi_driver);
pdrv_err:
kfree(huawei_wmi);
return err;
}
static __exit void huawei_wmi_exit(void)
{
struct platform_device *pdev = to_platform_device(huawei_wmi->dev);
platform_device_unregister(pdev);
platform_driver_unregister(&huawei_wmi_driver);
kfree(huawei_wmi);
}
module_init(huawei_wmi_init);
module_exit(huawei_wmi_exit);
MODULE_ALIAS("wmi:"HWMI_METHOD_GUID);
MODULE_DEVICE_TABLE(wmi, huawei_wmi_events_id_table);
MODULE_AUTHOR("Ayman Bagabas <[email protected]>");
MODULE_DESCRIPTION("Huawei WMI laptop extras driver");
MODULE_LICENSE("GPL v2");
|
/*
* ARM Juno Platform motherboard peripherals
*
* Copyright (c) 2013-2014 ARM Ltd
*
* This file is licensed under a dual GPLv2 or BSD license.
*
*/
/ {
mb_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "juno_mb:clk24mhz";
};
mb_clk25mhz: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "juno_mb:clk25mhz";
};
v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "juno_mb:refclk1mhz";
};
v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "juno_mb:refclk32khz";
};
mb_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "MCC_SB_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
gpio-keys {
compatible = "gpio-keys";
power-button {
debounce-interval = <50>;
wakeup-source;
linux,code = <116>;
label = "POWER";
gpios = <&iofpga_gpio0 0 0x4>;
};
home-button {
debounce-interval = <50>;
wakeup-source;
linux,code = <102>;
label = "HOME";
gpios = <&iofpga_gpio0 1 0x4>;
};
rlock-button {
debounce-interval = <50>;
wakeup-source;
linux,code = <152>;
label = "RLOCK";
gpios = <&iofpga_gpio0 2 0x4>;
};
vol-up-button {
debounce-interval = <50>;
wakeup-source;
linux,code = <115>;
label = "VOL+";
gpios = <&iofpga_gpio0 3 0x4>;
};
vol-down-button {
debounce-interval = <50>;
wakeup-source;
linux,code = <114>;
label = "VOL-";
gpios = <&iofpga_gpio0 4 0x4>;
};
nmi-button {
debounce-interval = <50>;
wakeup-source;
linux,code = <99>;
label = "NMI";
gpios = <&iofpga_gpio0 5 0x4>;
};
};
bus@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x8000000 0 0x8000000 0x18000000>;
motherboard-bus@8000000 {
compatible = "arm,vexpress,v2p-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
arm,hbi = <0x252>;
arm,vexpress,site = <0>;
flash@0 {
/* 2 * 32MiB NOR Flash memory mounted on CS0 */
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <4>;
/*
* Unfortunately, accessing the flash disturbs
* the CPU idle states (suspend) and CPU
* hotplug of the platform. For this reason,
* flash hardware access is disabled by default.
*/
status = "disabled";
partitions {
compatible = "arm,arm-firmware-suite";
};
};
ethernet@200000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <2 0x00000000 0x10000>;
interrupts = <3>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
clocks = <&mb_clk25mhz>;
vdd33a-supply = <&mb_fixed_3v3>;
vddvario-supply = <&mb_fixed_3v3>;
};
iofpga-bus@300000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
apbregs@10000 {
compatible = "arm,juno-fpga-apb-regs",
"syscon", "simple-mfd";
reg = <0x010000 0x1000>;
ranges = <0x0 0x10000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "vexpress:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "vexpress:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "vexpress:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "vexpress:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "vexpress:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "vexpress:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "vexpress:6";
default-state = "off";
};
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "vexpress:7";
default-state = "off";
};
};
mmc@50000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <5>;
/* cd-gpios = <&v2m_mmc_gpios 0 0>;
wp-gpios = <&v2m_mmc_gpios 1 0>; */
max-frequency = <12000000>;
vmmc-supply = <&mb_fixed_3v3>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "mclk", "apb_pclk";
};
kmi@60000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <8>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@70000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <8>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
watchdog@f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x10000>;
interrupts = <7>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "wdog_clk", "apb_pclk";
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x10000>;
interrupts = <9>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x10000>;
interrupts = <9>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x10000>;
interrupts = <0>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
};
iofpga_gpio0: gpio@1d0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x1d0000 0x1000>;
interrupts = <6>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
};
};
|
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Device Tree Source for mangOH Green Board with WP8548 Module
*
* Copyright (C) 2016 BayLibre, SAS.
* Author : Neil Armstrong <[email protected]>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "qcom-mdm9615-wp8548.dtsi"
/ {
model = "MangOH Green with WP8548 Module";
compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615";
aliases {
spi0 = &gsbi3_spi;
serial0 = &gsbi4_serial;
serial1 = &gsbi5_serial;
i2c0 = &gsbi5_i2c;
mmc0 = &sdcc1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&msmgpio {
/* MangOH GPIO Mapping :
* - 2 : GPIOEXP_INT2
* - 7 : IOT1_GPIO2
* - 8 : IOT0_GPIO4
* - 13: IOT0_GPIO3
* - 21: IOT1_GPIO4
* - 22: IOT2_GPIO1
* - 23: IOT2_GPIO2
* - 24: IOT2_GPIO3
* - 25: IOT1_GPIO1
* - 32: IOT1_GPIO3
* - 33: IOT0_GPIO2
* - 42: IOT0_GPIO1 and SD Card Detect
*/
gpioext1_pins: gpioext1-state {
gpioext1-pins {
pins = "gpio2";
function = "gpio";
bias-disable;
};
};
sdc_cd_pins: sdc-cd-state {
sdc-cd-pins {
pins = "gpio42";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&gsbi3_spi {
spi@0 {
compatible = "swir,mangoh-iotport-spi";
spi-max-frequency = <24000000>;
reg = <0>;
};
};
&gsbi5_i2c {
mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c_iot0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_iot1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_iot2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
usbhub: hub@8 {
compatible = "smsc,usb3503a";
reg = <0x8>;
connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>;
initial-mode = <1>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
gpioext0: pinctrl@3e {
/* GPIO Expander 0 Mapping :
* - 0: ARDUINO_RESET_Level shift
* - 1: BattChrgr_PG_N
* - 2: BattGauge_GPIO
* - 3: LED_ON (out active high)
* - 4: ATmega_reset_GPIO
* - 5: X
* - 6: PCM_ANALOG_SELECT (out active high)
* - 7: X
* - 8: Board_rev_res1 (in)
* - 9: Board_rev_res2 (in)
* - 10: UART_EXP1_ENn (out active low / pull-down)
* - 11: UART_EXP1_IN (out pull-down)
* - 12: UART_EXP2_IN (out pull-down)
* - 13: SDIO_SEL (out pull-down)
* - 14: SPI_EXP1_ENn (out active low / pull-down)
* - 15: SPI_EXP1_IN (out pull-down)
*/
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "semtech,sx1509q";
reg = <0x3e>;
interrupt-parent = <&gpioext1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
semtech,probe-reset;
gpio-controller;
interrupt-controller;
};
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
gpioext1: pinctrl@3f {
/* GPIO Expander 1 Mapping :
* - 0: GPIOEXP_INT1
* - 1: Battery detect
* - 2: GPIO_SCF3_RESET
* - 3: LED_CARD_DETECT_IOT0 (in)
* - 4: LED_CARD_DETECT_IOT1 (in)
* - 5: LED_CARD_DETECT_IOT2 (in)
* - 6: UIM2_PWM_SELECT
* - 7: UIM2_M2_S_SELECT
* - 8: TP900
* - 9: SENSOR_INT1 (in)
* - 10: SENSOR_INT2 (in)
* - 11: CARD_DETECT_IOT0 (in pull-up)
* - 12: CARD_DETECT_IOT2 (in pull-up)
* - 13: CARD_DETECT_IOT1 (in pull-up)
* - 14: GPIOEXP_INT3 (in active low / pull-up)
* - 15: BattChrgr_INT_N
*/
pinctrl-0 = <&gpioext1_pins>;
pinctrl-names = "default";
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "semtech,sx1509q";
reg = <0x3f>;
interrupt-parent = <&msmgpio>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
semtech,probe-reset;
gpio-controller;
interrupt-controller;
};
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
gpioext2: pinctrl@70 {
/* GPIO Expander 2 Mapping :
* - 0: USB_HUB_INTn
* - 1: HUB_CONNECT
* - 2: GPIO_IOT2_RESET (out active low / pull-up)
* - 3: GPIO_IOT1_RESET (out active low / pull-up)
* - 4: GPIO_IOT0_RESET (out active low / pull-up)
* - 5: TP901
* - 6: TP902
* - 7: TP903
* - 8: UART_EXP2_ENn (out active low / pull-down)
* - 9: PCM_EXP1_ENn (out active low)
* - 10: PCM_EXP1_SEL (out)
* - 11: ARD_FTDI
* - 12: TP904
* - 13: TP905
* - 14: TP906
* - 15: RS232_Enable (out active high / pull-up)
*/
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "semtech,sx1509q";
reg = <0x70>;
interrupt-parent = <&gpioext1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
semtech,probe-reset;
gpio-controller;
interrupt-controller;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&sdcc1 {
pinctrl-0 = <&sdc_cd_pins>;
pinctrl-names = "default";
disable-wp;
cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */
};
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.