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module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hdll__a31oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__a31oi_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule |
module synch_2 #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk // clock to synchronize on
);
reg [WIDTH-1:0] stage_1;
always @(posedge clk)
{o, stage_1} <= {stage_1, i};
endmodule |
module synch_3 #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk // clock to synchronize on
);
reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;
always @(posedge clk)
{stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i};
endmodule |
module synch_3r #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk, // clock to synchronize on
output wire rise // one-cycle rising edge pulse
);
reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;
assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0;
always @(posedge clk)
{stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i};
endmodule |
module sky130_fd_sc_hs__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule |
module outputs)
wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
wire emmu_access; // From etx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
wire etx_access; // From etx_arbiter of etx_arbiter.v
wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
wire etx_rd_wait; // From etx_protocol of etx_protocol.v
wire etx_remap_access; // From etx_remap of etx_remap.v
wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
wire etx_rr; // From etx_arbiter of etx_arbiter.v
wire etx_wr_wait; // From etx_protocol of etx_protocol.v
wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
wire gpio_enable; // From etx_cfg of etx_cfg.v
wire [14:0] mi_addr; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_cfg_dout; // From etx_cfg of etx_cfg.v
wire mi_cfg_en; // From etx_cfgif of ecfg_if.v
wire [63:0] mi_din; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_mmu_dout; // From etx_mmu of emmu.v
wire mi_mmu_en; // From etx_cfgif of ecfg_if.v
wire mi_we; // From etx_cfgif of ecfg_if.v
wire mmu_enable; // From etx_cfg of etx_cfg.v
wire remap_enable; // From etx_cfg of etx_cfg.v
wire tx_enable; // From etx_cfg of etx_cfg.v
// End of automatics
/************************************************************/
/*ELINK TRANSMIT ARBITER */
/************************************************************/
defparam etx_arbiter.ID=ID;
etx_arbiter etx_arbiter (
/*AUTOINST*/
// Outputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.txrr_wait (txrr_wait),
.etx_access (etx_access),
.etx_packet (etx_packet[PW-1:0]),
.etx_rr (etx_rr),
// Inputs
.clk (clk),
.reset (reset),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait),
.etx_cfg_wait (etx_cfg_wait),
.ctrlmode_bypass (ctrlmode_bypass),
.ctrlmode (ctrlmode[3:0]));
/************************************************************/
/* CONFIGURATOIN PACKET */
/************************************************************/
/*ecfg_if AUTO_TEMPLATE (
.\(.*\)_in (etx_\1[]),
.\(.*\)_out (etx_cfg_\1[]),
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
.wait_in (etx_cfg_wait),
);
*/
defparam etx_cfgif.RX =0;
ecfg_if etx_cfgif (.mi_dout3 (64'b0),
.mi_dout1 (64'b0),
.mi_dma_en (),
/*AUTOINST*/
// Outputs
.mi_mmu_en (mi_mmu_en),
.mi_cfg_en (mi_cfg_en),
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[63:0]),
.access_out (etx_cfg_access), // Templated
.packet_out (etx_cfg_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.access_in (etx_access), // Templated
.packet_in (etx_packet[PW-1:0]), // Templated
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
.wait_in (etx_cfg_wait)); // Templated
/************************************************************/
/* ETX CONFIGURATION REGISTERS */
/************************************************************/
/*etx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
.mi_en (mi_cfg_en),
);
*/
//todo: make more useufl
assign tx_status[15:0] = 16'b0;
/*
{2'b0, //15:14
etx_rd_wait, //13
etx_wr_wait, //12
txrr_fifo_read, //11
txrr_wait, //10
txrr_access, //9
txrd_fifo_read, //8
txrd_wait, //7
txrd_access, //6
txwr_fifo_read, //5
txwr_wait, //4
txwr_access, //3
1'b0, //2
1'b0, //1
1'b0 //0
};
*/
etx_cfg etx_cfg (
/*AUTOINST*/
// Outputs
.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
.tx_enable (tx_enable),
.mmu_enable (mmu_enable),
.gpio_enable (gpio_enable),
.remap_enable (remap_enable),
.gpio_data (gpio_data[8:0]),
.ctrlmode (ctrlmode[3:0]),
.ctrlmode_bypass (ctrlmode_bypass),
// Inputs
.reset (reset),
.clk (clk),
.mi_en (mi_cfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[31:0]),
.tx_status (tx_status[15:0]));
/************************************************************/
/* REMAPPING (SHIFT) DESTINATION ADDRESS */
/************************************************************/
/*etx_remap AUTO_TEMPLATE (
.emesh_\(.*\)_in (etx_\1[]),
.emesh_\(.*\)_out (etx_remap_\1[]),
.remap_en (remap_enable),
.remap_bypass (etx_rr),
.emesh_wait (etx_wait),
);
*/
etx_remap etx_remap (/*AUTOINST*/
// Outputs
.emesh_access_out(etx_remap_access), // Templated
.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.emesh_access_in(etx_access), // Templated
.emesh_packet_in(etx_packet[PW-1:0]), // Templated
.remap_en (remap_enable), // Templated
.remap_bypass (etx_rr), // Templated
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait));
/************************************************************/
/* EMMU */
/************************************************************/
/*emmu AUTO_TEMPLATE (
.emesh_\(.*\)_in (etx_remap_\1[]),
.emesh_\(.*\)_out (emmu_\1[]),
.mmu_en (mmu_enable),
.mmu_bp (etx_rr),
.rd_clk (clk),
.wr_clk (clk),
.emmu_access_out (emmu_access),
.emmu_packet_out (emmu_packet[PW-1:0]),
.mi_dout (mi_mmu_dout[DW-1:0]),
.emesh_rd_wait (etx_rd_wait),
.emesh_wr_wait (etx_wr_wait),
.emesh_packet_hi_out (),
.mi_en (mi_mmu_en),
);
*/
emmu etx_mmu (
/*AUTOINST*/
// Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
.emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
.emesh_packet_hi_out (), // Templated
// Inputs
.rd_clk (clk), // Templated
.wr_clk (clk), // Templated
.mmu_en (mmu_enable), // Templated
.mmu_bp (etx_rr), // Templated
.mi_en (mi_mmu_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[DW-1:0]),
.emesh_access_in (etx_remap_access), // Templated
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
.emesh_rd_wait (etx_rd_wait), // Templated
.emesh_wr_wait (etx_wr_wait)); // Templated
/************************************************************/
/*ELINK PROTOCOL LOGIC */
/************************************************************/
/*etx_protocol AUTO_TEMPLATE (
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait),
.etx_\(.*\) (emmu_\1[]),
.etx_wait (etx_wait),
);
*/
defparam etx_protocol.ID=ID;
etx_protocol etx_protocol (
/*AUTOINST*/
// Outputs
.etx_rd_wait (etx_rd_wait), // Templated
.etx_wr_wait (etx_wr_wait), // Templated
.tx_packet (tx_packet[PW-1:0]),
.tx_access (tx_access),
.tx_burst (tx_burst),
// Inputs
.reset (reset),
.clk (clk),
.etx_access (emmu_access), // Templated
.etx_packet (emmu_packet[PW-1:0]), // Templated
.tx_enable (tx_enable),
.gpio_data (gpio_data[8:0]),
.gpio_enable (gpio_enable),
.tx_io_wait (tx_io_wait),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait));
endmodule |
module multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
wire [WIDTH : 0] _a;
wire [WIDTH : 0] _b;
wire [2 * WIDTH - 1 : 0] _c;
assign _a = { {a[WIDTH - 1]}, {a[WIDTH - 1 : 0]} };
assign _b = { {b[WIDTH - 1]}, {b[WIDTH - 1 : 0]} };
assign c = _c;
_multiplier#(
.WIDTH(WIDTH + 1)
) mult(
.clk(clk),
.a(_a),
.b(_b),
.c(_c)
);
endmodule |
module _multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
localparam M_WIDTH = WIDTH;
localparam P_WIDTH = 2 * M_WIDTH;
reg [P_WIDTH - 1 : 0] P [M_WIDTH : 0];
reg signed [M_WIDTH - 1 : 0] M [M_WIDTH : 0];
reg [M_WIDTH - 1 : 0] Q;
assign c = P[M_WIDTH];
always @(a, b)
begin
P[0] <= { {(P_WIDTH){1'b0}}, {a} };
M[0] <= b;
end
always @(posedge clk)
begin
if (P[0][0])
begin
P[1] <= sub_shift_right(P[0], M[0]);
end
else
begin
P[1] <= shift_right(P[0]);
end
Q[0] <= P[0][0];
M[1] <= M[0];
end // always @ (posedge clk)
genvar i;
generate
for (i = 1; i < M_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
Q[i] <= P[i][0];
M[i + 1] <= M[i];
case( { P[i][0], Q[i - 1] } )
2'b01:
P[i + 1] <= add_shift_right(P[i], M[i]);
2'b10:
P[i + 1] <= sub_shift_right(P[i], M[i]);
default:
P[i + 1] <= shift_right(P[i]);
endcase
end
end // for (i = 0; i < WIDTH; i = i + 1)
endgenerate
function [P_WIDTH - 1 : 0] shift_right(input [P_WIDTH - 1 : 0] x);
shift_right = { {x[P_WIDTH - 1]}, x[P_WIDTH - 1 : 1] };
endfunction // shift_right
function [P_WIDTH - 1 : 0] add_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
add_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] + y}, {x[M_WIDTH - 1 : 0]} });
endfunction // add_shift_right
function [2 * WIDTH - 1 : 0] sub_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
sub_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] - y}, {x[M_WIDTH - 1 : 0]} });;
endfunction // sub_shift_right
endmodule |
module Decodificador(
input [6:0] Cuenta,
output reg [7:0] catodo1,catodo2,catodo3,catodo4
);
always @(*)
begin
case (Cuenta)
6'd0: begin
catodo1 <= 8'b00000011;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd1: begin
catodo1 <= 8'b10011111;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd2: begin
catodo1 <= 8'b00100101;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd3: begin
catodo1 <= 8'b00001101;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd4: begin
catodo1 <= 8'b10011001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd5: begin
catodo1 <= 8'b01001001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd6: begin
catodo1 <= 8'b01000001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd7: begin
catodo1 <= 8'b00011111;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd8: begin
catodo1 <= 8'b00000001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd9: begin
catodo1 <= 8'b00011001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd10: begin
catodo1 <= 8'b00000011;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd11: begin
catodo1 <= 8'b10011111;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd12: begin
catodo1 <= 8'b00100101;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd13: begin
catodo1 <= 8'b00001101;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd14: begin
catodo1 <= 8'b10011001;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd15: begin
catodo1 <= 8'b01001001;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
default: begin
catodo1 <= 8'b10011111;
catodo2 <= 8'b10011111;
catodo3 <= 8'b10011111;
catodo4 <= 8'b10011111;
end
endcase
end
endmodule |
module bmu (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
// outputs
output [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
// inputs
input cx0, cx1;
// registers
reg [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
always@ (cx0 or cx1)
begin
if (cx0==0 && cx1==0)
begin
bm0 <= 2'd0; // this is going from 00 to 00
bm1 <= 2'd2; // this is going from 00 to 10
bm2 <= 2'd2; // this is going from 01 to 00
bm3 <= 2'd0; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
else if (cx0==0 && cx1==1)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd2; // this is going from 10 to 01
bm5 <= 2'd0; // this is going from 10 to 11
bm6 <= 2'd0; // this is going from 11 to 01
bm7 <= 2'd2; // this is going from 11 to 11
end
else if (cx0==1 && cx1==0)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd0; // this is going from 10 to 01
bm5 <= 2'd2; // this is going from 10 to 11
bm6 <= 2'd2; // this is going from 11 to 01
bm7 <= 2'd0; // this is going from 11 to 11
end
else // if (cx0==1 && cx1==1)
begin
bm0 <= 2'd2; // this is going from 00 to 00
bm1 <= 2'd0; // this is going from 00 to 10
bm2 <= 2'd0; // this is going from 01 to 00
bm3 <= 2'd2; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
end // always @ (posedge clk)
endmodule |
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module core_top(
input clk, rst, run_n,
input [3:0] reg_addr_d,
output [15:0] reg_out
);
//wire clk;
wire reg_we, sram_we_n, ram_wren;
wire [2:0] alu_operator;
wire [3:0] reg_addr_a, reg_addr_b, reg_addr_c;
wire [15:0] ram_addr, ram_data, reg_data_a, reg_data_b, reg_data_c, reg_data_d, alu_op_a,alu_out,alu_status, ram_q,pc;
assign reg_out = reg_data_d;
assign ram_wren = ~sram_we_n;
//pll_slow mhz_5(clk_50, clk);
register_file register_file0(clk, rst, reg_we, reg_addr_a, reg_addr_b, reg_addr_c, reg_addr_d, reg_data_c, reg_data_a, reg_data_b, reg_data_d);
alu16 alu16_0( clk,rst,alu_operator, alu_op_a, reg_data_b, alu_out, alu_status);
control_fsm control_fsm0( clk, rst, run_n, ram_q, reg_data_a, reg_data_b, alu_status, alu_out,
sram_we_n, reg_we, alu_operator, reg_addr_a, reg_addr_b,
reg_addr_c, alu_op_a, reg_data_c, ram_addr, ram_data);
main_memory main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_sxm_d main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_sxm main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_ram_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_ram_test2 main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_addi_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_lw_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_sw_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_ble_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
endmodule |
module sky130_fd_sc_ms__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule |
module sky130_fd_sc_ls__xor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule |
module mig_7series_v2_0_ddr_phy_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter RANKS = 1, // # of DRAM ranks
parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter DEBUG_PORT = "OFF", // Enable debug port
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter OCAL_EN = "ON"
)
(
input clk,
input rst,
// Calibration status, control signals
input mpr_rdlvl_start,
output mpr_rdlvl_done,
output reg mpr_last_byte_done,
output mpr_rnk_done,
input rdlvl_stg1_start,
output reg rdlvl_stg1_done /* synthesis syn_maxfan = 30 */,
output rdlvl_stg1_rnk_done,
output reg rdlvl_stg1_err,
output mpr_rdlvl_err,
output rdlvl_err,
output reg rdlvl_prech_req,
output reg rdlvl_last_byte_done,
output reg rdlvl_assrt_common,
input prech_done,
input phy_if_empty,
input [4:0] idelaye2_init_val,
// Captured data in fabric clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Decrement initial Phaser_IN Fine tap delay
input dqs_po_dec_done,
input [5:0] pi_counter_read_val,
// Stage 1 calibration outputs
output reg pi_fine_dly_dec_done,
output reg pi_en_stg2_f,
output reg pi_stg2_f_incdec,
output reg pi_stg2_load,
output reg [5:0] pi_stg2_reg_l,
output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt,
// To DQ IDELAY required to find left edge of
// valid window
output idelay_ce,
output idelay_inc,
input idelay_ld,
input [DQS_CNT_WIDTH:0] wrcal_cnt,
// Only output if Per-bit de-skew enabled
output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// Debug Port
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl
);
// minimum time (in IDELAY taps) for which capture data must be stable for
// algorithm to consider a valid data eye to be found. The read leveling
// logic will ignore any window found smaller than this value. Limitations
// on how small this number can be is determined by: (1) the algorithmic
// limitation of how many taps wide the data eye can be (3 taps), and (2)
// how wide regions of "instability" that occur around the edges of the
// read valid window can be (i.e. need to be able to filter out "false"
// windows that occur for a short # of taps around the edges of the true
// data window, although with multi-sampling during read leveling, this is
// not as much a concern) - the larger the value, the more protection
// against "false" windows
localparam MIN_EYE_SIZE = 16;
// Length of calibration sequence (in # of words)
localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK);
// # of cycles required to perform read data shift register compare
// This is defined as from the cycle the new data is loaded until
// signal found_edge_r is valid
localparam RD_SHIFT_COMP_DELAY = 5;
// worst-case # of cycles to wait to ensure that both the SR and
// PREV_SR shift registers have valid data, and that the comparison
// of the two shift register values is valid. The "+1" at the end of
// this equation is a fudge factor, I freely admit that
localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1;
// # of clock cycles to wait after changing tap value or read data MUX
// to allow: (1) tap chain to settle, (2) for delayed input to propagate
// thru ISERDES, (3) for the read data comparison logic to have time to
// output the comparison of two consecutive samples of the settled read data
// The minimum delay is 16 cycles, which should be good enough to handle all
// three of the above conditions for the simulation-only case with a short
// training pattern. For H/W (or for simulation with longer training
// pattern), it will take longer to store and compare two consecutive
// samples, and the value of this parameter will reflect that
localparam PIPE_WAIT_CNT = (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8);
// # of read data samples to examine when detecting whether an edge has
// occured during stage 1 calibration. Width of local param must be
// changed as appropriate. Note that there are two counters used, each
// counter can be changed independently of the other - they are used in
// cascade to create a larger counter
localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF;
localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0
localparam [5:0] CAL1_IDLE = 6'h00;
localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01;
localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02;
localparam [5:0] CAL1_PAT_DETECT = 6'h03;
localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04;
localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05;
localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06;
localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07;
localparam [5:0] CAL1_DETECT_EDGE = 6'h08;
localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09;
localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A;
localparam [5:0] CAL1_CALC_IDEL = 6'h0B;
localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C;
localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D;
localparam [5:0] CAL1_NEXT_DQS = 6'h0E;
localparam [5:0] CAL1_DONE = 6'h0F;
localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10;
localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11;
localparam [5:0] CAL1_PB_INC_CPT = 6'h12;
localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13;
localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14;
localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15;
localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16;
localparam [5:0] CAL1_PB_INC_DQ = 6'h17;
localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18;
localparam [5:0] CAL1_PB_DEC_CPT = 6'h19;
localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A;
localparam [5:0] CAL1_REGL_LOAD = 6'h1B;
localparam [5:0] CAL1_RDLVL_ERR = 6'h1C;
localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D;
localparam [5:0] CAL1_VALID_WAIT = 6'h1E;
localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F;
localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20;
integer a;
integer b;
integer d;
integer e;
integer f;
integer h;
integer g;
integer i;
integer j;
integer k;
integer l;
integer m;
integer n;
integer r;
integer p;
integer q;
integer s;
integer t;
integer u;
integer w;
integer ce_i;
integer ce_rnk_i;
integer aa;
integer bb;
integer cc;
integer dd;
genvar x;
genvar z;
reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r;
wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing;
reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r;
reg cal1_dq_idel_ce;
reg cal1_dq_idel_inc;
reg cal1_dlyce_cpt_r;
reg cal1_dlyinc_cpt_r;
reg cal1_dlyce_dq_r;
reg cal1_dlyinc_dq_r;
reg cal1_wait_cnt_en_r;
reg [4:0] cal1_wait_cnt_r;
reg cal1_wait_r;
reg [DQ_WIDTH-1:0] dlyce_dq_r;
reg dlyinc_dq_r;
reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1];
reg cal1_prech_req_r;
reg [5:0] cal1_state_r;
reg [5:0] cal1_state_r1;
reg [5:0] cnt_idel_dec_cpt_r;
reg [3:0] cnt_shift_r;
reg detect_edge_done_r;
reg [5:0] right_edge_taps_r;
reg [5:0] first_edge_taps_r;
reg found_edge_r;
reg found_first_edge_r;
reg found_second_edge_r;
reg found_stable_eye_r;
reg found_stable_eye_last_r;
reg found_edge_all_r;
reg [5:0] tap_cnt_cpt_r;
reg tap_limit_cpt_r;
reg [4:0] idel_tap_cnt_dq_pb_r;
reg idel_tap_limit_dq_pb_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg mux_rd_valid_r;
reg new_cnt_cpt_r;
reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r;
reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r;
reg [DRAM_WIDTH-1:0] pb_found_edge_last_r;
reg [DRAM_WIDTH-1:0] pb_found_edge_r;
reg [DRAM_WIDTH-1:0] pb_found_first_edge_r;
reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r;
reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r;
reg pi_en_stg2_f_timing;
reg pi_stg2_f_incdec_timing;
reg pi_stg2_load_timing;
reg [5:0] pi_stg2_reg_l_timing;
reg [DRAM_WIDTH-1:0] prev_sr_diff_r;
reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg samp_cnt_done_r;
reg samp_edge_cnt0_en_r;
reg [11:0] samp_edge_cnt0_r;
reg samp_edge_cnt1_en_r;
reg [11:0] samp_edge_cnt1_r;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg [5:0] second_edge_taps_r;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg store_sr_r;
reg store_sr_req_pulsed_r;
reg store_sr_req_r;
reg sr_valid_r;
reg sr_valid_r1;
reg sr_valid_r2;
reg [DRAM_WIDTH-1:0] old_sr_diff_r;
reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r;
reg pat0_data_match_r;
reg pat1_data_match_r;
wire pat_data_match_r;
wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0];
reg [DRAM_WIDTH-1:0] pat0_match_fall0_r;
reg pat0_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall1_r;
reg pat0_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall2_r;
reg pat0_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall3_r;
reg pat0_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise0_r;
reg pat0_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise1_r;
reg pat0_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise2_r;
reg pat0_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise3_r;
reg pat0_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg pat1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg pat1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall2_r;
reg pat1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall3_r;
reg pat1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg pat1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg pat1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise2_r;
reg pat1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise3_r;
reg pat1_match_rise3_and_r;
reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];
reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w;
reg [4:0] idelay_tap_cnt_slice_r;
reg idelay_tap_limit_r;
wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0];
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r;
reg idel_pat0_match_rise0_and_r;
reg idel_pat0_match_fall0_and_r;
reg idel_pat0_match_rise1_and_r;
reg idel_pat0_match_fall1_and_r;
reg idel_pat0_match_rise2_and_r;
reg idel_pat0_match_fall2_and_r;
reg idel_pat0_match_rise3_and_r;
reg idel_pat0_match_fall3_and_r;
reg idel_pat1_match_rise0_and_r;
reg idel_pat1_match_fall0_and_r;
reg idel_pat1_match_rise1_and_r;
reg idel_pat1_match_fall1_and_r;
reg idel_pat1_match_rise2_and_r;
reg idel_pat1_match_fall2_and_r;
reg idel_pat1_match_rise3_and_r;
reg idel_pat1_match_fall3_and_r;
reg idel_pat0_data_match_r;
reg idel_pat1_data_match_r;
reg idel_pat_data_match;
reg idel_pat_data_match_r;
reg [4:0] idel_dec_cnt;
reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];
reg [1:0] rnk_cnt_r;
reg rdlvl_rank_done_r;
reg [3:0] done_cnt;
reg [1:0] regl_rank_cnt;
reg [DQS_CNT_WIDTH:0] regl_dqs_cnt;
reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r;
wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing;
reg regl_rank_done_r;
reg rdlvl_stg1_start_r;
reg dqs_po_dec_done_r1;
reg dqs_po_dec_done_r2;
reg fine_dly_dec_done_r1;
reg fine_dly_dec_done_r2;
reg [3:0] wait_cnt_r;
reg [5:0] pi_rdval_cnt;
reg pi_cnt_dec;
reg mpr_valid_r;
reg mpr_valid_r1;
reg mpr_valid_r2;
reg mpr_rd_rise0_prev_r;
reg mpr_rd_fall0_prev_r;
reg mpr_rd_rise1_prev_r;
reg mpr_rd_fall1_prev_r;
reg mpr_rd_rise2_prev_r;
reg mpr_rd_fall2_prev_r;
reg mpr_rd_rise3_prev_r;
reg mpr_rd_fall3_prev_r;
reg mpr_rdlvl_done_r;
reg mpr_rdlvl_done_r1;
reg mpr_rdlvl_done_r2;
reg mpr_rdlvl_start_r;
reg mpr_rank_done_r;
reg [2:0] stable_idel_cnt;
reg inhibit_edge_detect_r;
reg idel_pat_detect_valid_r;
reg idel_mpr_pat_detect_r;
reg mpr_pat_detect_r;
reg mpr_dec_cpt_r;
wire pb_detect_edge_setup;
wire pb_detect_edge;
// Debug
reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_taps;
reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_taps;
reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < RANKS; d = d + 1) begin
for (e = 0; e < DQS_WIDTH; e = e + 1) begin
idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e];
dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e];
end
end
end
assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done);
assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done);
assign dbg_phy_rdlvl[0] = rdlvl_stg1_start;
assign dbg_phy_rdlvl[1] = pat_data_match_r;
assign dbg_phy_rdlvl[2] = mux_rd_valid_r;
assign dbg_phy_rdlvl[3] = idelay_tap_limit_r;
assign dbg_phy_rdlvl[8:4] = 'b0;
assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0];
assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r;
assign dbg_phy_rdlvl[21] = found_first_edge_r;
assign dbg_phy_rdlvl[22] = found_second_edge_r;
assign dbg_phy_rdlvl[23] = found_edge_r;
assign dbg_phy_rdlvl[24] = store_sr_r;
// [40:25] previously used for sr, old_sr shift registers. If connecting
// these signals again, don't forget to parameterize based on RD_SHIFT_LEN
assign dbg_phy_rdlvl[40:25] = 'b0;
assign dbg_phy_rdlvl[41] = sr_valid_r;
assign dbg_phy_rdlvl[42] = found_stable_eye_r;
assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r;
assign dbg_phy_rdlvl[54:49] = first_edge_taps_r;
assign dbg_phy_rdlvl[60:55] = second_edge_taps_r;
assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r;
assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r;
assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r;
assign dbg_phy_rdlvl[67] = found_edge_r;
assign dbg_phy_rdlvl[68] = found_first_edge_r;
assign dbg_phy_rdlvl[73:69] = 'b0;
assign dbg_phy_rdlvl[74] = idel_pat_data_match;
assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r;
assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r;
assign dbg_phy_rdlvl[77] = pat0_data_match_r;
assign dbg_phy_rdlvl[78] = pat1_data_match_r;
assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w;
assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r;
assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r;
assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r;
assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r;
assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r;
assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r;
assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r;
assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r;
//***************************************************************************
// Debug output
//***************************************************************************
// CPT taps
assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps;
assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps;
assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w;
assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w;
// Record first and second edges found during CPT calibration
generate
always @(posedge clk)
if (rst) begin
dbg_cpt_first_edge_taps <= #TCQ 'b0;
dbg_cpt_second_edge_taps <= #TCQ 'b0;
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin
for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk
for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge
if (found_first_edge_r)
dbg_cpt_first_edge_taps[((6*ce_i)+(ce_rnk_i*DQS_WIDTH*6))+:6]
<= #TCQ first_edge_taps_r;
if (found_second_edge_r)
dbg_cpt_second_edge_taps[((6*ce_i)+(ce_rnk_i*DQS_WIDTH*6))+:6]
<= #TCQ second_edge_taps_r;
end
end
end else if (cal1_state_r == CAL1_CALC_IDEL) begin
// Record tap counts of first and second edge edges during
// CPT calibration for each DQS group. If neither edge has
// been found, then those taps will remain 0
if (found_first_edge_r)
dbg_cpt_first_edge_taps[(((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6]
<= #TCQ first_edge_taps_r;
if (found_second_edge_r)
dbg_cpt_second_edge_taps[(((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6]
<= #TCQ second_edge_taps_r;
end
endgenerate
assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r;
assign mpr_rnk_done = mpr_rank_done_r;
assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE")
mpr_rdlvl_done_r : 1'b1;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt_r : cal1_cnt_cpt_r;
assign idelay_ce = cal1_dq_idel_ce;
assign idelay_inc = cal1_dq_idel_inc;
//***************************************************************************
// Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all
// DQs simultaneously
//***************************************************************************
always @(posedge clk) begin
if (rst)
rdlvl_assrt_common <= #TCQ 1'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start &
!rdlvl_stg1_start_r)
rdlvl_assrt_common <= #TCQ 1'b1;
else if (!idel_pat_data_match_r & idel_pat_data_match)
rdlvl_assrt_common <= #TCQ 1'b0;
end
//***************************************************************************
// Data mux to route appropriate bit to calibration logic - i.e. calibration
// is done sequentially, one bit (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else begin: rd_data_div2_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
end
end
endgenerate
//***************************************************************************
// MPR Read Leveling
//***************************************************************************
// storing the previous read data for checking later. Only bit 0 is used
// since MPR contents (01010101) are available generally on DQ[0] per
// JEDEC spec.
always @(posedge clk)begin
if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||
((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin
mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0];
mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0];
mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0];
mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0];
mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0];
mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0];
mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0];
mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0];
end
end
generate
if (nCK_PER_CLK == 4) begin: mpr_4to1
// changed stable count of 2 IDELAY taps at 78 ps resolution
always @(posedge clk) begin
if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) |
//(cal1_state_r == CAL1_DETECT_EDGE) |
(mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) |
(mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) |
(mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) |
(mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) |
(mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))
stable_idel_cnt <= #TCQ 3'd0;
else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) &
((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idel_pat_detect_valid_r))) begin
if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &
(mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &
(mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &
(mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &
(mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) &
(mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) &
(mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) &
(mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) &
(stable_idel_cnt < 3'd2))
stable_idel_cnt <= #TCQ stable_idel_cnt + 1;
end
end
always @(posedge clk) begin
if (rst |
(mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &
mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &
mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r))
inhibit_edge_detect_r <= 1'b1;
// Wait for settling time after idelay tap increment before
// de-asserting inhibit_edge_detect_r
else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &
(~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &
~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &
~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r))
inhibit_edge_detect_r <= 1'b0;
end
//checking for transition from 01010101 to 10101010
always @(posedge clk)begin
if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
inhibit_edge_detect_r)
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 10101010 is not the correct pattern
else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &
mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &
mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) ||
((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)
&& (idel_pat_detect_valid_r)))
//|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 01010101 to 10101010 is the correct transition
else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &
~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &
~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) &
(stable_idel_cnt == 3'd2) &
((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) ||
(mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) ||
(mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) ||
(mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) ||
(mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])))
idel_mpr_pat_detect_r <= #TCQ 1'b1;
end
end else if (nCK_PER_CLK == 2) begin: mpr_2to1
// changed stable count of 2 IDELAY taps at 78 ps resolution
always @(posedge clk) begin
if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
(mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))
stable_idel_cnt <= #TCQ 3'd0;
else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) &
((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idel_pat_detect_valid_r))) begin
if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &
(mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &
(mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &
(mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &
(stable_idel_cnt < 3'd2))
stable_idel_cnt <= #TCQ stable_idel_cnt + 1;
end
end
always @(posedge clk) begin
if (rst |
(mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r))
inhibit_edge_detect_r <= 1'b1;
else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &
(~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r))
inhibit_edge_detect_r <= 1'b0;
end
//checking for transition from 01010101 to 10101010
always @(posedge clk)begin
if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
inhibit_edge_detect_r)
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 1010 is not the correct pattern
else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) ||
((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)
& (idel_pat_detect_valid_r)))
// ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 0101 to 1010 is the correct transition
else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) &
(stable_idel_cnt == 3'd2) &
((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])))
idel_mpr_pat_detect_r <= #TCQ 1'b1;
end
end
endgenerate
// Registered signal indicates when mux_rd_rise/fall_r is valid
always @(posedge clk)
mux_rd_valid_r <= #TCQ ~phy_if_empty;
//***************************************************************************
// Decrement initial Phaser_IN fine delay value before proceeding with
// read calibration
//***************************************************************************
always @(posedge clk) begin
dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done;
dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1;
fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1;
pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2;
end
always @(posedge clk) begin
if (rst || pi_cnt_dec)
wait_cnt_r <= #TCQ 'd8;
else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst) begin
pi_rdval_cnt <= #TCQ 'd0;
end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin
pi_rdval_cnt <= #TCQ pi_counter_read_val;
end else if (pi_rdval_cnt > 'd0) begin
if (pi_cnt_dec)
pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1;
else
pi_rdval_cnt <= #TCQ pi_rdval_cnt;
end else if (pi_rdval_cnt == 'd0) begin
pi_rdval_cnt <= #TCQ pi_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (pi_rdval_cnt == 'd0))
pi_cnt_dec <= #TCQ 1'b0;
else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0)
&& (wait_cnt_r == 'd1))
pi_cnt_dec <= #TCQ 1'b1;
else
pi_cnt_dec <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst) begin
fine_dly_dec_done_r1 <= #TCQ 1'b0;
end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) ||
(dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin
fine_dly_dec_done_r1 <= #TCQ 1'b1;
end
end
//***************************************************************************
// Demultiplexor to control Phaser_IN delay values
//***************************************************************************
// Read DQS
always @(posedge clk) begin
if (rst) begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (pi_cnt_dec) begin
pi_en_stg2_f_timing <= #TCQ 'b1;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (cal1_dlyce_cpt_r) begin
if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
// Change only specified DQS
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
// if simulating, and "shortcuts" for calibration enabled, apply
// results to all DQSs (i.e. assume same delay on all
// DQSs).
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;
end
end else begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;
pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
end
// This counter used to implement settling time between
// Phaser_IN rank register loads to different DQSs
always @(posedge clk) begin
if (rst)
done_cnt <= #TCQ 'b0;
else if (((cal1_state_r == CAL1_REGL_LOAD) &&
(cal1_state_r1 == CAL1_NEXT_DQS)) ||
((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE)))
done_cnt <= #TCQ 4'b1010;
else if (done_cnt > 'b0)
done_cnt <= #TCQ done_cnt - 1;
end
// During rank register loading the rank count must be sent to
// Phaser_IN via the phy_ctl_wd?? If so phy_init will have to
// issue NOPs during rank register loading with the appropriate
// rank count
always @(posedge clk) begin
if (rst || (regl_rank_done_r == 1'b1))
regl_rank_done_r <= #TCQ 1'b0;
else if ((regl_dqs_cnt == DQS_WIDTH-1) &&
(regl_rank_cnt != RANKS-1) &&
(done_cnt == 4'd1))
regl_rank_done_r <= #TCQ 1'b1;
end
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*regl_dqs_cnt.
// replacing this with two left shifts + 1 left shift to avoid
// DSP multiplier.
assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt};
// Load Phaser_OUT rank register with rdlvl delay value
// for each DQS per rank.
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0)) begin
pi_stg2_load_timing <= #TCQ 'b0;
pi_stg2_reg_l_timing <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
pi_stg2_load_timing <= #TCQ 'b1;
pi_stg2_reg_l_timing <= #TCQ
rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt];
end else begin
pi_stg2_load_timing <= #TCQ 'b0;
pi_stg2_reg_l_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_stg2_load <= #TCQ pi_stg2_load_timing;
pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing;
end
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0) ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
regl_rank_cnt <= #TCQ 2'b00;
else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
if (regl_rank_cnt == RANKS-1)
regl_rank_cnt <= #TCQ regl_rank_cnt;
else
regl_rank_cnt <= #TCQ regl_rank_cnt + 1;
end
end
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0) ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
if (regl_rank_cnt == RANKS-1)
regl_dqs_cnt <= #TCQ regl_dqs_cnt;
else
regl_dqs_cnt <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1)
&& (done_cnt == 4'd1))
regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1;
else
regl_dqs_cnt <= #TCQ regl_dqs_cnt;
end
always @(posedge clk)
regl_dqs_cnt_r <= #TCQ regl_dqs_cnt;
//*****************************************************************
// DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC:
// The actual IDELAY elements for each of the DQ bits is set via the
// DLYVAL parallel load port. However, the stage 1 calibration
// algorithm (well most of it) only needs to increment or decrement the DQ
// IDELAY value by 1 at any one time.
//*****************************************************************
// Chip-select generation for each of the individual counters tracking
// IDELAY tap values for each DQ
generate
for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq
always @(posedge clk)
if (rst)
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
else
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skipping calibration altogether (only for simulation), no
// need to set DQ IODELAY values - they are hardcoded
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
else if (SIM_CAL_OPTION == "FAST_CAL") begin
// If fast calibration option (simulation only) selected, DQ
// IODELAYs across all bytes are updated simultaneously
// (although per-bit deskew within DQS[0] is still supported)
for (h = 0; h < DRAM_WIDTH; h = h + 1) begin
dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r;
end
end else if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
if (cal1_cnt_cpt_r == z) begin
for (g = 0; g < DRAM_WIDTH; g = g + 1) begin
dlyce_dq_r[DRAM_WIDTH*z + g]
<= #TCQ cal1_dlyce_dq_r;
end
end else
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
end
end
endgenerate
// Also delay increment/decrement control to match delay on DLYCE
always @(posedge clk)
if (rst)
dlyinc_dq_r <= #TCQ 1'b0;
else
dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r;
// Each DQ has a counter associated with it to record current read-leveling
// delay value
always @(posedge clk)
// Reset or skipping calibration all together
if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin
for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r
for (bb = 0; bb < DQ_WIDTH; bb = bb + 1)
dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0;
end
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk
for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg
if (dlyce_dq_r[r]) begin
if (dlyinc_dq_r)
dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01;
else
dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01;
end
end
end
end else begin
if (dlyce_dq_r[cal1_cnt_cpt_r]) begin
if (dlyinc_dq_r)
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01;
else
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01;
end
end
// Register for timing (help with logic placement)
always @(posedge clk) begin
for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn
for (dd = 0; dd < DQ_WIDTH; dd = dd + 1)
dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd];
end
end
//***************************************************************************
// Generate signal used to delay calibration state machine - used when:
// (1) IDELAY value changed
// (2) RD_MUX_SEL value changed
// Use when a delay is necessary to give the change time to propagate
// through the data pipeline (through IDELAY and ISERDES, and fabric
// pipeline stages)
//***************************************************************************
// List all the stage 1 calibration wait states here.
// verilint STARC-2.7.3.3b off
always @(posedge clk)
if ((cal1_state_r == CAL1_NEW_DQS_WAIT) ||
(cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||
(cal1_state_r == CAL1_NEW_DQS_PREWAIT) ||
(cal1_state_r == CAL1_VALID_WAIT) ||
(cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_INC_CPT_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) ||
(cal1_state_r == CAL1_PB_INC_DQ_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_WAIT) ||
(cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) ||
(cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) ||
(cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) ||
(cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT))
cal1_wait_cnt_en_r <= #TCQ 1'b1;
else
cal1_wait_cnt_en_r <= #TCQ 1'b0;
// verilint STARC-2.7.3.3b on
always @(posedge clk)
if (!cal1_wait_cnt_en_r) begin
cal1_wait_cnt_r <= #TCQ 5'b00000;
cal1_wait_r <= #TCQ 1'b1;
end else begin
if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin
cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1;
cal1_wait_r <= #TCQ 1'b1;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
cal1_wait_cnt_r <= #TCQ 5'b00000;
cal1_wait_r <= #TCQ 1'b0;
end
end
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
rdlvl_prech_req <= #TCQ 1'b0;
else
rdlvl_prech_req <= #TCQ cal1_prech_req_r;
//***************************************************************************
// Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of
// data from ISERDES. The value of this register is also stored, so that
// previous and current values of the ISERDES data can be compared while
// varying the IODELAY taps to see if an "edge" of the data valid window
// has been encountered since the last IODELAY tap adjustment
//***************************************************************************
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end
end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall1_r[rd_i]};
sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise2_r[rd_i]};
sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall2_r[rd_i]};
sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise3_r[rd_i]};
sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall3_r[rd_i]};
end
end
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]};
end
end
end
end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall1_r[rd_i]};
end
end
end
end
end
endgenerate
//***************************************************************************
// Conversion to pattern calibration
//***************************************************************************
// Pattern for DQ IDELAY calibration
//*****************************************************************
// Expected data pattern when DQ shifted to the right such that
// DQS before the left edge of the DVW:
// Based on pattern of ({rise,fall}) =
// 0x1, 0xB, 0x4, 0x4, 0xB, 0x9
// Each nibble will look like:
// bit3: 0, 1, 0, 0, 1, 1
// bit2: 0, 0, 1, 1, 0, 0
// bit1: 0, 1, 0, 0, 1, 0
// bit0: 1, 1, 0, 0, 1, 1
// Or if the write is early it could look like:
// 0x4, 0x4, 0xB, 0x9, 0x6, 0xE
// bit3: 0, 0, 1, 1, 0, 1
// bit2: 1, 1, 0, 0, 1, 1
// bit1: 0, 0, 1, 0, 1, 1
// bit0: 0, 0, 1, 1, 0, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// Pattern for DQ IDELAY increment
// Target pattern for "early write"
assign {idel_pat0_rise0[3], idel_pat0_rise0[2],
idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1;
assign {idel_pat0_fall0[3], idel_pat0_fall0[2],
idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7;
assign {idel_pat0_rise1[3], idel_pat0_rise1[2],
idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE;
assign {idel_pat0_fall1[3], idel_pat0_fall1[2],
idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC;
assign {idel_pat0_rise2[3], idel_pat0_rise2[2],
idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9;
assign {idel_pat0_fall2[3], idel_pat0_fall2[2],
idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2;
assign {idel_pat0_rise3[3], idel_pat0_rise3[2],
idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4;
assign {idel_pat0_fall3[3], idel_pat0_fall3[2],
idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB;
// Target pattern for "on-time write"
assign {idel_pat1_rise0[3], idel_pat1_rise0[2],
idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4;
assign {idel_pat1_fall0[3], idel_pat1_fall0[2],
idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9;
assign {idel_pat1_rise1[3], idel_pat1_rise1[2],
idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3;
assign {idel_pat1_fall1[3], idel_pat1_fall1[2],
idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7;
assign {idel_pat1_rise2[3], idel_pat1_rise2[2],
idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE;
assign {idel_pat1_fall2[3], idel_pat1_fall2[2],
idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC;
assign {idel_pat1_rise3[3], idel_pat1_rise3[2],
idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9;
assign {idel_pat1_fall3[3], idel_pat1_fall3[2],
idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2;
// Correct data valid window for "early write"
assign {pat0_rise0[3], pat0_rise0[2],
pat0_rise0[1], pat0_rise0[0]} = 4'h7;
assign {pat0_fall0[3], pat0_fall0[2],
pat0_fall0[1], pat0_fall0[0]} = 4'hE;
assign {pat0_rise1[3], pat0_rise1[2],
pat0_rise1[1], pat0_rise1[0]} = 4'hC;
assign {pat0_fall1[3], pat0_fall1[2],
pat0_fall1[1], pat0_fall1[0]} = 4'h9;
assign {pat0_rise2[3], pat0_rise2[2],
pat0_rise2[1], pat0_rise2[0]} = 4'h2;
assign {pat0_fall2[3], pat0_fall2[2],
pat0_fall2[1], pat0_fall2[0]} = 4'h4;
assign {pat0_rise3[3], pat0_rise3[2],
pat0_rise3[1], pat0_rise3[0]} = 4'hB;
assign {pat0_fall3[3], pat0_fall3[2],
pat0_fall3[1], pat0_fall3[0]} = 4'h1;
// Correct data valid window for "on-time write"
assign {pat1_rise0[3], pat1_rise0[2],
pat1_rise0[1], pat1_rise0[0]} = 4'h9;
assign {pat1_fall0[3], pat1_fall0[2],
pat1_fall0[1], pat1_fall0[0]} = 4'h3;
assign {pat1_rise1[3], pat1_rise1[2],
pat1_rise1[1], pat1_rise1[0]} = 4'h7;
assign {pat1_fall1[3], pat1_fall1[2],
pat1_fall1[1], pat1_fall1[0]} = 4'hE;
assign {pat1_rise2[3], pat1_rise2[2],
pat1_rise2[1], pat1_rise2[0]} = 4'hC;
assign {pat1_fall2[3], pat1_fall2[2],
pat1_fall2[1], pat1_fall2[0]} = 4'h9;
assign {pat1_rise3[3], pat1_rise3[2],
pat1_rise3[1], pat1_rise3[0]} = 4'h2;
assign {pat1_fall3[3], pat1_fall3[2],
pat1_fall3[1], pat1_fall3[0]} = 4'h4;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// Pattern for DQ IDELAY increment
// Target pattern for "early write"
assign idel_pat0_rise0[3] = 2'b01;
assign idel_pat0_fall0[3] = 2'b00;
assign idel_pat0_rise1[3] = 2'b10;
assign idel_pat0_fall1[3] = 2'b11;
assign idel_pat0_rise0[2] = 2'b00;
assign idel_pat0_fall0[2] = 2'b10;
assign idel_pat0_rise1[2] = 2'b11;
assign idel_pat0_fall1[2] = 2'b10;
assign idel_pat0_rise0[1] = 2'b00;
assign idel_pat0_fall0[1] = 2'b11;
assign idel_pat0_rise1[1] = 2'b10;
assign idel_pat0_fall1[1] = 2'b01;
assign idel_pat0_rise0[0] = 2'b11;
assign idel_pat0_fall0[0] = 2'b10;
assign idel_pat0_rise1[0] = 2'b00;
assign idel_pat0_fall1[0] = 2'b01;
// Target pattern for "on-time write"
assign idel_pat1_rise0[3] = 2'b01;
assign idel_pat1_fall0[3] = 2'b11;
assign idel_pat1_rise1[3] = 2'b01;
assign idel_pat1_fall1[3] = 2'b00;
assign idel_pat1_rise0[2] = 2'b11;
assign idel_pat1_fall0[2] = 2'b01;
assign idel_pat1_rise1[2] = 2'b00;
assign idel_pat1_fall1[2] = 2'b10;
assign idel_pat1_rise0[1] = 2'b01;
assign idel_pat1_fall0[1] = 2'b00;
assign idel_pat1_rise1[1] = 2'b10;
assign idel_pat1_fall1[1] = 2'b11;
assign idel_pat1_rise0[0] = 2'b00;
assign idel_pat1_fall0[0] = 2'b10;
assign idel_pat1_rise1[0] = 2'b11;
assign idel_pat1_fall1[0] = 2'b10;
// Correct data valid window for "early write"
assign pat0_rise0[3] = 2'b00;
assign pat0_fall0[3] = 2'b10;
assign pat0_rise1[3] = 2'b11;
assign pat0_fall1[3] = 2'b10;
assign pat0_rise0[2] = 2'b10;
assign pat0_fall0[2] = 2'b11;
assign pat0_rise1[2] = 2'b10;
assign pat0_fall1[2] = 2'b00;
assign pat0_rise0[1] = 2'b11;
assign pat0_fall0[1] = 2'b10;
assign pat0_rise1[1] = 2'b01;
assign pat0_fall1[1] = 2'b00;
assign pat0_rise0[0] = 2'b10;
assign pat0_fall0[0] = 2'b00;
assign pat0_rise1[0] = 2'b01;
assign pat0_fall1[0] = 2'b11;
// Correct data valid window for "on-time write"
assign pat1_rise0[3] = 2'b11;
assign pat1_fall0[3] = 2'b01;
assign pat1_rise1[3] = 2'b00;
assign pat1_fall1[3] = 2'b10;
assign pat1_rise0[2] = 2'b01;
assign pat1_fall0[2] = 2'b00;
assign pat1_rise1[2] = 2'b10;
assign pat1_fall1[2] = 2'b11;
assign pat1_rise0[1] = 2'b00;
assign pat1_fall0[1] = 2'b10;
assign pat1_rise1[1] = 2'b11;
assign pat1_fall1[1] = 2'b10;
assign pat1_rise0[0] = 2'b10;
assign pat1_fall0[0] = 2'b11;
assign pat1_rise1[0] = 2'b10;
assign pat1_fall1[0] = 2'b00;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
// DQ IDELAY pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4])
idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4])
idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4])
idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4])
idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4])
idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4])
idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4])
idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4])
idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
// DQS DVW pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])
pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])
pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4])
pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4])
pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4])
pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4])
pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4])
pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4])
pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4])
pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4])
pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
// Combine pattern match "subterms" for DQ-IDELAY stage
always @(posedge clk) begin
idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;
idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;
idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;
idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;
idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r;
idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r;
idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r;
idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r;
idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&
idel_pat0_match_fall0_and_r &&
idel_pat0_match_rise1_and_r &&
idel_pat0_match_fall1_and_r &&
idel_pat0_match_rise2_and_r &&
idel_pat0_match_fall2_and_r &&
idel_pat0_match_rise3_and_r &&
idel_pat0_match_fall3_and_r);
end
always @(posedge clk) begin
idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;
idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;
idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;
idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;
idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r;
idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r;
idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r;
idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r;
idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&
idel_pat1_match_fall0_and_r &&
idel_pat1_match_rise1_and_r &&
idel_pat1_match_fall1_and_r &&
idel_pat1_match_rise2_and_r &&
idel_pat1_match_fall2_and_r &&
idel_pat1_match_rise3_and_r &&
idel_pat1_match_fall3_and_r);
end
always @(idel_pat0_data_match_r or idel_pat1_data_match_r)
idel_pat_data_match <= #TCQ idel_pat0_data_match_r |
idel_pat1_data_match_r;
always @(posedge clk)
idel_pat_data_match_r <= #TCQ idel_pat_data_match;
// Combine pattern match "subterms" for DQS-PHASER_IN stage
always @(posedge clk) begin
pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r;
pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r;
pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r;
pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r;
pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_fall0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_fall1_and_r &&
pat0_match_rise2_and_r &&
pat0_match_fall2_and_r &&
pat0_match_rise3_and_r &&
pat0_match_fall3_and_r);
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r;
pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r;
pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r;
pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r &&
pat1_match_rise2_and_r &&
pat1_match_fall2_and_r &&
pat1_match_rise3_and_r &&
pat1_match_fall3_and_r);
end
assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
// DQ IDELAY pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// DQS DVW pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])
pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])
pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
// Combine pattern match "subterms" for DQ-IDELAY stage
always @(posedge clk) begin
idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;
idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;
idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;
idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;
idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&
idel_pat0_match_fall0_and_r &&
idel_pat0_match_rise1_and_r &&
idel_pat0_match_fall1_and_r);
end
always @(posedge clk) begin
idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;
idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;
idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;
idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;
idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&
idel_pat1_match_fall0_and_r &&
idel_pat1_match_rise1_and_r &&
idel_pat1_match_fall1_and_r);
end
always @(posedge clk) begin
if (sr_valid_r2)
idel_pat_data_match <= #TCQ idel_pat0_data_match_r |
idel_pat1_data_match_r;
end
//assign idel_pat_data_match = idel_pat0_data_match_r |
// idel_pat1_data_match_r;
always @(posedge clk)
idel_pat_data_match_r <= #TCQ idel_pat_data_match;
// Combine pattern match "subterms" for DQS-PHASER_IN stage
always @(posedge clk) begin
pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_fall0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_fall1_and_r);
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
end
assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;
end
endgenerate
always @(posedge clk) begin
rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start;
mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r;
mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1;
mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start;
end
//***************************************************************************
// First stage calibration: Capture clock
//***************************************************************************
//*****************************************************************
// Keep track of how many samples have been written to shift registers
// Every time RD_SHIFT_LEN samples have been written, then we have a
// full read training pattern loaded into the sr_* registers. Then assert
// sr_valid_r to indicate that: (1) comparison between the sr_* and
// old_sr_* and prev_sr_* registers can take place, (2) transfer of
// the contents of sr_* to old_sr_* and prev_sr_* registers can also
// take place
//*****************************************************************
// verilint STARC-2.2.3.3 off
always @(posedge clk)
if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin
cnt_shift_r <= #TCQ 'b1;
sr_valid_r <= #TCQ 1'b0;
mpr_valid_r <= #TCQ 1'b0;
end else begin
if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin
if (cnt_shift_r == 'b0)
mpr_valid_r <= #TCQ 1'b1;
else begin
mpr_valid_r <= #TCQ 1'b0;
cnt_shift_r <= #TCQ cnt_shift_r + 1;
end
end else
mpr_valid_r <= #TCQ 1'b0;
if (mux_rd_valid_r && rdlvl_stg1_start) begin
if (cnt_shift_r == RD_SHIFT_LEN-1) begin
sr_valid_r <= #TCQ 1'b1;
cnt_shift_r <= #TCQ 'b0;
end else begin
sr_valid_r <= #TCQ 1'b0;
cnt_shift_r <= #TCQ cnt_shift_r + 1;
end
end else
// When the current mux_rd_* contents are not valid, then
// retain the current value of cnt_shift_r, and make sure
// that sr_valid_r = 0 to prevent any downstream loads or
// comparisons
sr_valid_r <= #TCQ 1'b0;
end
// verilint STARC-2.2.3.3 on
//*****************************************************************
// Logic to determine when either edge of the data eye encountered
// Pre- and post-IDELAY update data pattern is compared, if they
// differ, than an edge has been encountered. Currently no attempt
// made to determine if the data pattern itself is "correct", only
// whether it changes after incrementing the IDELAY (possible
// future enhancement)
//*****************************************************************
// One-way control for ensuring that state machine request to store
// current read data into OLD SR shift register only occurs on a
// valid clock cycle. The FSM provides a one-cycle request pulse.
// It is the responsibility of the FSM to wait the worst-case time
// before relying on any downstream results of this load.
always @(posedge clk)
if (rst)
store_sr_r <= #TCQ 1'b0;
else begin
if (store_sr_req_r)
store_sr_r <= #TCQ 1'b1;
else if ((sr_valid_r || mpr_valid_r) && store_sr_r)
store_sr_r <= #TCQ 1'b0;
end
// Transfer current data to old data, prior to incrementing delay
// Also store data from current sampling window - so that we can detect
// if the current delay tap yields data that is "jittery"
generate
if (nCK_PER_CLK == 4) begin: gen_old_sr_div4
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
always @(posedge clk) begin
if (sr_valid_r || mpr_valid_r) begin
// Load last sample (i.e. from current sampling interval)
prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
end
if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin
old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
end
end
end
end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
always @(posedge clk) begin
if (sr_valid_r || mpr_valid_r) begin
prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
end
if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin
old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
end
end
end
end
endgenerate
//*******************************************************
// Match determination occurs over 3 cycles - pipelined for better timing
//*******************************************************
// Match valid with # of cycles of pipelining in match determination
always @(posedge clk) begin
sr_valid_r1 <= #TCQ sr_valid_r;
sr_valid_r2 <= #TCQ sr_valid_r1;
mpr_valid_r1 <= #TCQ mpr_valid_r;
mpr_valid_r2 <= #TCQ mpr_valid_r1;
end
generate
if (nCK_PER_CLK == 4) begin: gen_sr_match_div4
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
always @(posedge clk) begin
// CYCLE1: Compare all bits in DQS grp, generate separate term for
// each bit over four bit times. For example, if there are 8-bits
// per DQS group, 32 terms are generated on cycle 1
// NOTE: Structure HDL such that X on data bus will result in a
// mismatch. This is required for memory models that can drive the
// bus with X's to model uncertainty regions (e.g. Denali)
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))
old_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];
else
old_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))
old_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];
else
old_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))
old_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];
else
old_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))
old_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];
else
old_sr_match_fall1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z]))
old_sr_match_rise2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z];
else
old_sr_match_rise2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z]))
old_sr_match_fall2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z];
else
old_sr_match_fall2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z]))
old_sr_match_rise3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z];
else
old_sr_match_rise3_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z]))
old_sr_match_fall3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z];
else
old_sr_match_fall3_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))
prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];
else
prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))
prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];
else
prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))
prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];
else
prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))
prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];
else
prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z]))
prev_sr_match_rise2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z];
else
prev_sr_match_rise2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z]))
prev_sr_match_fall2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z];
else
prev_sr_match_fall2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z]))
prev_sr_match_rise3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z];
else
prev_sr_match_rise3_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z]))
prev_sr_match_fall3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z];
else
prev_sr_match_fall3_r[z] <= #TCQ 1'b0;
// CYCLE2: Combine all the comparisons for every 8 words (rise0,
// fall0,rise1, fall1) in the calibration sequence. Now we're down
// to DRAM_WIDTH terms
old_sr_match_cyc2_r[z] <= #TCQ
old_sr_match_rise0_r[z] &
old_sr_match_fall0_r[z] &
old_sr_match_rise1_r[z] &
old_sr_match_fall1_r[z] &
old_sr_match_rise2_r[z] &
old_sr_match_fall2_r[z] &
old_sr_match_rise3_r[z] &
old_sr_match_fall3_r[z];
prev_sr_match_cyc2_r[z] <= #TCQ
prev_sr_match_rise0_r[z] &
prev_sr_match_fall0_r[z] &
prev_sr_match_rise1_r[z] &
prev_sr_match_fall1_r[z] &
prev_sr_match_rise2_r[z] &
prev_sr_match_fall2_r[z] &
prev_sr_match_rise3_r[z] &
prev_sr_match_fall3_r[z];
// CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
// and qualify with pipelined valid signal) - probably don't need
// a cycle just do do this....
if (sr_valid_r2 || mpr_valid_r2) begin
old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];
prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
end else begin
old_sr_diff_r[z] <= #TCQ 'b0;
prev_sr_diff_r[z] <= #TCQ 'b0;
end
end
end
end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
always @(posedge clk) begin
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))
old_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];
else
old_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))
old_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];
else
old_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))
old_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];
else
old_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))
old_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];
else
old_sr_match_fall1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))
prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];
else
prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))
prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];
else
prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))
prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];
else
prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))
prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];
else
prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
old_sr_match_cyc2_r[z] <= #TCQ
old_sr_match_rise0_r[z] &
old_sr_match_fall0_r[z] &
old_sr_match_rise1_r[z] &
old_sr_match_fall1_r[z];
prev_sr_match_cyc2_r[z] <= #TCQ
prev_sr_match_rise0_r[z] &
prev_sr_match_fall0_r[z] &
prev_sr_match_rise1_r[z] &
prev_sr_match_fall1_r[z];
// CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
// and qualify with pipelined valid signal) - probably don't need
// a cycle just do do this....
if (sr_valid_r2 || mpr_valid_r2) begin
old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];
prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
end else begin
old_sr_diff_r[z] <= #TCQ 'b0;
prev_sr_diff_r[z] <= #TCQ 'b0;
end
end
end
end
endgenerate
//***************************************************************************
// First stage calibration: DQS Capture
//***************************************************************************
//*******************************************************
// Counters for tracking # of samples compared
// For each comparision point (i.e. to determine if an edge has
// occurred after each IODELAY increment when read leveling),
// multiple samples are compared in order to average out the effects
// of jitter. If any one of these samples is different than the "old"
// sample corresponding to the previous IODELAY value, then an edge
// is declared to be detected.
//*******************************************************
// Two cascaded counters are used to keep track of # of samples compared,
// in order to make it easier to meeting timing on these paths. Once
// optimal sampling interval is determined, it may be possible to remove
// the second counter
always @(posedge clk)
samp_edge_cnt0_en_r <= #TCQ
(cal1_state_r == CAL1_PAT_DETECT) ||
(cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
// First counter counts # of samples compared
always @(posedge clk)
if (rst)
samp_edge_cnt0_r <= #TCQ 'b0;
else begin
if (!samp_edge_cnt0_en_r)
// Reset sample counter when not in any of the "sampling" states
samp_edge_cnt0_r <= #TCQ 'b0;
else if (sr_valid_r2 || mpr_valid_r2)
// Otherwise, count # of samples compared
samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1;
end
// Counter #2 enable generation
always @(posedge clk)
if (rst)
samp_edge_cnt1_en_r <= #TCQ 1'b0;
else begin
// Assert pulse when correct number of samples compared
if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) &&
(sr_valid_r2 || mpr_valid_r2))
samp_edge_cnt1_en_r <= #TCQ 1'b1;
else
samp_edge_cnt1_en_r <= #TCQ 1'b0;
end
// Counter #2
always @(posedge clk)
if (rst)
samp_edge_cnt1_r <= #TCQ 'b0;
else
if (!samp_edge_cnt0_en_r)
samp_edge_cnt1_r <= #TCQ 'b0;
else if (samp_edge_cnt1_en_r)
samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1;
always @(posedge clk)
if (rst)
samp_cnt_done_r <= #TCQ 1'b0;
else begin
if (!samp_edge_cnt0_en_r)
samp_cnt_done_r <= #TCQ 'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
if (samp_edge_cnt0_r == SR_VALID_DELAY-1)
// For simulation only, stay in edge detection mode a minimum
// amount of time - just enough for two data compares to finish
samp_cnt_done_r <= #TCQ 1'b1;
end else begin
if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1)
samp_cnt_done_r <= #TCQ 1'b1;
end
end
//*****************************************************************
// Logic to keep track of (on per-bit basis):
// 1. When a region of stability preceded by a known edge occurs
// 2. If for the current tap, the read data jitters
// 3. If an edge occured between the current and previous tap
// 4. When the current edge detection/sampling interval can end
// Essentially, these are a series of status bits - the stage 1
// calibration FSM monitors these to determine when an edge is
// found. Additional information is provided to help the FSM
// determine if a left or right edge has been found.
//****************************************************************
assign pb_detect_edge_setup
= (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT);
assign pb_detect_edge
= (cal1_state_r == CAL1_PAT_DETECT) ||
(cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
generate
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge
always @(posedge clk) begin
if (pb_detect_edge_setup) begin
// Reset eye size, stable eye marker, and jitter marker before
// starting new edge detection iteration
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_detect_edge_done_r[z] <= #TCQ 1'b0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_last_tap_jitter_r[z] <= #TCQ 1'b0;
pb_found_edge_last_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b0;
pb_found_first_edge_r[z] <= #TCQ 1'b0;
end else if (pb_detect_edge) begin
// Save information on which DQ bits are already out of the
// data valid window - those DQ bits will later not have their
// IDELAY tap value incremented
pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z];
if (!pb_detect_edge_done_r[z]) begin
if (samp_cnt_done_r) begin
// If we've reached end of sampling interval, no jitter on
// current tap has been found (although an edge could have
// been found between the current and previous taps), and
// the sampling interval is complete. Increment the stable
// eye counter if no edge found, and always clear the jitter
// flag in preparation for the next tap.
pb_last_tap_jitter_r[z] <= #TCQ 1'b0;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin
// If the data was completely stable during this tap and
// no edge was found between this and the previous tap
// then increment the stable eye counter "as appropriate"
if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1)
pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1;
else //if (pb_found_first_edge_r[z])
// We've reached minimum stable eye width
pb_found_stable_eye_r[z] <= #TCQ 1'b1;
end else begin
// Otherwise, an edge was found, either because of a
// difference between this and the previous tap's read
// data, and/or because the previous tap's data jittered
// (but not the current tap's data), then just set the
// edge found flag, and enable the stable eye counter
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
end
end else if (prev_sr_diff_r[z]) begin
// If we find that the current tap read data jitters, then
// set edge and jitter found flags, "enable" the eye size
// counter, and stop sampling interval for this bit
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_last_tap_jitter_r[z] <= #TCQ 1'b1;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_found_first_edge_r[z] <= #TCQ 1'b1;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin
// If either an edge was found (i.e. difference between
// current tap and previous tap read data), or the previous
// tap exhibited jitter (which means by definition that the
// current tap cannot match the previous tap because the
// previous tap gave unstable data), then set the edge found
// flag, and "enable" eye size counter. But do not stop
// sampling interval - we still need to check if the current
// tap exhibits jitter
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_found_first_edge_r[z] <= #TCQ 1'b1;
end
end
end else begin
// Before every edge detection interval, reset "intra-tap" flags
pb_found_edge_r[z] <= #TCQ 1'b0;
pb_detect_edge_done_r[z] <= #TCQ 1'b0;
end
end
end
endgenerate
// Combine the above per-bit status flags into combined terms when
// performing deskew on the aggregate data window
always @(posedge clk) begin
detect_edge_done_r <= #TCQ &pb_detect_edge_done_r;
found_edge_r <= #TCQ |pb_found_edge_r;
found_edge_all_r <= #TCQ &pb_found_edge_r;
found_stable_eye_r <= #TCQ &pb_found_stable_eye_r;
end
// last IODELAY "stable eye" indicator is updated only after
// detect_edge_done_r is asserted - so that when we do find the "right edge"
// of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1
// when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates
// immediately, then it never possible to have found_stable_eye_r = 1
// when we detect an edge - and we'll never know whether we've found
// a "right edge")
always @(posedge clk)
if (pb_detect_edge_setup)
found_stable_eye_last_r <= #TCQ 1'b0;
else if (detect_edge_done_r)
found_stable_eye_last_r <= #TCQ found_stable_eye_r;
//*****************************************************************
// Keep track of DQ IDELAYE2 taps used
//*****************************************************************
// Added additional register stage to improve timing
always @(posedge clk)
if (rst)
idelay_tap_cnt_slice_r <= 5'h0;
else
idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];
always @(posedge clk)
if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r
for (s = 0; s < RANKS; s = s + 1) begin
for (t = 0; t < DQS_WIDTH; t = t + 1) begin
idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val;
end
end
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
for (u = 0; u < RANKS; u = u + 1) begin
for (w = 0; w < DQS_WIDTH; w = w + 1) begin
if (cal1_dq_idel_ce) begin
if (cal1_dq_idel_inc)
idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1;
else
idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1;
end
end
end
end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) &&
rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin
for (f = 0; f < DQS_WIDTH; f = f + 1) begin
idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f];
end
end else if (cal1_dq_idel_ce) begin
if (cal1_dq_idel_inc)
idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1;
else
idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1;
end else if (idelay_ld)
idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000;
always @(posedge clk)
if (rst || new_cnt_cpt_r)
idelay_tap_limit_r <= #TCQ 1'b0;
else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31)
idelay_tap_limit_r <= #TCQ 1'b1;
//*****************************************************************
// keep track of edge tap counts found, and current capture clock
// tap count
//*****************************************************************
always @(posedge clk)
if (rst || new_cnt_cpt_r ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
tap_cnt_cpt_r <= #TCQ 'b0;
else if (cal1_dlyce_cpt_r) begin
if (cal1_dlyinc_cpt_r)
tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1;
else if (tap_cnt_cpt_r != 'd0)
tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1;
end
always @(posedge clk)
if (rst || new_cnt_cpt_r ||
(cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
tap_limit_cpt_r <= #TCQ 1'b0;
else if (tap_cnt_cpt_r == 6'd63)
tap_limit_cpt_r <= #TCQ 1'b1;
always @(posedge clk)
cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r;
assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r};
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop
for (b = 0; b < DQS_WIDTH; b = b + 1)
rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0;
end
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin
for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt
rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r;
end
end
end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt
for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt
rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31;
end
end
end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin
rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r;
end
end
// Counter to track maximum DQ IODELAY tap usage during the per-bit
// deskew portion of stage 1 calibration
always @(posedge clk)
if (rst) begin
idel_tap_cnt_dq_pb_r <= #TCQ 'b0;
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end else
if (new_cnt_cpt_r) begin
idel_tap_cnt_dq_pb_r <= #TCQ 'b0;
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end else if (|cal1_dlyce_dq_r) begin
if (cal1_dlyinc_dq_r)
idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1;
else
idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1;
if (idel_tap_cnt_dq_pb_r == 31)
idel_tap_limit_dq_pb_r <= #TCQ 1'b1;
else
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end
//*****************************************************************
always @(posedge clk)
cal1_state_r1 <= #TCQ cal1_state_r;
always @(posedge clk)
if (rst) begin
cal1_cnt_cpt_r <= #TCQ 'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx;
found_first_edge_r <= #TCQ 1'b0;
found_second_edge_r <= #TCQ 1'b0;
right_edge_taps_r <= #TCQ 6'bxxxxxx;
first_edge_taps_r <= #TCQ 6'bxxxxxx;
new_cnt_cpt_r <= #TCQ 1'b0;
rdlvl_stg1_done <= #TCQ 1'b0;
rdlvl_stg1_err <= #TCQ 1'b0;
second_edge_taps_r <= #TCQ 6'bxxxxxx;
store_sr_req_pulsed_r <= #TCQ 1'b0;
store_sr_req_r <= #TCQ 1'b0;
rnk_cnt_r <= #TCQ 2'b00;
rdlvl_rank_done_r <= #TCQ 1'b0;
idel_dec_cnt <= #TCQ 'd0;
rdlvl_last_byte_done <= #TCQ 1'b0;
idel_pat_detect_valid_r <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
if (OCAL_EN == "ON")
mpr_rdlvl_done_r <= #TCQ 1'b0;
else
mpr_rdlvl_done_r <= #TCQ 1'b1;
mpr_dec_cpt_r <= #TCQ 1'b0;
end else begin
// default (inactive) states for all "pulse" outputs
// verilint STARC-2.2.3.3 off
cal1_prech_req_r <= #TCQ 1'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
new_cnt_cpt_r <= #TCQ 1'b0;
store_sr_req_pulsed_r <= #TCQ 1'b0;
store_sr_req_r <= #TCQ 1'b0;
case (cal1_state_r)
CAL1_IDLE: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
rdlvl_last_byte_done <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin
cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT;
end else
if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin
if (SIM_CAL_OPTION == "SKIP_CAL")
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
else if (SIM_CAL_OPTION == "FAST_CAL")
cal1_state_r <= #TCQ CAL1_NEXT_DQS;
else begin
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end
end
CAL1_MPR_NEW_DQS_WAIT: begin
cal1_prech_req_r <= #TCQ 1'b0;
if (!cal1_wait_r && mpr_valid_r)
cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
end
// Wait for the new DQS group to change
// also gives time for the read data IN_FIFO to
// output the updated data for the new DQS group
CAL1_NEW_DQS_WAIT: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
rdlvl_last_byte_done <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
if (|pi_counter_read_val) begin //VK_REVIEW
mpr_dec_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val;
end else if (!cal1_wait_r) begin
//if (!cal1_wait_r) begin
// Store "previous tap" read data. Technically there is no
// "previous" read data, since we are starting a new DQS
// group, so we'll never find an edge at tap 0 unless the
// data is fluctuating/jittering
store_sr_req_r <= #TCQ 1'b1;
// If per-bit deskew is disabled, then skip the first
// portion of stage 1 calibration
if (PER_BIT_DESKEW == "OFF")
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
else if (PER_BIT_DESKEW == "ON")
cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT;
end
end
//*****************************************************************
// Per-bit deskew states
//*****************************************************************
// Wait state following storage of initial read data
CAL1_PB_STORE_FIRST_WAIT:
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
// Look for an edge on all DQ bits in current DQS group
CAL1_PB_DETECT_EDGE:
if (detect_edge_done_r) begin
if (found_stable_eye_r) begin
// If we've found the left edge for all bits (or more precisely,
// we've found the left edge, and then part of the stable
// window thereafter), then proceed to positioning the CPT clock
// right before the left margin
cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT;
end else begin
// If we've reached the end of the sampling time, and haven't
// yet found the left margin of all the DQ bits, then:
if (!tap_limit_cpt_r) begin
// If we still have taps left to use, then store current value
// of read data, increment the capture clock, and continue to
// look for (left) edges
store_sr_req_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_PB_INC_CPT;
end else begin
// If we ran out of taps moving the capture clock, and we
// haven't finished edge detection, then reset the capture
// clock taps to 0 (gradually, one tap at a time...
// then exit the per-bit portion of the algorithm -
// i.e. proceed to adjust the capture clock and DQ IODELAYs as
cnt_idel_dec_cpt_r <= #TCQ 6'd63;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
end
end
end
// Increment delay for DQS
CAL1_PB_INC_CPT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT;
end
// Wait for IODELAY for both capture and internal nodes within
// ISERDES to settle, before checking again for an edge
CAL1_PB_INC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
end
// We've found the left edges of the windows for all DQ bits
// (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture
// clock IDELAY to position just outside left edge of data window
CAL1_PB_DEC_CPT_LEFT:
if (cnt_idel_dec_cpt_r == 6'b000000)
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT;
else begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
end
CAL1_PB_DEC_CPT_LEFT_WAIT:
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
// If there is skew between individual DQ bits, then after we've
// positioned the CPT clock, we will be "in the window" for some
// DQ bits ("early" DQ bits), and "out of the window" for others
// ("late" DQ bits). Increase DQ taps until we are out of the
// window for all DQ bits
CAL1_PB_DETECT_EDGE_DQ:
if (detect_edge_done_r)
if (found_edge_all_r) begin
// We're out of the window for all DQ bits in this DQS group
// We're done with per-bit deskew for this group - now decr
// capture clock IODELAY tap count back to 0, and proceed
// with the rest of stage 1 calibration for this DQS group
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
end else
if (!idel_tap_limit_dq_pb_r)
// If we still have DQ taps available for deskew, keep
// incrementing IODELAY tap count for the appropriate DQ bits
cal1_state_r <= #TCQ CAL1_PB_INC_DQ;
else begin
// Otherwise, stop immediately (we've done the best we can)
// and proceed with rest of stage 1 calibration
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
end
CAL1_PB_INC_DQ: begin
// Increment only those DQ for which an edge hasn't been found yet
cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r;
cal1_dlyinc_dq_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT;
end
CAL1_PB_INC_DQ_WAIT:
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
// Decrement capture clock taps back to initial value
CAL1_PB_DEC_CPT:
if (cnt_idel_dec_cpt_r == 6'b000000)
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT;
else begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
end
// Wait for capture clock to settle, then proceed to rest of
// state 1 calibration for this DQS group
CAL1_PB_DEC_CPT_WAIT:
if (!cal1_wait_r) begin
store_sr_req_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
end
// When first starting calibration for a DQS group, save the
// current value of the read data shift register, and use this
// as a reference. Note that for the first iteration of the
// edge detection loop, we will in effect be checking for an edge
// at IODELAY taps = 0 - normally, we are comparing the read data
// for IODELAY taps = N, with the read data for IODELAY taps = N-1
// An edge can only be found at IODELAY taps = 0 if the read data
// is changing during this time (possible due to jitter)
CAL1_STORE_FIRST_WAIT: begin
mpr_dec_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PAT_DETECT;
end
CAL1_VALID_WAIT: begin
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
end
CAL1_MPR_PAT_DETECT: begin
// MPR read leveling for centering DQS in valid window before
// OCLKDELAYED calibration begins in order to eliminate read issues
if (idel_pat_detect_valid_r == 1'b0) begin
cal1_state_r <= #TCQ CAL1_VALID_WAIT;
idel_pat_detect_valid_r <= #TCQ 1'b1;
end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
idel_dec_cnt <= #TCQ 'd0;
end else if (!idelay_tap_limit_r)
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC;
else
cal1_state_r <= #TCQ CAL1_RDLVL_ERR;
end
CAL1_PAT_DETECT: begin
// All DQ bits associated with a DQS are pushed to the right one IDELAY
// tap at a time until first rising DQS is in the tri-state region
// before first rising edge window.
// The detect_edge_done_r condition included to support averaging
// during IDELAY tap increments
if (detect_edge_done_r) begin
if (idel_pat_data_match) begin
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
idel_dec_cnt <= #TCQ 'd0;
end else if (!idelay_tap_limit_r) begin
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC;
end else begin
cal1_state_r <= #TCQ CAL1_RDLVL_ERR;
end
end
end
// Increment IDELAY tap by 1 for DQ bits in the byte being calibrated
// until left edge of valid window detected
CAL1_DQ_IDEL_TAP_INC: begin
cal1_dq_idel_ce <= #TCQ 1'b1;
cal1_dq_idel_inc <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT;
idel_pat_detect_valid_r <= #TCQ 1'b0;
end
CAL1_DQ_IDEL_TAP_INC_WAIT: begin
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
if (!cal1_wait_r) begin
if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))
cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
else
cal1_state_r <= #TCQ CAL1_PAT_DETECT;
end
end
// Decrement by 2 IDELAY taps once idel_pat_data_match detected
CAL1_DQ_IDEL_TAP_DEC: begin
cal1_dq_idel_inc <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT;
if (idel_dec_cnt >= 'd0)
cal1_dq_idel_ce <= #TCQ 1'b1;
else
cal1_dq_idel_ce <= #TCQ 1'b0;
if (idel_dec_cnt > 'd0)
idel_dec_cnt <= #TCQ idel_dec_cnt - 1;
else
idel_dec_cnt <= #TCQ idel_dec_cnt;
end
CAL1_DQ_IDEL_TAP_DEC_WAIT: begin
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
if (!cal1_wait_r) begin
if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0))
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;
else if (mpr_dec_cpt_r)
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
else
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
end
end
// Check for presence of data eye edge. During this state, we
// sample the read data multiple times, and look for changes
// in the read data, specifically:
// 1. A change in the read data compared with the value of
// read data from the previous delay tap. This indicates
// that the most recent tap delay increment has moved us
// into either a new window, or moved/kept us in the
// transition/jitter region between windows. Note that this
// condition only needs to be checked for once, and for
// logistical purposes, we check this soon after entering
// this state (see comment in CAL1_DETECT_EDGE below for
// why this is done)
// 2. A change in the read data while we are in this state
// (i.e. in the absence of a tap delay increment). This
// indicates that we're close enough to a window edge that
// jitter will cause the read data to change even in the
// absence of a tap delay change
CAL1_DETECT_EDGE: begin
// Essentially wait for the first comparision to finish, then
// store current data into "old" data register. This store
// happens now, rather than later (e.g. when we've have already
// left this state) in order to avoid the situation the data that
// is stored as "old" data has not been used in an "active
// comparison" - i.e. data is stored after the last comparison
// of this state. In this case, we can miss an edge if the
// following sequence occurs:
// 1. Comparison completes in this state - no edge found
// 2. "Momentary jitter" occurs which "pushes" the data out the
// equivalent of one delay tap
// 3. We store this jittered data as the "old" data
// 4. "Jitter" no longer present
// 5. We increment the delay tap by one
// 6. Now we compare the current with the "old" data - they're
// the same, and no edge is detected
// NOTE: Given the large # of comparisons done in this state, it's
// highly unlikely the above sequence will occur in actual H/W
// Wait for the first load of read data into the comparison
// shift register to finish, then load the current read data
// into the "old" data register. This allows us to do one
// initial comparision between the current read data, and
// stored data corresponding to the previous delay tap
idel_pat_detect_valid_r <= #TCQ 1'b0;
if (!store_sr_req_pulsed_r) begin
// Pulse store_sr_req_r only once in this state
store_sr_req_r <= #TCQ 1'b1;
store_sr_req_pulsed_r <= #TCQ 1'b1;
end else begin
store_sr_req_r <= #TCQ 1'b0;
store_sr_req_pulsed_r <= #TCQ 1'b1;
end
// Continue to sample read data and look for edges until the
// appropriate time interval (shorter for simulation-only,
// much, much longer for actual h/w) has elapsed
if (detect_edge_done_r) begin
if (tap_limit_cpt_r)
// Only one edge detected and ran out of taps since only one
// bit time worth of taps available for window detection. This
// can happen if at tap 0 DQS is in previous window which results
// in only left edge being detected. Or at tap 0 DQS is in the
// current window resulting in only right edge being detected.
// Depending on the frequency this case can also happen if at
// tap 0 DQS is in the left noise region resulting in only left
// edge being detected.
cal1_state_r <= #TCQ CAL1_CALC_IDEL;
else if (found_edge_r) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
found_first_edge_r <= #TCQ 1'b1;
// Only the right edge of the data valid window is found
// Record the inner right edge tap value
if (!found_first_edge_r && found_stable_eye_last_r) begin
if (tap_cnt_cpt_r == 'd0)
right_edge_taps_r <= #TCQ 'd0;
else
right_edge_taps_r <= #TCQ tap_cnt_cpt_r;
end
// Both edges of data valid window found:
// If we've found a second edge after a region of stability
// then we must have just passed the second ("right" edge of
// the window. Record this second_edge_taps = current tap-1,
// because we're one past the actual second edge tap, where
// the edge taps represent the extremes of the data valid
// window (i.e. smallest & largest taps where data still valid
if (found_first_edge_r && found_stable_eye_last_r) begin
found_second_edge_r <= #TCQ 1'b1;
second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1;
cal1_state_r <= #TCQ CAL1_CALC_IDEL;
end else begin
// Otherwise, an edge was found (just not the "second" edge)
// Assuming DQS is in the correct window at tap 0 of Phaser IN
// fine tap. The first edge found is the right edge of the valid
// window and is the beginning of the jitter region hence done!
first_edge_taps_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT;
end
end else
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT;
end
end
// Increment Phaser_IN delay for DQS
CAL1_IDEL_INC_CPT: begin
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT;
if (~tap_limit_cpt_r) begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b1;
end else begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_IDEL_INC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
end
// Calculate final value of Phaser_IN taps. At this point, one or both
// edges of data eye have been found, and/or all taps have been
// exhausted looking for the edges
// NOTE: We're calculating the amount to decrement by, not the
// absolute setting for DQS.
CAL1_CALC_IDEL: begin
// CASE1: If 2 edges found.
if (found_second_edge_r)
cnt_idel_dec_cpt_r
<= #TCQ ((second_edge_taps_r -
first_edge_taps_r)>>1) + 1;
else if (right_edge_taps_r > 6'd0)
// Only right edge detected
// right_edge_taps_r is the inner right edge tap value
// hence used for calculation
cnt_idel_dec_cpt_r
<= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1));
else if (found_first_edge_r)
// Only left edge detected
cnt_idel_dec_cpt_r
<= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1);
else
cnt_idel_dec_cpt_r
<= #TCQ (tap_cnt_cpt_r>>1);
// Now use the value we just calculated to decrement CPT taps
// to the desired calibration point
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
end
// decrement capture clock for final adjustment - center
// capture clock in middle of data eye. This adjustment will occur
// only when both the edges are found usign CPT taps. Must do this
// incrementally to avoid clock glitching (since CPT drives clock
// divider within each ISERDES)
CAL1_IDEL_DEC_CPT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
if (cnt_idel_dec_cpt_r == 6'b000001) begin
if (mpr_dec_cpt_r) begin
if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin
idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;
end else
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
end else
cal1_state_r <= #TCQ CAL1_NEXT_DQS;
end else
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT;
end
CAL1_IDEL_DEC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
end
// Determine whether we're done, or have more DQS's to calibrate
// Also request precharge after every byte, as appropriate
CAL1_NEXT_DQS: begin
//if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2"))
cal1_prech_req_r <= #TCQ 1'b1;
//else
// cal1_prech_req_r <= #TCQ 1'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// Prepare for another iteration with next DQS group
found_first_edge_r <= #TCQ 1'b0;
found_second_edge_r <= #TCQ 1'b0;
first_edge_taps_r <= #TCQ 'd0;
second_edge_taps_r <= #TCQ 'd0;
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin
if (mpr_rdlvl_done_r) begin
rdlvl_last_byte_done <= #TCQ 1'b1;
mpr_last_byte_done <= #TCQ 1'b0;
end else begin
rdlvl_last_byte_done <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b1;
end
end
// Wait until precharge that occurs in between calibration of
// DQS groups is finished
if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
//rdlvl_rank_done_r <= #TCQ 1'b1;
rdlvl_last_byte_done <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD;
end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin
if (~mpr_rdlvl_done_r) begin
mpr_rank_done_r <= #TCQ 1'b1;
// if (rnk_cnt_r == RANKS-1) begin
// All DQS groups in all ranks done
cal1_state_r <= #TCQ CAL1_DONE;
cal1_cnt_cpt_r <= #TCQ 'b0;
// end else begin
// // Process DQS groups in next rank
// rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
// new_cnt_cpt_r <= #TCQ 1'b1;
// cal1_cnt_cpt_r <= #TCQ 'b0;
// cal1_state_r <= #TCQ CAL1_IDLE;
// end
end else begin
// All DQS groups in a rank done
rdlvl_rank_done_r <= #TCQ 1'b1;
if (rnk_cnt_r == RANKS-1) begin
// All DQS groups in all ranks done
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end else begin
// Process DQS groups in next rank
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_cnt_cpt_r <= #TCQ 'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
end
end
end else begin
// Process next DQS group
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1;
cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT;
end
end
end
CAL1_NEW_DQS_PREWAIT: begin
if (!cal1_wait_r) begin
if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))
cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT;
else
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end
// Load rank registers in Phaser_IN
CAL1_REGL_LOAD: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
cal1_cnt_cpt_r <= #TCQ 'b0;
rnk_cnt_r <= #TCQ 2'b00;
if ((regl_rank_cnt == RANKS-1) &&
((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin
cal1_state_r <= #TCQ CAL1_DONE;
rdlvl_last_byte_done <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
end else
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end
CAL1_RDLVL_ERR: begin
rdlvl_stg1_err <= #TCQ 1'b1;
end
// Done with this stage of calibration
// if used, allow DEBUG_PORT to control taps
CAL1_DONE: begin
mpr_rdlvl_done_r <= #TCQ 1'b1;
cal1_prech_req_r <= #TCQ 1'b0;
if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin
rdlvl_stg1_done <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
end else
rdlvl_stg1_done <= #TCQ 1'b1;
end
endcase
end
// verilint STARC-2.2.3.3 on
endmodule |
module ThingMuxOH
#(
parameter NTHINGS = 1,
parameter M = 5 )
(
input logic [NTHINGS-1:0] select_oh,
the_intf.t things_in [NTHINGS-1:0],
the_intf.i thing_out
);
endmodule |
module Thinker
#(
parameter M = 5,
parameter N = 2)
(
input logic clk,
input logic reset,
input unique_id_t uids[0:N-1],
the_intf.t thing_inp,
the_intf.i thing_out
);
the_intf #(.M(M)) curr_things [N-1:0] ();
the_intf #(.M(M)) prev_things [N-1:0] ();
the_intf #(.M(M)) curr_thing ();
the_intf #(.M(M)) prev_thing ();
logic [N-1:0] select_oh;
// 1st mux:
ThingMuxOH #(
.NTHINGS ( N ),
.M ( M ))
curr_thing_mux(
.select_oh( select_oh ),
.things_in( curr_things ),
.thing_out( curr_thing ));
// 2nd mux, comment this out and no problem:
ThingMuxOH #(
.NTHINGS ( N ),
.M ( M ))
prev_thing_mux(
.select_oh( select_oh ),
.things_in( prev_things ),
.thing_out( prev_thing ));
endmodule |
module t
(
input logic clk,
input logic reset
);
localparam M = 5;
localparam N = 2;
unique_id_t uids[0:N-1];
the_intf #(.M(M)) thing_inp();
the_intf #(.M(M)) thing_out();
Thinker #(
.M ( M ),
.N ( N ))
thinker(
.clk ( clk ),
.reset ( reset ),
.uids ( uids ),
.thing_inp( thing_inp ),
.thing_out( thing_out ));
// Previously there was a problem in V3Inst if non-default parameters was used
localparam K = 2;
the_intf #(.M(K)) thing_inp2();
the_intf #(.M(K)) thing_out2();
Thinker #(
.M ( K ),
.N ( N ))
thinker2(
.clk ( clk ),
.reset ( reset ),
.uids ( uids ),
.thing_inp( thing_inp2 ),
.thing_out( thing_out2 ));
endmodule |
module testbench();
reg tb_clk;
reg SCK;
reg MOSI;
reg SSEL;
wire MISO;
wire [7:0] MSG;
spi_slave spi1(.CLK(tb_clk),
.SCK(SCK),
.MOSI(MOSI),
.MISO(MISO),
.SSEL(SSEL),
.MSG(MSG));
initial
begin
$dumpfile("bench.vcd");
$dumpvars(0,testbench);
$display("starting testbench!!!!");
tb_clk <= 0;
repeat (10*100) begin
#1;
tb_clk <= 1;
#1;
tb_clk <= 0;
end
$display("finished OK!");
$finish;
end
reg [15:0] msg;
initial
begin
SSEL <= 1;
SCK <= 0;
MOSI <= 0;
msg <= 16'b1110001101010101;
#100;
SSEL <= 0;
repeat (16) begin
#10;
MOSI <= msg[15];
msg <= msg << 1;
SCK <= 1;
#10;
SCK <= 0;
end
SSEL <= 1;
end
reg a, b;
wand WA;
assign WA = a;
assign WA = b;
initial begin
a <= 1'bz;
b <= 1'bz;
#100;
a <= 1;
#100;
a <= 1'bz;
#100;
b <= 1;
#100;
b <= 1'bz;
#100;
a <= 0;
#100;
a <= 1'bz;
#100;
b <= 0;
#100;
b <= 1'bz;
#100;
a <= 0;
b <= 0;
#100;
a <= 1'bz;
b <= 1'bz;
#100;
a <= 1;
b <= 1;
#100;
a <= 1'bz;
b <= 1'bz;
#100;
a <= 0;
b <= 1;
#100;
a <= 1'bz;
b <= 1'bz;
#100;
a <= 1;
b <= 0;
#100;
a <= 1'bz;
b <= 1'bz;
end
endmodule |
module zynq_design_1_xbar_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input [0:0]s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output [0:0]s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12]" *) output [23:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *) output [63:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *) output [15:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *) output [5:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *) output [3:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *) output [1:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *) output [7:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *) output [5:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *) output [7:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *) output [7:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *) output [1:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *) input [1:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *) output [63:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *) output [7:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *) output [1:0]m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *) output [1:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *) input [1:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12]" *) input [23:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *) input [3:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *) input [1:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *) output [1:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12]" *) output [23:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *) output [63:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *) output [15:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *) output [5:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *) output [3:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *) output [1:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *) output [7:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *) output [5:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *) output [7:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *) output [7:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *) output [1:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *) input [1:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12]" *) input [23:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *) input [63:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *) input [3:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *) input [1:0]m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *) input [1:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *) output [1:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [63:0]m_axi_araddr;
wire [3:0]m_axi_arburst;
wire [7:0]m_axi_arcache;
wire [23:0]m_axi_arid;
wire [15:0]m_axi_arlen;
wire [1:0]m_axi_arlock;
wire [5:0]m_axi_arprot;
wire [7:0]m_axi_arqos;
wire [1:0]m_axi_arready;
wire [7:0]m_axi_arregion;
wire [5:0]m_axi_arsize;
wire [1:0]m_axi_arvalid;
wire [63:0]m_axi_awaddr;
wire [3:0]m_axi_awburst;
wire [7:0]m_axi_awcache;
wire [23:0]m_axi_awid;
wire [15:0]m_axi_awlen;
wire [1:0]m_axi_awlock;
wire [5:0]m_axi_awprot;
wire [7:0]m_axi_awqos;
wire [1:0]m_axi_awready;
wire [7:0]m_axi_awregion;
wire [5:0]m_axi_awsize;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rready;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [63:0]m_axi_wdata;
wire [1:0]m_axi_wlast;
wire [1:0]m_axi_wready;
wire [7:0]m_axi_wstrb;
wire [1:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [1:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "1" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "64'b0000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *)
(* C_M_AXI_READ_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *)
(* C_M_AXI_SECURE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *)
(* C_M_AXI_WRITE_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "2" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *)
(* C_S_AXI_THREAD_ID_WIDTH = "12" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "2'b11" *)
(* P_M_AXI_SUPPORTS_WRITE = "2'b11" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[1:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[1:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[23:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[1:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
(\s_axi_arready[0] ,
aa_mi_arvalid,
D,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
s_axi_rlast_i0,
\m_axi_arqos[7] ,
E,
\gen_axi.s_axi_rid_i_reg[11] ,
\gen_no_arbiter.m_valid_i_reg_0 ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ,
\gen_no_arbiter.m_target_hot_i_reg[0]_0 ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
m_axi_arvalid,
aresetn_d_reg,
aclk,
SR,
r_issuing_cnt,
\gen_axi.read_cnt_reg[5] ,
p_15_in,
mi_arready_2,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
s_axi_arvalid,
\chosen_reg[0] ,
\gen_multi_thread.accept_cnt_reg[3] ,
st_aa_artarget_hot,
\s_axi_arqos[3] ,
\s_axi_araddr[30] ,
\s_axi_araddr[28] ,
\s_axi_araddr[25] ,
\m_payload_i_reg[34] ,
m_axi_arready,
\m_payload_i_reg[34]_0 ,
s_axi_rready,
m_valid_i_reg,
Q,
m_valid_i,
aresetn_d,
aresetn_d_reg_0);
output \s_axi_arready[0] ;
output aa_mi_arvalid;
output [2:0]D;
output [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
output s_axi_rlast_i0;
output [68:0]\m_axi_arqos[7] ;
output [0:0]E;
output [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
output \gen_no_arbiter.m_valid_i_reg_0 ;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ;
output [0:0]\gen_no_arbiter.m_target_hot_i_reg[0]_0 ;
output [0:0]\gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [0:0]\gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [1:0]m_axi_arvalid;
input aresetn_d_reg;
input aclk;
input [0:0]SR;
input [7:0]r_issuing_cnt;
input \gen_axi.read_cnt_reg[5] ;
input p_15_in;
input mi_arready_2;
input \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input [0:0]s_axi_arvalid;
input \chosen_reg[0] ;
input \gen_multi_thread.accept_cnt_reg[3] ;
input [0:0]st_aa_artarget_hot;
input [68:0]\s_axi_arqos[3] ;
input \s_axi_araddr[30] ;
input \s_axi_araddr[28] ;
input \s_axi_araddr[25] ;
input \m_payload_i_reg[34] ;
input [1:0]m_axi_arready;
input \m_payload_i_reg[34]_0 ;
input [0:0]s_axi_rready;
input m_valid_i_reg;
input [0:0]Q;
input m_valid_i;
input aresetn_d;
input aresetn_d_reg_0;
wire [2:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [0:0]SR;
wire [1:0]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire aresetn_d_reg_0;
wire \chosen_reg[0] ;
wire \gen_axi.read_cnt_reg[5] ;
wire [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_axi.s_axi_rlast_i_i_6_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ;
wire [0:0]\gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ;
wire [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [0:0]\gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ;
wire \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1__0_n_0 ;
wire \gen_no_arbiter.m_valid_i_reg_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire [68:0]\m_axi_arqos[7] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire \m_payload_i_reg[34] ;
wire \m_payload_i_reg[34]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire mi_arready_2;
wire p_15_in;
wire [7:0]r_issuing_cnt;
wire \s_axi_araddr[25] ;
wire \s_axi_araddr[28] ;
wire \s_axi_araddr[30] ;
wire [68:0]\s_axi_arqos[3] ;
wire \s_axi_arready[0] ;
wire [0:0]s_axi_arvalid;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire s_ready_i2;
wire [0:0]st_aa_artarget_hot;
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0080))
\gen_axi.s_axi_rid_i[11]_i_1
(.I0(aa_mi_arvalid),
.I1(\gen_axi.s_axi_rid_i_reg[11] ),
.I2(mi_arready_2),
.I3(p_15_in),
.O(E));
LUT6 #(
.INIT(64'h444444444444444F))
\gen_axi.s_axi_rlast_i_i_2
(.I0(\gen_axi.read_cnt_reg[5] ),
.I1(p_15_in),
.I2(\gen_axi.s_axi_rlast_i_i_6_n_0 ),
.I3(\m_axi_arqos[7] [44]),
.I4(\m_axi_arqos[7] [45]),
.I5(\m_axi_arqos[7] [47]),
.O(s_axi_rlast_i0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_axi.s_axi_rlast_i_i_6
(.I0(\m_axi_arqos[7] [49]),
.I1(p_15_in),
.I2(\m_axi_arqos[7] [48]),
.I3(\m_axi_arqos[7] [46]),
.I4(\m_axi_arqos[7] [51]),
.I5(\m_axi_arqos[7] [50]),
.O(\gen_axi.s_axi_rlast_i_i_6_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[0].r_issuing_cnt[1]_i_1
(.I0(r_issuing_cnt[0]),
.I1(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I2(r_issuing_cnt[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].r_issuing_cnt[2]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I1(r_issuing_cnt[0]),
.I2(r_issuing_cnt[1]),
.I3(r_issuing_cnt[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h6666666666666662))
\gen_master_slots[0].r_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ),
.I1(\m_payload_i_reg[34] ),
.I2(r_issuing_cnt[0]),
.I3(r_issuing_cnt[1]),
.I4(r_issuing_cnt[2]),
.I5(r_issuing_cnt[3]),
.O(\gen_master_slots[0].r_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[0].r_issuing_cnt[3]_i_2
(.I0(r_issuing_cnt[3]),
.I1(r_issuing_cnt[2]),
.I2(r_issuing_cnt[1]),
.I3(r_issuing_cnt[0]),
.I4(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[0].r_issuing_cnt[3]_i_3
(.I0(m_axi_arready[0]),
.I1(aa_mi_artarget_hot[0]),
.I2(aa_mi_arvalid),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[0].r_issuing_cnt[3]_i_5
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.I2(m_axi_arready[0]),
.I3(\m_payload_i_reg[34] ),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].r_issuing_cnt[10]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I1(r_issuing_cnt[4]),
.I2(r_issuing_cnt[5]),
.I3(r_issuing_cnt[6]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [1]));
LUT6 #(
.INIT(64'h6666666666666662))
\gen_master_slots[1].r_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ),
.I1(\m_payload_i_reg[34]_0 ),
.I2(r_issuing_cnt[4]),
.I3(r_issuing_cnt[5]),
.I4(r_issuing_cnt[6]),
.I5(r_issuing_cnt[7]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[8] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[1].r_issuing_cnt[11]_i_2
(.I0(r_issuing_cnt[7]),
.I1(r_issuing_cnt[6]),
.I2(r_issuing_cnt[5]),
.I3(r_issuing_cnt[4]),
.I4(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[1].r_issuing_cnt[11]_i_3
(.I0(m_axi_arready[1]),
.I1(aa_mi_artarget_hot[1]),
.I2(aa_mi_arvalid),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0080808080808080))
\gen_master_slots[1].r_issuing_cnt[11]_i_5
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[1]),
.I2(m_axi_arready[1]),
.I3(s_axi_rready),
.I4(m_valid_i_reg),
.I5(Q),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[1].r_issuing_cnt[9]_i_1
(.I0(r_issuing_cnt[4]),
.I1(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I2(r_issuing_cnt[5]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[2].r_issuing_cnt[16]_i_2
(.I0(mi_arready_2),
.I1(\gen_axi.s_axi_rid_i_reg[11] ),
.I2(aa_mi_arvalid),
.O(\gen_no_arbiter.m_valid_i_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0
(.I0(st_aa_artarget_hot),
.I1(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1__0
(.I0(aa_mi_arvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [0]),
.Q(\m_axi_arqos[7] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [10]),
.Q(\m_axi_arqos[7] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [11]),
.Q(\m_axi_arqos[7] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [12]),
.Q(\m_axi_arqos[7] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [13]),
.Q(\m_axi_arqos[7] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [14]),
.Q(\m_axi_arqos[7] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [15]),
.Q(\m_axi_arqos[7] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [16]),
.Q(\m_axi_arqos[7] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [17]),
.Q(\m_axi_arqos[7] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [18]),
.Q(\m_axi_arqos[7] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [19]),
.Q(\m_axi_arqos[7] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [1]),
.Q(\m_axi_arqos[7] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [20]),
.Q(\m_axi_arqos[7] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [21]),
.Q(\m_axi_arqos[7] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [22]),
.Q(\m_axi_arqos[7] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [23]),
.Q(\m_axi_arqos[7] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [24]),
.Q(\m_axi_arqos[7] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [25]),
.Q(\m_axi_arqos[7] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [26]),
.Q(\m_axi_arqos[7] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [27]),
.Q(\m_axi_arqos[7] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [28]),
.Q(\m_axi_arqos[7] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [29]),
.Q(\m_axi_arqos[7] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [2]),
.Q(\m_axi_arqos[7] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [30]),
.Q(\m_axi_arqos[7] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [31]),
.Q(\m_axi_arqos[7] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [32]),
.Q(\m_axi_arqos[7] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [33]),
.Q(\m_axi_arqos[7] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [34]),
.Q(\m_axi_arqos[7] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [35]),
.Q(\m_axi_arqos[7] [35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [36]),
.Q(\m_axi_arqos[7] [36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [37]),
.Q(\m_axi_arqos[7] [37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [38]),
.Q(\m_axi_arqos[7] [38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [39]),
.Q(\m_axi_arqos[7] [39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [3]),
.Q(\m_axi_arqos[7] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [40]),
.Q(\m_axi_arqos[7] [40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [41]),
.Q(\m_axi_arqos[7] [41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [42]),
.Q(\m_axi_arqos[7] [42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [43]),
.Q(\m_axi_arqos[7] [43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [44]),
.Q(\m_axi_arqos[7] [44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [45]),
.Q(\m_axi_arqos[7] [45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [46]),
.Q(\m_axi_arqos[7] [46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [47]),
.Q(\m_axi_arqos[7] [47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [48]),
.Q(\m_axi_arqos[7] [48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [49]),
.Q(\m_axi_arqos[7] [49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [4]),
.Q(\m_axi_arqos[7] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [50]),
.Q(\m_axi_arqos[7] [50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [51]),
.Q(\m_axi_arqos[7] [51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [52]),
.Q(\m_axi_arqos[7] [52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [53]),
.Q(\m_axi_arqos[7] [53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [54]),
.Q(\m_axi_arqos[7] [54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [55]),
.Q(\m_axi_arqos[7] [55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [56]),
.Q(\m_axi_arqos[7] [56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [57]),
.Q(\m_axi_arqos[7] [57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [58]),
.Q(\m_axi_arqos[7] [58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [5]),
.Q(\m_axi_arqos[7] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [59]),
.Q(\m_axi_arqos[7] [59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [60]),
.Q(\m_axi_arqos[7] [60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [61]),
.Q(\m_axi_arqos[7] [61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [62]),
.Q(\m_axi_arqos[7] [62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [63]),
.Q(\m_axi_arqos[7] [63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [64]),
.Q(\m_axi_arqos[7] [64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [6]),
.Q(\m_axi_arqos[7] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [65]),
.Q(\m_axi_arqos[7] [65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [66]),
.Q(\m_axi_arqos[7] [66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [67]),
.Q(\m_axi_arqos[7] [67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [68]),
.Q(\m_axi_arqos[7] [68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [7]),
.Q(\m_axi_arqos[7] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [8]),
.Q(\m_axi_arqos[7] [8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [9]),
.Q(\m_axi_arqos[7] [9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_artarget_hot[0]),
.O(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\gen_no_arbiter.m_target_hot_i[0]_i_2
(.I0(\s_axi_arqos[3] [33]),
.I1(\s_axi_arqos[3] [36]),
.I2(\s_axi_araddr[30] ),
.I3(\s_axi_araddr[28] ),
.I4(\s_axi_araddr[25] ),
.O(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(st_aa_artarget_hot),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_artarget_hot[1]),
.O(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ),
.Q(aa_mi_artarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ),
.Q(aa_mi_artarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg_0),
.Q(\gen_axi.s_axi_rid_i_reg[11] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF0000002A))
\gen_no_arbiter.m_valid_i_i_1__0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.I2(m_axi_arready[0]),
.I3(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ),
.I4(\gen_no_arbiter.m_valid_i_reg_0 ),
.I5(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ),
.Q(aa_mi_arvalid),
.R(SR));
LUT6 #(
.INIT(64'hFFEFFFEFFFEFFFFF))
\gen_no_arbiter.s_ready_i[0]_i_7__0
(.I0(\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.I1(aa_mi_arvalid),
.I2(s_axi_arvalid),
.I3(\s_axi_arready[0] ),
.I4(\chosen_reg[0] ),
.I5(\gen_multi_thread.accept_cnt_reg[3] ),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg),
.Q(\s_axi_arready[0] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[0]_INST_0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[1]_INST_0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[1]),
.O(m_axi_arvalid[1]));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
(ss_aa_awready,
aa_sa_awvalid,
\m_ready_d_reg[0] ,
\m_ready_d_reg[1] ,
aa_mi_awtarget_hot,
D,
\gen_master_slots[1].w_issuing_cnt_reg[9] ,
\gen_master_slots[0].w_issuing_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
E,
\gen_master_slots[0].w_issuing_cnt_reg[0] ,
m_axi_awvalid,
st_aa_awtarget_hot,
\gen_no_arbiter.m_target_hot_i_reg[2]_0 ,
\m_ready_d_reg[1]_0 ,
Q,
aresetn_d_reg,
aclk,
SR,
m_ready_d,
aresetn_d,
w_issuing_cnt,
\chosen_reg[1] ,
m_axi_awready,
\chosen_reg[0] ,
mi_awready_2,
m_valid_i_reg,
s_axi_bready,
\s_axi_awaddr[26] ,
\s_axi_awaddr[20] ,
\s_axi_awqos[3] ,
m_ready_d_0,
m_valid_i,
st_aa_awtarget_enc,
aresetn_d_reg_0);
output ss_aa_awready;
output aa_sa_awvalid;
output \m_ready_d_reg[0] ;
output \m_ready_d_reg[1] ;
output [2:0]aa_mi_awtarget_hot;
output [2:0]D;
output \gen_master_slots[1].w_issuing_cnt_reg[9] ;
output [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]E;
output [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
output [1:0]m_axi_awvalid;
output [0:0]st_aa_awtarget_hot;
output \gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
output \m_ready_d_reg[1]_0 ;
output [68:0]Q;
input aresetn_d_reg;
input aclk;
input [0:0]SR;
input [1:0]m_ready_d;
input aresetn_d;
input [7:0]w_issuing_cnt;
input \chosen_reg[1] ;
input [1:0]m_axi_awready;
input \chosen_reg[0] ;
input mi_awready_2;
input m_valid_i_reg;
input [0:0]s_axi_bready;
input \s_axi_awaddr[26] ;
input \s_axi_awaddr[20] ;
input [68:0]\s_axi_awqos[3] ;
input [0:0]m_ready_d_0;
input m_valid_i;
input [0:0]st_aa_awtarget_enc;
input aresetn_d_reg_0;
wire [2:0]D;
wire [0:0]E;
wire [68:0]Q;
wire [0:0]SR;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire aresetn_d_reg_0;
wire \chosen_reg[0] ;
wire \chosen_reg[1] ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ;
wire [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
wire [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ;
wire \gen_master_slots[1].w_issuing_cnt_reg[9] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [1:0]m_ready_d;
wire \m_ready_d[1]_i_4_n_0 ;
wire [0:0]m_ready_d_0;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire mi_awready_2;
wire \s_axi_awaddr[20] ;
wire \s_axi_awaddr[26] ;
wire [68:0]\s_axi_awqos[3] ;
wire [0:0]s_axi_bready;
wire s_ready_i2;
wire ss_aa_awready;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [7:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h4000))
\gen_axi.s_axi_wready_i_i_2
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[2]),
.I3(mi_awready_2),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16] ));
LUT6 #(
.INIT(64'h6AAAAAAA95555555))
\gen_master_slots[0].w_issuing_cnt[1]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\chosen_reg[0] ),
.I2(m_axi_awready[0]),
.I3(aa_mi_awtarget_hot[0]),
.I4(\gen_master_slots[1].w_issuing_cnt_reg[9] ),
.I5(w_issuing_cnt[1]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].w_issuing_cnt[2]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]));
LUT6 #(
.INIT(64'hAAAAAAAA55555554))
\gen_master_slots[0].w_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ),
.I1(w_issuing_cnt[3]),
.I2(w_issuing_cnt[0]),
.I3(w_issuing_cnt[2]),
.I4(w_issuing_cnt[1]),
.I5(\chosen_reg[0] ),
.O(\gen_master_slots[0].w_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[0].w_issuing_cnt[3]_i_2
(.I0(w_issuing_cnt[3]),
.I1(w_issuing_cnt[0]),
.I2(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I3(w_issuing_cnt[1]),
.I4(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h4000))
\gen_master_slots[0].w_issuing_cnt[3]_i_3
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[0]),
.I3(m_axi_awready[0]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00008000))
\gen_master_slots[0].w_issuing_cnt[3]_i_5
(.I0(\chosen_reg[0] ),
.I1(m_axi_awready[0]),
.I2(aa_mi_awtarget_hot[0]),
.I3(aa_sa_awvalid),
.I4(m_ready_d[1]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].w_issuing_cnt[10]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I2(w_issuing_cnt[5]),
.I3(w_issuing_cnt[6]),
.O(D[1]));
LUT6 #(
.INIT(64'hAAAAAAAA55555554))
\gen_master_slots[1].w_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ),
.I1(w_issuing_cnt[7]),
.I2(w_issuing_cnt[4]),
.I3(w_issuing_cnt[6]),
.I4(w_issuing_cnt[5]),
.I5(\chosen_reg[1] ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[1].w_issuing_cnt[11]_i_2
(.I0(w_issuing_cnt[7]),
.I1(w_issuing_cnt[4]),
.I2(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I3(w_issuing_cnt[5]),
.I4(w_issuing_cnt[6]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h4000))
\gen_master_slots[1].w_issuing_cnt[11]_i_3
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[1]),
.I3(m_axi_awready[1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000070000000))
\gen_master_slots[1].w_issuing_cnt[11]_i_5
(.I0(m_valid_i_reg),
.I1(s_axi_bready),
.I2(m_axi_awready[1]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_sa_awvalid),
.I5(m_ready_d[1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAA95555555))
\gen_master_slots[1].w_issuing_cnt[9]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\chosen_reg[1] ),
.I2(m_axi_awready[1]),
.I3(aa_mi_awtarget_hot[1]),
.I4(\gen_master_slots[1].w_issuing_cnt_reg[9] ),
.I5(w_issuing_cnt[5]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h2))
\gen_master_slots[1].w_issuing_cnt[9]_i_2
(.I0(aa_sa_awvalid),
.I1(m_ready_d[1]),
.O(\gen_master_slots[1].w_issuing_cnt_reg[9] ));
LUT5 #(
.INIT(32'h10000000))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ),
.I1(\s_axi_awaddr[26] ),
.I2(\s_axi_awaddr[20] ),
.I3(\s_axi_awqos[3] [33]),
.I4(\s_axi_awqos[3] [36]),
.O(st_aa_awtarget_hot));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9
(.I0(\s_axi_awqos[3] [35]),
.I1(\s_axi_awqos[3] [31]),
.I2(\s_axi_awqos[3] [28]),
.I3(\s_axi_awqos[3] [39]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_2
(.I0(aa_sa_awvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [0]),
.Q(Q[0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [10]),
.Q(Q[10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [11]),
.Q(Q[11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [12]),
.Q(Q[12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [13]),
.Q(Q[13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [14]),
.Q(Q[14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [15]),
.Q(Q[15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [16]),
.Q(Q[16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [17]),
.Q(Q[17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [18]),
.Q(Q[18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [19]),
.Q(Q[19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [1]),
.Q(Q[1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [20]),
.Q(Q[20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [21]),
.Q(Q[21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [22]),
.Q(Q[22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [23]),
.Q(Q[23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [24]),
.Q(Q[24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [25]),
.Q(Q[25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [26]),
.Q(Q[26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [27]),
.Q(Q[27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [28]),
.Q(Q[28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [29]),
.Q(Q[29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [2]),
.Q(Q[2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [30]),
.Q(Q[30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [31]),
.Q(Q[31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [32]),
.Q(Q[32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [33]),
.Q(Q[33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [34]),
.Q(Q[34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [35]),
.Q(Q[35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [36]),
.Q(Q[36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [37]),
.Q(Q[37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [38]),
.Q(Q[38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [39]),
.Q(Q[39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [3]),
.Q(Q[3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [40]),
.Q(Q[40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [41]),
.Q(Q[41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [42]),
.Q(Q[42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [43]),
.Q(Q[43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [44]),
.Q(Q[44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [45]),
.Q(Q[45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [46]),
.Q(Q[46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [47]),
.Q(Q[47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [48]),
.Q(Q[48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [49]),
.Q(Q[49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [4]),
.Q(Q[4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [50]),
.Q(Q[50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [51]),
.Q(Q[51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [52]),
.Q(Q[52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [53]),
.Q(Q[53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [54]),
.Q(Q[54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [55]),
.Q(Q[55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [56]),
.Q(Q[56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [57]),
.Q(Q[57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [58]),
.Q(Q[58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [5]),
.Q(Q[5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [59]),
.Q(Q[59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [60]),
.Q(Q[60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [61]),
.Q(Q[61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [62]),
.Q(Q[62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [63]),
.Q(Q[63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [64]),
.Q(Q[64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [6]),
.Q(Q[6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [65]),
.Q(Q[65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [66]),
.Q(Q[66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [67]),
.Q(Q[67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [68]),
.Q(Q[68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [7]),
.Q(Q[7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [8]),
.Q(Q[8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [9]),
.Q(Q[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(st_aa_awtarget_hot),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_awtarget_hot[0]),
.O(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(st_aa_awtarget_enc),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_awtarget_hot[1]),
.O(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ),
.Q(aa_mi_awtarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ),
.Q(aa_mi_awtarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg_0),
.Q(aa_mi_awtarget_hot[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF2))
\gen_no_arbiter.m_valid_i_i_1
(.I0(aa_sa_awvalid),
.I1(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.I2(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h0000FFFE))
\gen_no_arbiter.m_valid_i_i_2
(.I0(aa_mi_awtarget_hot[0]),
.I1(aa_mi_awtarget_hot[1]),
.I2(aa_mi_awtarget_hot[2]),
.I3(m_ready_d[0]),
.I4(\m_ready_d_reg[1] ),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(aa_sa_awvalid),
.R(SR));
LUT2 #(
.INIT(4'hE))
\gen_no_arbiter.s_ready_i[0]_i_29
(.I0(ss_aa_awready),
.I1(m_ready_d_0),
.O(\gen_no_arbiter.m_target_hot_i_reg[2]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg),
.Q(ss_aa_awready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h20))
\m_axi_awvalid[0]_INST_0
(.I0(aa_mi_awtarget_hot[0]),
.I1(m_ready_d[1]),
.I2(aa_sa_awvalid),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h20))
\m_axi_awvalid[1]_INST_0
(.I0(aa_mi_awtarget_hot[1]),
.I1(m_ready_d[1]),
.I2(aa_sa_awvalid),
.O(m_axi_awvalid[1]));
LUT6 #(
.INIT(64'h55555554FFFFFFFF))
\m_ready_d[0]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(m_ready_d[0]),
.I2(aa_mi_awtarget_hot[2]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_mi_awtarget_hot[0]),
.I5(aresetn_d),
.O(\m_ready_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hFFFE))
\m_ready_d[1]_i_2
(.I0(m_ready_d[0]),
.I1(aa_mi_awtarget_hot[2]),
.I2(aa_mi_awtarget_hot[1]),
.I3(aa_mi_awtarget_hot[0]),
.O(\m_ready_d_reg[1]_0 ));
LUT6 #(
.INIT(64'h0000000000000777))
\m_ready_d[1]_i_3
(.I0(m_axi_awready[1]),
.I1(aa_mi_awtarget_hot[1]),
.I2(mi_awready_2),
.I3(aa_mi_awtarget_hot[2]),
.I4(\m_ready_d[1]_i_4_n_0 ),
.I5(m_ready_d[1]),
.O(\m_ready_d_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\m_ready_d[1]_i_4
(.I0(m_axi_awready[0]),
.I1(aa_mi_awtarget_hot[0]),
.O(\m_ready_d[1]_i_4_n_0 ));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
D,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
\chosen_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
SR,
E,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
s_axi_bvalid,
\chosen_reg[1]_0 ,
\gen_master_slots[1].w_issuing_cnt_reg[8] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ,
aresetn_d,
Q,
\m_ready_d_reg[1] ,
p_80_out,
s_axi_bready,
\s_axi_awaddr[26] ,
st_aa_awtarget_hot,
aa_mi_awtarget_hot,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ,
\gen_master_slots[1].w_issuing_cnt_reg[10] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ,
CO,
\m_ready_d_reg[1]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ,
\m_ready_d_reg[1]_1 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
\m_ready_d_reg[1]_2 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
cmd_push_3,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ,
\m_ready_d_reg[1]_3 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
\m_ready_d_reg[1]_4 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
cmd_push_0,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ,
\gen_multi_thread.accept_cnt_reg[0] ,
aa_sa_awvalid,
s_axi_awvalid,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
m_valid_i_reg,
p_38_out,
p_60_out,
w_issuing_cnt,
\m_ready_d_reg[1]_5 ,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output [2:0]D;
output \gen_master_slots[0].w_issuing_cnt_reg[1] ;
output \chosen_reg[0]_0 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]SR;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]s_axi_bvalid;
output \chosen_reg[1]_0 ;
output \gen_master_slots[1].w_issuing_cnt_reg[8] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
input aresetn_d;
input [3:0]Q;
input \m_ready_d_reg[1] ;
input p_80_out;
input [0:0]s_axi_bready;
input [0:0]\s_axi_awaddr[26] ;
input [0:0]st_aa_awtarget_hot;
input [0:0]aa_mi_awtarget_hot;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ;
input \gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ;
input \gen_master_slots[1].w_issuing_cnt_reg[10] ;
input \gen_master_slots[2].w_issuing_cnt_reg[16]_1 ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ;
input [0:0]CO;
input \m_ready_d_reg[1]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
input \m_ready_d_reg[1]_1 ;
input \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input \m_ready_d_reg[1]_2 ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input cmd_push_3;
input \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
input \m_ready_d_reg[1]_3 ;
input \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input \m_ready_d_reg[1]_4 ;
input \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input cmd_push_0;
input \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
input [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
input \gen_multi_thread.accept_cnt_reg[0] ;
input aa_sa_awvalid;
input [0:0]s_axi_awvalid;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input m_valid_i_reg;
input p_38_out;
input p_60_out;
input [4:0]w_issuing_cnt;
input \m_ready_d_reg[1]_5 ;
input aclk;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [0:0]SR;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \chosen[0]_i_1__0_n_0 ;
wire \chosen[1]_i_1__0_n_0 ;
wire \chosen[2]_i_1__0_n_0 ;
wire \chosen_reg[0]_0 ;
wire \chosen_reg[1]_0 ;
wire cmd_push_0;
wire cmd_push_3;
wire \gen_master_slots[0].w_issuing_cnt_reg[1] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[10] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_1 ;
wire \gen_multi_thread.accept_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire \gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire \gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i[0]_i_24_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_25_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_7_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \last_rr_hot[0]_i_1_n_0 ;
wire \last_rr_hot[1]_i_1_n_0 ;
wire \last_rr_hot[2]_i_1_n_0 ;
wire \last_rr_hot[2]_i_6_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[1]_2 ;
wire \m_ready_d_reg[1]_3 ;
wire \m_ready_d_reg[1]_4 ;
wire \m_ready_d_reg[1]_5 ;
wire m_valid_i;
wire m_valid_i_reg;
wire need_arbitration;
wire [2:0]next_rr_hot;
wire p_38_out;
wire p_3_in;
wire p_4_in;
wire p_60_out;
wire p_80_out;
wire [0:0]\s_axi_awaddr[26] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]st_aa_awtarget_hot;
wire [4:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\chosen[0]_i_1__0
(.I0(next_rr_hot[0]),
.I1(need_arbitration),
.I2(\chosen_reg[0]_0 ),
.O(\chosen[0]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\chosen[1]_i_1__0
(.I0(next_rr_hot[1]),
.I1(need_arbitration),
.I2(\chosen_reg[1]_0 ),
.O(\chosen[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\chosen[2]_i_1__0
(.I0(next_rr_hot[2]),
.I1(need_arbitration),
.I2(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.O(\chosen[2]_i_1__0_n_0 ));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\chosen[0]_i_1__0_n_0 ),
.Q(\chosen_reg[0]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\chosen[1]_i_1__0_n_0 ),
.Q(\chosen_reg[1]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\chosen[2]_i_1__0_n_0 ),
.Q(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.R(SR));
LUT3 #(
.INIT(8'h7F))
\gen_master_slots[0].w_issuing_cnt[3]_i_4
(.I0(\chosen_reg[0]_0 ),
.I1(p_80_out),
.I2(s_axi_bready),
.O(\gen_master_slots[0].w_issuing_cnt_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h7F))
\gen_master_slots[1].w_issuing_cnt[11]_i_4
(.I0(s_axi_bready),
.I1(\chosen_reg[1]_0 ),
.I2(p_60_out),
.O(\gen_master_slots[1].w_issuing_cnt_reg[8] ));
LUT5 #(
.INIT(32'h807F7F00))
\gen_master_slots[2].w_issuing_cnt[16]_i_1
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(s_axi_bready),
.I3(\m_ready_d_reg[1]_5 ),
.I4(w_issuing_cnt[4]),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hA956))
\gen_multi_thread.accept_cnt[1]_i_1
(.I0(Q[0]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\m_ready_d_reg[1] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT5 #(
.INIT(32'hEFF1100E))
\gen_multi_thread.accept_cnt[2]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFE00000000FFFF))
\gen_multi_thread.accept_cnt[3]_i_1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hAAA6AAAAAAAA999A))
\gen_multi_thread.accept_cnt[3]_i_2
(.I0(Q[3]),
.I1(Q[0]),
.I2(\m_ready_d_reg[1] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I4(Q[1]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1
(.I0(cmd_push_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1
(.I0(\m_ready_d_reg[1]_4 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1
(.I0(\m_ready_d_reg[1]_3 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1
(.I0(cmd_push_3),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1
(.I0(\m_ready_d_reg[1]_2 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1
(.I0(\m_ready_d_reg[1]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1
(.I0(\m_ready_d_reg[1]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ),
.I3(CO),
.O(E));
LUT6 #(
.INIT(64'h00AAAA80AA80AA80))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3
(.I0(s_axi_bready),
.I1(\chosen_reg[0]_0 ),
.I2(p_80_out),
.I3(m_valid_i_reg),
.I4(p_38_out),
.I5(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1
(.I0(aresetn_d),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT5 #(
.INIT(32'h1FFF1000))
\gen_no_arbiter.m_target_hot_i[2]_i_1
(.I0(\s_axi_awaddr[26] ),
.I1(st_aa_awtarget_hot),
.I2(m_valid_i),
.I3(aresetn_d),
.I4(aa_mi_awtarget_hot),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h000000000000F022))
\gen_no_arbiter.s_ready_i[0]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ),
.I3(\s_axi_awaddr[26] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ),
.O(m_valid_i));
LUT6 #(
.INIT(64'hFFFFFFFFFF40FFFF))
\gen_no_arbiter.s_ready_i[0]_i_24
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I1(Q[3]),
.I2(\gen_multi_thread.accept_cnt_reg[0] ),
.I3(aa_sa_awvalid),
.I4(s_axi_awvalid),
.I5(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ));
LUT5 #(
.INIT(32'h00020000))
\gen_no_arbiter.s_ready_i[0]_i_25
(.I0(\gen_master_slots[0].w_issuing_cnt_reg[1] ),
.I1(w_issuing_cnt[2]),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[0]),
.I4(w_issuing_cnt[3]),
.O(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ));
LUT6 #(
.INIT(64'hEFAAEFEFEFAAEAEA))
\gen_no_arbiter.s_ready_i[0]_i_7
(.I0(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ),
.I2(st_aa_awtarget_hot),
.I3(\gen_master_slots[1].w_issuing_cnt_reg[10] ),
.I4(\s_axi_awaddr[26] ),
.I5(\gen_master_slots[2].w_issuing_cnt_reg[16]_1 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFF57AA00))
\last_rr_hot[0]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF5F7A0A0))
\last_rr_hot[1]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_3_in),
.O(\last_rr_hot[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hDDDF8888))
\last_rr_hot[2]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_4_in),
.O(\last_rr_hot[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEE00000FEE))
\last_rr_hot[2]_i_2
(.I0(p_60_out),
.I1(p_38_out),
.I2(\chosen_reg[0]_0 ),
.I3(p_80_out),
.I4(\last_rr_hot[2]_i_6_n_0 ),
.I5(s_axi_bready),
.O(need_arbitration));
LUT6 #(
.INIT(64'hAAAAAAAA20222020))
\last_rr_hot[2]_i_3__0
(.I0(p_38_out),
.I1(p_60_out),
.I2(\last_rr_hot_reg_n_0_[0] ),
.I3(p_80_out),
.I4(p_4_in),
.I5(p_3_in),
.O(next_rr_hot[2]));
LUT6 #(
.INIT(64'hAAAAAAAA0A0A0008))
\last_rr_hot[2]_i_4__0
(.I0(p_60_out),
.I1(p_3_in),
.I2(p_80_out),
.I3(p_38_out),
.I4(p_4_in),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[1]));
LUT6 #(
.INIT(64'h8A8A8A8A88888A88))
\last_rr_hot[2]_i_5__0
(.I0(p_80_out),
.I1(p_4_in),
.I2(p_38_out),
.I3(\last_rr_hot_reg_n_0_[0] ),
.I4(p_60_out),
.I5(p_3_in),
.O(next_rr_hot[0]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hF888))
\last_rr_hot[2]_i_6
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_60_out),
.O(\last_rr_hot[2]_i_6_n_0 ));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[0]_i_1_n_0 ),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[1]_i_1_n_0 ),
.Q(p_3_in),
.R(SR));
FDSE \last_rr_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[2]_i_1_n_0 ),
.Q(p_4_in),
.S(SR));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_bvalid[0]_INST_0
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_60_out),
.I4(p_80_out),
.I5(\chosen_reg[0]_0 ),
.O(s_axi_bvalid));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
(D,
\gen_multi_thread.accept_cnt_reg[2] ,
E,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
s_axi_rlast,
s_axi_rvalid,
\chosen_reg[1]_0 ,
\m_payload_i_reg[34] ,
s_axi_rresp,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
s_axi_rid,
s_axi_rdata,
\m_payload_i_reg[34]_0 ,
Q,
\gen_no_arbiter.s_ready_i_reg[0] ,
cmd_push_3,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ,
CO,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ,
\gen_no_arbiter.s_ready_i_reg[0]_1 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ,
\gen_no_arbiter.s_ready_i_reg[0]_2 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
\gen_no_arbiter.s_ready_i_reg[0]_3 ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ,
\gen_no_arbiter.s_ready_i_reg[0]_4 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
\gen_no_arbiter.s_ready_i_reg[0]_5 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
cmd_push_0,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ,
p_74_out,
s_axi_rready,
p_54_out,
p_32_out,
\m_payload_i_reg[46] ,
\m_payload_i_reg[46]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ,
\m_payload_i_reg[46]_1 ,
SR,
aclk);
output [2:0]D;
output \gen_multi_thread.accept_cnt_reg[2] ;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output [0:0]\m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output \chosen_reg[1]_0 ;
output \m_payload_i_reg[34] ;
output [0:0]s_axi_rresp;
output [3:0]S;
output [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output [11:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[34]_0 ;
input [3:0]Q;
input \gen_no_arbiter.s_ready_i_reg[0] ;
input cmd_push_3;
input \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
input [0:0]CO;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ;
input \gen_no_arbiter.s_ready_i_reg[0]_1 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
input \gen_no_arbiter.s_ready_i_reg[0]_2 ;
input \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input \gen_no_arbiter.s_ready_i_reg[0]_3 ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ;
input \gen_no_arbiter.s_ready_i_reg[0]_4 ;
input \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input \gen_no_arbiter.s_ready_i_reg[0]_5 ;
input \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input cmd_push_0;
input \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
input [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
input p_74_out;
input [0:0]s_axi_rready;
input p_54_out;
input p_32_out;
input [25:0]\m_payload_i_reg[46] ;
input [25:0]\m_payload_i_reg[46]_0 ;
input [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
input [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
input [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
input [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
input [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
input [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
input [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
input [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
input [12:0]\m_payload_i_reg[46]_1 ;
input [0:0]SR;
input aclk;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]S;
wire [0:0]SR;
wire aclk;
wire \chosen[0]_i_1_n_0 ;
wire \chosen[1]_i_1_n_0 ;
wire \chosen[2]_i_1_n_0 ;
wire \chosen_reg[1]_0 ;
wire cmd_push_0;
wire cmd_push_3;
wire \gen_multi_thread.accept_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_1 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_2 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_3 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_4 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_5 ;
wire i__carry_i_10_n_0;
wire i__carry_i_11_n_0;
wire i__carry_i_12_n_0;
wire i__carry_i_13_n_0;
wire i__carry_i_14_n_0;
wire i__carry_i_15_n_0;
wire i__carry_i_16_n_0;
wire i__carry_i_5_n_0;
wire i__carry_i_6_n_0;
wire i__carry_i_7_n_0;
wire i__carry_i_8_n_0;
wire i__carry_i_9_n_0;
wire \last_rr_hot[0]_i_1__0_n_0 ;
wire \last_rr_hot[1]_i_1__0_n_0 ;
wire \last_rr_hot[2]_i_1__0_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire [0:0]\m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire \m_payload_i_reg[34] ;
wire [0:0]\m_payload_i_reg[34]_0 ;
wire [25:0]\m_payload_i_reg[46] ;
wire [25:0]\m_payload_i_reg[46]_0 ;
wire [12:0]\m_payload_i_reg[46]_1 ;
wire need_arbitration;
wire [2:0]next_rr_hot;
wire p_32_out;
wire p_3_in;
wire p_4_in;
wire p_54_out;
wire p_74_out;
wire [11:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire \s_axi_rid[11]_INST_0_i_1_n_0 ;
wire \s_axi_rid[11]_INST_0_i_2_n_0 ;
wire \s_axi_rid[11]_INST_0_i_3_n_0 ;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\chosen[0]_i_1
(.I0(next_rr_hot[0]),
.I1(need_arbitration),
.I2(\m_payload_i_reg[0]_0 ),
.O(\chosen[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\chosen[1]_i_1
(.I0(next_rr_hot[1]),
.I1(need_arbitration),
.I2(\chosen_reg[1]_0 ),
.O(\chosen[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\chosen[2]_i_1
(.I0(next_rr_hot[2]),
.I1(need_arbitration),
.I2(\m_payload_i_reg[34] ),
.O(\chosen[2]_i_1_n_0 ));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\chosen[0]_i_1_n_0 ),
.Q(\m_payload_i_reg[0]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\chosen[1]_i_1_n_0 ),
.Q(\chosen_reg[1]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\chosen[2]_i_1_n_0 ),
.Q(\m_payload_i_reg[34] ),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT4 #(
.INIT(16'hA659))
\gen_multi_thread.accept_cnt[1]_i_1__0
(.I0(Q[0]),
.I1(\gen_no_arbiter.s_ready_i_reg[0] ),
.I2(\gen_multi_thread.accept_cnt_reg[2] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hBFF4400B))
\gen_multi_thread.accept_cnt[2]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg[2] ),
.I1(\gen_no_arbiter.s_ready_i_reg[0] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_multi_thread.accept_cnt[3]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(\gen_multi_thread.accept_cnt_reg[2] ),
.I5(\gen_no_arbiter.s_ready_i_reg[0] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hA6AAAAAAAAAA9A99))
\gen_multi_thread.accept_cnt[3]_i_2__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(\gen_multi_thread.accept_cnt_reg[2] ),
.I3(\gen_no_arbiter.s_ready_i_reg[0] ),
.I4(Q[1]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0
(.I0(cmd_push_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ),
.I3(\gen_multi_thread.accept_cnt_reg[2] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_5 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_4 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0
(.I0(cmd_push_3),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ),
.I2(CO),
.I3(\gen_multi_thread.accept_cnt_reg[2] ),
.O(E));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_3 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_2 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'hA8880000))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0
(.I0(s_axi_rlast),
.I1(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(p_74_out),
.I4(s_axi_rready),
.O(\gen_multi_thread.accept_cnt_reg[2] ));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_10
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [9]),
.I2(\m_payload_i_reg[46]_0 [22]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [22]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_10_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_11
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [5]),
.I2(\m_payload_i_reg[46]_0 [18]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [18]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_11_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_12
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [17]),
.I2(\m_payload_i_reg[46]_1 [4]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46]_0 [17]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(i__carry_i_12_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_13
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [19]),
.I2(\m_payload_i_reg[46]_1 [6]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [19]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_13_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_14
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [2]),
.I2(\m_payload_i_reg[46]_0 [15]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [15]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_14_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_15
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [14]),
.I2(\m_payload_i_reg[46]_1 [1]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [14]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_15_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_16
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [3]),
.I2(\m_payload_i_reg[46]_0 [16]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [16]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_16_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [10]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [7]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [4]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_5
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [11]),
.I2(\m_payload_i_reg[46] [24]),
.I3(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I4(\m_payload_i_reg[46]_0 [24]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(i__carry_i_5_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_6
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [23]),
.I2(\m_payload_i_reg[46]_1 [10]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [23]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_6_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_7
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [25]),
.I2(\m_payload_i_reg[46]_1 [12]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [25]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_7_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_8
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [8]),
.I2(\m_payload_i_reg[46]_0 [21]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [21]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_8_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_9
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [7]),
.I2(\m_payload_i_reg[46]_0 [20]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [20]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_9_n_0));
LUT5 #(
.INIT(32'hFF57AA00))
\last_rr_hot[0]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hF5F7A0A0))
\last_rr_hot[1]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_3_in),
.O(\last_rr_hot[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hDDDF8888))
\last_rr_hot[2]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_4_in),
.O(\last_rr_hot[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hABBBABBBABBBAB88))
\last_rr_hot[2]_i_2__0
(.I0(s_axi_rready),
.I1(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(p_74_out),
.I4(p_54_out),
.I5(p_32_out),
.O(need_arbitration));
LUT6 #(
.INIT(64'hAAAAAAAA20222020))
\last_rr_hot[2]_i_3
(.I0(p_32_out),
.I1(p_54_out),
.I2(\last_rr_hot_reg_n_0_[0] ),
.I3(p_74_out),
.I4(p_4_in),
.I5(p_3_in),
.O(next_rr_hot[2]));
LUT6 #(
.INIT(64'hAAAAAAAA0A0A0008))
\last_rr_hot[2]_i_4
(.I0(p_54_out),
.I1(p_3_in),
.I2(p_74_out),
.I3(p_32_out),
.I4(p_4_in),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[1]));
LUT6 #(
.INIT(64'h8A8A8A8A88888A88))
\last_rr_hot[2]_i_5
(.I0(p_74_out),
.I1(p_4_in),
.I2(p_32_out),
.I3(\last_rr_hot_reg_n_0_[0] ),
.I4(p_54_out),
.I5(p_3_in),
.O(next_rr_hot[0]));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[0]_i_1__0_n_0 ),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[1]_i_1__0_n_0 ),
.Q(p_3_in),
.R(SR));
FDSE \last_rr_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[2]_i_1__0_n_0 ),
.Q(p_4_in),
.S(SR));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB3))
\m_payload_i[46]_i_1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(p_74_out),
.I2(s_axi_rready),
.O(\m_payload_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__1
(.I0(s_axi_rready),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.O(\m_payload_i_reg[34]_0 ));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [10]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [7]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [4]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [7]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [4]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [10]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [11]),
.I5(i__carry_i_7_n_0),
.O(S[3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [7]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [8]),
.I5(i__carry_i_10_n_0),
.O(S[2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [4]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [5]),
.I5(i__carry_i_13_n_0),
.O(S[1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [2]),
.I5(i__carry_i_16_n_0),
.O(S[0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [10]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [7]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [4]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [10]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [7]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [4]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [10]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [7]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [4]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [10]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [7]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [4]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [0]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[0]_INST_0
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [0]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[10]_INST_0
(.I0(\m_payload_i_reg[46] [5]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [5]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[11]_INST_0
(.I0(\m_payload_i_reg[46] [6]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [6]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[19]_INST_0
(.I0(\m_payload_i_reg[46] [7]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [7]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[20]_INST_0
(.I0(\m_payload_i_reg[46] [8]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [8]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[22]_INST_0
(.I0(\m_payload_i_reg[46] [9]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [9]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[27]_INST_0
(.I0(\m_payload_i_reg[46] [10]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [10]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[31]_INST_0
(.I0(\m_payload_i_reg[46] [11]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [11]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[4]_INST_0
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [1]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[6]_INST_0
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [2]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[8]_INST_0
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [3]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[9]_INST_0
(.I0(\m_payload_i_reg[46] [4]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [4]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[0]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [14]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [1]),
.I4(\m_payload_i_reg[46]_0 [14]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[0]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[10]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [24]),
.I2(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I3(\m_payload_i_reg[46] [24]),
.I4(\m_payload_i_reg[46]_1 [11]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[10]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[11]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [25]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [12]),
.I4(\m_payload_i_reg[46]_0 [25]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[11]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'hF888))
\s_axi_rid[11]_INST_0_i_1
(.I0(\m_payload_i_reg[34] ),
.I1(p_32_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_54_out),
.O(\s_axi_rid[11]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'h8FFF))
\s_axi_rid[11]_INST_0_i_2
(.I0(\chosen_reg[1]_0 ),
.I1(p_54_out),
.I2(\m_payload_i_reg[34] ),
.I3(p_32_out),
.O(\s_axi_rid[11]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT4 #(
.INIT(16'h8FFF))
\s_axi_rid[11]_INST_0_i_3
(.I0(\m_payload_i_reg[34] ),
.I1(p_32_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_54_out),
.O(\s_axi_rid[11]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[1]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [15]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [15]),
.I4(\m_payload_i_reg[46]_1 [2]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[1]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[2]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [16]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [16]),
.I4(\m_payload_i_reg[46]_1 [3]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[2]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[3]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [17]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [4]),
.I4(\m_payload_i_reg[46] [17]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(s_axi_rid[3]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[4]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [18]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [18]),
.I4(\m_payload_i_reg[46]_1 [5]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[4]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[5]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [19]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [6]),
.I4(\m_payload_i_reg[46]_0 [19]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[5]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[6]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [20]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [20]),
.I4(\m_payload_i_reg[46]_1 [7]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[6]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[7]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [21]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [21]),
.I4(\m_payload_i_reg[46]_1 [8]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[7]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[8]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [22]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [22]),
.I4(\m_payload_i_reg[46]_1 [9]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[8]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[9]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [23]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [10]),
.I4(\m_payload_i_reg[46]_0 [23]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[9]));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\s_axi_rlast[0]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [0]),
.I2(\m_payload_i_reg[46] [13]),
.I3(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I4(\m_payload_i_reg[46]_0 [13]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rlast));
LUT6 #(
.INIT(64'h3FEAEAEA00EAEAEA))
\s_axi_rresp[1]_INST_0
(.I0(\m_payload_i_reg[46] [12]),
.I1(p_32_out),
.I2(\m_payload_i_reg[34] ),
.I3(p_54_out),
.I4(\chosen_reg[1]_0 ),
.I5(\m_payload_i_reg[46]_0 [12]),
.O(s_axi_rresp));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rvalid[0]_INST_0
(.I0(p_54_out),
.I1(\chosen_reg[1]_0 ),
.I2(p_32_out),
.I3(\m_payload_i_reg[34] ),
.I4(\m_payload_i_reg[0]_0 ),
.I5(p_74_out),
.O(s_axi_rvalid));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [23:0]m_axi_awid;
output [63:0]m_axi_awaddr;
output [15:0]m_axi_awlen;
output [5:0]m_axi_awsize;
output [3:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [7:0]m_axi_awcache;
output [5:0]m_axi_awprot;
output [7:0]m_axi_awregion;
output [7:0]m_axi_awqos;
output [1:0]m_axi_awuser;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [23:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wlast;
output [1:0]m_axi_wuser;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [1:0]m_axi_buser;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [23:0]m_axi_arid;
output [63:0]m_axi_araddr;
output [15:0]m_axi_arlen;
output [5:0]m_axi_arsize;
output [3:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [7:0]m_axi_arcache;
output [5:0]m_axi_arprot;
output [7:0]m_axi_arregion;
output [7:0]m_axi_arqos;
output [1:0]m_axi_aruser;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [23:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rlast;
input [1:0]m_axi_ruser;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [63:32]\^m_axi_araddr ;
wire [3:2]\^m_axi_arburst ;
wire [7:4]\^m_axi_arcache ;
wire [11:0]\^m_axi_arid ;
wire [7:0]\^m_axi_arlen ;
wire [1:1]\^m_axi_arlock ;
wire [5:3]\^m_axi_arprot ;
wire [7:4]\^m_axi_arqos ;
wire [1:0]m_axi_arready;
wire [5:3]\^m_axi_arsize ;
wire [1:0]m_axi_arvalid;
wire [63:32]\^m_axi_awaddr ;
wire [3:2]\^m_axi_awburst ;
wire [7:4]\^m_axi_awcache ;
wire [11:0]\^m_axi_awid ;
wire [15:8]\^m_axi_awlen ;
wire [1:1]\^m_axi_awlock ;
wire [5:3]\^m_axi_awprot ;
wire [7:4]\^m_axi_awqos ;
wire [1:0]m_axi_awready;
wire [5:3]\^m_axi_awsize ;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rready;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[63:32] = \^m_axi_araddr [63:32];
assign m_axi_araddr[31:0] = \^m_axi_araddr [63:32];
assign m_axi_arburst[3:2] = \^m_axi_arburst [3:2];
assign m_axi_arburst[1:0] = \^m_axi_arburst [3:2];
assign m_axi_arcache[7:4] = \^m_axi_arcache [7:4];
assign m_axi_arcache[3:0] = \^m_axi_arcache [7:4];
assign m_axi_arid[23:12] = \^m_axi_arid [11:0];
assign m_axi_arid[11:0] = \^m_axi_arid [11:0];
assign m_axi_arlen[15:8] = \^m_axi_arlen [7:0];
assign m_axi_arlen[7:0] = \^m_axi_arlen [7:0];
assign m_axi_arlock[1] = \^m_axi_arlock [1];
assign m_axi_arlock[0] = \^m_axi_arlock [1];
assign m_axi_arprot[5:3] = \^m_axi_arprot [5:3];
assign m_axi_arprot[2:0] = \^m_axi_arprot [5:3];
assign m_axi_arqos[7:4] = \^m_axi_arqos [7:4];
assign m_axi_arqos[3:0] = \^m_axi_arqos [7:4];
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[5:3] = \^m_axi_arsize [5:3];
assign m_axi_arsize[2:0] = \^m_axi_arsize [5:3];
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[63:32] = \^m_axi_awaddr [63:32];
assign m_axi_awaddr[31:0] = \^m_axi_awaddr [63:32];
assign m_axi_awburst[3:2] = \^m_axi_awburst [3:2];
assign m_axi_awburst[1:0] = \^m_axi_awburst [3:2];
assign m_axi_awcache[7:4] = \^m_axi_awcache [7:4];
assign m_axi_awcache[3:0] = \^m_axi_awcache [7:4];
assign m_axi_awid[23:12] = \^m_axi_awid [11:0];
assign m_axi_awid[11:0] = \^m_axi_awid [11:0];
assign m_axi_awlen[15:8] = \^m_axi_awlen [15:8];
assign m_axi_awlen[7:0] = \^m_axi_awlen [15:8];
assign m_axi_awlock[1] = \^m_axi_awlock [1];
assign m_axi_awlock[0] = \^m_axi_awlock [1];
assign m_axi_awprot[5:3] = \^m_axi_awprot [5:3];
assign m_axi_awprot[2:0] = \^m_axi_awprot [5:3];
assign m_axi_awqos[7:4] = \^m_axi_awqos [7:4];
assign m_axi_awqos[3:0] = \^m_axi_awqos [7:4];
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[5:3] = \^m_axi_awsize [5:3];
assign m_axi_awsize[2:0] = \^m_axi_awsize [5:3];
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[23] = \<const0> ;
assign m_axi_wid[22] = \<const0> ;
assign m_axi_wid[21] = \<const0> ;
assign m_axi_wid[20] = \<const0> ;
assign m_axi_wid[19] = \<const0> ;
assign m_axi_wid[18] = \<const0> ;
assign m_axi_wid[17] = \<const0> ;
assign m_axi_wid[16] = \<const0> ;
assign m_axi_wid[15] = \<const0> ;
assign m_axi_wid[14] = \<const0> ;
assign m_axi_wid[13] = \<const0> ;
assign m_axi_wid[12] = \<const0> ;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[1] = s_axi_wlast;
assign m_axi_wlast[0] = s_axi_wlast;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar \gen_samd.crossbar_samd
(.D({s_axi_awqos,s_axi_awcache,s_axi_awburst,s_axi_awprot,s_axi_awlock,s_axi_awsize,s_axi_awlen,s_axi_awaddr}),
.M_AXI_RREADY(m_axi_rready),
.Q({\^m_axi_awqos ,\^m_axi_awcache ,\^m_axi_awburst ,\^m_axi_awprot ,\^m_axi_awlock ,\^m_axi_awsize ,\^m_axi_awlen ,\^m_axi_awaddr ,\^m_axi_awid }),
.S_AXI_ARREADY(s_axi_arready),
.aclk(aclk),
.aresetn(aresetn),
.\m_axi_arqos[7] ({\^m_axi_arqos ,\^m_axi_arcache ,\^m_axi_arburst ,\^m_axi_arprot ,\^m_axi_arlock ,\^m_axi_arsize ,\^m_axi_arlen ,\^m_axi_araddr ,\^m_axi_arid }),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_arid(s_axi_arid),
.\s_axi_arqos[3] ({s_axi_arqos,s_axi_arcache,s_axi_arburst,s_axi_arprot,s_axi_arlock,s_axi_arsize,s_axi_arlen,s_axi_araddr}),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
(S_AXI_ARREADY,
Q,
\m_axi_arqos[7] ,
m_axi_bready,
M_AXI_RREADY,
m_axi_awvalid,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_awready,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
m_axi_arvalid,
m_axi_wvalid,
s_axi_wready,
m_axi_awready,
m_axi_bvalid,
s_axi_bready,
aclk,
s_axi_arid,
s_axi_awid,
s_axi_awvalid,
m_axi_bid,
m_axi_bresp,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
aresetn,
D,
\s_axi_arqos[3] ,
s_axi_arvalid,
m_axi_rvalid,
s_axi_rready,
m_axi_arready,
s_axi_wvalid,
s_axi_wlast,
m_axi_wready);
output [0:0]S_AXI_ARREADY;
output [68:0]Q;
output [68:0]\m_axi_arqos[7] ;
output [1:0]m_axi_bready;
output [1:0]M_AXI_RREADY;
output [1:0]m_axi_awvalid;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
output [0:0]s_axi_awready;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output [1:0]s_axi_rresp;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]m_axi_arvalid;
output [1:0]m_axi_wvalid;
output [0:0]s_axi_wready;
input [1:0]m_axi_awready;
input [1:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input aclk;
input [11:0]s_axi_arid;
input [11:0]s_axi_awid;
input [0:0]s_axi_awvalid;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [23:0]m_axi_rid;
input [1:0]m_axi_rlast;
input [3:0]m_axi_rresp;
input [63:0]m_axi_rdata;
input aresetn;
input [56:0]D;
input [56:0]\s_axi_arqos[3] ;
input [0:0]s_axi_arvalid;
input [1:0]m_axi_rvalid;
input [0:0]s_axi_rready;
input [1:0]m_axi_arready;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
wire [56:0]D;
wire [1:0]M_AXI_RREADY;
wire [68:0]Q;
wire [0:0]S_AXI_ARREADY;
wire [2:2]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire addr_arbiter_ar_n_2;
wire addr_arbiter_ar_n_3;
wire addr_arbiter_ar_n_4;
wire addr_arbiter_ar_n_5;
wire addr_arbiter_ar_n_6;
wire addr_arbiter_ar_n_7;
wire addr_arbiter_ar_n_80;
wire addr_arbiter_ar_n_81;
wire addr_arbiter_ar_n_82;
wire addr_arbiter_ar_n_84;
wire addr_arbiter_ar_n_85;
wire addr_arbiter_aw_n_10;
wire addr_arbiter_aw_n_11;
wire addr_arbiter_aw_n_12;
wire addr_arbiter_aw_n_13;
wire addr_arbiter_aw_n_14;
wire addr_arbiter_aw_n_15;
wire addr_arbiter_aw_n_16;
wire addr_arbiter_aw_n_2;
wire addr_arbiter_aw_n_20;
wire addr_arbiter_aw_n_21;
wire addr_arbiter_aw_n_3;
wire addr_arbiter_aw_n_7;
wire addr_arbiter_aw_n_8;
wire addr_arbiter_aw_n_9;
wire aresetn;
wire aresetn_d;
wire \gen_decerr_slave.decerr_slave_inst_n_7 ;
wire \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[0].reg_slice_mi_n_4 ;
wire \gen_master_slots[0].reg_slice_mi_n_5 ;
wire \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[1].reg_slice_mi_n_12 ;
wire \gen_master_slots[1].reg_slice_mi_n_20 ;
wire \gen_master_slots[1].reg_slice_mi_n_21 ;
wire \gen_master_slots[1].reg_slice_mi_n_22 ;
wire \gen_master_slots[1].reg_slice_mi_n_23 ;
wire \gen_master_slots[1].reg_slice_mi_n_26 ;
wire \gen_master_slots[1].reg_slice_mi_n_27 ;
wire \gen_master_slots[1].reg_slice_mi_n_5 ;
wire \gen_master_slots[1].reg_slice_mi_n_6 ;
wire \gen_master_slots[1].reg_slice_mi_n_75 ;
wire \gen_master_slots[1].reg_slice_mi_n_76 ;
wire \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[2].reg_slice_mi_n_1 ;
wire \gen_master_slots[2].reg_slice_mi_n_13 ;
wire \gen_master_slots[2].reg_slice_mi_n_19 ;
wire \gen_master_slots[2].reg_slice_mi_n_20 ;
wire \gen_master_slots[2].reg_slice_mi_n_21 ;
wire \gen_master_slots[2].reg_slice_mi_n_22 ;
wire \gen_master_slots[2].reg_slice_mi_n_23 ;
wire \gen_master_slots[2].reg_slice_mi_n_24 ;
wire \gen_master_slots[2].reg_slice_mi_n_25 ;
wire \gen_master_slots[2].reg_slice_mi_n_26 ;
wire \gen_master_slots[2].reg_slice_mi_n_27 ;
wire \gen_master_slots[2].reg_slice_mi_n_28 ;
wire \gen_master_slots[2].reg_slice_mi_n_29 ;
wire \gen_master_slots[2].reg_slice_mi_n_30 ;
wire \gen_master_slots[2].reg_slice_mi_n_31 ;
wire \gen_master_slots[2].reg_slice_mi_n_45 ;
wire \gen_master_slots[2].reg_slice_mi_n_5 ;
wire [2:0]\gen_multi_thread.arbiter_resp_inst/chosen ;
wire [2:0]\gen_multi_thread.arbiter_resp_inst/chosen_1 ;
wire [8:6]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ;
wire \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ;
wire \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ;
wire [68:0]\m_axi_arqos[7] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [1:0]m_ready_d_3;
wire m_valid_i;
wire m_valid_i_2;
wire mi_arready_2;
wire mi_awready_2;
wire mi_bready_2;
wire mi_rready_2;
wire p_14_in;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire [11:0]p_20_in;
wire p_21_in;
wire [11:0]p_24_in;
wire p_32_out;
wire p_34_out;
wire p_38_out;
wire p_54_out;
wire p_56_out;
wire p_60_out;
wire p_74_out;
wire p_76_out;
wire p_80_out;
wire [16:0]r_issuing_cnt;
wire \r_pipe/p_1_in ;
wire \r_pipe/p_1_in_0 ;
wire reset;
wire [11:0]s_axi_arid;
wire [56:0]\s_axi_arqos[3] ;
wire [0:0]s_axi_arvalid;
wire [11:0]s_axi_awid;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire s_axi_rvalid_i;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [1:0]st_aa_artarget_hot;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [34:0]st_mr_bid;
wire [1:0]st_mr_bmesg;
wire [35:0]st_mr_rid;
wire [69:0]st_mr_rmesg;
wire [16:0]w_issuing_cnt;
wire [1:1]write_cs;
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter addr_arbiter_ar
(.D({addr_arbiter_ar_n_2,addr_arbiter_ar_n_3,addr_arbiter_ar_n_4}),
.E(s_axi_rvalid_i),
.Q(p_56_out),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ),
.aresetn_d_reg_0(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ),
.\chosen_reg[0] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ),
.\gen_axi.read_cnt_reg[5] (\gen_decerr_slave.decerr_slave_inst_n_7 ),
.\gen_axi.s_axi_rid_i_reg[11] (aa_mi_artarget_hot),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (addr_arbiter_ar_n_84),
.\gen_master_slots[1].r_issuing_cnt_reg[11] ({addr_arbiter_ar_n_5,addr_arbiter_ar_n_6,addr_arbiter_ar_n_7}),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (addr_arbiter_ar_n_85),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_31 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] (addr_arbiter_ar_n_82),
.\gen_no_arbiter.m_target_hot_i_reg[0]_0 (st_aa_artarget_hot[0]),
.\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_ar_n_80),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_ar_n_81),
.\m_axi_arqos[7] (\m_axi_arqos[7] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[34] (\gen_master_slots[0].reg_slice_mi_n_5 ),
.\m_payload_i_reg[34]_0 (\gen_master_slots[1].reg_slice_mi_n_27 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_75 ),
.mi_arready_2(mi_arready_2),
.p_15_in(p_15_in),
.r_issuing_cnt({r_issuing_cnt[11:8],r_issuing_cnt[3:0]}),
.\s_axi_araddr[25] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ),
.\s_axi_araddr[28] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ),
.\s_axi_araddr[30] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ),
.\s_axi_arqos[3] ({\s_axi_arqos[3] ,s_axi_arid}),
.\s_axi_arready[0] (S_AXI_ARREADY),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rlast_i0(s_axi_rlast_i0),
.s_axi_rready(s_axi_rready),
.st_aa_artarget_hot(st_aa_artarget_hot[1]));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 addr_arbiter_aw
(.D({addr_arbiter_aw_n_7,addr_arbiter_aw_n_8,addr_arbiter_aw_n_9}),
.E(addr_arbiter_aw_n_15),
.Q(Q),
.SR(reset),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ),
.aresetn_d_reg_0(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ),
.\chosen_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ),
.\chosen_reg[1] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ),
.\gen_master_slots[0].w_issuing_cnt_reg[0] (addr_arbiter_aw_n_16),
.\gen_master_slots[0].w_issuing_cnt_reg[3] ({addr_arbiter_aw_n_11,addr_arbiter_aw_n_12,addr_arbiter_aw_n_13}),
.\gen_master_slots[1].w_issuing_cnt_reg[9] (addr_arbiter_aw_n_10),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (addr_arbiter_aw_n_14),
.\gen_no_arbiter.m_target_hot_i_reg[2]_0 (addr_arbiter_aw_n_20),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_ready_d(m_ready_d_3),
.m_ready_d_0(m_ready_d[0]),
.\m_ready_d_reg[0] (addr_arbiter_aw_n_2),
.\m_ready_d_reg[1] (addr_arbiter_aw_n_3),
.\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_21),
.m_valid_i(m_valid_i_2),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_6 ),
.mi_awready_2(mi_awready_2),
.\s_axi_awaddr[20] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ),
.\s_axi_awaddr[26] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ),
.\s_axi_awqos[3] ({D,s_axi_awid}),
.s_axi_bready(s_axi_bready),
.ss_aa_awready(ss_aa_awready),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt({w_issuing_cnt[11:8],w_issuing_cnt[3:0]}));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave \gen_decerr_slave.decerr_slave_inst
(.E(s_axi_rvalid_i),
.Q(p_24_in),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot[2]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axi.s_axi_arready_i_reg_0 (\gen_decerr_slave.decerr_slave_inst_n_7 ),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.\gen_no_arbiter.m_mesg_i_reg[11] (Q[11:0]),
.\gen_no_arbiter.m_mesg_i_reg[51] ({\m_axi_arqos[7] [51:44],\m_axi_arqos[7] [11:0]}),
.\gen_no_arbiter.m_target_hot_i_reg[2] (aa_mi_artarget_hot),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_aw_n_10),
.m_ready_d(m_ready_d_3[1]),
.\m_ready_d_reg[1] (addr_arbiter_aw_n_14),
.mi_arready_2(mi_arready_2),
.mi_awready_2(mi_awready_2),
.mi_bready_2(mi_bready_2),
.mi_rready_2(mi_rready_2),
.p_14_in(p_14_in),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_21_in(p_21_in),
.s_axi_rlast_i0(s_axi_rlast_i0),
.\skid_buffer_reg[46] (p_20_in),
.\storage_data1_reg[0] (\gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].r_issuing_cnt[0]_i_1
(.I0(r_issuing_cnt[0]),
.O(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[0]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ),
.Q(r_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[1]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_4),
.Q(r_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[2]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_3),
.Q(r_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[3]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_2),
.Q(r_issuing_cnt[3]),
.R(reset));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice \gen_master_slots[0].reg_slice_mi
(.D({m_axi_bid[11:0],m_axi_bresp[1:0]}),
.E(\r_pipe/p_1_in_0 ),
.Q(r_issuing_cnt[3:0]),
.aclk(aclk),
.\aresetn_d_reg[1] (\gen_master_slots[2].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[2].reg_slice_mi_n_5 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [0]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [0]),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_5 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ({st_mr_bid[11:0],st_mr_bmesg}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[11:0],p_76_out,st_mr_rmesg[1:0],st_mr_rmesg[34:3]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[0].reg_slice_mi_n_4 ),
.m_axi_bready(m_axi_bready[0]),
.m_axi_bvalid(m_axi_bvalid[0]),
.m_axi_rdata(m_axi_rdata[31:0]),
.m_axi_rid(m_axi_rid[11:0]),
.m_axi_rlast(m_axi_rlast[0]),
.\m_axi_rready[0] (M_AXI_RREADY[0]),
.m_axi_rresp(m_axi_rresp[1:0]),
.m_axi_rvalid(m_axi_rvalid[0]),
.p_1_in(p_1_in),
.p_74_out(p_74_out),
.p_80_out(p_80_out),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].w_issuing_cnt[0]_i_1
(.I0(w_issuing_cnt[0]),
.O(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[0]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ),
.Q(w_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[1]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_13),
.Q(w_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[2]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_12),
.Q(w_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[3]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_11),
.Q(w_issuing_cnt[3]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].r_issuing_cnt[8]_i_1
(.I0(r_issuing_cnt[8]),
.O(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[10]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_6),
.Q(r_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[11]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_5),
.Q(r_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[8]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ),
.Q(r_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[9]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_7),
.Q(r_issuing_cnt[9]),
.R(reset));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 \gen_master_slots[1].reg_slice_mi
(.D({m_axi_bid[23:12],m_axi_bresp[3:2]}),
.Q(w_issuing_cnt[11:8]),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\gen_master_slots[1].reg_slice_mi_n_76 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[2].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_1 (\gen_master_slots[2].reg_slice_mi_n_5 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [2:1]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [2:1]),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].reg_slice_mi_n_75 ),
.\gen_master_slots[1].r_issuing_cnt_reg[11]_0 (r_issuing_cnt[11:8]),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_27 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_master_slots[1].reg_slice_mi_n_6 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_master_slots[1].reg_slice_mi_n_12 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ({st_mr_bid[23],st_mr_bid[21:18],st_mr_bid[16],st_mr_bid[12]}),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_master_slots[1].reg_slice_mi_n_20 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_master_slots[1].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 (\gen_master_slots[1].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 (\gen_master_slots[1].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[23:12],p_56_out,st_mr_rmesg[36],st_mr_rmesg[69],st_mr_rmesg[65],st_mr_rmesg[60],st_mr_rmesg[58:57],st_mr_rmesg[49:46],st_mr_rmesg[44],st_mr_rmesg[42],st_mr_rmesg[38]}),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_master_slots[1].reg_slice_mi_n_5 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[1].reg_slice_mi_n_26 ),
.m_axi_bready(m_axi_bready[1]),
.m_axi_bvalid(m_axi_bvalid[1]),
.m_axi_rdata(m_axi_rdata[63:32]),
.m_axi_rid(m_axi_rid[23:12]),
.m_axi_rlast(m_axi_rlast[1]),
.\m_axi_rready[1] (M_AXI_RREADY[1]),
.m_axi_rresp(m_axi_rresp[3:2]),
.m_axi_rvalid(m_axi_rvalid[1]),
.\m_payload_i_reg[12] ({st_mr_bid[34],st_mr_bid[29],st_mr_bid[27:25],st_mr_bid[10],st_mr_bid[5],st_mr_bid[3:1]}),
.\m_payload_i_reg[1] (st_mr_bmesg),
.\m_payload_i_reg[32] ({st_mr_rmesg[0],st_mr_rmesg[33:31],st_mr_rmesg[29:26],st_mr_rmesg[24],st_mr_rmesg[21:15],st_mr_rmesg[10],st_mr_rmesg[8],st_mr_rmesg[6:4]}),
.p_1_in(p_1_in),
.p_32_out(p_32_out),
.p_38_out(p_38_out),
.p_54_out(p_54_out),
.p_60_out(p_60_out),
.s_axi_bid({s_axi_bid[10],s_axi_bid[5],s_axi_bid[3:1]}),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_rdata({s_axi_rdata[30:28],s_axi_rdata[26:23],s_axi_rdata[21],s_axi_rdata[18:12],s_axi_rdata[7],s_axi_rdata[5],s_axi_rdata[3:1]}),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp[0]));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].w_issuing_cnt[8]_i_1
(.I0(w_issuing_cnt[8]),
.O(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[10]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_8),
.Q(w_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[11]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_7),
.Q(w_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[8]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ),
.Q(w_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[9]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_9),
.Q(w_issuing_cnt[9]),
.R(reset));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[16]
(.C(aclk),
.CE(1'b1),
.D(\gen_master_slots[2].reg_slice_mi_n_45 ),
.Q(r_issuing_cnt[16]),
.R(reset));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 \gen_master_slots[2].reg_slice_mi
(.D(p_24_in),
.E(\r_pipe/p_1_in ),
.Q({st_mr_bid[34],st_mr_bid[29],st_mr_bid[27:25]}),
.S(\gen_master_slots[2].reg_slice_mi_n_20 ),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_master_slots[1].reg_slice_mi_n_76 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [2]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [2]),
.\gen_axi.s_axi_arready_i_reg (addr_arbiter_ar_n_80),
.\gen_axi.s_axi_rid_i_reg[11] (p_20_in),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_4 ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_26 ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_45 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_master_slots[2].reg_slice_mi_n_13 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_master_slots[2].reg_slice_mi_n_19 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_master_slots[2].reg_slice_mi_n_28 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_master_slots[2].reg_slice_mi_n_29 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] (\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_master_slots[2].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_master_slots[2].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_master_slots[2].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_master_slots[2].reg_slice_mi_n_24 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_master_slots[2].reg_slice_mi_n_25 ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_master_slots[2].reg_slice_mi_n_26 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_master_slots[2].reg_slice_mi_n_27 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_rid[35:24],p_34_out}),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_master_slots[2].reg_slice_mi_n_30 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[2].reg_slice_mi_n_31 ),
.\m_payload_i_reg[13] ({st_mr_bid[23],st_mr_bid[21:18],st_mr_bid[16],st_mr_bid[12:11],st_mr_bid[9:6],st_mr_bid[4],st_mr_bid[0]}),
.m_valid_i_reg(\gen_master_slots[2].reg_slice_mi_n_1 ),
.m_valid_i_reg_0(\gen_master_slots[1].reg_slice_mi_n_6 ),
.mi_bready_2(mi_bready_2),
.mi_rready_2(mi_rready_2),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.p_21_in(p_21_in),
.p_32_out(p_32_out),
.p_38_out(p_38_out),
.r_issuing_cnt(r_issuing_cnt[16]),
.s_axi_bid({s_axi_bid[11],s_axi_bid[9:6],s_axi_bid[4],s_axi_bid[0]}),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready),
.s_ready_i_reg(\gen_master_slots[2].reg_slice_mi_n_5 ),
.st_aa_artarget_hot(st_aa_artarget_hot),
.w_issuing_cnt(w_issuing_cnt[16]));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[16]
(.C(aclk),
.CE(1'b1),
.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ),
.Q(w_issuing_cnt[16]),
.R(reset));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor \gen_slave_slots[0].gen_si_read.si_transactor_ar
(.E(\r_pipe/p_1_in_0 ),
.SR(reset),
.aclk(aclk),
.aresetn_d(aresetn_d),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen ),
.\gen_multi_thread.accept_cnt_reg[2]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ),
.\gen_no_arbiter.m_target_hot_i_reg[2]_0 (aa_mi_artarget_hot),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_ar_n_81),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ),
.\gen_no_arbiter.s_ready_i_reg[0]_1 (S_AXI_ARREADY),
.\m_payload_i_reg[34] (\r_pipe/p_1_in ),
.\m_payload_i_reg[46] ({st_mr_rid[11:0],p_76_out,st_mr_rmesg[1],st_mr_rmesg[34],st_mr_rmesg[30],st_mr_rmesg[25],st_mr_rmesg[23:22],st_mr_rmesg[14:11],st_mr_rmesg[9],st_mr_rmesg[7],st_mr_rmesg[3]}),
.\m_payload_i_reg[46]_0 ({st_mr_rid[23:12],p_56_out,st_mr_rmesg[36],st_mr_rmesg[69],st_mr_rmesg[65],st_mr_rmesg[60],st_mr_rmesg[58:57],st_mr_rmesg[49:46],st_mr_rmesg[44],st_mr_rmesg[42],st_mr_rmesg[38]}),
.\m_payload_i_reg[46]_1 ({st_mr_rid[35:24],p_34_out}),
.m_valid_i(m_valid_i),
.p_32_out(p_32_out),
.p_54_out(p_54_out),
.p_74_out(p_74_out),
.\s_axi_araddr[25] (st_aa_artarget_hot[0]),
.\s_axi_araddr[25]_0 (addr_arbiter_ar_n_82),
.\s_axi_araddr[31] ({\s_axi_arqos[3] [31:16],s_axi_arid}),
.s_axi_rdata({s_axi_rdata[31],s_axi_rdata[27],s_axi_rdata[22],s_axi_rdata[20:19],s_axi_rdata[11:8],s_axi_rdata[6],s_axi_rdata[4],s_axi_rdata[0]}),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp[1]),
.s_axi_rvalid(s_axi_rvalid),
.st_aa_artarget_hot(st_aa_artarget_hot[1]));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0 \gen_slave_slots[0].gen_si_write.si_transactor_aw
(.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.S(\gen_master_slots[2].reg_slice_mi_n_20 ),
.SR(reset),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot[2]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 ),
.\gen_master_slots[0].w_issuing_cnt_reg[1] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ),
.\gen_master_slots[1].w_issuing_cnt_reg[10] (\gen_master_slots[1].reg_slice_mi_n_5 ),
.\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_0 (\gen_master_slots[2].reg_slice_mi_n_30 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 (\gen_master_slots[2].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 (\gen_master_slots[2].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 (\gen_master_slots[2].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 (\gen_master_slots[2].reg_slice_mi_n_24 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 (\gen_master_slots[2].reg_slice_mi_n_25 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 (\gen_master_slots[2].reg_slice_mi_n_26 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 (\gen_master_slots[2].reg_slice_mi_n_27 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_aw_n_20),
.\m_payload_i_reg[11] (\gen_master_slots[2].reg_slice_mi_n_28 ),
.\m_payload_i_reg[12] (\gen_master_slots[1].reg_slice_mi_n_23 ),
.\m_payload_i_reg[13] (\gen_master_slots[2].reg_slice_mi_n_29 ),
.\m_payload_i_reg[2] (\gen_master_slots[2].reg_slice_mi_n_13 ),
.\m_payload_i_reg[3] (\gen_master_slots[1].reg_slice_mi_n_12 ),
.\m_payload_i_reg[4] (\gen_master_slots[1].reg_slice_mi_n_20 ),
.\m_payload_i_reg[5] (\gen_master_slots[1].reg_slice_mi_n_21 ),
.\m_payload_i_reg[6] (\gen_master_slots[2].reg_slice_mi_n_19 ),
.\m_payload_i_reg[7] (\gen_master_slots[1].reg_slice_mi_n_22 ),
.\m_ready_d_reg[1] (\gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ),
.\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_14),
.m_valid_i(m_valid_i_2),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_6 ),
.p_38_out(p_38_out),
.p_60_out(p_60_out),
.p_80_out(p_80_out),
.\s_axi_awaddr[31] ({D[31:16],s_axi_awid}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt({w_issuing_cnt[16],w_issuing_cnt[3:0]}));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter \gen_slave_slots[0].gen_si_write.splitter_aw_si
(.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ),
.m_ready_d(m_ready_d),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.ss_aa_awready(ss_aa_awready),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router \gen_slave_slots[0].gen_si_write.wdata_router_w
(.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ),
.SR(reset),
.aclk(aclk),
.\gen_axi.write_cs_reg[1] (\gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d[1]),
.p_14_in(p_14_in),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 splitter_aw_mi
(.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.m_target_hot_i_reg[1] (addr_arbiter_aw_n_3),
.m_ready_d(m_ready_d_3),
.\m_ready_d_reg[0]_0 (addr_arbiter_aw_n_21),
.\m_ready_d_reg[0]_1 (addr_arbiter_aw_n_2));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
(mi_awready_2,
p_14_in,
p_21_in,
p_15_in,
p_17_in,
\gen_axi.write_cs_reg[1]_0 ,
mi_arready_2,
\gen_axi.s_axi_arready_i_reg_0 ,
Q,
\skid_buffer_reg[46] ,
SR,
aclk,
aa_mi_awtarget_hot,
aa_sa_awvalid,
m_ready_d,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
aa_mi_arvalid,
mi_rready_2,
\gen_no_arbiter.m_mesg_i_reg[51] ,
\gen_no_arbiter.m_valid_i_reg ,
mi_bready_2,
\m_ready_d_reg[1] ,
\storage_data1_reg[0] ,
s_axi_rlast_i0,
E,
\gen_no_arbiter.m_mesg_i_reg[11] ,
aresetn_d);
output mi_awready_2;
output p_14_in;
output p_21_in;
output p_15_in;
output p_17_in;
output [0:0]\gen_axi.write_cs_reg[1]_0 ;
output mi_arready_2;
output \gen_axi.s_axi_arready_i_reg_0 ;
output [11:0]Q;
output [11:0]\skid_buffer_reg[46] ;
input [0:0]SR;
input aclk;
input [0:0]aa_mi_awtarget_hot;
input aa_sa_awvalid;
input [0:0]m_ready_d;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[2] ;
input aa_mi_arvalid;
input mi_rready_2;
input [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
input \gen_no_arbiter.m_valid_i_reg ;
input mi_bready_2;
input \m_ready_d_reg[1] ;
input \storage_data1_reg[0] ;
input s_axi_rlast_i0;
input [0:0]E;
input [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
input aresetn_d;
wire [0:0]E;
wire [11:0]Q;
wire [0:0]SR;
wire aa_mi_arvalid;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_axi.read_cnt[4]_i_2_n_0 ;
wire \gen_axi.read_cnt[7]_i_1_n_0 ;
wire \gen_axi.read_cnt[7]_i_3_n_0 ;
wire [0:0]\gen_axi.read_cnt_reg ;
wire [7:1]\gen_axi.read_cnt_reg__0 ;
wire \gen_axi.read_cs[0]_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_reg_0 ;
wire \gen_axi.s_axi_awready_i_i_1_n_0 ;
wire \gen_axi.s_axi_bid_i[11]_i_1_n_0 ;
wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_3_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_4_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_5_n_0 ;
wire \gen_axi.s_axi_wready_i_i_1_n_0 ;
wire \gen_axi.write_cs[0]_i_1_n_0 ;
wire \gen_axi.write_cs[1]_i_1_n_0 ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
wire [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire mi_arready_2;
wire mi_awready_2;
wire mi_bready_2;
wire mi_rready_2;
wire [7:0]p_0_in;
wire p_14_in;
wire p_15_in;
wire p_17_in;
wire p_21_in;
wire s_axi_rlast_i0;
wire [11:0]\skid_buffer_reg[46] ;
wire \storage_data1_reg[0] ;
wire [0:0]write_cs;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h74))
\gen_axi.read_cnt[0]_i_1
(.I0(\gen_axi.read_cnt_reg ),
.I1(p_15_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [12]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9F90))
\gen_axi.read_cnt[1]_i_1
(.I0(\gen_axi.read_cnt_reg ),
.I1(\gen_axi.read_cnt_reg__0 [1]),
.I2(p_15_in),
.I3(\gen_no_arbiter.m_mesg_i_reg[51] [13]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hA9FFA900))
\gen_axi.read_cnt[2]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [2]),
.I1(\gen_axi.read_cnt_reg__0 [1]),
.I2(\gen_axi.read_cnt_reg ),
.I3(p_15_in),
.I4(\gen_no_arbiter.m_mesg_i_reg[51] [14]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'hAAA9FFFFAAA90000))
\gen_axi.read_cnt[3]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [3]),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg ),
.I3(\gen_axi.read_cnt_reg__0 [1]),
.I4(p_15_in),
.I5(\gen_no_arbiter.m_mesg_i_reg[51] [15]),
.O(p_0_in[3]));
LUT6 #(
.INIT(64'hFACAFAFACACACACA))
\gen_axi.read_cnt[4]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [16]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(p_15_in),
.I3(\gen_axi.read_cnt_reg__0 [3]),
.I4(\gen_axi.read_cnt[4]_i_2_n_0 ),
.I5(\gen_axi.read_cnt_reg__0 [4]),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h01))
\gen_axi.read_cnt[4]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [1]),
.I1(\gen_axi.read_cnt_reg ),
.I2(\gen_axi.read_cnt_reg__0 [2]),
.O(\gen_axi.read_cnt[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h3CAA))
\gen_axi.read_cnt[5]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [17]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.I3(p_15_in),
.O(p_0_in[5]));
LUT5 #(
.INIT(32'hEE2E22E2))
\gen_axi.read_cnt[6]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [18]),
.I1(p_15_in),
.I2(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I3(\gen_axi.read_cnt_reg__0 [5]),
.I4(\gen_axi.read_cnt_reg__0 [6]),
.O(p_0_in[6]));
LUT6 #(
.INIT(64'h00800080FF800080))
\gen_axi.read_cnt[7]_i_1
(.I0(mi_arready_2),
.I1(\gen_no_arbiter.m_target_hot_i_reg[2] ),
.I2(aa_mi_arvalid),
.I3(p_15_in),
.I4(mi_rready_2),
.I5(\gen_axi.s_axi_arready_i_reg_0 ),
.O(\gen_axi.read_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B874B8))
\gen_axi.read_cnt[7]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(p_15_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [19]),
.I3(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I4(\gen_axi.read_cnt_reg__0 [5]),
.I5(\gen_axi.read_cnt_reg__0 [6]),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h00000001))
\gen_axi.read_cnt[7]_i_3
(.I0(\gen_axi.read_cnt_reg ),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [4]),
.I4(\gen_axi.read_cnt_reg__0 [3]),
.O(\gen_axi.read_cnt[7]_i_3_n_0 ));
FDRE \gen_axi.read_cnt_reg[0]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(\gen_axi.read_cnt_reg ),
.R(SR));
FDRE \gen_axi.read_cnt_reg[1]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(\gen_axi.read_cnt_reg__0 [1]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[2]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(\gen_axi.read_cnt_reg__0 [2]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[3]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(\gen_axi.read_cnt_reg__0 [3]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[4]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(\gen_axi.read_cnt_reg__0 [4]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[5]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(\gen_axi.read_cnt_reg__0 [5]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[6]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(\gen_axi.read_cnt_reg__0 [6]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[7]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[7]),
.Q(\gen_axi.read_cnt_reg__0 [7]),
.R(SR));
LUT6 #(
.INIT(64'h0080FF80FF80FF80))
\gen_axi.read_cs[0]_i_1
(.I0(mi_arready_2),
.I1(\gen_no_arbiter.m_target_hot_i_reg[2] ),
.I2(aa_mi_arvalid),
.I3(p_15_in),
.I4(mi_rready_2),
.I5(\gen_axi.s_axi_arready_i_reg_0 ),
.O(\gen_axi.read_cs[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.read_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.read_cs[0]_i_1_n_0 ),
.Q(p_15_in),
.R(SR));
LUT6 #(
.INIT(64'h00000000FBBB0000))
\gen_axi.s_axi_arready_i_i_1
(.I0(mi_arready_2),
.I1(p_15_in),
.I2(mi_rready_2),
.I3(\gen_axi.s_axi_arready_i_reg_0 ),
.I4(aresetn_d),
.I5(E),
.O(\gen_axi.s_axi_arready_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0002))
\gen_axi.s_axi_arready_i_i_2
(.I0(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I1(\gen_axi.read_cnt_reg__0 [5]),
.I2(\gen_axi.read_cnt_reg__0 [6]),
.I3(\gen_axi.read_cnt_reg__0 [7]),
.O(\gen_axi.s_axi_arready_i_reg_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready_2),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFF7F70F000F0F))
\gen_axi.s_axi_awready_i_i_1
(.I0(\gen_no_arbiter.m_valid_i_reg ),
.I1(aa_mi_awtarget_hot),
.I2(write_cs),
.I3(mi_bready_2),
.I4(\gen_axi.write_cs_reg[1]_0 ),
.I5(mi_awready_2),
.O(\gen_axi.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_awready_i_i_1_n_0 ),
.Q(mi_awready_2),
.R(SR));
LUT6 #(
.INIT(64'h0000000010000000))
\gen_axi.s_axi_bid_i[11]_i_1
(.I0(write_cs),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(mi_awready_2),
.I3(aa_mi_awtarget_hot),
.I4(aa_sa_awvalid),
.I5(m_ready_d),
.O(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ));
FDRE \gen_axi.s_axi_bid_i_reg[0]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [0]),
.Q(Q[0]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[10]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [10]),
.Q(Q[10]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[11]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [11]),
.Q(Q[11]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[1]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [1]),
.Q(Q[1]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[2]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [2]),
.Q(Q[2]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[3]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [3]),
.Q(Q[3]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[4]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [4]),
.Q(Q[4]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[5]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [5]),
.Q(Q[5]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[6]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [6]),
.Q(Q[6]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[7]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [7]),
.Q(Q[7]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[8]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [8]),
.Q(Q[8]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[9]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [9]),
.Q(Q[9]),
.R(SR));
LUT5 #(
.INIT(32'hEFFFA888))
\gen_axi.s_axi_bvalid_i_i_1
(.I0(\storage_data1_reg[0] ),
.I1(write_cs),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(mi_bready_2),
.I4(p_21_in),
.O(\gen_axi.s_axi_bvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ),
.Q(p_21_in),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[0]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [0]),
.Q(\skid_buffer_reg[46] [0]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[10]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [10]),
.Q(\skid_buffer_reg[46] [10]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[11]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [11]),
.Q(\skid_buffer_reg[46] [11]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[1]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [1]),
.Q(\skid_buffer_reg[46] [1]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[2]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [2]),
.Q(\skid_buffer_reg[46] [2]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[3]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [3]),
.Q(\skid_buffer_reg[46] [3]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[4]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [4]),
.Q(\skid_buffer_reg[46] [4]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[5]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [5]),
.Q(\skid_buffer_reg[46] [5]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[6]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [6]),
.Q(\skid_buffer_reg[46] [6]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[7]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [7]),
.Q(\skid_buffer_reg[46] [7]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[8]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [8]),
.Q(\skid_buffer_reg[46] [8]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[9]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [9]),
.Q(\skid_buffer_reg[46] [9]),
.R(SR));
LUT6 #(
.INIT(64'hBBBBBBBA8888888A))
\gen_axi.s_axi_rlast_i_i_1
(.I0(s_axi_rlast_i0),
.I1(E),
.I2(\gen_axi.s_axi_rlast_i_i_3_n_0 ),
.I3(\gen_axi.s_axi_rlast_i_i_4_n_0 ),
.I4(\gen_axi.s_axi_rlast_i_i_5_n_0 ),
.I5(p_17_in),
.O(\gen_axi.s_axi_rlast_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\gen_axi.s_axi_rlast_i_i_3
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(\gen_axi.read_cnt_reg__0 [6]),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.O(\gen_axi.s_axi_rlast_i_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h7))
\gen_axi.s_axi_rlast_i_i_4
(.I0(p_15_in),
.I1(mi_rready_2),
.O(\gen_axi.s_axi_rlast_i_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_axi.s_axi_rlast_i_i_5
(.I0(\gen_axi.read_cnt_reg__0 [3]),
.I1(\gen_axi.read_cnt_reg__0 [4]),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [2]),
.O(\gen_axi.s_axi_rlast_i_i_5_n_0 ));
FDRE \gen_axi.s_axi_rlast_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_rlast_i_i_1_n_0 ),
.Q(p_17_in),
.R(SR));
LUT5 #(
.INIT(32'h0FFF0202))
\gen_axi.s_axi_wready_i_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(write_cs),
.I3(\storage_data1_reg[0] ),
.I4(p_14_in),
.O(\gen_axi.s_axi_wready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_wready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_wready_i_i_1_n_0 ),
.Q(p_14_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0252))
\gen_axi.write_cs[0]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(write_cs),
.I3(\storage_data1_reg[0] ),
.O(\gen_axi.write_cs[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFF10FA10))
\gen_axi.write_cs[1]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(mi_bready_2),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(write_cs),
.I4(\storage_data1_reg[0] ),
.O(\gen_axi.write_cs[1]_i_1_n_0 ));
FDRE \gen_axi.write_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[0]_i_1_n_0 ),
.Q(write_cs),
.R(SR));
FDRE \gen_axi.write_cs_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[1]_i_1_n_0 ),
.Q(\gen_axi.write_cs_reg[1]_0 ),
.R(SR));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_multi_thread.accept_cnt_reg[2]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_artarget_hot,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
E,
chosen,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
\m_payload_i_reg[34] ,
aresetn_d,
\s_axi_araddr[25] ,
\gen_no_arbiter.s_ready_i_reg[0]_1 ,
\s_axi_araddr[25]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2]_0 ,
\gen_no_arbiter.m_valid_i_reg ,
\s_axi_araddr[31] ,
p_74_out,
s_axi_rready,
p_54_out,
p_32_out,
\m_payload_i_reg[46] ,
\m_payload_i_reg[46]_0 ,
\m_payload_i_reg[46]_1 ,
SR,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \gen_multi_thread.accept_cnt_reg[2]_0 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]st_aa_artarget_hot;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output [0:0]E;
output [2:0]chosen;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output [0:0]s_axi_rresp;
output [11:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[34] ;
input aresetn_d;
input [0:0]\s_axi_araddr[25] ;
input \gen_no_arbiter.s_ready_i_reg[0]_1 ;
input \s_axi_araddr[25]_0 ;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
input \gen_no_arbiter.m_valid_i_reg ;
input [27:0]\s_axi_araddr[31] ;
input p_74_out;
input [0:0]s_axi_rready;
input p_54_out;
input p_32_out;
input [25:0]\m_payload_i_reg[46] ;
input [25:0]\m_payload_i_reg[46]_0 ;
input [12:0]\m_payload_i_reg[46]_1 ;
input [0:0]SR;
input aclk;
wire [0:0]E;
wire [0:0]SR;
wire aclk;
wire [59:0]active_cnt;
wire [57:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1_n_0;
wire aid_match_00_carry_i_2_n_0;
wire aid_match_00_carry_i_3_n_0;
wire aid_match_00_carry_i_4_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_10;
wire aid_match_10_carry_i_1_n_0;
wire aid_match_10_carry_i_2_n_0;
wire aid_match_10_carry_i_3_n_0;
wire aid_match_10_carry_i_4_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_20;
wire aid_match_20_carry_i_1_n_0;
wire aid_match_20_carry_i_2_n_0;
wire aid_match_20_carry_i_3_n_0;
wire aid_match_20_carry_i_4_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_30;
wire aid_match_30_carry_i_1_n_0;
wire aid_match_30_carry_i_2_n_0;
wire aid_match_30_carry_i_3_n_0;
wire aid_match_30_carry_i_4_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_40;
wire aid_match_40_carry_i_1_n_0;
wire aid_match_40_carry_i_2_n_0;
wire aid_match_40_carry_i_3_n_0;
wire aid_match_40_carry_i_4_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_50;
wire aid_match_50_carry_i_1_n_0;
wire aid_match_50_carry_i_2_n_0;
wire aid_match_50_carry_i_3_n_0;
wire aid_match_50_carry_i_4_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_60;
wire aid_match_60_carry_i_1_n_0;
wire aid_match_60_carry_i_2_n_0;
wire aid_match_60_carry_i_3_n_0;
wire aid_match_60_carry_i_4_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_70;
wire aid_match_70_carry_i_1_n_0;
wire aid_match_70_carry_i_2_n_0;
wire aid_match_70_carry_i_3_n_0;
wire aid_match_70_carry_i_4_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aresetn_d;
wire [2:0]chosen;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire \gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.accept_cnt_reg[2]_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg__0 ;
wire \gen_multi_thread.arbiter_resp_inst_n_0 ;
wire \gen_multi_thread.arbiter_resp_inst_n_1 ;
wire \gen_multi_thread.arbiter_resp_inst_n_10 ;
wire \gen_multi_thread.arbiter_resp_inst_n_11 ;
wire \gen_multi_thread.arbiter_resp_inst_n_12 ;
wire \gen_multi_thread.arbiter_resp_inst_n_2 ;
wire \gen_multi_thread.arbiter_resp_inst_n_20 ;
wire \gen_multi_thread.arbiter_resp_inst_n_21 ;
wire \gen_multi_thread.arbiter_resp_inst_n_22 ;
wire \gen_multi_thread.arbiter_resp_inst_n_23 ;
wire \gen_multi_thread.arbiter_resp_inst_n_24 ;
wire \gen_multi_thread.arbiter_resp_inst_n_25 ;
wire \gen_multi_thread.arbiter_resp_inst_n_26 ;
wire \gen_multi_thread.arbiter_resp_inst_n_27 ;
wire \gen_multi_thread.arbiter_resp_inst_n_28 ;
wire \gen_multi_thread.arbiter_resp_inst_n_29 ;
wire \gen_multi_thread.arbiter_resp_inst_n_30 ;
wire \gen_multi_thread.arbiter_resp_inst_n_31 ;
wire \gen_multi_thread.arbiter_resp_inst_n_32 ;
wire \gen_multi_thread.arbiter_resp_inst_n_33 ;
wire \gen_multi_thread.arbiter_resp_inst_n_34 ;
wire \gen_multi_thread.arbiter_resp_inst_n_35 ;
wire \gen_multi_thread.arbiter_resp_inst_n_36 ;
wire \gen_multi_thread.arbiter_resp_inst_n_37 ;
wire \gen_multi_thread.arbiter_resp_inst_n_38 ;
wire \gen_multi_thread.arbiter_resp_inst_n_39 ;
wire \gen_multi_thread.arbiter_resp_inst_n_4 ;
wire \gen_multi_thread.arbiter_resp_inst_n_40 ;
wire \gen_multi_thread.arbiter_resp_inst_n_41 ;
wire \gen_multi_thread.arbiter_resp_inst_n_42 ;
wire \gen_multi_thread.arbiter_resp_inst_n_43 ;
wire \gen_multi_thread.arbiter_resp_inst_n_44 ;
wire \gen_multi_thread.arbiter_resp_inst_n_45 ;
wire \gen_multi_thread.arbiter_resp_inst_n_46 ;
wire \gen_multi_thread.arbiter_resp_inst_n_47 ;
wire \gen_multi_thread.arbiter_resp_inst_n_48 ;
wire \gen_multi_thread.arbiter_resp_inst_n_49 ;
wire \gen_multi_thread.arbiter_resp_inst_n_5 ;
wire \gen_multi_thread.arbiter_resp_inst_n_50 ;
wire \gen_multi_thread.arbiter_resp_inst_n_51 ;
wire \gen_multi_thread.arbiter_resp_inst_n_6 ;
wire \gen_multi_thread.arbiter_resp_inst_n_7 ;
wire \gen_multi_thread.arbiter_resp_inst_n_8 ;
wire \gen_multi_thread.arbiter_resp_inst_n_9 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_13_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[34] ;
wire [25:0]\m_payload_i_reg[46] ;
wire [25:0]\m_payload_i_reg[46]_0 ;
wire [12:0]\m_payload_i_reg[46]_1 ;
wire m_valid_i;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_10_out;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_12_out;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_32_out;
wire p_4_out;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_54_out;
wire p_6_out;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_74_out;
wire p_8_out;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [0:0]\s_axi_araddr[25] ;
wire \s_axi_araddr[25]_0 ;
wire [27:0]\s_axi_araddr[31] ;
wire [11:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [0:0]st_aa_artarget_hot;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1_n_0,aid_match_00_carry_i_2_n_0,aid_match_00_carry_i_3_n_0,aid_match_00_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.O(aid_match_00_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.I1(\s_axi_araddr[31] [7]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.O(aid_match_00_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.O(aid_match_00_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.O(aid_match_00_carry_i_4_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1_n_0,aid_match_10_carry_i_2_n_0,aid_match_10_carry_i_3_n_0,aid_match_10_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1
(.I0(\s_axi_araddr[31] [10]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.I3(\s_axi_araddr[31] [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.I5(\s_axi_araddr[31] [11]),
.O(aid_match_10_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2
(.I0(\s_axi_araddr[31] [7]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.I3(\s_axi_araddr[31] [8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.I5(\s_axi_araddr[31] [6]),
.O(aid_match_10_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3
(.I0(\s_axi_araddr[31] [3]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.I3(\s_axi_araddr[31] [5]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.I5(\s_axi_araddr[31] [4]),
.O(aid_match_10_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4
(.I0(\s_axi_araddr[31] [0]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.I3(\s_axi_araddr[31] [2]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.I5(\s_axi_araddr[31] [1]),
.O(aid_match_10_carry_i_4_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1_n_0,aid_match_20_carry_i_2_n_0,aid_match_20_carry_i_3_n_0,aid_match_20_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.O(aid_match_20_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.I1(\s_axi_araddr[31] [7]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.O(aid_match_20_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.O(aid_match_20_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.O(aid_match_20_carry_i_4_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1_n_0,aid_match_30_carry_i_2_n_0,aid_match_30_carry_i_3_n_0,aid_match_30_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.I1(\s_axi_araddr[31] [10]),
.I2(\s_axi_araddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.I4(\s_axi_araddr[31] [9]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.O(aid_match_30_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.O(aid_match_30_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.O(aid_match_30_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.O(aid_match_30_carry_i_4_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1_n_0,aid_match_40_carry_i_2_n_0,aid_match_40_carry_i_3_n_0,aid_match_40_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.O(aid_match_40_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.O(aid_match_40_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3
(.I0(\s_axi_araddr[31] [5]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.I2(\s_axi_araddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.I5(\s_axi_araddr[31] [4]),
.O(aid_match_40_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.O(aid_match_40_carry_i_4_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1_n_0,aid_match_50_carry_i_2_n_0,aid_match_50_carry_i_3_n_0,aid_match_50_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.O(aid_match_50_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.O(aid_match_50_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.O(aid_match_50_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.O(aid_match_50_carry_i_4_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1_n_0,aid_match_60_carry_i_2_n_0,aid_match_60_carry_i_3_n_0,aid_match_60_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.I4(\s_axi_araddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.O(aid_match_60_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.O(aid_match_60_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.O(aid_match_60_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.O(aid_match_60_carry_i_4_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1_n_0,aid_match_70_carry_i_2_n_0,aid_match_70_carry_i_3_n_0,aid_match_70_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.I1(\s_axi_araddr[31] [10]),
.I2(\s_axi_araddr[31] [9]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.O(aid_match_70_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.O(aid_match_70_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.O(aid_match_70_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.O(aid_match_70_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_2 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_1 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [3]),
.R(SR));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 \gen_multi_thread.arbiter_resp_inst
(.CO(p_8_out),
.D({\gen_multi_thread.arbiter_resp_inst_n_0 ,\gen_multi_thread.arbiter_resp_inst_n_1 ,\gen_multi_thread.arbiter_resp_inst_n_2 }),
.E(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 ),
.S({\gen_multi_thread.arbiter_resp_inst_n_20 ,\gen_multi_thread.arbiter_resp_inst_n_21 ,\gen_multi_thread.arbiter_resp_inst_n_22 ,\gen_multi_thread.arbiter_resp_inst_n_23 }),
.SR(SR),
.aclk(aclk),
.\chosen_reg[1]_0 (chosen[1]),
.cmd_push_0(cmd_push_0),
.cmd_push_3(cmd_push_3),
.\gen_multi_thread.accept_cnt_reg[2] (\gen_multi_thread.accept_cnt_reg[2]_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.arbiter_resp_inst_n_12 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.arbiter_resp_inst_n_11 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] (p_14_out),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] (\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.arbiter_resp_inst_n_10 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ({\gen_multi_thread.arbiter_resp_inst_n_24 ,\gen_multi_thread.arbiter_resp_inst_n_25 ,\gen_multi_thread.arbiter_resp_inst_n_26 ,\gen_multi_thread.arbiter_resp_inst_n_27 }),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] (\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] (\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.arbiter_resp_inst_n_9 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ({\gen_multi_thread.arbiter_resp_inst_n_28 ,\gen_multi_thread.arbiter_resp_inst_n_29 ,\gen_multi_thread.arbiter_resp_inst_n_30 ,\gen_multi_thread.arbiter_resp_inst_n_31 }),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] (\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] (\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ({\gen_multi_thread.arbiter_resp_inst_n_32 ,\gen_multi_thread.arbiter_resp_inst_n_33 ,\gen_multi_thread.arbiter_resp_inst_n_34 ,\gen_multi_thread.arbiter_resp_inst_n_35 }),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] (\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.arbiter_resp_inst_n_8 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ({\gen_multi_thread.arbiter_resp_inst_n_36 ,\gen_multi_thread.arbiter_resp_inst_n_37 ,\gen_multi_thread.arbiter_resp_inst_n_38 ,\gen_multi_thread.arbiter_resp_inst_n_39 }),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] (\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] (\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] (\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.arbiter_resp_inst_n_7 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ({\gen_multi_thread.arbiter_resp_inst_n_40 ,\gen_multi_thread.arbiter_resp_inst_n_41 ,\gen_multi_thread.arbiter_resp_inst_n_42 ,\gen_multi_thread.arbiter_resp_inst_n_43 }),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] (\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.arbiter_resp_inst_n_6 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ({\gen_multi_thread.arbiter_resp_inst_n_44 ,\gen_multi_thread.arbiter_resp_inst_n_45 ,\gen_multi_thread.arbiter_resp_inst_n_46 ,\gen_multi_thread.arbiter_resp_inst_n_47 }),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] (\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] (\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.arbiter_resp_inst_n_5 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({\gen_multi_thread.arbiter_resp_inst_n_48 ,\gen_multi_thread.arbiter_resp_inst_n_49 ,\gen_multi_thread.arbiter_resp_inst_n_50 ,\gen_multi_thread.arbiter_resp_inst_n_51 }),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] (\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] (p_0_out),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] (\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_1 (\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_2 (\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_3 (\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_4 (\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_5 (\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[0]_0 (chosen[0]),
.\m_payload_i_reg[34] (chosen[2]),
.\m_payload_i_reg[34]_0 (\m_payload_i_reg[34] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[46]_0 (\m_payload_i_reg[46]_0 ),
.\m_payload_i_reg[46]_1 (\m_payload_i_reg[46]_1 ),
.p_32_out(p_32_out),
.p_54_out(p_54_out),
.p_74_out(p_74_out),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0
(.I0(active_cnt[2]),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(cmd_push_0),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0
(.I0(active_cnt[3]),
.I1(active_cnt[2]),
.I2(cmd_push_0),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.R(SR));
LUT6 #(
.INIT(64'h00000F0088888888))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0
(.I0(aid_match_00),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.O(cmd_push_0));
LUT6 #(
.INIT(64'hAAAAAAA8FFFFFFFF))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0
(.I0(aid_match_30),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(st_aa_artarget_hot),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0
(.I0(active_cnt[10]),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0
(.I0(active_cnt[11]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF55FF55CF55FF55))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'h3B080808))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I3(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I4(aid_match_10),
.O(cmd_push_1));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT4 #(
.INIT(16'h0080))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(st_aa_artarget_hot),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0
(.I0(active_cnt[18]),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0
(.I0(active_cnt[19]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.O(cmd_push_2));
LUT6 #(
.INIT(64'hFF77FF77F077FF77))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0
(.I0(aid_match_20),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(st_aa_artarget_hot),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[17]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0
(.I0(active_cnt[26]),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(cmd_push_3),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0
(.I0(active_cnt[27]),
.I1(active_cnt[26]),
.I2(cmd_push_3),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10
(.I0(active_cnt[2]),
.I1(active_cnt[3]),
.I2(active_cnt[1]),
.I3(active_cnt[0]),
.I4(aid_match_00),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11
(.I0(aid_match_60),
.I1(active_cnt[49]),
.I2(active_cnt[48]),
.I3(active_cnt[50]),
.I4(active_cnt[51]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(aid_match_20),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0A0A0A0A3A0A0A0A))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(cmd_push_3));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.I1(active_cnt[26]),
.I2(active_cnt[27]),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(aid_match_30),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(aid_match_10),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0
(.I0(aid_match_70),
.I1(active_cnt[57]),
.I2(active_cnt[56]),
.I3(active_cnt[58]),
.I4(active_cnt[59]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0
(.I0(aid_match_40),
.I1(active_cnt[33]),
.I2(active_cnt[32]),
.I3(active_cnt[34]),
.I4(active_cnt[35]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(aid_match_50),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(st_aa_artarget_hot),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[25]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0
(.I0(active_cnt[34]),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0
(.I0(active_cnt[35]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0
(.I0(active_cnt[35]),
.I1(active_cnt[34]),
.I2(active_cnt[32]),
.I3(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'h5545FFFFFFEFFFFF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I5(aid_match_40),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(st_aa_artarget_hot),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[33]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0
(.I0(active_cnt[42]),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0
(.I0(active_cnt[43]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.O(cmd_push_5));
LUT6 #(
.INIT(64'hFF77FF77F077FF77))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0
(.I0(aid_match_50),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAABFFFFFFFF))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'h80))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(st_aa_artarget_hot),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[41]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0
(.I0(active_cnt[50]),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0
(.I0(active_cnt[51]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0
(.I0(active_cnt[51]),
.I1(active_cnt[50]),
.I2(active_cnt[48]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.O(cmd_push_6));
LUT6 #(
.INIT(64'h5555555545555555))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000000))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(active_cnt[51]),
.I2(active_cnt[50]),
.I3(active_cnt[48]),
.I4(active_cnt[49]),
.I5(aid_match_60),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I1(active_cnt[51]),
.I2(active_cnt[50]),
.I3(active_cnt[48]),
.I4(active_cnt[49]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(st_aa_artarget_hot),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[49]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0
(.I0(active_cnt[58]),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0
(.I0(active_cnt[59]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0
(.I0(active_cnt[59]),
.I1(active_cnt[58]),
.I2(active_cnt[56]),
.I3(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'h00000010))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0
(.I0(\s_axi_araddr[31] [17]),
.I1(\s_axi_araddr[31] [20]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ),
.O(st_aa_artarget_hot));
LUT6 #(
.INIT(64'h0000000100000000))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0
(.I0(\s_axi_araddr[31] [13]),
.I1(\s_axi_araddr[31] [22]),
.I2(\s_axi_araddr[31] [15]),
.I3(\s_axi_araddr[31] [12]),
.I4(\s_axi_araddr[31] [14]),
.I5(\s_axi_araddr[31] [26]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3
(.I0(\s_axi_araddr[31] [25]),
.I1(\s_axi_araddr[31] [27]),
.I2(\s_axi_araddr[31] [23]),
.I3(\s_axi_araddr[31] [24]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4
(.I0(\s_axi_araddr[31] [18]),
.I1(\s_axi_araddr[31] [19]),
.I2(\s_axi_araddr[31] [16]),
.I3(\s_axi_araddr[31] [21]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.O(cmd_push_7));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2
(.I0(\s_axi_araddr[25]_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFF5555CFFF5555))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(st_aa_artarget_hot),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[57]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT4 #(
.INIT(16'h7F40))
\gen_no_arbiter.m_target_hot_i[2]_i_1__0
(.I0(\s_axi_araddr[25]_0 ),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(\gen_no_arbiter.m_target_hot_i_reg[2]_0 ),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT5 #(
.INIT(32'hDDDDFFFD))
\gen_no_arbiter.s_ready_i[0]_i_10__0
(.I0(aid_match_30),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[25]),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ));
LUT5 #(
.INIT(32'h88880008))
\gen_no_arbiter.s_ready_i[0]_i_11
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[49]),
.I4(active_target[48]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ));
LUT5 #(
.INIT(32'h22220002))
\gen_no_arbiter.s_ready_i[0]_i_12__0
(.I0(aid_match_50),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[41]),
.I4(active_target[40]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ));
LUT6 #(
.INIT(64'h40FF404040404040))
\gen_no_arbiter.s_ready_i[0]_i_13
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I1(aid_match_10),
.I2(active_target[8]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I4(aid_match_00),
.I5(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_13_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_14__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I1(aid_match_50),
.I2(active_target[40]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I4(aid_match_10),
.I5(active_target[8]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ));
LUT6 #(
.INIT(64'h1010101010FF1010))
\gen_no_arbiter.s_ready_i[0]_i_15__0
(.I0(active_target[16]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I2(aid_match_20),
.I3(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I4(aid_match_30),
.I5(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ));
LUT6 #(
.INIT(64'h00000000AAAAAAA8))
\gen_no_arbiter.s_ready_i[0]_i_16__0
(.I0(aid_match_00),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(active_cnt[3]),
.I4(active_cnt[2]),
.I5(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ));
LUT6 #(
.INIT(64'h08080808FF080808))
\gen_no_arbiter.s_ready_i[0]_i_17__0
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(active_target[48]),
.I3(aid_match_40),
.I4(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I5(active_target[32]),
.O(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ));
LUT6 #(
.INIT(64'h00000000F1000000))
\gen_no_arbiter.s_ready_i[0]_i_18__0
(.I0(active_target[33]),
.I1(\s_axi_araddr[25] ),
.I2(active_target[32]),
.I3(aid_match_40),
.I4(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I5(st_aa_artarget_hot),
.O(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_19__0
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(active_target[49]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(aid_match_20),
.I5(active_target[17]),
.O(\gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1__0
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h7F007F7F7F7F7F7F))
\gen_no_arbiter.s_ready_i[0]_i_20__0
(.I0(active_target[33]),
.I1(aid_match_40),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I4(aid_match_50),
.I5(active_target[41]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_21__0
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[57]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I4(aid_match_30),
.I5(active_target[25]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ));
LUT6 #(
.INIT(64'h40FF404040404040))
\gen_no_arbiter.s_ready_i[0]_i_22__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I1(aid_match_10),
.I2(active_target[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I4(aid_match_00),
.I5(active_target[1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT4 #(
.INIT(16'hFFFD))
\gen_no_arbiter.s_ready_i[0]_i_24__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [3]),
.I1(\gen_multi_thread.accept_cnt_reg__0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg__0 [1]),
.I3(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h00000000000002F2))
\gen_no_arbiter.s_ready_i[0]_i_2__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ),
.I2(st_aa_artarget_hot),
.I3(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ),
.I5(\gen_no_arbiter.m_valid_i_reg ),
.O(m_valid_i));
LUT6 #(
.INIT(64'h0000000000000E00))
\gen_no_arbiter.s_ready_i[0]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ),
.I1(\s_axi_araddr[25] ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0000111F))
\gen_no_arbiter.s_ready_i[0]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I1(active_target[9]),
.I2(active_target[1]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I4(\s_axi_araddr[25] ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_13_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEEEF))
\gen_no_arbiter.s_ready_i[0]_i_5__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I3(active_target[56]),
.I4(\gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEFAAAAAAAA))
\gen_no_arbiter.s_ready_i[0]_i_6__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ),
.I5(\s_axi_araddr[25]_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hF7F7F700F7F7F7F7))
\gen_no_arbiter.s_ready_i[0]_i_8
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[57]),
.I3(active_target[17]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I5(aid_match_20),
.O(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_9
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[56]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(aid_match_20),
.I5(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_48 ,\gen_multi_thread.arbiter_resp_inst_n_49 ,\gen_multi_thread.arbiter_resp_inst_n_50 ,\gen_multi_thread.arbiter_resp_inst_n_51 }));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_28 ,\gen_multi_thread.arbiter_resp_inst_n_29 ,\gen_multi_thread.arbiter_resp_inst_n_30 ,\gen_multi_thread.arbiter_resp_inst_n_31 }));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_24 ,\gen_multi_thread.arbiter_resp_inst_n_25 ,\gen_multi_thread.arbiter_resp_inst_n_26 ,\gen_multi_thread.arbiter_resp_inst_n_27 }));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_20 ,\gen_multi_thread.arbiter_resp_inst_n_21 ,\gen_multi_thread.arbiter_resp_inst_n_22 ,\gen_multi_thread.arbiter_resp_inst_n_23 }));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_44 ,\gen_multi_thread.arbiter_resp_inst_n_45 ,\gen_multi_thread.arbiter_resp_inst_n_46 ,\gen_multi_thread.arbiter_resp_inst_n_47 }));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_40 ,\gen_multi_thread.arbiter_resp_inst_n_41 ,\gen_multi_thread.arbiter_resp_inst_n_42 ,\gen_multi_thread.arbiter_resp_inst_n_43 }));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_36 ,\gen_multi_thread.arbiter_resp_inst_n_37 ,\gen_multi_thread.arbiter_resp_inst_n_38 ,\gen_multi_thread.arbiter_resp_inst_n_39 }));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_32 ,\gen_multi_thread.arbiter_resp_inst_n_33 ,\gen_multi_thread.arbiter_resp_inst_n_34 ,\gen_multi_thread.arbiter_resp_inst_n_35 }));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
chosen,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_awtarget_enc,
D,
SR,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ,
Q,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
s_axi_bvalid,
\gen_master_slots[1].w_issuing_cnt_reg[8] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ,
S,
aresetn_d,
st_aa_awtarget_hot,
\m_ready_d_reg[1] ,
p_80_out,
s_axi_bready,
aa_mi_awtarget_hot,
\gen_master_slots[1].w_issuing_cnt_reg[10] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ,
\s_axi_awaddr[31] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[2] ,
\m_payload_i_reg[4] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[5] ,
\m_payload_i_reg[7] ,
\m_payload_i_reg[12] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[13] ,
aa_sa_awvalid,
s_axi_awvalid,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
m_valid_i_reg,
p_38_out,
p_60_out,
w_issuing_cnt,
\m_ready_d_reg[1]_0 ,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \gen_master_slots[0].w_issuing_cnt_reg[1] ;
output [2:0]chosen;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]st_aa_awtarget_enc;
output [0:0]D;
output [0:0]SR;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ;
output [2:0]Q;
output [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output [0:0]s_axi_bvalid;
output \gen_master_slots[1].w_issuing_cnt_reg[8] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ;
input [0:0]S;
input aresetn_d;
input [0:0]st_aa_awtarget_hot;
input \m_ready_d_reg[1] ;
input p_80_out;
input [0:0]s_axi_bready;
input [0:0]aa_mi_awtarget_hot;
input \gen_master_slots[1].w_issuing_cnt_reg[10] ;
input \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
input [27:0]\s_axi_awaddr[31] ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[2] ;
input \m_payload_i_reg[4] ;
input \m_payload_i_reg[6] ;
input \m_payload_i_reg[5] ;
input \m_payload_i_reg[7] ;
input \m_payload_i_reg[12] ;
input \m_payload_i_reg[11] ;
input \m_payload_i_reg[13] ;
input aa_sa_awvalid;
input [0:0]s_axi_awvalid;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input m_valid_i_reg;
input p_38_out;
input p_60_out;
input [4:0]w_issuing_cnt;
input \m_ready_d_reg[1]_0 ;
input aclk;
wire [0:0]D;
wire [2:0]Q;
wire [0:0]S;
wire [0:0]SR;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire [59:0]active_cnt;
wire [57:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1__0_n_0;
wire aid_match_00_carry_i_2__0_n_0;
wire aid_match_00_carry_i_3__0_n_0;
wire aid_match_00_carry_i_4__0_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_10;
wire aid_match_10_carry_i_1__0_n_0;
wire aid_match_10_carry_i_2__0_n_0;
wire aid_match_10_carry_i_3__0_n_0;
wire aid_match_10_carry_i_4__0_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_20;
wire aid_match_20_carry_i_1__0_n_0;
wire aid_match_20_carry_i_2__0_n_0;
wire aid_match_20_carry_i_3__0_n_0;
wire aid_match_20_carry_i_4__0_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_30;
wire aid_match_30_carry_i_1__0_n_0;
wire aid_match_30_carry_i_2__0_n_0;
wire aid_match_30_carry_i_3__0_n_0;
wire aid_match_30_carry_i_4__0_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_40;
wire aid_match_40_carry_i_1__0_n_0;
wire aid_match_40_carry_i_2__0_n_0;
wire aid_match_40_carry_i_3__0_n_0;
wire aid_match_40_carry_i_4__0_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_50;
wire aid_match_50_carry_i_1__0_n_0;
wire aid_match_50_carry_i_2__0_n_0;
wire aid_match_50_carry_i_3__0_n_0;
wire aid_match_50_carry_i_4__0_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_60;
wire aid_match_60_carry_i_1__0_n_0;
wire aid_match_60_carry_i_2__0_n_0;
wire aid_match_60_carry_i_3__0_n_0;
wire aid_match_60_carry_i_4__0_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_70;
wire aid_match_70_carry_i_1__0_n_0;
wire aid_match_70_carry_i_2__0_n_0;
wire aid_match_70_carry_i_3__0_n_0;
wire aid_match_70_carry_i_4__0_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aresetn_d;
wire [2:0]chosen;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire \gen_master_slots[0].w_issuing_cnt_reg[1] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[10] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
wire \gen_multi_thread.accept_cnt[0]_i_1_n_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg ;
wire \gen_multi_thread.arbiter_resp_inst_n_10 ;
wire \gen_multi_thread.arbiter_resp_inst_n_11 ;
wire \gen_multi_thread.arbiter_resp_inst_n_12 ;
wire \gen_multi_thread.arbiter_resp_inst_n_13 ;
wire \gen_multi_thread.arbiter_resp_inst_n_14 ;
wire \gen_multi_thread.arbiter_resp_inst_n_15 ;
wire \gen_multi_thread.arbiter_resp_inst_n_16 ;
wire \gen_multi_thread.arbiter_resp_inst_n_17 ;
wire \gen_multi_thread.arbiter_resp_inst_n_2 ;
wire \gen_multi_thread.arbiter_resp_inst_n_3 ;
wire \gen_multi_thread.arbiter_resp_inst_n_4 ;
wire \gen_multi_thread.arbiter_resp_inst_n_9 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i[0]_i_10_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_16_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_19_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_23_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_28_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire i__carry_i_1_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4_n_0;
wire \m_payload_i_reg[11] ;
wire \m_payload_i_reg[12] ;
wire \m_payload_i_reg[13] ;
wire \m_payload_i_reg[2] ;
wire \m_payload_i_reg[3] ;
wire \m_payload_i_reg[4] ;
wire \m_payload_i_reg[5] ;
wire \m_payload_i_reg[6] ;
wire \m_payload_i_reg[7] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_10_out;
wire p_10_out_carry_i_1_n_0;
wire p_10_out_carry_i_3_n_0;
wire p_10_out_carry_i_4_n_0;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_12_out;
wire p_12_out_carry_i_1_n_0;
wire p_12_out_carry_i_3_n_0;
wire p_12_out_carry_i_4_n_0;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_i_1_n_0;
wire p_14_out_carry_i_3_n_0;
wire p_14_out_carry_i_4_n_0;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_i_1_n_0;
wire p_2_out_carry_i_3_n_0;
wire p_2_out_carry_i_4_n_0;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_38_out;
wire p_4_out;
wire p_4_out_carry_i_1_n_0;
wire p_4_out_carry_i_3_n_0;
wire p_4_out_carry_i_4_n_0;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_60_out;
wire p_6_out;
wire p_6_out_carry_i_1_n_0;
wire p_6_out_carry_i_3_n_0;
wire p_6_out_carry_i_4_n_0;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_80_out;
wire p_8_out;
wire p_8_out_carry_i_1_n_0;
wire p_8_out_carry_i_3_n_0;
wire p_8_out_carry_i_4_n_0;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [27:0]\s_axi_awaddr[31] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [4:0]w_issuing_cnt;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1__0_n_0,aid_match_00_carry_i_2__0_n_0,aid_match_00_carry_i_3__0_n_0,aid_match_00_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.O(aid_match_00_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2__0
(.I0(Q[0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [7]),
.I3(Q[1]),
.I4(\s_axi_awaddr[31] [8]),
.I5(Q[2]),
.O(aid_match_00_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I4(\s_axi_awaddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.O(aid_match_00_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.O(aid_match_00_carry_i_4__0_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1__0_n_0,aid_match_10_carry_i_2__0_n_0,aid_match_10_carry_i_3__0_n_0,aid_match_10_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1__0
(.I0(\s_axi_awaddr[31] [9]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I3(\s_axi_awaddr[31] [10]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\s_axi_awaddr[31] [11]),
.O(aid_match_10_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2__0
(.I0(\s_axi_awaddr[31] [6]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [2]),
.I3(\s_axi_awaddr[31] [8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [1]),
.I5(\s_axi_awaddr[31] [7]),
.O(aid_match_10_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3__0
(.I0(\s_axi_awaddr[31] [3]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I3(\s_axi_awaddr[31] [4]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\s_axi_awaddr[31] [5]),
.O(aid_match_10_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4__0
(.I0(\s_axi_awaddr[31] [0]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I3(\s_axi_awaddr[31] [2]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I5(\s_axi_awaddr[31] [1]),
.O(aid_match_10_carry_i_4__0_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1__0_n_0,aid_match_20_carry_i_2__0_n_0,aid_match_20_carry_i_3__0_n_0,aid_match_20_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.O(aid_match_20_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]),
.I4(\s_axi_awaddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]),
.O(aid_match_20_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.O(aid_match_20_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.O(aid_match_20_carry_i_4__0_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1__0_n_0,aid_match_30_carry_i_2__0_n_0,aid_match_30_carry_i_3__0_n_0,aid_match_30_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I1(\s_axi_awaddr[31] [10]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [9]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.O(aid_match_30_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [1]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [2]),
.O(aid_match_30_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I1(\s_axi_awaddr[31] [3]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.O(aid_match_30_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.O(aid_match_30_carry_i_4__0_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1__0_n_0,aid_match_40_carry_i_2__0_n_0,aid_match_40_carry_i_3__0_n_0,aid_match_40_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.O(aid_match_40_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [6]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]),
.O(aid_match_40_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I4(\s_axi_awaddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.O(aid_match_40_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.O(aid_match_40_carry_i_4__0_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1__0_n_0,aid_match_50_carry_i_2__0_n_0,aid_match_50_carry_i_3__0_n_0,aid_match_50_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I1(\s_axi_awaddr[31] [10]),
.I2(\s_axi_awaddr[31] [9]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.O(aid_match_50_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]),
.I4(\s_axi_awaddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]),
.O(aid_match_50_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.O(aid_match_50_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.O(aid_match_50_carry_i_4__0_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1__0_n_0,aid_match_60_carry_i_2__0_n_0,aid_match_60_carry_i_3__0_n_0,aid_match_60_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.O(aid_match_60_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]),
.I4(\s_axi_awaddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]),
.O(aid_match_60_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I1(\s_axi_awaddr[31] [3]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.O(aid_match_60_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.O(aid_match_60_carry_i_4__0_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1__0_n_0,aid_match_70_carry_i_2__0_n_0,aid_match_70_carry_i_3__0_n_0,aid_match_70_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.O(aid_match_70_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [6]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]),
.O(aid_match_70_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.O(aid_match_70_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.O(aid_match_70_carry_i_4__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.Q(\gen_multi_thread.accept_cnt_reg [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_3 ),
.Q(\gen_multi_thread.accept_cnt_reg [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_2 ),
.Q(\gen_multi_thread.accept_cnt_reg [3]),
.R(SR));
zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp \gen_multi_thread.arbiter_resp_inst
(.CO(p_0_out),
.D({\gen_multi_thread.arbiter_resp_inst_n_2 ,\gen_multi_thread.arbiter_resp_inst_n_3 ,\gen_multi_thread.arbiter_resp_inst_n_4 }),
.E(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.Q(\gen_multi_thread.accept_cnt_reg ),
.SR(SR),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\chosen_reg[0]_0 (chosen[0]),
.\chosen_reg[1]_0 (chosen[1]),
.cmd_push_0(cmd_push_0),
.cmd_push_3(cmd_push_3),
.\gen_master_slots[0].w_issuing_cnt_reg[1] (\gen_master_slots[0].w_issuing_cnt_reg[1] ),
.\gen_master_slots[1].w_issuing_cnt_reg[10] (\gen_master_slots[1].w_issuing_cnt_reg[10] ),
.\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_master_slots[1].w_issuing_cnt_reg[8] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (chosen[2]),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_0 (\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_1 (\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ),
.\gen_multi_thread.accept_cnt_reg[0] (\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.arbiter_resp_inst_n_17 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.arbiter_resp_inst_n_16 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] (p_14_out),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.arbiter_resp_inst_n_15 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] (\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.arbiter_resp_inst_n_14 ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] (\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] (\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.arbiter_resp_inst_n_13 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] (p_8_out),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] (\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.arbiter_resp_inst_n_12 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 (\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 (\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] (\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.arbiter_resp_inst_n_11 ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.arbiter_resp_inst_n_10 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] (\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] (\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] (\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.\m_ready_d_reg[1] (\m_ready_d_reg[1] ),
.\m_ready_d_reg[1]_0 (\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.\m_ready_d_reg[1]_1 (\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.\m_ready_d_reg[1]_2 (\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.\m_ready_d_reg[1]_3 (\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.\m_ready_d_reg[1]_4 (\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.\m_ready_d_reg[1]_5 (\m_ready_d_reg[1]_0 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(m_valid_i_reg),
.p_38_out(p_38_out),
.p_60_out(p_60_out),
.p_80_out(p_80_out),
.\s_axi_awaddr[26] (st_aa_awtarget_enc),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt(w_issuing_cnt));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1
(.I0(active_cnt[2]),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(cmd_push_0),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2
(.I0(active_cnt[3]),
.I1(active_cnt[2]),
.I2(cmd_push_0),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [6]),
.Q(Q[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [7]),
.Q(Q[1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [8]),
.Q(Q[2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.R(SR));
LUT6 #(
.INIT(64'h0500050035300500))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(aid_match_00),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(cmd_push_0));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2
(.I0(aid_match_40),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(aid_match_50),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(st_aa_awtarget_enc),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(D),
.Q(active_target[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1
(.I0(active_cnt[10]),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2
(.I0(active_cnt[11]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFBBFFBBF0BBFFBB))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3
(.I0(\m_ready_d_reg[1] ),
.I1(aid_match_10),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.R(SR));
LUT5 #(
.INIT(32'h08083B08))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(aid_match_10),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_1));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT4 #(
.INIT(16'h0010))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(st_aa_awtarget_enc),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(D),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1
(.I0(active_cnt[18]),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2
(.I0(active_cnt[19]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.O(cmd_push_2));
LUT6 #(
.INIT(64'hFFDDFFDDF0DDFFDD))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2
(.I0(aid_match_20),
.I1(\m_ready_d_reg[1] ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(st_aa_awtarget_enc),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(D),
.Q(active_target[17]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1
(.I0(active_cnt[26]),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(cmd_push_3),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2
(.I0(active_cnt[27]),
.I1(active_cnt[26]),
.I2(cmd_push_3),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.R(SR));
LUT6 #(
.INIT(64'h004400440F440044))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(aid_match_30),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(cmd_push_3));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT3 #(
.INIT(8'h02))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(aid_match_20),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8
(.I0(aid_match_10),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9
(.I0(aid_match_30),
.I1(active_cnt[26]),
.I2(active_cnt[27]),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(st_aa_awtarget_enc),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(D),
.Q(active_target[25]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1
(.I0(active_cnt[34]),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2
(.I0(active_cnt[35]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'hAFAFAFAFAFACAFAF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4
(.I0(aid_match_00),
.I1(active_cnt[2]),
.I2(active_cnt[3]),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(st_aa_awtarget_enc),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(D),
.Q(active_target[33]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1
(.I0(active_cnt[42]),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2
(.I0(active_cnt[43]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.O(cmd_push_5));
LUT6 #(
.INIT(64'hFAFAFFFFFACAFFCF))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ),
.I4(aid_match_50),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(st_aa_awtarget_enc),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(D),
.Q(active_target[41]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1
(.I0(active_cnt[50]),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2
(.I0(active_cnt[51]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3
(.I0(active_cnt[51]),
.I1(active_cnt[50]),
.I2(active_cnt[48]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.O(cmd_push_6));
LUT6 #(
.INIT(64'hEEEEEEEEEEE0EEEE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3
(.I0(aid_match_60),
.I1(active_cnt[49]),
.I2(active_cnt[48]),
.I3(active_cnt[50]),
.I4(active_cnt[51]),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(active_cnt[51]),
.I3(active_cnt[50]),
.I4(active_cnt[48]),
.I5(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.I4(aid_match_40),
.I5(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(st_aa_awtarget_enc),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(D),
.Q(active_target[49]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1
(.I0(active_cnt[58]),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2
(.I0(active_cnt[59]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.R(SR));
LUT3 #(
.INIT(8'h02))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ),
.I1(\s_axi_awaddr[31] [17]),
.I2(\s_axi_awaddr[31] [20]),
.O(st_aa_awtarget_enc));
LUT6 #(
.INIT(64'h0000000000000002))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ),
.I2(\s_axi_awaddr[31] [19]),
.I3(\s_axi_awaddr[31] [15]),
.I4(\s_axi_awaddr[31] [12]),
.I5(\s_axi_awaddr[31] [23]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.O(cmd_push_7));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10
(.I0(\s_axi_awaddr[31] [14]),
.I1(\s_axi_awaddr[31] [25]),
.I2(\s_axi_awaddr[31] [21]),
.I3(\s_axi_awaddr[31] [22]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ));
LUT6 #(
.INIT(64'h0000000000000100))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11
(.I0(\s_axi_awaddr[31] [24]),
.I1(\s_axi_awaddr[31] [27]),
.I2(\s_axi_awaddr[31] [13]),
.I3(\s_axi_awaddr[31] [26]),
.I4(\s_axi_awaddr[31] [18]),
.I5(\s_axi_awaddr[31] [16]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ));
LUT2 #(
.INIT(4'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0
(.I0(st_aa_awtarget_enc),
.I1(st_aa_awtarget_hot),
.O(D));
LUT6 #(
.INIT(64'hFFFFFFFF0000FFEF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5
(.I0(active_cnt[34]),
.I1(active_cnt[35]),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFD))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6
(.I0(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(active_cnt[58]),
.I3(active_cnt[59]),
.I4(active_cnt[57]),
.I5(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ));
LUT4 #(
.INIT(16'hEFFF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8
(.I0(aid_match_70),
.I1(active_cnt[58]),
.I2(active_cnt[59]),
.I3(active_cnt[57]),
.I4(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(st_aa_awtarget_enc),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(D),
.Q(active_target[57]),
.R(SR));
LUT5 #(
.INIT(32'h0000F100))
\gen_no_arbiter.s_ready_i[0]_i_10
(.I0(active_target[41]),
.I1(st_aa_awtarget_hot),
.I2(active_target[40]),
.I3(aid_match_50),
.I4(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_10_n_0 ));
LUT5 #(
.INIT(32'h22220002))
\gen_no_arbiter.s_ready_i[0]_i_11__0
(.I0(aid_match_20),
.I1(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I2(active_target[17]),
.I3(st_aa_awtarget_hot),
.I4(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_12
(.I0(active_target[56]),
.I1(st_aa_awtarget_hot),
.I2(active_target[57]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_13__0
(.I0(active_target[8]),
.I1(st_aa_awtarget_hot),
.I2(active_target[9]),
.O(\gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ));
LUT5 #(
.INIT(32'h44440004))
\gen_no_arbiter.s_ready_i[0]_i_14
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I1(aid_match_00),
.I2(active_target[1]),
.I3(st_aa_awtarget_hot),
.I4(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ));
LUT5 #(
.INIT(32'h44440004))
\gen_no_arbiter.s_ready_i[0]_i_15
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I1(aid_match_30),
.I2(active_target[25]),
.I3(st_aa_awtarget_hot),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_16
(.I0(active_target[32]),
.I1(aid_match_40),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.I3(active_target[8]),
.I4(aid_match_10),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_16_n_0 ));
LUT6 #(
.INIT(64'hFBFBFBFBFB00FBFB))
\gen_no_arbiter.s_ready_i[0]_i_17
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I1(aid_match_50),
.I2(active_target[40]),
.I3(active_target[24]),
.I4(aid_match_30),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_18
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I1(aid_match_20),
.I2(active_target[16]),
.I3(active_target[0]),
.I4(aid_match_00),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_19
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.I4(aid_match_70),
.I5(active_target[56]),
.O(\gen_no_arbiter.s_ready_i[0]_i_19_n_0 ));
LUT6 #(
.INIT(64'h4040FF4040404040))
\gen_no_arbiter.s_ready_i[0]_i_20
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I1(aid_match_20),
.I2(active_target[17]),
.I3(aid_match_00),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I5(active_target[1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\gen_no_arbiter.s_ready_i[0]_i_21
(.I0(aid_match_40),
.I1(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.I2(active_target[33]),
.I3(aid_match_70),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ),
.I5(active_target[57]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ));
LUT6 #(
.INIT(64'hDFDF00DFDFDFDFDF))
\gen_no_arbiter.s_ready_i[0]_i_22
(.I0(active_target[41]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(aid_match_50),
.I3(aid_match_10),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I5(active_target[9]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ));
LUT6 #(
.INIT(64'h8080FF8080808080))
\gen_no_arbiter.s_ready_i[0]_i_23
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.I2(active_target[49]),
.I3(aid_match_30),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I5(active_target[25]),
.O(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT3 #(
.INIT(8'h01))
\gen_no_arbiter.s_ready_i[0]_i_28
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.I1(\gen_multi_thread.accept_cnt_reg [1]),
.I2(\gen_multi_thread.accept_cnt_reg [2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ));
LUT6 #(
.INIT(64'h000000000000DDD0))
\gen_no_arbiter.s_ready_i[0]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_10_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\gen_no_arbiter.s_ready_i[0]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000004040400))
\gen_no_arbiter.s_ready_i[0]_i_5
(.I0(\gen_no_arbiter.s_ready_i[0]_i_16_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I4(active_target[48]),
.I5(\gen_no_arbiter.s_ready_i[0]_i_19_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEEEEE0EEEE))
\gen_no_arbiter.s_ready_i[0]_i_6
(.I0(st_aa_awtarget_hot),
.I1(st_aa_awtarget_enc),
.I2(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_8__0
(.I0(active_target[32]),
.I1(st_aa_awtarget_hot),
.I2(active_target[33]),
.O(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_9__0
(.I0(active_target[48]),
.I1(st_aa_awtarget_hot),
.I2(active_target[49]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(i__carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(i__carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(i__carry_i_4_n_0));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({i__carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ,i__carry_i_3_n_0,i__carry_i_4_n_0}));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({p_10_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ,p_10_out_carry_i_3_n_0,p_10_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_10_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_10_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_10_out_carry_i_4_n_0));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({p_12_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ,p_12_out_carry_i_3_n_0,p_12_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_12_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_12_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_12_out_carry_i_4_n_0));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({p_14_out_carry_i_1_n_0,S,p_14_out_carry_i_3_n_0,p_14_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_14_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_14_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_14_out_carry_i_4_n_0));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({p_2_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ,p_2_out_carry_i_3_n_0,p_2_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_2_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_2_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_2_out_carry_i_4_n_0));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({p_4_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ,p_4_out_carry_i_3_n_0,p_4_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_4_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_4_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_4_out_carry_i_4_n_0));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({p_6_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ,p_6_out_carry_i_3_n_0,p_6_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_6_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_6_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_6_out_carry_i_4_n_0));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({p_8_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ,p_8_out_carry_i_3_n_0,p_8_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_8_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_8_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_8_out_carry_i_4_n_0));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
(s_axi_awready,
m_ready_d,
\gen_multi_thread.accept_cnt_reg[3] ,
ss_wr_awvalid,
ss_aa_awready,
ss_wr_awready,
s_axi_awvalid,
aresetn_d,
aclk);
output [0:0]s_axi_awready;
output [1:0]m_ready_d;
output \gen_multi_thread.accept_cnt_reg[3] ;
output ss_wr_awvalid;
input ss_aa_awready;
input ss_wr_awready;
input [0:0]s_axi_awvalid;
input aresetn_d;
input aclk;
wire aclk;
wire aresetn_d;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
LUT2 #(
.INIT(4'h2))
\FSM_onehot_state[3]_i_4
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.O(ss_wr_awvalid));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'h111F))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2
(.I0(m_ready_d[1]),
.I1(ss_wr_awready),
.I2(m_ready_d[0]),
.I3(ss_aa_awready),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'h0302030000000000))
\m_ready_d[0]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.I2(ss_wr_awready),
.I3(m_ready_d[0]),
.I4(ss_aa_awready),
.I5(aresetn_d),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000EC00000000))
\m_ready_d[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.I2(ss_wr_awready),
.I3(m_ready_d[0]),
.I4(ss_aa_awready),
.I5(aresetn_d),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'hEEE0))
\s_axi_awready[0]_INST_0
(.I0(ss_aa_awready),
.I1(m_ready_d[0]),
.I2(ss_wr_awready),
.I3(m_ready_d[1]),
.O(s_axi_awready));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
(m_ready_d,
aa_sa_awvalid,
aresetn_d,
\m_ready_d_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[1] ,
aa_mi_awtarget_hot,
\m_ready_d_reg[0]_1 ,
aclk);
output [1:0]m_ready_d;
input aa_sa_awvalid;
input aresetn_d;
input \m_ready_d_reg[0]_0 ;
input \gen_no_arbiter.m_target_hot_i_reg[1] ;
input [2:0]aa_mi_awtarget_hot;
input \m_ready_d_reg[0]_1 ;
input aclk;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_no_arbiter.m_target_hot_i_reg[1] ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
LUT6 #(
.INIT(64'h00000000EEEEEEEC))
\m_ready_d[0]_i_1
(.I0(aa_sa_awvalid),
.I1(m_ready_d[0]),
.I2(aa_mi_awtarget_hot[2]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_mi_awtarget_hot[0]),
.I5(\m_ready_d_reg[0]_1 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E0))
\m_ready_d[1]_i_1
(.I0(aa_sa_awvalid),
.I1(m_ready_d[1]),
.I2(aresetn_d),
.I3(\m_ready_d_reg[0]_0 ),
.I4(\gen_no_arbiter.m_target_hot_i_reg[1] ),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
(ss_wr_awready,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlast,
m_axi_wready,
p_14_in,
ss_wr_awvalid);
output ss_wr_awready;
output [1:0]m_axi_wvalid;
output \gen_axi.write_cs_reg[1] ;
output [0:0]s_axi_wready;
input [0:0]st_aa_awtarget_enc;
input aclk;
input [0:0]D;
input [0:0]SR;
input [0:0]st_aa_awtarget_hot;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wvalid;
input [0:0]\gen_axi.write_cs_reg[1]_0 ;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
input p_14_in;
input ss_wr_awvalid;
wire [0:0]D;
wire [0:0]SR;
wire aclk;
wire \gen_axi.write_cs_reg[1] ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire p_14_in;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo wrouter_aw_fifo
(.D(D),
.SR(SR),
.aclk(aclk),
.\gen_axi.write_cs_reg[1] (\gen_axi.write_cs_reg[1] ),
.\gen_axi.write_cs_reg[1]_0 (\gen_axi.write_cs_reg[1]_0 ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d),
.p_14_in(p_14_in),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg_0(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot));
endmodule |
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
(s_ready_i_reg_0,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlast,
m_axi_wready,
p_14_in,
ss_wr_awvalid);
output s_ready_i_reg_0;
output [1:0]m_axi_wvalid;
output \gen_axi.write_cs_reg[1] ;
output [0:0]s_axi_wready;
input [0:0]st_aa_awtarget_enc;
input aclk;
input [0:0]D;
input [0:0]SR;
input [0:0]st_aa_awtarget_hot;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wvalid;
input [0:0]\gen_axi.write_cs_reg[1]_0 ;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
input p_14_in;
input ss_wr_awvalid;
wire \/FSM_onehot_state[0]_i_1_n_0 ;
wire \/FSM_onehot_state[1]_i_1_n_0 ;
wire \/FSM_onehot_state[2]_i_1_n_0 ;
wire \/FSM_onehot_state[3]_i_2_n_0 ;
wire [0:0]D;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[2] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[3] ;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire [2:0]fifoaddr;
wire \gen_axi.write_cs_reg[1] ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[2]_i_1_n_0 ;
wire \gen_srls[0].gen_rep[0].srl_nx1_n_0 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_1 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_2 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_3 ;
wire load_s1;
wire m_avalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire m_valid_i;
wire m_valid_i_i_1_n_0;
wire p_0_in5_out;
(* RTL_KEEP = "yes" *) wire p_0_in8_in;
wire p_14_in;
(* RTL_KEEP = "yes" *) wire p_9_in;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i_i_1__2_n_0;
wire s_ready_i_i_2_n_0;
wire s_ready_i_reg_0;
wire ss_wr_awvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire \storage_data1[0]_i_1_n_0 ;
wire \storage_data1_reg_n_0_[0] ;
wire \storage_data1_reg_n_0_[1] ;
LUT5 #(
.INIT(32'h40440000))
\/FSM_onehot_state[0]_i_1
(.I0(p_9_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(m_ready_d),
.I3(s_axi_awvalid),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20202F20))
\/FSM_onehot_state[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB0B0B0BF))
\/FSM_onehot_state[2]_i_1
(.I0(m_ready_d),
.I1(s_axi_awvalid),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00002A22))
\/FSM_onehot_state[3]_i_2
(.I0(p_0_in8_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(m_ready_d),
.I3(s_axi_awvalid),
.I4(p_9_in),
.O(\/FSM_onehot_state[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF488F488F488))
\FSM_onehot_state[3]_i_1
(.I0(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i));
LUT6 #(
.INIT(64'h0000000010000000))
\FSM_onehot_state[3]_i_5
(.I0(fifoaddr[1]),
.I1(fifoaddr[0]),
.I2(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I5(fifoaddr[2]),
.O(p_0_in5_out));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[0]_i_1_n_0 ),
.Q(p_9_in),
.S(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[1]_i_1_n_0 ),
.Q(p_0_in8_in),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[2] ),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[3]_i_2_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[3] ),
.R(areset_d1));
FDRE areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(SR),
.Q(areset_d1),
.R(1'b0));
LUT6 #(
.INIT(64'h0400000000000000))
\gen_axi.write_cs[1]_i_2
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(s_axi_wlast),
.I4(s_axi_wvalid),
.I5(m_avalid),
.O(\gen_axi.write_cs_reg[1] ));
LUT6 #(
.INIT(64'hC133DDFF3ECC2200))
\gen_rep[0].fifoaddr[0]_i_1
(.I0(p_0_in8_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(s_ready_i_reg_0),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(fifoaddr[0]),
.O(\gen_rep[0].fifoaddr[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hBFD5402A))
\gen_rep[0].fifoaddr[1]_i_1
(.I0(fifoaddr[0]),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(\FSM_onehot_state_reg_n_0_[3] ),
.I3(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I4(fifoaddr[1]),
.O(\gen_rep[0].fifoaddr[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFFFF77710000888))
\gen_rep[0].fifoaddr[2]_i_1
(.I0(fifoaddr[0]),
.I1(fifoaddr[1]),
.I2(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I5(fifoaddr[2]),
.O(\gen_rep[0].fifoaddr[2]_i_1_n_0 ));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ),
.Q(fifoaddr[0]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ),
.Q(fifoaddr[1]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[2]_i_1_n_0 ),
.Q(fifoaddr[2]),
.S(SR));
zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0 \gen_srls[0].gen_rep[0].srl_nx1
(.aclk(aclk),
.fifoaddr(fifoaddr),
.push(push),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_0 ));
zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4 \gen_srls[0].gen_rep[1].srl_nx1
(.D(D),
.aclk(aclk),
.fifoaddr(fifoaddr),
.\gen_rep[0].fifoaddr_reg[0] (\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.load_s1(load_s1),
.m_avalid(m_avalid),
.m_axi_wready(m_axi_wready),
.m_ready_d(m_ready_d),
.out0({p_0_in8_in,\FSM_onehot_state_reg_n_0_[3] }),
.p_14_in(p_14_in),
.push(push),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.s_ready_i_reg_0(s_ready_i_reg_0),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.\storage_data1_reg[0] (\storage_data1_reg_n_0_[0] ),
.\storage_data1_reg[1] (\gen_srls[0].gen_rep[1].srl_nx1_n_1 ),
.\storage_data1_reg[1]_0 (\storage_data1_reg_n_0_[1] ));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h1000))
\m_axi_wvalid[0]_INST_0
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(m_avalid),
.I3(s_axi_wvalid),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_wvalid[1]_INST_0
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(m_avalid),
.I3(s_axi_wvalid),
.O(m_axi_wvalid[1]));
LUT6 #(
.INIT(64'hFFFFF400F400F400))
m_valid_i_i_1
(.I0(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(m_valid_i),
.D(m_valid_i_i_1_n_0),
.Q(m_avalid),
.R(areset_d1));
LUT6 #(
.INIT(64'h0A8A008A0A800080))
\s_axi_wready[0]_INST_0
(.I0(m_avalid),
.I1(m_axi_wready[1]),
.I2(\storage_data1_reg_n_0_[0] ),
.I3(\storage_data1_reg_n_0_[1] ),
.I4(p_14_in),
.I5(m_axi_wready[0]),
.O(s_axi_wready));
LUT6 #(
.INIT(64'hFEFFFFFFAAAAAAAA))
s_ready_i_i_1__2
(.I0(s_ready_i_i_2_n_0),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I2(fifoaddr[0]),
.I3(fifoaddr[1]),
.I4(fifoaddr[2]),
.I5(s_ready_i_reg_0),
.O(s_ready_i_i_1__2_n_0));
LUT3 #(
.INIT(8'hEA))
s_ready_i_i_2
(.I0(areset_d1),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(\FSM_onehot_state_reg_n_0_[3] ),
.O(s_ready_i_i_2_n_0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(s_ready_i_reg_0),
.R(SR));
LUT5 #(
.INIT(32'hB8FFB800))
\storage_data1[0]_i_1
(.I0(\gen_srls[0].gen_rep[0].srl_nx1_n_0 ),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(st_aa_awtarget_enc),
.I3(load_s1),
.I4(\storage_data1_reg_n_0_[0] ),
.O(\storage_data1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h88888888FFC88888))
\storage_data1[1]_i_2
(.I0(\FSM_onehot_state_reg_n_0_[3] ),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(p_0_in8_in),
.I3(p_9_in),
.I4(s_axi_awvalid),
.I5(m_ready_d),
.O(load_s1));
FDRE \storage_data1_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\storage_data1[0]_i_1_n_0 ),
.Q(\storage_data1_reg_n_0_[0] ),
.R(1'b0));
FDRE \storage_data1_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_srls[0].gen_rep[1].srl_nx1_n_1 ),
.Q(\storage_data1_reg_n_0_[1] ),
.R(1'b0));
endmodule |
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0
(\storage_data1_reg[0] ,
push,
st_aa_awtarget_enc,
fifoaddr,
aclk);
output \storage_data1_reg[0] ;
input push;
input [0:0]st_aa_awtarget_enc;
input [2:0]fifoaddr;
input aclk;
wire aclk;
wire [2:0]fifoaddr;
wire push;
wire [0:0]st_aa_awtarget_enc;
wire \storage_data1_reg[0] ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(st_aa_awtarget_enc),
.Q(\storage_data1_reg[0] ),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
endmodule |
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4
(push,
\storage_data1_reg[1] ,
s_ready_i_reg,
\gen_rep[0].fifoaddr_reg[0] ,
D,
fifoaddr,
aclk,
st_aa_awtarget_enc,
st_aa_awtarget_hot,
out0,
load_s1,
\storage_data1_reg[1]_0 ,
s_ready_i_reg_0,
m_ready_d,
s_axi_awvalid,
s_axi_wlast,
s_axi_wvalid,
m_avalid,
m_axi_wready,
p_14_in,
\storage_data1_reg[0] );
output push;
output \storage_data1_reg[1] ;
output s_ready_i_reg;
output \gen_rep[0].fifoaddr_reg[0] ;
input [0:0]D;
input [2:0]fifoaddr;
input aclk;
input [0:0]st_aa_awtarget_enc;
input [0:0]st_aa_awtarget_hot;
input [1:0]out0;
input load_s1;
input \storage_data1_reg[1]_0 ;
input s_ready_i_reg_0;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
input m_avalid;
input [1:0]m_axi_wready;
input p_14_in;
input \storage_data1_reg[0] ;
wire [0:0]D;
wire \FSM_onehot_state[3]_i_6_n_0 ;
wire aclk;
wire [2:0]fifoaddr;
wire \gen_rep[0].fifoaddr_reg[0] ;
wire load_s1;
wire m_avalid;
wire [1:0]m_axi_wready;
wire [0:0]m_ready_d;
wire [1:0]out0;
wire p_14_in;
wire p_2_out;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wvalid;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire \storage_data1_reg[0] ;
wire \storage_data1_reg[1] ;
wire \storage_data1_reg[1]_0 ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
LUT4 #(
.INIT(16'h4000))
\FSM_onehot_state[3]_i_3
(.I0(\FSM_onehot_state[3]_i_6_n_0 ),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.I3(m_avalid),
.O(\gen_rep[0].fifoaddr_reg[0] ));
LUT5 #(
.INIT(32'hF035FF35))
\FSM_onehot_state[3]_i_6
(.I0(m_axi_wready[0]),
.I1(p_14_in),
.I2(\storage_data1_reg[1]_0 ),
.I3(\storage_data1_reg[0] ),
.I4(m_axi_wready[1]),
.O(\FSM_onehot_state[3]_i_6_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(D),
.Q(p_2_out),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
LUT1 #(
.INIT(2'h1))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1
(.I0(s_ready_i_reg),
.O(push));
LUT6 #(
.INIT(64'hFF0DFFFFFFDDFFFF))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2
(.I0(out0[1]),
.I1(\gen_rep[0].fifoaddr_reg[0] ),
.I2(s_ready_i_reg_0),
.I3(m_ready_d),
.I4(s_axi_awvalid),
.I5(out0[0]),
.O(s_ready_i_reg));
LUT6 #(
.INIT(64'hF011FFFFF0110000))
\storage_data1[1]_i_1
(.I0(st_aa_awtarget_enc),
.I1(st_aa_awtarget_hot),
.I2(p_2_out),
.I3(out0[0]),
.I4(load_s1),
.I5(\storage_data1_reg[1]_0 ),
.O(\storage_data1_reg[1] ));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
(p_80_out,
m_axi_bready,
p_74_out,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
m_axi_rvalid,
chosen_0,
s_axi_rready,
Q,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
E);
output p_80_out;
output [0:0]m_axi_bready;
output p_74_out;
output \m_axi_rready[0] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]chosen;
input [0:0]s_axi_bready;
input \aresetn_d_reg[1]_0 ;
input [0:0]m_axi_rvalid;
input [0:0]chosen_0;
input [0:0]s_axi_rready;
input [3:0]Q;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
input [0:0]E;
wire [13:0]D;
wire [0:0]E;
wire [3:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]chosen;
wire [0:0]chosen_0;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_1_in;
wire p_74_out;
wire p_80_out;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8 b_pipe
(.D(D),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.chosen(chosen),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_80_out),
.p_1_in(p_1_in),
.s_axi_bready(s_axi_bready));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9 r_pipe
(.E(E),
.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.chosen_0(chosen_0),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[0] (\m_axi_rready[0] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_74_out),
.p_1_in(p_1_in),
.s_axi_rready(s_axi_rready));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
(p_60_out,
m_axi_bready,
p_1_in,
p_54_out,
\m_axi_rready[1] ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ,
s_axi_bresp,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\aresetn_d_reg[1] ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
chosen,
\aresetn_d_reg[1]_1 ,
Q,
\m_payload_i_reg[12] ,
p_38_out,
\m_payload_i_reg[1] ,
s_axi_rready,
chosen_0,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ,
\m_payload_i_reg[32] ,
p_32_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D);
output p_60_out;
output [0:0]m_axi_bready;
output p_1_in;
output p_54_out;
output \m_axi_rready[1] ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_multi_thread.accept_cnt_reg[3] ;
output [4:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
output [1:0]s_axi_bresp;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]s_axi_rresp;
output [19:0]s_axi_rdata;
output \gen_master_slots[1].r_issuing_cnt_reg[11] ;
output \aresetn_d_reg[1] ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [1:0]chosen;
input \aresetn_d_reg[1]_1 ;
input [3:0]Q;
input [9:0]\m_payload_i_reg[12] ;
input p_38_out;
input [1:0]\m_payload_i_reg[1] ;
input [0:0]s_axi_rready;
input [1:0]chosen_0;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
input [20:0]\m_payload_i_reg[32] ;
input p_32_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
wire [13:0]D;
wire [3:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [1:0]chosen;
wire [1:0]chosen_0;
wire \gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
wire [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire [9:0]\m_payload_i_reg[12] ;
wire [1:0]\m_payload_i_reg[1] ;
wire [20:0]\m_payload_i_reg[32] ;
wire p_1_in;
wire p_32_out;
wire p_38_out;
wire p_54_out;
wire p_60_out;
wire [4:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [19:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6 b_pipe
(.D(D),
.Q(Q),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\aresetn_d_reg[1]_1 (\aresetn_d_reg[1]_1 ),
.chosen(chosen),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.accept_cnt_reg[3] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_60_out),
.\m_payload_i_reg[12]_0 (\m_payload_i_reg[12] ),
.\m_payload_i_reg[1]_0 (\m_payload_i_reg[1] ),
.p_1_in(p_1_in),
.p_38_out(p_38_out),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1]_0 ),
.chosen_0(chosen_0),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].r_issuing_cnt_reg[11] ),
.\gen_master_slots[1].r_issuing_cnt_reg[11]_0 (\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[1] (\m_axi_rready[1] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.\m_payload_i_reg[32]_0 (\m_payload_i_reg[32] ),
.p_1_in(p_1_in),
.p_32_out(p_32_out),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_ready_i_reg_0(p_54_out));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
(p_38_out,
m_valid_i_reg,
mi_bready_2,
p_32_out,
mi_rready_2,
s_ready_i_reg,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
Q,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_21_in,
chosen,
s_axi_bready,
\m_payload_i_reg[13] ,
m_valid_i_reg_0,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ,
w_issuing_cnt,
r_issuing_cnt,
st_aa_artarget_hot,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
p_15_in,
s_axi_rready,
chosen_0,
\gen_axi.s_axi_rid_i_reg[11] ,
p_17_in,
\gen_axi.s_axi_arready_i_reg ,
D,
E);
output p_38_out;
output m_valid_i_reg;
output mi_bready_2;
output p_32_out;
output mi_rready_2;
output s_ready_i_reg;
output [6:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [4:0]Q;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output [0:0]S;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_21_in;
input [0:0]chosen;
input [0:0]s_axi_bready;
input [13:0]\m_payload_i_reg[13] ;
input m_valid_i_reg_0;
input [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
input [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
input [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
input [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
input [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
input [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
input [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
input [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
input [0:0]w_issuing_cnt;
input [0:0]r_issuing_cnt;
input [1:0]st_aa_artarget_hot;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input p_15_in;
input [0:0]s_axi_rready;
input [0:0]chosen_0;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_17_in;
input \gen_axi.s_axi_arready_i_reg ;
input [11:0]D;
input [0:0]E;
wire [11:0]D;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]S;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]chosen;
wire [0:0]chosen_0;
wire \gen_axi.s_axi_arready_i_reg ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [13:0]\m_payload_i_reg[13] ;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire mi_bready_2;
wire mi_rready_2;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire p_21_in;
wire p_32_out;
wire p_38_out;
wire [0:0]r_issuing_cnt;
wire [6:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
wire s_ready_i_reg;
wire [1:0]st_aa_artarget_hot;
wire [0:0]w_issuing_cnt;
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.D(D),
.Q(Q),
.S(S),
.aclk(aclk),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.chosen(chosen),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] (\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] (\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] (\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] (\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] (\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] (\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] (\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] (\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.\m_payload_i_reg[13]_0 (\m_payload_i_reg[13] ),
.\m_payload_i_reg[2]_0 (p_38_out),
.m_valid_i_reg_0(m_valid_i_reg),
.m_valid_i_reg_1(m_valid_i_reg_0),
.mi_bready_2(mi_bready_2),
.p_1_in(p_1_in),
.p_21_in(p_21_in),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_ready_i_reg_0(s_ready_i_reg),
.w_issuing_cnt(w_issuing_cnt));
zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (m_valid_i_reg),
.chosen_0(chosen_0),
.\gen_axi.s_axi_arready_i_reg (\gen_axi.s_axi_arready_i_reg ),
.\gen_axi.s_axi_rid_i_reg[11] (\gen_axi.s_axi_rid_i_reg[11] ),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_valid_i_reg_0(p_32_out),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.r_issuing_cnt(r_issuing_cnt),
.s_axi_rready(s_axi_rready),
.\skid_buffer_reg[34]_0 (mi_rready_2),
.st_aa_artarget_hot(st_aa_artarget_hot));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(\m_payload_i_reg[2]_0 ,
m_valid_i_reg_0,
mi_bready_2,
s_ready_i_reg_0,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
Q,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_21_in,
chosen,
s_axi_bready,
\m_payload_i_reg[13]_0 ,
m_valid_i_reg_1,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ,
w_issuing_cnt,
D);
output \m_payload_i_reg[2]_0 ;
output m_valid_i_reg_0;
output mi_bready_2;
output s_ready_i_reg_0;
output [6:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output [0:0]S;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [4:0]Q;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_21_in;
input [0:0]chosen;
input [0:0]s_axi_bready;
input [13:0]\m_payload_i_reg[13]_0 ;
input m_valid_i_reg_1;
input [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
input [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
input [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
input [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
input [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
input [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
input [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
input [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
input [0:0]w_issuing_cnt;
input [11:0]D;
wire [11:0]D;
wire [4:0]Q;
wire [0:0]S;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]chosen;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ;
wire [13:0]\m_payload_i_reg[13]_0 ;
wire \m_payload_i_reg[2]_0 ;
wire m_valid_i_i_1__1_n_0;
wire m_valid_i_reg_0;
wire m_valid_i_reg_1;
wire mi_bready_2;
wire p_1_in;
wire p_21_in;
wire [6:0]s_axi_bid;
wire \s_axi_bid[6]_INST_0_i_1_n_0 ;
wire \s_axi_bid[7]_INST_0_i_1_n_0 ;
wire \s_axi_bid[8]_INST_0_i_1_n_0 ;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__5_n_0;
wire s_ready_i_reg_0;
wire [35:24]st_mr_bid;
wire [0:0]w_issuing_cnt;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0] ),
.Q(s_ready_i_reg_0),
.R(1'b0));
LUT4 #(
.INIT(16'h2AAA))
\gen_no_arbiter.s_ready_i[0]_i_27
(.I0(w_issuing_cnt),
.I1(s_axi_bready),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__0
(.I0(\m_payload_i_reg[2]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[8]),
.Q(st_mr_bid[32]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[9]),
.Q(st_mr_bid[33]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[10]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[11]),
.Q(st_mr_bid[35]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[0]),
.Q(st_mr_bid[24]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[1]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[2]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[3]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[4]),
.Q(st_mr_bid[28]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[5]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[6]),
.Q(st_mr_bid[30]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[7]),
.Q(st_mr_bid[31]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__1
(.I0(p_21_in),
.I1(mi_bready_2),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[2]_0 ),
.I4(chosen),
.O(m_valid_i_i_1__1_n_0));
LUT1 #(
.INIT(2'h1))
m_valid_i_i_1__5
(.I0(s_ready_i_reg_0),
.O(m_valid_i_reg_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(\m_payload_i_reg[2]_0 ),
.R(m_valid_i_reg_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[0]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.O(s_axi_bid[0]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[0]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [0]),
.I1(st_mr_bid[24]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [7]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[11]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.O(s_axi_bid[6]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[11]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [6]),
.I1(st_mr_bid[35]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [13]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[4]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.O(s_axi_bid[1]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[4]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [1]),
.I1(st_mr_bid[28]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [8]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[6]_INST_0
(.I0(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.O(s_axi_bid[2]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[6]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [2]),
.I1(st_mr_bid[30]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [9]),
.O(\s_axi_bid[6]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[7]_INST_0
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.O(s_axi_bid[3]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[7]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [3]),
.I1(st_mr_bid[31]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [10]),
.O(\s_axi_bid[7]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[8]_INST_0
(.I0(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(s_axi_bid[4]));
LUT6 #(
.INIT(64'hF5303030F53F3F3F))
\s_axi_bid[8]_INST_0_i_1
(.I0(st_mr_bid[32]),
.I1(\m_payload_i_reg[13]_0 [11]),
.I2(m_valid_i_reg_1),
.I3(\m_payload_i_reg[2]_0 ),
.I4(chosen),
.I5(\m_payload_i_reg[13]_0 [4]),
.O(\s_axi_bid[8]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[9]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.O(s_axi_bid[5]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[9]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [5]),
.I1(st_mr_bid[33]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [12]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__5
(.I0(\m_payload_i_reg[2]_0 ),
.I1(p_21_in),
.I2(chosen),
.I3(s_axi_bready),
.I4(s_ready_i_reg_0),
.O(s_ready_i_i_1__5_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__5_n_0),
.Q(mi_bready_2),
.R(p_1_in));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
p_1_in,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ,
s_axi_bresp,
\aresetn_d_reg[1] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
chosen,
\aresetn_d_reg[1]_1 ,
Q,
\m_payload_i_reg[12]_0 ,
p_38_out,
\m_payload_i_reg[1]_0 ,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output p_1_in;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_multi_thread.accept_cnt_reg[3] ;
output [4:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
output [1:0]s_axi_bresp;
output \aresetn_d_reg[1] ;
output [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [1:0]chosen;
input \aresetn_d_reg[1]_1 ;
input [3:0]Q;
input [9:0]\m_payload_i_reg[12]_0 ;
input p_38_out;
input [1:0]\m_payload_i_reg[1]_0 ;
input [13:0]D;
wire [13:0]D;
wire [3:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [1:0]chosen;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
wire [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire [9:0]\m_payload_i_reg[12]_0 ;
wire [1:0]\m_payload_i_reg[1]_0 ;
wire m_valid_i_i_1__0_n_0;
wire [1:1]p_0_in;
wire p_1_in;
wire p_38_out;
wire [4:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_ready_i_i_2__0_n_0;
wire [22:13]st_mr_bid;
wire [4:3]st_mr_bmesg;
LUT2 #(
.INIT(4'h8))
\aresetn_d[1]_i_1
(.I0(p_0_in),
.I1(aresetn),
.O(\aresetn_d_reg[1] ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(p_0_in),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000700000000))
\gen_no_arbiter.s_ready_i[0]_i_26
(.I0(\gen_multi_thread.accept_cnt_reg[3] ),
.I1(s_axi_bready),
.I2(Q[2]),
.I3(Q[1]),
.I4(Q[0]),
.I5(Q[3]),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[0]),
.Q(st_mr_bmesg[3]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [4]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [5]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[12]),
.Q(st_mr_bid[22]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [6]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[1]),
.Q(st_mr_bmesg[4]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [0]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[3]),
.Q(st_mr_bid[13]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[4]),
.Q(st_mr_bid[14]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[5]),
.Q(st_mr_bid[15]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [1]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[7]),
.Q(st_mr_bid[17]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [2]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__0
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(chosen[0]),
.I4(\m_payload_i_reg[0]_0 ),
.O(m_valid_i_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__0_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[10]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ),
.O(s_axi_bid[4]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[10]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [4]),
.I1(st_mr_bid[22]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [9]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h8))
\s_axi_bid[11]_INST_0_i_2
(.I0(\m_payload_i_reg[0]_0 ),
.I1(chosen[0]),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[1]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.O(s_axi_bid[0]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[1]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [0]),
.I1(st_mr_bid[13]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [5]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[2]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.O(s_axi_bid[1]));
LUT6 #(
.INIT(64'hF0535353FF535353))
\s_axi_bid[2]_INST_0_i_1
(.I0(st_mr_bid[14]),
.I1(\m_payload_i_reg[12]_0 [1]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [6]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[3]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.O(s_axi_bid[2]));
LUT6 #(
.INIT(64'hF0535353FF535353))
\s_axi_bid[3]_INST_0_i_1
(.I0(st_mr_bid[15]),
.I1(\m_payload_i_reg[12]_0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [7]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[5]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.O(s_axi_bid[3]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[5]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [3]),
.I1(st_mr_bid[17]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [8]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ));
LUT6 #(
.INIT(64'h3FBFBFBF3F808080))
\s_axi_bresp[0]_INST_0
(.I0(st_mr_bmesg[3]),
.I1(chosen[0]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(chosen[1]),
.I4(p_38_out),
.I5(\m_payload_i_reg[1]_0 [0]),
.O(s_axi_bresp[0]));
LUT6 #(
.INIT(64'h0CCCFAAAFAAAFAAA))
\s_axi_bresp[1]_INST_0
(.I0(\m_payload_i_reg[1]_0 [1]),
.I1(st_mr_bmesg[4]),
.I2(chosen[1]),
.I3(p_38_out),
.I4(\m_payload_i_reg[0]_0 ),
.I5(chosen[0]),
.O(s_axi_bresp[1]));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__3
(.I0(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_2__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(chosen[0]),
.I4(\aresetn_d_reg[1]_1 ),
.O(s_ready_i_i_2__0_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_2__0_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]chosen;
input [0:0]s_axi_bready;
input \aresetn_d_reg[1]_0 ;
input [13:0]D;
wire [13:0]D;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]chosen;
wire [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_2_n_0;
wire p_1_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__4_n_0;
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[12]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_2
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(chosen),
.I3(\m_payload_i_reg[0]_0 ),
.I4(s_axi_bready),
.O(m_valid_i_i_2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_2_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__4
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(chosen),
.I3(s_axi_bready),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1__4_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__4_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(m_valid_i_reg_0,
\skid_buffer_reg[34]_0 ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
r_issuing_cnt,
st_aa_artarget_hot,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
p_15_in,
s_axi_rready,
chosen_0,
\gen_axi.s_axi_rid_i_reg[11] ,
p_17_in,
\gen_axi.s_axi_arready_i_reg ,
E);
output m_valid_i_reg_0;
output \skid_buffer_reg[34]_0 ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]r_issuing_cnt;
input [1:0]st_aa_artarget_hot;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input p_15_in;
input [0:0]s_axi_rready;
input [0:0]chosen_0;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_17_in;
input \gen_axi.s_axi_arready_i_reg ;
input [0:0]E;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]chosen_0;
wire \gen_axi.s_axi_arready_i_reg ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire [0:0]r_issuing_cnt;
wire [0:0]s_axi_rready;
wire s_ready_i0;
wire [46:34]skid_buffer;
wire \skid_buffer_reg[34]_0 ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire [1:0]st_aa_artarget_hot;
LUT6 #(
.INIT(64'h955555552AAAAAAA))
\gen_master_slots[2].r_issuing_cnt[16]_i_1
(.I0(\gen_axi.s_axi_arready_i_reg ),
.I1(s_axi_rready),
.I2(chosen_0),
.I3(m_valid_i_reg_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I5(r_issuing_cnt),
.O(\gen_master_slots[2].r_issuing_cnt_reg[16] ));
LUT6 #(
.INIT(64'hFF0FF2020000F202))
\gen_no_arbiter.s_ready_i[0]_i_23__0
(.I0(r_issuing_cnt),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ),
.I2(st_aa_artarget_hot[0]),
.I3(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.I4(st_aa_artarget_hot[1]),
.I5(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT4 #(
.INIT(16'h8000))
\gen_no_arbiter.s_ready_i[0]_i_25__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I1(m_valid_i_reg_0),
.I2(chosen_0),
.I3(s_axi_rready),
.O(\gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(p_17_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [0]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [1]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [2]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [3]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [4]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [5]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [6]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [7]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [8]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [9]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [10]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [11]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__4
(.I0(s_axi_rready),
.I1(chosen_0),
.I2(m_valid_i_reg_0),
.I3(p_15_in),
.I4(\skid_buffer_reg[34]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__1
(.I0(p_15_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(s_axi_rready),
.I3(chosen_0),
.I4(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[34]_0 ),
.R(p_1_in));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(p_17_in),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7
(s_ready_i_reg_0,
\m_axi_rready[1] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
chosen_0,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ,
\m_payload_i_reg[32]_0 ,
p_32_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata);
output s_ready_i_reg_0;
output \m_axi_rready[1] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]s_axi_rresp;
output [19:0]s_axi_rdata;
output \gen_master_slots[1].r_issuing_cnt_reg[11] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [1:0]chosen_0;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
input [20:0]\m_payload_i_reg[32]_0 ;
input p_32_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [1:0]chosen_0;
wire \gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire [20:0]\m_payload_i_reg[32]_0 ;
wire m_valid_i0;
wire p_1_in;
wire p_1_in_0;
wire p_32_out;
wire [19:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire [68:35]st_mr_rmesg;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[1].r_issuing_cnt[11]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.I1(s_ready_i_reg_0),
.I2(chosen_0[0]),
.I3(s_axi_rready),
.O(\gen_master_slots[1].r_issuing_cnt_reg[8] ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h8))
\gen_master_slots[1].r_issuing_cnt[11]_i_6
(.I0(s_ready_i_reg_0),
.I1(chosen_0[0]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] ));
LUT5 #(
.INIT(32'h00000100))
\gen_no_arbiter.s_ready_i[0]_i_27__0
(.I0(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [0]),
.I1(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [1]),
.I2(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [2]),
.I3(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [3]),
.I4(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__3
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__0
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(m_axi_rlast),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__0
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__0
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__0
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__0
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__0
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
LUT3 #(
.INIT(8'hD5))
\m_payload_i[46]_i_1__0
(.I0(s_ready_i_reg_0),
.I1(s_axi_rready),
.I2(chosen_0[0]),
.O(p_1_in_0));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__0
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[12]),
.Q(st_mr_rmesg[50]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[13]),
.Q(st_mr_rmesg[51]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[14]),
.Q(st_mr_rmesg[52]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[15]),
.Q(st_mr_rmesg[53]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[16]),
.Q(st_mr_rmesg[54]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[17]),
.Q(st_mr_rmesg[55]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[18]),
.Q(st_mr_rmesg[56]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[1]),
.Q(st_mr_rmesg[39]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[21]),
.Q(st_mr_rmesg[59]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[23]),
.Q(st_mr_rmesg[61]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[24]),
.Q(st_mr_rmesg[62]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[25]),
.Q(st_mr_rmesg[63]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[26]),
.Q(st_mr_rmesg[64]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[28]),
.Q(st_mr_rmesg[66]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[29]),
.Q(st_mr_rmesg[67]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[2]),
.Q(st_mr_rmesg[40]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[30]),
.Q(st_mr_rmesg[68]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[32]),
.Q(st_mr_rmesg[35]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[3]),
.Q(st_mr_rmesg[41]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[5]),
.Q(st_mr_rmesg[43]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[7]),
.Q(st_mr_rmesg[45]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hFF2AFFFF))
m_valid_i_i_1__3
(.I0(s_ready_i_reg_0),
.I1(s_axi_rready),
.I2(chosen_0[0]),
.I3(m_axi_rvalid),
.I4(\m_axi_rready[1] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[12]_INST_0
(.I0(st_mr_rmesg[50]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [5]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[13]_INST_0
(.I0(st_mr_rmesg[51]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [6]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[14]_INST_0
(.I0(st_mr_rmesg[52]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [7]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[15]_INST_0
(.I0(st_mr_rmesg[53]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [8]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[16]_INST_0
(.I0(st_mr_rmesg[54]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [9]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[17]_INST_0
(.I0(st_mr_rmesg[55]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [10]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[18]_INST_0
(.I0(st_mr_rmesg[56]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [11]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[1]_INST_0
(.I0(st_mr_rmesg[39]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [0]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[21]_INST_0
(.I0(st_mr_rmesg[59]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [12]),
.O(s_axi_rdata[12]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[23]_INST_0
(.I0(st_mr_rmesg[61]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [13]),
.O(s_axi_rdata[13]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[24]_INST_0
(.I0(st_mr_rmesg[62]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [14]),
.O(s_axi_rdata[14]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[25]_INST_0
(.I0(st_mr_rmesg[63]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [15]),
.O(s_axi_rdata[15]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[26]_INST_0
(.I0(st_mr_rmesg[64]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [16]),
.O(s_axi_rdata[16]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[28]_INST_0
(.I0(st_mr_rmesg[66]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [17]),
.O(s_axi_rdata[17]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[29]_INST_0
(.I0(st_mr_rmesg[67]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [18]),
.O(s_axi_rdata[18]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[2]_INST_0
(.I0(st_mr_rmesg[40]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [1]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[30]_INST_0
(.I0(st_mr_rmesg[68]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [19]),
.O(s_axi_rdata[19]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[3]_INST_0
(.I0(st_mr_rmesg[41]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [2]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[5]_INST_0
(.I0(st_mr_rmesg[43]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [3]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[7]_INST_0
(.I0(st_mr_rmesg[45]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [4]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'h0FFFACCCACCCACCC))
\s_axi_rresp[0]_INST_0
(.I0(st_mr_rmesg[35]),
.I1(\m_payload_i_reg[32]_0 [20]),
.I2(s_ready_i_reg_0),
.I3(chosen_0[0]),
.I4(p_32_out),
.I5(chosen_0[1]),
.O(s_axi_rresp));
LUT5 #(
.INIT(32'hFF4F4F4F))
s_ready_i_i_1__0
(.I0(m_axi_rvalid),
.I1(\m_axi_rready[1] ),
.I2(s_ready_i_reg_0),
.I3(s_axi_rready),
.I4(chosen_0[0]),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\m_axi_rready[1] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9
(m_valid_i_reg_0,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_rvalid,
chosen_0,
s_axi_rready,
Q,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
E);
output m_valid_i_reg_0;
output \m_axi_rready[0] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_rvalid;
input [0:0]chosen_0;
input [0:0]s_axi_rready;
input [3:0]Q;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]E;
wire [0:0]E;
wire [3:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]chosen_0;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire [0:0]s_axi_rready;
wire s_ready_i0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[0].r_issuing_cnt[3]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(s_axi_rready),
.I2(m_valid_i_reg_0),
.I3(chosen_0),
.O(\gen_master_slots[0].r_issuing_cnt_reg[0] ));
LUT5 #(
.INIT(32'h00000100))
\gen_no_arbiter.s_ready_i[0]_i_26__0
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.I3(Q[3]),
.I4(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(m_axi_rlast),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF4CFFFF))
m_valid_i_i_1__2
(.I0(chosen_0),
.I1(m_valid_i_reg_0),
.I2(s_axi_rready),
.I3(m_axi_rvalid),
.I4(\m_axi_rready[0] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hF4FF44FF))
s_ready_i_i_1
(.I0(m_axi_rvalid),
.I1(\m_axi_rready[0] ),
.I2(chosen_0),
.I3(m_valid_i_reg_0),
.I4(s_axi_rready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\m_axi_rready[0] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule |
module sky130_fd_sc_lp__inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule |
module lsu_addr_calculator(
in_vector_source_b,
in_scalar_source_a,
in_scalar_source_b,
in_opcode,
in_lds_base,
in_imm_value0,
out_ld_st_addr,
out_gm_or_lds
);
input [2047:0] in_vector_source_b;
input [127:0] in_scalar_source_a;
input [31:0] in_scalar_source_b;
input [31:0] in_opcode;
input [15:0] in_lds_base;
input [15:0] in_imm_value0;
output [2047:0] out_ld_st_addr;
output out_gm_or_lds;
`define ADD_TID_ENABLE in_scalar_source_a[119]
reg [63:0] out_exec_value;
reg [2047:0] out_ld_st_addr;
reg out_gm_or_lds;
wire [383:0] thread_id;
wire [2047:0] mtbuf_address;
wire [2047:0]ds_address;
always @(*)
begin
casex(in_opcode[31:24])
`LSU_SMRD_FORMAT:
begin
//Only 32 bits of the result is the address
//Other bits are ignored since exec mask is 64'd1
out_ld_st_addr <= in_scalar_source_a[47:0] + (in_opcode[`LSU_SMRD_IMM_POS] ? (in_imm_value0 * 4) : in_scalar_source_b);
out_gm_or_lds <= 1'b0;
end
`LSU_DS_FORMAT:
begin
out_ld_st_addr <= ds_address;
out_gm_or_lds <= 1'b1;
end
`LSU_MTBUF_FORMAT:
begin
// We suffer a architectural limitation here wherein we cannot support
// both an offset and index value as inputs into the address
// calculation, as that would require two vector register reads
// instead of the one that we currently do. Proposed future solution
// is to have the LSU be able to utilize two read ports to the VGPR to
// facilitate two reads in a cycle instead of just one.
out_ld_st_addr <= ({in_opcode[`LSU_MTBUF_IDXEN_POS],in_opcode[`LSU_MTBUF_OFFEN_POS]} == 2'b11) ? {2048{1'bx}} : mtbuf_address;
out_gm_or_lds <= 1'b0;
end
default:
begin
out_ld_st_addr <= {2048{1'bx}};
out_gm_or_lds <= 1'b0;
end
endcase
end
mtbuf_addr_calc mtbuf_address_calc[63:0](
.out_addr(mtbuf_address),
.vector_source_b(in_vector_source_b),
.scalar_source_a(in_scalar_source_a),
.scalar_source_b(in_scalar_source_b),
.imm_value0(in_imm_value0),
.idx_en(in_opcode[`LSU_MTBUF_IDXEN_POS]),
.off_en(in_opcode[`LSU_MTBUF_OFFEN_POS]),
.tid(thread_id)
);
ds_addr_calc ds_address_calc[63:0](
.lds_base(in_lds_base),
.in_addr(in_vector_source_b),
.out_addr(ds_address)
);
// %%start_veriperl
// my $i;
// my $high;
// my $low;
// for($i=0; $i<64; $i=$i+1)
// {
// $high = (($i+1)*6) - 1;
// $low = $i * 6;
// print "assign thread_id[$high:$low] = `ADD_TID_ENABLE ? 6'd$i : 6'd0;\n";
// }
// %%stop_veriperl
assign thread_id[5:0] = `ADD_TID_ENABLE ? 6'd0 : 6'd0;
assign thread_id[11:6] = `ADD_TID_ENABLE ? 6'd1 : 6'd0;
assign thread_id[17:12] = `ADD_TID_ENABLE ? 6'd2 : 6'd0;
assign thread_id[23:18] = `ADD_TID_ENABLE ? 6'd3 : 6'd0;
assign thread_id[29:24] = `ADD_TID_ENABLE ? 6'd4 : 6'd0;
assign thread_id[35:30] = `ADD_TID_ENABLE ? 6'd5 : 6'd0;
assign thread_id[41:36] = `ADD_TID_ENABLE ? 6'd6 : 6'd0;
assign thread_id[47:42] = `ADD_TID_ENABLE ? 6'd7 : 6'd0;
assign thread_id[53:48] = `ADD_TID_ENABLE ? 6'd8 : 6'd0;
assign thread_id[59:54] = `ADD_TID_ENABLE ? 6'd9 : 6'd0;
assign thread_id[65:60] = `ADD_TID_ENABLE ? 6'd10 : 6'd0;
assign thread_id[71:66] = `ADD_TID_ENABLE ? 6'd11 : 6'd0;
assign thread_id[77:72] = `ADD_TID_ENABLE ? 6'd12 : 6'd0;
assign thread_id[83:78] = `ADD_TID_ENABLE ? 6'd13 : 6'd0;
assign thread_id[89:84] = `ADD_TID_ENABLE ? 6'd14 : 6'd0;
assign thread_id[95:90] = `ADD_TID_ENABLE ? 6'd15 : 6'd0;
assign thread_id[101:96] = `ADD_TID_ENABLE ? 6'd16 : 6'd0;
assign thread_id[107:102] = `ADD_TID_ENABLE ? 6'd17 : 6'd0;
assign thread_id[113:108] = `ADD_TID_ENABLE ? 6'd18 : 6'd0;
assign thread_id[119:114] = `ADD_TID_ENABLE ? 6'd19 : 6'd0;
assign thread_id[125:120] = `ADD_TID_ENABLE ? 6'd20 : 6'd0;
assign thread_id[131:126] = `ADD_TID_ENABLE ? 6'd21 : 6'd0;
assign thread_id[137:132] = `ADD_TID_ENABLE ? 6'd22 : 6'd0;
assign thread_id[143:138] = `ADD_TID_ENABLE ? 6'd23 : 6'd0;
assign thread_id[149:144] = `ADD_TID_ENABLE ? 6'd24 : 6'd0;
assign thread_id[155:150] = `ADD_TID_ENABLE ? 6'd25 : 6'd0;
assign thread_id[161:156] = `ADD_TID_ENABLE ? 6'd26 : 6'd0;
assign thread_id[167:162] = `ADD_TID_ENABLE ? 6'd27 : 6'd0;
assign thread_id[173:168] = `ADD_TID_ENABLE ? 6'd28 : 6'd0;
assign thread_id[179:174] = `ADD_TID_ENABLE ? 6'd29 : 6'd0;
assign thread_id[185:180] = `ADD_TID_ENABLE ? 6'd30 : 6'd0;
assign thread_id[191:186] = `ADD_TID_ENABLE ? 6'd31 : 6'd0;
assign thread_id[197:192] = `ADD_TID_ENABLE ? 6'd32 : 6'd0;
assign thread_id[203:198] = `ADD_TID_ENABLE ? 6'd33 : 6'd0;
assign thread_id[209:204] = `ADD_TID_ENABLE ? 6'd34 : 6'd0;
assign thread_id[215:210] = `ADD_TID_ENABLE ? 6'd35 : 6'd0;
assign thread_id[221:216] = `ADD_TID_ENABLE ? 6'd36 : 6'd0;
assign thread_id[227:222] = `ADD_TID_ENABLE ? 6'd37 : 6'd0;
assign thread_id[233:228] = `ADD_TID_ENABLE ? 6'd38 : 6'd0;
assign thread_id[239:234] = `ADD_TID_ENABLE ? 6'd39 : 6'd0;
assign thread_id[245:240] = `ADD_TID_ENABLE ? 6'd40 : 6'd0;
assign thread_id[251:246] = `ADD_TID_ENABLE ? 6'd41 : 6'd0;
assign thread_id[257:252] = `ADD_TID_ENABLE ? 6'd42 : 6'd0;
assign thread_id[263:258] = `ADD_TID_ENABLE ? 6'd43 : 6'd0;
assign thread_id[269:264] = `ADD_TID_ENABLE ? 6'd44 : 6'd0;
assign thread_id[275:270] = `ADD_TID_ENABLE ? 6'd45 : 6'd0;
assign thread_id[281:276] = `ADD_TID_ENABLE ? 6'd46 : 6'd0;
assign thread_id[287:282] = `ADD_TID_ENABLE ? 6'd47 : 6'd0;
assign thread_id[293:288] = `ADD_TID_ENABLE ? 6'd48 : 6'd0;
assign thread_id[299:294] = `ADD_TID_ENABLE ? 6'd49 : 6'd0;
assign thread_id[305:300] = `ADD_TID_ENABLE ? 6'd50 : 6'd0;
assign thread_id[311:306] = `ADD_TID_ENABLE ? 6'd51 : 6'd0;
assign thread_id[317:312] = `ADD_TID_ENABLE ? 6'd52 : 6'd0;
assign thread_id[323:318] = `ADD_TID_ENABLE ? 6'd53 : 6'd0;
assign thread_id[329:324] = `ADD_TID_ENABLE ? 6'd54 : 6'd0;
assign thread_id[335:330] = `ADD_TID_ENABLE ? 6'd55 : 6'd0;
assign thread_id[341:336] = `ADD_TID_ENABLE ? 6'd56 : 6'd0;
assign thread_id[347:342] = `ADD_TID_ENABLE ? 6'd57 : 6'd0;
assign thread_id[353:348] = `ADD_TID_ENABLE ? 6'd58 : 6'd0;
assign thread_id[359:354] = `ADD_TID_ENABLE ? 6'd59 : 6'd0;
assign thread_id[365:360] = `ADD_TID_ENABLE ? 6'd60 : 6'd0;
assign thread_id[371:366] = `ADD_TID_ENABLE ? 6'd61 : 6'd0;
assign thread_id[377:372] = `ADD_TID_ENABLE ? 6'd62 : 6'd0;
assign thread_id[383:378] = `ADD_TID_ENABLE ? 6'd63 : 6'd0;
endmodule |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram7 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[7]),
.D (sw[7]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram6 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[6]),
.D (sw[8]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram5 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[5]),
.D (sw[9]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[4]),
.D (sw[10]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[3]),
.D (sw[14]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram2 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[2]),
.D (sw[13]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram1 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[1]),
.D (sw[12]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram0 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[0]),
.D (sw[11]),
.WE (sw[15])
);
assign led[15:8] = { 8{&sw[15:5]} };
assign tx = rx;
endmodule |
module sky130_fd_sc_hdll__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ls__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module affine_block_ieee754_fp_multiplier_0_0(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule |
module or1200_genpc(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_rty_i, icpu_adr_i,
// Internal i/f
branch_op, except_type, except_prefix,
branch_addrofs, lr_restor, flag, taken, except_start,
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
genpc_freeze, genpc_stop_prefetch, no_more_dslot
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input icpu_rty_i;
input [31:0] icpu_adr_i;
//
// Internal i/f
//
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
input except_prefix;
input [31:2] branch_addrofs;
input [31:0] lr_restor;
input flag;
output taken;
input except_start;
input [31:2] binsn_addr;
input [31:0] epcr;
input [31:0] spr_dat_i;
input spr_pc_we;
input genpc_refetch;
input genpc_stop_prefetch;
input genpc_freeze;
input no_more_dslot;
//
// Internal wires and regs
//
reg [31:2] pcreg;
reg [31:0] pc;
reg taken; /* Set to in case of jump or taken branch */
reg genpc_refetch_r;
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
//
// genpc_freeze_r
//
always @(posedge clk or posedge rst)
if (rst)
genpc_refetch_r <= #1 1'b0;
else if (genpc_refetch)
genpc_refetch_r <= #1 1'b1;
else
genpc_refetch_r <= #1 1'b0;
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix ) begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 30'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
pc = {branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
pc = lr_restor;
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_BF}:
if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
pc = {pcreg + 30'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_BNF}:
if (flag) begin
pc = {pcreg + 30'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
taken = 1'b0;
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
pc = epcr;
taken = 1'b1;
end
{2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
taken = 1'b1;
end
default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
pc = spr_dat_i;
taken = 1'b0;
end
endcase
end
//
// PC register
//
//always @(posedge clk or posedge rst) // asynch reset causes latches to be generated
always @(posedge clk)
if (rst)
pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
else if (spr_pc_we)
pcreg <= #1 spr_dat_i[31:2];
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
pcreg <= #1 pc[31:2];
endmodule |
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule |
module custom(
input RESET,
input CLK,
input [2:0] COL,
output [3:0] ROW,
output OPEN,
output [255:0] W,
output [7:0] DEBUG
);
nand(OPEN,W[240],W[242]);
nand(ROW[0],W[9],W[9]);
nand(ROW[1],W[8],W[8]);
nand(ROW[2],W[6],W[6]);
nand(ROW[3],W[2],W[2]);
nand(W[0],CLK,CLK);
nand(W[1],W[0],W[0]);
nand(W[2],W[3],W[4]);
nand(W[3],W[198],W[200]);
nand(W[4],W[205],W[207]);
nand(W[5],W[3],W[3]);
nand(W[6],W[5],W[4]);
nand(W[7],W[4],W[4]);
nand(W[8],W[3],W[7]);
nand(W[9],W[5],W[7]);
nand(W[10],RESET,RESET);
nand(W[11],COL[0],COL[0]);
nand(W[12],COL[1],COL[1]);
nand(W[13],COL[2],COL[2]);
nand(W[14],W[13],W[12]);
nand(W[15],W[14],W[14]);
nand(W[16],W[15],W[11]);
nand(W[17],W[16],W[10]);
nand(W[18],W[17],W[17]);
nand(W[19],W[20],W[20]);
nand(W[20],W[191],W[193]);
nand(W[21],W[16],W[19]);
nand(W[22],W[21],W[21]);
nand(W[23],W[24],W[25]);
nand(W[24],W[233],W[235]);
nand(W[25],W[226],W[228]);
nand(W[26],W[23],W[23]);
nand(W[27],COL[2],W[12]);
nand(W[28],W[27],W[27]);
nand(W[29],W[28],W[26]);
nand(W[30],W[29],W[29]);
nand(W[31],W[32],W[33]);
nand(W[32],W[212],W[214]);
nand(W[33],W[219],W[221]);
nand(W[34],W[31],W[31]);
nand(W[35],W[34],ROW[1]);
nand(W[36],W[35],W[35]);
nand(W[37],W[36],W[10]);
nand(W[38],W[37],W[37]);
nand(W[39],W[38],W[30]);
nand(W[40],W[39],W[39]);
nand(W[41],W[40],W[22]);
nand(W[42],W[41],W[41]);
nand(W[43],W[21],W[32]);
nand(W[44],W[15],ROW[0]);
nand(W[45],W[44],W[44]);
nand(W[46],W[33],W[33]);
nand(W[47],W[32],W[32]);
nand(W[48],W[47],W[46]);
nand(W[49],W[48],W[48]);
nand(W[50],W[49],W[26]);
nand(W[51],W[50],W[50]);
nand(W[52],W[51],W[45]);
nand(W[53],W[47],W[33]);
nand(W[54],W[53],W[53]);
nand(W[55],W[54],ROW[0]);
nand(W[56],W[55],W[55]);
nand(W[57],W[56],W[30]);
nand(W[58],W[57],W[52]);
nand(W[59],W[58],W[58]);
nand(W[60],W[25],W[25]);
nand(W[61],W[24],W[60]);
nand(W[62],W[61],W[61]);
nand(W[63],W[62],W[45]);
nand(W[64],W[63],W[63]);
nand(W[65],W[64],W[47]);
nand(W[66],W[65],W[59]);
nand(W[67],W[66],W[66]);
nand(W[68],W[13],COL[1]);
nand(W[69],W[68],W[68]);
nand(W[70],W[69],ROW[2]);
nand(W[71],W[70],W[70]);
nand(W[72],W[24],W[24]);
nand(W[73],W[72],W[25]);
nand(W[74],W[73],W[73]);
nand(W[75],W[74],W[49]);
nand(W[76],W[75],W[75]);
nand(W[77],W[76],W[71]);
nand(W[78],W[72],W[60]);
nand(W[79],W[78],W[78]);
nand(W[80],W[79],W[49]);
nand(W[81],W[80],W[80]);
nand(W[82],W[81],W[71]);
nand(W[83],W[82],W[77]);
nand(W[84],W[83],W[83]);
nand(W[85],W[74],W[15]);
nand(W[86],W[85],W[85]);
nand(W[87],W[54],ROW[2]);
nand(W[88],W[87],W[87]);
nand(W[89],W[88],W[86]);
nand(W[90],W[79],W[54]);
nand(W[91],W[90],W[90]);
nand(W[92],W[91],W[45]);
nand(W[93],W[92],W[89]);
nand(W[94],W[93],W[93]);
nand(W[95],W[94],W[84]);
nand(W[96],W[95],W[95]);
nand(W[97],W[96],W[67]);
nand(W[98],W[97],W[22]);
nand(W[99],W[98],W[43]);
nand(W[100],W[99],W[10]);
nand(W[101],W[100],W[100]);
nand(W[102],W[21],W[33]);
nand(W[103],W[15],W[25]);
nand(W[104],W[103],W[103]);
nand(W[105],W[32],W[46]);
nand(W[106],W[105],W[105]);
nand(W[107],W[106],ROW[0]);
nand(W[108],W[107],W[107]);
nand(W[109],W[108],W[104]);
nand(W[110],W[62],W[54]);
nand(W[111],W[110],W[110]);
nand(W[112],W[111],W[45]);
nand(W[113],W[112],W[57]);
nand(W[114],W[113],W[113]);
nand(W[115],W[114],W[109]);
nand(W[116],W[115],W[115]);
nand(W[117],W[62],W[15]);
nand(W[118],W[117],W[117]);
nand(W[119],W[106],ROW[2]);
nand(W[120],W[119],W[119]);
nand(W[121],W[120],W[118]);
nand(W[122],W[28],W[72]);
nand(W[123],W[122],W[122]);
nand(W[124],W[123],W[120]);
nand(W[125],W[124],W[121]);
nand(W[126],W[125],W[125]);
nand(W[127],W[126],W[94]);
nand(W[128],W[127],W[127]);
nand(W[129],W[128],W[116]);
nand(W[130],W[129],W[22]);
nand(W[131],W[130],W[102]);
nand(W[132],W[131],W[10]);
nand(W[133],W[132],W[132]);
nand(W[134],W[21],W[25]);
nand(W[135],W[69],W[62]);
nand(W[136],W[135],W[135]);
nand(W[137],W[136],W[36]);
nand(W[138],W[137],W[109]);
nand(W[139],W[138],W[138]);
nand(W[140],W[139],W[59]);
nand(W[141],W[140],W[140]);
nand(W[142],W[15],ROW[2]);
nand(W[143],W[142],W[142]);
nand(W[144],W[79],W[34]);
nand(W[145],W[144],W[144]);
nand(W[146],W[145],W[143]);
nand(W[147],W[77],W[89]);
nand(W[148],W[147],W[147]);
nand(W[149],W[148],W[146]);
nand(W[150],W[149],W[149]);
nand(W[151],W[150],W[141]);
nand(W[152],W[151],W[22]);
nand(W[153],W[152],W[134]);
nand(W[154],W[153],W[10]);
nand(W[155],W[154],W[154]);
nand(W[156],W[21],W[24]);
nand(W[157],W[26],W[15]);
nand(W[158],W[157],W[157]);
nand(W[159],W[108],W[158]);
nand(W[160],W[159],W[121]);
nand(W[161],W[160],W[160]);
nand(W[162],W[86],W[36]);
nand(W[163],W[162],W[137]);
nand(W[164],W[163],W[163]);
nand(W[165],W[164],W[161]);
nand(W[166],W[165],W[165]);
nand(W[167],W[166],W[67]);
nand(W[168],W[167],W[22]);
nand(W[169],W[168],W[156]);
nand(W[170],W[169],W[10]);
nand(W[171],W[170],W[170]);
nand(W[172],W[16],W[16]);
nand(W[173],W[19],W[5]);
nand(W[174],W[173],W[172]);
nand(W[175],W[16],W[5]);
nand(W[176],W[175],W[10]);
nand(W[177],W[176],W[176]);
nand(W[178],W[177],W[174]);
nand(W[179],W[178],W[178]);
nand(W[180],W[174],W[4]);
nand(W[181],ROW[1],W[19]);
nand(W[182],W[181],W[181]);
nand(W[183],W[182],W[172]);
nand(W[184],W[183],W[180]);
nand(W[185],W[184],W[10]);
nand(W[186],W[185],W[185]);
nand(W[187],W[0],W[18]);
nand(W[188],W[0],W[187]);
nand(W[189],W[188],W[190]);
nand(W[190],W[187],W[189]);
nand(W[191],W[1],W[190]);
nand(W[192],W[1],W[191]);
nand(W[193],W[192],W[20]);
nand(W[194],W[0],W[179]);
nand(W[195],W[0],W[194]);
nand(W[196],W[195],W[197]);
nand(W[197],W[194],W[196]);
nand(W[198],W[1],W[197]);
nand(W[199],W[1],W[198]);
nand(W[200],W[199],W[3]);
nand(W[201],W[0],W[186]);
nand(W[202],W[0],W[201]);
nand(W[203],W[202],W[204]);
nand(W[204],W[201],W[203]);
nand(W[205],W[1],W[204]);
nand(W[206],W[1],W[205]);
nand(W[207],W[206],W[4]);
nand(W[208],W[0],W[101]);
nand(W[209],W[0],W[208]);
nand(W[210],W[209],W[211]);
nand(W[211],W[208],W[210]);
nand(W[212],W[1],W[211]);
nand(W[213],W[1],W[212]);
nand(W[214],W[213],W[32]);
nand(W[215],W[0],W[133]);
nand(W[216],W[0],W[215]);
nand(W[217],W[216],W[218]);
nand(W[218],W[215],W[217]);
nand(W[219],W[1],W[218]);
nand(W[220],W[1],W[219]);
nand(W[221],W[220],W[33]);
nand(W[222],W[0],W[155]);
nand(W[223],W[0],W[222]);
nand(W[224],W[223],W[225]);
nand(W[225],W[222],W[224]);
nand(W[226],W[1],W[225]);
nand(W[227],W[1],W[226]);
nand(W[228],W[227],W[25]);
nand(W[229],W[0],W[171]);
nand(W[230],W[0],W[229]);
nand(W[231],W[230],W[232]);
nand(W[232],W[229],W[231]);
nand(W[233],W[1],W[232]);
nand(W[234],W[1],W[233]);
nand(W[235],W[234],W[24]);
nand(W[236],W[0],W[42]);
nand(W[237],W[0],W[236]);
nand(W[238],W[237],W[239]);
nand(W[239],W[236],W[238]);
nand(W[240],W[1],W[239]);
nand(W[241],W[1],W[240]);
nand(W[242],W[241],OPEN);
assign DEBUG = {ROW[3:0],COL[2:0],CLK};
assign W[243] = 1;
assign W[244] = RESET;
assign W[245] = CLK;
assign W[249:246] = ROW;
assign W[252:250] = COL;
assign W[253] = OPEN;
assign W[254] = OPEN;
assign W[255] = OPEN;
endmodule |
module sky130_fd_sc_hd__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module alink_slave(
// system clock and reset
input clk ,
input rst ,
// wishbone interface signals
input ALINK_CYC_I ,//NC
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,//NC
input [2:0] ALINK_CTI_I ,//NC
input [1:0] ALINK_BTE_I ,//NC
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,//NC
output reg ALINK_ACK_O ,
output ALINK_ERR_O ,//const 0
output ALINK_RTY_O ,//const 0
output reg [31:0] ALINK_DAT_O ,
output reg txfifo_push ,
output reg [31:0] txfifo_din ,
input [9:0] rxcnt ,
input rxempty ,
input [10:0] txcnt ,
output reg_flush ,
input txfull ,
output reg [31:0] reg_mask ,
output reg reg_scan ,
input [31:0] busy ,
output rxfifo_pop ,
input [31:0] rxfifo_dout
);
parameter ALINK_TXFIFO = 6'h00 ;
parameter ALINK_STATE = 6'h04 ;
parameter ALINK_MASK = 6'h08 ;
parameter ALINK_BUSY = 6'h0c ;
parameter ALINK_RXFIFO = 6'h10 ;
//-----------------------------------------------------
// WB bus ACK
//-----------------------------------------------------
always @ ( posedge clk or posedge rst ) begin
if( rst )
ALINK_ACK_O <= 1'b0 ;
else if( ALINK_STB_I && (~ALINK_ACK_O) )
ALINK_ACK_O <= 1'b1 ;
else
ALINK_ACK_O <= 1'b0 ;
end
//-----------------------------------------------------
// ADDR MUX
//-----------------------------------------------------
wire alink_txfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_txfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_state_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_state_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_mask_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_mask_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_busy_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_busy_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_rxfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
wire alink_rxfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
//-----------------------------------------------------
// Register.txfifo
//-----------------------------------------------------
always @ ( posedge clk ) begin
txfifo_push <= alink_txfifo_wr_en ;
txfifo_din <= ALINK_DAT_I ;
end
//-----------------------------------------------------
// Register.state
//-----------------------------------------------------
reg [3:0] reg_flush_r ;
wire [31:0] rd_state = {reg_scan,1'b0,rxcnt[9:0],3'b0,rxempty,
1'b0,txcnt[10:0],2'b0,reg_flush,txfull} ;
always @ ( posedge clk ) begin
if( alink_state_wr_en )
reg_flush_r <= {3'b0,ALINK_DAT_I[1]} ;
else
reg_flush_r <= reg_flush_r << 1 ;
end
always @ ( posedge clk ) begin
if( rst )
reg_scan <= 1'b0 ;
else if( alink_state_wr_en )
reg_scan <= ALINK_DAT_I[31] ;
end
assign reg_flush = |reg_flush_r ;
//-----------------------------------------------------
// Register.mask
//-----------------------------------------------------
always @ ( posedge clk ) begin
if( alink_mask_wr_en )
reg_mask <= ALINK_DAT_I ;
end
//-----------------------------------------------------
// Register.busy
//-----------------------------------------------------
wire [31:0] rd_busy = busy[31:0] ;
//-----------------------------------------------------
// Register.rxfifo
//-----------------------------------------------------
wire [31:0] rd_rxfifo = rxfifo_dout[31:0] ;
//-----------------------------------------------------
// WB read
//-----------------------------------------------------
assign rxfifo_pop = alink_rxfifo_rd_en ;
always @ ( posedge clk ) begin
case( 1'b1 )
alink_state_rd_en : ALINK_DAT_O <= rd_state ;
alink_busy_rd_en : ALINK_DAT_O <= rd_busy ;
alink_rxfifo_rd_en : ALINK_DAT_O <= rd_rxfifo ;
default: ALINK_DAT_O <= 32'hdeaddead ;
endcase
end
endmodule |