module_content
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module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i or negedge rst_i)
//always @(posedge wb_clk_i)//Bob: Here the ack is X by default, so add the rst here
if (!rst_i)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
//default: ; //Bob: here have a lint warning, so commented it out
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule |
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule |
module xilinx_v6_pcie_wrapper
(
// Outputs
trn_terr_drop_n, trn_tdst_rdy_n, trn_tcfg_req_n, trn_tbuf_av,
trn_rsrc_rdy_n, trn_rsrc_dsc_n, trn_rsof_n, trn_rrem_n,
trn_reset_n, trn_rerrfwd_n, trn_reof_n, trn_rd, trn_rbar_hit_n,
trn_lnk_up_n, trn_fc_ph, trn_fc_pd, trn_fc_nph, trn_fc_npd,
trn_fc_cplh, trn_fc_cpld, trn_clk, trn2_clk, pl_sel_link_width,
pl_sel_link_rate, pl_received_hot_rst, pl_ltssm_state,
pl_link_upcfg_capable, pl_link_partner_gen2_supported,
pl_link_gen2_capable, pl_lane_reversal_mode,
pl_initial_link_width, pci_exp_txn, pci_exp_txp,
cfg_to_turnoff_n, cfg_status, cfg_rd_wr_done_n, cfg_pmcsr_powerstate,
cfg_pmcsr_pme_status, cfg_pmcsr_pme_en, cfg_pcie_link_state_n,
cfg_lstatus, cfg_lcommand, cfg_interrupt_rdy_n,
cfg_interrupt_msixfm, cfg_interrupt_msixenable,
cfg_interrupt_msienable, cfg_interrupt_mmenable, cfg_interrupt_do,
cfg_function_number, cfg_err_cpl_rdy_n, cfg_dstatus, cfg_do,
cfg_device_number, cfg_dcommand2, cfg_dcommand, cfg_command,
cfg_bus_number,
// Inputs
trn_tstr_n, trn_tsrc_rdy_n, trn_tsrc_dsc_n, trn_tsof_n,
trn_trem_n, trn_terrfwd_n, trn_teof_n, trn_td, trn_tcfg_gnt_n,
trn_rnp_ok_n, trn_rdst_rdy_n, trn_fc_sel, sys_reset_n, sys_clk,
pl_upstream_prefer_deemph, pl_directed_link_width,
pl_directed_link_speed, pl_directed_link_change,
pl_directed_link_auton, pci_exp_rxp, pci_exp_rxn, cfg_wr_en_n,
cfg_turnoff_ok_n, cfg_trn_pending_n, cfg_rd_en_n, cfg_pm_wake_n,
cfg_interrupt_n, cfg_interrupt_di, cfg_interrupt_assert_n,
cfg_err_ur_n, cfg_err_tlp_cpl_header, cfg_err_posted_n,
cfg_err_locked_n, cfg_err_ecrc_n, cfg_err_cpl_unexpect_n,
cfg_err_cpl_timeout_n, cfg_err_cpl_abort_n, cfg_err_cor_n,
cfg_dwaddr, cfg_dsn, cfg_di, cfg_byte_en_n
);
// synthesis attribute keep of trn_clk is "true";
// synthesis attribute keep of trn2_clk is "true";
// synthesis attribute keep of trn_reset_n is "true";
// synthesis attribute keep of trn_fc_ph is "true";
// synthesis attribute keep of trn_fc_pd is "true";
// synthesis attribute keep of trn_fc_nph is "true";
// synthesis attribute keep of trn_fc_npd is "true";
// synthesis attribute keep of trn_fc_cplh is "true";
// synthesis attribute keep of trn_fc_cpld is "true";
// synthesis attribute keep of trn_fc_sel is "true";
// synthesis attribute keep of trn_tsof_n is "true";
// synthesis attribute keep of trn_teof_n is "true";
// synthesis attribute keep of trn_td is "true";
// synthesis attribute keep of trn_trem_n is "true";
// synthesis attribute keep of trn_tsrc_rdy_n is "true";
// synthesis attribute keep of trn_tdst_rdy_n is "true";
// synthesis attribute keep of trn_tsrc_dsc_n is "true";
// synthesis attribute keep of trn_tbuf_av is "true";
// synthesis attribute keep of trn_terr_drop_n is "true";
// synthesis attribute keep of trn_tstr_n is "true";
// synthesis attribute keep of trn_tcfg_req_n is "true";
// synthesis attribute keep of trn_tcfg_gnt_n is "true";
// synthesis attribute keep of trn_terrfwd_n is "true";
// synthesis attribute keep of trn_rsof_n is "true";
// synthesis attribute keep of trn_reof_n is "true";
// synthesis attribute keep of trn_rd is "true";
// synthesis attribute keep of trn_rrem_n is "true";
// synthesis attribute keep of trn_rerrfwd_n is "true";
// synthesis attribute keep of trn_rsrc_rdy_n is "true";
// synthesis attribute keep of trn_rdst_rdy_n is "true";
// synthesis attribute keep of trn_rsrc_dsc_n is "true";
// synthesis attribute keep of trn_rnp_ok_n is "true";
// synthesis attribute keep of trn_rbar_hit_n is "true";
// synthesis attribute keep of trn_lnk_up_n is "true";
parameter PL_FAST_TRAIN = "FALSE";
input [3:0] cfg_byte_en_n; // To endpoint of pcie_endpoint.v
input [31:0] cfg_di; // To endpoint of pcie_endpoint.v
input [63:0] cfg_dsn; // To endpoint of pcie_endpoint.v
input [9:0] cfg_dwaddr; // To endpoint of pcie_endpoint.v
input cfg_err_cor_n; // To endpoint of pcie_endpoint.v
input cfg_err_cpl_abort_n; // To endpoint of pcie_endpoint.v
input cfg_err_cpl_timeout_n; // To endpoint of pcie_endpoint.v
input cfg_err_cpl_unexpect_n; // To endpoint of pcie_endpoint.v
input cfg_err_ecrc_n; // To endpoint of pcie_endpoint.v
input cfg_err_locked_n; // To endpoint of pcie_endpoint.v
input cfg_err_posted_n; // To endpoint of pcie_endpoint.v
input [47:0] cfg_err_tlp_cpl_header; // To endpoint of pcie_endpoint.v
input cfg_err_ur_n; // To endpoint of pcie_endpoint.v
input cfg_interrupt_assert_n; // To endpoint of pcie_endpoint.v
input [7:0] cfg_interrupt_di; // To endpoint of pcie_endpoint.v
input cfg_interrupt_n; // To endpoint of pcie_endpoint.v
input cfg_pm_wake_n; // To endpoint of pcie_endpoint.v
input cfg_rd_en_n; // To endpoint of pcie_endpoint.v
input cfg_trn_pending_n; // To endpoint of pcie_endpoint.v
input cfg_turnoff_ok_n; // To endpoint of pcie_endpoint.v
input cfg_wr_en_n; // To endpoint of pcie_endpoint.v
//input [7:0] pci_exp_rxn; // To endpoint of pcie_endpoint.v
//input [7:0] pci_exp_rxp; // To endpoint of pcie_endpoint.v
input [3:0] pci_exp_rxn; // To endpoint of pcie_endpoint.v
input [3:0] pci_exp_rxp; // To endpoint of pcie_endpoint.v
input pl_directed_link_auton; // To endpoint of pcie_endpoint.v
input [1:0] pl_directed_link_change;// To endpoint of pcie_endpoint.v
input pl_directed_link_speed; // To endpoint of pcie_endpoint.v
input [1:0] pl_directed_link_width; // To endpoint of pcie_endpoint.v
input pl_upstream_prefer_deemph;// To endpoint of pcie_endpoint.v
input sys_clk; // To endpoint of pcie_endpoint.v
input sys_reset_n; // To endpoint of pcie_endpoint.v
input [2:0] trn_fc_sel; // To endpoint of pcie_endpoint.v
input trn_rdst_rdy_n; // To endpoint of pcie_endpoint.v
input trn_rnp_ok_n; // To endpoint of pcie_endpoint.v
input trn_tcfg_gnt_n; // To endpoint of pcie_endpoint.v
input [63:0] trn_td; // To endpoint of pcie_endpoint.v
input trn_teof_n; // To endpoint of pcie_endpoint.v
input trn_terrfwd_n; // To endpoint of pcie_endpoint.v
input trn_trem_n; // To endpoint of pcie_endpoint.v
input trn_tsof_n; // To endpoint of pcie_endpoint.v
input trn_tsrc_dsc_n; // To endpoint of pcie_endpoint.v
input trn_tsrc_rdy_n; // To endpoint of pcie_endpoint.v
input trn_tstr_n; // To endpoint of pcie_endpoint.v
output [7:0] cfg_bus_number; // From endpoint of pcie_endpoint.v
output [15:0] cfg_command; // From endpoint of pcie_endpoint.v
output [15:0] cfg_dcommand; // From endpoint of pcie_endpoint.v
output [15:0] cfg_dcommand2; // From endpoint of pcie_endpoint.v
output [4:0] cfg_device_number; // From endpoint of pcie_endpoint.v
output [31:0] cfg_do; // From endpoint of pcie_endpoint.v
output [15:0] cfg_dstatus; // From endpoint of pcie_endpoint.v
output cfg_err_cpl_rdy_n; // From endpoint of pcie_endpoint.v
output [2:0] cfg_function_number; // From endpoint of pcie_endpoint.v
output [7:0] cfg_interrupt_do; // From endpoint of pcie_endpoint.v
output [2:0] cfg_interrupt_mmenable; // From endpoint of pcie_endpoint.v
output cfg_interrupt_msienable;// From endpoint of pcie_endpoint.v
output cfg_interrupt_msixenable;// From endpoint of pcie_endpoint.v
output cfg_interrupt_msixfm; // From endpoint of pcie_endpoint.v
output cfg_interrupt_rdy_n; // From endpoint of pcie_endpoint.v
output [15:0] cfg_lcommand; // From endpoint of pcie_endpoint.v
output [15:0] cfg_lstatus; // From endpoint of pcie_endpoint.v
output [2:0] cfg_pcie_link_state_n; // From endpoint of pcie_endpoint.v
output cfg_pmcsr_pme_en; // From endpoint of pcie_endpoint.v
output cfg_pmcsr_pme_status; // From endpoint of pcie_endpoint.v
output [1:0] cfg_pmcsr_powerstate; // From endpoint of pcie_endpoint.v
output cfg_rd_wr_done_n; // From endpoint of pcie_endpoint.v
output [15:0] cfg_status; // From endpoint of pcie_endpoint.v
output cfg_to_turnoff_n; // From endpoint of pcie_endpoint.v
//output [7:0] pci_exp_txn; // From endpoint of pcie_endpoint.v
//output [7:0] pci_exp_txp; // From endpoint of pcie_endpoint.v
output [3:0] pci_exp_txn; // From endpoint of pcie_endpoint.v
output [3:0] pci_exp_txp; // From endpoint of pcie_endpoint.v
output [2:0] pl_initial_link_width; // From endpoint of pcie_endpoint.v
output [1:0] pl_lane_reversal_mode; // From endpoint of pcie_endpoint.v
output pl_link_gen2_capable; // From endpoint of pcie_endpoint.v
output pl_link_partner_gen2_supported;// From endpoint of pcie_endpoint.v
output pl_link_upcfg_capable; // From endpoint of pcie_endpoint.v
output [5:0] pl_ltssm_state; // From endpoint of pcie_endpoint.v
output pl_received_hot_rst; // From endpoint of pcie_endpoint.v
output pl_sel_link_rate; // From endpoint of pcie_endpoint.v
output [1:0] pl_sel_link_width; // From endpoint of pcie_endpoint.v
output trn_clk; // From endpoint of pcie_endpoint.v
output trn2_clk; // From endpoint of pcie_endpoint.v
output [11:0] trn_fc_cpld; // From endpoint of pcie_endpoint.v
output [7:0] trn_fc_cplh; // From endpoint of pcie_endpoint.v
output [11:0] trn_fc_npd; // From endpoint of pcie_endpoint.v
output [7:0] trn_fc_nph; // From endpoint of pcie_endpoint.v
output [11:0] trn_fc_pd; // From endpoint of pcie_endpoint.v
output [7:0] trn_fc_ph; // From endpoint of pcie_endpoint.v
output trn_lnk_up_n; // From endpoint of pcie_endpoint.v
output [6:0] trn_rbar_hit_n; // From endpoint of pcie_endpoint.v
output [63:0] trn_rd; // From endpoint of pcie_endpoint.v
output trn_reof_n; // From endpoint of pcie_endpoint.v
output trn_rerrfwd_n; // From endpoint of pcie_endpoint.v
output trn_reset_n; // From endpoint of pcie_endpoint.v
output trn_rrem_n; // From endpoint of pcie_endpoint.v
output trn_rsof_n; // From endpoint of pcie_endpoint.v
output trn_rsrc_dsc_n; // From endpoint of pcie_endpoint.v
output trn_rsrc_rdy_n; // From endpoint of pcie_endpoint.v
output [5:0] trn_tbuf_av; // From endpoint of pcie_endpoint.v
output trn_tcfg_req_n; // From endpoint of pcie_endpoint.v
output trn_tdst_rdy_n; // From endpoint of pcie_endpoint.v
output trn_terr_drop_n; // From endpoint of pcie_endpoint.v
// endpoint instance
v6_pcie_v1_5 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN )
)
ep
(
// Outputs
.pci_exp_txn (pci_exp_txn),
.pci_exp_txp (pci_exp_txp),
.trn_clk (trn_clk),
.drp_clk (trn2_clk) , //use MMCM for clock divide 125 MHz
.trn_reset_n (trn_reset_n),
.trn_lnk_up_n (trn_lnk_up_n),
.trn_tbuf_av (trn_tbuf_av),
.trn_tcfg_req_n (trn_tcfg_req_n),
.trn_terr_drop_n (trn_terr_drop_n),
.trn_tdst_rdy_n (trn_tdst_rdy_n),
.trn_rd (trn_rd),
.trn_rrem_n (trn_rrem_n),
.trn_rsof_n (trn_rsof_n),
.trn_reof_n (trn_reof_n),
.trn_rsrc_rdy_n (trn_rsrc_rdy_n),
.trn_rsrc_dsc_n (trn_rsrc_dsc_n),
.trn_rerrfwd_n (trn_rerrfwd_n),
.trn_rbar_hit_n (trn_rbar_hit_n),
.trn_fc_cpld (trn_fc_cpld),
.trn_fc_cplh (trn_fc_cplh),
.trn_fc_npd (trn_fc_npd),
.trn_fc_nph (trn_fc_nph),
.trn_fc_pd (trn_fc_pd),
.trn_fc_ph (trn_fc_ph),
.cfg_do (cfg_do),
.cfg_rd_wr_done_n (cfg_rd_wr_done_n),
.cfg_err_cpl_rdy_n (cfg_err_cpl_rdy_n),
.cfg_interrupt_rdy_n (cfg_interrupt_rdy_n),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_to_turnoff_n (cfg_to_turnoff_n),
.cfg_bus_number (cfg_bus_number),
.cfg_device_number (cfg_device_number),
.cfg_function_number (cfg_function_number),
.cfg_status (cfg_status),
.cfg_command (cfg_command),
.cfg_dstatus (cfg_dstatus),
.cfg_dcommand (cfg_dcommand),
.cfg_lstatus (cfg_lstatus),
.cfg_lcommand (cfg_lcommand),
.cfg_dcommand2 (cfg_dcommand2),
.cfg_pcie_link_state_n (cfg_pcie_link_state_n),
.cfg_pmcsr_pme_en (cfg_pmcsr_pme_en),
.cfg_pmcsr_pme_status (cfg_pmcsr_pme_status),
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate),
.pl_initial_link_width (pl_initial_link_width),
.pl_lane_reversal_mode (pl_lane_reversal_mode),
.pl_link_gen2_capable (pl_link_gen2_capable),
.pl_link_partner_gen2_supported (pl_link_partner_gen2_supported),
.pl_link_upcfg_capable (pl_link_upcfg_capable),
.pl_ltssm_state (pl_ltssm_state),
.pl_received_hot_rst (pl_received_hot_rst),
.pl_sel_link_rate (pl_sel_link_rate),
.pl_sel_link_width (pl_sel_link_width),
// Inputs
.pci_exp_rxp (pci_exp_rxp),
.pci_exp_rxn (pci_exp_rxn),
.trn_td (trn_td),
.trn_trem_n (trn_trem_n),
.trn_tsof_n (trn_tsof_n),
.trn_teof_n (trn_teof_n),
.trn_tsrc_rdy_n (trn_tsrc_rdy_n),
.trn_tsrc_dsc_n (trn_tsrc_dsc_n),
.trn_terrfwd_n (trn_terrfwd_n),
.trn_tcfg_gnt_n (trn_tcfg_gnt_n),
.trn_tstr_n (trn_tstr_n),
.trn_rdst_rdy_n (trn_rdst_rdy_n),
.trn_rnp_ok_n (trn_rnp_ok_n),
.trn_fc_sel (trn_fc_sel),
.cfg_di (cfg_di),
.cfg_byte_en_n (cfg_byte_en_n),
.cfg_dwaddr (cfg_dwaddr),
.cfg_wr_en_n (cfg_wr_en_n),
.cfg_rd_en_n (cfg_rd_en_n),
.cfg_err_cor_n (cfg_err_cor_n),
.cfg_err_ur_n (cfg_err_ur_n),
.cfg_err_ecrc_n (cfg_err_ecrc_n),
.cfg_err_cpl_timeout_n (cfg_err_cpl_timeout_n),
.cfg_err_cpl_abort_n (cfg_err_cpl_abort_n),
.cfg_err_cpl_unexpect_n (cfg_err_cpl_unexpect_n),
.cfg_err_posted_n (cfg_err_posted_n),
.cfg_err_locked_n (cfg_err_locked_n),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header),
.cfg_interrupt_n (cfg_interrupt_n),
.cfg_interrupt_assert_n (cfg_interrupt_assert_n),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_turnoff_ok_n (cfg_turnoff_ok_n),
.cfg_trn_pending_n (cfg_trn_pending_n),
.cfg_pm_wake_n (cfg_pm_wake_n),
.cfg_dsn (cfg_dsn),
.pl_directed_link_auton (pl_directed_link_auton),
.pl_directed_link_change (pl_directed_link_change),
.pl_directed_link_speed (pl_directed_link_speed),
.pl_directed_link_width (pl_directed_link_width),
.pl_upstream_prefer_deemph (pl_upstream_prefer_deemph),
.sys_clk (sys_clk),
.sys_reset_n (sys_reset_n));
endmodule |
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_logic_analyzer s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule |
module sky130_fd_sc_lp__sdfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__sdfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule |
module CPU
(
clk_i,
rst_i,
start_i,
mem_data_i,
mem_ack_i,
mem_data_o,
mem_addr_o,
mem_enable_o,
mem_write_o
);
//input
input clk_i;
input rst_i;
input start_i;
//
// to Data Memory interface
//
input [256-1:0] mem_data_i;
input mem_ack_i;
output [256-1:0] mem_data_o;
output [32-1:0] mem_addr_o;
output mem_enable_o;
output mem_write_o;
//
// add your project1 here!
//
PC PC
(
.clk_i(clk_i),
.rst_i(rst_i),
.start_i(start_i),
.stall_i(),
.pcEnable_i(),
.pc_i(),
.pc_o()
);
Instruction_Memory Instruction_Memory(
.addr_i(),
.instr_o()
);
Registers Registers(
.clk_i(clk_i),
.RSaddr_i(),
.RTaddr_i(),
.RDaddr_i(),
.RDdata_i(),
.RegWrite_i(),
.RSdata_o(),
.RTdata_o()
);
//data cache
dcache_top dcache
(
// System clock, reset and stall
.clk_i(clk_i),
.rst_i(rst_i),
// to Data Memory interface
.mem_data_i(mem_data_i),
.mem_ack_i(mem_ack_i),
.mem_data_o(mem_data_o),
.mem_addr_o(mem_addr_o),
.mem_enable_o(mem_enable_o),
.mem_write_o(mem_write_o),
// to CPU interface
.p1_data_i(),
.p1_addr_i(),
.p1_MemRead_i(),
.p1_MemWrite_i(),
.p1_data_o(),
.p1_stall_o()
);
endmodule |
module hps_design_SMP_HPS_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [1:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
hps_design_SMP_HPS_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule |
module fifo_four(clk,rstp,din,readp,writep,dout,emptyp,fullp);
input clk; //时钟
input rstp; //复位
input[15:0]din; //16位输入信号
input readp; //读指令
input writep; //写指令
output[15:0]dout; //16位输出信号
output emptyp; //空指示信号
output fullp; //满指示信号
parameter DEPTH=2, MAX_COUNT=2'b11; // 最大深度为4
reg[15:0]dout;
reg emptyp;
reg fullp;
reg[(DEPTH-1):0] tail; //读指针
reg[(DEPTH-1):0] head; //写指针
reg[(DEPTH-1):0] count; //计数器
reg[15:0]fifomem[0:MAX_COUNT]; //四个16位存储单元
//read
always@(posedge clk)
if(rstp == 1)
dout <= 0;
else if(readp == 1 && emptyp == 0)
dout <= fifomem[tail];
//write
always@(posedge clk)
if(rstp == 1 && writep == 1 && fullp == 0)
fifomem[head] <= din;
//更新head指针
always@(posedge clk)
if(rstp == 1)
head <= 0;
else if(writep == 1 && fullp == 0)
head<=head+1;
//更新tail指针
always@(posedge clk)
if(rstp == 1)
tail <= 0;
else if(readp == 1 && emptyp == 0)
tail <= tail+1;
//count
always@(posedge clk)
if(rstp == 1)
count< = 0;
else
case({readp,writep})
2'b00:
count <= count;
2'b01:
if(count != MAX_COUNT)
count <= count+1;
2'b10:
if(count != 0)
count <= count-1;
2'b11:
count <= count;
endcase
//更新标志位emptyp
always@(count)
if(count == 0)
emptyp <= 1;
else
emptyp <= 0;
//更新标志位tail
always@(count)
if(count == MAX_COUNT)
tail <= 1;
else
tail <= 0;
endmodule |
module regs_testbench();
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// indica o numero de testes a serem feitos
parameter N_TESTES = 11;
// contador de testes a serem feitos
integer testes;
// declaracao input / output
reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
reg signed [DATA_WIDTH-1:0] data_write;
wire signed [DATA_WIDTH-1:0] data_read1, data_read2;
// criacao das instancias
regs regs0(
.clk(clk),
.en_write(en_write),
.data_write(data_write),
.addr_write(addr_write),
.addr_read1(addr_read1),
.addr_read2(addr_read2),
.data_read1(data_read1),
.data_read2(data_read2));
// inicializando testes em 0
initial begin
testes <= 0;
// inicilizacao dos inputs
clk <= 0;
end
// gerando clock
always begin
// gere o clock quando os sinais de teste estiverem estabilizados
#2;
clk = !clk;
end
// gerandos os testes aqui
always begin
#4;
testes = testes+1;
// DESCREVA OS CASOS DE TESTE ABAIXO
case(testes)
1: begin
en_write = 1;
addr_write = 0;
data_write = 5;
addr_read1 = 0;
addr_read2 = 0;
end
2: begin
en_write = 0;
addr_write = 7;
data_write = 65;
addr_read1 = 0;
addr_read2 = 1;
end
3: begin
en_write = 1;
addr_write = 8;
data_write = 11;
addr_read1 = 0;
addr_read2 = 1;
end
4: begin
en_write = 0;
addr_write = 7;
data_write = 18;
addr_read1 = 8;
addr_read2 = 1;
end
5: begin
en_write = 1;
addr_write = 1;
data_write = 16;
addr_read1 = 0;
addr_read2 = 1;
end
6: begin
en_write = 1;
addr_write = 2;
data_write = 24;
addr_read1 = 0;
addr_read2 = 1;
end
7: begin
en_write = 0;
addr_write = 2;
data_write = 29;
addr_read1 = 1;
addr_read2 = 2;
end
8: begin
en_write = 1;
addr_write = 15;
data_write = 20;
addr_read1 = 1;
addr_read2 = 2;
end
9: begin
en_write = 0;
addr_write = 21;
data_write = 25400;
addr_read1 = 15;
addr_read2 = 0;
end
10: begin
en_write = 1;
addr_write = 31;
data_write = 2000;
addr_read1 = 15;
addr_read2 = 0;
end
11: begin
en_write = 0;
addr_write = 20;
data_write = 200;
addr_read1 = 31;
addr_read2 = 0;
end
default: begin
// nao faca nada de proposito
end
endcase
end
// mostre os resultados dos testes
always @(posedge clk) begin
if (testes > 0 && testes <= N_TESTES) begin
// aqui aparecem os resultados das entradas
$display(" Teste # %2d => ", testes);
$display("\t WRITE - EN: %b - ADDR: %3d - DATA: %6d ", en_write, addr_write, data_write);
$display("\t READ_1\n\t ADDR: %3d ", addr_read1);
$display("\t DATA: %6d ", data_read1);
$display("\t READ_2\n\t ADDR: %3d ", addr_read2);
$display("\t DATA: %6d ", data_read2);
$display(" ");
end
end
endmodule |
module mig_7series_v2_0_qdr_rld_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
reg my_empty;
reg my_full;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty, my_full})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 1'b0;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_empty <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_full <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty, my_full);
rd_ptr <= 2'bxx;
wr_ptr <= 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
wire [WIDTH-1:0] mem_out;
assign d_out = my_empty ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in & my_empty;
always @(posedge clk)
if (rst) begin
my_empty <= 1'b1;
my_full <= 1'b0;
rd_ptr <= 'b0;
wr_ptr <= 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty && !my_full && rd_en_in && !empty_in) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, ~empty_in);
end
wire wr_en;
assign wr_en = (!rd_en_in & !empty_in & !my_full)
| (rd_en_in & !empty_in & !my_empty);
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem [rd_ptr];
endmodule |
module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
input clk;
input reset; // for the arithmethic core
input sel;
input [5:0] addr;
input w;
input update; // update reg_in & reg_out
input ready; // shift reg_in & reg_out
input i;
output o;
output done;
reg [197:0] reg_in, reg_out;
wire [197:0] out;
assign o = reg_out[0];
tiny
tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
always @ (posedge clk) // write LSB firstly
if (update) reg_in <= 0;
else if (ready) reg_in <= {i,reg_in[197:1]};
always @ (posedge clk) // read LSB firstly
if (update) reg_out <= out;
else if (ready) reg_out <= reg_out>>1;
endmodule |
module BCD7segment(
input [3:0] IN,
input select,
output reg [6:0] OUT
);
always @ (IN or select)
begin
if(select)
begin
case (IN)
0: OUT = 7'b0000001;
1: OUT = 7'b1001111;
2: OUT = 7'b0010010;
3: OUT = 7'b0000110;
4: OUT = 7'b1001100;
5: OUT = 7'b0100100;
6: OUT = 7'b0100000;
7: OUT = 7'b0001111;
8: OUT = 7'b0000000;
9: OUT = 7'b0000100;
10: OUT = 7'b0001000;
11: OUT = 7'b0000000;
12: OUT = 7'b0110001;
13: OUT = 7'b0000001;
14: OUT = 7'b0110000;
15: OUT = 7'b0111000;
endcase
end
else
OUT = 7'b1111110;
end
// 4 enable switches //
endmodule |
module gtwizard_ultrascale_v1_7_1_gtye4_delay_powergood # (
parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
parameter C_PCIE_ENABLE = "FALSE"
)(
input wire GT_TXOUTCLKPCS,
input wire GT_GTPOWERGOOD,
input wire [2:0] USER_TXRATE,
input wire USER_TXRATEMODE,
input wire USER_GTTXRESET,
input wire USER_TXPMARESET,
input wire USER_TXPISOPD,
output wire USER_GTPOWERGOOD,
output wire [2:0] GT_TXRATE,
output wire GT_TXRATEMODE,
output wire GT_GTTXRESET,
output wire GT_TXPMARESET,
output wire GT_TXPISOPD
);
generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
begin : gen_powergood_nodelay
assign GT_TXPISOPD = USER_TXPISOPD;
assign GT_GTTXRESET = USER_GTTXRESET;
assign GT_TXPMARESET = USER_TXPMARESET;
assign GT_TXRATE = USER_TXRATE;
assign GT_TXRATEMODE = USER_TXRATEMODE;
assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
end
else
begin: gen_powergood_delay
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r;
reg [3:0] wait_cnt;
(* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
wire intclk_rrst_n;
wire gt_intclk;
and and1(gt_intclk, GT_TXOUTCLKPCS, !pwr_on_fsm);
//--------------------------------------------------------------------------
// POWER ON FSM Encoding
//--------------------------------------------------------------------------
localparam PWR_ON_WAIT_CNT = 4'd0;
localparam PWR_ON_DONE = 4'd1;
//--------------------------------------------------------------------------------------------------
// Reset Synchronizer
//--------------------------------------------------------------------------------------------------
always @ (posedge gt_intclk or negedge GT_GTPOWERGOOD)
begin
if (!GT_GTPOWERGOOD)
intclk_rrst_n_r <= 5'd0;
else
intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1};
end
assign intclk_rrst_n = intclk_rrst_n_r[4];
//--------------------------------------------------------------------------------------------------
// Wait counter
//--------------------------------------------------------------------------------------------------
always @ (posedge gt_intclk)
begin
if (!intclk_rrst_n)
wait_cnt <= 4'd0;
else begin
if (pwr_on_fsm == PWR_ON_WAIT_CNT)
wait_cnt <= wait_cnt + 4'd1;
else
wait_cnt <= 4'd0;
end
end
//--------------------------------------------------------------------------------------------------
// Power On FSM
//--------------------------------------------------------------------------------------------------
always @ (posedge gt_intclk or negedge GT_GTPOWERGOOD)
begin
if (!GT_GTPOWERGOOD)
begin
pwr_on_fsm <= PWR_ON_WAIT_CNT;
end
else begin
case (pwr_on_fsm)
PWR_ON_WAIT_CNT :
begin
pwr_on_fsm <= (wait_cnt[3] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
end
PWR_ON_DONE :
begin
pwr_on_fsm <= PWR_ON_DONE;
end
default :
begin
pwr_on_fsm <= PWR_ON_WAIT_CNT;
end
endcase
end
end
assign GT_TXPISOPD = pwr_on_fsm ? USER_TXPISOPD : 1'b1;
assign GT_GTTXRESET = pwr_on_fsm ? USER_GTTXRESET : !GT_GTPOWERGOOD;
assign GT_TXPMARESET = pwr_on_fsm ? USER_TXPMARESET : 1'b0;
assign GT_TXRATE = pwr_on_fsm ? USER_TXRATE : 3'b001;
assign GT_TXRATEMODE = pwr_on_fsm ? USER_TXRATEMODE : 1'b1;
assign USER_GTPOWERGOOD = pwr_on_fsm;
end
endgenerate
endmodule |
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule |
module log2_table
(
input clk, // Drawing engine clock.
input trilinear_en, // Trilinear Enable.
input [31:0] val, // Current Largest delta 23.9.
output [9:0] log2
);
reg [3:0] int_mm_no;
reg [5:0] lod_fract;
wire over_flow;
wire [9:0] log_in;
// assign log_in = val[26:17];
// assign over_flow = |val[39:27];
assign log_in = val[17:8];
assign over_flow = |val[31:18];
// 17 = 9
// 16 = 8
// 15 = 7
//
// 9 = 1
// 8 = 0
// 7 = -1
// 6 = -2
// 5 = -3
// Mipmap Number Generation
// Select Mipmap based on delta and if mipmapping is on.
// Determine the largest delta value.
// Extract LOD
always @(posedge clk) begin
// casex (largest_delta_AM2[17:8])
casex ({over_flow, log_in})
11'b0_10xxxxxxx_x, 11'b0_011xxxxxx_x: begin // 192.0 <= l < 384.0
if(trilinear_en && log_in[9]) begin
int_mm_no <= 4'h9;
lod_fract <= val[16:11];
end
else begin
int_mm_no <= 4'h8;
lod_fract <= val[15:10];
end
end
11'b0_010xxxxxx_x, 11'b0_0011xxxxx_x: begin // 96.0 <= l < 192.0
if(trilinear_en && log_in[8]) begin
int_mm_no <= 4'h8;
lod_fract <= val[15:10];
end
else begin
int_mm_no <= 4'h7;
lod_fract <= val[14:9];
end
end
11'b0_0010xxxxx_x, 11'b0_00011xxxx_x: begin // 48.0 <= l < 96.0
if(trilinear_en && log_in[7]) begin
int_mm_no <= 4'h7;
lod_fract <= val[14:9];
end
else begin
int_mm_no <= 4'h6;
lod_fract <= val[13:8];
end
end
11'b0_00010xxxx_x, 11'b0_000011xxx_x: begin // 24.0 <= l < 48.0
if(trilinear_en && log_in[6]) begin
int_mm_no <= 4'h6;
lod_fract <= val[13:8];
end
else begin
int_mm_no <= 4'h5;
lod_fract <= val[12:7];
end
end
11'b0_000010xxx_x, 11'b0_0000011xx_x: begin // 12.0 <= l < 24.0
if(trilinear_en && log_in[5]) begin
int_mm_no <= 4'h5;
lod_fract <= val[12:7];
end
else begin
int_mm_no <= 4'h4;
lod_fract <= val[11:6];
end
end
11'b0_0000010xx_x, 11'b0_00000011x_x: begin // 6.0 <= l < 12.0
if(trilinear_en && log_in[4]) begin
int_mm_no <= 4'h4;
lod_fract <= val[11:6];
end
else begin
int_mm_no <= 4'h3;
lod_fract <= val[10:5];
end
end
11'b0_00000010x_x, 11'b0_000000011_x: begin // 3.0 <= l < 6.0
if(trilinear_en && log_in[3]) begin
int_mm_no <= 4'h3;
lod_fract <= val[10:5];
end
else begin
int_mm_no <= 4'h2;
lod_fract <= val[9:4];
end
end
11'b0_000000010_x, 11'b0_000000001_1: begin // 1.5 <= l < 3.0
if(trilinear_en && log_in[2]) begin
int_mm_no <= 4'h2;
lod_fract <= val[9:4];
end
else begin
int_mm_no <= 4'h1;
lod_fract <= val[8:3];
end
end
11'b0_000000001_0, 11'b0_000000000_x: begin // 0.0 <= l < 1.5
if(trilinear_en && log_in[1]) begin
int_mm_no <= 4'h1;
lod_fract <= val[8:3];
end
else begin
int_mm_no <= 4'h0;
lod_fract <= val[7:2];
end
end
// 384.0 <= l < infinity
default: begin
int_mm_no <= 4'h9;
lod_fract <= val[16:11];
end
endcase
end
assign log2 = {int_mm_no, lod_fract};
endmodule |
module EtherPBI(
inout tri [15:0] SysAddr,
input wire Phi2,
output tri MPD,
inout tri RdWr,
output wire OE,
output wire RamCS,
output wire RomCS,
output wire [13:8] RamAddrOut,
output wire [15:10] RomAddrOut,
inout tri [7:0] Data,
inout tri Dx,
output tri IRQ,
output DmaReqOut,
input wire Halt,
input wire Reset,
input wire SpiDI,
output wire SpiDO,
output wire SpiCK,
output wire SpiCS,
output wire DeviceWr,
output wire DeviceRd,
output wire DeviceCS,
output tri EXTSEL,
input wire DeviceInt,
output wire [9:0] DeviceAddr
);
reg [13:8] RamAddr;
reg [15:10] RomAddr;
reg [3:0] DeviceBank;
reg [15:0] DmaAddr;
reg [15:0] DmaCount;
reg DmaReq;
reg DmaCycle;
reg DmaRead; /* Read from device, write to RAM if 1, Write to device, read from RAM if 0 */
reg DmaOdd;
reg DmaOddPickup; /* Blank read/write to align FIFO access */
reg Selected;
reg SpiBit;
reg SpiSel;
reg SpiClkSig;
reg [7:0] DataOut;
reg [9:0] DeviceAddrOut;
initial begin
DeviceBank = 0;
DmaAddr = 0;
DmaCount = 0;
DmaCycle = 0;
RamAddr = 0;
RomAddr = 0;
Selected = 0;
DmaReq = 0;
SpiBit = 0;
SpiSel = 0;
end
always @(negedge Phi2) begin
if (Reset == 1'b0) begin
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
end else begin
if ((DmaReq & !Halt) == 1'b1) begin
/* Just *starting* a DMA cycle */
DmaCycle <= 1'b1;
if (DmaOddPickup == 1'b1 || DmaCount == 16'h1 && DmaOdd == 1'b0) begin
/* Will be the last cycle */
DmaReq <= 0;
end
end else begin
DmaCycle <= 1'b0;
end
if (DmaCycle == 1'b1) begin
/* Just *finishing* a DMA cycle */
if (DmaOddPickup == 1'b0) begin
/* actual cycle */
if (DmaCount == 16'h1) begin
/* Last DMA cycle (maybe) */
if (DmaOdd == 1'b1) begin
/* One more cycle to align */
DmaOdd <= 0;
DmaOddPickup <= 1'b1;
end else begin
/* Next cycle is the last DMA cycle */
DmaRead <= 0;
DmaReq <= 0;
end
end
DmaAddr <= DmaAddr + 1;
DmaCount <= DmaCount - 1;
end
end else if ((Selected & RdWr) == 1'b0) begin
/* Just *finishing* a non-DMA cycle */
/* register loads */
if (SysAddr[15:6] == ('hD100 >> 6)) begin
RamAddr[13:8] <= SysAddr[5:0];
end else if (SysAddr[15:6] == ('hD140 >> 6)) begin
RomAddr[15:10] <= SysAddr[5:0];
// D180..D1BF = W5300 access
end else if (SysAddr[15:4] == ('hD1E0 >> 4)) begin
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr == 'hD1F7) begin
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1F8) begin
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1F9) begin
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1FA) begin
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1FB) begin
// initiate DMA transfer, bit 0 = R/!W
DmaRead <= Data[0];
DmaOddPickup <= 0;
DmaOdd <= DmaCount[0];
DmaReq <= 1'b1;
// D1FC = /HALT detect (read only)
end else if (SysAddr == 'hD1FD) begin
SpiSel <= Data[0]; // Write 1 to select SPI, 0 to deselect
end else if (SysAddr == 'hD1FE) begin
SpiBit <= Data[7]; // MSB first, left shift to empty register
SpiClkSig <= 1'b1;
end else if (SysAddr == 'hD1FF) begin
Selected <= Dx;
end
end
end
if (SpiBit == 1'b1) begin
SpiBit <= 0;
end
if (SpiClkSig == 1'b1) begin
SpiClkSig <= 0;
end
end
always
begin
if ((Selected & Phi2 & RdWr) == 1'b1) begin
if (SysAddr[15:0] == 'hD1F7) begin
DataOut <= DmaAddr[7:0];
end else if (SysAddr[15:0] == 'hD1F8) begin
DataOut <= DmaAddr[15:8];
end else if (SysAddr[15:0] == 'hD1F9) begin
DataOut <= DmaCount[7:0];
end else if (SysAddr[15:0] == 'hD1FA) begin
DataOut <= DmaCount[15:8];
// D1FB = DMA initiate (write only)
end else if (SysAddr == 'hD1FC) begin
DataOut <= {Halt, 7'b0000000};
// D1FD = SPI select (write only)
end else if (SysAddr == 'hD1FE) begin
DataOut <= {7'b0000000, SpiDI};
end else if (SysAddr == 'hD1FF) begin
DataOut <= 8'bzzzzzzzz;
end else if (SysAddr[15:8] == 'hD1) begin
DataOut <= 8'b00000000;
end else begin
DataOut <= 8'bzzzzzzzz;
end
end else begin
DataOut <= 8'bzzzzzzzz;
end
end
always
begin
if (DmaCycle == 1'b1) begin
if (DmaRead == 1'b1) begin
DeviceAddrOut <= {DeviceBank, 5'b10111, DmaOdd^DmaCount[0]};
end else begin
DeviceAddrOut <= {DeviceBank, 5'b11000, DmaOdd^DmaCount[0]};
end
end else begin
DeviceAddrOut <= {DeviceBank, SysAddr[5:0]};
end
end
assign SpiCK = Phi2 & (SpiClkSig | (Selected & RdWr & (SysAddr == 'hD197)));
assign SpiCS = SpiSel;
assign SpiDO = SpiBit;
assign IRQ = DeviceInt ? 1'b0 : 1'bz;
assign MPD = Selected ? 1'b0 : 1'bz;
assign OE = ~(Selected & RdWr);
assign RamAddrOut = SysAddr[8] ? RamAddr : 0;
assign RomAddrOut = SysAddr[10] ? RomAddr : 0;
assign DmaReqOut = DmaReq ? 1'b0 : 1'bz;
assign EXTSEL = DmaOddPickup | Selected & (SysAddr[15:11] == ('hD800 >> 11) || SysAddr[15:9] == ('hD600 >> 9) || SysAddr[15:8] == ('hD100 >> 8)) ? 1'b0 : 1'bz;
assign Dx = (Selected & (SysAddr == 'hD1FF) & RdWr) ? ~DeviceInt : 1'bz;
assign RomCS = ~(Selected & Phi2 & (SysAddr[15:11] == ('hD800 >> 11)));
assign RamCS = ~(Selected & Phi2 & (SysAddr[15:9] == ('hD600 >> 9)));
/* HALT and SPI read registers */
assign Data[7:0] = DataOut[7:0];
assign DeviceAddr = DeviceAddrOut;
assign SysAddr = DmaCycle ? DmaAddr : 16'bz;
assign DeviceWr = ~(DmaCycle ? ~DmaRead : ~DeviceCS & ~RdWr);
assign DeviceRd = ~(DmaCycle ? DmaRead : ~DeviceCS & RdWr);
assign DeviceCS = ~(Phi2 & (DmaCycle | Selected & (SysAddr[15:6] == ('hD180 >> 6))));
assign RdWr = DmaCycle ? DmaRead : 1'bz;
endmodule |
module sky130_fd_sc_ls__maj3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__maj3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule |
module TBCTRL_2 (
input HRESETn,
input HCLK,
// input
input HREADYin,
input HREADYout,
input HWRITEin,
input HWRITEout,
input HSEL,
//input [3:0] HMASTER,
input HGRANT,
// Output
output MAPSn,
output MDPSn,
output DENn,
output SDPSn,
output SRSn
);
// Master
wire MasterReadData;
wire SlaveAddrPhaseSel;
wire MasterAddrPhaseSel;
reg MasterDataPhaseSel;
reg MRWSel;
reg reg_HGRANT;
// Slave
reg SlaveDataPhaseSel;
reg RWSel;
always@(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
reg_HGRANT<=1'd0;
else
reg_HGRANT<=HGRANT;
end
//assign DENn= MDPSn & SDPSn;
assign DENn = (MDPSn)?SDPSn:MDPSn;
// ----------------------------------------------------------
// ------ Master Control ------------------------------------
// ----------------------------------------------------------
// Control Logic
assign MAPSn = ~MasterAddrPhaseSel;
assign MDPSn = ~(MasterDataPhaseSel & MRWSel);
// Master Address Phase
//assign MasterAddrPhaseSel = (HMASTER == 4'd4)?(1'b1):(1'b0);
assign MasterAddrPhaseSel = reg_HGRANT;
// Master Data Phase
assign MasterReadData = MasterDataPhaseSel & (~MRWSel);
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
MasterDataPhaseSel <= 1'b1;
else
begin
if (HREADYin)
MasterDataPhaseSel <= MasterAddrPhaseSel ;
end
end
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
MRWSel <= 1'b0;
else
begin
if (HREADYin)
MRWSel <= HWRITEout;
end
end
//---------END MASTER CONTROL -------------------------------
// ----------------------------------------------------------
// ------ Slave Control ------------------------------------
// ----------------------------------------------------------
// Slave Address Phase
assign SlaveAddrPhaseSel = HSEL;
assign SDPSn = ~(SlaveDataPhaseSel & RWSel);
assign SRSn = ~SlaveDataPhaseSel;
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
SlaveDataPhaseSel <= 1'b1;
else
begin
if (HREADYin)
SlaveDataPhaseSel <= SlaveAddrPhaseSel ;
else
SlaveDataPhaseSel <= SlaveDataPhaseSel;
end
end
// Read Write Select
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
RWSel <= 1'b0;
else
begin
if (HREADYin)
RWSel <= ~HWRITEin ;
else
RWSel <=RWSel;
end
end
endmodule |
module system_xlconstant_0_0
(dout);
output [0:0]dout;
wire \<const1> ;
assign dout[0] = \<const1> ;
VCC VCC
(.P(\<const1> ));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module upd77c25_datram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [10:0] address_b;
input clock;
input [15:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [7:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule |
module sensor_interface_v1_0 #
(
// Users to add parameters here
parameter integer C_SYSTEM_CLOCK = 100_000_000,
parameter integer C_BUS_CLOCK = 400_000,
// User parameters ends
// THESE AREN'T USER CONFIGURABLE
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 8
)
(
// Users to add ports here
// I2C interface ports
input wire m00_iic_scl_i,
output wire m00_iic_scl_o,
output wire m00_iic_scl_t,
input wire m00_iic_sda_i,
output wire m00_iic_sda_o,
output wire m00_iic_sda_t,
input wire sync,
output wire interrupt,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
wire mm_en;
wire mm_wr;
wire [C_S00_AXI_ADDR_WIDTH-1:0] mm_addr;
wire [C_S00_AXI_DATA_WIDTH-1:0] mm_rdata;
// Instantiation of Axi Bus Interface S00_AXI
sensor_interface_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) sensor_interface_v1_0_S00_AXI_inst (
// Memory mapped interface
.clk(s00_axi_aclk),
.mm_en(mm_en),
.mm_wr(mm_wr),
.mm_addr(mm_addr),
.mm_rdata(mm_rdata),
// AXI interface
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
wire i2c_en;
wire [6:0] i2c_addr;
wire i2c_write;
wire [7:0] i2c_wdata;
wire [7:0] i2c_rdata;
wire i2c_act;
wire i2c_err;
wire i2c_next;
wire i2c_multibyte_n;
sensor_control #(
.C_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.C_SYSTEM_CLOCK(C_SYSTEM_CLOCK)
) sensor_control_inst(
// Device
.clk(s00_axi_aclk),
.rst_n(s00_axi_aresetn),
.sync(sync),
.interrupt(interrupt),
// Memory mapped interface
.mm_en(mm_en),
.mm_wr(mm_wr),
.mm_addr(mm_addr[C_S00_AXI_ADDR_WIDTH-1:2]),
.mm_rdata(mm_rdata),
// I2C interface
.en(i2c_ena),
.addr(i2c_addr),
.write(i2c_write),
.wdata(i2c_wdata),
.rdata(i2c_rdata),
.act(i2c_act),
.err(i2c_err),
.next(i2c_next),
.multibyte_n(i2c_multibyte_n)
);
i2c_master #
(
.SYSTEM_CLOCK(C_SYSTEM_CLOCK),
.BUS_CLOCK(C_BUS_CLOCK)
)
I2C_master_inst
(
.clk(s00_axi_aclk),
.rst_n(s00_axi_aresetn),
.en(i2c_ena),
.addr(i2c_addr),
.write(i2c_write),
.wdata(i2c_wdata),
.rdata(i2c_rdata),
.act(i2c_act),
.err(i2c_err),
.next(i2c_next),
.multibyte_n(i2c_multibyte_n),
.sda_i(m00_iic_sda_i),
.sda_o(m00_iic_sda_o),
.sda_t(m00_iic_sda_t),
.scl_i(m00_iic_scl_i),
.scl_o(m00_iic_scl_o),
.scl_t(m00_iic_scl_t)
);
// User logic ends
endmodule |
module ddr3_int_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module LCD(
input clk,
input rst,
input [127:0] row_A,
input [127:0] row_B,
output LCD_E,
output LCD_RS,
output LCD_RW,
output [3:0] LCD_D
);
reg lcd_inited;
reg [3:0] init_d,icode,tcode,text_d;
reg init_rs,init_rw,init_e;
reg text_rs,text_rw,text_e;
reg [23:0]init_count,text_count;
assign LCD_E=(lcd_inited)?text_e:init_e;
assign LCD_RS=(lcd_inited)?text_rs:init_rs;
assign LCD_RW=(lcd_inited)?text_rw:init_rw;
assign LCD_D=(lcd_inited)?text_d:init_d;
always@(posedge clk or posedge rst) begin
if(rst)begin
init_count<=0;
init_rs<=0;
init_rw<=1;
init_e<=0;
init_d<=0;
icode<=0;
lcd_inited<=0;
end
else if(!lcd_inited)begin
init_count<=init_count+1;
init_e<=init_count[19];
init_rw<=0;
init_rs<=0;
init_d<=icode;
case(init_count[23:20])
0:icode<=4'h3;
1:icode<=4'h3;
2:icode<=4'h3;
3:icode<=4'h2;
4:icode<=4'h2;
5:icode<=4'h8;
6:icode<=4'h0;
7:icode<=4'h6;
8:icode<=4'h0;
9:icode<=4'hC;
10:icode<=4'h0;
11:icode<=4'h1;
default:{init_rw,lcd_inited}<=2'b11;
endcase
end
end
always@(posedge clk or posedge rst)begin
if(rst)begin
text_e<=0;
text_rs<=0;
text_rw<=1;
text_count<=0;
text_d<=0;
tcode<=0;
end
else if (lcd_inited)begin
text_count<=(text_count[23:17]<68)?text_count+1:0;
text_e<=text_count[16];
text_rs<=1;
text_rw<=0;
text_d<=tcode;
case(text_count[23:17])
0:{text_rs,text_rw,tcode}<=6'b001000;
1:{text_rs,text_rw,tcode}<=6'b000000;
2:tcode<=row_A[127:124];
3:tcode<=row_A[123:120];
4:tcode<=row_A[119:116];
5:tcode<=row_A[115:112];
6:tcode<=row_A[111:108];
7:tcode<=row_A[107:104];
8:tcode<=row_A[103:100];
9:tcode<=row_A[99:96];
10:tcode<=row_A[95:92];
11:tcode<=row_A[91:88];
12:tcode<=row_A[87:84];
13:tcode<=row_A[83:80];
14:tcode<=row_A[79:76];
15:tcode<=row_A[75:72];
16:tcode<=row_A[71:68];
17:tcode<=row_A[67:64];
18:tcode<=row_A[63:60];
19:tcode<=row_A[59:56];
20:tcode<=row_A[55:52];
21:tcode<=row_A[51:48];
22:tcode<=row_A[47:44];
23:tcode<=row_A[43:40];
24:tcode<=row_A[39:36];
25:tcode<=row_A[35:32];
26:tcode<=row_A[31:28];
27:tcode<=row_A[27:24];
28:tcode<=row_A[23:20];
29:tcode<=row_A[19:16];
30:tcode<=row_A[15:12];
31:tcode<=row_A[11:8];
32:tcode<=row_A[7:4];
33:tcode<=row_A[3:0];
34:{text_rs,text_rw,tcode}<=6'b001100;
35:{text_rs,text_rw,tcode}<=6'b000000;
36:tcode<=row_B[127:124];
37:tcode<=row_B[123:120];
38:tcode<=row_B[119:116];
39:tcode<=row_B[115:112];
40:tcode<=row_B[111:108];
41:tcode<=row_B[107:104];
42:tcode<=row_B[103:100];
43:tcode<=row_B[99:96];
44:tcode<=row_B[95:92];
45:tcode<=row_B[91:88];
46:tcode<=row_B[87:84];
47:tcode<=row_B[83:80];
48:tcode<=row_B[79:76];
49:tcode<=row_B[75:72];
50:tcode<=row_B[71:68];
51:tcode<=row_B[67:64];
52:tcode<=row_B[63:60];
53:tcode<=row_B[59:56];
54:tcode<=row_B[55:52];
55:tcode<=row_B[51:48];
56:tcode<=row_B[47:44];
57:tcode<=row_B[43:40];
58:tcode<=row_B[39:36];
59:tcode<=row_B[35:32];
60:tcode<=row_B[31:28];
61:tcode<=row_B[27:24];
62:tcode<=row_B[23:20];
63:tcode<=row_B[19:16];
64:tcode<=row_B[15:12];
65:tcode<=row_B[11:8];
66:tcode<=row_B[7:4];
67:tcode<=row_B[3:0];
default:{text_rs,text_rw,tcode}<=6'h10;
endcase
end
end
endmodule |
module clock_divider(
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 8_000;
reg [63:0] count;
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
count <= 32'd0;
else if (count == (constantNumber - 32'd1))
count <= 32'd0;
else
count <= count + 32'b1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == (constantNumber - 1))
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule |
module clkgen
(
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
// TX clock
output tx_clk_o,
// JTAG clock
`ifdef SIM
input tck_pad_i,
output dbg_tck_o,
`endif
// Main memory clocks
output sdram_clk_o,
output sdram_rst_o
);
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
assign async_rst_n = rst_n_pad_i;
assign async_rst = ~async_rst_n;
// Everyone likes active-high reset signals...
assign async_rst_o = ~async_rst_n;
`ifdef SIM
assign dbg_tck_o = tck_pad_i;
`endif
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
wire pll_lock;
`ifndef SIM
pll pll0
(
.areset (async_rst),
.inclk0 (sys_clk_pad_i),
.c0 (sdram_clk_o),
.c1 (wb_clk_o),
.c2 (tx_clk_o),
.locked (pll_lock)
);
`else
assign sdram_clk_o = sys_clk_pad_i;
assign wb_clk_o = sys_clk_pad_i;
assign pll_lock = 1'b1;
`endif
assign sync_rst_n = pll_lock;
//
// Reset generation
//
//
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
// Reset generation for SDRAM controller
reg [15:0] sdram_rst_shr;
always @(posedge sdram_clk_o or posedge async_rst)
if (async_rst)
sdram_rst_shr <= 16'hffff;
else
sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
assign sdram_rst_o = sdram_rst_shr[15];
endmodule |
module sky130_fd_sc_lp__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule |
module sky130_fd_sc_hdll__inv_12 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__inv_12 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule |
module testbench;
`include "test_management.v"
reg [31:0] read_word;
wire TX;
wire RX;
wire wb_clk = clk;
wire wb_rst = reset;
soc_template dut(
// Outputs
.uart_tx(TX),
// Inputs
.clk_sys_i(clk),
.reset_sys_i(reset),
.uart_rx(RX)
);
/****************************************************************************
TEST SUPPORT
***************************************************************************/
//
// Tasks used to help test cases
//
test_tasks test_tasks();
//
// The actual test cases that are being tested
//
reg [31:0] local_mem[0:16384];
test_case test_case();
/****************************************************************************
UART 0
The WB UART16550 from opencores is used here to simulate a UART on the other end
of the cable. It will allow us to send/receive characters to the NGMCU firmware
***************************************************************************/
wire [31:0] uart0_adr;
wire [31:0] uart0_dat_o;
wire [31:0] uart0_dat_i;
wire [3:0] uart0_sel;
wire uart0_cyc;
wire uart0_stb;
wire uart0_we;
wire uart0_ack;
wire uart0_int;
uart_top uart0(
.wb_clk_i(clk),
.wb_rst_i(reset),
.wb_adr_i(uart0_adr[4:0]),
.wb_dat_o(uart0_dat_o),
.wb_dat_i(uart0_dat_i),
.wb_sel_i(uart0_sel),
.wb_cyc_i(uart0_cyc),
.wb_stb_i(uart0_stb),
.wb_we_i(uart0_we),
.wb_ack_o(uart0_ack),
.int_o(uart0_int),
.stx_pad_o(RX),
.srx_pad_i(TX),
.rts_pad_o(),
.cts_pad_i(1'b0),
.dtr_pad_o(),
.dsr_pad_i(1'b0),
.ri_pad_i(1'b0),
.dcd_pad_i(1'b0),
.baud_o()
);
wb_mast uart_master0(
.clk (clk),
.rst (reset),
.adr (uart0_adr),
.din (uart0_dat_o),
.dout(uart0_dat_i),
.cyc (uart0_cyc),
.stb (uart0_stb),
.sel (uart0_sel),
.we (uart0_we ),
.ack (uart0_ack),
.err (1'b0),
.rty (1'b0)
);
uart_tasks uart_tasks();
endmodule |
module pcie3_7x_0_gt_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lane
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 = 7'b1000000 ,
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
(
//---------- GT User Ports -----------------------------
input GT_MASTER,
input GT_GEN3,
input GT_RX_CONVERGE,
//---------- GT Clock Ports ----------------------------
input GT_CPLLPDREFCLK,
input GT_GTREFCLK0,
input GT_QPLLCLK,
input GT_QPLLREFCLK,
input GT_TXUSRCLK,
input GT_RXUSRCLK,
input GT_TXUSRCLK2,
input GT_RXUSRCLK2,
input GT_OOBCLK,
input [ 1:0] GT_TXSYSCLKSEL,
input [ 1:0] GT_RXSYSCLKSEL,
output GT_TXOUTCLK,
output GT_RXOUTCLK,
output GT_CPLLLOCK,
output GT_RXCDRLOCK,
//---------- GT Reset Ports ----------------------------
input GT_CPLLPD,
input GT_CPLLRESET,
input GT_TXUSERRDY,
input GT_RXUSERRDY,
input GT_RESETOVRD,
input GT_GTTXRESET,
input GT_GTRXRESET,
input GT_TXPMARESET,
input GT_RXPMARESET,
input GT_RXCDRRESET,
input GT_RXCDRFREQRESET,
input GT_RXDFELPMRESET,
input GT_EYESCANRESET,
input GT_TXPCSRESET,
input GT_RXPCSRESET,
input GT_RXBUFRESET,
output GT_EYESCANDATAERROR,
output GT_TXRESETDONE,
output GT_RXRESETDONE,
output GT_RXPMARESETDONE,
//---------- GT TX Data Ports --------------------------
input [31:0] GT_TXDATA,
input [ 3:0] GT_TXDATAK,
output GT_TXP,
output GT_TXN,
//---------- GT RX Data Ports --------------------------
input GT_RXN,
input GT_RXP,
output [31:0] GT_RXDATA,
output [ 3:0] GT_RXDATAK,
//---------- GT Command Ports --------------------------
input GT_TXDETECTRX,
input GT_TXELECIDLE,
input GT_TXCOMPLIANCE,
input GT_RXPOLARITY,
input [ 1:0] GT_TXPOWERDOWN,
input [ 1:0] GT_RXPOWERDOWN,
input [ 2:0] GT_TXRATE,
input [ 2:0] GT_RXRATE,
//---------- GT Electrical Command Ports ---------------
input [ 2:0] GT_TXMARGIN,
input GT_TXSWING,
input GT_TXDEEMPH,
input GT_TXINHIBIT,
input [ 4:0] GT_TXPRECURSOR,
input [ 6:0] GT_TXMAINCURSOR,
input [ 4:0] GT_TXPOSTCURSOR,
//---------- GT Status Ports ---------------------------
output GT_RXVALID,
output GT_PHYSTATUS,
output GT_RXELECIDLE,
output [ 2:0] GT_RXSTATUS,
output [ 2:0] GT_RXBUFSTATUS,
output GT_TXRATEDONE,
output GT_RXRATEDONE,
output [7:0] GT_RXDISPERR,
output [7:0] GT_RXNOTINTABLE,
//---------- GT DRP Ports ------------------------------
input GT_DRPCLK,
input [ 8:0] GT_DRPADDR,
input GT_DRPEN,
input [15:0] GT_DRPDI,
input GT_DRPWE,
output [15:0] GT_DRPDO,
output GT_DRPRDY,
//---------- GT TX Sync Ports --------------------------
input [15:0] GT_PCSRSVDIN,
input GT_TXPHALIGN,
input GT_TXPHALIGNEN,
input GT_TXPHINIT,
input GT_TXDLYBYPASS,
input GT_TXDLYSRESET,
input GT_TXDLYEN,
output GT_TXDLYSRESETDONE,
output GT_TXPHINITDONE,
output GT_TXPHALIGNDONE,
input GT_TXPHDLYRESET,
input GT_TXSYNCMODE, // GTH
input GT_TXSYNCIN, // GTH
input GT_TXSYNCALLIN, // GTH
output GT_TXSYNCOUT, // GTH
output GT_TXSYNCDONE, // GTH
//---------- GT RX Sync Ports --------------------------
input GT_RXPHALIGN,
input GT_RXPHALIGNEN,
input GT_RXDLYBYPASS,
input GT_RXDLYSRESET,
input GT_RXDLYEN,
input GT_RXDDIEN,
output GT_RXDLYSRESETDONE,
output GT_RXPHALIGNDONE,
input GT_RXSYNCMODE, // GTH
input GT_RXSYNCIN, // GTH
input GT_RXSYNCALLIN, // GTH
output GT_RXSYNCOUT, // GTH
output GT_RXSYNCDONE, // GTH
//---------- GT Comma Alignment Ports ------------------
input GT_RXSLIDE,
output GT_RXCOMMADET,
output [ 3:0] GT_RXCHARISCOMMA,
output GT_RXBYTEISALIGNED,
output GT_RXBYTEREALIGN,
//---------- GT Channel Bonding Ports ------------------
input GT_RXCHBONDEN,
input [ 4:0] GT_RXCHBONDI,
input [ 2:0] GT_RXCHBONDLEVEL,
input GT_RXCHBONDMASTER,
input GT_RXCHBONDSLAVE,
output GT_RXCHANISALIGNED,
output [ 4:0] GT_RXCHBONDO,
//---------- GT PRBS/Loopback Ports --------------------
input [ 2:0] GT_TXPRBSSEL,
input [ 2:0] GT_RXPRBSSEL,
input GT_TXPRBSFORCEERR,
input GT_RXPRBSCNTRESET,
input [ 2:0] GT_LOOPBACK,
output GT_RXPRBSERR,
//---------- GT Debug Ports ----------------------------
output [14:0] GT_DMONITOROUT,
input TXPDELECIDLEMODE,
input POWERDOWN
);
//---------- Internal Signals --------------------------
wire [ 2:0] txoutclksel;
wire [ 2:0] rxoutclksel;
wire [63:0] rxdata;
wire [ 7:0] rxdatak;
wire [ 7:0] rxchariscomma;
wire rxlpmen;
wire [14:0] dmonitorout;
wire dmonitorclk;
wire cpllpd;
wire cpllrst;
wire txpdelecidlemode_mux;
//---------- Select CPLL and Clock Dividers ------------
localparam CPLL_REFCLK_DIV = 1;
localparam CPLL_FBDIV_45 = 5;
localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 :
(PCIE_REFCLK_FREQ == 1) ? 4 : 5;
localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2;
localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 :
(PCIE_REFCLK_FREQ == 1) ? 5 : 4;
//---------- Select IES vs. GES ------------------------
localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1;
//---------- Select GTP CPLL configuration -------------
// PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units
// PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000
// (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100
// (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100
// (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100
// (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100
// (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100
// (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000
//---------- Select GTX CPLL configuration -------------
// CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units
// CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (9/3=3) = 1010_0100_0000_0111_1100_1100
//------------------------------------------------------
localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC;
//---------- Select TX XCLK ----------------------------
// TXOUT for TX Buffer Use
// TXUSR for TX Buffer Bypass
//------------------------------------------------------
localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR";
//---------- Select TX Receiver Detection Configuration
localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 :
(PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100;
localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011;
localparam SIM_VERSION = "2.0";
//localparam SIM_VERSION = (PCIE_SIM_MODE == "FALSE") ? PCIE_USE_MODE : "2.0";
//---------- Select PCS_RSVD_ATTR ----------------------
// [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer
// [1]: 1 = enable manual TX sync, 0 = enable auto TX sync
// [2]: 1 = enable manual RX sync, 0 = enable auto RX sync
// [3]: 1 = select external clock for OOB 0 = select reference clock for OOB
// [6]: 1 = enable DMON 0 = disable DMON
// [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle
// [8]: 1 = power up OOB 0 = power down OOB
//------------------------------------------------------
localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX
localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP
localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7};
//---------- Select RXCDR_CFG --------------------------
//---------- GTX Note ----------------------------------
// For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin
// Async 72'h03_8000_23FF_1040_0020
// Sync: 72'h03_0000_23FF_1040_0020
//------------------------------------------------------
localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ?
((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000
: 72'h11_07FE_4060_0104_0000): // IES setting
((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 //
: 72'h03_0000_23FF_1020_0020); // optimized for GES silicon
localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ?
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010
: 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018
: 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon
localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010
: 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon
//---------- Select TX and RX Sync Mode ----------------
localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
//---------- Select Clock Correction Min and Max Latency
// CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11)
// = 13 when PCIE_LANE = 1
// CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1
// = CLK_COR_MIN_LAT + 2
//------------------------------------------------------
//---------- CLK_COR_MIN_LAT Look-up Table -------------
// Lane | One-Hop | Daisy-Chain | Binary-Tree
//------------------------------------------------------
// 0 | 13 | 13 | 13
// 1 | 15 to 18 | 15 to 18 | 15 to 18
// 2 | 15 to 18 | 17 to 18 | 15 to 18
// 3 | 15 to 18 | 19 | 17 to 18
// 4 | 15 to 18 | 21 | 17 to 18
// 5 | 15 to 18 | 23 | 19
// 6 | 15 to 18 | 25 | 19
// 7 | 15 to 18 | 27 | 21
//------------------------------------------------------
localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) :
((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) :
((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) :
((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) :
((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) :
((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18;
localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2;
//---------- Simulation Speedup ------------------------
//localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK
//localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK
//---------- Select [TX/RX]OUTCLK ----------------------
assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0;
assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0;
//---------- Select DFE vs. LPM ------------------------
// Gen1/2 = Use LPM by default. Option to use DFE.
// Gen3 = Use DFE by default. Option to use LPM.
//------------------------------------------------------
assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0);
assign txpdelecidlemode_mux = (POWERDOWN) ? TXPDELECIDLEMODE : 1'b0;
pcie3_7x_0_gtx_cpllpd_ovrd cpllPDInst (
.i_ibufds_gte2(GT_CPLLPDREFCLK),
.o_cpllpd_ovrd(cpllpd),
.o_cpllreset_ovrd(cpllrst));
//---------- Generate DMONITOR Clock Buffer for Debug ------
generate if (PCIE_DEBUG_MODE == 1)
begin : dmonitorclk_i
//---------- DMONITOR CLK ------------------------------
BUFG dmonitorclk_i
(
//---------- Input ---------------------------------
.I (dmonitorout[7]),
//---------- Output --------------------------------
.O (dmonitorclk)
);
end
else
begin : dmonitorclk_i_disable
assign dmonitorclk = 1'd0;
end
endgenerate
//---------- Select GTX or GTH or GTP ------------------------------------------
// Notes : Attributes that are commented out always use the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTP")
begin : gtp_channel
//---------- GTP Channel Module --------------------------------------------
(* SET_SPEEDUP_SIM_TRUE = "TRUE"*)
GTPE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
//.TX_CLKMUX_EN ( 1'b1), // GTP rename
//.RX_CLKMUX_EN ( 1'b1), // GTP rename
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
//.OUTREFCLK_SEL_INV ( 2'b11), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME ( 5'b00001), //
.RXPCSRESET_TIME ( 5'b00001), //
.TXPMARESET_TIME ( 5'b00011), //
.RXPMARESET_TIME ( 5'b00011), // Optimized for sim
//.RXISCANRESET_TIME ( 5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim
.TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTP
//---------- Status Attributes -----------------------------------------
//.RX_SIG_VALID_DLY ( 4), // CHECK
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up
//---------- PMA Attributes -------------------------------------------
//.CLK_COMMON_SWING ( 1'b0), // GTP new
//.PMA_RSV (32'd0), //
.PMA_RSV2 (32'h00002040), // Optimized for GES
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits
//.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit
//.PMA_RSV6 ( 1'd0), // GTP new
//.PMA_RSV7 ( 1'd0), // GTP new
.RX_BIAS_CFG (16'h0F33), // Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Optimized for IES
//---------- TX PI ----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), //
//.TXPI_CFG1 ( 2'd0), //
//.TXPI_CFG2 ( 2'd0), //
//.TXPI_CFG3 ( 1'd0), //
//.TXPI_CFG4 ( 1'd0), //
//.TXPI_CFG5 ( 3'd000), //
//.TXPI_GREY_SEL ( 1'd0), //
//.TXPI_INVSTROBE_SEL ( 1'd0), //
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), //
//.TXPI_PPM_CFG ( 8'd0), //
//.TXPI_SYNFREQ_PPM ( 3'd0), //
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES
.RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
.RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
//---------- CDR Attributes ---------------------------------------------
//.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK
.RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
//.RXLPMRESET_TIME ( 7'b0001111), // GTP new
//.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new
.RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES
//.RXLPM_CFG1 ( 1'b0), // GTP new
//.RXLPM_CM_CFG ( 1'b0), // GTP new
.RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES
.RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES
//.RXLPM_HF_CFG (14'b00001111110000), //
.RXLPM_HF_CFG2 ( 5'b01010), // GTP new
//.RXLPM_HF_CFG3 ( 4'b0000), // GTP new
.RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new
.RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES
.RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES
//.RXLPM_LF_CFG (18'b000000001111110000), //
.RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES
.RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // CHECK
.RXOSCALRESET_TIME (5'b00011), // Optimized for IES
.RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'b0), //
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("FALSE"), //
//.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
.TXDLY_CFG (16'h001F), //
.TXDLY_LCFG ( 9'h030), //
.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), //
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), //
.TXSYNC_SKIP_DA (1'b0), //
//---------- RX Sync Attributes ----------------------------------------
.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
.RXDLY_CFG (16'h001F), //
.RXDLY_LCFG ( 9'h030), //
.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), //
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), //
.RXSYNC_SKIP_DA (1'b0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE (4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE ( 3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes ---------------------------------
.LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes --------------------------------------
.TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_PLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), //
.RX_DEBUG_CFG (14'h0000), // Optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
//---------- GTP -------------------------------------------------------
//.ACJTAG_DEBUG_MODE (1'd0), //
//.ACJTAG_MODE (1'd0), //
//.ACJTAG_RESET (1'd0), //
//.ADAPT_CFG0 (20'd0), //
.CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES
.CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES
.CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES
.CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES
)
gtpe2_channel_i
(
//---------- Clock -----------------------------------------------------
.PLL0CLK (GT_QPLLCLK), //
.PLL1CLK (1'd0), //
.PLL0REFCLK (GT_QPLLREFCLK), //
.PLL1REFCLK (1'd0), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CLKRSVD0 (1'd0), //
.CLKRSVD1 (1'd0), //
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
//---------- Reset -----------------------------------------------------
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA (GT_TXDATA), //
.TXCHARISK (GT_TXDATAK), //
.GTPTXP (GT_TXP), // GTP
.GTPTXN (GT_TXN), // GTP
//---------- RX Data ---------------------------------------------------
.GTPRXP (GT_RXP), // GTP
.GTPRXN (GT_RXN), // GTP
.RXDATA (rxdata[31:0]), //
.RXCHARISK (rxdatak[3:0]), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits
.TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'b0), //
.RXRATEMODE (1'b0), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (GT_TXINHIBIT),//(1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMRESET ( 1'd0), // GTP new
.RXLPMOSINTNTRLEN ( 1'd0), // GTP new
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFOVRDEN ( 1'd0), //
.PMARSVDIN0 ( 1'd0), // GTP new
.PMARSVDIN1 ( 1'd0), // GTP new
.PMARSVDIN2 ( 1'd0), // GTP new
.PMARSVDIN3 ( 1'd0), // GTP new
.PMARSVDIN4 ( 1'd0), // GTP new
.GTRSVD (16'd0), //
.PMARSVDOUT0 (), // GTP new
.PMARSVDOUT1 (), // GTP new
.DMONITOROUT (dmonitorout), // GTP 15-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (GT_PCSRSVDIN),//(16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), //
.TXPIPPMOVRDEN (1'd0), //
.TXPIPPMPD (1'd0), //
.TXPIPPMSEL (1'd0), //
.TXPIPPMSTEPSIZE (5'd0), //
.TXPISOPD (1'd0), // GTP new
//---------- DFE -------------------------------------------------------
.RXDFEXYDEN (1'd0), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // Optimized for IES
.RXOSOVRDEN (1'd0), // Optimized for IES
.RXOSINTEN (1'd1), // Optimized for IES
.RXOSINTHOLD (1'd0), // Optimized for IES
.RXOSINTNTRLEN (1'd0), // Optimized for IES
.RXOSINTOVRDEN (1'd0), // Optimized for IES
.RXOSINTPD (1'd0), // GTP new, Optimized for IES
.RXOSINTSTROBE (1'd0), // Optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // Optimized for IES
.RXOSINTCFG (4'b0010), // Optimized for IES
.RXOSINTID0 (4'd0), // Optimized for IES
.RXOSINTDONE (), //
.RXOSINTSTARTED (), //
.RXOSINTSTROBEDONE (), //
.RXOSINTSTROBESTARTED (), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (GT_EYESCANDATAERROR), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), //
.TXSYNCIN (GT_TXSYNCIN), //
.TXSYNCALLIN (GT_TXSYNCALLIN), //
.TXSYNCDONE (GT_TXSYNCDONE), //
.TXSYNCOUT (GT_TXSYNCOUT), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), //
.RXSYNCIN (GT_RXSYNCIN), //
.RXSYNCALLIN (GT_RXSYNCALLIN), //
.RXSYNCDONE (GT_RXSYNCDONE), //
.RXSYNCOUT (GT_RXSYNCOUT), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN (1'd1), //
.RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXSLIDE (GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma[3:0]), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI[3:0]), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO[3:0]), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (4'd0), //
.TX8B10BEN (1'b1), // No Gen3 support in GTP
.RX8B10BEN (1'b1), // No Gen3 support in GTP
.RXDISPERR (GT_RXDISPERR), //
.RXNOTINTABLE (GT_RXNOTINTABLE), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // Optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTP -------------------------------------------------------
.RXADAPTSELTEST (14'd0), //
.DMONFIFORESET ( 1'd0), //
.DMONITORCLK (dmonitorclk), //
.RXOSCALRESET ( 1'd0), //
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTP
.TXPMARESETDONE () //
);
assign GT_CPLLLOCK = 1'b0;
end
else if (PCIE_GT_DEVICE == "GTH")
begin : gth_channel
//---------- GTH Channel Module --------------------------------------------
(* SET_SPEEDUP_SIM_TRUE = "TRUE"*)
GTHE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (SIM_VERSION), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD ( 1'b1), // GTH
.RX_CLKMUX_PD ( 1'b1), // GTH
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW
.CPLL_INIT_CFG (24'h00001E), // Optimized for IES
.CPLL_LOCK_CFG (16'h01E8), // Optimized for IES
//.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits
.TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00000080), // Optimized for IES
.PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES
//.PMA_RSV3 ( 2'h0), //
.PMA_RSV4 (15'h0008), // GTH new, Optimized for IES
//.PMA_RSV5 ( 4'h00), // GTH new
.RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES
//---------- TX PI -----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), // GTH new
//.TXPI_CFG1 ( 2'd0), // GTH new
//.TXPI_CFG2 ( 2'd0), // GTH new
//.TXPI_CFG3 ( 1'd0), // GTH new
//.TXPI_CFG4 ( 1'd0), // GTH new
//.TXPI_CFG5 ( 3'b100), // GTH new
//.TXPI_GREY_SEL ( 1'd0), // GTH new
//.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new
//.TXPI_PPM_CFG ( 8'd0), // GTH new
//.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 (2'b00), // GTH new
.RXPI_CFG1 (2'b11), // GTH new
.RXPI_CFG2 (2'b11), // GTH new
.RXPI_CFG3 (2'b11), // GTH new
.RXPI_CFG4 (1'b0), // GTH new
.RXPI_CFG5 (1'b0), // GTH new
.RXPI_CFG6 (3'b100), // GTH new
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTH), //
//.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1)
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES
//.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h0200), // Optimized for IES
.RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES
//---------- DFE Attributes --------------------------------------------
.RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES
.RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES
.RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE
.RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES
.RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES
.RX_DFE_H2_CFG (12'h000), // Optimized for IES
.RX_DFE_H3_CFG (12'h040), // Optimized for IES
.RX_DFE_H4_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H5_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES
.RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES
.RX_DFE_LPM_CFG (16'h0080), // Optimized for IES
.RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES
.RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES
.RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode
.RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES
.RX_DFE_UT_CFG (17'h03800), // Optimized for IES
.RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // Optimized for IES
.A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES
.RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES
.RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'd0), // GTH new
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("FALSE"), // Optimized for IES
.ES_HORZ_OFFSET (12'h000), // Optimized for IES
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), // GTH new
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new
.TXSYNC_SKIP_DA (1'b0), // GTH new
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), // GTH new
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new
.RXSYNC_SKIP_DA (1'b0), // GTH new
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
.TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC
//.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM
.RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0), //
//---------- GTH -------------------------------------------------------
//.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new
//.ACJTAG_MODE ( 1'd0), // GTH new
//.ACJTAG_RESET ( 1'd0), // GTH new
.ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES
.CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK
.CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES
.CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES
)
gthe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD0 (1'd0), // GTH
.CLKRSVD1 (1'd0), // GTH
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (cpllpd | GT_CPLLPD), //
.CPLLRESET (cpllrst | GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTHTXP (GT_TXP), // GTH
.GTHTXN (GT_TXN), // GTH
//---------- RX Data ---------------------------------------------------
.GTHRXP (GT_RXP), // GTH
.GTHRXN (GT_RXN), // GTH
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( txpdelecidlemode_mux ), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'd0), // GTH
.RXRATEMODE (1'd0), // GTH
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (GT_TXINHIBIT),//(1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1111), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), // ***
.RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMHFOVRDEN (1'd0), //
.RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMLFKLOVRDEN (1'd0), //
.TXQPIBIASEN (1'd0), //
.TXQPISTRONGPDOWN (1'd0), //
.TXQPIWEAKPUP (1'd0), //
.RXQPIEN (1'd0), // Optimized for IES
.PMARSVDIN (5'd0), //
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout), // GTH 15-bits.
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (GT_PCSRSVDIN),//(16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), // GTH new
.TXPIPPMOVRDEN (1'd0), // GTH new
.TXPIPPMPD (1'd0), // GTH new
.TXPIPPMSEL (1'd0), // GTH new
.TXPIPPMSTEPSIZE (5'd0), // GTH new
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFETAP6HOLD (1'd0), // GTH new
.RXDFETAP6OVRDEN (1'd0), // GTH new
.RXDFETAP7HOLD (1'd0), // GTH new
.RXDFETAP7OVRDEN (1'd0), // GTH new
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFEAGCOVRDEN (rxlpmen), //
.RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFELFOVRDEN (1'd0), //
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd1), // Optimized for IES
.RXMONITORSEL (2'd0), //
.RXDFESLIDETAP (5'd0), // GTH new
.RXDFESLIDETAPID (6'd0), // GTH new
.RXDFESLIDETAPHOLD (1'd0), // GTH new
.RXDFESLIDETAPOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPSTROBE (1'd0), // GTH new
.RXMONITOROUT (), //
.RXDFESLIDETAPSTARTED (), // GTH new
.RXDFESLIDETAPSTROBEDONE (), // GTH new
.RXDFESLIDETAPSTROBESTARTED (), // GTH new
.RXDFESTADAPTDONE (), // GTH new
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // optimized for IES
.RXOSOVRDEN (1'd0), // optimized for IES
.RXOSINTEN (1'd1), // GTH new, optimized for IES
.RXOSINTHOLD (1'd0), // GTH new, optimized for IES
.RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES
.RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTSTROBE (1'd0), // GTH new, optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTCFG (4'b0110), // GTH new, optimized for IES
.RXOSINTID0 (4'b0000), // GTH new, optimized for IES
.RXOSCALRESET ( 1'd0), // GTH, optimized for IES
.RSOSINTDONE (), // GTH new
.RXOSINTSTARTED (), // GTH new
.RXOSINTSTROBEDONE (), // GTH new
.RXOSINTSTROBESTARTED (), // GTH new
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (GT_EYESCANDATAERROR), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), // GTH
.TXSYNCIN (GT_TXSYNCIN), // GTH
.TXSYNCALLIN (GT_TXSYNCALLIN), // GTH
.TXSYNCDONE (GT_TXSYNCDONE), // GTH
.TXSYNCOUT (GT_TXSYNCOUT), // GTH
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), // GTH
.RXSYNCIN (GT_RXSYNCIN), // GTH
.RXSYNCALLIN (GT_RXSYNCALLIN), // GTH
.RXSYNCDONE (GT_RXSYNCDONE), // GTH
.RXSYNCOUT (GT_RXSYNCOUT), // GTH
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (GT_RXDISPERR), //
.RXNOTINTABLE (GT_RXNOTINTABLE), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS & Loopback -------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTH -------------------------------------------------------
.RXADAPTSELTEST (14'd0), // GTH new
.DMONFIFORESET ( 1'd0), // GTH
.DMONITORCLK (dmonitorclk), // GTH, optimized for debug
//.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTH
.TXPMARESETDONE () // GTH
);
end
else
begin : gtx_channel
//---------- GTX Channel Module --------------------------------------------
(* SET_SPEEDUP_SIM_TRUE = "TRUE"*)
GTXE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD (CLKMUX_PD), // GTX
.RX_CLKMUX_PD (CLKMUX_PD), // GTX
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (CPLL_CFG), // Optimized for silicon
//.CPLL_INIT_CFG (24'h00001E), //
//.CPLL_LOCK_CFG (16'h01E8), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF (TX_RXDETECT_REF), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 3'b010), // Select 800mV
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTX
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (PCS_RSVD_ATTR), //
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2
.PMA_RSV2 (16'h2050), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 (32'd0), // GTX 3.0 new
.RX_BIAS_CFG (12'b000000000100), // Optimized for GES
//.TERM_RCAL_CFG ( 5'b10000), //
//.TERM_RCAL_OVRD ( 1'd0), //
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTX), //
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h00F0), // Optimized for silicon
.RXLPM_LF_CFG (14'h00F0), // Optimized for silicon
//---------- DFE Attributes --------------------------------------------
//.RXDFELPMRESET_TIME ( 7'b0001111), //
.RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A
.RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES
.RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES
.RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES
.RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES
.RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES
.RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C
.RX_DFE_LPM_CFG (16'h0954), // Optimized for GES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe
.RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00
.RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES
.RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'b0000010000000), // Optimized for GES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("FALSE"), //
.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), //
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // Optimized for sim
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.RXPRBS_ERR_LOOPBACK (1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
//.RXOOB_CFG ( 7'b0000110), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), // Optimized for debug
.RX_DEBUG_CFG (12'd0) // Optimized for GES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
)
gtxe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (cpllpd | GT_CPLLPD), //
.CPLLRESET (cpllrst | GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTXTXP (GT_TXP), // GTX
.GTXTXN (GT_TXN), // GTX
//---------- RX Data ---------------------------------------------------
.GTXRXP (GT_RXP), // GTX
.GTXRXN (GT_RXN), // GTX
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (GT_TXINHIBIT),//(1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), //
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), //
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), //
.PMARSVDIN ( 5'd0), //
.PMARSVDIN2 ( 5'd0), // GTX
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (GT_PCSRSVDIN),//(16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence
.RXDFEAGCOVRDEN (1'd0), //
.RXDFELFHOLD (1'd0), //
.RXDFELFOVRDEN (1'd1), // Optimized for GES
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd0), //
.RXDFEXYDHOLD (1'd0), // GTX
.RXDFEXYDOVRDEN (1'd0), // GTX
.RXMONITORSEL (2'd0), //
.RXMONITOROUT (), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), //
.RXOSOVRDEN (1'd0), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (GT_EYESCANDATAERROR), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (1'd0), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (GT_RXDISPERR), //
.RXNOTINTABLE (GT_RXNOTINTABLE), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
.TSTOUT () // GTX
);
//---------- Default -------------------------------------------------------
assign dmonitorout[14:8] = 7'd0; // GTH GTP
assign GT_TXSYNCOUT = 1'd0; // GTH GTP
assign GT_TXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXSYNCOUT = 1'd0; // GTH GTP
assign GT_RXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXPMARESETDONE = 1'd0; // GTH GTP
end
endgenerate
//---------- GT Wrapper Outputs ------------------------------------------------
assign GT_RXDATA = rxdata [31:0];
assign GT_RXDATAK = rxdatak[ 3:0];
assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0];
assign GT_DMONITOROUT = dmonitorout;
endmodule |
module mux4to1_beh_1_tb;
// Inputs
reg [3:0] data_in;
reg [1:0] ctrl_sel;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
mux4to1_beh_1 uut (
.data_in(data_in),
.ctrl_sel(ctrl_sel),
.data_out(data_out)
);
task expect;
input exp_out;
if (data_out !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d data_in=%b, ctrl_sel=%b, data_out=%b",
$time, data_in, ctrl_sel, data_out);
$display("data_out should be %b", exp_out);
$finish;
end
else begin
$display("At time %0d data_in=%b, ctrl_sel=%b, data_out=%b",
$time, data_in, ctrl_sel, data_out);
end
endtask
initial begin
data_in = 4'b1010;
ctrl_sel = 2'b00;
#10 expect(1'b0);
ctrl_sel = 2'b01;
#10 expect(1'b1);
ctrl_sel = 2'b10;
#10 expect(1'b0);
ctrl_sel = 2'b11;
#10 expect(1'b1);
$display("TEST PASSED");
$finish;
end
endmodule |
module sky130_fd_sc_hs__or2_4 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule |
module GeAr_N16_R2_P4 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire intadd_26_CI, intadd_26_n4, intadd_26_n3, intadd_26_n2, intadd_26_n1,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42;
CMPR32X2TS intadd_26_U5 ( .A(in2[1]), .B(in1[1]), .C(intadd_26_CI), .CO(
intadd_26_n4), .S(res[1]) );
CMPR32X2TS intadd_26_U4 ( .A(in2[2]), .B(in1[2]), .C(intadd_26_n4), .CO(
intadd_26_n3), .S(res[2]) );
CMPR32X2TS intadd_26_U3 ( .A(in2[3]), .B(in1[3]), .C(intadd_26_n3), .CO(
intadd_26_n2), .S(res[3]) );
CMPR32X2TS intadd_26_U2 ( .A(in2[4]), .B(in1[4]), .C(intadd_26_n2), .CO(
intadd_26_n1), .S(res[4]) );
OAI21XLTS U2 ( .A0(n8), .A1(n7), .B0(intadd_26_n1), .Y(n5) );
OAI21XLTS U3 ( .A0(n26), .A1(n25), .B0(n34), .Y(n32) );
ADDFX1TS U4 ( .A(in2[15]), .B(in1[15]), .CI(n3), .CO(res[16]), .S(res[15])
);
OAI21X1TS U5 ( .A0(n29), .A1(n33), .B0(n28), .Y(n27) );
OAI21X1TS U6 ( .A0(n23), .A1(n22), .B0(n20), .Y(n19) );
OAI21X1TS U7 ( .A0(n15), .A1(n14), .B0(n13), .Y(n12) );
ADDFX1TS U8 ( .A(in2[14]), .B(in1[14]), .CI(n4), .CO(n3), .S(res[14]) );
OAI21X1TS U9 ( .A0(n18), .A1(n17), .B0(n26), .Y(n31) );
OAI21X1TS U10 ( .A0(n11), .A1(n10), .B0(n18), .Y(n30) );
OAI31X2TS U11 ( .A0(n33), .A1(n36), .A2(n35), .B0(n21), .Y(n37) );
NOR2X2TS U12 ( .A(in2[5]), .B(in1[5]), .Y(n7) );
CLKAND2X2TS U13 ( .A(in2[5]), .B(in1[5]), .Y(n8) );
NOR2X2TS U14 ( .A(in2[7]), .B(in1[7]), .Y(n14) );
CLKAND2X2TS U15 ( .A(in2[7]), .B(in1[7]), .Y(n15) );
NOR2X2TS U16 ( .A(in2[9]), .B(in1[9]), .Y(n22) );
CLKAND2X2TS U17 ( .A(in2[9]), .B(in1[9]), .Y(n23) );
INVX2TS U18 ( .A(in1[10]), .Y(n35) );
INVX2TS U19 ( .A(in2[10]), .Y(n36) );
NOR2X2TS U20 ( .A(in2[11]), .B(in1[11]), .Y(n33) );
CLKAND2X2TS U21 ( .A(in2[0]), .B(in1[0]), .Y(intadd_26_CI) );
AO22XLTS U22 ( .A0(in2[3]), .A1(in1[3]), .B0(in1[2]), .B1(in2[2]), .Y(n6) );
INVX2TS U23 ( .A(n7), .Y(n9) );
INVX2TS U24 ( .A(n14), .Y(n16) );
INVX2TS U25 ( .A(n22), .Y(n24) );
OAI31X1TS U26 ( .A0(n8), .A1(intadd_26_n1), .A2(n7), .B0(n5), .Y(res[5]) );
OAI31X1TS U27 ( .A0(n15), .A1(n13), .A2(n14), .B0(n12), .Y(res[7]) );
OAI31X1TS U28 ( .A0(n23), .A1(n20), .A2(n22), .B0(n19), .Y(res[9]) );
OAI31X1TS U29 ( .A0(n29), .A1(n28), .A2(n33), .B0(n27), .Y(res[11]) );
XOR2XLTS U30 ( .A(n42), .B(n41), .Y(res[13]) );
OAI2BB2XLTS U31 ( .B0(n39), .B1(n2), .A0N(in2[13]), .A1N(in1[13]), .Y(n4) );
OR2X1TS U32 ( .A(n38), .B(n37), .Y(n40) );
AOI222X1TS U33 ( .A0(in2[12]), .A1(in1[12]), .B0(in2[12]), .B1(n37), .C0(
in1[12]), .C1(n37), .Y(n2) );
INVX2TS U34 ( .A(n21), .Y(n29) );
NOR2X1TS U35 ( .A(in2[13]), .B(in1[13]), .Y(n39) );
NAND2X1TS U36 ( .A(in2[11]), .B(in1[11]), .Y(n21) );
OAI21XLTS U37 ( .A0(in2[3]), .A1(in1[3]), .B0(n6), .Y(n11) );
OAI22X1TS U38 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[4]), .B1(in1[4]), .Y(n10)
);
AOI31X1TS U39 ( .A0(in2[4]), .A1(in1[4]), .A2(n9), .B0(n8), .Y(n18) );
OAI22X1TS U40 ( .A0(in2[7]), .A1(in1[7]), .B0(in2[6]), .B1(in1[6]), .Y(n17)
);
AOI31X1TS U41 ( .A0(in2[6]), .A1(in1[6]), .A2(n16), .B0(n15), .Y(n26) );
OAI22X1TS U42 ( .A0(in2[9]), .A1(in1[9]), .B0(in2[8]), .B1(in1[8]), .Y(n25)
);
AOI31X1TS U43 ( .A0(in2[8]), .A1(in1[8]), .A2(n24), .B0(n23), .Y(n34) );
AOI2BB1XLTS U44 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_26_CI), .Y(res[0])
);
CMPR32X2TS U45 ( .A(in2[6]), .B(in1[6]), .C(n30), .CO(n13), .S(res[6]) );
CMPR32X2TS U46 ( .A(in2[8]), .B(in1[8]), .C(n31), .CO(n20), .S(res[8]) );
CMPR32X2TS U47 ( .A(in2[10]), .B(in1[10]), .C(n32), .CO(n28), .S(res[10]) );
AOI211XLTS U48 ( .A0(n36), .A1(n35), .B0(n34), .C0(n33), .Y(n38) );
AOI21X1TS U49 ( .A0(in1[13]), .A1(in2[13]), .B0(n39), .Y(n42) );
CMPR32X2TS U50 ( .A(in2[12]), .B(in1[12]), .C(n40), .CO(n41), .S(res[12]) );
initial $sdf_annotate("GeAr_N16_R2_P4_syn.sdf");
endmodule |
module sky130_fd_sc_ls__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule |
module TDP18K_FIFO (
RMODE_A,
RMODE_B,
WMODE_A,
WMODE_B,
WEN_A,
WEN_B,
REN_A,
REN_B,
CLK_A,
CLK_B,
BE_A,
BE_B,
ADDR_A,
ADDR_B,
WDATA_A,
WDATA_B,
RDATA_A,
RDATA_B,
EMPTY,
EPO,
EWM,
UNDERRUN,
FULL,
FMO,
FWM,
OVERRUN,
FLUSH,
RAM_ID,
FMODE,
PL_INIT,
PL_ENA,
PL_WEN,
PL_REN,
PL_CLK,
PL_ADDR,
PL_DATA_IN,
PL_DATA_OUT
);
parameter SYNC_FIFO = 1'b0;
parameter POWERDN = 1'b0;
parameter SLEEP = 1'b0;
parameter PROTECT = 1'b0;
parameter UPAF = 11'b0;
parameter UPAE = 11'b0;
input wire [2:0] RMODE_A;
input wire [2:0] RMODE_B;
input wire [2:0] WMODE_A;
input wire [2:0] WMODE_B;
input wire WEN_A;
input wire WEN_B;
input wire REN_A;
input wire REN_B;
(* clkbuf_sink *)
input wire CLK_A;
(* clkbuf_sink *)
input wire CLK_B;
input wire [1:0] BE_A;
input wire [1:0] BE_B;
input wire [13:0] ADDR_A;
input wire [13:0] ADDR_B;
input wire [17:0] WDATA_A;
input wire [17:0] WDATA_B;
output reg [17:0] RDATA_A;
output reg [17:0] RDATA_B;
output wire EMPTY;
output wire EPO;
output wire EWM;
output wire UNDERRUN;
output wire FULL;
output wire FMO;
output wire FWM;
output wire OVERRUN;
input wire FLUSH;
input wire [15:0] RAM_ID;
input wire FMODE;
input PL_INIT;
input PL_ENA;
input PL_WEN;
input PL_REN;
input PL_CLK;
input [31:0] PL_ADDR;
input [17:0] PL_DATA_IN;
output reg [17:0] PL_DATA_OUT;
reg [17:0] wmsk_a;
reg [17:0] wmsk_b;
wire [8:0] addr_a;
wire [8:0] addr_b;
reg [4:0] addr_a_d;
reg [4:0] addr_b_d;
wire [17:0] ram_rdata_a;
wire [17:0] ram_rdata_b;
reg [17:0] aligned_wdata_a;
reg [17:0] aligned_wdata_b;
wire ren_o;
wire [10:0] ff_raddr;
wire [10:0] ff_waddr;
wire [13:0] ram_addr_a;
wire [13:0] ram_addr_b;
wire [3:0] ram_waddr_a;
wire [3:0] ram_waddr_b;
wire preload;
wire my_id;
wire initn;
wire smux_rclk;
wire smux_wclk;
wire real_fmode;
wire [3:0] raw_fflags;
reg [1:0] fifo_rmode;
reg [1:0] fifo_wmode;
wire smux_clk_a;
wire smux_clk_b;
wire ram_ren_a;
wire ram_ren_b;
wire ram_wen_a;
wire ram_wen_b;
wire cen_a;
wire cen_b;
localparam MODE_9 = 3'b101;
always @(*) begin
fifo_rmode = (RMODE_B == MODE_9 ? 2'b10 : 2'b01);
fifo_wmode = (WMODE_A == MODE_9 ? 2'b10 : 2'b01);
end
assign my_id = (PL_ADDR[31:16] == RAM_ID) | PL_INIT;
assign preload = (PROTECT ? 1'b0 : my_id & PL_ENA);
assign smux_clk_a = (preload ? PL_CLK : CLK_A);
assign smux_clk_b = (preload ? 0 : (FMODE ? (SYNC_FIFO ? CLK_A : CLK_B) : CLK_B));
assign real_fmode = (preload ? 1'b0 : FMODE);
assign ram_ren_b = (preload ? PL_REN : (real_fmode ? ren_o : REN_B));
assign ram_wen_a = (preload ? PL_WEN : (FMODE ? ~FULL & WEN_A : WEN_A));
assign ram_ren_a = (preload ? 1'b1 : (FMODE ? 0 : REN_A));
assign ram_wen_b = (preload ? 1'b1 : (FMODE ? 1'b0 : WEN_B));
assign cen_b = ram_ren_b | ram_wen_b;
assign cen_a = ram_ren_a | ram_wen_a;
assign ram_waddr_b = (preload ? 4'b0000 : (real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B[3:0]));
assign ram_waddr_a = (preload ? 4'b0000 : (real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A[3:0]));
assign ram_addr_b = (preload ? {PL_ADDR[10:0], 3'h0} : (real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B[13:4], addr_b_d[3:0]}));
assign ram_addr_a = (preload ? {PL_ADDR[10:0], 3'h0} : (real_fmode ? {ff_waddr[10:0], 3'b000} : {ADDR_A[13:4], addr_a_d[3:0]}));
always @(posedge CLK_A) addr_a_d[3:0] <= ADDR_A[3:0];
always @(posedge CLK_B) addr_b_d[3:0] <= ADDR_B[3:0];
sram1024x18 uram(
.clk_a(smux_clk_a),
.cen_a(~cen_a),
.wen_a(~ram_wen_a),
.addr_a(ram_addr_a[13:4]),
.wmsk_a(wmsk_a),
.wdata_a(aligned_wdata_a),
.rdata_a(ram_rdata_a),
.clk_b(smux_clk_b),
.cen_b(~cen_b),
.wen_b(~ram_wen_b),
.addr_b(ram_addr_b[13:4]),
.wmsk_b(wmsk_b),
.wdata_b(aligned_wdata_b),
.rdata_b(ram_rdata_b)
);
fifo_ctl #(
.ADDR_WIDTH(11),
.FIFO_WIDTH(2)
) fifo_ctl(
.rclk(smux_clk_b),
.rst_R_n(~FLUSH),
.wclk(smux_clk_a),
.rst_W_n(~FLUSH),
.ren(REN_B),
.wen(ram_wen_a),
.depth(3'b000),
.sync(SYNC_FIFO),
.rmode(fifo_rmode),
.wmode(fifo_wmode),
.ren_o(ren_o),
.fflags({FULL, FMO, FWM, OVERRUN, EMPTY, EPO, EWM, UNDERRUN}),
.raddr(ff_raddr),
.waddr(ff_waddr),
.upaf(UPAF),
.upae(UPAE)
);
always @(*) begin : PRELOAD_DATA
if (preload & ram_ren_a)
PL_DATA_OUT = ram_rdata_a;
else
PL_DATA_OUT = PL_DATA_IN;
end
localparam MODE_1 = 3'b001;
localparam MODE_18 = 3'b110;
localparam MODE_2 = 3'b010;
localparam MODE_4 = 3'b100;
always @(*) begin : WDATA_MODE_SEL
if (ram_wen_a == 1) begin
if (preload) begin
aligned_wdata_a = PL_DATA_IN;
wmsk_a = 18'h00000;
end
else
case (WMODE_A)
MODE_18: begin
aligned_wdata_a = WDATA_A;
{wmsk_a[17], wmsk_a[15:8]} = (FMODE ? 9'h000 : (BE_A[1] ? 9'h000 : 9'h1ff));
{wmsk_a[16], wmsk_a[7:0]} = (FMODE ? 9'h000 : (BE_A[0] ? 9'h000 : 9'h1ff));
end
MODE_9: begin
aligned_wdata_a = {{2 {WDATA_A[8]}}, {2 {WDATA_A[7:0]}}};
{wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff);
{wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000);
end
MODE_4: begin
aligned_wdata_a = {2'b00, {4 {WDATA_A[3:0]}}};
wmsk_a[17:16] = 2'b11;
wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf);
wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf);
wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf);
wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf);
end
MODE_2: begin
aligned_wdata_a = {2'b00, {8 {WDATA_A[1:0]}}};
wmsk_a[17:16] = 2'b11;
wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3);
wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3);
wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3);
wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3);
wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3);
wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3);
wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3);
wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3);
end
MODE_1: begin
aligned_wdata_a = {2'b00, {16 {WDATA_A[0]}}};
wmsk_a = 18'h3ffff;
wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0;
end
default: wmsk_a = 18'h3ffff;
endcase
end
else begin
aligned_wdata_a = 18'h00000;
wmsk_a = 18'h3ffff;
end
if (ram_wen_b == 1)
case (WMODE_B)
MODE_18: begin
aligned_wdata_b = WDATA_B;
{wmsk_b[17], wmsk_b[15:8]} = (BE_B[1] ? 9'h000 : 9'h1ff);
{wmsk_b[16], wmsk_b[7:0]} = (BE_B[0] ? 9'h000 : 9'h1ff);
end
MODE_9: begin
aligned_wdata_b = {{2 {WDATA_B[8]}}, {2 {WDATA_B[7:0]}}};
{wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff);
{wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000);
end
MODE_4: begin
aligned_wdata_b = {2'b00, {4 {WDATA_B[3:0]}}};
wmsk_b[17:16] = 2'b11;
wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf);
wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf);
wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf);
wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf);
end
MODE_2: begin
aligned_wdata_b = {2'b00, {8 {WDATA_B[1:0]}}};
wmsk_b[17:16] = 2'b11;
wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3);
wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3);
wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3);
wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3);
wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3);
wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3);
wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3);
wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3);
end
MODE_1: begin
aligned_wdata_b = {2'b00, {16 {WDATA_B[0]}}};
wmsk_b = 18'h3ffff;
wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0;
end
default: wmsk_b = 18'h3ffff;
endcase
else begin
aligned_wdata_b = 18'b000000000000000000;
wmsk_b = 18'h3ffff;
end
end
always @(*) begin : RDATA_A_MODE_SEL
case (RMODE_A)
default: RDATA_A = 18'h00000;
MODE_18: RDATA_A = ram_rdata_a;
MODE_9: begin
RDATA_A[17:9] = 9'h000;
RDATA_A[8:0] = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]});
end
MODE_4: begin
RDATA_A[17:4] = 14'h0000;
case (ram_addr_a[3:2])
3: RDATA_A[3:0] = ram_rdata_a[15:12];
2: RDATA_A[3:0] = ram_rdata_a[11:8];
1: RDATA_A[3:0] = ram_rdata_a[7:4];
0: RDATA_A[3:0] = ram_rdata_a[3:0];
endcase
end
MODE_2: begin
RDATA_A[17:2] = 16'h0000;
case (ram_addr_a[3:1])
7: RDATA_A[1:0] = ram_rdata_a[15:14];
6: RDATA_A[1:0] = ram_rdata_a[13:12];
5: RDATA_A[1:0] = ram_rdata_a[11:10];
4: RDATA_A[1:0] = ram_rdata_a[9:8];
3: RDATA_A[1:0] = ram_rdata_a[7:6];
2: RDATA_A[1:0] = ram_rdata_a[5:4];
1: RDATA_A[1:0] = ram_rdata_a[3:2];
0: RDATA_A[1:0] = ram_rdata_a[1:0];
endcase
end
MODE_1: begin
RDATA_A[17:1] = 17'h00000;
RDATA_A[0] = ram_rdata_a[ram_addr_a[3:0]];
end
endcase
end
always @(*)
case (RMODE_B)
default: RDATA_B = 18'h15566;
MODE_18: RDATA_B = ram_rdata_b;
MODE_9: begin
RDATA_B[17:9] = 1'sb1;
RDATA_B[8:0] = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]});
end
MODE_4:
case (ram_addr_b[3:2])
3: RDATA_B[3:0] = ram_rdata_b[15:12];
2: RDATA_B[3:0] = ram_rdata_b[11:8];
1: RDATA_B[3:0] = ram_rdata_b[7:4];
0: RDATA_B[3:0] = ram_rdata_b[3:0];
endcase
MODE_2:
case (ram_addr_b[3:1])
7: RDATA_B[1:0] = ram_rdata_b[15:14];
6: RDATA_B[1:0] = ram_rdata_b[13:12];
5: RDATA_B[1:0] = ram_rdata_b[11:10];
4: RDATA_B[1:0] = ram_rdata_b[9:8];
3: RDATA_B[1:0] = ram_rdata_b[7:6];
2: RDATA_B[1:0] = ram_rdata_b[5:4];
1: RDATA_B[1:0] = ram_rdata_b[3:2];
0: RDATA_B[1:0] = ram_rdata_b[1:0];
endcase
MODE_1: RDATA_B[0] = ram_rdata_b[ram_addr_b[3:0]];
endcase
endmodule |
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule |
module sky130_fd_sc_hdll__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule |
module sky130_fd_sc_lp__dlybuf4s50kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule |
module sparc_exu_ecl_cnt6 (/*AUTOARG*/
// Outputs
cntr,
// Inputs
reset, clk, se
) ;
input reset;
input clk;
input se;
output [5:0] cntr;
wire [5:0] next_cntr;
wire tog1;
wire tog2;
wire tog3;
wire tog4;
wire tog5;
assign tog1 = cntr[0];
assign tog2 = cntr[0] & cntr[1];
assign tog3 = cntr[0] & cntr[1] & cntr[2];
assign tog4 = cntr[0] & cntr[1] & cntr[2] & cntr[3];
assign tog5 = cntr[0] & cntr[1] & cntr[2] & cntr[3] & cntr[4];
assign next_cntr[0] = ~reset & ~cntr[0];
assign next_cntr[1] = ~reset & ((~cntr[1] & tog1) | (cntr[1] & ~tog1));
assign next_cntr[2] = ~reset & ((~cntr[2] & tog2) | (cntr[2] & ~tog2));
assign next_cntr[3] = ~reset & ((~cntr[3] & tog3) | (cntr[3] & ~tog3));
assign next_cntr[4] = ~reset & ((~cntr[4] & tog4) | (cntr[4] & ~tog4));
assign next_cntr[5] = ~reset & ((~cntr[5] & tog5) | (cntr[5] & ~tog5));
// counter flop
dff_s #(6) cntr_dff(.din(next_cntr[5:0]), .clk(clk), .q(cntr[5:0]), .se(se), .si(), .so());
endmodule |
module ay_note_ram(addr, data);
input wire [6:0] addr;
output wire [11:0] data; //12 бит - максимум
reg [11:0] note_ram [0:127];
initial begin
note_ram[0] <= 12'd03977;
note_ram[1] <= 12'd03977;
note_ram[2] <= 12'd03977;
note_ram[3] <= 12'd03977;
note_ram[4] <= 12'd03977;
note_ram[5] <= 12'd03977;
note_ram[6] <= 12'd03977;
note_ram[7] <= 12'd03977;
note_ram[8] <= 12'd03977;
note_ram[9] <= 12'd03977;
note_ram[10] <= 12'd03977;
note_ram[11] <= 12'd03977;
note_ram[12] <= 12'd03977;
note_ram[13] <= 12'd03977;
note_ram[14] <= 12'd03977;
note_ram[15] <= 12'd03977;
note_ram[16] <= 12'd03977;
note_ram[17] <= 12'd03977;
note_ram[18] <= 12'd03977;
note_ram[19] <= 12'd03977;
note_ram[20] <= 12'd03977;
note_ram[21] <= 12'd03977;
note_ram[22] <= 12'd03754;
note_ram[23] <= 12'd03543;
note_ram[24] <= 12'd03344;
note_ram[25] <= 12'd03157;
note_ram[26] <= 12'd02980;
note_ram[27] <= 12'd02812;
note_ram[28] <= 12'd02655;
note_ram[29] <= 12'd02506;
note_ram[30] <= 12'd02365;
note_ram[31] <= 12'd02232;
note_ram[32] <= 12'd02107;
note_ram[33] <= 12'd01989;
note_ram[34] <= 12'd01877;
note_ram[35] <= 12'd01772;
note_ram[36] <= 12'd01672;
note_ram[37] <= 12'd01578;
note_ram[38] <= 12'd01490;
note_ram[39] <= 12'd01406;
note_ram[40] <= 12'd01327;
note_ram[41] <= 12'd01253;
note_ram[42] <= 12'd01182;
note_ram[43] <= 12'd01116;
note_ram[44] <= 12'd01053;
note_ram[45] <= 12'd0994;
note_ram[46] <= 12'd0939;
note_ram[47] <= 12'd0886;
note_ram[48] <= 12'd0836;
note_ram[49] <= 12'd0789;
note_ram[50] <= 12'd0745;
note_ram[51] <= 12'd0703;
note_ram[52] <= 12'd0664;
note_ram[53] <= 12'd0626;
note_ram[54] <= 12'd0591;
note_ram[55] <= 12'd0558;
note_ram[56] <= 12'd0527;
note_ram[57] <= 12'd0497;
note_ram[58] <= 12'd0469;
note_ram[59] <= 12'd0443;
note_ram[60] <= 12'd0418;
note_ram[61] <= 12'd0395;
note_ram[62] <= 12'd0372;
note_ram[63] <= 12'd0352;
note_ram[64] <= 12'd0332;
note_ram[65] <= 12'd0313;
note_ram[66] <= 12'd0296;
note_ram[67] <= 12'd0279;
note_ram[68] <= 12'd0263;
note_ram[69] <= 12'd0249;
note_ram[70] <= 12'd0235;
note_ram[71] <= 12'd0221;
note_ram[72] <= 12'd0209;
note_ram[73] <= 12'd0197;
note_ram[74] <= 12'd0186;
note_ram[75] <= 12'd0176;
note_ram[76] <= 12'd0166;
note_ram[77] <= 12'd0157;
note_ram[78] <= 12'd0148;
note_ram[79] <= 12'd0140;
note_ram[80] <= 12'd0132;
note_ram[81] <= 12'd0124;
note_ram[82] <= 12'd0117;
note_ram[83] <= 12'd0111;
note_ram[84] <= 12'd0105;
note_ram[85] <= 12'd099;
note_ram[86] <= 12'd093;
note_ram[87] <= 12'd088;
note_ram[88] <= 12'd083;
note_ram[89] <= 12'd078;
note_ram[90] <= 12'd074;
note_ram[91] <= 12'd070;
note_ram[92] <= 12'd066;
note_ram[93] <= 12'd062;
note_ram[94] <= 12'd059;
note_ram[95] <= 12'd055;
note_ram[96] <= 12'd052;
note_ram[97] <= 12'd049;
note_ram[98] <= 12'd047;
note_ram[99] <= 12'd044;
note_ram[100] <= 12'd041;
note_ram[101] <= 12'd039;
note_ram[102] <= 12'd037;
note_ram[103] <= 12'd035;
note_ram[104] <= 12'd033;
note_ram[105] <= 12'd031;
note_ram[106] <= 12'd029;
note_ram[107] <= 12'd028;
note_ram[108] <= 12'd026;
note_ram[109] <= 12'd025;
note_ram[110] <= 12'd023;
note_ram[111] <= 12'd022;
note_ram[112] <= 12'd021;
note_ram[113] <= 12'd020;
note_ram[114] <= 12'd018;
note_ram[115] <= 12'd017;
note_ram[116] <= 12'd016;
note_ram[117] <= 12'd016;
note_ram[118] <= 12'd015;
note_ram[119] <= 12'd014;
note_ram[120] <= 12'd013;
note_ram[121] <= 12'd012;
note_ram[122] <= 12'd012;
note_ram[123] <= 12'd011;
note_ram[124] <= 12'd010;
note_ram[125] <= 12'd010;
note_ram[126] <= 12'd09;
note_ram[127] <= 12'd09;
end
assign data = note_ram[addr];
endmodule |
module system_auto_us_1
(s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [127:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [127:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire NLW_inst_m_axi_awvalid_UNCONNECTED;
wire NLW_inst_m_axi_bready_UNCONNECTED;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire NLW_inst_m_axi_wvalid_UNCONNECTED;
wire NLW_inst_s_axi_awready_UNCONNECTED;
wire NLW_inst_s_axi_bvalid_UNCONNECTED;
wire NLW_inst_s_axi_wready_UNCONNECTED;
wire [31:0]NLW_inst_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [127:0]NLW_inst_m_axi_wdata_UNCONNECTED;
wire [15:0]NLW_inst_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_inst_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_IS_ACLK_ASYNC = "0" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_WRITE = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FIFO_MODE = "0" *)
(* C_MAX_SPLIT_BEATS = "16" *)
(* C_M_AXI_ACLK_RATIO = "2" *)
(* C_M_AXI_BYTES_LOG = "4" *)
(* C_M_AXI_DATA_WIDTH = "128" *)
(* C_PACKING_LEVEL = "1" *)
(* C_RATIO = "0" *)
(* C_RATIO_LOG = "0" *)
(* C_SUPPORTS_ID = "0" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_S_AXI_ACLK_RATIO = "1" *)
(* C_S_AXI_BYTES_LOG = "2" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_CONVERSION = "2" *)
(* P_MAX_SPLIT_BEATS = "16" *)
system_auto_us_1_axi_dwidth_converter_v2_1_11_top inst
(.m_axi_aclk(1'b0),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_aresetn(1'b0),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(NLW_inst_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_inst_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awvalid(NLW_inst_m_axi_awvalid_UNCONNECTED),
.m_axi_bready(NLW_inst_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_bvalid(1'b0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(NLW_inst_m_axi_wdata_UNCONNECTED[127:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_inst_m_axi_wstrb_UNCONNECTED[15:0]),
.m_axi_wvalid(NLW_inst_m_axi_wvalid_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(1'b0),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b1}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_inst_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_inst_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_inst_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b1),
.s_axi_wready(NLW_inst_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b1,1'b1,1'b1,1'b1}),
.s_axi_wvalid(1'b0));
endmodule |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer
(rd_cmd_valid,
CO,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,
\USE_RTL_LENGTH.length_counter_q_reg[7] ,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ,
E,
D,
\current_word_1_reg[3] ,
Q,
first_word_reg,
first_word_reg_0,
\s_axi_rdata[31] ,
\s_axi_rdata[31]_0 ,
s_axi_rvalid,
\M_AXI_RDATA_I_reg[127] ,
s_ready_i_reg,
m_axi_arvalid,
SR,
out,
DI,
S,
\m_payload_i_reg[50] ,
\m_payload_i_reg[51] ,
mr_rvalid,
wrap_buffer_available_reg,
use_wrap_buffer,
wrap_buffer_available,
\USE_RTL_LENGTH.length_counter_q_reg[1] ,
s_axi_rready,
\pre_next_word_1_reg[2] ,
\pre_next_word_1_reg[3] ,
\pre_next_word_1_reg[3]_0 ,
first_word,
sr_arvalid,
use_wrap_buffer_reg,
\current_word_1_reg[3]_0 ,
\current_word_1_reg[2] ,
\current_word_1_reg[3]_1 ,
first_mi_word_q,
m_axi_arready,
s_axi_aresetn,
in);
output rd_cmd_valid;
output [0:0]CO;
output [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ;
output \USE_RTL_LENGTH.length_counter_q_reg[7] ;
output \USE_RTL_LENGTH.length_counter_q_reg[7]_0 ;
output [0:0]E;
output [3:0]D;
output [3:0]\current_word_1_reg[3] ;
output [12:0]Q;
output first_word_reg;
output first_word_reg_0;
output \s_axi_rdata[31] ;
output \s_axi_rdata[31]_0 ;
output s_axi_rvalid;
output [0:0]\M_AXI_RDATA_I_reg[127] ;
output s_ready_i_reg;
output m_axi_arvalid;
input [0:0]SR;
input out;
input [1:0]DI;
input [3:0]S;
input [3:0]\m_payload_i_reg[50] ;
input [3:0]\m_payload_i_reg[51] ;
input mr_rvalid;
input wrap_buffer_available_reg;
input use_wrap_buffer;
input wrap_buffer_available;
input \USE_RTL_LENGTH.length_counter_q_reg[1] ;
input s_axi_rready;
input \pre_next_word_1_reg[2] ;
input \pre_next_word_1_reg[3] ;
input [3:0]\pre_next_word_1_reg[3]_0 ;
input first_word;
input sr_arvalid;
input use_wrap_buffer_reg;
input \current_word_1_reg[3]_0 ;
input \current_word_1_reg[2] ;
input [3:0]\current_word_1_reg[3]_1 ;
input first_mi_word_q;
input m_axi_arready;
input s_axi_aresetn;
input [32:0]in;
wire [0:0]CO;
wire [3:0]D;
wire [1:0]DI;
wire [0:0]E;
wire [0:0]\M_AXI_RDATA_I_reg[127] ;
wire [12:0]Q;
wire [3:0]S;
wire [0:0]SR;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[1] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7]_0 ;
wire cmd_packed_wrap_i1_carry_n_1;
wire cmd_packed_wrap_i1_carry_n_2;
wire cmd_packed_wrap_i1_carry_n_3;
wire cmd_push_block;
wire cmd_push_block0;
wire \current_word_1_reg[2] ;
wire [3:0]\current_word_1_reg[3] ;
wire \current_word_1_reg[3]_0 ;
wire [3:0]\current_word_1_reg[3]_1 ;
wire first_mi_word_q;
wire first_word;
wire first_word_reg;
wire first_word_reg_0;
wire [32:0]in;
wire m_axi_arready;
wire m_axi_arvalid;
wire [3:0]\m_payload_i_reg[50] ;
wire [3:0]\m_payload_i_reg[51] ;
wire mr_rvalid;
wire out;
wire \pre_next_word_1_reg[2] ;
wire \pre_next_word_1_reg[3] ;
wire [3:0]\pre_next_word_1_reg[3]_0 ;
wire rd_cmd_valid;
wire s_axi_aresetn;
wire \s_axi_rdata[31] ;
wire \s_axi_rdata[31]_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_reg;
wire sr_arvalid;
wire sub_sized_wrap0_carry_n_1;
wire sub_sized_wrap0_carry_n_2;
wire sub_sized_wrap0_carry_n_3;
wire use_wrap_buffer;
wire use_wrap_buffer_reg;
wire wrap_buffer_available;
wire wrap_buffer_available_reg;
wire [3:0]NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED;
wire [3:0]NLW_sub_sized_wrap0_carry_O_UNCONNECTED;
system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo \GEN_CMD_QUEUE.cmd_queue
(.D(D),
.E(E),
.\M_AXI_RDATA_I_reg[127] (rd_cmd_valid),
.\M_AXI_RDATA_I_reg[127]_0 (\M_AXI_RDATA_I_reg[127] ),
.Q(Q),
.SR(SR),
.\USE_RTL_LENGTH.length_counter_q_reg[1] (\USE_RTL_LENGTH.length_counter_q_reg[1] ),
.\USE_RTL_LENGTH.length_counter_q_reg[7] (\USE_RTL_LENGTH.length_counter_q_reg[7] ),
.\USE_RTL_LENGTH.length_counter_q_reg[7]_0 (\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ),
.cmd_push_block(cmd_push_block),
.cmd_push_block0(cmd_push_block0),
.\current_word_1_reg[2] (\current_word_1_reg[2] ),
.\current_word_1_reg[3] (\current_word_1_reg[3] ),
.\current_word_1_reg[3]_0 (\current_word_1_reg[3]_0 ),
.\current_word_1_reg[3]_1 (\current_word_1_reg[3]_1 ),
.first_mi_word_q(first_mi_word_q),
.first_word(first_word),
.first_word_reg(first_word_reg),
.first_word_reg_0(first_word_reg_0),
.in(in),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.mr_rvalid(mr_rvalid),
.out(out),
.\pre_next_word_1_reg[2] (\pre_next_word_1_reg[2] ),
.\pre_next_word_1_reg[3] (\pre_next_word_1_reg[3] ),
.\pre_next_word_1_reg[3]_0 (\pre_next_word_1_reg[3]_0 ),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata[31] (\s_axi_rdata[31] ),
.\s_axi_rdata[31]_0 (\s_axi_rdata[31]_0 ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_ready_i_reg(s_ready_i_reg),
.sr_arvalid(sr_arvalid),
.use_wrap_buffer(use_wrap_buffer),
.use_wrap_buffer_reg(use_wrap_buffer_reg),
.wrap_buffer_available(wrap_buffer_available),
.wrap_buffer_available_reg(wrap_buffer_available_reg));
CARRY4 cmd_packed_wrap_i1_carry
(.CI(1'b0),
.CO({\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,cmd_packed_wrap_i1_carry_n_1,cmd_packed_wrap_i1_carry_n_2,cmd_packed_wrap_i1_carry_n_3}),
.CYINIT(1'b0),
.DI(\m_payload_i_reg[50] ),
.O(NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED[3:0]),
.S(\m_payload_i_reg[51] ));
FDRE cmd_push_block_reg
(.C(out),
.CE(1'b1),
.D(cmd_push_block0),
.Q(cmd_push_block),
.R(SR));
CARRY4 sub_sized_wrap0_carry
(.CI(1'b0),
.CO({CO,sub_sized_wrap0_carry_n_1,sub_sized_wrap0_carry_n_2,sub_sized_wrap0_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,DI}),
.O(NLW_sub_sized_wrap0_carry_O_UNCONNECTED[3:0]),
.S(S));
endmodule |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer
(m_axi_arlen,
m_axi_rready,
s_axi_rlast,
Q,
s_axi_arready,
s_axi_rdata,
s_axi_rvalid,
m_axi_arvalid,
s_axi_rresp,
m_axi_arsize,
m_axi_arburst,
m_axi_araddr,
s_axi_rready,
out,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
s_axi_arvalid,
m_axi_arready,
s_axi_aresetn,
m_axi_rvalid);
output [7:0]m_axi_arlen;
output m_axi_rready;
output s_axi_rlast;
output [43:0]Q;
output s_axi_arready;
output [31:0]s_axi_rdata;
output s_axi_rvalid;
output m_axi_arvalid;
output [1:0]s_axi_rresp;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [3:0]m_axi_araddr;
input s_axi_rready;
input out;
input m_axi_rlast;
input [1:0]m_axi_rresp;
input [127:0]m_axi_rdata;
input [60:0]D;
input s_axi_arvalid;
input m_axi_arready;
input s_axi_aresetn;
input m_axi_rvalid;
wire [60:0]D;
wire M_AXI_RLAST;
wire [43:0]Q;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6 ;
wire \USE_READ.read_addr_inst_n_19 ;
wire \USE_READ.read_addr_inst_n_20 ;
wire \USE_READ.read_addr_inst_n_21 ;
wire \USE_READ.read_addr_inst_n_22 ;
wire \USE_READ.read_addr_inst_n_23 ;
wire \USE_READ.read_addr_inst_n_24 ;
wire \USE_READ.read_addr_inst_n_25 ;
wire \USE_READ.read_addr_inst_n_26 ;
wire \USE_READ.read_addr_inst_n_27 ;
wire \USE_READ.read_addr_inst_n_28 ;
wire \USE_READ.read_addr_inst_n_29 ;
wire \USE_READ.read_addr_inst_n_3 ;
wire \USE_READ.read_addr_inst_n_30 ;
wire \USE_READ.read_addr_inst_n_33 ;
wire \USE_READ.read_addr_inst_n_4 ;
wire \USE_READ.read_addr_inst_n_5 ;
wire cmd_complete_wrap_i;
wire [3:0]cmd_first_word_i;
wire cmd_fix_i;
wire cmd_modified_i;
wire cmd_packed_wrap_i;
wire cmd_packed_wrap_i1;
wire [3:0]current_word_1;
wire first_mi_word_q;
wire first_word;
wire [3:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [7:0]m_axi_arlen;
wire m_axi_arready;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [127:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [1:0]mr_rresp;
wire mr_rvalid;
wire [3:0]next_word;
wire out;
wire [26:17]p_1_out;
wire p_7_in;
wire [3:0]pre_next_word;
wire [3:0]pre_next_word_1;
wire [3:2]rd_cmd_first_word;
wire rd_cmd_fix;
wire [3:2]rd_cmd_next_word;
wire rd_cmd_valid;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire si_register_slice_inst_n_0;
wire si_register_slice_inst_n_1;
wire si_register_slice_inst_n_100;
wire si_register_slice_inst_n_101;
wire si_register_slice_inst_n_102;
wire si_register_slice_inst_n_103;
wire si_register_slice_inst_n_3;
wire si_register_slice_inst_n_4;
wire si_register_slice_inst_n_5;
wire si_register_slice_inst_n_6;
wire si_register_slice_inst_n_73;
wire si_register_slice_inst_n_74;
wire si_register_slice_inst_n_75;
wire si_register_slice_inst_n_76;
wire si_register_slice_inst_n_77;
wire si_register_slice_inst_n_78;
wire si_register_slice_inst_n_79;
wire si_register_slice_inst_n_90;
wire si_register_slice_inst_n_91;
wire si_register_slice_inst_n_92;
wire si_register_slice_inst_n_93;
wire si_register_slice_inst_n_98;
wire si_register_slice_inst_n_99;
wire sr_arvalid;
wire sub_sized_wrap0;
wire use_wrap_buffer;
wire wrap_buffer_available;
system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst
(.E(\USE_READ.read_addr_inst_n_5 ),
.Q({M_AXI_RLAST,mr_rresp,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133 }),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_READ.read_addr_inst_n_30 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] (\USE_READ.read_addr_inst_n_29 ),
.\aresetn_d_reg[0] (si_register_slice_inst_n_0),
.\aresetn_d_reg[1] (si_register_slice_inst_n_1),
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.\s_axi_rdata[0] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2 ),
.\s_axi_rdata[10] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143 ),
.\s_axi_rdata[11] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144 ),
.\s_axi_rdata[12] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145 ),
.\s_axi_rdata[13] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146 ),
.\s_axi_rdata[14] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147 ),
.\s_axi_rdata[15] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148 ),
.\s_axi_rdata[16] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149 ),
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.\s_axi_rdata[19] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152 ),
.\s_axi_rdata[1] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134 ),
.\s_axi_rdata[20] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153 ),
.\s_axi_rdata[21] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154 ),
.\s_axi_rdata[22] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155 ),
.\s_axi_rdata[23] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156 ),
.\s_axi_rdata[24] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157 ),
.\s_axi_rdata[25] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158 ),
.\s_axi_rdata[26] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159 ),
.\s_axi_rdata[27] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160 ),
.\s_axi_rdata[28] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161 ),
.\s_axi_rdata[29] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162 ),
.\s_axi_rdata[2] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135 ),
.\s_axi_rdata[30] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163 ),
.\s_axi_rdata[31] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164 ),
.\s_axi_rdata[3] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136 ),
.\s_axi_rdata[4] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137 ),
.\s_axi_rdata[5] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138 ),
.\s_axi_rdata[6] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139 ),
.\s_axi_rdata[7] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140 ),
.\s_axi_rdata[8] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141 ),
.\s_axi_rdata[9] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142 ));
system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer \USE_READ.gen_non_fifo_r_upsizer.read_data_inst
(.D(pre_next_word),
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.\M_AXI_RDATA_I_reg[0]_0 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1 ),
.Q({M_AXI_RLAST,mr_rresp,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133 }),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] (next_word),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_READ.read_addr_inst_n_30 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] (\USE_READ.read_addr_inst_n_29 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] ({rd_cmd_fix,rd_cmd_first_word,rd_cmd_next_word,\USE_READ.read_addr_inst_n_19 ,\USE_READ.read_addr_inst_n_20 ,\USE_READ.read_addr_inst_n_21 ,\USE_READ.read_addr_inst_n_22 ,\USE_READ.read_addr_inst_n_23 ,\USE_READ.read_addr_inst_n_24 ,\USE_READ.read_addr_inst_n_25 ,\USE_READ.read_addr_inst_n_26 }),
.\USE_RTL_ADDR.addr_q_reg[4] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51 ),
.\current_word_1_reg[0]_0 (\USE_READ.read_addr_inst_n_28 ),
.\current_word_1_reg[1]_0 (\USE_READ.read_addr_inst_n_27 ),
.\current_word_1_reg[3]_0 (pre_next_word_1),
.first_mi_word_q(first_mi_word_q),
.first_word(first_word),
.first_word_reg_0(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45 ),
.first_word_reg_1(current_word_1),
.first_word_reg_2(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50 ),
.\m_payload_i_reg[0] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2 ),
.\m_payload_i_reg[10] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143 ),
.\m_payload_i_reg[11] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144 ),
.\m_payload_i_reg[12] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145 ),
.\m_payload_i_reg[130] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52 ),
.\m_payload_i_reg[13] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146 ),
.\m_payload_i_reg[14] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147 ),
.\m_payload_i_reg[15] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148 ),
.\m_payload_i_reg[16] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149 ),
.\m_payload_i_reg[17] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150 ),
.\m_payload_i_reg[18] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151 ),
.\m_payload_i_reg[19] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152 ),
.\m_payload_i_reg[1] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134 ),
.\m_payload_i_reg[20] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153 ),
.\m_payload_i_reg[21] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154 ),
.\m_payload_i_reg[22] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155 ),
.\m_payload_i_reg[23] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156 ),
.\m_payload_i_reg[24] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157 ),
.\m_payload_i_reg[25] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158 ),
.\m_payload_i_reg[26] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159 ),
.\m_payload_i_reg[27] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160 ),
.\m_payload_i_reg[28] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161 ),
.\m_payload_i_reg[29] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162 ),
.\m_payload_i_reg[2] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135 ),
.\m_payload_i_reg[30] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163 ),
.\m_payload_i_reg[31] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164 ),
.\m_payload_i_reg[3] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136 ),
.\m_payload_i_reg[4] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137 ),
.\m_payload_i_reg[5] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138 ),
.\m_payload_i_reg[6] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139 ),
.\m_payload_i_reg[7] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140 ),
.\m_payload_i_reg[8] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141 ),
.\m_payload_i_reg[9] (\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142 ),
.m_valid_i_reg(\USE_READ.read_addr_inst_n_3 ),
.mr_rvalid(mr_rvalid),
.out(out),
.\pre_next_word_1_reg[3]_0 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6 ),
.\pre_next_word_1_reg[3]_1 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11 ),
.rd_cmd_valid(rd_cmd_valid),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_rdata(s_axi_rdata),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.use_wrap_buffer(use_wrap_buffer),
.use_wrap_buffer_reg_0(\USE_READ.read_addr_inst_n_4 ),
.wrap_buffer_available(wrap_buffer_available),
.wrap_buffer_available_reg_0(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12 ));
system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer \USE_READ.read_addr_inst
(.CO(sub_sized_wrap0),
.D(pre_next_word),
.DI({si_register_slice_inst_n_98,si_register_slice_inst_n_99}),
.E(\USE_READ.read_addr_inst_n_5 ),
.\M_AXI_RDATA_I_reg[127] (p_7_in),
.Q({rd_cmd_fix,rd_cmd_first_word,rd_cmd_next_word,\USE_READ.read_addr_inst_n_19 ,\USE_READ.read_addr_inst_n_20 ,\USE_READ.read_addr_inst_n_21 ,\USE_READ.read_addr_inst_n_22 ,\USE_READ.read_addr_inst_n_23 ,\USE_READ.read_addr_inst_n_24 ,\USE_READ.read_addr_inst_n_25 ,\USE_READ.read_addr_inst_n_26 }),
.S({si_register_slice_inst_n_100,si_register_slice_inst_n_101,si_register_slice_inst_n_102,si_register_slice_inst_n_103}),
.SR(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] (cmd_packed_wrap_i1),
.\USE_RTL_LENGTH.length_counter_q_reg[1] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12 ),
.\USE_RTL_LENGTH.length_counter_q_reg[7] (\USE_READ.read_addr_inst_n_3 ),
.\USE_RTL_LENGTH.length_counter_q_reg[7]_0 (\USE_READ.read_addr_inst_n_4 ),
.\current_word_1_reg[2] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50 ),
.\current_word_1_reg[3] (next_word),
.\current_word_1_reg[3]_0 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45 ),
.\current_word_1_reg[3]_1 (current_word_1),
.first_mi_word_q(first_mi_word_q),
.first_word(first_word),
.first_word_reg(\USE_READ.read_addr_inst_n_27 ),
.first_word_reg_0(\USE_READ.read_addr_inst_n_28 ),
.in({cmd_fix_i,cmd_modified_i,cmd_complete_wrap_i,cmd_packed_wrap_i,cmd_first_word_i,p_1_out,si_register_slice_inst_n_73,si_register_slice_inst_n_74,si_register_slice_inst_n_75,si_register_slice_inst_n_76,si_register_slice_inst_n_77,si_register_slice_inst_n_78,si_register_slice_inst_n_79,m_axi_arlen}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[50] ({si_register_slice_inst_n_3,si_register_slice_inst_n_4,si_register_slice_inst_n_5,si_register_slice_inst_n_6}),
.\m_payload_i_reg[51] ({si_register_slice_inst_n_90,si_register_slice_inst_n_91,si_register_slice_inst_n_92,si_register_slice_inst_n_93}),
.mr_rvalid(mr_rvalid),
.out(out),
.\pre_next_word_1_reg[2] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11 ),
.\pre_next_word_1_reg[3] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6 ),
.\pre_next_word_1_reg[3]_0 (pre_next_word_1),
.rd_cmd_valid(rd_cmd_valid),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata[31] (\USE_READ.read_addr_inst_n_29 ),
.\s_axi_rdata[31]_0 (\USE_READ.read_addr_inst_n_30 ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_ready_i_reg(\USE_READ.read_addr_inst_n_33 ),
.sr_arvalid(sr_arvalid),
.use_wrap_buffer(use_wrap_buffer),
.use_wrap_buffer_reg(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51 ),
.wrap_buffer_available(wrap_buffer_available),
.wrap_buffer_available_reg(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52 ));
system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0 si_register_slice_inst
(.CO(sub_sized_wrap0),
.D(D),
.DI({si_register_slice_inst_n_98,si_register_slice_inst_n_99}),
.Q(Q),
.S({si_register_slice_inst_n_100,si_register_slice_inst_n_101,si_register_slice_inst_n_102,si_register_slice_inst_n_103}),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ({si_register_slice_inst_n_3,si_register_slice_inst_n_4,si_register_slice_inst_n_5,si_register_slice_inst_n_6}),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ({si_register_slice_inst_n_90,si_register_slice_inst_n_91,si_register_slice_inst_n_92,si_register_slice_inst_n_93}),
.\aresetn_d_reg[1] (si_register_slice_inst_n_0),
.cmd_push_block_reg(\USE_READ.read_addr_inst_n_33 ),
.in({cmd_fix_i,cmd_modified_i,cmd_complete_wrap_i,cmd_packed_wrap_i,cmd_first_word_i,p_1_out,si_register_slice_inst_n_73,si_register_slice_inst_n_74,si_register_slice_inst_n_75,si_register_slice_inst_n_76,si_register_slice_inst_n_77,si_register_slice_inst_n_78,si_register_slice_inst_n_79,m_axi_arlen}),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arsize(m_axi_arsize),
.\m_payload_i_reg[50] (cmd_packed_wrap_i1),
.out(out),
.s_axi_aresetn(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1 ),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(si_register_slice_inst_n_1),
.sr_arvalid(sr_arvalid));
endmodule |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer
(first_mi_word_q,
\M_AXI_RDATA_I_reg[0]_0 ,
first_word,
s_axi_rlast,
use_wrap_buffer,
wrap_buffer_available,
\pre_next_word_1_reg[3]_0 ,
\current_word_1_reg[3]_0 ,
\pre_next_word_1_reg[3]_1 ,
wrap_buffer_available_reg_0,
s_axi_rdata,
first_word_reg_0,
first_word_reg_1,
first_word_reg_2,
\USE_RTL_ADDR.addr_q_reg[4] ,
\m_payload_i_reg[130] ,
s_axi_rresp,
m_valid_i_reg,
Q,
out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] ,
s_axi_rready,
mr_rvalid,
rd_cmd_valid,
\current_word_1_reg[0]_0 ,
\current_word_1_reg[1]_0 ,
\m_payload_i_reg[0] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ,
\m_payload_i_reg[1] ,
\m_payload_i_reg[2] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[4] ,
\m_payload_i_reg[5] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[7] ,
\m_payload_i_reg[8] ,
\m_payload_i_reg[9] ,
\m_payload_i_reg[10] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[12] ,
\m_payload_i_reg[13] ,
\m_payload_i_reg[14] ,
\m_payload_i_reg[15] ,
\m_payload_i_reg[16] ,
\m_payload_i_reg[17] ,
\m_payload_i_reg[18] ,
\m_payload_i_reg[19] ,
\m_payload_i_reg[20] ,
\m_payload_i_reg[21] ,
\m_payload_i_reg[22] ,
\m_payload_i_reg[23] ,
\m_payload_i_reg[24] ,
\m_payload_i_reg[25] ,
\m_payload_i_reg[26] ,
\m_payload_i_reg[27] ,
\m_payload_i_reg[28] ,
\m_payload_i_reg[29] ,
\m_payload_i_reg[30] ,
\m_payload_i_reg[31] ,
s_axi_aresetn,
use_wrap_buffer_reg_0,
E,
D,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] );
output first_mi_word_q;
output \M_AXI_RDATA_I_reg[0]_0 ;
output first_word;
output s_axi_rlast;
output use_wrap_buffer;
output wrap_buffer_available;
output \pre_next_word_1_reg[3]_0 ;
output [3:0]\current_word_1_reg[3]_0 ;
output \pre_next_word_1_reg[3]_1 ;
output wrap_buffer_available_reg_0;
output [31:0]s_axi_rdata;
output first_word_reg_0;
output [3:0]first_word_reg_1;
output first_word_reg_2;
output \USE_RTL_ADDR.addr_q_reg[4] ;
output \m_payload_i_reg[130] ;
output [1:0]s_axi_rresp;
input m_valid_i_reg;
input [130:0]Q;
input out;
input [12:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] ;
input s_axi_rready;
input mr_rvalid;
input rd_cmd_valid;
input \current_word_1_reg[0]_0 ;
input \current_word_1_reg[1]_0 ;
input \m_payload_i_reg[0] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ;
input \m_payload_i_reg[1] ;
input \m_payload_i_reg[2] ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[4] ;
input \m_payload_i_reg[5] ;
input \m_payload_i_reg[6] ;
input \m_payload_i_reg[7] ;
input \m_payload_i_reg[8] ;
input \m_payload_i_reg[9] ;
input \m_payload_i_reg[10] ;
input \m_payload_i_reg[11] ;
input \m_payload_i_reg[12] ;
input \m_payload_i_reg[13] ;
input \m_payload_i_reg[14] ;
input \m_payload_i_reg[15] ;
input \m_payload_i_reg[16] ;
input \m_payload_i_reg[17] ;
input \m_payload_i_reg[18] ;
input \m_payload_i_reg[19] ;
input \m_payload_i_reg[20] ;
input \m_payload_i_reg[21] ;
input \m_payload_i_reg[22] ;
input \m_payload_i_reg[23] ;
input \m_payload_i_reg[24] ;
input \m_payload_i_reg[25] ;
input \m_payload_i_reg[26] ;
input \m_payload_i_reg[27] ;
input \m_payload_i_reg[28] ;
input \m_payload_i_reg[29] ;
input \m_payload_i_reg[30] ;
input \m_payload_i_reg[31] ;
input s_axi_aresetn;
input use_wrap_buffer_reg_0;
input [0:0]E;
input [3:0]D;
input [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] ;
wire [3:0]D;
wire [0:0]E;
wire \M_AXI_RDATA_I_reg[0]_0 ;
wire \M_AXI_RDATA_I_reg_n_0_[0] ;
wire \M_AXI_RDATA_I_reg_n_0_[100] ;
wire \M_AXI_RDATA_I_reg_n_0_[101] ;
wire \M_AXI_RDATA_I_reg_n_0_[102] ;
wire \M_AXI_RDATA_I_reg_n_0_[103] ;
wire \M_AXI_RDATA_I_reg_n_0_[104] ;
wire \M_AXI_RDATA_I_reg_n_0_[105] ;
wire \M_AXI_RDATA_I_reg_n_0_[106] ;
wire \M_AXI_RDATA_I_reg_n_0_[107] ;
wire \M_AXI_RDATA_I_reg_n_0_[108] ;
wire \M_AXI_RDATA_I_reg_n_0_[109] ;
wire \M_AXI_RDATA_I_reg_n_0_[10] ;
wire \M_AXI_RDATA_I_reg_n_0_[110] ;
wire \M_AXI_RDATA_I_reg_n_0_[111] ;
wire \M_AXI_RDATA_I_reg_n_0_[112] ;
wire \M_AXI_RDATA_I_reg_n_0_[113] ;
wire \M_AXI_RDATA_I_reg_n_0_[114] ;
wire \M_AXI_RDATA_I_reg_n_0_[115] ;
wire \M_AXI_RDATA_I_reg_n_0_[116] ;
wire \M_AXI_RDATA_I_reg_n_0_[117] ;
wire \M_AXI_RDATA_I_reg_n_0_[118] ;
wire \M_AXI_RDATA_I_reg_n_0_[119] ;
wire \M_AXI_RDATA_I_reg_n_0_[11] ;
wire \M_AXI_RDATA_I_reg_n_0_[120] ;
wire \M_AXI_RDATA_I_reg_n_0_[121] ;
wire \M_AXI_RDATA_I_reg_n_0_[122] ;
wire \M_AXI_RDATA_I_reg_n_0_[123] ;
wire \M_AXI_RDATA_I_reg_n_0_[124] ;
wire \M_AXI_RDATA_I_reg_n_0_[125] ;
wire \M_AXI_RDATA_I_reg_n_0_[126] ;
wire \M_AXI_RDATA_I_reg_n_0_[127] ;
wire \M_AXI_RDATA_I_reg_n_0_[12] ;
wire \M_AXI_RDATA_I_reg_n_0_[13] ;
wire \M_AXI_RDATA_I_reg_n_0_[14] ;
wire \M_AXI_RDATA_I_reg_n_0_[15] ;
wire \M_AXI_RDATA_I_reg_n_0_[16] ;
wire \M_AXI_RDATA_I_reg_n_0_[17] ;
wire \M_AXI_RDATA_I_reg_n_0_[18] ;
wire \M_AXI_RDATA_I_reg_n_0_[19] ;
wire \M_AXI_RDATA_I_reg_n_0_[1] ;
wire \M_AXI_RDATA_I_reg_n_0_[20] ;
wire \M_AXI_RDATA_I_reg_n_0_[21] ;
wire \M_AXI_RDATA_I_reg_n_0_[22] ;
wire \M_AXI_RDATA_I_reg_n_0_[23] ;
wire \M_AXI_RDATA_I_reg_n_0_[24] ;
wire \M_AXI_RDATA_I_reg_n_0_[25] ;
wire \M_AXI_RDATA_I_reg_n_0_[26] ;
wire \M_AXI_RDATA_I_reg_n_0_[27] ;
wire \M_AXI_RDATA_I_reg_n_0_[28] ;
wire \M_AXI_RDATA_I_reg_n_0_[29] ;
wire \M_AXI_RDATA_I_reg_n_0_[2] ;
wire \M_AXI_RDATA_I_reg_n_0_[30] ;
wire \M_AXI_RDATA_I_reg_n_0_[31] ;
wire \M_AXI_RDATA_I_reg_n_0_[32] ;
wire \M_AXI_RDATA_I_reg_n_0_[33] ;
wire \M_AXI_RDATA_I_reg_n_0_[34] ;
wire \M_AXI_RDATA_I_reg_n_0_[35] ;
wire \M_AXI_RDATA_I_reg_n_0_[36] ;
wire \M_AXI_RDATA_I_reg_n_0_[37] ;
wire \M_AXI_RDATA_I_reg_n_0_[38] ;
wire \M_AXI_RDATA_I_reg_n_0_[39] ;
wire \M_AXI_RDATA_I_reg_n_0_[3] ;
wire \M_AXI_RDATA_I_reg_n_0_[40] ;
wire \M_AXI_RDATA_I_reg_n_0_[41] ;
wire \M_AXI_RDATA_I_reg_n_0_[42] ;
wire \M_AXI_RDATA_I_reg_n_0_[43] ;
wire \M_AXI_RDATA_I_reg_n_0_[44] ;
wire \M_AXI_RDATA_I_reg_n_0_[45] ;
wire \M_AXI_RDATA_I_reg_n_0_[46] ;
wire \M_AXI_RDATA_I_reg_n_0_[47] ;
wire \M_AXI_RDATA_I_reg_n_0_[48] ;
wire \M_AXI_RDATA_I_reg_n_0_[49] ;
wire \M_AXI_RDATA_I_reg_n_0_[4] ;
wire \M_AXI_RDATA_I_reg_n_0_[50] ;
wire \M_AXI_RDATA_I_reg_n_0_[51] ;
wire \M_AXI_RDATA_I_reg_n_0_[52] ;
wire \M_AXI_RDATA_I_reg_n_0_[53] ;
wire \M_AXI_RDATA_I_reg_n_0_[54] ;
wire \M_AXI_RDATA_I_reg_n_0_[55] ;
wire \M_AXI_RDATA_I_reg_n_0_[56] ;
wire \M_AXI_RDATA_I_reg_n_0_[57] ;
wire \M_AXI_RDATA_I_reg_n_0_[58] ;
wire \M_AXI_RDATA_I_reg_n_0_[59] ;
wire \M_AXI_RDATA_I_reg_n_0_[5] ;
wire \M_AXI_RDATA_I_reg_n_0_[60] ;
wire \M_AXI_RDATA_I_reg_n_0_[61] ;
wire \M_AXI_RDATA_I_reg_n_0_[62] ;
wire \M_AXI_RDATA_I_reg_n_0_[63] ;
wire \M_AXI_RDATA_I_reg_n_0_[64] ;
wire \M_AXI_RDATA_I_reg_n_0_[65] ;
wire \M_AXI_RDATA_I_reg_n_0_[66] ;
wire \M_AXI_RDATA_I_reg_n_0_[67] ;
wire \M_AXI_RDATA_I_reg_n_0_[68] ;
wire \M_AXI_RDATA_I_reg_n_0_[69] ;
wire \M_AXI_RDATA_I_reg_n_0_[6] ;
wire \M_AXI_RDATA_I_reg_n_0_[70] ;
wire \M_AXI_RDATA_I_reg_n_0_[71] ;
wire \M_AXI_RDATA_I_reg_n_0_[72] ;
wire \M_AXI_RDATA_I_reg_n_0_[73] ;
wire \M_AXI_RDATA_I_reg_n_0_[74] ;
wire \M_AXI_RDATA_I_reg_n_0_[75] ;
wire \M_AXI_RDATA_I_reg_n_0_[76] ;
wire \M_AXI_RDATA_I_reg_n_0_[77] ;
wire \M_AXI_RDATA_I_reg_n_0_[78] ;
wire \M_AXI_RDATA_I_reg_n_0_[79] ;
wire \M_AXI_RDATA_I_reg_n_0_[7] ;
wire \M_AXI_RDATA_I_reg_n_0_[80] ;
wire \M_AXI_RDATA_I_reg_n_0_[81] ;
wire \M_AXI_RDATA_I_reg_n_0_[82] ;
wire \M_AXI_RDATA_I_reg_n_0_[83] ;
wire \M_AXI_RDATA_I_reg_n_0_[84] ;
wire \M_AXI_RDATA_I_reg_n_0_[85] ;
wire \M_AXI_RDATA_I_reg_n_0_[86] ;
wire \M_AXI_RDATA_I_reg_n_0_[87] ;
wire \M_AXI_RDATA_I_reg_n_0_[88] ;
wire \M_AXI_RDATA_I_reg_n_0_[89] ;
wire \M_AXI_RDATA_I_reg_n_0_[8] ;
wire \M_AXI_RDATA_I_reg_n_0_[90] ;
wire \M_AXI_RDATA_I_reg_n_0_[91] ;
wire \M_AXI_RDATA_I_reg_n_0_[92] ;
wire \M_AXI_RDATA_I_reg_n_0_[93] ;
wire \M_AXI_RDATA_I_reg_n_0_[94] ;
wire \M_AXI_RDATA_I_reg_n_0_[95] ;
wire \M_AXI_RDATA_I_reg_n_0_[96] ;
wire \M_AXI_RDATA_I_reg_n_0_[97] ;
wire \M_AXI_RDATA_I_reg_n_0_[98] ;
wire \M_AXI_RDATA_I_reg_n_0_[99] ;
wire \M_AXI_RDATA_I_reg_n_0_[9] ;
wire [130:0]Q;
wire [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ;
wire [12:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] ;
wire \USE_RTL_ADDR.addr_q[4]_i_5_n_0 ;
wire \USE_RTL_ADDR.addr_q_reg[4] ;
wire \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0 ;
wire [7:0]\USE_RTL_LENGTH.length_counter_q_reg ;
wire \current_word_1_reg[0]_0 ;
wire \current_word_1_reg[1]_0 ;
wire [3:0]\current_word_1_reg[3]_0 ;
wire first_mi_word_q;
wire first_word;
wire first_word_reg_0;
wire [3:0]first_word_reg_1;
wire first_word_reg_2;
wire \m_payload_i[130]_i_7_n_0 ;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[10] ;
wire \m_payload_i_reg[11] ;
wire \m_payload_i_reg[12] ;
wire \m_payload_i_reg[130] ;
wire \m_payload_i_reg[13] ;
wire \m_payload_i_reg[14] ;
wire \m_payload_i_reg[15] ;
wire \m_payload_i_reg[16] ;
wire \m_payload_i_reg[17] ;
wire \m_payload_i_reg[18] ;
wire \m_payload_i_reg[19] ;
wire \m_payload_i_reg[1] ;
wire \m_payload_i_reg[20] ;
wire \m_payload_i_reg[21] ;
wire \m_payload_i_reg[22] ;
wire \m_payload_i_reg[23] ;
wire \m_payload_i_reg[24] ;
wire \m_payload_i_reg[25] ;
wire \m_payload_i_reg[26] ;
wire \m_payload_i_reg[27] ;
wire \m_payload_i_reg[28] ;
wire \m_payload_i_reg[29] ;
wire \m_payload_i_reg[2] ;
wire \m_payload_i_reg[30] ;
wire \m_payload_i_reg[31] ;
wire \m_payload_i_reg[3] ;
wire \m_payload_i_reg[4] ;
wire \m_payload_i_reg[5] ;
wire \m_payload_i_reg[6] ;
wire \m_payload_i_reg[7] ;
wire \m_payload_i_reg[8] ;
wire \m_payload_i_reg[9] ;
wire m_valid_i_reg;
wire mr_rvalid;
wire out;
wire p_15_in;
wire \pre_next_word_1_reg[3]_0 ;
wire \pre_next_word_1_reg[3]_1 ;
wire rd_cmd_valid;
wire [1:0]rresp_wrap_buffer;
wire s_axi_aresetn;
wire [31:0]s_axi_rdata;
wire \s_axi_rdata[0]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[10]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[11]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[12]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[13]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[14]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[15]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[16]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[17]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[18]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[19]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[1]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[20]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[21]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[22]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[23]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[24]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[25]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[26]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[27]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[28]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[29]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[2]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[30]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[31]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[3]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[4]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[5]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[6]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[7]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[8]_INST_0_i_2_n_0 ;
wire \s_axi_rdata[9]_INST_0_i_2_n_0 ;
wire s_axi_rlast;
wire s_axi_rlast_INST_0_i_4_n_0;
wire s_axi_rlast_INST_0_i_5_n_0;
wire s_axi_rlast_INST_0_i_6_n_0;
wire s_axi_rlast_INST_0_i_7_n_0;
wire s_axi_rlast_INST_0_i_8_n_0;
wire s_axi_rlast_INST_0_i_9_n_0;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire use_wrap_buffer;
wire use_wrap_buffer_i_1_n_0;
wire use_wrap_buffer_i_2_n_0;
wire use_wrap_buffer_i_3_n_0;
wire use_wrap_buffer_reg_0;
wire wrap_buffer_available;
wire wrap_buffer_available_i_1_n_0;
wire wrap_buffer_available_i_2_n_0;
wire wrap_buffer_available_reg_0;
FDRE \M_AXI_RDATA_I_reg[0]
(.C(out),
.CE(E),
.D(Q[0]),
.Q(\M_AXI_RDATA_I_reg_n_0_[0] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[100]
(.C(out),
.CE(E),
.D(Q[100]),
.Q(\M_AXI_RDATA_I_reg_n_0_[100] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[101]
(.C(out),
.CE(E),
.D(Q[101]),
.Q(\M_AXI_RDATA_I_reg_n_0_[101] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[102]
(.C(out),
.CE(E),
.D(Q[102]),
.Q(\M_AXI_RDATA_I_reg_n_0_[102] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[103]
(.C(out),
.CE(E),
.D(Q[103]),
.Q(\M_AXI_RDATA_I_reg_n_0_[103] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[104]
(.C(out),
.CE(E),
.D(Q[104]),
.Q(\M_AXI_RDATA_I_reg_n_0_[104] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[105]
(.C(out),
.CE(E),
.D(Q[105]),
.Q(\M_AXI_RDATA_I_reg_n_0_[105] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[106]
(.C(out),
.CE(E),
.D(Q[106]),
.Q(\M_AXI_RDATA_I_reg_n_0_[106] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[107]
(.C(out),
.CE(E),
.D(Q[107]),
.Q(\M_AXI_RDATA_I_reg_n_0_[107] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[108]
(.C(out),
.CE(E),
.D(Q[108]),
.Q(\M_AXI_RDATA_I_reg_n_0_[108] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[109]
(.C(out),
.CE(E),
.D(Q[109]),
.Q(\M_AXI_RDATA_I_reg_n_0_[109] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[10]
(.C(out),
.CE(E),
.D(Q[10]),
.Q(\M_AXI_RDATA_I_reg_n_0_[10] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[110]
(.C(out),
.CE(E),
.D(Q[110]),
.Q(\M_AXI_RDATA_I_reg_n_0_[110] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[111]
(.C(out),
.CE(E),
.D(Q[111]),
.Q(\M_AXI_RDATA_I_reg_n_0_[111] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[112]
(.C(out),
.CE(E),
.D(Q[112]),
.Q(\M_AXI_RDATA_I_reg_n_0_[112] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[113]
(.C(out),
.CE(E),
.D(Q[113]),
.Q(\M_AXI_RDATA_I_reg_n_0_[113] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[114]
(.C(out),
.CE(E),
.D(Q[114]),
.Q(\M_AXI_RDATA_I_reg_n_0_[114] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[115]
(.C(out),
.CE(E),
.D(Q[115]),
.Q(\M_AXI_RDATA_I_reg_n_0_[115] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[116]
(.C(out),
.CE(E),
.D(Q[116]),
.Q(\M_AXI_RDATA_I_reg_n_0_[116] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[117]
(.C(out),
.CE(E),
.D(Q[117]),
.Q(\M_AXI_RDATA_I_reg_n_0_[117] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[118]
(.C(out),
.CE(E),
.D(Q[118]),
.Q(\M_AXI_RDATA_I_reg_n_0_[118] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[119]
(.C(out),
.CE(E),
.D(Q[119]),
.Q(\M_AXI_RDATA_I_reg_n_0_[119] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[11]
(.C(out),
.CE(E),
.D(Q[11]),
.Q(\M_AXI_RDATA_I_reg_n_0_[11] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[120]
(.C(out),
.CE(E),
.D(Q[120]),
.Q(\M_AXI_RDATA_I_reg_n_0_[120] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[121]
(.C(out),
.CE(E),
.D(Q[121]),
.Q(\M_AXI_RDATA_I_reg_n_0_[121] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[122]
(.C(out),
.CE(E),
.D(Q[122]),
.Q(\M_AXI_RDATA_I_reg_n_0_[122] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[123]
(.C(out),
.CE(E),
.D(Q[123]),
.Q(\M_AXI_RDATA_I_reg_n_0_[123] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[124]
(.C(out),
.CE(E),
.D(Q[124]),
.Q(\M_AXI_RDATA_I_reg_n_0_[124] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[125]
(.C(out),
.CE(E),
.D(Q[125]),
.Q(\M_AXI_RDATA_I_reg_n_0_[125] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[126]
(.C(out),
.CE(E),
.D(Q[126]),
.Q(\M_AXI_RDATA_I_reg_n_0_[126] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[127]
(.C(out),
.CE(E),
.D(Q[127]),
.Q(\M_AXI_RDATA_I_reg_n_0_[127] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[12]
(.C(out),
.CE(E),
.D(Q[12]),
.Q(\M_AXI_RDATA_I_reg_n_0_[12] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[13]
(.C(out),
.CE(E),
.D(Q[13]),
.Q(\M_AXI_RDATA_I_reg_n_0_[13] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[14]
(.C(out),
.CE(E),
.D(Q[14]),
.Q(\M_AXI_RDATA_I_reg_n_0_[14] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[15]
(.C(out),
.CE(E),
.D(Q[15]),
.Q(\M_AXI_RDATA_I_reg_n_0_[15] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[16]
(.C(out),
.CE(E),
.D(Q[16]),
.Q(\M_AXI_RDATA_I_reg_n_0_[16] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[17]
(.C(out),
.CE(E),
.D(Q[17]),
.Q(\M_AXI_RDATA_I_reg_n_0_[17] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[18]
(.C(out),
.CE(E),
.D(Q[18]),
.Q(\M_AXI_RDATA_I_reg_n_0_[18] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[19]
(.C(out),
.CE(E),
.D(Q[19]),
.Q(\M_AXI_RDATA_I_reg_n_0_[19] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[1]
(.C(out),
.CE(E),
.D(Q[1]),
.Q(\M_AXI_RDATA_I_reg_n_0_[1] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[20]
(.C(out),
.CE(E),
.D(Q[20]),
.Q(\M_AXI_RDATA_I_reg_n_0_[20] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[21]
(.C(out),
.CE(E),
.D(Q[21]),
.Q(\M_AXI_RDATA_I_reg_n_0_[21] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[22]
(.C(out),
.CE(E),
.D(Q[22]),
.Q(\M_AXI_RDATA_I_reg_n_0_[22] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[23]
(.C(out),
.CE(E),
.D(Q[23]),
.Q(\M_AXI_RDATA_I_reg_n_0_[23] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[24]
(.C(out),
.CE(E),
.D(Q[24]),
.Q(\M_AXI_RDATA_I_reg_n_0_[24] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[25]
(.C(out),
.CE(E),
.D(Q[25]),
.Q(\M_AXI_RDATA_I_reg_n_0_[25] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[26]
(.C(out),
.CE(E),
.D(Q[26]),
.Q(\M_AXI_RDATA_I_reg_n_0_[26] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[27]
(.C(out),
.CE(E),
.D(Q[27]),
.Q(\M_AXI_RDATA_I_reg_n_0_[27] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[28]
(.C(out),
.CE(E),
.D(Q[28]),
.Q(\M_AXI_RDATA_I_reg_n_0_[28] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[29]
(.C(out),
.CE(E),
.D(Q[29]),
.Q(\M_AXI_RDATA_I_reg_n_0_[29] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[2]
(.C(out),
.CE(E),
.D(Q[2]),
.Q(\M_AXI_RDATA_I_reg_n_0_[2] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[30]
(.C(out),
.CE(E),
.D(Q[30]),
.Q(\M_AXI_RDATA_I_reg_n_0_[30] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[31]
(.C(out),
.CE(E),
.D(Q[31]),
.Q(\M_AXI_RDATA_I_reg_n_0_[31] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[32]
(.C(out),
.CE(E),
.D(Q[32]),
.Q(\M_AXI_RDATA_I_reg_n_0_[32] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[33]
(.C(out),
.CE(E),
.D(Q[33]),
.Q(\M_AXI_RDATA_I_reg_n_0_[33] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[34]
(.C(out),
.CE(E),
.D(Q[34]),
.Q(\M_AXI_RDATA_I_reg_n_0_[34] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[35]
(.C(out),
.CE(E),
.D(Q[35]),
.Q(\M_AXI_RDATA_I_reg_n_0_[35] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[36]
(.C(out),
.CE(E),
.D(Q[36]),
.Q(\M_AXI_RDATA_I_reg_n_0_[36] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[37]
(.C(out),
.CE(E),
.D(Q[37]),
.Q(\M_AXI_RDATA_I_reg_n_0_[37] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[38]
(.C(out),
.CE(E),
.D(Q[38]),
.Q(\M_AXI_RDATA_I_reg_n_0_[38] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[39]
(.C(out),
.CE(E),
.D(Q[39]),
.Q(\M_AXI_RDATA_I_reg_n_0_[39] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[3]
(.C(out),
.CE(E),
.D(Q[3]),
.Q(\M_AXI_RDATA_I_reg_n_0_[3] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[40]
(.C(out),
.CE(E),
.D(Q[40]),
.Q(\M_AXI_RDATA_I_reg_n_0_[40] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[41]
(.C(out),
.CE(E),
.D(Q[41]),
.Q(\M_AXI_RDATA_I_reg_n_0_[41] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[42]
(.C(out),
.CE(E),
.D(Q[42]),
.Q(\M_AXI_RDATA_I_reg_n_0_[42] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[43]
(.C(out),
.CE(E),
.D(Q[43]),
.Q(\M_AXI_RDATA_I_reg_n_0_[43] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[44]
(.C(out),
.CE(E),
.D(Q[44]),
.Q(\M_AXI_RDATA_I_reg_n_0_[44] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[45]
(.C(out),
.CE(E),
.D(Q[45]),
.Q(\M_AXI_RDATA_I_reg_n_0_[45] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[46]
(.C(out),
.CE(E),
.D(Q[46]),
.Q(\M_AXI_RDATA_I_reg_n_0_[46] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[47]
(.C(out),
.CE(E),
.D(Q[47]),
.Q(\M_AXI_RDATA_I_reg_n_0_[47] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[48]
(.C(out),
.CE(E),
.D(Q[48]),
.Q(\M_AXI_RDATA_I_reg_n_0_[48] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[49]
(.C(out),
.CE(E),
.D(Q[49]),
.Q(\M_AXI_RDATA_I_reg_n_0_[49] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[4]
(.C(out),
.CE(E),
.D(Q[4]),
.Q(\M_AXI_RDATA_I_reg_n_0_[4] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[50]
(.C(out),
.CE(E),
.D(Q[50]),
.Q(\M_AXI_RDATA_I_reg_n_0_[50] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[51]
(.C(out),
.CE(E),
.D(Q[51]),
.Q(\M_AXI_RDATA_I_reg_n_0_[51] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[52]
(.C(out),
.CE(E),
.D(Q[52]),
.Q(\M_AXI_RDATA_I_reg_n_0_[52] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[53]
(.C(out),
.CE(E),
.D(Q[53]),
.Q(\M_AXI_RDATA_I_reg_n_0_[53] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[54]
(.C(out),
.CE(E),
.D(Q[54]),
.Q(\M_AXI_RDATA_I_reg_n_0_[54] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[55]
(.C(out),
.CE(E),
.D(Q[55]),
.Q(\M_AXI_RDATA_I_reg_n_0_[55] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[56]
(.C(out),
.CE(E),
.D(Q[56]),
.Q(\M_AXI_RDATA_I_reg_n_0_[56] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[57]
(.C(out),
.CE(E),
.D(Q[57]),
.Q(\M_AXI_RDATA_I_reg_n_0_[57] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[58]
(.C(out),
.CE(E),
.D(Q[58]),
.Q(\M_AXI_RDATA_I_reg_n_0_[58] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[59]
(.C(out),
.CE(E),
.D(Q[59]),
.Q(\M_AXI_RDATA_I_reg_n_0_[59] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[5]
(.C(out),
.CE(E),
.D(Q[5]),
.Q(\M_AXI_RDATA_I_reg_n_0_[5] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[60]
(.C(out),
.CE(E),
.D(Q[60]),
.Q(\M_AXI_RDATA_I_reg_n_0_[60] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[61]
(.C(out),
.CE(E),
.D(Q[61]),
.Q(\M_AXI_RDATA_I_reg_n_0_[61] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[62]
(.C(out),
.CE(E),
.D(Q[62]),
.Q(\M_AXI_RDATA_I_reg_n_0_[62] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[63]
(.C(out),
.CE(E),
.D(Q[63]),
.Q(\M_AXI_RDATA_I_reg_n_0_[63] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[64]
(.C(out),
.CE(E),
.D(Q[64]),
.Q(\M_AXI_RDATA_I_reg_n_0_[64] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[65]
(.C(out),
.CE(E),
.D(Q[65]),
.Q(\M_AXI_RDATA_I_reg_n_0_[65] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[66]
(.C(out),
.CE(E),
.D(Q[66]),
.Q(\M_AXI_RDATA_I_reg_n_0_[66] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[67]
(.C(out),
.CE(E),
.D(Q[67]),
.Q(\M_AXI_RDATA_I_reg_n_0_[67] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[68]
(.C(out),
.CE(E),
.D(Q[68]),
.Q(\M_AXI_RDATA_I_reg_n_0_[68] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[69]
(.C(out),
.CE(E),
.D(Q[69]),
.Q(\M_AXI_RDATA_I_reg_n_0_[69] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[6]
(.C(out),
.CE(E),
.D(Q[6]),
.Q(\M_AXI_RDATA_I_reg_n_0_[6] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[70]
(.C(out),
.CE(E),
.D(Q[70]),
.Q(\M_AXI_RDATA_I_reg_n_0_[70] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[71]
(.C(out),
.CE(E),
.D(Q[71]),
.Q(\M_AXI_RDATA_I_reg_n_0_[71] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[72]
(.C(out),
.CE(E),
.D(Q[72]),
.Q(\M_AXI_RDATA_I_reg_n_0_[72] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[73]
(.C(out),
.CE(E),
.D(Q[73]),
.Q(\M_AXI_RDATA_I_reg_n_0_[73] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[74]
(.C(out),
.CE(E),
.D(Q[74]),
.Q(\M_AXI_RDATA_I_reg_n_0_[74] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[75]
(.C(out),
.CE(E),
.D(Q[75]),
.Q(\M_AXI_RDATA_I_reg_n_0_[75] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[76]
(.C(out),
.CE(E),
.D(Q[76]),
.Q(\M_AXI_RDATA_I_reg_n_0_[76] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[77]
(.C(out),
.CE(E),
.D(Q[77]),
.Q(\M_AXI_RDATA_I_reg_n_0_[77] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[78]
(.C(out),
.CE(E),
.D(Q[78]),
.Q(\M_AXI_RDATA_I_reg_n_0_[78] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[79]
(.C(out),
.CE(E),
.D(Q[79]),
.Q(\M_AXI_RDATA_I_reg_n_0_[79] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[7]
(.C(out),
.CE(E),
.D(Q[7]),
.Q(\M_AXI_RDATA_I_reg_n_0_[7] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[80]
(.C(out),
.CE(E),
.D(Q[80]),
.Q(\M_AXI_RDATA_I_reg_n_0_[80] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[81]
(.C(out),
.CE(E),
.D(Q[81]),
.Q(\M_AXI_RDATA_I_reg_n_0_[81] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[82]
(.C(out),
.CE(E),
.D(Q[82]),
.Q(\M_AXI_RDATA_I_reg_n_0_[82] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[83]
(.C(out),
.CE(E),
.D(Q[83]),
.Q(\M_AXI_RDATA_I_reg_n_0_[83] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[84]
(.C(out),
.CE(E),
.D(Q[84]),
.Q(\M_AXI_RDATA_I_reg_n_0_[84] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[85]
(.C(out),
.CE(E),
.D(Q[85]),
.Q(\M_AXI_RDATA_I_reg_n_0_[85] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[86]
(.C(out),
.CE(E),
.D(Q[86]),
.Q(\M_AXI_RDATA_I_reg_n_0_[86] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[87]
(.C(out),
.CE(E),
.D(Q[87]),
.Q(\M_AXI_RDATA_I_reg_n_0_[87] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[88]
(.C(out),
.CE(E),
.D(Q[88]),
.Q(\M_AXI_RDATA_I_reg_n_0_[88] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[89]
(.C(out),
.CE(E),
.D(Q[89]),
.Q(\M_AXI_RDATA_I_reg_n_0_[89] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[8]
(.C(out),
.CE(E),
.D(Q[8]),
.Q(\M_AXI_RDATA_I_reg_n_0_[8] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[90]
(.C(out),
.CE(E),
.D(Q[90]),
.Q(\M_AXI_RDATA_I_reg_n_0_[90] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[91]
(.C(out),
.CE(E),
.D(Q[91]),
.Q(\M_AXI_RDATA_I_reg_n_0_[91] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[92]
(.C(out),
.CE(E),
.D(Q[92]),
.Q(\M_AXI_RDATA_I_reg_n_0_[92] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[93]
(.C(out),
.CE(E),
.D(Q[93]),
.Q(\M_AXI_RDATA_I_reg_n_0_[93] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[94]
(.C(out),
.CE(E),
.D(Q[94]),
.Q(\M_AXI_RDATA_I_reg_n_0_[94] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[95]
(.C(out),
.CE(E),
.D(Q[95]),
.Q(\M_AXI_RDATA_I_reg_n_0_[95] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[96]
(.C(out),
.CE(E),
.D(Q[96]),
.Q(\M_AXI_RDATA_I_reg_n_0_[96] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[97]
(.C(out),
.CE(E),
.D(Q[97]),
.Q(\M_AXI_RDATA_I_reg_n_0_[97] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[98]
(.C(out),
.CE(E),
.D(Q[98]),
.Q(\M_AXI_RDATA_I_reg_n_0_[98] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[99]
(.C(out),
.CE(E),
.D(Q[99]),
.Q(\M_AXI_RDATA_I_reg_n_0_[99] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \M_AXI_RDATA_I_reg[9]
(.C(out),
.CE(E),
.D(Q[9]),
.Q(\M_AXI_RDATA_I_reg_n_0_[9] ),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
LUT1 #(
.INIT(2'h1))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_1
(.I0(s_axi_aresetn),
.O(\M_AXI_RDATA_I_reg[0]_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAAE))
\USE_RTL_ADDR.addr_q[4]_i_4
(.I0(use_wrap_buffer),
.I1(s_axi_rlast_INST_0_i_4_n_0),
.I2(\m_payload_i[130]_i_7_n_0 ),
.I3(\USE_RTL_ADDR.addr_q[4]_i_5_n_0 ),
.I4(s_axi_rlast_INST_0_i_9_n_0),
.I5(wrap_buffer_available),
.O(\USE_RTL_ADDR.addr_q_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT5 #(
.INIT(32'hFFFACCFA))
\USE_RTL_ADDR.addr_q[4]_i_5
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [5]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [4]),
.O(\USE_RTL_ADDR.addr_q[4]_i_5_n_0 ));
FDSE \USE_RTL_LENGTH.first_mi_word_q_reg
(.C(out),
.CE(m_valid_i_reg),
.D(Q[130]),
.Q(first_mi_word_q),
.S(\M_AXI_RDATA_I_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'h1D))
\USE_RTL_LENGTH.length_counter_q[0]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I1(first_mi_word_q),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [0]),
.O(\USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'hCCA533A5))
\USE_RTL_LENGTH.length_counter_q[1]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [1]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [0]),
.O(\USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h56A6))
\USE_RTL_LENGTH.length_counter_q[2]_i_1
(.I0(s_axi_rlast_INST_0_i_4_n_0),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I2(first_mi_word_q),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [2]),
.O(\USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[3]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [3]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [2]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I5(s_axi_rlast_INST_0_i_4_n_0),
.O(\USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'hB847))
\USE_RTL_LENGTH.length_counter_q[4]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [4]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I3(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCCAACCAAC3AAC355))
\USE_RTL_LENGTH.length_counter_q[5]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [5]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [4]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I5(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBBFCB8FFFFFFFF))
\USE_RTL_LENGTH.length_counter_q[5]_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [2]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [3]),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I5(s_axi_rlast_INST_0_i_4_n_0),
.O(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[6]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [6]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [5]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I5(\USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'h0151))
\USE_RTL_LENGTH.length_counter_q[6]_i_2
(.I0(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I2(first_mi_word_q),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [4]),
.O(\USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[7]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [7]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [6]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I5(\USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000305050003))
\USE_RTL_LENGTH.length_counter_q[7]_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [4]),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I2(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I4(first_mi_word_q),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [5]),
.O(\USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[0]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[1]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[2]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[3]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[4]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[5]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[6]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[7]
(.C(out),
.CE(m_valid_i_reg),
.D(\USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \current_word_1_reg[0]
(.C(out),
.CE(p_15_in),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] [0]),
.Q(first_word_reg_1[0]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \current_word_1_reg[1]
(.C(out),
.CE(p_15_in),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] [1]),
.Q(first_word_reg_1[1]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \current_word_1_reg[2]
(.C(out),
.CE(p_15_in),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] [2]),
.Q(first_word_reg_1[2]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \current_word_1_reg[3]
(.C(out),
.CE(p_15_in),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14] [3]),
.Q(first_word_reg_1[3]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDSE first_word_reg
(.C(out),
.CE(p_15_in),
.D(s_axi_rlast),
.Q(first_word),
.S(\M_AXI_RDATA_I_reg[0]_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
\m_payload_i[130]_i_5
(.I0(wrap_buffer_available),
.I1(s_axi_rlast_INST_0_i_9_n_0),
.I2(s_axi_rlast_INST_0_i_8_n_0),
.I3(s_axi_rlast_INST_0_i_7_n_0),
.I4(\m_payload_i[130]_i_7_n_0 ),
.I5(s_axi_rlast_INST_0_i_4_n_0),
.O(\m_payload_i_reg[130] ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT5 #(
.INIT(32'hFFFACCFA))
\m_payload_i[130]_i_7
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [3]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [2]),
.O(\m_payload_i[130]_i_7_n_0 ));
LUT4 #(
.INIT(16'hA888))
\pre_next_word_1[3]_i_1
(.I0(s_axi_rready),
.I1(use_wrap_buffer),
.I2(mr_rvalid),
.I3(rd_cmd_valid),
.O(p_15_in));
LUT4 #(
.INIT(16'hFE02))
\pre_next_word_1[3]_i_3
(.I0(\current_word_1_reg[3]_0 [2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [8]),
.O(\pre_next_word_1_reg[3]_1 ));
LUT4 #(
.INIT(16'h01FD))
\pre_next_word_1[3]_i_5
(.I0(\current_word_1_reg[3]_0 [3]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [9]),
.O(\pre_next_word_1_reg[3]_0 ));
FDRE \pre_next_word_1_reg[0]
(.C(out),
.CE(p_15_in),
.D(D[0]),
.Q(\current_word_1_reg[3]_0 [0]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \pre_next_word_1_reg[1]
(.C(out),
.CE(p_15_in),
.D(D[1]),
.Q(\current_word_1_reg[3]_0 [1]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \pre_next_word_1_reg[2]
(.C(out),
.CE(p_15_in),
.D(D[2]),
.Q(\current_word_1_reg[3]_0 [2]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \pre_next_word_1_reg[3]
(.C(out),
.CE(p_15_in),
.D(D[3]),
.Q(\current_word_1_reg[3]_0 [3]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \rresp_wrap_buffer_reg[0]
(.C(out),
.CE(E),
.D(Q[128]),
.Q(rresp_wrap_buffer[0]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
FDRE \rresp_wrap_buffer_reg[1]
(.C(out),
.CE(E),
.D(Q[129]),
.Q(rresp_wrap_buffer[1]),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
MUXF7 \s_axi_rdata[0]_INST_0
(.I0(\m_payload_i_reg[0] ),
.I1(\s_axi_rdata[0]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[0]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[0]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[0] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[64] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[32] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[96] ),
.O(\s_axi_rdata[0]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[10]_INST_0
(.I0(\m_payload_i_reg[10] ),
.I1(\s_axi_rdata[10]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[10]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[10]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[10] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[74] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[42] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[106] ),
.O(\s_axi_rdata[10]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[11]_INST_0
(.I0(\m_payload_i_reg[11] ),
.I1(\s_axi_rdata[11]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[11]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[11]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[11] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[75] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[43] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[107] ),
.O(\s_axi_rdata[11]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[12]_INST_0
(.I0(\m_payload_i_reg[12] ),
.I1(\s_axi_rdata[12]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[12]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[12]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[12] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[76] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[44] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[108] ),
.O(\s_axi_rdata[12]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[13]_INST_0
(.I0(\m_payload_i_reg[13] ),
.I1(\s_axi_rdata[13]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[13]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[13]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[13] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[77] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[45] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[109] ),
.O(\s_axi_rdata[13]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[14]_INST_0
(.I0(\m_payload_i_reg[14] ),
.I1(\s_axi_rdata[14]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[14]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[14]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[14] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[78] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[46] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[110] ),
.O(\s_axi_rdata[14]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[15]_INST_0
(.I0(\m_payload_i_reg[15] ),
.I1(\s_axi_rdata[15]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[15]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[15]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[15] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[79] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[47] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[111] ),
.O(\s_axi_rdata[15]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[16]_INST_0
(.I0(\m_payload_i_reg[16] ),
.I1(\s_axi_rdata[16]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[16]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[16]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[16] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[80] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[48] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[112] ),
.O(\s_axi_rdata[16]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[17]_INST_0
(.I0(\m_payload_i_reg[17] ),
.I1(\s_axi_rdata[17]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[17]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[17]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[17] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[81] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[49] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[113] ),
.O(\s_axi_rdata[17]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[18]_INST_0
(.I0(\m_payload_i_reg[18] ),
.I1(\s_axi_rdata[18]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[18]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[18]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[18] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[82] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[50] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[114] ),
.O(\s_axi_rdata[18]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[19]_INST_0
(.I0(\m_payload_i_reg[19] ),
.I1(\s_axi_rdata[19]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[19]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[19]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[19] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[83] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[51] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[115] ),
.O(\s_axi_rdata[19]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[1]_INST_0
(.I0(\m_payload_i_reg[1] ),
.I1(\s_axi_rdata[1]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[1]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[1]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[1] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[65] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[33] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[97] ),
.O(\s_axi_rdata[1]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[20]_INST_0
(.I0(\m_payload_i_reg[20] ),
.I1(\s_axi_rdata[20]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[20]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[20]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[20] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[84] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[52] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[116] ),
.O(\s_axi_rdata[20]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[21]_INST_0
(.I0(\m_payload_i_reg[21] ),
.I1(\s_axi_rdata[21]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[21]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[21]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[21] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[85] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[53] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[117] ),
.O(\s_axi_rdata[21]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[22]_INST_0
(.I0(\m_payload_i_reg[22] ),
.I1(\s_axi_rdata[22]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[22]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[22]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[22] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[86] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[54] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[118] ),
.O(\s_axi_rdata[22]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[23]_INST_0
(.I0(\m_payload_i_reg[23] ),
.I1(\s_axi_rdata[23]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[23]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[23]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[23] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[87] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[55] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[119] ),
.O(\s_axi_rdata[23]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[24]_INST_0
(.I0(\m_payload_i_reg[24] ),
.I1(\s_axi_rdata[24]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[24]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[24]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[24] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[88] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[56] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[120] ),
.O(\s_axi_rdata[24]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[25]_INST_0
(.I0(\m_payload_i_reg[25] ),
.I1(\s_axi_rdata[25]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[25]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[25]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[25] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[89] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[57] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[121] ),
.O(\s_axi_rdata[25]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[26]_INST_0
(.I0(\m_payload_i_reg[26] ),
.I1(\s_axi_rdata[26]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[26]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[26]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[26] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[90] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[58] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[122] ),
.O(\s_axi_rdata[26]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[27]_INST_0
(.I0(\m_payload_i_reg[27] ),
.I1(\s_axi_rdata[27]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[27]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[27]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[27] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[91] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[59] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[123] ),
.O(\s_axi_rdata[27]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[28]_INST_0
(.I0(\m_payload_i_reg[28] ),
.I1(\s_axi_rdata[28]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[28]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[28]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[28] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[92] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[60] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[124] ),
.O(\s_axi_rdata[28]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[29]_INST_0
(.I0(\m_payload_i_reg[29] ),
.I1(\s_axi_rdata[29]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[29]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[29]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[29] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[93] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[61] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[125] ),
.O(\s_axi_rdata[29]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[2]_INST_0
(.I0(\m_payload_i_reg[2] ),
.I1(\s_axi_rdata[2]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[2]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[2]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[2] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[66] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[34] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[98] ),
.O(\s_axi_rdata[2]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[30]_INST_0
(.I0(\m_payload_i_reg[30] ),
.I1(\s_axi_rdata[30]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[30]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[30]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[30] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[94] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[62] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[126] ),
.O(\s_axi_rdata[30]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[31]_INST_0
(.I0(\m_payload_i_reg[31] ),
.I1(\s_axi_rdata[31]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[31]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[31]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[31] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[95] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[63] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[127] ),
.O(\s_axi_rdata[31]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[3]_INST_0
(.I0(\m_payload_i_reg[3] ),
.I1(\s_axi_rdata[3]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[3]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[3]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[3] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[67] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[35] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[99] ),
.O(\s_axi_rdata[3]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[4]_INST_0
(.I0(\m_payload_i_reg[4] ),
.I1(\s_axi_rdata[4]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[4]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[4]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[4] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[68] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[36] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[100] ),
.O(\s_axi_rdata[4]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[5]_INST_0
(.I0(\m_payload_i_reg[5] ),
.I1(\s_axi_rdata[5]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[5]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[5]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[5] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[69] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[37] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[101] ),
.O(\s_axi_rdata[5]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[6]_INST_0
(.I0(\m_payload_i_reg[6] ),
.I1(\s_axi_rdata[6]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[6]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[6]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[6] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[70] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[38] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[102] ),
.O(\s_axi_rdata[6]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[7]_INST_0
(.I0(\m_payload_i_reg[7] ),
.I1(\s_axi_rdata[7]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[7]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[7]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[7] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[71] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[39] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[103] ),
.O(\s_axi_rdata[7]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[8]_INST_0
(.I0(\m_payload_i_reg[8] ),
.I1(\s_axi_rdata[8]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[8]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[8]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[8] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[72] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[40] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[104] ),
.O(\s_axi_rdata[8]_INST_0_i_2_n_0 ));
MUXF7 \s_axi_rdata[9]_INST_0
(.I0(\m_payload_i_reg[9] ),
.I1(\s_axi_rdata[9]_INST_0_i_2_n_0 ),
.O(s_axi_rdata[9]),
.S(use_wrap_buffer));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[9]_INST_0_i_2
(.I0(\M_AXI_RDATA_I_reg_n_0_[9] ),
.I1(\M_AXI_RDATA_I_reg_n_0_[73] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(\M_AXI_RDATA_I_reg_n_0_[41] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(\M_AXI_RDATA_I_reg_n_0_[105] ),
.O(\s_axi_rdata[9]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'h000000F1))
s_axi_rlast_INST_0
(.I0(wrap_buffer_available),
.I1(wrap_buffer_available_reg_0),
.I2(use_wrap_buffer),
.I3(\current_word_1_reg[0]_0 ),
.I4(\current_word_1_reg[1]_0 ),
.O(s_axi_rlast));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFD))
s_axi_rlast_INST_0_i_1
(.I0(s_axi_rlast_INST_0_i_4_n_0),
.I1(s_axi_rlast_INST_0_i_5_n_0),
.I2(s_axi_rlast_INST_0_i_6_n_0),
.I3(s_axi_rlast_INST_0_i_7_n_0),
.I4(s_axi_rlast_INST_0_i_8_n_0),
.I5(s_axi_rlast_INST_0_i_9_n_0),
.O(wrap_buffer_available_reg_0));
LUT4 #(
.INIT(16'h01FD))
s_axi_rlast_INST_0_i_11
(.I0(first_word_reg_1[2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [10]),
.O(first_word_reg_2));
LUT4 #(
.INIT(16'h01FD))
s_axi_rlast_INST_0_i_12
(.I0(first_word_reg_1[3]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [11]),
.O(first_word_reg_0));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'h00053305))
s_axi_rlast_INST_0_i_4
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [1]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [0]),
.O(s_axi_rlast_INST_0_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
s_axi_rlast_INST_0_i_5
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [3]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.O(s_axi_rlast_INST_0_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
s_axi_rlast_INST_0_i_6
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [2]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.O(s_axi_rlast_INST_0_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
s_axi_rlast_INST_0_i_7
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [5]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.O(s_axi_rlast_INST_0_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
s_axi_rlast_INST_0_i_8
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [4]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.O(s_axi_rlast_INST_0_i_8_n_0));
LUT5 #(
.INIT(32'hFFFACCFA))
s_axi_rlast_INST_0_i_9
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [7]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34] [6]),
.O(s_axi_rlast_INST_0_i_9_n_0));
LUT3 #(
.INIT(8'hB8))
\s_axi_rresp[0]_INST_0
(.I0(rresp_wrap_buffer[0]),
.I1(use_wrap_buffer),
.I2(Q[128]),
.O(s_axi_rresp[0]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\s_axi_rresp[1]_INST_0
(.I0(rresp_wrap_buffer[1]),
.I1(use_wrap_buffer),
.I2(Q[129]),
.O(s_axi_rresp[1]));
LUT6 #(
.INIT(64'hBBFBBBBB00F00000))
use_wrap_buffer_i_1
(.I0(use_wrap_buffer_i_2_n_0),
.I1(s_axi_rlast),
.I2(use_wrap_buffer_reg_0),
.I3(use_wrap_buffer_i_3_n_0),
.I4(wrap_buffer_available),
.I5(use_wrap_buffer),
.O(use_wrap_buffer_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT4 #(
.INIT(16'h57FF))
use_wrap_buffer_i_2
(.I0(s_axi_rready),
.I1(use_wrap_buffer),
.I2(mr_rvalid),
.I3(rd_cmd_valid),
.O(use_wrap_buffer_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT4 #(
.INIT(16'hAABF))
use_wrap_buffer_i_3
(.I0(wrap_buffer_available_reg_0),
.I1(rd_cmd_valid),
.I2(mr_rvalid),
.I3(use_wrap_buffer),
.O(use_wrap_buffer_i_3_n_0));
FDRE use_wrap_buffer_reg
(.C(out),
.CE(1'b1),
.D(use_wrap_buffer_i_1_n_0),
.Q(use_wrap_buffer),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
LUT5 #(
.INIT(32'hFEFFAA00))
wrap_buffer_available_i_1
(.I0(E),
.I1(wrap_buffer_available_reg_0),
.I2(wrap_buffer_available_i_2_n_0),
.I3(use_wrap_buffer_reg_0),
.I4(wrap_buffer_available),
.O(wrap_buffer_available_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'h15))
wrap_buffer_available_i_2
(.I0(use_wrap_buffer),
.I1(mr_rvalid),
.I2(rd_cmd_valid),
.O(wrap_buffer_available_i_2_n_0));
FDRE wrap_buffer_available_reg
(.C(out),
.CE(1'b1),
.D(wrap_buffer_available_i_1_n_0),
.Q(wrap_buffer_available),
.R(\M_AXI_RDATA_I_reg[0]_0 ));
endmodule |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_top
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* keep = "true" *) input s_axi_aclk;
(* keep = "true" *) input s_axi_aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
(* keep = "true" *) input m_axi_aclk;
(* keep = "true" *) input m_axi_aresetn;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
(* RTL_KEEP = "true" *) wire m_axi_aclk;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
(* RTL_KEEP = "true" *) wire m_axi_aresetn;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [127:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
(* RTL_KEEP = "true" *) wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
(* RTL_KEEP = "true" *) wire s_axi_aresetn;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_wdata[127] = \<const0> ;
assign m_axi_wdata[126] = \<const0> ;
assign m_axi_wdata[125] = \<const0> ;
assign m_axi_wdata[124] = \<const0> ;
assign m_axi_wdata[123] = \<const0> ;
assign m_axi_wdata[122] = \<const0> ;
assign m_axi_wdata[121] = \<const0> ;
assign m_axi_wdata[120] = \<const0> ;
assign m_axi_wdata[119] = \<const0> ;
assign m_axi_wdata[118] = \<const0> ;
assign m_axi_wdata[117] = \<const0> ;
assign m_axi_wdata[116] = \<const0> ;
assign m_axi_wdata[115] = \<const0> ;
assign m_axi_wdata[114] = \<const0> ;
assign m_axi_wdata[113] = \<const0> ;
assign m_axi_wdata[112] = \<const0> ;
assign m_axi_wdata[111] = \<const0> ;
assign m_axi_wdata[110] = \<const0> ;
assign m_axi_wdata[109] = \<const0> ;
assign m_axi_wdata[108] = \<const0> ;
assign m_axi_wdata[107] = \<const0> ;
assign m_axi_wdata[106] = \<const0> ;
assign m_axi_wdata[105] = \<const0> ;
assign m_axi_wdata[104] = \<const0> ;
assign m_axi_wdata[103] = \<const0> ;
assign m_axi_wdata[102] = \<const0> ;
assign m_axi_wdata[101] = \<const0> ;
assign m_axi_wdata[100] = \<const0> ;
assign m_axi_wdata[99] = \<const0> ;
assign m_axi_wdata[98] = \<const0> ;
assign m_axi_wdata[97] = \<const0> ;
assign m_axi_wdata[96] = \<const0> ;
assign m_axi_wdata[95] = \<const0> ;
assign m_axi_wdata[94] = \<const0> ;
assign m_axi_wdata[93] = \<const0> ;
assign m_axi_wdata[92] = \<const0> ;
assign m_axi_wdata[91] = \<const0> ;
assign m_axi_wdata[90] = \<const0> ;
assign m_axi_wdata[89] = \<const0> ;
assign m_axi_wdata[88] = \<const0> ;
assign m_axi_wdata[87] = \<const0> ;
assign m_axi_wdata[86] = \<const0> ;
assign m_axi_wdata[85] = \<const0> ;
assign m_axi_wdata[84] = \<const0> ;
assign m_axi_wdata[83] = \<const0> ;
assign m_axi_wdata[82] = \<const0> ;
assign m_axi_wdata[81] = \<const0> ;
assign m_axi_wdata[80] = \<const0> ;
assign m_axi_wdata[79] = \<const0> ;
assign m_axi_wdata[78] = \<const0> ;
assign m_axi_wdata[77] = \<const0> ;
assign m_axi_wdata[76] = \<const0> ;
assign m_axi_wdata[75] = \<const0> ;
assign m_axi_wdata[74] = \<const0> ;
assign m_axi_wdata[73] = \<const0> ;
assign m_axi_wdata[72] = \<const0> ;
assign m_axi_wdata[71] = \<const0> ;
assign m_axi_wdata[70] = \<const0> ;
assign m_axi_wdata[69] = \<const0> ;
assign m_axi_wdata[68] = \<const0> ;
assign m_axi_wdata[67] = \<const0> ;
assign m_axi_wdata[66] = \<const0> ;
assign m_axi_wdata[65] = \<const0> ;
assign m_axi_wdata[64] = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[15] = \<const0> ;
assign m_axi_wstrb[14] = \<const0> ;
assign m_axi_wstrb[13] = \<const0> ;
assign m_axi_wstrb[12] = \<const0> ;
assign m_axi_wstrb[11] = \<const0> ;
assign m_axi_wstrb[10] = \<const0> ;
assign m_axi_wstrb[9] = \<const0> ;
assign m_axi_wstrb[8] = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_wready = \<const0> ;
GND GND
(.G(\<const0> ));
system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer \gen_upsizer.gen_full_upsizer.axi_upsizer_inst
(.D({s_axi_arregion,s_axi_arqos,s_axi_arlock,s_axi_arlen,s_axi_arcache,s_axi_arburst,s_axi_arsize,s_axi_arprot,s_axi_araddr}),
.Q({m_axi_arregion,m_axi_arqos,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_araddr[31:4]}),
.m_axi_araddr(m_axi_araddr[3:0]),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlen(m_axi_arlen),
.m_axi_arready(m_axi_arready),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.out(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid));
endmodule |
module system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice
(m_axi_rready,
mr_rvalid,
\s_axi_rdata[0] ,
Q,
\s_axi_rdata[1] ,
\s_axi_rdata[2] ,
\s_axi_rdata[3] ,
\s_axi_rdata[4] ,
\s_axi_rdata[5] ,
\s_axi_rdata[6] ,
\s_axi_rdata[7] ,
\s_axi_rdata[8] ,
\s_axi_rdata[9] ,
\s_axi_rdata[10] ,
\s_axi_rdata[11] ,
\s_axi_rdata[12] ,
\s_axi_rdata[13] ,
\s_axi_rdata[14] ,
\s_axi_rdata[15] ,
\s_axi_rdata[16] ,
\s_axi_rdata[17] ,
\s_axi_rdata[18] ,
\s_axi_rdata[19] ,
\s_axi_rdata[20] ,
\s_axi_rdata[21] ,
\s_axi_rdata[22] ,
\s_axi_rdata[23] ,
\s_axi_rdata[24] ,
\s_axi_rdata[25] ,
\s_axi_rdata[26] ,
\s_axi_rdata[27] ,
\s_axi_rdata[28] ,
\s_axi_rdata[29] ,
\s_axi_rdata[30] ,
\s_axi_rdata[31] ,
out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
E,
\aresetn_d_reg[1] ,
\aresetn_d_reg[0] );
output m_axi_rready;
output mr_rvalid;
output \s_axi_rdata[0] ;
output [130:0]Q;
output \s_axi_rdata[1] ;
output \s_axi_rdata[2] ;
output \s_axi_rdata[3] ;
output \s_axi_rdata[4] ;
output \s_axi_rdata[5] ;
output \s_axi_rdata[6] ;
output \s_axi_rdata[7] ;
output \s_axi_rdata[8] ;
output \s_axi_rdata[9] ;
output \s_axi_rdata[10] ;
output \s_axi_rdata[11] ;
output \s_axi_rdata[12] ;
output \s_axi_rdata[13] ;
output \s_axi_rdata[14] ;
output \s_axi_rdata[15] ;
output \s_axi_rdata[16] ;
output \s_axi_rdata[17] ;
output \s_axi_rdata[18] ;
output \s_axi_rdata[19] ;
output \s_axi_rdata[20] ;
output \s_axi_rdata[21] ;
output \s_axi_rdata[22] ;
output \s_axi_rdata[23] ;
output \s_axi_rdata[24] ;
output \s_axi_rdata[25] ;
output \s_axi_rdata[26] ;
output \s_axi_rdata[27] ;
output \s_axi_rdata[28] ;
output \s_axi_rdata[29] ;
output \s_axi_rdata[30] ;
output \s_axi_rdata[31] ;
input out;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ;
input m_axi_rlast;
input [1:0]m_axi_rresp;
input [127:0]m_axi_rdata;
input m_axi_rvalid;
input [0:0]E;
input \aresetn_d_reg[1] ;
input \aresetn_d_reg[0] ;
wire [0:0]E;
wire [130:0]Q;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1] ;
wire [127:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire mr_rvalid;
wire out;
wire \s_axi_rdata[0] ;
wire \s_axi_rdata[10] ;
wire \s_axi_rdata[11] ;
wire \s_axi_rdata[12] ;
wire \s_axi_rdata[13] ;
wire \s_axi_rdata[14] ;
wire \s_axi_rdata[15] ;
wire \s_axi_rdata[16] ;
wire \s_axi_rdata[17] ;
wire \s_axi_rdata[18] ;
wire \s_axi_rdata[19] ;
wire \s_axi_rdata[1] ;
wire \s_axi_rdata[20] ;
wire \s_axi_rdata[21] ;
wire \s_axi_rdata[22] ;
wire \s_axi_rdata[23] ;
wire \s_axi_rdata[24] ;
wire \s_axi_rdata[25] ;
wire \s_axi_rdata[26] ;
wire \s_axi_rdata[27] ;
wire \s_axi_rdata[28] ;
wire \s_axi_rdata[29] ;
wire \s_axi_rdata[2] ;
wire \s_axi_rdata[30] ;
wire \s_axi_rdata[31] ;
wire \s_axi_rdata[3] ;
wire \s_axi_rdata[4] ;
wire \s_axi_rdata[5] ;
wire \s_axi_rdata[6] ;
wire \s_axi_rdata[7] ;
wire \s_axi_rdata[8] ;
wire \s_axi_rdata[9] ;
system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 r_pipe
(.E(E),
.Q(Q),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.mr_rvalid(mr_rvalid),
.out(out),
.\s_axi_rdata[0] (\s_axi_rdata[0] ),
.\s_axi_rdata[10] (\s_axi_rdata[10] ),
.\s_axi_rdata[11] (\s_axi_rdata[11] ),
.\s_axi_rdata[12] (\s_axi_rdata[12] ),
.\s_axi_rdata[13] (\s_axi_rdata[13] ),
.\s_axi_rdata[14] (\s_axi_rdata[14] ),
.\s_axi_rdata[15] (\s_axi_rdata[15] ),
.\s_axi_rdata[16] (\s_axi_rdata[16] ),
.\s_axi_rdata[17] (\s_axi_rdata[17] ),
.\s_axi_rdata[18] (\s_axi_rdata[18] ),
.\s_axi_rdata[19] (\s_axi_rdata[19] ),
.\s_axi_rdata[1] (\s_axi_rdata[1] ),
.\s_axi_rdata[20] (\s_axi_rdata[20] ),
.\s_axi_rdata[21] (\s_axi_rdata[21] ),
.\s_axi_rdata[22] (\s_axi_rdata[22] ),
.\s_axi_rdata[23] (\s_axi_rdata[23] ),
.\s_axi_rdata[24] (\s_axi_rdata[24] ),
.\s_axi_rdata[25] (\s_axi_rdata[25] ),
.\s_axi_rdata[26] (\s_axi_rdata[26] ),
.\s_axi_rdata[27] (\s_axi_rdata[27] ),
.\s_axi_rdata[28] (\s_axi_rdata[28] ),
.\s_axi_rdata[29] (\s_axi_rdata[29] ),
.\s_axi_rdata[2] (\s_axi_rdata[2] ),
.\s_axi_rdata[30] (\s_axi_rdata[30] ),
.\s_axi_rdata[31] (\s_axi_rdata[31] ),
.\s_axi_rdata[3] (\s_axi_rdata[3] ),
.\s_axi_rdata[4] (\s_axi_rdata[4] ),
.\s_axi_rdata[5] (\s_axi_rdata[5] ),
.\s_axi_rdata[6] (\s_axi_rdata[6] ),
.\s_axi_rdata[7] (\s_axi_rdata[7] ),
.\s_axi_rdata[8] (\s_axi_rdata[8] ),
.\s_axi_rdata[9] (\s_axi_rdata[9] ));
endmodule |
module system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0
(\aresetn_d_reg[1] ,
s_ready_i_reg,
sr_arvalid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,
s_axi_arready,
Q,
m_axi_arsize,
in,
m_axi_arburst,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ,
m_axi_araddr,
DI,
S,
s_axi_aresetn,
out,
cmd_push_block_reg,
s_axi_arvalid,
D,
CO,
\m_payload_i_reg[50] );
output \aresetn_d_reg[1] ;
output s_ready_i_reg;
output sr_arvalid;
output [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ;
output s_axi_arready;
output [43:0]Q;
output [2:0]m_axi_arsize;
output [32:0]in;
output [1:0]m_axi_arburst;
output [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ;
output [3:0]m_axi_araddr;
output [1:0]DI;
output [3:0]S;
input s_axi_aresetn;
input out;
input cmd_push_block_reg;
input s_axi_arvalid;
input [60:0]D;
input [0:0]CO;
input [0:0]\m_payload_i_reg[50] ;
wire [0:0]CO;
wire [60:0]D;
wire [1:0]DI;
wire [43:0]Q;
wire [3:0]S;
wire [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ;
wire [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ;
wire \aresetn_d_reg[1] ;
wire cmd_push_block_reg;
wire [32:0]in;
wire [3:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [2:0]m_axi_arsize;
wire [0:0]\m_payload_i_reg[50] ;
wire out;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sr_arvalid;
system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice ar_pipe
(.CO(CO),
.D(D),
.DI(DI),
.Q(Q),
.S(S),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1] ),
.cmd_push_block_reg(cmd_push_block_reg),
.in(in),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arsize(m_axi_arsize),
.\m_payload_i_reg[50]_0 (\m_payload_i_reg[50] ),
.out(out),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(s_ready_i_reg),
.sr_arvalid(sr_arvalid));
endmodule |
module system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice
(\aresetn_d_reg[1]_0 ,
s_ready_i_reg_0,
sr_arvalid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,
s_axi_arready,
Q,
m_axi_arsize,
in,
m_axi_arburst,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ,
m_axi_araddr,
DI,
S,
s_axi_aresetn,
out,
cmd_push_block_reg,
s_axi_arvalid,
D,
CO,
\m_payload_i_reg[50]_0 );
output \aresetn_d_reg[1]_0 ;
output s_ready_i_reg_0;
output sr_arvalid;
output [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ;
output s_axi_arready;
output [43:0]Q;
output [2:0]m_axi_arsize;
output [32:0]in;
output [1:0]m_axi_arburst;
output [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ;
output [3:0]m_axi_araddr;
output [1:0]DI;
output [3:0]S;
input s_axi_aresetn;
input out;
input cmd_push_block_reg;
input s_axi_arvalid;
input [60:0]D;
input [0:0]CO;
input [0:0]\m_payload_i_reg[50]_0 ;
wire [0:0]CO;
wire [60:0]D;
wire [1:0]DI;
wire [43:0]Q;
wire [3:0]S;
wire [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ;
wire [3:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 ;
wire [3:3]\USE_READ.read_addr_inst/mi_word_intra_len__10 ;
wire \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0 ;
wire \aresetn_d_reg[1]_0 ;
wire cmd_push_block_reg;
wire [32:0]in;
wire [3:0]m_axi_araddr;
wire \m_axi_araddr[0]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[1]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[2]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[3]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[3]_INST_0_i_2_n_0 ;
wire [1:0]m_axi_arburst;
wire \m_axi_arlen[0]_INST_0_i_10_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_5_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_6_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_7_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_8_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_9_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_5_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_6_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_7_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_8_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_9_n_0 ;
wire \m_axi_arlen[2]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[2]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[2]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_5_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_6_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_6_n_0 ;
wire \m_axi_arlen[5]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[6]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[6]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[6]_INST_0_i_3_n_0 ;
wire [2:0]m_axi_arsize;
wire \m_axi_arsize[1]_INST_0_i_1_n_0 ;
wire \m_axi_arsize[1]_INST_0_i_2_n_0 ;
wire \m_axi_arsize[2]_INST_0_i_1_n_0 ;
wire \m_axi_arsize[2]_INST_0_i_2_n_0 ;
wire \m_axi_arsize[2]_INST_0_i_3_n_0 ;
wire \m_payload_i[31]_i_1_n_0 ;
wire [0:0]\m_payload_i_reg[50]_0 ;
wire m_valid_i_i_1_n_0;
wire out;
wire s_axi_aresetn;
wire [7:0]s_axi_arlen_ii;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_ready_i_i_1_n_0;
wire s_ready_i_reg_0;
wire [3:0]sr_araddr;
wire [1:0]sr_arburst;
wire [2:0]sr_arsize;
wire sr_arvalid;
wire [4:0]upsized_length;
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hDFDFFFDF))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1
(.I0(CO),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(s_axi_arlen_ii[0]),
.I4(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.O(in[11]));
LUT6 #(
.INIT(64'hFFFFFFFF11011000))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1
(.I0(sr_arsize[1]),
.I1(sr_arsize[2]),
.I2(sr_arsize[0]),
.I3(s_axi_arlen_ii[0]),
.I4(s_axi_arlen_ii[1]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ),
.O(in[12]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hDF))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(CO),
.O(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT4 #(
.INIT(16'hFBFF))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0 ),
.I1(CO),
.I2(sr_arburst[0]),
.I3(sr_arburst[1]),
.O(in[13]));
LUT6 #(
.INIT(64'h00000FAC000000AC))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2
(.I0(s_axi_arlen_ii[1]),
.I1(s_axi_arlen_ii[2]),
.I2(sr_arsize[0]),
.I3(sr_arsize[1]),
.I4(sr_arsize[2]),
.I5(s_axi_arlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFBFBBBBBB))
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0 ),
.I1(CO),
.I2(sr_arsize[2]),
.I3(sr_arsize[1]),
.I4(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0 ),
.O(in[14]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'hB))
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2
(.I0(sr_arburst[0]),
.I1(sr_arburst[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000CA))
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3
(.I0(s_axi_arlen_ii[3]),
.I1(s_axi_arlen_ii[2]),
.I2(sr_arsize[0]),
.I3(sr_arsize[2]),
.I4(sr_arsize[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'h20000000))
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(CO),
.I3(sr_araddr[2]),
.I4(\m_axi_araddr[2]_INST_0_i_1_n_0 ),
.O(in[15]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'h20000000))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(CO),
.I3(sr_araddr[3]),
.I4(\m_axi_araddr[3]_INST_0_i_1_n_0 ),
.O(in[16]));
LUT6 #(
.INIT(64'h1101115544444400))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1
(.I0(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[0]),
.I2(CO),
.I3(sr_arburst[0]),
.I4(sr_arburst[1]),
.I5(sr_araddr[0]),
.O(in[17]));
LUT6 #(
.INIT(64'h4888884848884888))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1
(.I0(sr_araddr[1]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0 ),
.I2(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0 ),
.I3(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0 ),
.I4(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0 ),
.I5(sr_araddr[0]),
.O(in[18]));
LUT6 #(
.INIT(64'hFFFFFFFF11011111))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2
(.I0(sr_arsize[1]),
.I1(sr_arsize[2]),
.I2(sr_arburst[1]),
.I3(sr_arburst[0]),
.I4(CO),
.I5(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'hE))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3
(.I0(sr_arburst[0]),
.I1(sr_arburst[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000CA))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4
(.I0(s_axi_arlen_ii[1]),
.I1(s_axi_arlen_ii[0]),
.I2(sr_arsize[0]),
.I3(sr_arsize[2]),
.I4(sr_arsize[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'hFEFF))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5
(.I0(sr_arsize[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.I3(s_axi_arlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAA55155555AA2AA))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1
(.I0(sr_araddr[2]),
.I1(CO),
.I2(sr_arburst[0]),
.I3(sr_arburst[1]),
.I4(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0 ),
.O(in[19]));
LUT6 #(
.INIT(64'hFFBAAAAAAAAAAAAA))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2
(.I0(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0 ),
.I1(CO),
.I2(sr_arburst[1]),
.I3(sr_arburst[0]),
.I4(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h0E02020200000000))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3
(.I0(\m_axi_arlen[1]_INST_0_i_7_n_0 ),
.I1(sr_arsize[0]),
.I2(\m_axi_arlen[0]_INST_0_i_7_n_0 ),
.I3(s_axi_arlen_ii[0]),
.I4(sr_araddr[1]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'h02))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4
(.I0(sr_araddr[0]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT2 #(
.INIT(4'h8))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5
(.I0(sr_araddr[1]),
.I1(s_axi_arlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0 ));
LUT6 #(
.INIT(64'h000D0000FFF20000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0 ),
.I1(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0 ),
.I2(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0 ),
.I3(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0 ),
.I4(in[14]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0 ),
.O(in[20]));
LUT6 #(
.INIT(64'h8000800080808000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2
(.I0(s_axi_arlen_ii[2]),
.I1(sr_araddr[0]),
.I2(sr_araddr[1]),
.I3(sr_arburst[0]),
.I4(sr_arburst[1]),
.I5(CO),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFC0000080800000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3
(.I0(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0 ),
.I1(s_axi_arlen_ii[1]),
.I2(in[9]),
.I3(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0 ),
.I4(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0 ),
.I5(sr_araddr[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0 ));
LUT6 #(
.INIT(64'hEAEAEEEAAAAAAAAA))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4
(.I0(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0 ),
.I1(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0 ),
.I2(sr_arburst[0]),
.I3(sr_arburst[1]),
.I4(CO),
.I5(sr_araddr[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0 ));
LUT6 #(
.INIT(64'h55555575AAAAAA8A))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5
(.I0(sr_araddr[3]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0 ),
.I2(CO),
.I3(\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0 ),
.I4(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0 ),
.I5(\USE_READ.read_addr_inst/mi_word_intra_len__10 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h00230020))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6
(.I0(s_axi_arlen_ii[0]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'h54000000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7
(.I0(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I1(sr_arburst[1]),
.I2(sr_arburst[0]),
.I3(s_axi_arlen_ii[2]),
.I4(\m_axi_arlen[1]_INST_0_i_7_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0 ));
LUT6 #(
.INIT(64'h3330303030200000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8
(.I0(sr_arsize[0]),
.I1(\m_axi_arlen[0]_INST_0_i_7_n_0 ),
.I2(sr_araddr[1]),
.I3(sr_araddr[0]),
.I4(s_axi_arlen_ii[0]),
.I5(s_axi_arlen_ii[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF000010000000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9
(.I0(sr_arsize[2]),
.I1(sr_arsize[0]),
.I2(sr_arsize[1]),
.I3(s_axi_arlen_ii[1]),
.I4(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0 ),
.O(\USE_READ.read_addr_inst/mi_word_intra_len__10 ));
LUT6 #(
.INIT(64'h000000000000FFDF))
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(CO),
.I3(s_axi_arlen_ii[0]),
.I4(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I5(sr_araddr[0]),
.O(in[21]));
LUT6 #(
.INIT(64'hAAAAAA02000000A8))
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0 ),
.I1(sr_araddr[0]),
.I2(sr_arsize[0]),
.I3(sr_arsize[2]),
.I4(sr_arsize[1]),
.I5(sr_araddr[1]),
.O(in[22]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h802A2A80))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1
(.I0(in[13]),
.I1(sr_araddr[1]),
.I2(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0 ),
.I3(in[10]),
.I4(sr_araddr[2]),
.O(in[23]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT4 #(
.INIT(16'h0302))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2
(.I0(sr_araddr[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.I3(sr_arsize[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h4844444484888888))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0 ),
.I1(in[14]),
.I2(sr_arsize[2]),
.I3(sr_arsize[1]),
.I4(sr_arsize[0]),
.I5(sr_araddr[3]),
.O(in[24]));
LUT6 #(
.INIT(64'h000000F000C00080))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2
(.I0(sr_araddr[0]),
.I1(sr_araddr[1]),
.I2(sr_araddr[2]),
.I3(sr_arsize[2]),
.I4(sr_arsize[0]),
.I5(sr_arsize[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h5545555500000000))
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1
(.I0(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[0]),
.I2(CO),
.I3(sr_arburst[0]),
.I4(sr_arburst[1]),
.I5(sr_araddr[0]),
.O(in[25]));
LUT6 #(
.INIT(64'h00FF00CA00000000))
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1
(.I0(s_axi_arlen_ii[1]),
.I1(s_axi_arlen_ii[0]),
.I2(sr_arsize[0]),
.I3(\m_axi_arlen[0]_INST_0_i_7_n_0 ),
.I4(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ),
.I5(sr_araddr[1]),
.O(in[26]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1
(.I0(in[13]),
.I1(sr_araddr[2]),
.O(in[27]));
LUT6 #(
.INIT(64'hFFEFFFFF00000000))
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0 ),
.I1(\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0 ),
.I2(CO),
.I3(sr_arburst[0]),
.I4(sr_arburst[1]),
.I5(sr_araddr[3]),
.O(in[28]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h44400040))
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(s_axi_arlen_ii[1]),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000800000000000))
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0 ),
.I1(Q[32]),
.I2(\m_payload_i_reg[50]_0 ),
.I3(sr_arburst[1]),
.I4(sr_arburst[0]),
.I5(\m_axi_arsize[2]_INST_0_i_1_n_0 ),
.O(in[29]));
LUT4 #(
.INIT(16'hFFFE))
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2
(.I0(sr_araddr[3]),
.I1(sr_araddr[2]),
.I2(sr_araddr[1]),
.I3(sr_araddr[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h20000000))
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(CO),
.I3(Q[32]),
.I4(\m_axi_arsize[2]_INST_0_i_1_n_0 ),
.O(in[30]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT4 #(
.INIT(16'h8880))
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1
(.I0(\m_axi_arsize[2]_INST_0_i_1_n_0 ),
.I1(Q[32]),
.I2(sr_arburst[0]),
.I3(sr_arburst[1]),
.O(in[31]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h1))
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.O(in[32]));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'h01))
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1
(.I0(sr_arsize[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.O(in[8]));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(out),
.CE(1'b1),
.D(1'b1),
.Q(\aresetn_d_reg[1]_0 ),
.R(s_axi_aresetn));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(out),
.CE(1'b1),
.D(\aresetn_d_reg[1]_0 ),
.Q(s_ready_i_reg_0),
.R(s_axi_aresetn));
LUT2 #(
.INIT(4'hE))
cmd_packed_wrap_i1_carry_i_1
(.I0(s_axi_arlen_ii[6]),
.I1(s_axi_arlen_ii[7]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] [3]));
LUT2 #(
.INIT(4'hE))
cmd_packed_wrap_i1_carry_i_2
(.I0(s_axi_arlen_ii[4]),
.I1(s_axi_arlen_ii[5]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] [2]));
LUT5 #(
.INIT(32'hFAFAFA88))
cmd_packed_wrap_i1_carry_i_3
(.I0(s_axi_arlen_ii[3]),
.I1(sr_arsize[0]),
.I2(s_axi_arlen_ii[2]),
.I3(sr_arsize[1]),
.I4(sr_arsize[2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] [1]));
LUT5 #(
.INIT(32'hEAEAEA00))
cmd_packed_wrap_i1_carry_i_4
(.I0(sr_arsize[2]),
.I1(sr_arsize[0]),
.I2(sr_arsize[1]),
.I3(s_axi_arlen_ii[1]),
.I4(s_axi_arlen_ii[0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] [0]));
LUT2 #(
.INIT(4'h1))
cmd_packed_wrap_i1_carry_i_5
(.I0(s_axi_arlen_ii[7]),
.I1(s_axi_arlen_ii[6]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 [3]));
LUT2 #(
.INIT(4'h1))
cmd_packed_wrap_i1_carry_i_6
(.I0(s_axi_arlen_ii[5]),
.I1(s_axi_arlen_ii[4]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 [2]));
LUT5 #(
.INIT(32'h010010EE))
cmd_packed_wrap_i1_carry_i_7
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.I3(s_axi_arlen_ii[2]),
.I4(s_axi_arlen_ii[3]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 [1]));
LUT5 #(
.INIT(32'h11181188))
cmd_packed_wrap_i1_carry_i_8
(.I0(s_axi_arlen_ii[0]),
.I1(s_axi_arlen_ii[1]),
.I2(sr_arsize[0]),
.I3(sr_arsize[2]),
.I4(sr_arsize[1]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0 [0]));
LUT5 #(
.INIT(32'hFF00B000))
\m_axi_araddr[0]_INST_0
(.I0(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[0]),
.I2(CO),
.I3(sr_araddr[0]),
.I4(\m_axi_araddr[3]_INST_0_i_2_n_0 ),
.O(m_axi_araddr[0]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hFE))
\m_axi_araddr[0]_INST_0_i_1
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.O(\m_axi_araddr[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF0000EF000000))
\m_axi_araddr[1]_INST_0
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I3(CO),
.I4(sr_araddr[1]),
.I5(\m_axi_araddr[3]_INST_0_i_2_n_0 ),
.O(m_axi_araddr[1]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_axi_araddr[1]_INST_0_i_1
(.I0(s_axi_arlen_ii[0]),
.I1(sr_arsize[0]),
.I2(s_axi_arlen_ii[1]),
.O(\m_axi_araddr[1]_INST_0_i_1_n_0 ));
LUT4 #(
.INIT(16'hF080))
\m_axi_araddr[2]_INST_0
(.I0(\m_axi_araddr[2]_INST_0_i_1_n_0 ),
.I1(CO),
.I2(sr_araddr[2]),
.I3(\m_axi_araddr[3]_INST_0_i_2_n_0 ),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hFFFFF530FFFFF53F))
\m_axi_araddr[2]_INST_0_i_1
(.I0(s_axi_arlen_ii[1]),
.I1(s_axi_arlen_ii[0]),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(sr_arsize[2]),
.I5(s_axi_arlen_ii[2]),
.O(\m_axi_araddr[2]_INST_0_i_1_n_0 ));
LUT4 #(
.INIT(16'hF080))
\m_axi_araddr[3]_INST_0
(.I0(\m_axi_araddr[3]_INST_0_i_1_n_0 ),
.I1(CO),
.I2(sr_araddr[3]),
.I3(\m_axi_araddr[3]_INST_0_i_2_n_0 ),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hF3F3F3F3F5F5F0FF))
\m_axi_araddr[3]_INST_0_i_1
(.I0(s_axi_arlen_ii[2]),
.I1(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I2(sr_arsize[2]),
.I3(s_axi_arlen_ii[3]),
.I4(sr_arsize[0]),
.I5(sr_arsize[1]),
.O(\m_axi_araddr[3]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT5 #(
.INIT(32'hFFFFBBBF))
\m_axi_araddr[3]_INST_0_i_2
(.I0(sr_arburst[0]),
.I1(sr_arburst[1]),
.I2(\m_payload_i_reg[50]_0 ),
.I3(CO),
.I4(\m_axi_arsize[1]_INST_0_i_1_n_0 ),
.O(\m_axi_araddr[3]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'hFFFF8000))
\m_axi_arburst[0]_INST_0
(.I0(\m_axi_arsize[2]_INST_0_i_1_n_0 ),
.I1(Q[32]),
.I2(sr_arburst[1]),
.I3(CO),
.I4(sr_arburst[0]),
.O(m_axi_arburst[0]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'hF0B0))
\m_axi_arburst[1]_INST_0
(.I0(sr_arburst[0]),
.I1(CO),
.I2(sr_arburst[1]),
.I3(\m_axi_arsize[1]_INST_0_i_1_n_0 ),
.O(m_axi_arburst[1]));
LUT6 #(
.INIT(64'h5555555566665666))
\m_axi_arlen[0]_INST_0
(.I0(upsized_length[0]),
.I1(\m_axi_arlen[0]_INST_0_i_2_n_0 ),
.I2(\m_axi_arlen[0]_INST_0_i_3_n_0 ),
.I3(\m_axi_arlen[0]_INST_0_i_4_n_0 ),
.I4(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I5(\m_axi_arlen[0]_INST_0_i_5_n_0 ),
.O(in[0]));
LUT6 #(
.INIT(64'hAABBAAABAABAAAAA))
\m_axi_arlen[0]_INST_0_i_1
(.I0(\m_axi_arlen[0]_INST_0_i_6_n_0 ),
.I1(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I2(sr_arsize[0]),
.I3(\m_axi_arlen[0]_INST_0_i_7_n_0 ),
.I4(s_axi_arlen_ii[3]),
.I5(s_axi_arlen_ii[4]),
.O(upsized_length[0]));
LUT2 #(
.INIT(4'h1))
\m_axi_arlen[0]_INST_0_i_10
(.I0(sr_arsize[0]),
.I1(sr_arsize[2]),
.O(\m_axi_arlen[0]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'h0000400000000000))
\m_axi_arlen[0]_INST_0_i_2
(.I0(sr_arburst[1]),
.I1(Q[32]),
.I2(sr_arburst[0]),
.I3(sr_araddr[3]),
.I4(\m_axi_arlen[0]_INST_0_i_7_n_0 ),
.I5(\m_axi_arlen[4]_INST_0_i_6_n_0 ),
.O(\m_axi_arlen[0]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAEAAA))
\m_axi_arlen[0]_INST_0_i_3
(.I0(sr_araddr[3]),
.I1(s_axi_arlen_ii[1]),
.I2(sr_araddr[1]),
.I3(s_axi_arlen_ii[2]),
.I4(sr_araddr[2]),
.I5(\m_axi_arlen[1]_INST_0_i_8_n_0 ),
.O(\m_axi_arlen[0]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'h0800))
\m_axi_arlen[0]_INST_0_i_4
(.I0(sr_arburst[0]),
.I1(Q[32]),
.I2(sr_arburst[1]),
.I3(s_axi_arlen_ii[3]),
.O(\m_axi_arlen[0]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEEECCCCEEEECCCC))
\m_axi_arlen[0]_INST_0_i_5
(.I0(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I1(\m_axi_arlen[0]_INST_0_i_8_n_0 ),
.I2(\m_axi_arlen[0]_INST_0_i_9_n_0 ),
.I3(s_axi_arlen_ii[3]),
.I4(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
.I5(sr_araddr[0]),
.O(\m_axi_arlen[0]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h888888B888888888))
\m_axi_arlen[0]_INST_0_i_6
(.I0(s_axi_arlen_ii[0]),
.I1(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(sr_arsize[2]),
.I5(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[0]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT2 #(
.INIT(4'hE))
\m_axi_arlen[0]_INST_0_i_7
(.I0(sr_arsize[1]),
.I1(sr_arsize[2]),
.O(\m_axi_arlen[0]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h8888800080000000))
\m_axi_arlen[0]_INST_0_i_8
(.I0(in[10]),
.I1(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
.I2(s_axi_arlen_ii[0]),
.I3(sr_araddr[2]),
.I4(sr_araddr[3]),
.I5(s_axi_arlen_ii[1]),
.O(\m_axi_arlen[0]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'h8F00000088000000))
\m_axi_arlen[0]_INST_0_i_9
(.I0(\m_axi_arlen[0]_INST_0_i_10_n_0 ),
.I1(sr_araddr[2]),
.I2(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I3(s_axi_arlen_ii[0]),
.I4(s_axi_arlen_ii[1]),
.I5(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[0]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'h000100010001FFFE))
\m_axi_arlen[1]_INST_0
(.I0(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
.I2(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
.I3(\m_axi_arlen[1]_INST_0_i_4_n_0 ),
.I4(\m_axi_arlen[1]_INST_0_i_5_n_0 ),
.I5(\m_axi_arlen[1]_INST_0_i_6_n_0 ),
.O(in[1]));
LUT6 #(
.INIT(64'h4444444040404040))
\m_axi_arlen[1]_INST_0_i_1
(.I0(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I2(sr_araddr[3]),
.I3(s_axi_arlen_ii[2]),
.I4(sr_araddr[2]),
.I5(\m_axi_arlen[1]_INST_0_i_7_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0E00000000000000))
\m_axi_arlen[1]_INST_0_i_2
(.I0(sr_araddr[3]),
.I1(s_axi_arlen_ii[3]),
.I2(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I3(s_axi_arlen_ii[4]),
.I4(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
.I5(\m_axi_arlen[1]_INST_0_i_8_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000008800C8))
\m_axi_arlen[1]_INST_0_i_3
(.I0(s_axi_arlen_ii[2]),
.I1(\m_axi_arlen[1]_INST_0_i_9_n_0 ),
.I2(sr_araddr[2]),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[1]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h0F00000008000000))
\m_axi_arlen[1]_INST_0_i_4
(.I0(s_axi_arlen_ii[3]),
.I1(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I2(sr_arburst[1]),
.I3(Q[32]),
.I4(sr_arburst[0]),
.I5(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFF000002000200))
\m_axi_arlen[1]_INST_0_i_5
(.I0(s_axi_arlen_ii[4]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[1]),
.I5(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h00000000000A000C))
\m_axi_arlen[1]_INST_0_i_6
(.I0(s_axi_arlen_ii[3]),
.I1(s_axi_arlen_ii[5]),
.I2(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[1]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT4 #(
.INIT(16'hEA00))
\m_axi_arlen[1]_INST_0_i_7
(.I0(sr_araddr[1]),
.I1(sr_araddr[0]),
.I2(s_axi_arlen_ii[0]),
.I3(s_axi_arlen_ii[1]),
.O(\m_axi_arlen[1]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT5 #(
.INIT(32'hFF808000))
\m_axi_arlen[1]_INST_0_i_8
(.I0(s_axi_arlen_ii[0]),
.I1(sr_araddr[1]),
.I2(sr_araddr[0]),
.I3(s_axi_arlen_ii[2]),
.I4(sr_araddr[2]),
.O(\m_axi_arlen[1]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
\m_axi_arlen[1]_INST_0_i_9
(.I0(\m_axi_arlen[1]_INST_0_i_7_n_0 ),
.I1(sr_araddr[3]),
.I2(s_axi_arlen_ii[4]),
.I3(sr_arburst[0]),
.I4(Q[32]),
.I5(sr_arburst[1]),
.O(\m_axi_arlen[1]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'h5555555555AA6A6A))
\m_axi_arlen[2]_INST_0
(.I0(\m_axi_arlen[2]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[5]),
.I2(in[9]),
.I3(s_axi_arlen_ii[2]),
.I4(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I5(\m_axi_arlen[2]_INST_0_i_3_n_0 ),
.O(in[2]));
LUT6 #(
.INIT(64'hFFFFC888C888C888))
\m_axi_arlen[2]_INST_0_i_1
(.I0(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[0]_INST_0_i_4_n_0 ),
.I2(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I3(s_axi_arlen_ii[4]),
.I4(\m_axi_arlen[4]_INST_0_i_3_n_0 ),
.I5(\m_axi_arlen[2]_INST_0_i_4_n_0 ),
.O(\m_axi_arlen[2]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'h02))
\m_axi_arlen[2]_INST_0_i_2
(.I0(sr_arsize[0]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.O(in[9]));
LUT6 #(
.INIT(64'h00000000000A000C))
\m_axi_arlen[2]_INST_0_i_3
(.I0(s_axi_arlen_ii[4]),
.I1(s_axi_arlen_ii[6]),
.I2(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[2]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000400000000000))
\m_axi_arlen[2]_INST_0_i_4
(.I0(sr_arburst[1]),
.I1(Q[32]),
.I2(sr_arburst[0]),
.I3(s_axi_arlen_ii[4]),
.I4(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I5(s_axi_arlen_ii[5]),
.O(\m_axi_arlen[2]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h00551555FFAAEAAA))
\m_axi_arlen[3]_INST_0
(.I0(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[5]),
.I3(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I4(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.I5(upsized_length[3]),
.O(in[3]));
LUT6 #(
.INIT(64'h0800000000000000))
\m_axi_arlen[3]_INST_0_i_1
(.I0(s_axi_arlen_ii[5]),
.I1(s_axi_arlen_ii[6]),
.I2(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I3(s_axi_arlen_ii[4]),
.I4(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
.I5(\m_axi_arlen[4]_INST_0_i_3_n_0 ),
.O(\m_axi_arlen[3]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h1010100010000000))
\m_axi_arlen[3]_INST_0_i_2
(.I0(sr_arsize[1]),
.I1(sr_arsize[2]),
.I2(sr_arsize[0]),
.I3(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
.I4(sr_araddr[3]),
.I5(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[3]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hFBEAEAEA))
\m_axi_arlen[3]_INST_0_i_3
(.I0(\m_axi_arlen[3]_INST_0_i_6_n_0 ),
.I1(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I2(s_axi_arlen_ii[3]),
.I3(in[9]),
.I4(s_axi_arlen_ii[6]),
.O(upsized_length[3]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'h40))
\m_axi_arlen[3]_INST_0_i_4
(.I0(sr_arburst[1]),
.I1(Q[32]),
.I2(sr_arburst[0]),
.O(\m_axi_arlen[3]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT4 #(
.INIT(16'hE8A0))
\m_axi_arlen[3]_INST_0_i_5
(.I0(s_axi_arlen_ii[1]),
.I1(sr_araddr[1]),
.I2(sr_araddr[2]),
.I3(s_axi_arlen_ii[0]),
.O(\m_axi_arlen[3]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h00000000000A000C))
\m_axi_arlen[3]_INST_0_i_6
(.I0(s_axi_arlen_ii[5]),
.I1(s_axi_arlen_ii[7]),
.I2(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[3]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'h00007FFFFFFF8000))
\m_axi_arlen[4]_INST_0
(.I0(\m_axi_arlen[4]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[7]),
.I3(\m_axi_arlen[4]_INST_0_i_3_n_0 ),
.I4(\m_axi_arlen[4]_INST_0_i_4_n_0 ),
.I5(upsized_length[4]),
.O(in[4]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h00004000))
\m_axi_arlen[4]_INST_0_i_1
(.I0(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[4]),
.I2(sr_arburst[0]),
.I3(Q[32]),
.I4(sr_arburst[1]),
.O(\m_axi_arlen[4]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arlen[4]_INST_0_i_2
(.I0(s_axi_arlen_ii[5]),
.I1(s_axi_arlen_ii[6]),
.O(\m_axi_arlen[4]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'hE8))
\m_axi_arlen[4]_INST_0_i_3
(.I0(sr_araddr[3]),
.I1(s_axi_arlen_ii[3]),
.I2(\m_axi_arlen[4]_INST_0_i_6_n_0 ),
.O(\m_axi_arlen[4]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'hEA000000))
\m_axi_arlen[4]_INST_0_i_4
(.I0(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[6]),
.I3(s_axi_arlen_ii[5]),
.I4(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.O(\m_axi_arlen[4]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFF0000F888F888))
\m_axi_arlen[4]_INST_0_i_5
(.I0(in[10]),
.I1(s_axi_arlen_ii[6]),
.I2(in[9]),
.I3(s_axi_arlen_ii[7]),
.I4(s_axi_arlen_ii[4]),
.I5(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.O(upsized_length[4]));
LUT6 #(
.INIT(64'hFCE8E8C0E8E8C0C0))
\m_axi_arlen[4]_INST_0_i_6
(.I0(s_axi_arlen_ii[1]),
.I1(sr_araddr[2]),
.I2(s_axi_arlen_ii[2]),
.I3(sr_araddr[0]),
.I4(sr_araddr[1]),
.I5(s_axi_arlen_ii[0]),
.O(\m_axi_arlen[4]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h596A6A6A))
\m_axi_arlen[5]_INST_0
(.I0(\m_axi_arlen[5]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.I2(s_axi_arlen_ii[5]),
.I3(in[10]),
.I4(s_axi_arlen_ii[7]),
.O(in[5]));
LUT6 #(
.INIT(64'hF800000000000000))
\m_axi_arlen[5]_INST_0_i_1
(.I0(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I1(s_axi_arlen_ii[7]),
.I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.I3(s_axi_arlen_ii[6]),
.I4(s_axi_arlen_ii[5]),
.I5(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.O(\m_axi_arlen[5]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'h10))
\m_axi_arlen[5]_INST_0_i_2
(.I0(sr_arsize[2]),
.I1(sr_arsize[0]),
.I2(sr_arsize[1]),
.O(in[10]));
LUT6 #(
.INIT(64'h7FFF000080000000))
\m_axi_arlen[6]_INST_0
(.I0(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[5]),
.I3(s_axi_arlen_ii[7]),
.I4(s_axi_arlen_ii[6]),
.I5(\m_axi_arlen[6]_INST_0_i_3_n_0 ),
.O(in[6]));
LUT6 #(
.INIT(64'h8888800080000000))
\m_axi_arlen[6]_INST_0_i_1
(.I0(s_axi_arlen_ii[2]),
.I1(in[10]),
.I2(s_axi_arlen_ii[0]),
.I3(sr_araddr[2]),
.I4(sr_araddr[3]),
.I5(s_axi_arlen_ii[1]),
.O(\m_axi_arlen[6]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h20000000))
\m_axi_arlen[6]_INST_0_i_2
(.I0(s_axi_arlen_ii[3]),
.I1(sr_arburst[1]),
.I2(Q[32]),
.I3(sr_arburst[0]),
.I4(s_axi_arlen_ii[4]),
.O(\m_axi_arlen[6]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'h1F))
\m_axi_arlen[6]_INST_0_i_3
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(Q[32]),
.O(\m_axi_arlen[6]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT4 #(
.INIT(16'h5700))
\m_axi_arlen[7]_INST_0
(.I0(Q[32]),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(s_axi_arlen_ii[7]),
.O(in[7]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT4 #(
.INIT(16'hF100))
\m_axi_arsize[0]_INST_0
(.I0(sr_arburst[0]),
.I1(sr_arburst[1]),
.I2(\m_axi_arsize[1]_INST_0_i_1_n_0 ),
.I3(sr_arsize[0]),
.O(m_axi_arsize[0]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT4 #(
.INIT(16'hF100))
\m_axi_arsize[1]_INST_0
(.I0(sr_arburst[0]),
.I1(sr_arburst[1]),
.I2(\m_axi_arsize[1]_INST_0_i_1_n_0 ),
.I3(sr_arsize[1]),
.O(m_axi_arsize[1]));
LUT6 #(
.INIT(64'h00000002FFFFFFFF))
\m_axi_arsize[1]_INST_0_i_1
(.I0(\m_axi_arsize[1]_INST_0_i_2_n_0 ),
.I1(\m_axi_arsize[2]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[3]),
.I3(s_axi_arlen_ii[2]),
.I4(\m_axi_arsize[2]_INST_0_i_3_n_0 ),
.I5(Q[32]),
.O(\m_axi_arsize[1]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT2 #(
.INIT(4'h1))
\m_axi_arsize[1]_INST_0_i_2
(.I0(s_axi_arlen_ii[0]),
.I1(s_axi_arlen_ii[1]),
.O(\m_axi_arsize[1]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT5 #(
.INIT(32'hFFFFE000))
\m_axi_arsize[2]_INST_0
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(Q[32]),
.I3(\m_axi_arsize[2]_INST_0_i_1_n_0 ),
.I4(sr_arsize[2]),
.O(m_axi_arsize[2]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\m_axi_arsize[2]_INST_0_i_1
(.I0(s_axi_arlen_ii[0]),
.I1(s_axi_arlen_ii[1]),
.I2(s_axi_arlen_ii[2]),
.I3(s_axi_arlen_ii[3]),
.I4(\m_axi_arsize[2]_INST_0_i_2_n_0 ),
.I5(\m_axi_arsize[2]_INST_0_i_3_n_0 ),
.O(\m_axi_arsize[2]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'hE))
\m_axi_arsize[2]_INST_0_i_2
(.I0(s_axi_arlen_ii[6]),
.I1(s_axi_arlen_ii[7]),
.O(\m_axi_arsize[2]_INST_0_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\m_axi_arsize[2]_INST_0_i_3
(.I0(s_axi_arlen_ii[4]),
.I1(s_axi_arlen_ii[5]),
.O(\m_axi_arsize[2]_INST_0_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[31]_i_1
(.I0(sr_arvalid),
.O(\m_payload_i[31]_i_1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[0]),
.Q(sr_araddr[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[10]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[11]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[12]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[13]),
.Q(Q[9]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[14]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[15]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[16]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[17]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[18]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[19]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[1]),
.Q(sr_araddr[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[20]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[21]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[22]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[23]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[24]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[25]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[26]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[27]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[28]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[29]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[2]),
.Q(sr_araddr[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[30]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[31]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[32]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[33]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[34]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[35]),
.Q(sr_arsize[0]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[36]),
.Q(sr_arsize[1]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[37]),
.Q(sr_arsize[2]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[38]),
.Q(sr_arburst[0]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[39]),
.Q(sr_arburst[1]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[3]),
.Q(sr_araddr[3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[40]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[41]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[42]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[43]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[44]),
.Q(s_axi_arlen_ii[0]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[45]),
.Q(s_axi_arlen_ii[1]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[46]),
.Q(s_axi_arlen_ii[2]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[47]),
.Q(s_axi_arlen_ii[3]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[48]),
.Q(s_axi_arlen_ii[4]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[49]),
.Q(s_axi_arlen_ii[5]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[4]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[50]),
.Q(s_axi_arlen_ii[6]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[51]),
.Q(s_axi_arlen_ii[7]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[52]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[53]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[54]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[55]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[56]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[57]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[58]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[5]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[59]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[60]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[6]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[7]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[8]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(out),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[9]),
.Q(Q[5]),
.R(1'b0));
LUT4 #(
.INIT(16'hB100))
m_valid_i_i_1
(.I0(s_axi_arready),
.I1(cmd_push_block_reg),
.I2(s_axi_arvalid),
.I3(s_ready_i_reg_0),
.O(m_valid_i_i_1_n_0));
FDRE m_valid_i_reg
(.C(out),
.CE(1'b1),
.D(m_valid_i_i_1_n_0),
.Q(sr_arvalid),
.R(1'b0));
LUT5 #(
.INIT(32'hDD5F0000))
s_ready_i_i_1
(.I0(s_ready_i_reg_0),
.I1(cmd_push_block_reg),
.I2(s_axi_arvalid),
.I3(sr_arvalid),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(s_axi_arready),
.R(1'b0));
LUT5 #(
.INIT(32'h00010111))
sub_sized_wrap0_carry_i_1
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.I3(s_axi_arlen_ii[2]),
.I4(s_axi_arlen_ii[3]),
.O(DI[1]));
LUT5 #(
.INIT(32'h00070077))
sub_sized_wrap0_carry_i_2
(.I0(s_axi_arlen_ii[1]),
.I1(s_axi_arlen_ii[0]),
.I2(sr_arsize[1]),
.I3(sr_arsize[2]),
.I4(sr_arsize[0]),
.O(DI[0]));
LUT2 #(
.INIT(4'h1))
sub_sized_wrap0_carry_i_3
(.I0(s_axi_arlen_ii[7]),
.I1(s_axi_arlen_ii[6]),
.O(S[3]));
LUT2 #(
.INIT(4'h1))
sub_sized_wrap0_carry_i_4
(.I0(s_axi_arlen_ii[5]),
.I1(s_axi_arlen_ii[4]),
.O(S[2]));
LUT5 #(
.INIT(32'h010010EE))
sub_sized_wrap0_carry_i_5
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.I3(s_axi_arlen_ii[2]),
.I4(s_axi_arlen_ii[3]),
.O(S[1]));
LUT5 #(
.INIT(32'h11181188))
sub_sized_wrap0_carry_i_6
(.I0(s_axi_arlen_ii[0]),
.I1(s_axi_arlen_ii[1]),
.I2(sr_arsize[0]),
.I3(sr_arsize[2]),
.I4(sr_arsize[1]),
.O(S[0]));
endmodule |
module system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2
(m_axi_rready,
mr_rvalid,
\s_axi_rdata[0] ,
Q,
\s_axi_rdata[1] ,
\s_axi_rdata[2] ,
\s_axi_rdata[3] ,
\s_axi_rdata[4] ,
\s_axi_rdata[5] ,
\s_axi_rdata[6] ,
\s_axi_rdata[7] ,
\s_axi_rdata[8] ,
\s_axi_rdata[9] ,
\s_axi_rdata[10] ,
\s_axi_rdata[11] ,
\s_axi_rdata[12] ,
\s_axi_rdata[13] ,
\s_axi_rdata[14] ,
\s_axi_rdata[15] ,
\s_axi_rdata[16] ,
\s_axi_rdata[17] ,
\s_axi_rdata[18] ,
\s_axi_rdata[19] ,
\s_axi_rdata[20] ,
\s_axi_rdata[21] ,
\s_axi_rdata[22] ,
\s_axi_rdata[23] ,
\s_axi_rdata[24] ,
\s_axi_rdata[25] ,
\s_axi_rdata[26] ,
\s_axi_rdata[27] ,
\s_axi_rdata[28] ,
\s_axi_rdata[29] ,
\s_axi_rdata[30] ,
\s_axi_rdata[31] ,
out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
E,
\aresetn_d_reg[1] ,
\aresetn_d_reg[0] );
output m_axi_rready;
output mr_rvalid;
output \s_axi_rdata[0] ;
output [130:0]Q;
output \s_axi_rdata[1] ;
output \s_axi_rdata[2] ;
output \s_axi_rdata[3] ;
output \s_axi_rdata[4] ;
output \s_axi_rdata[5] ;
output \s_axi_rdata[6] ;
output \s_axi_rdata[7] ;
output \s_axi_rdata[8] ;
output \s_axi_rdata[9] ;
output \s_axi_rdata[10] ;
output \s_axi_rdata[11] ;
output \s_axi_rdata[12] ;
output \s_axi_rdata[13] ;
output \s_axi_rdata[14] ;
output \s_axi_rdata[15] ;
output \s_axi_rdata[16] ;
output \s_axi_rdata[17] ;
output \s_axi_rdata[18] ;
output \s_axi_rdata[19] ;
output \s_axi_rdata[20] ;
output \s_axi_rdata[21] ;
output \s_axi_rdata[22] ;
output \s_axi_rdata[23] ;
output \s_axi_rdata[24] ;
output \s_axi_rdata[25] ;
output \s_axi_rdata[26] ;
output \s_axi_rdata[27] ;
output \s_axi_rdata[28] ;
output \s_axi_rdata[29] ;
output \s_axi_rdata[30] ;
output \s_axi_rdata[31] ;
input out;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ;
input m_axi_rlast;
input [1:0]m_axi_rresp;
input [127:0]m_axi_rdata;
input m_axi_rvalid;
input [0:0]E;
input \aresetn_d_reg[1] ;
input \aresetn_d_reg[0] ;
wire [0:0]E;
wire [130:0]Q;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1] ;
wire [127:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_valid_i_i_1__0_n_0;
wire mr_rvalid;
wire out;
wire \s_axi_rdata[0] ;
wire \s_axi_rdata[10] ;
wire \s_axi_rdata[11] ;
wire \s_axi_rdata[12] ;
wire \s_axi_rdata[13] ;
wire \s_axi_rdata[14] ;
wire \s_axi_rdata[15] ;
wire \s_axi_rdata[16] ;
wire \s_axi_rdata[17] ;
wire \s_axi_rdata[18] ;
wire \s_axi_rdata[19] ;
wire \s_axi_rdata[1] ;
wire \s_axi_rdata[20] ;
wire \s_axi_rdata[21] ;
wire \s_axi_rdata[22] ;
wire \s_axi_rdata[23] ;
wire \s_axi_rdata[24] ;
wire \s_axi_rdata[25] ;
wire \s_axi_rdata[26] ;
wire \s_axi_rdata[27] ;
wire \s_axi_rdata[28] ;
wire \s_axi_rdata[29] ;
wire \s_axi_rdata[2] ;
wire \s_axi_rdata[30] ;
wire \s_axi_rdata[31] ;
wire \s_axi_rdata[3] ;
wire \s_axi_rdata[4] ;
wire \s_axi_rdata[5] ;
wire \s_axi_rdata[6] ;
wire \s_axi_rdata[7] ;
wire \s_axi_rdata[8] ;
wire \s_axi_rdata[9] ;
wire s_ready_i_i_1_n_0;
wire [130:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[100] ;
wire \skid_buffer_reg_n_0_[101] ;
wire \skid_buffer_reg_n_0_[102] ;
wire \skid_buffer_reg_n_0_[103] ;
wire \skid_buffer_reg_n_0_[104] ;
wire \skid_buffer_reg_n_0_[105] ;
wire \skid_buffer_reg_n_0_[106] ;
wire \skid_buffer_reg_n_0_[107] ;
wire \skid_buffer_reg_n_0_[108] ;
wire \skid_buffer_reg_n_0_[109] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[110] ;
wire \skid_buffer_reg_n_0_[111] ;
wire \skid_buffer_reg_n_0_[112] ;
wire \skid_buffer_reg_n_0_[113] ;
wire \skid_buffer_reg_n_0_[114] ;
wire \skid_buffer_reg_n_0_[115] ;
wire \skid_buffer_reg_n_0_[116] ;
wire \skid_buffer_reg_n_0_[117] ;
wire \skid_buffer_reg_n_0_[118] ;
wire \skid_buffer_reg_n_0_[119] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[120] ;
wire \skid_buffer_reg_n_0_[121] ;
wire \skid_buffer_reg_n_0_[122] ;
wire \skid_buffer_reg_n_0_[123] ;
wire \skid_buffer_reg_n_0_[124] ;
wire \skid_buffer_reg_n_0_[125] ;
wire \skid_buffer_reg_n_0_[126] ;
wire \skid_buffer_reg_n_0_[127] ;
wire \skid_buffer_reg_n_0_[128] ;
wire \skid_buffer_reg_n_0_[129] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[130] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[65] ;
wire \skid_buffer_reg_n_0_[66] ;
wire \skid_buffer_reg_n_0_[67] ;
wire \skid_buffer_reg_n_0_[68] ;
wire \skid_buffer_reg_n_0_[69] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[70] ;
wire \skid_buffer_reg_n_0_[71] ;
wire \skid_buffer_reg_n_0_[72] ;
wire \skid_buffer_reg_n_0_[73] ;
wire \skid_buffer_reg_n_0_[74] ;
wire \skid_buffer_reg_n_0_[75] ;
wire \skid_buffer_reg_n_0_[76] ;
wire \skid_buffer_reg_n_0_[77] ;
wire \skid_buffer_reg_n_0_[78] ;
wire \skid_buffer_reg_n_0_[79] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[80] ;
wire \skid_buffer_reg_n_0_[81] ;
wire \skid_buffer_reg_n_0_[82] ;
wire \skid_buffer_reg_n_0_[83] ;
wire \skid_buffer_reg_n_0_[84] ;
wire \skid_buffer_reg_n_0_[85] ;
wire \skid_buffer_reg_n_0_[86] ;
wire \skid_buffer_reg_n_0_[87] ;
wire \skid_buffer_reg_n_0_[88] ;
wire \skid_buffer_reg_n_0_[89] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[90] ;
wire \skid_buffer_reg_n_0_[91] ;
wire \skid_buffer_reg_n_0_[92] ;
wire \skid_buffer_reg_n_0_[93] ;
wire \skid_buffer_reg_n_0_[94] ;
wire \skid_buffer_reg_n_0_[95] ;
wire \skid_buffer_reg_n_0_[96] ;
wire \skid_buffer_reg_n_0_[97] ;
wire \skid_buffer_reg_n_0_[98] ;
wire \skid_buffer_reg_n_0_[99] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(m_axi_rdata[0]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[100]_i_1
(.I0(m_axi_rdata[100]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[100] ),
.O(skid_buffer[100]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[101]_i_1
(.I0(m_axi_rdata[101]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[101] ),
.O(skid_buffer[101]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[102]_i_1
(.I0(m_axi_rdata[102]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[102] ),
.O(skid_buffer[102]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[103]_i_1
(.I0(m_axi_rdata[103]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[103] ),
.O(skid_buffer[103]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[104]_i_1
(.I0(m_axi_rdata[104]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[104] ),
.O(skid_buffer[104]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[105]_i_1
(.I0(m_axi_rdata[105]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[105] ),
.O(skid_buffer[105]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[106]_i_1
(.I0(m_axi_rdata[106]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[106] ),
.O(skid_buffer[106]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[107]_i_1
(.I0(m_axi_rdata[107]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[107] ),
.O(skid_buffer[107]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[108]_i_1
(.I0(m_axi_rdata[108]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[108] ),
.O(skid_buffer[108]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[109]_i_1
(.I0(m_axi_rdata[109]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[109] ),
.O(skid_buffer[109]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(m_axi_rdata[10]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[110]_i_1
(.I0(m_axi_rdata[110]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[110] ),
.O(skid_buffer[110]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[111]_i_1
(.I0(m_axi_rdata[111]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[111] ),
.O(skid_buffer[111]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[112]_i_1
(.I0(m_axi_rdata[112]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[112] ),
.O(skid_buffer[112]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[113]_i_1
(.I0(m_axi_rdata[113]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[113] ),
.O(skid_buffer[113]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[114]_i_1
(.I0(m_axi_rdata[114]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[114] ),
.O(skid_buffer[114]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[115]_i_1
(.I0(m_axi_rdata[115]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[115] ),
.O(skid_buffer[115]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[116]_i_1
(.I0(m_axi_rdata[116]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[116] ),
.O(skid_buffer[116]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[117]_i_1
(.I0(m_axi_rdata[117]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[117] ),
.O(skid_buffer[117]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[118]_i_1
(.I0(m_axi_rdata[118]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[118] ),
.O(skid_buffer[118]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[119]_i_1
(.I0(m_axi_rdata[119]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[119] ),
.O(skid_buffer[119]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(m_axi_rdata[11]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[120]_i_1
(.I0(m_axi_rdata[120]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[120] ),
.O(skid_buffer[120]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[121]_i_1
(.I0(m_axi_rdata[121]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[121] ),
.O(skid_buffer[121]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[122]_i_1
(.I0(m_axi_rdata[122]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[122] ),
.O(skid_buffer[122]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[123]_i_1
(.I0(m_axi_rdata[123]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[123] ),
.O(skid_buffer[123]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[124]_i_1
(.I0(m_axi_rdata[124]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[124] ),
.O(skid_buffer[124]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[125]_i_1
(.I0(m_axi_rdata[125]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[125] ),
.O(skid_buffer[125]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[126]_i_1
(.I0(m_axi_rdata[126]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[126] ),
.O(skid_buffer[126]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[127]_i_1
(.I0(m_axi_rdata[127]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[127] ),
.O(skid_buffer[127]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[128]_i_1
(.I0(m_axi_rresp[0]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[128] ),
.O(skid_buffer[128]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[129]_i_1
(.I0(m_axi_rresp[1]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[129] ),
.O(skid_buffer[129]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(m_axi_rdata[12]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[130]_i_2
(.I0(m_axi_rlast),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[130] ),
.O(skid_buffer[130]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(m_axi_rdata[13]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(m_axi_rdata[14]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(m_axi_rdata[15]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(m_axi_rdata[16]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(m_axi_rdata[17]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(m_axi_rdata[18]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(m_axi_rdata[19]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(m_axi_rdata[1]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(m_axi_rdata[20]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(m_axi_rdata[21]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(m_axi_rdata[22]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(m_axi_rdata[23]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(m_axi_rdata[24]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(m_axi_rdata[25]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(m_axi_rdata[26]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(m_axi_rdata[27]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(m_axi_rdata[28]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(m_axi_rdata[29]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(m_axi_rdata[2]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(m_axi_rdata[30]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__0
(.I0(m_axi_rdata[31]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(m_axi_rdata[32]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(m_axi_rdata[33]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(m_axi_rdata[34]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(m_axi_rdata[35]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(m_axi_rdata[36]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(m_axi_rdata[37]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(m_axi_rdata[38]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(m_axi_rdata[39]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(m_axi_rdata[3]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(m_axi_rdata[40]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(m_axi_rdata[41]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(m_axi_rdata[42]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(m_axi_rdata[43]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(m_axi_rdata[44]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(m_axi_rdata[45]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1
(.I0(m_axi_rdata[46]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(m_axi_rdata[47]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(m_axi_rdata[48]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(m_axi_rdata[49]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(m_axi_rdata[4]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(m_axi_rdata[50]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(m_axi_rdata[51]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(m_axi_rdata[52]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(m_axi_rdata[53]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(m_axi_rdata[54]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(m_axi_rdata[55]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(m_axi_rdata[56]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(m_axi_rdata[57]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(m_axi_rdata[58]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(m_axi_rdata[59]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(m_axi_rdata[5]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(m_axi_rdata[60]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(m_axi_rdata[61]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1
(.I0(m_axi_rdata[62]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(skid_buffer[62]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1
(.I0(m_axi_rdata[63]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(skid_buffer[63]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1
(.I0(m_axi_rdata[64]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(skid_buffer[64]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[65]_i_1
(.I0(m_axi_rdata[65]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[65] ),
.O(skid_buffer[65]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[66]_i_1
(.I0(m_axi_rdata[66]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[66] ),
.O(skid_buffer[66]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[67]_i_1
(.I0(m_axi_rdata[67]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[67] ),
.O(skid_buffer[67]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[68]_i_1
(.I0(m_axi_rdata[68]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[68] ),
.O(skid_buffer[68]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[69]_i_1
(.I0(m_axi_rdata[69]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[69] ),
.O(skid_buffer[69]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(m_axi_rdata[6]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[70]_i_1
(.I0(m_axi_rdata[70]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[70] ),
.O(skid_buffer[70]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[71]_i_1
(.I0(m_axi_rdata[71]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[71] ),
.O(skid_buffer[71]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[72]_i_1
(.I0(m_axi_rdata[72]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[72] ),
.O(skid_buffer[72]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[73]_i_1
(.I0(m_axi_rdata[73]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[73] ),
.O(skid_buffer[73]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[74]_i_1
(.I0(m_axi_rdata[74]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[74] ),
.O(skid_buffer[74]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[75]_i_1
(.I0(m_axi_rdata[75]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[75] ),
.O(skid_buffer[75]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[76]_i_1
(.I0(m_axi_rdata[76]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[76] ),
.O(skid_buffer[76]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[77]_i_1
(.I0(m_axi_rdata[77]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[77] ),
.O(skid_buffer[77]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[78]_i_1
(.I0(m_axi_rdata[78]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[78] ),
.O(skid_buffer[78]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[79]_i_1
(.I0(m_axi_rdata[79]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[79] ),
.O(skid_buffer[79]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(m_axi_rdata[7]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[80]_i_1
(.I0(m_axi_rdata[80]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[80] ),
.O(skid_buffer[80]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[81]_i_1
(.I0(m_axi_rdata[81]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[81] ),
.O(skid_buffer[81]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[82]_i_1
(.I0(m_axi_rdata[82]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[82] ),
.O(skid_buffer[82]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[83]_i_1
(.I0(m_axi_rdata[83]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[83] ),
.O(skid_buffer[83]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[84]_i_1
(.I0(m_axi_rdata[84]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[84] ),
.O(skid_buffer[84]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[85]_i_1
(.I0(m_axi_rdata[85]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[85] ),
.O(skid_buffer[85]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[86]_i_1
(.I0(m_axi_rdata[86]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[86] ),
.O(skid_buffer[86]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[87]_i_1
(.I0(m_axi_rdata[87]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[87] ),
.O(skid_buffer[87]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[88]_i_1
(.I0(m_axi_rdata[88]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[88] ),
.O(skid_buffer[88]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[89]_i_1
(.I0(m_axi_rdata[89]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[89] ),
.O(skid_buffer[89]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(m_axi_rdata[8]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[90]_i_1
(.I0(m_axi_rdata[90]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[90] ),
.O(skid_buffer[90]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[91]_i_1
(.I0(m_axi_rdata[91]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[91] ),
.O(skid_buffer[91]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[92]_i_1
(.I0(m_axi_rdata[92]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[92] ),
.O(skid_buffer[92]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[93]_i_1
(.I0(m_axi_rdata[93]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[93] ),
.O(skid_buffer[93]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[94]_i_1
(.I0(m_axi_rdata[94]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[94] ),
.O(skid_buffer[94]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[95]_i_1
(.I0(m_axi_rdata[95]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[95] ),
.O(skid_buffer[95]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[96]_i_1
(.I0(m_axi_rdata[96]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[96] ),
.O(skid_buffer[96]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[97]_i_1
(.I0(m_axi_rdata[97]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[97] ),
.O(skid_buffer[97]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[98]_i_1
(.I0(m_axi_rdata[98]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[98] ),
.O(skid_buffer[98]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[99]_i_1
(.I0(m_axi_rdata[99]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[99] ),
.O(skid_buffer[99]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(m_axi_rdata[9]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(out),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[100]
(.C(out),
.CE(E),
.D(skid_buffer[100]),
.Q(Q[100]),
.R(1'b0));
FDRE \m_payload_i_reg[101]
(.C(out),
.CE(E),
.D(skid_buffer[101]),
.Q(Q[101]),
.R(1'b0));
FDRE \m_payload_i_reg[102]
(.C(out),
.CE(E),
.D(skid_buffer[102]),
.Q(Q[102]),
.R(1'b0));
FDRE \m_payload_i_reg[103]
(.C(out),
.CE(E),
.D(skid_buffer[103]),
.Q(Q[103]),
.R(1'b0));
FDRE \m_payload_i_reg[104]
(.C(out),
.CE(E),
.D(skid_buffer[104]),
.Q(Q[104]),
.R(1'b0));
FDRE \m_payload_i_reg[105]
(.C(out),
.CE(E),
.D(skid_buffer[105]),
.Q(Q[105]),
.R(1'b0));
FDRE \m_payload_i_reg[106]
(.C(out),
.CE(E),
.D(skid_buffer[106]),
.Q(Q[106]),
.R(1'b0));
FDRE \m_payload_i_reg[107]
(.C(out),
.CE(E),
.D(skid_buffer[107]),
.Q(Q[107]),
.R(1'b0));
FDRE \m_payload_i_reg[108]
(.C(out),
.CE(E),
.D(skid_buffer[108]),
.Q(Q[108]),
.R(1'b0));
FDRE \m_payload_i_reg[109]
(.C(out),
.CE(E),
.D(skid_buffer[109]),
.Q(Q[109]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(out),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[110]
(.C(out),
.CE(E),
.D(skid_buffer[110]),
.Q(Q[110]),
.R(1'b0));
FDRE \m_payload_i_reg[111]
(.C(out),
.CE(E),
.D(skid_buffer[111]),
.Q(Q[111]),
.R(1'b0));
FDRE \m_payload_i_reg[112]
(.C(out),
.CE(E),
.D(skid_buffer[112]),
.Q(Q[112]),
.R(1'b0));
FDRE \m_payload_i_reg[113]
(.C(out),
.CE(E),
.D(skid_buffer[113]),
.Q(Q[113]),
.R(1'b0));
FDRE \m_payload_i_reg[114]
(.C(out),
.CE(E),
.D(skid_buffer[114]),
.Q(Q[114]),
.R(1'b0));
FDRE \m_payload_i_reg[115]
(.C(out),
.CE(E),
.D(skid_buffer[115]),
.Q(Q[115]),
.R(1'b0));
FDRE \m_payload_i_reg[116]
(.C(out),
.CE(E),
.D(skid_buffer[116]),
.Q(Q[116]),
.R(1'b0));
FDRE \m_payload_i_reg[117]
(.C(out),
.CE(E),
.D(skid_buffer[117]),
.Q(Q[117]),
.R(1'b0));
FDRE \m_payload_i_reg[118]
(.C(out),
.CE(E),
.D(skid_buffer[118]),
.Q(Q[118]),
.R(1'b0));
FDRE \m_payload_i_reg[119]
(.C(out),
.CE(E),
.D(skid_buffer[119]),
.Q(Q[119]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(out),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[120]
(.C(out),
.CE(E),
.D(skid_buffer[120]),
.Q(Q[120]),
.R(1'b0));
FDRE \m_payload_i_reg[121]
(.C(out),
.CE(E),
.D(skid_buffer[121]),
.Q(Q[121]),
.R(1'b0));
FDRE \m_payload_i_reg[122]
(.C(out),
.CE(E),
.D(skid_buffer[122]),
.Q(Q[122]),
.R(1'b0));
FDRE \m_payload_i_reg[123]
(.C(out),
.CE(E),
.D(skid_buffer[123]),
.Q(Q[123]),
.R(1'b0));
FDRE \m_payload_i_reg[124]
(.C(out),
.CE(E),
.D(skid_buffer[124]),
.Q(Q[124]),
.R(1'b0));
FDRE \m_payload_i_reg[125]
(.C(out),
.CE(E),
.D(skid_buffer[125]),
.Q(Q[125]),
.R(1'b0));
FDRE \m_payload_i_reg[126]
(.C(out),
.CE(E),
.D(skid_buffer[126]),
.Q(Q[126]),
.R(1'b0));
FDRE \m_payload_i_reg[127]
(.C(out),
.CE(E),
.D(skid_buffer[127]),
.Q(Q[127]),
.R(1'b0));
FDRE \m_payload_i_reg[128]
(.C(out),
.CE(E),
.D(skid_buffer[128]),
.Q(Q[128]),
.R(1'b0));
FDRE \m_payload_i_reg[129]
(.C(out),
.CE(E),
.D(skid_buffer[129]),
.Q(Q[129]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(out),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[130]
(.C(out),
.CE(E),
.D(skid_buffer[130]),
.Q(Q[130]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(out),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(out),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(out),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(out),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(out),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(out),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(out),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(out),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(out),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(out),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(out),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(out),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(out),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(out),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(out),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(out),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(out),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(out),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(out),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(out),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(out),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(out),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(out),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(out),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(out),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(out),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(out),
.CE(E),
.D(skid_buffer[37]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(out),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(out),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(out),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(out),
.CE(E),
.D(skid_buffer[40]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(out),
.CE(E),
.D(skid_buffer[41]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(out),
.CE(E),
.D(skid_buffer[42]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(out),
.CE(E),
.D(skid_buffer[43]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(out),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(out),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(out),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(out),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(out),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(out),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(out),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(out),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(out),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(out),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(out),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(out),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(out),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(out),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(out),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(out),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(out),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[59]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(out),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(out),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[60]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(out),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[61]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(out),
.CE(E),
.D(skid_buffer[62]),
.Q(Q[62]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(out),
.CE(E),
.D(skid_buffer[63]),
.Q(Q[63]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(out),
.CE(E),
.D(skid_buffer[64]),
.Q(Q[64]),
.R(1'b0));
FDRE \m_payload_i_reg[65]
(.C(out),
.CE(E),
.D(skid_buffer[65]),
.Q(Q[65]),
.R(1'b0));
FDRE \m_payload_i_reg[66]
(.C(out),
.CE(E),
.D(skid_buffer[66]),
.Q(Q[66]),
.R(1'b0));
FDRE \m_payload_i_reg[67]
(.C(out),
.CE(E),
.D(skid_buffer[67]),
.Q(Q[67]),
.R(1'b0));
FDRE \m_payload_i_reg[68]
(.C(out),
.CE(E),
.D(skid_buffer[68]),
.Q(Q[68]),
.R(1'b0));
FDRE \m_payload_i_reg[69]
(.C(out),
.CE(E),
.D(skid_buffer[69]),
.Q(Q[69]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(out),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[70]
(.C(out),
.CE(E),
.D(skid_buffer[70]),
.Q(Q[70]),
.R(1'b0));
FDRE \m_payload_i_reg[71]
(.C(out),
.CE(E),
.D(skid_buffer[71]),
.Q(Q[71]),
.R(1'b0));
FDRE \m_payload_i_reg[72]
(.C(out),
.CE(E),
.D(skid_buffer[72]),
.Q(Q[72]),
.R(1'b0));
FDRE \m_payload_i_reg[73]
(.C(out),
.CE(E),
.D(skid_buffer[73]),
.Q(Q[73]),
.R(1'b0));
FDRE \m_payload_i_reg[74]
(.C(out),
.CE(E),
.D(skid_buffer[74]),
.Q(Q[74]),
.R(1'b0));
FDRE \m_payload_i_reg[75]
(.C(out),
.CE(E),
.D(skid_buffer[75]),
.Q(Q[75]),
.R(1'b0));
FDRE \m_payload_i_reg[76]
(.C(out),
.CE(E),
.D(skid_buffer[76]),
.Q(Q[76]),
.R(1'b0));
FDRE \m_payload_i_reg[77]
(.C(out),
.CE(E),
.D(skid_buffer[77]),
.Q(Q[77]),
.R(1'b0));
FDRE \m_payload_i_reg[78]
(.C(out),
.CE(E),
.D(skid_buffer[78]),
.Q(Q[78]),
.R(1'b0));
FDRE \m_payload_i_reg[79]
(.C(out),
.CE(E),
.D(skid_buffer[79]),
.Q(Q[79]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(out),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[80]
(.C(out),
.CE(E),
.D(skid_buffer[80]),
.Q(Q[80]),
.R(1'b0));
FDRE \m_payload_i_reg[81]
(.C(out),
.CE(E),
.D(skid_buffer[81]),
.Q(Q[81]),
.R(1'b0));
FDRE \m_payload_i_reg[82]
(.C(out),
.CE(E),
.D(skid_buffer[82]),
.Q(Q[82]),
.R(1'b0));
FDRE \m_payload_i_reg[83]
(.C(out),
.CE(E),
.D(skid_buffer[83]),
.Q(Q[83]),
.R(1'b0));
FDRE \m_payload_i_reg[84]
(.C(out),
.CE(E),
.D(skid_buffer[84]),
.Q(Q[84]),
.R(1'b0));
FDRE \m_payload_i_reg[85]
(.C(out),
.CE(E),
.D(skid_buffer[85]),
.Q(Q[85]),
.R(1'b0));
FDRE \m_payload_i_reg[86]
(.C(out),
.CE(E),
.D(skid_buffer[86]),
.Q(Q[86]),
.R(1'b0));
FDRE \m_payload_i_reg[87]
(.C(out),
.CE(E),
.D(skid_buffer[87]),
.Q(Q[87]),
.R(1'b0));
FDRE \m_payload_i_reg[88]
(.C(out),
.CE(E),
.D(skid_buffer[88]),
.Q(Q[88]),
.R(1'b0));
FDRE \m_payload_i_reg[89]
(.C(out),
.CE(E),
.D(skid_buffer[89]),
.Q(Q[89]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(out),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[90]
(.C(out),
.CE(E),
.D(skid_buffer[90]),
.Q(Q[90]),
.R(1'b0));
FDRE \m_payload_i_reg[91]
(.C(out),
.CE(E),
.D(skid_buffer[91]),
.Q(Q[91]),
.R(1'b0));
FDRE \m_payload_i_reg[92]
(.C(out),
.CE(E),
.D(skid_buffer[92]),
.Q(Q[92]),
.R(1'b0));
FDRE \m_payload_i_reg[93]
(.C(out),
.CE(E),
.D(skid_buffer[93]),
.Q(Q[93]),
.R(1'b0));
FDRE \m_payload_i_reg[94]
(.C(out),
.CE(E),
.D(skid_buffer[94]),
.Q(Q[94]),
.R(1'b0));
FDRE \m_payload_i_reg[95]
(.C(out),
.CE(E),
.D(skid_buffer[95]),
.Q(Q[95]),
.R(1'b0));
FDRE \m_payload_i_reg[96]
(.C(out),
.CE(E),
.D(skid_buffer[96]),
.Q(Q[96]),
.R(1'b0));
FDRE \m_payload_i_reg[97]
(.C(out),
.CE(E),
.D(skid_buffer[97]),
.Q(Q[97]),
.R(1'b0));
FDRE \m_payload_i_reg[98]
(.C(out),
.CE(E),
.D(skid_buffer[98]),
.Q(Q[98]),
.R(1'b0));
FDRE \m_payload_i_reg[99]
(.C(out),
.CE(E),
.D(skid_buffer[99]),
.Q(Q[99]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(out),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hDF00))
m_valid_i_i_1__0
(.I0(m_axi_rready),
.I1(m_axi_rvalid),
.I2(E),
.I3(\aresetn_d_reg[1] ),
.O(m_valid_i_i_1__0_n_0));
FDRE m_valid_i_reg
(.C(out),
.CE(1'b1),
.D(m_valid_i_i_1__0_n_0),
.Q(mr_rvalid),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[0]_INST_0_i_1
(.I0(Q[0]),
.I1(Q[64]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[32]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[96]),
.O(\s_axi_rdata[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[10]_INST_0_i_1
(.I0(Q[10]),
.I1(Q[74]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[42]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[106]),
.O(\s_axi_rdata[10] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[11]_INST_0_i_1
(.I0(Q[11]),
.I1(Q[75]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[43]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[107]),
.O(\s_axi_rdata[11] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[12]_INST_0_i_1
(.I0(Q[12]),
.I1(Q[76]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[44]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[108]),
.O(\s_axi_rdata[12] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[13]_INST_0_i_1
(.I0(Q[13]),
.I1(Q[77]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[45]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[109]),
.O(\s_axi_rdata[13] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[14]_INST_0_i_1
(.I0(Q[14]),
.I1(Q[78]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[46]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[110]),
.O(\s_axi_rdata[14] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[15]_INST_0_i_1
(.I0(Q[15]),
.I1(Q[79]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[47]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[111]),
.O(\s_axi_rdata[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[16]_INST_0_i_1
(.I0(Q[16]),
.I1(Q[80]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[48]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[112]),
.O(\s_axi_rdata[16] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[17]_INST_0_i_1
(.I0(Q[17]),
.I1(Q[81]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[49]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[113]),
.O(\s_axi_rdata[17] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[18]_INST_0_i_1
(.I0(Q[18]),
.I1(Q[82]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[50]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[114]),
.O(\s_axi_rdata[18] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[19]_INST_0_i_1
(.I0(Q[19]),
.I1(Q[83]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[51]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[115]),
.O(\s_axi_rdata[19] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[1]_INST_0_i_1
(.I0(Q[1]),
.I1(Q[65]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[33]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[97]),
.O(\s_axi_rdata[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[20]_INST_0_i_1
(.I0(Q[20]),
.I1(Q[84]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[52]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[116]),
.O(\s_axi_rdata[20] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[21]_INST_0_i_1
(.I0(Q[21]),
.I1(Q[85]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[53]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[117]),
.O(\s_axi_rdata[21] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[22]_INST_0_i_1
(.I0(Q[22]),
.I1(Q[86]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[54]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[118]),
.O(\s_axi_rdata[22] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[23]_INST_0_i_1
(.I0(Q[23]),
.I1(Q[87]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[55]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[119]),
.O(\s_axi_rdata[23] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[24]_INST_0_i_1
(.I0(Q[24]),
.I1(Q[88]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[56]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[120]),
.O(\s_axi_rdata[24] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[25]_INST_0_i_1
(.I0(Q[25]),
.I1(Q[89]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[57]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[121]),
.O(\s_axi_rdata[25] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[26]_INST_0_i_1
(.I0(Q[26]),
.I1(Q[90]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[58]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[122]),
.O(\s_axi_rdata[26] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[27]_INST_0_i_1
(.I0(Q[27]),
.I1(Q[91]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[59]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[123]),
.O(\s_axi_rdata[27] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[28]_INST_0_i_1
(.I0(Q[28]),
.I1(Q[92]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[60]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[124]),
.O(\s_axi_rdata[28] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[29]_INST_0_i_1
(.I0(Q[29]),
.I1(Q[93]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[61]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[125]),
.O(\s_axi_rdata[29] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[2]_INST_0_i_1
(.I0(Q[2]),
.I1(Q[66]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[34]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[98]),
.O(\s_axi_rdata[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[30]_INST_0_i_1
(.I0(Q[30]),
.I1(Q[94]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[62]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[126]),
.O(\s_axi_rdata[30] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[31]_INST_0_i_1
(.I0(Q[31]),
.I1(Q[95]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[63]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[127]),
.O(\s_axi_rdata[31] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[3]_INST_0_i_1
(.I0(Q[3]),
.I1(Q[67]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[35]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[99]),
.O(\s_axi_rdata[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[4]_INST_0_i_1
(.I0(Q[4]),
.I1(Q[68]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[36]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[100]),
.O(\s_axi_rdata[4] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[5]_INST_0_i_1
(.I0(Q[5]),
.I1(Q[69]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[37]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[101]),
.O(\s_axi_rdata[5] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[6]_INST_0_i_1
(.I0(Q[6]),
.I1(Q[70]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[38]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[102]),
.O(\s_axi_rdata[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[7]_INST_0_i_1
(.I0(Q[7]),
.I1(Q[71]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[39]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[103]),
.O(\s_axi_rdata[7] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[8]_INST_0_i_1
(.I0(Q[8]),
.I1(Q[72]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[40]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[104]),
.O(\s_axi_rdata[8] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[9]_INST_0_i_1
(.I0(Q[9]),
.I1(Q[73]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.I3(Q[41]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30] ),
.I5(Q[105]),
.O(\s_axi_rdata[9] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hF200))
s_ready_i_i_1
(.I0(m_axi_rready),
.I1(m_axi_rvalid),
.I2(E),
.I3(\aresetn_d_reg[0] ),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(m_axi_rready),
.R(1'b0));
FDRE \skid_buffer_reg[0]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[100]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[100]),
.Q(\skid_buffer_reg_n_0_[100] ),
.R(1'b0));
FDRE \skid_buffer_reg[101]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[101]),
.Q(\skid_buffer_reg_n_0_[101] ),
.R(1'b0));
FDRE \skid_buffer_reg[102]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[102]),
.Q(\skid_buffer_reg_n_0_[102] ),
.R(1'b0));
FDRE \skid_buffer_reg[103]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[103]),
.Q(\skid_buffer_reg_n_0_[103] ),
.R(1'b0));
FDRE \skid_buffer_reg[104]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[104]),
.Q(\skid_buffer_reg_n_0_[104] ),
.R(1'b0));
FDRE \skid_buffer_reg[105]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[105]),
.Q(\skid_buffer_reg_n_0_[105] ),
.R(1'b0));
FDRE \skid_buffer_reg[106]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[106]),
.Q(\skid_buffer_reg_n_0_[106] ),
.R(1'b0));
FDRE \skid_buffer_reg[107]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[107]),
.Q(\skid_buffer_reg_n_0_[107] ),
.R(1'b0));
FDRE \skid_buffer_reg[108]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[108]),
.Q(\skid_buffer_reg_n_0_[108] ),
.R(1'b0));
FDRE \skid_buffer_reg[109]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[109]),
.Q(\skid_buffer_reg_n_0_[109] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[110]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[110]),
.Q(\skid_buffer_reg_n_0_[110] ),
.R(1'b0));
FDRE \skid_buffer_reg[111]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[111]),
.Q(\skid_buffer_reg_n_0_[111] ),
.R(1'b0));
FDRE \skid_buffer_reg[112]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[112]),
.Q(\skid_buffer_reg_n_0_[112] ),
.R(1'b0));
FDRE \skid_buffer_reg[113]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[113]),
.Q(\skid_buffer_reg_n_0_[113] ),
.R(1'b0));
FDRE \skid_buffer_reg[114]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[114]),
.Q(\skid_buffer_reg_n_0_[114] ),
.R(1'b0));
FDRE \skid_buffer_reg[115]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[115]),
.Q(\skid_buffer_reg_n_0_[115] ),
.R(1'b0));
FDRE \skid_buffer_reg[116]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[116]),
.Q(\skid_buffer_reg_n_0_[116] ),
.R(1'b0));
FDRE \skid_buffer_reg[117]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[117]),
.Q(\skid_buffer_reg_n_0_[117] ),
.R(1'b0));
FDRE \skid_buffer_reg[118]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[118]),
.Q(\skid_buffer_reg_n_0_[118] ),
.R(1'b0));
FDRE \skid_buffer_reg[119]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[119]),
.Q(\skid_buffer_reg_n_0_[119] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[120]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[120]),
.Q(\skid_buffer_reg_n_0_[120] ),
.R(1'b0));
FDRE \skid_buffer_reg[121]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[121]),
.Q(\skid_buffer_reg_n_0_[121] ),
.R(1'b0));
FDRE \skid_buffer_reg[122]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[122]),
.Q(\skid_buffer_reg_n_0_[122] ),
.R(1'b0));
FDRE \skid_buffer_reg[123]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[123]),
.Q(\skid_buffer_reg_n_0_[123] ),
.R(1'b0));
FDRE \skid_buffer_reg[124]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[124]),
.Q(\skid_buffer_reg_n_0_[124] ),
.R(1'b0));
FDRE \skid_buffer_reg[125]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[125]),
.Q(\skid_buffer_reg_n_0_[125] ),
.R(1'b0));
FDRE \skid_buffer_reg[126]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[126]),
.Q(\skid_buffer_reg_n_0_[126] ),
.R(1'b0));
FDRE \skid_buffer_reg[127]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[127]),
.Q(\skid_buffer_reg_n_0_[127] ),
.R(1'b0));
FDRE \skid_buffer_reg[128]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[128] ),
.R(1'b0));
FDRE \skid_buffer_reg[129]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[129] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[130]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[130] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[34]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[35]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[36]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[37]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[38]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[39]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[40]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[41]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[42]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[43]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[44]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[45]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[46]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[47]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[48]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[49]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[50]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[51]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[52]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[53]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[54]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[55]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[56]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[57]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[58]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[59]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[60]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[61]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[62]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[63]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[64]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[65]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[65]),
.Q(\skid_buffer_reg_n_0_[65] ),
.R(1'b0));
FDRE \skid_buffer_reg[66]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[66]),
.Q(\skid_buffer_reg_n_0_[66] ),
.R(1'b0));
FDRE \skid_buffer_reg[67]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[67]),
.Q(\skid_buffer_reg_n_0_[67] ),
.R(1'b0));
FDRE \skid_buffer_reg[68]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[68]),
.Q(\skid_buffer_reg_n_0_[68] ),
.R(1'b0));
FDRE \skid_buffer_reg[69]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[69]),
.Q(\skid_buffer_reg_n_0_[69] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[70]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[70]),
.Q(\skid_buffer_reg_n_0_[70] ),
.R(1'b0));
FDRE \skid_buffer_reg[71]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[71]),
.Q(\skid_buffer_reg_n_0_[71] ),
.R(1'b0));
FDRE \skid_buffer_reg[72]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[72]),
.Q(\skid_buffer_reg_n_0_[72] ),
.R(1'b0));
FDRE \skid_buffer_reg[73]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[73]),
.Q(\skid_buffer_reg_n_0_[73] ),
.R(1'b0));
FDRE \skid_buffer_reg[74]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[74]),
.Q(\skid_buffer_reg_n_0_[74] ),
.R(1'b0));
FDRE \skid_buffer_reg[75]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[75]),
.Q(\skid_buffer_reg_n_0_[75] ),
.R(1'b0));
FDRE \skid_buffer_reg[76]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[76]),
.Q(\skid_buffer_reg_n_0_[76] ),
.R(1'b0));
FDRE \skid_buffer_reg[77]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[77]),
.Q(\skid_buffer_reg_n_0_[77] ),
.R(1'b0));
FDRE \skid_buffer_reg[78]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[78]),
.Q(\skid_buffer_reg_n_0_[78] ),
.R(1'b0));
FDRE \skid_buffer_reg[79]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[79]),
.Q(\skid_buffer_reg_n_0_[79] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[80]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[80]),
.Q(\skid_buffer_reg_n_0_[80] ),
.R(1'b0));
FDRE \skid_buffer_reg[81]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[81]),
.Q(\skid_buffer_reg_n_0_[81] ),
.R(1'b0));
FDRE \skid_buffer_reg[82]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[82]),
.Q(\skid_buffer_reg_n_0_[82] ),
.R(1'b0));
FDRE \skid_buffer_reg[83]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[83]),
.Q(\skid_buffer_reg_n_0_[83] ),
.R(1'b0));
FDRE \skid_buffer_reg[84]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[84]),
.Q(\skid_buffer_reg_n_0_[84] ),
.R(1'b0));
FDRE \skid_buffer_reg[85]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[85]),
.Q(\skid_buffer_reg_n_0_[85] ),
.R(1'b0));
FDRE \skid_buffer_reg[86]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[86]),
.Q(\skid_buffer_reg_n_0_[86] ),
.R(1'b0));
FDRE \skid_buffer_reg[87]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[87]),
.Q(\skid_buffer_reg_n_0_[87] ),
.R(1'b0));
FDRE \skid_buffer_reg[88]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[88]),
.Q(\skid_buffer_reg_n_0_[88] ),
.R(1'b0));
FDRE \skid_buffer_reg[89]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[89]),
.Q(\skid_buffer_reg_n_0_[89] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[90]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[90]),
.Q(\skid_buffer_reg_n_0_[90] ),
.R(1'b0));
FDRE \skid_buffer_reg[91]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[91]),
.Q(\skid_buffer_reg_n_0_[91] ),
.R(1'b0));
FDRE \skid_buffer_reg[92]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[92]),
.Q(\skid_buffer_reg_n_0_[92] ),
.R(1'b0));
FDRE \skid_buffer_reg[93]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[93]),
.Q(\skid_buffer_reg_n_0_[93] ),
.R(1'b0));
FDRE \skid_buffer_reg[94]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[94]),
.Q(\skid_buffer_reg_n_0_[94] ),
.R(1'b0));
FDRE \skid_buffer_reg[95]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[95]),
.Q(\skid_buffer_reg_n_0_[95] ),
.R(1'b0));
FDRE \skid_buffer_reg[96]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[96]),
.Q(\skid_buffer_reg_n_0_[96] ),
.R(1'b0));
FDRE \skid_buffer_reg[97]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[97]),
.Q(\skid_buffer_reg_n_0_[97] ),
.R(1'b0));
FDRE \skid_buffer_reg[98]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[98]),
.Q(\skid_buffer_reg_n_0_[98] ),
.R(1'b0));
FDRE \skid_buffer_reg[99]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[99]),
.Q(\skid_buffer_reg_n_0_[99] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(out),
.CE(m_axi_rready),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo
(\M_AXI_RDATA_I_reg[127] ,
\USE_RTL_LENGTH.length_counter_q_reg[7] ,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ,
E,
D,
\current_word_1_reg[3] ,
Q,
first_word_reg,
first_word_reg_0,
\s_axi_rdata[31] ,
\s_axi_rdata[31]_0 ,
s_axi_rvalid,
\M_AXI_RDATA_I_reg[127]_0 ,
s_ready_i_reg,
cmd_push_block0,
m_axi_arvalid,
SR,
out,
mr_rvalid,
wrap_buffer_available_reg,
use_wrap_buffer,
wrap_buffer_available,
\USE_RTL_LENGTH.length_counter_q_reg[1] ,
s_axi_rready,
\pre_next_word_1_reg[2] ,
\pre_next_word_1_reg[3] ,
\pre_next_word_1_reg[3]_0 ,
first_word,
cmd_push_block,
sr_arvalid,
use_wrap_buffer_reg,
\current_word_1_reg[3]_0 ,
\current_word_1_reg[2] ,
\current_word_1_reg[3]_1 ,
first_mi_word_q,
m_axi_arready,
s_axi_aresetn,
in);
output \M_AXI_RDATA_I_reg[127] ;
output \USE_RTL_LENGTH.length_counter_q_reg[7] ;
output \USE_RTL_LENGTH.length_counter_q_reg[7]_0 ;
output [0:0]E;
output [3:0]D;
output [3:0]\current_word_1_reg[3] ;
output [12:0]Q;
output first_word_reg;
output first_word_reg_0;
output \s_axi_rdata[31] ;
output \s_axi_rdata[31]_0 ;
output s_axi_rvalid;
output [0:0]\M_AXI_RDATA_I_reg[127]_0 ;
output s_ready_i_reg;
output cmd_push_block0;
output m_axi_arvalid;
input [0:0]SR;
input out;
input mr_rvalid;
input wrap_buffer_available_reg;
input use_wrap_buffer;
input wrap_buffer_available;
input \USE_RTL_LENGTH.length_counter_q_reg[1] ;
input s_axi_rready;
input \pre_next_word_1_reg[2] ;
input \pre_next_word_1_reg[3] ;
input [3:0]\pre_next_word_1_reg[3]_0 ;
input first_word;
input cmd_push_block;
input sr_arvalid;
input use_wrap_buffer_reg;
input \current_word_1_reg[3]_0 ;
input \current_word_1_reg[2] ;
input [3:0]\current_word_1_reg[3]_1 ;
input first_mi_word_q;
input m_axi_arready;
input s_axi_aresetn;
input [32:0]in;
wire [3:0]D;
wire [0:0]E;
wire \M_AXI_RDATA_I_reg[127] ;
wire [0:0]\M_AXI_RDATA_I_reg[127]_0 ;
wire [12:0]Q;
wire [0:0]SR;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0 ;
wire \USE_RTL_ADDR.addr_q[0]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[1]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[2]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[3]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_2_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_3_n_0 ;
wire [4:0]\USE_RTL_ADDR.addr_q_reg__0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q_reg[1] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7]_0 ;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0 ;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0 ;
wire addr_q;
wire buffer_Full_q;
wire [3:0]cmd_last_word;
wire cmd_push_block;
wire cmd_push_block0;
wire [2:0]cmd_step;
wire \current_word_1_reg[2] ;
wire [3:0]\current_word_1_reg[3] ;
wire \current_word_1_reg[3]_0 ;
wire [3:0]\current_word_1_reg[3]_1 ;
wire data_Exists_I;
wire data_Exists_I_i_2_n_0;
wire first_mi_word_q;
wire first_word;
wire first_word_reg;
wire first_word_reg_0;
wire [32:0]in;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i[130]_i_3_n_0 ;
wire \m_payload_i[130]_i_4_n_0 ;
wire \m_payload_i[130]_i_6_n_0 ;
wire mr_rvalid;
wire next_Data_Exists;
wire out;
wire \pre_next_word_1[1]_i_2_n_0 ;
wire \pre_next_word_1[3]_i_4_n_0 ;
wire \pre_next_word_1_reg[2] ;
wire \pre_next_word_1_reg[3] ;
wire [3:0]\pre_next_word_1_reg[3]_0 ;
wire rd_cmd_complete_wrap;
wire [1:0]rd_cmd_first_word;
wire [3:0]rd_cmd_mask;
wire rd_cmd_modified;
wire [1:0]rd_cmd_next_word;
wire [3:2]rd_cmd_offset;
wire rd_cmd_packed_wrap;
wire s_axi_aresetn;
wire \s_axi_rdata[31] ;
wire \s_axi_rdata[31]_0 ;
wire s_axi_rlast_INST_0_i_10_n_0;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_reg;
wire sr_arvalid;
wire use_wrap_buffer;
wire use_wrap_buffer_reg;
wire valid_Write;
wire wrap_buffer_available;
wire wrap_buffer_available_reg;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT5 #(
.INIT(32'h00800000))
\M_AXI_RDATA_I[127]_i_1
(.I0(mr_rvalid),
.I1(\M_AXI_RDATA_I_reg[127] ),
.I2(first_mi_word_q),
.I3(use_wrap_buffer),
.I4(rd_cmd_packed_wrap),
.O(\M_AXI_RDATA_I_reg[127]_0 ));
LUT6 #(
.INIT(64'h00005501FFFFFFFF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0 ),
.I1(wrap_buffer_available),
.I2(\USE_RTL_LENGTH.length_counter_q_reg[1] ),
.I3(use_wrap_buffer),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0 ),
.I5(\M_AXI_RDATA_I_reg[127] ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT4 #(
.INIT(16'h07FF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3
(.I0(\M_AXI_RDATA_I_reg[127] ),
.I1(mr_rvalid),
.I2(use_wrap_buffer),
.I3(s_axi_rready),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF9F9FF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4
(.I0(cmd_last_word[3]),
.I1(\current_word_1_reg[3]_0 ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0 ),
.I3(cmd_last_word[2]),
.I4(\current_word_1_reg[2] ),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0 ));
LUT5 #(
.INIT(32'h6665666A))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5
(.I0(cmd_last_word[1]),
.I1(rd_cmd_first_word[1]),
.I2(first_word),
.I3(Q[12]),
.I4(\current_word_1_reg[3]_1 [1]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0 ));
LUT5 #(
.INIT(32'h6665666A))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6
(.I0(cmd_last_word[0]),
.I1(rd_cmd_first_word[0]),
.I2(first_word),
.I3(Q[12]),
.I4(\current_word_1_reg[3]_1 [0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0 ));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ),
.Q(Q[0]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ),
.Q(cmd_step[2]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ),
.Q(rd_cmd_mask[0]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ),
.Q(rd_cmd_mask[1]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ),
.Q(rd_cmd_mask[2]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0 ),
.Q(rd_cmd_mask[3]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ),
.Q(rd_cmd_offset[2]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ),
.Q(rd_cmd_offset[3]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ),
.Q(cmd_last_word[0]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ),
.Q(Q[1]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ),
.Q(cmd_last_word[1]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ),
.Q(cmd_last_word[2]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ),
.Q(cmd_last_word[3]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ),
.Q(rd_cmd_next_word[0]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ),
.Q(rd_cmd_next_word[1]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ),
.Q(Q[8]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ),
.Q(Q[9]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ),
.Q(rd_cmd_first_word[0]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ),
.Q(rd_cmd_first_word[1]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ),
.Q(Q[10]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ),
.Q(Q[2]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0 ),
.Q(Q[11]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0 ),
.Q(rd_cmd_packed_wrap),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[32]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0 ),
.Q(rd_cmd_complete_wrap),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[33]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0 ),
.Q(rd_cmd_modified),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0 ),
.Q(Q[12]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ),
.Q(Q[3]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ),
.Q(Q[4]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ),
.Q(Q[5]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ),
.Q(Q[6]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ),
.Q(Q[7]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ),
.Q(cmd_step[0]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ),
.Q(cmd_step[1]),
.R(SR));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg
(.C(out),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.D(data_Exists_I),
.Q(\M_AXI_RDATA_I_reg[127] ),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT1 #(
.INIT(2'h1))
\USE_RTL_ADDR.addr_q[0]_i_1
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.O(\USE_RTL_ADDR.addr_q[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAA9A55555565))
\USE_RTL_ADDR.addr_q[1]_i_1
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I1(cmd_push_block),
.I2(sr_arvalid),
.I3(buffer_Full_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.O(\USE_RTL_ADDR.addr_q[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'hBF40F40B))
\USE_RTL_ADDR.addr_q[2]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.I1(valid_Write),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.O(\USE_RTL_ADDR.addr_q[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFF2000FFBA0045))
\USE_RTL_ADDR.addr_q[3]_i_1
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.I2(valid_Write),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.O(\USE_RTL_ADDR.addr_q[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h80808080800C8080))
\USE_RTL_ADDR.addr_q[4]_i_1
(.I0(data_Exists_I_i_2_n_0),
.I1(data_Exists_I),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.I3(buffer_Full_q),
.I4(sr_arvalid),
.I5(cmd_push_block),
.O(addr_q));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAA9))
\USE_RTL_ADDR.addr_q[4]_i_2
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I3(\USE_RTL_ADDR.addr_q[4]_i_3_n_0 ),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.O(\USE_RTL_ADDR.addr_q[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8888888888808888))
\USE_RTL_ADDR.addr_q[4]_i_3
(.I0(valid_Write),
.I1(\M_AXI_RDATA_I_reg[127] ),
.I2(first_word_reg),
.I3(first_word_reg_0),
.I4(use_wrap_buffer_reg),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0 ),
.O(\USE_RTL_ADDR.addr_q[4]_i_3_n_0 ));
FDRE \USE_RTL_ADDR.addr_q_reg[0]
(.C(out),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[0]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.R(SR));
FDRE \USE_RTL_ADDR.addr_q_reg[1]
(.C(out),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[1]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.R(SR));
FDRE \USE_RTL_ADDR.addr_q_reg[2]
(.C(out),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[2]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.R(SR));
FDRE \USE_RTL_ADDR.addr_q_reg[3]
(.C(out),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[3]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.R(SR));
FDRE \USE_RTL_ADDR.addr_q_reg[4]
(.C(out),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[4]_i_2_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.R(SR));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[0]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT3 #(
.INIT(8'h04))
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1
(.I0(buffer_Full_q),
.I1(sr_arvalid),
.I2(cmd_push_block),
.O(valid_Write));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[10]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[11]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[12]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[13]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[14]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[15]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[16]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[17]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[1]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[18]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[19]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[20]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[21]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[22]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[23]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[24]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[25]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[26]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[27]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[2]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[28]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[29]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[30]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[31]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][34]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[32]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[3]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[4]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[5]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[6]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[7]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[8]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(out),
.D(in[9]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT2 #(
.INIT(4'h8))
\USE_RTL_LENGTH.first_mi_word_q_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ),
.I1(mr_rvalid),
.O(\USE_RTL_LENGTH.length_counter_q_reg[7] ));
LUT6 #(
.INIT(64'h00000000FFFF0001))
\USE_RTL_LENGTH.first_mi_word_q_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0 ),
.I1(use_wrap_buffer),
.I2(\USE_RTL_LENGTH.length_counter_q_reg[1] ),
.I3(wrap_buffer_available),
.I4(\m_payload_i[130]_i_4_n_0 ),
.I5(\m_payload_i[130]_i_3_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ));
LUT6 #(
.INIT(64'h00FFFFFF00040000))
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1
(.I0(cmd_push_block),
.I1(sr_arvalid),
.I2(\USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.I4(data_Exists_I),
.I5(buffer_Full_q),
.O(\USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hFF7FFFFF))
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.O(\USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0 ));
FDRE \USE_RTL_VALID_WRITE.buffer_Full_q_reg
(.C(out),
.CE(1'b1),
.D(\USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0 ),
.Q(buffer_Full_q),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT4 #(
.INIT(16'h00D0))
cmd_push_block_i_1
(.I0(buffer_Full_q),
.I1(cmd_push_block),
.I2(sr_arvalid),
.I3(m_axi_arready),
.O(cmd_push_block0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[0]_i_1
(.I0(rd_cmd_mask[0]),
.I1(rd_cmd_next_word[0]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[3]_0 [0]),
.O(\current_word_1_reg[3] [0]));
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[1]_i_1
(.I0(rd_cmd_mask[1]),
.I1(rd_cmd_next_word[1]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[3]_0 [1]),
.O(\current_word_1_reg[3] [1]));
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[2]_i_1
(.I0(rd_cmd_mask[2]),
.I1(Q[8]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[3]_0 [2]),
.O(\current_word_1_reg[3] [2]));
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[3]_i_1
(.I0(rd_cmd_mask[3]),
.I1(Q[9]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[3]_0 [3]),
.O(\current_word_1_reg[3] [3]));
LUT6 #(
.INIT(64'hC4C4C4C4C4CFC4C4))
data_Exists_I_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0 ),
.I1(data_Exists_I),
.I2(data_Exists_I_i_2_n_0),
.I3(buffer_Full_q),
.I4(sr_arvalid),
.I5(cmd_push_block),
.O(next_Data_Exists));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
data_Exists_I_i_2
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.O(data_Exists_I_i_2_n_0));
FDRE data_Exists_I_reg
(.C(out),
.CE(1'b1),
.D(next_Data_Exists),
.Q(data_Exists_I),
.R(SR));
LUT3 #(
.INIT(8'h8A))
m_axi_arvalid_INST_0
(.I0(sr_arvalid),
.I1(cmd_push_block),
.I2(buffer_Full_q),
.O(m_axi_arvalid));
LUT6 #(
.INIT(64'h44444454FFFFFFFF))
\m_payload_i[130]_i_1
(.I0(\m_payload_i[130]_i_3_n_0 ),
.I1(\m_payload_i[130]_i_4_n_0 ),
.I2(wrap_buffer_available_reg),
.I3(use_wrap_buffer),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0 ),
.I5(mr_rvalid),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h7))
\m_payload_i[130]_i_3
(.I0(s_axi_rready),
.I1(\M_AXI_RDATA_I_reg[127] ),
.O(\m_payload_i[130]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0100FFFF))
\m_payload_i[130]_i_4
(.I0(\current_word_1_reg[3] [1]),
.I1(\current_word_1_reg[3] [2]),
.I2(\current_word_1_reg[3] [0]),
.I3(\m_payload_i[130]_i_6_n_0 ),
.I4(rd_cmd_modified),
.I5(Q[12]),
.O(\m_payload_i[130]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0001555155555555))
\m_payload_i[130]_i_6
(.I0(rd_cmd_complete_wrap),
.I1(\pre_next_word_1_reg[3]_0 [3]),
.I2(Q[12]),
.I3(first_word),
.I4(Q[9]),
.I5(rd_cmd_mask[3]),
.O(\m_payload_i[130]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0002AAA2AAA80008))
\pre_next_word_1[0]_i_1
(.I0(rd_cmd_mask[0]),
.I1(\pre_next_word_1_reg[3]_0 [0]),
.I2(Q[12]),
.I3(first_word),
.I4(rd_cmd_next_word[0]),
.I5(cmd_step[0]),
.O(D[0]));
LUT6 #(
.INIT(64'h8882228222288828))
\pre_next_word_1[1]_i_1
(.I0(rd_cmd_mask[1]),
.I1(cmd_step[1]),
.I2(rd_cmd_next_word[1]),
.I3(s_axi_rlast_INST_0_i_10_n_0),
.I4(\pre_next_word_1_reg[3]_0 [1]),
.I5(\pre_next_word_1[1]_i_2_n_0 ),
.O(D[1]));
LUT5 #(
.INIT(32'h888A8880))
\pre_next_word_1[1]_i_2
(.I0(cmd_step[0]),
.I1(rd_cmd_next_word[0]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[3]_0 [0]),
.O(\pre_next_word_1[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8882228222288828))
\pre_next_word_1[2]_i_1
(.I0(rd_cmd_mask[2]),
.I1(cmd_step[2]),
.I2(Q[8]),
.I3(s_axi_rlast_INST_0_i_10_n_0),
.I4(\pre_next_word_1_reg[3]_0 [2]),
.I5(\pre_next_word_1[3]_i_4_n_0 ),
.O(D[2]));
LUT5 #(
.INIT(32'hA880022A))
\pre_next_word_1[3]_i_2
(.I0(rd_cmd_mask[3]),
.I1(\pre_next_word_1_reg[2] ),
.I2(\pre_next_word_1[3]_i_4_n_0 ),
.I3(cmd_step[2]),
.I4(\pre_next_word_1_reg[3] ),
.O(D[3]));
LUT6 #(
.INIT(64'hEEEFEEEA888A8880))
\pre_next_word_1[3]_i_4
(.I0(cmd_step[1]),
.I1(rd_cmd_next_word[1]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[3]_0 [1]),
.I5(\pre_next_word_1[1]_i_2_n_0 ),
.O(\pre_next_word_1[3]_i_4_n_0 ));
LUT5 #(
.INIT(32'h00005457))
\s_axi_rdata[31]_INST_0_i_3
(.I0(Q[10]),
.I1(first_word),
.I2(Q[12]),
.I3(\current_word_1_reg[3]_1 [2]),
.I4(rd_cmd_offset[2]),
.O(\s_axi_rdata[31]_0 ));
LUT5 #(
.INIT(32'h00005457))
\s_axi_rdata[31]_INST_0_i_4
(.I0(Q[11]),
.I1(first_word),
.I2(Q[12]),
.I3(\current_word_1_reg[3]_1 [3]),
.I4(rd_cmd_offset[3]),
.O(\s_axi_rdata[31] ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h1))
s_axi_rlast_INST_0_i_10
(.I0(Q[12]),
.I1(first_word),
.O(s_axi_rlast_INST_0_i_10_n_0));
LUT6 #(
.INIT(64'hFFFF47B847B8FFFF))
s_axi_rlast_INST_0_i_2
(.I0(\current_word_1_reg[3]_1 [0]),
.I1(s_axi_rlast_INST_0_i_10_n_0),
.I2(rd_cmd_first_word[0]),
.I3(cmd_last_word[0]),
.I4(\current_word_1_reg[2] ),
.I5(cmd_last_word[2]),
.O(first_word_reg_0));
LUT6 #(
.INIT(64'hFFFF47B847B8FFFF))
s_axi_rlast_INST_0_i_3
(.I0(\current_word_1_reg[3]_1 [1]),
.I1(s_axi_rlast_INST_0_i_10_n_0),
.I2(rd_cmd_first_word[1]),
.I3(cmd_last_word[1]),
.I4(\current_word_1_reg[3]_0 ),
.I5(cmd_last_word[3]),
.O(first_word_reg));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hF8))
s_axi_rvalid_INST_0
(.I0(\M_AXI_RDATA_I_reg[127] ),
.I1(mr_rvalid),
.I2(use_wrap_buffer),
.O(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT4 #(
.INIT(16'hB000))
s_ready_i_i_2
(.I0(cmd_push_block),
.I1(buffer_Full_q),
.I2(m_axi_arready),
.I3(s_axi_aresetn),
.O(s_ready_i_reg));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module encoder(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
(in[9]==1'b1)?6'd9:
(in[10]==1'b1)?6'd10:
(in[11]==1'b1)?6'd11:
(in[12]==1'b1)?6'd12:
(in[13]==1'b1)?6'd13:
(in[14]==1'b1)?6'd14:
(in[15]==1'b1)?6'd15:
(in[16]==1'b1)?6'd16:
(in[17]==1'b1)?6'd17:
(in[18]==1'b1)?6'd18:
(in[19]==1'b1)?6'd19:
(in[20]==1'b1)?6'd20:
(in[21]==1'b1)?6'd21:
(in[22]==1'b1)?6'd22:
(in[23]==1'b1)?6'd23:
(in[24]==1'b1)?6'd24:
(in[25]==1'b1)?6'd25:
(in[26]==1'b1)?6'd26:
(in[27]==1'b1)?6'd27:
(in[28]==1'b1)?6'd28:
(in[29]==1'b1)?6'd29:
(in[30]==1'b1)?6'd30:
(in[31]==1'b1)?6'd31:
(in[32]==1'b1)?6'd32:
(in[33]==1'b1)?6'd33:
(in[34]==1'b1)?6'd34:
(in[35]==1'b1)?6'd35:
(in[36]==1'b1)?6'd36:
(in[37]==1'b1)?6'd37:
(in[38]==1'b1)?6'd38:
(in[39]==1'b1)?6'd39:
6'b000000;
endmodule |
module fifo_tx(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input rst;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(8),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(14),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(13),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule |
module soc_system_key_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule |
module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module ui_rd_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ORDERING = "NORM"
)
(/*AUTOARG*/
// Outputs
ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,
app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r,
// Inputs
rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end,
rd_data, ecc_multiple, rd_accepted
);
input rst;
input clk;
output wire ram_init_done_r;
output wire [3:0] ram_init_addr;
// rd_buf_indx points to the status and data storage rams for
// reading data out to the app.
reg [5:0] rd_buf_indx_r;
reg ram_init_done_r_lcl;
assign ram_init_done_r = ram_init_done_r_lcl;
wire app_rd_data_valid_ns;
wire single_data;
reg [5:0] rd_buf_indx_ns;
generate begin : rd_buf_indx
wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns;
// Loop through all status write addresses once after rst. Initializes
// the status and pointer RAMs.
wire ram_init_done_ns =
~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f));
always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns;
always @(/*AS*/rd_buf_indx_r or rst or single_data
or upd_rd_buf_indx) begin
rd_buf_indx_ns = rd_buf_indx_r;
if (rst) rd_buf_indx_ns = 6'b0;
else if (upd_rd_buf_indx) rd_buf_indx_ns =
rd_buf_indx_r + 6'h1 + single_data;
end
always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns;
end
endgenerate
assign ram_init_addr = rd_buf_indx_r[3:0];
input rd_data_en;
input [3:0] rd_data_addr;
input rd_data_offset;
input rd_data_end;
input [APP_DATA_WIDTH-1:0] rd_data;
output reg app_rd_data_valid;
output reg app_rd_data_end;
output reg [APP_DATA_WIDTH-1:0] app_rd_data;
input [3:0] ecc_multiple;
reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0;
output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err;
assign app_ecc_multiple_err = app_ecc_multiple_err_r;
input rd_accepted;
output wire rd_buf_full;
output wire [3:0] rd_data_buf_addr_r;
// Compute dimensions of read data buffer. Depending on width of
// DQ bus and DRAM CK
// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
// single write, single read, 6 bit wide mode.
localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6);
localparam REMAINDER = RD_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
if (ORDERING == "STRICT") begin : strict_mode
assign app_rd_data_valid_ns = 1'b0;
assign single_data = 1'b0;
assign rd_buf_full = 1'b0;
reg [3:0] rd_data_buf_addr_r_lcl;
wire [3:0] rd_data_buf_addr_ns =
rst
? 4'b0
: rd_data_buf_addr_r_lcl + {3'b0, rd_accepted};
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
assign rd_data_buf_addr_r = rd_data_buf_addr_ns;
// app_* signals required to be registered.
if (ECC == "OFF") begin : ecc_off
always @(/*AS*/rd_data) app_rd_data = rd_data;
always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en;
always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end;
end
else begin : ecc_on
always @(posedge clk) app_rd_data <= #TCQ rd_data;
always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en;
always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end;
always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple;
end
end
else begin : not_strict_mode
wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en;
wire [4:0] rd_buf_wr_addr = {rd_data_addr, rd_data_offset};
wire [1:0] rd_status;
// Instantiate status RAM. One bit for status and one for "end".
begin : status_ram
// Turns out read to write back status is a timing path. Update
// the status in the ram on the state following the read. Bypass
// the write data into the status read path.
wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl
? rd_buf_wr_addr
: rd_buf_indx_r[4:0];
reg [4:0] status_ram_wr_addr_r;
always @(posedge clk) status_ram_wr_addr_r <=
#TCQ status_ram_wr_addr_ns;
wire [1:0] wr_status;
// Not guaranteed to write second status bit. If it is written, always
// copy in the first status bit.
reg wr_status_r1;
always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0];
wire [1:0] status_ram_wr_data_ns =
ram_init_done_r_lcl
? {rd_data_end, ~(rd_data_offset
? wr_status_r1
: wr_status[0])}
: 2'b0;
reg [1:0] status_ram_wr_data_r;
always @(posedge clk) status_ram_wr_data_r <=
#TCQ status_ram_wr_data_ns;
reg rd_buf_we_r1;
always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we;
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_status),
.DOB(),
.DOC(wr_status),
.DOD(),
.DIA(status_ram_wr_data_r),
.DIB(2'b0),
.DIC(status_ram_wr_data_r),
.DID(status_ram_wr_data_r),
.ADDRA(rd_buf_indx_r[4:0]),
.ADDRB(5'b0),
.ADDRC(status_ram_wr_addr_ns),
.ADDRD(status_ram_wr_addr_r),
.WE(rd_buf_we_r1),
.WCLK(clk)
);
end // block: status_ram
wire [RAM_WIDTH-1:0] rd_buf_out_data;
begin : rd_buf
wire [RAM_WIDTH-1:0] rd_buf_in_data;
if (REMAINDER == 0)
if (ECC == "OFF")
assign rd_buf_in_data = rd_data;
else
assign rd_buf_in_data = {ecc_multiple, rd_data};
else
if (ECC == "OFF")
assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data};
else
assign rd_buf_in_data =
{{6-REMAINDER{1'b0}}, ecc_multiple, rd_data};
// Dedicated copy for driving distributed RAM.
(* equivalent_register_removal = "no" *)
reg [4:0] rd_buf_indx_copy_r;
always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0];
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_buf_out_data[((i*6)+4)+:2]),
.DOB(rd_buf_out_data[((i*6)+2)+:2]),
.DOC(rd_buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(rd_buf_in_data[((i*6)+4)+:2]),
.DIB(rd_buf_in_data[((i*6)+2)+:2]),
.DIC(rd_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_buf_indx_copy_r[4:0]),
.ADDRB(rd_buf_indx_copy_r[4:0]),
.ADDRC(rd_buf_indx_copy_r[4:0]),
.ADDRD(rd_buf_wr_addr),
.WE(rd_buf_we),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]);
wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]);
assign app_rd_data_valid_ns =
ram_init_done_r_lcl && (bypass || rd_data_rdy);
wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1];
always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns;
always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns;
assign single_data =
app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0];
wire [APP_DATA_WIDTH-1:0] app_rd_data_ns =
bypass
? rd_data
: rd_buf_out_data[APP_DATA_WIDTH-1:0];
always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns;
if (ECC != "OFF") begin : assign_app_ecc_multiple
wire [3:0] app_ecc_multiple_err_ns =
bypass
? ecc_multiple
: rd_buf_out_data[APP_DATA_WIDTH+:4];
always @(posedge clk) app_ecc_multiple_err_r <=
#TCQ app_ecc_multiple_err_ns;
end
//Added to fix timing. The signal app_rd_data_valid has
//a very high fanout. So making a dedicated copy for usage
//with the occ_cnt counter.
(* equivalent_register_removal = "no" *)
reg app_rd_data_valid_copy;
always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns;
// Keep track of how many entries in the queue hold data.
wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version
//of the signals in ordered to fix timing
reg [4:0] occ_cnt_r;
wire [4:0] occ_minus_one = occ_cnt_r - 5'b1;
wire [4:0] occ_plus_one = occ_cnt_r + 5'b1;
begin : occupied_counter
reg [4:0] occ_cnt_ns;
always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin
occ_cnt_ns = occ_cnt_r;
if (rst) occ_cnt_ns = 5'b0;
else case ({rd_accepted, free_rd_buf})
2'b01 : occ_cnt_ns = occ_minus_one;
2'b10 : occ_cnt_ns = occ_plus_one;
endcase // case ({wr_data_end, new_rd_data})
end
always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
assign rd_buf_full = occ_cnt_ns[4];
`ifdef MC_SVA
rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full));
rd_data_buffer_inc_dec_15: cover property (@(posedge clk)
(~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 5'hf)));
rd_data_underflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
rd_data_overflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
// Generate the data_buf_address written into the memory controller
// for reads. Increment with each accepted read, and rollover at 0xf.
reg [3:0] rd_data_buf_addr_r_lcl;
assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl;
begin : data_buf_addr
reg [3:0] rd_data_buf_addr_ns;
always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin
rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl;
if (rst) rd_data_buf_addr_ns = 4'b0;
else if (rd_accepted) rd_data_buf_addr_ns =
rd_data_buf_addr_r_lcl + 4'h1;
end
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
end // block: data_buf_addr
end // block: not_strict_mode
endgenerate
endmodule |
module sky130_fd_sc_ms__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__mux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule |
module NIOS_SYSTEMV3_RAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "NIOS_SYSTEMV3_RAM.hex";
output [ 31: 0] readdata;
input [ 10: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2048,
the_altsyncram.numwords_a = 2048,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 11;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule |
module sky130_fd_sc_hs__a22oi (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sirv_qspi_4cs(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
output io_tl_i_0_0,
output io_tl_r_0_a_ready,
input io_tl_r_0_a_valid,
input [2:0] io_tl_r_0_a_bits_opcode,
input [2:0] io_tl_r_0_a_bits_param,
input [2:0] io_tl_r_0_a_bits_size,
input [4:0] io_tl_r_0_a_bits_source,
input [28:0] io_tl_r_0_a_bits_address,
input [3:0] io_tl_r_0_a_bits_mask,
input [31:0] io_tl_r_0_a_bits_data,
input io_tl_r_0_b_ready,
output io_tl_r_0_b_valid,
output [2:0] io_tl_r_0_b_bits_opcode,
output [1:0] io_tl_r_0_b_bits_param,
output [2:0] io_tl_r_0_b_bits_size,
output [4:0] io_tl_r_0_b_bits_source,
output [28:0] io_tl_r_0_b_bits_address,
output [3:0] io_tl_r_0_b_bits_mask,
output [31:0] io_tl_r_0_b_bits_data,
output io_tl_r_0_c_ready,
input io_tl_r_0_c_valid,
input [2:0] io_tl_r_0_c_bits_opcode,
input [2:0] io_tl_r_0_c_bits_param,
input [2:0] io_tl_r_0_c_bits_size,
input [4:0] io_tl_r_0_c_bits_source,
input [28:0] io_tl_r_0_c_bits_address,
input [31:0] io_tl_r_0_c_bits_data,
input io_tl_r_0_c_bits_error,
input io_tl_r_0_d_ready,
output io_tl_r_0_d_valid,
output [2:0] io_tl_r_0_d_bits_opcode,
output [1:0] io_tl_r_0_d_bits_param,
output [2:0] io_tl_r_0_d_bits_size,
output [4:0] io_tl_r_0_d_bits_source,
output io_tl_r_0_d_bits_sink,
output [1:0] io_tl_r_0_d_bits_addr_lo,
output [31:0] io_tl_r_0_d_bits_data,
output io_tl_r_0_d_bits_error,
output io_tl_r_0_e_ready,
input io_tl_r_0_e_valid,
input io_tl_r_0_e_bits_sink
);
wire [1:0] T_955_fmt_proto;
wire T_955_fmt_endian;
wire T_955_fmt_iodir;
wire [3:0] T_955_fmt_len;
wire [11:0] T_955_sck_div;
wire T_955_sck_pol;
wire T_955_sck_pha;
wire [1:0] T_955_cs_id;
wire T_955_cs_dflt_0;
wire T_955_cs_dflt_1;
wire T_955_cs_dflt_2;
wire T_955_cs_dflt_3;
wire [1:0] T_955_cs_mode;
wire [7:0] T_955_dla_cssck;
wire [7:0] T_955_dla_sckcs;
wire [7:0] T_955_dla_intercs;
wire [7:0] T_955_dla_interxfr;
wire [3:0] T_955_wm_tx;
wire [3:0] T_955_wm_rx;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_245;
reg ctrl_fmt_endian;
reg [31:0] GEN_246;
reg ctrl_fmt_iodir;
reg [31:0] GEN_247;
reg [3:0] ctrl_fmt_len;
reg [31:0] GEN_248;
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_249;
reg ctrl_sck_pol;
reg [31:0] GEN_250;
reg ctrl_sck_pha;
reg [31:0] GEN_251;
reg [1:0] ctrl_cs_id;
reg [31:0] GEN_252;
reg ctrl_cs_dflt_0;
reg [31:0] GEN_253;
reg ctrl_cs_dflt_1;
reg [31:0] GEN_254;
reg ctrl_cs_dflt_2;
reg [31:0] GEN_255;
reg ctrl_cs_dflt_3;
reg [31:0] GEN_256;
reg [1:0] ctrl_cs_mode;
reg [31:0] GEN_257;
reg [7:0] ctrl_dla_cssck;
reg [31:0] GEN_258;
reg [7:0] ctrl_dla_sckcs;
reg [31:0] GEN_259;
reg [7:0] ctrl_dla_intercs;
reg [31:0] GEN_260;
reg [7:0] ctrl_dla_interxfr;
reg [31:0] GEN_261;
reg [3:0] ctrl_wm_tx;
reg [31:0] GEN_262;
reg [3:0] ctrl_wm_rx;
reg [31:0] GEN_263;
wire fifo_clock;
wire fifo_reset;
wire [1:0] fifo_io_ctrl_fmt_proto;
wire fifo_io_ctrl_fmt_endian;
wire fifo_io_ctrl_fmt_iodir;
wire [3:0] fifo_io_ctrl_fmt_len;
wire [1:0] fifo_io_ctrl_cs_mode;
wire [3:0] fifo_io_ctrl_wm_tx;
wire [3:0] fifo_io_ctrl_wm_rx;
wire fifo_io_link_tx_ready;
wire fifo_io_link_tx_valid;
wire [7:0] fifo_io_link_tx_bits;
wire fifo_io_link_rx_valid;
wire [7:0] fifo_io_link_rx_bits;
wire [7:0] fifo_io_link_cnt;
wire [1:0] fifo_io_link_fmt_proto;
wire fifo_io_link_fmt_endian;
wire fifo_io_link_fmt_iodir;
wire fifo_io_link_cs_set;
wire fifo_io_link_cs_clear;
wire fifo_io_link_cs_hold;
wire fifo_io_link_active;
wire fifo_io_link_lock;
wire fifo_io_tx_ready;
wire fifo_io_tx_valid;
wire [7:0] fifo_io_tx_bits;
wire fifo_io_rx_ready;
wire fifo_io_rx_valid;
wire [7:0] fifo_io_rx_bits;
wire fifo_io_ip_txwm;
wire fifo_io_ip_rxwm;
wire mac_clock;
wire mac_reset;
wire mac_io_port_sck;
wire mac_io_port_dq_0_i;
wire mac_io_port_dq_0_o;
wire mac_io_port_dq_0_oe;
wire mac_io_port_dq_1_i;
wire mac_io_port_dq_1_o;
wire mac_io_port_dq_1_oe;
wire mac_io_port_dq_2_i;
wire mac_io_port_dq_2_o;
wire mac_io_port_dq_2_oe;
wire mac_io_port_dq_3_i;
wire mac_io_port_dq_3_o;
wire mac_io_port_dq_3_oe;
wire mac_io_port_cs_0;
wire mac_io_port_cs_1;
wire mac_io_port_cs_2;
wire mac_io_port_cs_3;
wire [11:0] mac_io_ctrl_sck_div;
wire mac_io_ctrl_sck_pol;
wire mac_io_ctrl_sck_pha;
wire [7:0] mac_io_ctrl_dla_cssck;
wire [7:0] mac_io_ctrl_dla_sckcs;
wire [7:0] mac_io_ctrl_dla_intercs;
wire [7:0] mac_io_ctrl_dla_interxfr;
wire [1:0] mac_io_ctrl_cs_id;
wire mac_io_ctrl_cs_dflt_0;
wire mac_io_ctrl_cs_dflt_1;
wire mac_io_ctrl_cs_dflt_2;
wire mac_io_ctrl_cs_dflt_3;
wire mac_io_link_tx_ready;
wire mac_io_link_tx_valid;
wire [7:0] mac_io_link_tx_bits;
wire mac_io_link_rx_valid;
wire [7:0] mac_io_link_rx_bits;
wire [7:0] mac_io_link_cnt;
wire [1:0] mac_io_link_fmt_proto;
wire mac_io_link_fmt_endian;
wire mac_io_link_fmt_iodir;
wire mac_io_link_cs_set;
wire mac_io_link_cs_clear;
wire mac_io_link_cs_hold;
wire mac_io_link_active;
wire T_1024_txwm;
wire T_1024_rxwm;
wire [1:0] T_1028;
wire T_1029;
wire T_1030;
reg ie_txwm;
reg [31:0] GEN_264;
reg ie_rxwm;
reg [31:0] GEN_265;
wire T_1033;
wire T_1034;
wire T_1035;
wire T_1039;
wire T_1042;
wire T_1066_ready;
wire T_1066_valid;
wire T_1066_bits_read;
wire [9:0] T_1066_bits_index;
wire [31:0] T_1066_bits_data;
wire [3:0] T_1066_bits_mask;
wire [9:0] T_1066_bits_extra;
wire T_1083;
wire [26:0] T_1084;
wire [1:0] T_1085;
wire [6:0] T_1086;
wire [9:0] T_1087;
wire T_1105_ready;
wire T_1105_valid;
wire T_1105_bits_read;
wire [31:0] T_1105_bits_data;
wire [9:0] T_1105_bits_extra;
wire T_1141_ready;
wire T_1141_valid;
wire T_1141_bits_read;
wire [9:0] T_1141_bits_index;
wire [31:0] T_1141_bits_data;
wire [3:0] T_1141_bits_mask;
wire [9:0] T_1141_bits_extra;
wire [9:0] T_1226;
wire T_1228;
wire [9:0] T_1234;
wire [9:0] T_1235;
wire T_1237;
wire [9:0] T_1243;
wire [9:0] T_1244;
wire T_1246;
wire [9:0] T_1252;
wire [9:0] T_1253;
wire T_1255;
wire [9:0] T_1261;
wire [9:0] T_1262;
wire T_1264;
wire [9:0] T_1270;
wire [9:0] T_1271;
wire T_1273;
wire [9:0] T_1279;
wire [9:0] T_1280;
wire T_1282;
wire [9:0] T_1288;
wire [9:0] T_1289;
wire T_1291;
wire [9:0] T_1297;
wire [9:0] T_1298;
wire T_1300;
wire [9:0] T_1306;
wire [9:0] T_1307;
wire T_1309;
wire [9:0] T_1315;
wire [9:0] T_1316;
wire T_1318;
wire [9:0] T_1324;
wire [9:0] T_1325;
wire T_1327;
wire [9:0] T_1333;
wire [9:0] T_1334;
wire T_1336;
wire [9:0] T_1342;
wire [9:0] T_1343;
wire T_1345;
wire T_1353_0;
wire T_1353_1;
wire T_1353_2;
wire T_1353_3;
wire T_1353_4;
wire T_1353_5;
wire T_1353_6;
wire T_1353_7;
wire T_1353_8;
wire T_1353_9;
wire T_1353_10;
wire T_1353_11;
wire T_1353_12;
wire T_1353_13;
wire T_1353_14;
wire T_1353_15;
wire T_1353_16;
wire T_1353_17;
wire T_1353_18;
wire T_1353_19;
wire T_1353_20;
wire T_1353_21;
wire T_1353_22;
wire T_1353_23;
wire T_1353_24;
wire T_1353_25;
wire T_1353_26;
wire T_1353_27;
wire T_1353_28;
wire T_1358_0;
wire T_1358_1;
wire T_1358_2;
wire T_1358_3;
wire T_1358_4;
wire T_1358_5;
wire T_1358_6;
wire T_1358_7;
wire T_1358_8;
wire T_1358_9;
wire T_1358_10;
wire T_1358_11;
wire T_1358_12;
wire T_1358_13;
wire T_1358_14;
wire T_1358_15;
wire T_1358_16;
wire T_1358_17;
wire T_1358_18;
wire T_1358_19;
wire T_1358_20;
wire T_1358_21;
wire T_1358_22;
wire T_1358_23;
wire T_1358_24;
wire T_1358_25;
wire T_1358_26;
wire T_1358_27;
wire T_1358_28;
wire T_1363_0;
wire T_1363_1;
wire T_1363_2;
wire T_1363_3;
wire T_1363_4;
wire T_1363_5;
wire T_1363_6;
wire T_1363_7;
wire T_1363_8;
wire T_1363_9;
wire T_1363_10;
wire T_1363_11;
wire T_1363_12;
wire T_1363_13;
wire T_1363_14;
wire T_1363_15;
wire T_1363_16;
wire T_1363_17;
wire T_1363_18;
wire T_1363_19;
wire T_1363_20;
wire T_1363_21;
wire T_1363_22;
wire T_1363_23;
wire T_1363_24;
wire T_1363_25;
wire T_1363_26;
wire T_1363_27;
wire T_1363_28;
wire T_1368_0;
wire T_1368_1;
wire T_1368_2;
wire T_1368_3;
wire T_1368_4;
wire T_1368_5;
wire T_1368_6;
wire T_1368_7;
wire T_1368_8;
wire T_1368_9;
wire T_1368_10;
wire T_1368_11;
wire T_1368_12;
wire T_1368_13;
wire T_1368_14;
wire T_1368_15;
wire T_1368_16;
wire T_1368_17;
wire T_1368_18;
wire T_1368_19;
wire T_1368_20;
wire T_1368_21;
wire T_1368_22;
wire T_1368_23;
wire T_1368_24;
wire T_1368_25;
wire T_1368_26;
wire T_1368_27;
wire T_1368_28;
wire T_1373_0;
wire T_1373_1;
wire T_1373_2;
wire T_1373_3;
wire T_1373_4;
wire T_1373_5;
wire T_1373_6;
wire T_1373_7;
wire T_1373_8;
wire T_1373_9;
wire T_1373_10;
wire T_1373_11;
wire T_1373_12;
wire T_1373_13;
wire T_1373_14;
wire T_1373_15;
wire T_1373_16;
wire T_1373_17;
wire T_1373_18;
wire T_1373_19;
wire T_1373_20;
wire T_1373_21;
wire T_1373_22;
wire T_1373_23;
wire T_1373_24;
wire T_1373_25;
wire T_1373_26;
wire T_1373_27;
wire T_1373_28;
wire T_1378_0;
wire T_1378_1;
wire T_1378_2;
wire T_1378_3;
wire T_1378_4;
wire T_1378_5;
wire T_1378_6;
wire T_1378_7;
wire T_1378_8;
wire T_1378_9;
wire T_1378_10;
wire T_1378_11;
wire T_1378_12;
wire T_1378_13;
wire T_1378_14;
wire T_1378_15;
wire T_1378_16;
wire T_1378_17;
wire T_1378_18;
wire T_1378_19;
wire T_1378_20;
wire T_1378_21;
wire T_1378_22;
wire T_1378_23;
wire T_1378_24;
wire T_1378_25;
wire T_1378_26;
wire T_1378_27;
wire T_1378_28;
wire T_1383_0;
wire T_1383_1;
wire T_1383_2;
wire T_1383_3;
wire T_1383_4;
wire T_1383_5;
wire T_1383_6;
wire T_1383_7;
wire T_1383_8;
wire T_1383_9;
wire T_1383_10;
wire T_1383_11;
wire T_1383_12;
wire T_1383_13;
wire T_1383_14;
wire T_1383_15;
wire T_1383_16;
wire T_1383_17;
wire T_1383_18;
wire T_1383_19;
wire T_1383_20;
wire T_1383_21;
wire T_1383_22;
wire T_1383_23;
wire T_1383_24;
wire T_1383_25;
wire T_1383_26;
wire T_1383_27;
wire T_1383_28;
wire T_1388_0;
wire T_1388_1;
wire T_1388_2;
wire T_1388_3;
wire T_1388_4;
wire T_1388_5;
wire T_1388_6;
wire T_1388_7;
wire T_1388_8;
wire T_1388_9;
wire T_1388_10;
wire T_1388_11;
wire T_1388_12;
wire T_1388_13;
wire T_1388_14;
wire T_1388_15;
wire T_1388_16;
wire T_1388_17;
wire T_1388_18;
wire T_1388_19;
wire T_1388_20;
wire T_1388_21;
wire T_1388_22;
wire T_1388_23;
wire T_1388_24;
wire T_1388_25;
wire T_1388_26;
wire T_1388_27;
wire T_1388_28;
wire T_1550;
wire T_1551;
wire T_1552;
wire T_1553;
wire [7:0] T_1557;
wire [7:0] T_1561;
wire [7:0] T_1565;
wire [7:0] T_1569;
wire [15:0] T_1570;
wire [15:0] T_1571;
wire [31:0] T_1572;
wire [11:0] T_1596;
wire [11:0] T_1600;
wire T_1602;
wire T_1615;
wire [11:0] T_1616;
wire [11:0] GEN_6;
wire T_1636;
wire T_1640;
wire T_1642;
wire T_1655;
wire T_1656;
wire GEN_7;
wire T_1676;
wire T_1680;
wire T_1682;
wire T_1695;
wire T_1696;
wire GEN_8;
wire [1:0] GEN_213;
wire [1:0] T_1711;
wire [1:0] GEN_214;
wire [1:0] T_1715;
wire T_1716;
wire T_1720;
wire T_1722;
wire T_1735;
wire T_1736;
wire GEN_9;
wire [2:0] GEN_215;
wire [2:0] T_1751;
wire [2:0] GEN_216;
wire [2:0] T_1755;
wire T_1756;
wire T_1760;
wire T_1762;
wire T_1775;
wire T_1776;
wire GEN_10;
wire [3:0] GEN_217;
wire [3:0] T_1791;
wire [3:0] GEN_218;
wire [3:0] T_1795;
wire [7:0] T_1796;
wire T_1798;
wire [7:0] T_1800;
wire T_1802;
wire T_1815;
wire [7:0] T_1816;
wire [7:0] GEN_11;
wire [7:0] T_1836;
wire [7:0] T_1840;
wire T_1842;
wire T_1855;
wire [7:0] T_1856;
wire [7:0] GEN_12;
wire [23:0] GEN_219;
wire [23:0] T_1871;
wire [23:0] GEN_220;
wire [23:0] T_1875;
wire [3:0] T_1876;
wire [3:0] T_1880;
wire T_1882;
wire T_1895;
wire [3:0] T_1896;
wire [3:0] GEN_13;
wire T_1951;
wire [1:0] GEN_221;
wire [1:0] T_1991;
wire [1:0] GEN_222;
wire [1:0] T_1995;
wire T_2015;
wire GEN_14;
wire T_2055;
wire GEN_15;
wire [1:0] GEN_223;
wire [1:0] T_2071;
wire [1:0] GEN_224;
wire [1:0] T_2075;
wire [1:0] T_2076;
wire [1:0] T_2080;
wire T_2082;
wire T_2095;
wire [1:0] T_2096;
wire [1:0] GEN_16;
wire T_2135;
wire GEN_17;
wire T_2175;
wire GEN_18;
wire [1:0] GEN_225;
wire [1:0] T_2191;
wire [1:0] GEN_226;
wire [1:0] T_2195;
wire T_2215;
wire [3:0] GEN_19;
wire T_2255;
wire [31:0] GEN_227;
wire [31:0] T_2351;
wire T_2375;
wire [1:0] GEN_20;
wire T_2415;
wire GEN_21;
wire [2:0] GEN_228;
wire [2:0] T_2431;
wire [2:0] GEN_229;
wire [2:0] T_2435;
wire T_2455;
wire GEN_22;
wire [3:0] GEN_230;
wire [3:0] T_2471;
wire [3:0] GEN_231;
wire [3:0] T_2475;
wire [3:0] T_2476;
wire [3:0] T_2480;
wire T_2482;
wire T_2495;
wire [3:0] T_2496;
wire [3:0] GEN_23;
wire [19:0] GEN_232;
wire [19:0] T_2511;
wire [19:0] GEN_233;
wire [19:0] T_2515;
wire T_2535;
wire [7:0] GEN_24;
wire T_2575;
wire [7:0] GEN_25;
wire [23:0] GEN_234;
wire [23:0] T_2591;
wire [23:0] GEN_235;
wire [23:0] T_2595;
wire T_2611;
wire [7:0] T_2631;
wire [30:0] T_2675;
wire [31:0] GEN_236;
wire [31:0] T_2711;
wire [31:0] GEN_237;
wire [31:0] T_2715;
wire T_2735;
wire [1:0] GEN_26;
wire T_2757;
wire T_2759;
wire T_2761;
wire T_2762;
wire T_2764;
wire T_2772;
wire T_2774;
wire T_2776;
wire T_2777;
wire T_2778;
wire T_2779;
wire T_2781;
wire T_2783;
wire T_2785;
wire T_2796;
wire T_2797;
wire T_2799;
wire T_2801;
wire T_2802;
wire T_2804;
wire T_2818;
wire T_2819;
wire T_2820;
wire T_2821;
wire T_2823;
wire T_2828;
wire T_2829;
wire T_2830;
wire T_2832;
wire T_2834;
wire T_2835;
wire T_2836;
wire T_2838;
wire T_2840;
wire T_2842;
wire T_2844;
wire T_2846;
wire T_2866;
wire T_2867;
wire T_2869;
wire T_2871;
wire T_2872;
wire T_2874;
wire T_2916_0;
wire T_2916_1;
wire T_2916_2;
wire T_2916_3;
wire T_2916_4;
wire T_2916_5;
wire T_2916_6;
wire T_2916_7;
wire T_2916_8;
wire T_2916_9;
wire T_2916_10;
wire T_2916_11;
wire T_2916_12;
wire T_2916_13;
wire T_2916_14;
wire T_2916_15;
wire T_2916_16;
wire T_2916_17;
wire T_2916_18;
wire T_2916_19;
wire T_2916_20;
wire T_2916_21;
wire T_2916_22;
wire T_2916_23;
wire T_2916_24;
wire T_2916_25;
wire T_2916_26;
wire T_2916_27;
wire T_2916_28;
wire T_2916_29;
wire T_2916_30;
wire T_2916_31;
wire T_2954;
wire T_2957;
wire T_2959;
wire T_2969;
wire T_2972;
wire T_2973;
wire T_2974;
wire T_2976;
wire T_2980;
wire T_2992;
wire T_2994;
wire T_2997;
wire T_2999;
wire T_3014;
wire T_3015;
wire T_3016;
wire T_3018;
wire T_3024;
wire T_3025;
wire T_3027;
wire T_3030;
wire T_3031;
wire T_3033;
wire T_3037;
wire T_3041;
wire T_3062;
wire T_3064;
wire T_3067;
wire T_3069;
wire T_3111_0;
wire T_3111_1;
wire T_3111_2;
wire T_3111_3;
wire T_3111_4;
wire T_3111_5;
wire T_3111_6;
wire T_3111_7;
wire T_3111_8;
wire T_3111_9;
wire T_3111_10;
wire T_3111_11;
wire T_3111_12;
wire T_3111_13;
wire T_3111_14;
wire T_3111_15;
wire T_3111_16;
wire T_3111_17;
wire T_3111_18;
wire T_3111_19;
wire T_3111_20;
wire T_3111_21;
wire T_3111_22;
wire T_3111_23;
wire T_3111_24;
wire T_3111_25;
wire T_3111_26;
wire T_3111_27;
wire T_3111_28;
wire T_3111_29;
wire T_3111_30;
wire T_3111_31;
wire T_3149;
wire T_3152;
wire T_3154;
wire T_3164;
wire T_3167;
wire T_3168;
wire T_3169;
wire T_3171;
wire T_3175;
wire T_3187;
wire T_3189;
wire T_3192;
wire T_3194;
wire T_3209;
wire T_3210;
wire T_3211;
wire T_3213;
wire T_3219;
wire T_3220;
wire T_3222;
wire T_3225;
wire T_3226;
wire T_3228;
wire T_3232;
wire T_3236;
wire T_3257;
wire T_3259;
wire T_3262;
wire T_3264;
wire T_3306_0;
wire T_3306_1;
wire T_3306_2;
wire T_3306_3;
wire T_3306_4;
wire T_3306_5;
wire T_3306_6;
wire T_3306_7;
wire T_3306_8;
wire T_3306_9;
wire T_3306_10;
wire T_3306_11;
wire T_3306_12;
wire T_3306_13;
wire T_3306_14;
wire T_3306_15;
wire T_3306_16;
wire T_3306_17;
wire T_3306_18;
wire T_3306_19;
wire T_3306_20;
wire T_3306_21;
wire T_3306_22;
wire T_3306_23;
wire T_3306_24;
wire T_3306_25;
wire T_3306_26;
wire T_3306_27;
wire T_3306_28;
wire T_3306_29;
wire T_3306_30;
wire T_3306_31;
wire T_3344;
wire T_3347;
wire T_3349;
wire T_3359;
wire T_3362;
wire T_3363;
wire T_3364;
wire T_3366;
wire T_3370;
wire T_3382;
wire T_3384;
wire T_3387;
wire T_3389;
wire T_3404;
wire T_3405;
wire T_3406;
wire T_3408;
wire T_3414;
wire T_3415;
wire T_3417;
wire T_3420;
wire T_3421;
wire T_3423;
wire T_3427;
wire T_3431;
wire T_3452;
wire T_3454;
wire T_3457;
wire T_3459;
wire T_3501_0;
wire T_3501_1;
wire T_3501_2;
wire T_3501_3;
wire T_3501_4;
wire T_3501_5;
wire T_3501_6;
wire T_3501_7;
wire T_3501_8;
wire T_3501_9;
wire T_3501_10;
wire T_3501_11;
wire T_3501_12;
wire T_3501_13;
wire T_3501_14;
wire T_3501_15;
wire T_3501_16;
wire T_3501_17;
wire T_3501_18;
wire T_3501_19;
wire T_3501_20;
wire T_3501_21;
wire T_3501_22;
wire T_3501_23;
wire T_3501_24;
wire T_3501_25;
wire T_3501_26;
wire T_3501_27;
wire T_3501_28;
wire T_3501_29;
wire T_3501_30;
wire T_3501_31;
wire T_3536;
wire T_3537;
wire T_3538;
wire T_3539;
wire T_3540;
wire [1:0] T_3546;
wire [1:0] T_3547;
wire [2:0] T_3548;
wire [4:0] T_3549;
wire GEN_0;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire GEN_49;
wire GEN_50;
wire GEN_51;
wire GEN_52;
wire GEN_53;
wire GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire GEN_1;
wire GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire GEN_62;
wire GEN_63;
wire GEN_64;
wire GEN_65;
wire GEN_66;
wire GEN_67;
wire GEN_68;
wire GEN_69;
wire GEN_70;
wire GEN_71;
wire GEN_72;
wire GEN_73;
wire GEN_74;
wire GEN_75;
wire GEN_76;
wire GEN_77;
wire GEN_78;
wire GEN_79;
wire GEN_80;
wire GEN_81;
wire GEN_82;
wire GEN_83;
wire GEN_84;
wire GEN_85;
wire GEN_86;
wire GEN_87;
wire GEN_88;
wire T_3566;
wire GEN_2;
wire GEN_89;
wire GEN_90;
wire GEN_91;
wire GEN_92;
wire GEN_93;
wire GEN_94;
wire GEN_95;
wire GEN_96;
wire GEN_97;
wire GEN_98;
wire GEN_99;
wire GEN_100;
wire GEN_101;
wire GEN_102;
wire GEN_103;
wire GEN_104;
wire GEN_105;
wire GEN_106;
wire GEN_107;
wire GEN_108;
wire GEN_109;
wire GEN_110;
wire GEN_111;
wire GEN_112;
wire GEN_113;
wire GEN_114;
wire GEN_115;
wire GEN_116;
wire GEN_117;
wire GEN_118;
wire GEN_119;
wire GEN_3;
wire GEN_120;
wire GEN_121;
wire GEN_122;
wire GEN_123;
wire GEN_124;
wire GEN_125;
wire GEN_126;
wire GEN_127;
wire GEN_128;
wire GEN_129;
wire GEN_130;
wire GEN_131;
wire GEN_132;
wire GEN_133;
wire GEN_134;
wire GEN_135;
wire GEN_136;
wire GEN_137;
wire GEN_138;
wire GEN_139;
wire GEN_140;
wire GEN_141;
wire GEN_142;
wire GEN_143;
wire GEN_144;
wire GEN_145;
wire GEN_146;
wire GEN_147;
wire GEN_148;
wire GEN_149;
wire GEN_150;
wire T_3569;
wire T_3570;
wire T_3571;
wire T_3572;
wire T_3573;
wire [31:0] T_3575;
wire [1:0] T_3576;
wire [3:0] T_3578;
wire [1:0] T_3579;
wire [1:0] T_3580;
wire [3:0] T_3581;
wire [7:0] T_3582;
wire [1:0] T_3584;
wire [3:0] T_3585;
wire [7:0] T_3589;
wire [15:0] T_3590;
wire [1:0] T_3591;
wire [1:0] T_3592;
wire [3:0] T_3593;
wire [1:0] T_3594;
wire [3:0] T_3596;
wire [7:0] T_3597;
wire [1:0] T_3601;
wire [3:0] T_3603;
wire [7:0] T_3604;
wire [15:0] T_3605;
wire [31:0] T_3606;
wire [31:0] T_3607;
wire T_3642;
wire T_3643;
wire T_3644;
wire T_3645;
wire T_3648;
wire T_3649;
wire T_3651;
wire T_3652;
wire T_3653;
wire T_3655;
wire T_3659;
wire T_3661;
wire T_3664;
wire T_3665;
wire T_3671;
wire T_3675;
wire T_3681;
wire T_3724;
wire T_3725;
wire T_3731;
wire T_3735;
wire T_3741;
wire T_3744;
wire T_3745;
wire T_3751;
wire T_3755;
wire T_3761;
wire T_3764;
wire T_3765;
wire T_3771;
wire T_3775;
wire T_3781;
wire T_3844;
wire T_3845;
wire T_3851;
wire T_3855;
wire T_3861;
wire T_3864;
wire T_3865;
wire T_3871;
wire T_3875;
wire T_3881;
wire T_3964;
wire T_3965;
wire T_3971;
wire T_3975;
wire T_3981;
wire T_4004;
wire T_4005;
wire T_4011;
wire T_4015;
wire T_4021;
wire T_4024;
wire T_4025;
wire T_4031;
wire T_4035;
wire T_4041;
wire T_4044;
wire T_4045;
wire T_4051;
wire T_4055;
wire T_4061;
wire T_4064;
wire T_4065;
wire T_4071;
wire T_4075;
wire T_4081;
wire T_4204;
wire T_4205;
wire T_4211;
wire T_4215;
wire T_4221;
wire T_4224;
wire T_4225;
wire T_4231;
wire T_4235;
wire T_4241;
wire T_4286;
wire T_4287;
wire T_4288;
wire T_4290;
wire T_4291;
wire T_4292;
wire T_4294;
wire T_4295;
wire T_4296;
wire T_4298;
wire T_4299;
wire T_4300;
wire T_4304;
wire T_4308;
wire T_4312;
wire T_4316;
wire T_4319;
wire T_4320;
wire T_4323;
wire T_4324;
wire T_4327;
wire T_4328;
wire T_4331;
wire T_4332;
wire T_4334;
wire T_4335;
wire T_4336;
wire T_4338;
wire T_4339;
wire T_4340;
wire T_4342;
wire T_4343;
wire T_4344;
wire T_4346;
wire T_4347;
wire T_4348;
wire T_4350;
wire T_4352;
wire T_4354;
wire T_4356;
wire T_4358;
wire T_4360;
wire T_4362;
wire T_4364;
wire T_4370;
wire T_4372;
wire T_4374;
wire T_4376;
wire T_4378;
wire T_4380;
wire T_4382;
wire T_4384;
wire T_4386;
wire T_4388;
wire T_4390;
wire T_4392;
wire T_4394;
wire T_4396;
wire T_4398;
wire T_4400;
wire T_4406;
wire T_4408;
wire T_4410;
wire T_4412;
wire T_4414;
wire T_4416;
wire T_4418;
wire T_4420;
wire T_4426;
wire T_4427;
wire T_4429;
wire T_4430;
wire T_4432;
wire T_4433;
wire T_4435;
wire T_4436;
wire T_4439;
wire T_4442;
wire T_4445;
wire T_4448;
wire T_4450;
wire T_4451;
wire T_4453;
wire T_4454;
wire T_4456;
wire T_4457;
wire T_4459;
wire T_4460;
wire T_4462;
wire T_4463;
wire T_4464;
wire T_4466;
wire T_4467;
wire T_4468;
wire T_4470;
wire T_4471;
wire T_4472;
wire T_4474;
wire T_4475;
wire T_4476;
wire T_4480;
wire T_4484;
wire T_4488;
wire T_4492;
wire T_4495;
wire T_4496;
wire T_4499;
wire T_4500;
wire T_4503;
wire T_4504;
wire T_4507;
wire T_4508;
wire T_4510;
wire T_4511;
wire T_4512;
wire T_4514;
wire T_4515;
wire T_4516;
wire T_4518;
wire T_4519;
wire T_4520;
wire T_4522;
wire T_4523;
wire T_4524;
wire T_4526;
wire T_4528;
wire T_4530;
wire T_4532;
wire T_4534;
wire T_4536;
wire T_4538;
wire T_4540;
wire T_4542;
wire T_4543;
wire T_4545;
wire T_4546;
wire T_4548;
wire T_4549;
wire T_4551;
wire T_4552;
wire T_4555;
wire T_4558;
wire T_4561;
wire T_4564;
wire T_4566;
wire T_4567;
wire T_4569;
wire T_4570;
wire T_4572;
wire T_4573;
wire T_4575;
wire T_4576;
wire T_4617_0;
wire T_4617_1;
wire T_4617_2;
wire T_4617_3;
wire T_4617_4;
wire T_4617_5;
wire T_4617_6;
wire T_4617_7;
wire T_4617_8;
wire T_4617_9;
wire T_4617_10;
wire T_4617_11;
wire T_4617_12;
wire T_4617_13;
wire T_4617_14;
wire T_4617_15;
wire T_4617_16;
wire T_4617_17;
wire T_4617_18;
wire T_4617_19;
wire T_4617_20;
wire T_4617_21;
wire T_4617_22;
wire T_4617_23;
wire T_4617_24;
wire T_4617_25;
wire T_4617_26;
wire T_4617_27;
wire T_4617_28;
wire T_4617_29;
wire T_4617_30;
wire T_4617_31;
wire [31:0] T_4688_0;
wire [31:0] T_4688_1;
wire [31:0] T_4688_2;
wire [31:0] T_4688_3;
wire [31:0] T_4688_4;
wire [31:0] T_4688_5;
wire [31:0] T_4688_6;
wire [31:0] T_4688_7;
wire [31:0] T_4688_8;
wire [31:0] T_4688_9;
wire [31:0] T_4688_10;
wire [31:0] T_4688_11;
wire [31:0] T_4688_12;
wire [31:0] T_4688_13;
wire [31:0] T_4688_14;
wire [31:0] T_4688_15;
wire [31:0] T_4688_16;
wire [31:0] T_4688_17;
wire [31:0] T_4688_18;
wire [31:0] T_4688_19;
wire [31:0] T_4688_20;
wire [31:0] T_4688_21;
wire [31:0] T_4688_22;
wire [31:0] T_4688_23;
wire [31:0] T_4688_24;
wire [31:0] T_4688_25;
wire [31:0] T_4688_26;
wire [31:0] T_4688_27;
wire [31:0] T_4688_28;
wire [31:0] T_4688_29;
wire [31:0] T_4688_30;
wire [31:0] T_4688_31;
wire GEN_4;
wire GEN_151;
wire GEN_152;
wire GEN_153;
wire GEN_154;
wire GEN_155;
wire GEN_156;
wire GEN_157;
wire GEN_158;
wire GEN_159;
wire GEN_160;
wire GEN_161;
wire GEN_162;
wire GEN_163;
wire GEN_164;
wire GEN_165;
wire GEN_166;
wire GEN_167;
wire GEN_168;
wire GEN_169;
wire GEN_170;
wire GEN_171;
wire GEN_172;
wire GEN_173;
wire GEN_174;
wire GEN_175;
wire GEN_176;
wire GEN_177;
wire GEN_178;
wire GEN_179;
wire GEN_180;
wire GEN_181;
wire [31:0] GEN_5;
wire [31:0] GEN_182;
wire [31:0] GEN_183;
wire [31:0] GEN_184;
wire [31:0] GEN_185;
wire [31:0] GEN_186;
wire [31:0] GEN_187;
wire [31:0] GEN_188;
wire [31:0] GEN_189;
wire [31:0] GEN_190;
wire [31:0] GEN_191;
wire [31:0] GEN_192;
wire [31:0] GEN_193;
wire [31:0] GEN_194;
wire [31:0] GEN_195;
wire [31:0] GEN_196;
wire [31:0] GEN_197;
wire [31:0] GEN_198;
wire [31:0] GEN_199;
wire [31:0] GEN_200;
wire [31:0] GEN_201;
wire [31:0] GEN_202;
wire [31:0] GEN_203;
wire [31:0] GEN_204;
wire [31:0] GEN_205;
wire [31:0] GEN_206;
wire [31:0] GEN_207;
wire [31:0] GEN_208;
wire [31:0] GEN_209;
wire [31:0] GEN_210;
wire [31:0] GEN_211;
wire [31:0] GEN_212;
wire [31:0] T_4725;
wire [1:0] T_4726;
wire [4:0] T_4728;
wire [2:0] T_4729;
wire [2:0] T_4740_opcode;
wire [1:0] T_4740_param;
wire [2:0] T_4740_size;
wire [4:0] T_4740_source;
wire T_4740_sink;
wire [1:0] T_4740_addr_lo;
wire [31:0] T_4740_data;
wire T_4740_error;
wire [2:0] GEN_238 = 3'b0;
reg [31:0] GEN_266;
wire [1:0] GEN_239 = 2'b0;
reg [31:0] GEN_267;
wire [2:0] GEN_240 = 3'b0;
reg [31:0] GEN_268;
wire [4:0] GEN_241 = 5'b0;
reg [31:0] GEN_269;
wire [28:0] GEN_242 = 29'b0;
reg [31:0] GEN_270;
wire [3:0] GEN_243 = 4'b0;
reg [31:0] GEN_271;
wire [31:0] GEN_244 = 32'b0;
reg [31:0] GEN_272;
sirv_qspi_fifo fifo (
.clock(fifo_clock),
.reset(fifo_reset),
.io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir),
.io_ctrl_fmt_len(fifo_io_ctrl_fmt_len),
.io_ctrl_cs_mode(fifo_io_ctrl_cs_mode),
.io_ctrl_wm_tx(fifo_io_ctrl_wm_tx),
.io_ctrl_wm_rx(fifo_io_ctrl_wm_rx),
.io_link_tx_ready(fifo_io_link_tx_ready),
.io_link_tx_valid(fifo_io_link_tx_valid),
.io_link_tx_bits(fifo_io_link_tx_bits),
.io_link_rx_valid(fifo_io_link_rx_valid),
.io_link_rx_bits(fifo_io_link_rx_bits),
.io_link_cnt(fifo_io_link_cnt),
.io_link_fmt_proto(fifo_io_link_fmt_proto),
.io_link_fmt_endian(fifo_io_link_fmt_endian),
.io_link_fmt_iodir(fifo_io_link_fmt_iodir),
.io_link_cs_set(fifo_io_link_cs_set),
.io_link_cs_clear(fifo_io_link_cs_clear),
.io_link_cs_hold(fifo_io_link_cs_hold),
.io_link_active(fifo_io_link_active),
.io_link_lock(fifo_io_link_lock),
.io_tx_ready(fifo_io_tx_ready),
.io_tx_valid(fifo_io_tx_valid),
.io_tx_bits(fifo_io_tx_bits),
.io_rx_ready(fifo_io_rx_ready),
.io_rx_valid(fifo_io_rx_valid),
.io_rx_bits(fifo_io_rx_bits),
.io_ip_txwm(fifo_io_ip_txwm),
.io_ip_rxwm(fifo_io_ip_rxwm)
);
sirv_qspi_media_1 mac (
.clock(mac_clock),
.reset(mac_reset),
.io_port_sck(mac_io_port_sck),
.io_port_dq_0_i(mac_io_port_dq_0_i),
.io_port_dq_0_o(mac_io_port_dq_0_o),
.io_port_dq_0_oe(mac_io_port_dq_0_oe),
.io_port_dq_1_i(mac_io_port_dq_1_i),
.io_port_dq_1_o(mac_io_port_dq_1_o),
.io_port_dq_1_oe(mac_io_port_dq_1_oe),
.io_port_dq_2_i(mac_io_port_dq_2_i),
.io_port_dq_2_o(mac_io_port_dq_2_o),
.io_port_dq_2_oe(mac_io_port_dq_2_oe),
.io_port_dq_3_i(mac_io_port_dq_3_i),
.io_port_dq_3_o(mac_io_port_dq_3_o),
.io_port_dq_3_oe(mac_io_port_dq_3_oe),
.io_port_cs_0(mac_io_port_cs_0),
.io_port_cs_1(mac_io_port_cs_1),
.io_port_cs_2(mac_io_port_cs_2),
.io_port_cs_3(mac_io_port_cs_3),
.io_ctrl_sck_div(mac_io_ctrl_sck_div),
.io_ctrl_sck_pol(mac_io_ctrl_sck_pol),
.io_ctrl_sck_pha(mac_io_ctrl_sck_pha),
.io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck),
.io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs),
.io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs),
.io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr),
.io_ctrl_cs_id(mac_io_ctrl_cs_id),
.io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0),
.io_ctrl_cs_dflt_1(mac_io_ctrl_cs_dflt_1),
.io_ctrl_cs_dflt_2(mac_io_ctrl_cs_dflt_2),
.io_ctrl_cs_dflt_3(mac_io_ctrl_cs_dflt_3),
.io_link_tx_ready(mac_io_link_tx_ready),
.io_link_tx_valid(mac_io_link_tx_valid),
.io_link_tx_bits(mac_io_link_tx_bits),
.io_link_rx_valid(mac_io_link_rx_valid),
.io_link_rx_bits(mac_io_link_rx_bits),
.io_link_cnt(mac_io_link_cnt),
.io_link_fmt_proto(mac_io_link_fmt_proto),
.io_link_fmt_endian(mac_io_link_fmt_endian),
.io_link_fmt_iodir(mac_io_link_fmt_iodir),
.io_link_cs_set(mac_io_link_cs_set),
.io_link_cs_clear(mac_io_link_cs_clear),
.io_link_cs_hold(mac_io_link_cs_hold),
.io_link_active(mac_io_link_active)
);
assign io_port_sck = mac_io_port_sck;
assign io_port_dq_0_o = mac_io_port_dq_0_o;
assign io_port_dq_0_oe = mac_io_port_dq_0_oe;
assign io_port_dq_1_o = mac_io_port_dq_1_o;
assign io_port_dq_1_oe = mac_io_port_dq_1_oe;
assign io_port_dq_2_o = mac_io_port_dq_2_o;
assign io_port_dq_2_oe = mac_io_port_dq_2_oe;
assign io_port_dq_3_o = mac_io_port_dq_3_o;
assign io_port_dq_3_oe = mac_io_port_dq_3_oe;
assign io_port_cs_0 = mac_io_port_cs_0;
assign io_port_cs_1 = mac_io_port_cs_1;
assign io_port_cs_2 = mac_io_port_cs_2;
assign io_port_cs_3 = mac_io_port_cs_3;
assign io_tl_i_0_0 = T_1035;
assign io_tl_r_0_a_ready = T_1066_ready;
assign io_tl_r_0_b_valid = 1'h0;
assign io_tl_r_0_b_bits_opcode = GEN_238;
assign io_tl_r_0_b_bits_param = GEN_239;
assign io_tl_r_0_b_bits_size = GEN_240;
assign io_tl_r_0_b_bits_source = GEN_241;
assign io_tl_r_0_b_bits_address = GEN_242;
assign io_tl_r_0_b_bits_mask = GEN_243;
assign io_tl_r_0_b_bits_data = GEN_244;
assign io_tl_r_0_c_ready = 1'h1;
assign io_tl_r_0_d_valid = T_1105_valid;
assign io_tl_r_0_d_bits_opcode = {{2'd0}, T_1105_bits_read};
assign io_tl_r_0_d_bits_param = T_4740_param;
assign io_tl_r_0_d_bits_size = T_4740_size;
assign io_tl_r_0_d_bits_source = T_4740_source;
assign io_tl_r_0_d_bits_sink = T_4740_sink;
assign io_tl_r_0_d_bits_addr_lo = T_4740_addr_lo;
assign io_tl_r_0_d_bits_data = T_1105_bits_data;
assign io_tl_r_0_d_bits_error = T_4740_error;
assign io_tl_r_0_e_ready = 1'h1;
assign T_955_fmt_proto = 2'h0;
assign T_955_fmt_endian = 1'h0;
assign T_955_fmt_iodir = 1'h0;
assign T_955_fmt_len = 4'h8;
assign T_955_sck_div = 12'h3;
assign T_955_sck_pol = 1'h0;
assign T_955_sck_pha = 1'h0;
assign T_955_cs_id = 2'h0;
assign T_955_cs_dflt_0 = 1'h1;
assign T_955_cs_dflt_1 = 1'h1;
assign T_955_cs_dflt_2 = 1'h1;
assign T_955_cs_dflt_3 = 1'h1;
assign T_955_cs_mode = 2'h0;
assign T_955_dla_cssck = 8'h1;
assign T_955_dla_sckcs = 8'h1;
assign T_955_dla_intercs = 8'h1;
assign T_955_dla_interxfr = 8'h0;
assign T_955_wm_tx = 4'h0;
assign T_955_wm_rx = 4'h0;
assign fifo_clock = clock;
assign fifo_reset = reset;
assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto;
assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian;
assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir;
assign fifo_io_ctrl_fmt_len = ctrl_fmt_len;
assign fifo_io_ctrl_cs_mode = ctrl_cs_mode;
assign fifo_io_ctrl_wm_tx = ctrl_wm_tx;
assign fifo_io_ctrl_wm_rx = ctrl_wm_rx;
assign fifo_io_link_tx_ready = mac_io_link_tx_ready;
assign fifo_io_link_rx_valid = mac_io_link_rx_valid;
assign fifo_io_link_rx_bits = mac_io_link_rx_bits;
assign fifo_io_link_active = mac_io_link_active;
assign fifo_io_tx_valid = T_2255;
assign fifo_io_tx_bits = T_1816;
assign fifo_io_rx_ready = T_2611;
assign mac_clock = clock;
assign mac_reset = reset;
assign mac_io_port_dq_0_i = io_port_dq_0_i;
assign mac_io_port_dq_1_i = io_port_dq_1_i;
assign mac_io_port_dq_2_i = io_port_dq_2_i;
assign mac_io_port_dq_3_i = io_port_dq_3_i;
assign mac_io_ctrl_sck_div = ctrl_sck_div;
assign mac_io_ctrl_sck_pol = ctrl_sck_pol;
assign mac_io_ctrl_sck_pha = ctrl_sck_pha;
assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck;
assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs;
assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs;
assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr;
assign mac_io_ctrl_cs_id = ctrl_cs_id;
assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0;
assign mac_io_ctrl_cs_dflt_1 = ctrl_cs_dflt_1;
assign mac_io_ctrl_cs_dflt_2 = ctrl_cs_dflt_2;
assign mac_io_ctrl_cs_dflt_3 = ctrl_cs_dflt_3;
assign mac_io_link_tx_valid = fifo_io_link_tx_valid;
assign mac_io_link_tx_bits = fifo_io_link_tx_bits;
assign mac_io_link_cnt = fifo_io_link_cnt;
assign mac_io_link_fmt_proto = fifo_io_link_fmt_proto;
assign mac_io_link_fmt_endian = fifo_io_link_fmt_endian;
assign mac_io_link_fmt_iodir = fifo_io_link_fmt_iodir;
assign mac_io_link_cs_set = fifo_io_link_cs_set;
assign mac_io_link_cs_clear = fifo_io_link_cs_clear;
assign mac_io_link_cs_hold = fifo_io_link_cs_hold;
assign T_1024_txwm = T_1030;
assign T_1024_rxwm = T_1029;
assign T_1028 = 2'h0;
assign T_1029 = T_1028[0];
assign T_1030 = T_1028[1];
assign T_1033 = fifo_io_ip_txwm & ie_txwm;
assign T_1034 = fifo_io_ip_rxwm & ie_rxwm;
assign T_1035 = T_1033 | T_1034;
assign T_1039 = fifo_io_tx_ready == 1'h0;
assign T_1042 = fifo_io_rx_valid == 1'h0;
assign T_1066_ready = T_3570;
assign T_1066_valid = io_tl_r_0_a_valid;
assign T_1066_bits_read = T_1083;
assign T_1066_bits_index = T_1084[9:0];
assign T_1066_bits_data = io_tl_r_0_a_bits_data;
assign T_1066_bits_mask = io_tl_r_0_a_bits_mask;
assign T_1066_bits_extra = T_1087;
assign T_1083 = io_tl_r_0_a_bits_opcode == 3'h4;
assign T_1084 = io_tl_r_0_a_bits_address[28:2];
assign T_1085 = io_tl_r_0_a_bits_address[1:0];
assign T_1086 = {T_1085,io_tl_r_0_a_bits_source};
assign T_1087 = {T_1086,io_tl_r_0_a_bits_size};
assign T_1105_ready = io_tl_r_0_d_ready;
assign T_1105_valid = T_3573;
assign T_1105_bits_read = T_1141_bits_read;
assign T_1105_bits_data = T_4725;
assign T_1105_bits_extra = T_1141_bits_extra;
assign T_1141_ready = T_3572;
assign T_1141_valid = T_3571;
assign T_1141_bits_read = T_1066_bits_read;
assign T_1141_bits_index = T_1066_bits_index;
assign T_1141_bits_data = T_1066_bits_data;
assign T_1141_bits_mask = T_1066_bits_mask;
assign T_1141_bits_extra = T_1066_bits_extra;
assign T_1226 = T_1141_bits_index & 10'h3e0;
assign T_1228 = T_1226 == 10'h0;
assign T_1234 = T_1141_bits_index ^ 10'h5;
assign T_1235 = T_1234 & 10'h3e0;
assign T_1237 = T_1235 == 10'h0;
assign T_1243 = T_1141_bits_index ^ 10'ha;
assign T_1244 = T_1243 & 10'h3e0;
assign T_1246 = T_1244 == 10'h0;
assign T_1252 = T_1141_bits_index ^ 10'h14;
assign T_1253 = T_1252 & 10'h3e0;
assign T_1255 = T_1253 == 10'h0;
assign T_1261 = T_1141_bits_index ^ 10'h1d;
assign T_1262 = T_1261 & 10'h3e0;
assign T_1264 = T_1262 == 10'h0;
assign T_1270 = T_1141_bits_index ^ 10'h1;
assign T_1271 = T_1270 & 10'h3e0;
assign T_1273 = T_1271 == 10'h0;
assign T_1279 = T_1141_bits_index ^ 10'h6;
assign T_1280 = T_1279 & 10'h3e0;
assign T_1282 = T_1280 == 10'h0;
assign T_1288 = T_1141_bits_index ^ 10'h1c;
assign T_1289 = T_1288 & 10'h3e0;
assign T_1291 = T_1289 == 10'h0;
assign T_1297 = T_1141_bits_index ^ 10'h15;
assign T_1298 = T_1297 & 10'h3e0;
assign T_1300 = T_1298 == 10'h0;
assign T_1306 = T_1141_bits_index ^ 10'h12;
assign T_1307 = T_1306 & 10'h3e0;
assign T_1309 = T_1307 == 10'h0;
assign T_1315 = T_1141_bits_index ^ 10'h10;
assign T_1316 = T_1315 & 10'h3e0;
assign T_1318 = T_1316 == 10'h0;
assign T_1324 = T_1141_bits_index ^ 10'hb;
assign T_1325 = T_1324 & 10'h3e0;
assign T_1327 = T_1325 == 10'h0;
assign T_1333 = T_1141_bits_index ^ 10'h13;
assign T_1334 = T_1333 & 10'h3e0;
assign T_1336 = T_1334 == 10'h0;
assign T_1342 = T_1141_bits_index ^ 10'h4;
assign T_1343 = T_1342 & 10'h3e0;
assign T_1345 = T_1343 == 10'h0;
assign T_1353_0 = T_3645;
assign T_1353_1 = T_4288;
assign T_1353_2 = T_4304;
assign T_1353_3 = T_4320;
assign T_1353_4 = T_4336;
assign T_1353_5 = T_4350;
assign T_1353_6 = T_4358;
assign T_1353_7 = T_4045;
assign T_1353_8 = T_4370;
assign T_1353_9 = T_4378;
assign T_1353_10 = T_4386;
assign T_1353_11 = T_4394;
assign T_1353_12 = T_3765;
assign T_1353_13 = T_4406;
assign T_1353_14 = T_4414;
assign T_1353_15 = T_4065;
assign T_1353_16 = T_4427;
assign T_1353_17 = T_4439;
assign T_1353_18 = T_4451;
assign T_1353_19 = T_4464;
assign T_1353_20 = T_4480;
assign T_1353_21 = T_4496;
assign T_1353_22 = T_4512;
assign T_1353_23 = T_4526;
assign T_1353_24 = T_4534;
assign T_1353_25 = T_4543;
assign T_1353_26 = T_4555;
assign T_1353_27 = T_4567;
assign T_1353_28 = T_3725;
assign T_1358_0 = T_3651;
assign T_1358_1 = T_4292;
assign T_1358_2 = T_4308;
assign T_1358_3 = T_4324;
assign T_1358_4 = T_4340;
assign T_1358_5 = T_4352;
assign T_1358_6 = T_4360;
assign T_1358_7 = T_4051;
assign T_1358_8 = T_4372;
assign T_1358_9 = T_4380;
assign T_1358_10 = T_4388;
assign T_1358_11 = T_4396;
assign T_1358_12 = T_3771;
assign T_1358_13 = T_4408;
assign T_1358_14 = T_4416;
assign T_1358_15 = T_4071;
assign T_1358_16 = T_4430;
assign T_1358_17 = T_4442;
assign T_1358_18 = T_4454;
assign T_1358_19 = T_4468;
assign T_1358_20 = T_4484;
assign T_1358_21 = T_4500;
assign T_1358_22 = T_4516;
assign T_1358_23 = T_4528;
assign T_1358_24 = T_4536;
assign T_1358_25 = T_4546;
assign T_1358_26 = T_4558;
assign T_1358_27 = T_4570;
assign T_1358_28 = T_3731;
assign T_1363_0 = 1'h1;
assign T_1363_1 = 1'h1;
assign T_1363_2 = 1'h1;
assign T_1363_3 = 1'h1;
assign T_1363_4 = 1'h1;
assign T_1363_5 = 1'h1;
assign T_1363_6 = 1'h1;
assign T_1363_7 = 1'h1;
assign T_1363_8 = 1'h1;
assign T_1363_9 = 1'h1;
assign T_1363_10 = 1'h1;
assign T_1363_11 = 1'h1;
assign T_1363_12 = 1'h1;
assign T_1363_13 = 1'h1;
assign T_1363_14 = 1'h1;
assign T_1363_15 = 1'h1;
assign T_1363_16 = 1'h1;
assign T_1363_17 = 1'h1;
assign T_1363_18 = 1'h1;
assign T_1363_19 = 1'h1;
assign T_1363_20 = 1'h1;
assign T_1363_21 = 1'h1;
assign T_1363_22 = 1'h1;
assign T_1363_23 = 1'h1;
assign T_1363_24 = 1'h1;
assign T_1363_25 = 1'h1;
assign T_1363_26 = 1'h1;
assign T_1363_27 = 1'h1;
assign T_1363_28 = 1'h1;
assign T_1368_0 = 1'h1;
assign T_1368_1 = 1'h1;
assign T_1368_2 = 1'h1;
assign T_1368_3 = 1'h1;
assign T_1368_4 = 1'h1;
assign T_1368_5 = 1'h1;
assign T_1368_6 = 1'h1;
assign T_1368_7 = 1'h1;
assign T_1368_8 = 1'h1;
assign T_1368_9 = 1'h1;
assign T_1368_10 = 1'h1;
assign T_1368_11 = 1'h1;
assign T_1368_12 = 1'h1;
assign T_1368_13 = 1'h1;
assign T_1368_14 = 1'h1;
assign T_1368_15 = 1'h1;
assign T_1368_16 = 1'h1;
assign T_1368_17 = 1'h1;
assign T_1368_18 = 1'h1;
assign T_1368_19 = 1'h1;
assign T_1368_20 = 1'h1;
assign T_1368_21 = 1'h1;
assign T_1368_22 = 1'h1;
assign T_1368_23 = 1'h1;
assign T_1368_24 = 1'h1;
assign T_1368_25 = 1'h1;
assign T_1368_26 = 1'h1;
assign T_1368_27 = 1'h1;
assign T_1368_28 = 1'h1;
assign T_1373_0 = 1'h1;
assign T_1373_1 = 1'h1;
assign T_1373_2 = 1'h1;
assign T_1373_3 = 1'h1;
assign T_1373_4 = 1'h1;
assign T_1373_5 = 1'h1;
assign T_1373_6 = 1'h1;
assign T_1373_7 = 1'h1;
assign T_1373_8 = 1'h1;
assign T_1373_9 = 1'h1;
assign T_1373_10 = 1'h1;
assign T_1373_11 = 1'h1;
assign T_1373_12 = 1'h1;
assign T_1373_13 = 1'h1;
assign T_1373_14 = 1'h1;
assign T_1373_15 = 1'h1;
assign T_1373_16 = 1'h1;
assign T_1373_17 = 1'h1;
assign T_1373_18 = 1'h1;
assign T_1373_19 = 1'h1;
assign T_1373_20 = 1'h1;
assign T_1373_21 = 1'h1;
assign T_1373_22 = 1'h1;
assign T_1373_23 = 1'h1;
assign T_1373_24 = 1'h1;
assign T_1373_25 = 1'h1;
assign T_1373_26 = 1'h1;
assign T_1373_27 = 1'h1;
assign T_1373_28 = 1'h1;
assign T_1378_0 = 1'h1;
assign T_1378_1 = 1'h1;
assign T_1378_2 = 1'h1;
assign T_1378_3 = 1'h1;
assign T_1378_4 = 1'h1;
assign T_1378_5 = 1'h1;
assign T_1378_6 = 1'h1;
assign T_1378_7 = 1'h1;
assign T_1378_8 = 1'h1;
assign T_1378_9 = 1'h1;
assign T_1378_10 = 1'h1;
assign T_1378_11 = 1'h1;
assign T_1378_12 = 1'h1;
assign T_1378_13 = 1'h1;
assign T_1378_14 = 1'h1;
assign T_1378_15 = 1'h1;
assign T_1378_16 = 1'h1;
assign T_1378_17 = 1'h1;
assign T_1378_18 = 1'h1;
assign T_1378_19 = 1'h1;
assign T_1378_20 = 1'h1;
assign T_1378_21 = 1'h1;
assign T_1378_22 = 1'h1;
assign T_1378_23 = 1'h1;
assign T_1378_24 = 1'h1;
assign T_1378_25 = 1'h1;
assign T_1378_26 = 1'h1;
assign T_1378_27 = 1'h1;
assign T_1378_28 = 1'h1;
assign T_1383_0 = T_3655;
assign T_1383_1 = T_4296;
assign T_1383_2 = T_4312;
assign T_1383_3 = T_4328;
assign T_1383_4 = T_4344;
assign T_1383_5 = T_4354;
assign T_1383_6 = T_4362;
assign T_1383_7 = T_4055;
assign T_1383_8 = T_4374;
assign T_1383_9 = T_4382;
assign T_1383_10 = T_4390;
assign T_1383_11 = T_4398;
assign T_1383_12 = T_3775;
assign T_1383_13 = T_4410;
assign T_1383_14 = T_4418;
assign T_1383_15 = T_4075;
assign T_1383_16 = T_4433;
assign T_1383_17 = T_4445;
assign T_1383_18 = T_4457;
assign T_1383_19 = T_4472;
assign T_1383_20 = T_4488;
assign T_1383_21 = T_4504;
assign T_1383_22 = T_4520;
assign T_1383_23 = T_4530;
assign T_1383_24 = T_4538;
assign T_1383_25 = T_4549;
assign T_1383_26 = T_4561;
assign T_1383_27 = T_4573;
assign T_1383_28 = T_3735;
assign T_1388_0 = T_3661;
assign T_1388_1 = T_4300;
assign T_1388_2 = T_4316;
assign T_1388_3 = T_4332;
assign T_1388_4 = T_4348;
assign T_1388_5 = T_4356;
assign T_1388_6 = T_4364;
assign T_1388_7 = T_4061;
assign T_1388_8 = T_4376;
assign T_1388_9 = T_4384;
assign T_1388_10 = T_4392;
assign T_1388_11 = T_4400;
assign T_1388_12 = T_3781;
assign T_1388_13 = T_4412;
assign T_1388_14 = T_4420;
assign T_1388_15 = T_4081;
assign T_1388_16 = T_4436;
assign T_1388_17 = T_4448;
assign T_1388_18 = T_4460;
assign T_1388_19 = T_4476;
assign T_1388_20 = T_4492;
assign T_1388_21 = T_4508;
assign T_1388_22 = T_4524;
assign T_1388_23 = T_4532;
assign T_1388_24 = T_4540;
assign T_1388_25 = T_4552;
assign T_1388_26 = T_4564;
assign T_1388_27 = T_4576;
assign T_1388_28 = T_3741;
assign T_1550 = T_1141_bits_mask[0];
assign T_1551 = T_1141_bits_mask[1];
assign T_1552 = T_1141_bits_mask[2];
assign T_1553 = T_1141_bits_mask[3];
assign T_1557 = T_1550 ? 8'hff : 8'h0;
assign T_1561 = T_1551 ? 8'hff : 8'h0;
assign T_1565 = T_1552 ? 8'hff : 8'h0;
assign T_1569 = T_1553 ? 8'hff : 8'h0;
assign T_1570 = {T_1561,T_1557};
assign T_1571 = {T_1569,T_1565};
assign T_1572 = {T_1571,T_1570};
assign T_1596 = T_1572[11:0];
assign T_1600 = ~ T_1596;
assign T_1602 = T_1600 == 12'h0;
assign T_1615 = T_1388_0 & T_1602;
assign T_1616 = T_1141_bits_data[11:0];
assign GEN_6 = T_1615 ? T_1616 : ctrl_sck_div;
assign T_1636 = T_1572[0];
assign T_1640 = ~ T_1636;
assign T_1642 = T_1640 == 1'h0;
assign T_1655 = T_1388_1 & T_1642;
assign T_1656 = T_1141_bits_data[0];
assign GEN_7 = T_1655 ? T_1656 : ctrl_cs_dflt_0;
assign T_1676 = T_1572[1];
assign T_1680 = ~ T_1676;
assign T_1682 = T_1680 == 1'h0;
assign T_1695 = T_1388_2 & T_1682;
assign T_1696 = T_1141_bits_data[1];
assign GEN_8 = T_1695 ? T_1696 : ctrl_cs_dflt_1;
assign GEN_213 = {{1'd0}, ctrl_cs_dflt_1};
assign T_1711 = GEN_213 << 1;
assign GEN_214 = {{1'd0}, ctrl_cs_dflt_0};
assign T_1715 = GEN_214 | T_1711;
assign T_1716 = T_1572[2];
assign T_1720 = ~ T_1716;
assign T_1722 = T_1720 == 1'h0;
assign T_1735 = T_1388_3 & T_1722;
assign T_1736 = T_1141_bits_data[2];
assign GEN_9 = T_1735 ? T_1736 : ctrl_cs_dflt_2;
assign GEN_215 = {{2'd0}, ctrl_cs_dflt_2};
assign T_1751 = GEN_215 << 2;
assign GEN_216 = {{1'd0}, T_1715};
assign T_1755 = GEN_216 | T_1751;
assign T_1756 = T_1572[3];
assign T_1760 = ~ T_1756;
assign T_1762 = T_1760 == 1'h0;
assign T_1775 = T_1388_4 & T_1762;
assign T_1776 = T_1141_bits_data[3];
assign GEN_10 = T_1775 ? T_1776 : ctrl_cs_dflt_3;
assign GEN_217 = {{3'd0}, ctrl_cs_dflt_3};
assign T_1791 = GEN_217 << 3;
assign GEN_218 = {{1'd0}, T_1755};
assign T_1795 = GEN_218 | T_1791;
assign T_1796 = T_1572[7:0];
assign T_1798 = T_1796 != 8'h0;
assign T_1800 = ~ T_1796;
assign T_1802 = T_1800 == 8'h0;
assign T_1815 = T_1388_5 & T_1802;
assign T_1816 = T_1141_bits_data[7:0];
assign GEN_11 = T_1815 ? T_1816 : ctrl_dla_cssck;
assign T_1836 = T_1572[23:16];
assign T_1840 = ~ T_1836;
assign T_1842 = T_1840 == 8'h0;
assign T_1855 = T_1388_6 & T_1842;
assign T_1856 = T_1141_bits_data[23:16];
assign GEN_12 = T_1855 ? T_1856 : ctrl_dla_sckcs;
assign GEN_219 = {{16'd0}, ctrl_dla_sckcs};
assign T_1871 = GEN_219 << 16;
assign GEN_220 = {{16'd0}, ctrl_dla_cssck};
assign T_1875 = GEN_220 | T_1871;
assign T_1876 = T_1572[3:0];
assign T_1880 = ~ T_1876;
assign T_1882 = T_1880 == 4'h0;
assign T_1895 = T_1388_7 & T_1882;
assign T_1896 = T_1141_bits_data[3:0];
assign GEN_13 = T_1895 ? T_1896 : ctrl_wm_tx;
assign T_1951 = fifo_io_ip_txwm;
assign GEN_221 = {{1'd0}, fifo_io_ip_rxwm};
assign T_1991 = GEN_221 << 1;
assign GEN_222 = {{1'd0}, T_1951};
assign T_1995 = GEN_222 | T_1991;
assign T_2015 = T_1388_10 & T_1642;
assign GEN_14 = T_2015 ? T_1656 : ctrl_sck_pha;
assign T_2055 = T_1388_11 & T_1682;
assign GEN_15 = T_2055 ? T_1696 : ctrl_sck_pol;
assign GEN_223 = {{1'd0}, ctrl_sck_pol};
assign T_2071 = GEN_223 << 1;
assign GEN_224 = {{1'd0}, ctrl_sck_pha};
assign T_2075 = GEN_224 | T_2071;
assign T_2076 = T_1572[1:0];
assign T_2080 = ~ T_2076;
assign T_2082 = T_2080 == 2'h0;
assign T_2095 = T_1388_12 & T_2082;
assign T_2096 = T_1141_bits_data[1:0];
assign GEN_16 = T_2095 ? T_2096 : ctrl_cs_mode;
assign T_2135 = T_1388_13 & T_1642;
assign GEN_17 = T_2135 ? T_1656 : ie_txwm;
assign T_2175 = T_1388_14 & T_1682;
assign GEN_18 = T_2175 ? T_1696 : ie_rxwm;
assign GEN_225 = {{1'd0}, ie_rxwm};
assign T_2191 = GEN_225 << 1;
assign GEN_226 = {{1'd0}, ie_txwm};
assign T_2195 = GEN_226 | T_2191;
assign T_2215 = T_1388_15 & T_1882;
assign GEN_19 = T_2215 ? T_1896 : ctrl_wm_rx;
assign T_2255 = T_1388_16 & T_1802;
assign GEN_227 = {{31'd0}, T_1039};
assign T_2351 = GEN_227 << 31;
assign T_2375 = T_1388_19 & T_2082;
assign GEN_20 = T_2375 ? T_2096 : ctrl_fmt_proto;
assign T_2415 = T_1388_20 & T_1722;
assign GEN_21 = T_2415 ? T_1736 : ctrl_fmt_endian;
assign GEN_228 = {{2'd0}, ctrl_fmt_endian};
assign T_2431 = GEN_228 << 2;
assign GEN_229 = {{1'd0}, ctrl_fmt_proto};
assign T_2435 = GEN_229 | T_2431;
assign T_2455 = T_1388_21 & T_1762;
assign GEN_22 = T_2455 ? T_1776 : ctrl_fmt_iodir;
assign GEN_230 = {{3'd0}, ctrl_fmt_iodir};
assign T_2471 = GEN_230 << 3;
assign GEN_231 = {{1'd0}, T_2435};
assign T_2475 = GEN_231 | T_2471;
assign T_2476 = T_1572[19:16];
assign T_2480 = ~ T_2476;
assign T_2482 = T_2480 == 4'h0;
assign T_2495 = T_1388_22 & T_2482;
assign T_2496 = T_1141_bits_data[19:16];
assign GEN_23 = T_2495 ? T_2496 : ctrl_fmt_len;
assign GEN_232 = {{16'd0}, ctrl_fmt_len};
assign T_2511 = GEN_232 << 16;
assign GEN_233 = {{16'd0}, T_2475};
assign T_2515 = GEN_233 | T_2511;
assign T_2535 = T_1388_23 & T_1802;
assign GEN_24 = T_2535 ? T_1816 : ctrl_dla_intercs;
assign T_2575 = T_1388_24 & T_1842;
assign GEN_25 = T_2575 ? T_1856 : ctrl_dla_interxfr;
assign GEN_234 = {{16'd0}, ctrl_dla_interxfr};
assign T_2591 = GEN_234 << 16;
assign GEN_235 = {{16'd0}, ctrl_dla_intercs};
assign T_2595 = GEN_235 | T_2591;
assign T_2611 = T_1383_25 & T_1798;
assign T_2631 = fifo_io_rx_bits;
assign T_2675 = {{23'd0}, T_2631};
assign GEN_236 = {{31'd0}, T_1042};
assign T_2711 = GEN_236 << 31;
assign GEN_237 = {{1'd0}, T_2675};
assign T_2715 = GEN_237 | T_2711;
assign T_2735 = T_1388_28 & T_2082;
assign GEN_26 = T_2735 ? T_2096 : ctrl_cs_id;
assign T_2757 = T_1228 == 1'h0;
assign T_2759 = T_2757 | T_1363_0;
assign T_2761 = T_1273 == 1'h0;
assign T_2762 = T_1363_11 & T_1363_10;
assign T_2764 = T_2761 | T_2762;
assign T_2772 = T_1345 == 1'h0;
assign T_2774 = T_2772 | T_1363_28;
assign T_2776 = T_1237 == 1'h0;
assign T_2777 = T_1363_4 & T_1363_3;
assign T_2778 = T_2777 & T_1363_2;
assign T_2779 = T_2778 & T_1363_1;
assign T_2781 = T_2776 | T_2779;
assign T_2783 = T_1282 == 1'h0;
assign T_2785 = T_2783 | T_1363_12;
assign T_2796 = T_1246 == 1'h0;
assign T_2797 = T_1363_6 & T_1363_5;
assign T_2799 = T_2796 | T_2797;
assign T_2801 = T_1327 == 1'h0;
assign T_2802 = T_1363_24 & T_1363_23;
assign T_2804 = T_2801 | T_2802;
assign T_2818 = T_1318 == 1'h0;
assign T_2819 = T_1363_22 & T_1363_21;
assign T_2820 = T_2819 & T_1363_20;
assign T_2821 = T_2820 & T_1363_19;
assign T_2823 = T_2818 | T_2821;
assign T_2828 = T_1309 == 1'h0;
assign T_2829 = T_1363_18 & T_1363_17;
assign T_2830 = T_2829 & T_1363_16;
assign T_2832 = T_2828 | T_2830;
assign T_2834 = T_1336 == 1'h0;
assign T_2835 = T_1363_27 & T_1363_26;
assign T_2836 = T_2835 & T_1363_25;
assign T_2838 = T_2834 | T_2836;
assign T_2840 = T_1255 == 1'h0;
assign T_2842 = T_2840 | T_1363_7;
assign T_2844 = T_1300 == 1'h0;
assign T_2846 = T_2844 | T_1363_15;
assign T_2866 = T_1291 == 1'h0;
assign T_2867 = T_1363_14 & T_1363_13;
assign T_2869 = T_2866 | T_2867;
assign T_2871 = T_1264 == 1'h0;
assign T_2872 = T_1363_9 & T_1363_8;
assign T_2874 = T_2871 | T_2872;
assign T_2916_0 = T_2759;
assign T_2916_1 = T_2764;
assign T_2916_2 = 1'h1;
assign T_2916_3 = 1'h1;
assign T_2916_4 = T_2774;
assign T_2916_5 = T_2781;
assign T_2916_6 = T_2785;
assign T_2916_7 = 1'h1;
assign T_2916_8 = 1'h1;
assign T_2916_9 = 1'h1;
assign T_2916_10 = T_2799;
assign T_2916_11 = T_2804;
assign T_2916_12 = 1'h1;
assign T_2916_13 = 1'h1;
assign T_2916_14 = 1'h1;
assign T_2916_15 = 1'h1;
assign T_2916_16 = T_2823;
assign T_2916_17 = 1'h1;
assign T_2916_18 = T_2832;
assign T_2916_19 = T_2838;
assign T_2916_20 = T_2842;
assign T_2916_21 = T_2846;
assign T_2916_22 = 1'h1;
assign T_2916_23 = 1'h1;
assign T_2916_24 = 1'h1;
assign T_2916_25 = 1'h1;
assign T_2916_26 = 1'h1;
assign T_2916_27 = 1'h1;
assign T_2916_28 = T_2869;
assign T_2916_29 = T_2874;
assign T_2916_30 = 1'h1;
assign T_2916_31 = 1'h1;
assign T_2954 = T_2757 | T_1368_0;
assign T_2957 = T_1368_11 & T_1368_10;
assign T_2959 = T_2761 | T_2957;
assign T_2969 = T_2772 | T_1368_28;
assign T_2972 = T_1368_4 & T_1368_3;
assign T_2973 = T_2972 & T_1368_2;
assign T_2974 = T_2973 & T_1368_1;
assign T_2976 = T_2776 | T_2974;
assign T_2980 = T_2783 | T_1368_12;
assign T_2992 = T_1368_6 & T_1368_5;
assign T_2994 = T_2796 | T_2992;
assign T_2997 = T_1368_24 & T_1368_23;
assign T_2999 = T_2801 | T_2997;
assign T_3014 = T_1368_22 & T_1368_21;
assign T_3015 = T_3014 & T_1368_20;
assign T_3016 = T_3015 & T_1368_19;
assign T_3018 = T_2818 | T_3016;
assign T_3024 = T_1368_18 & T_1368_17;
assign T_3025 = T_3024 & T_1368_16;
assign T_3027 = T_2828 | T_3025;
assign T_3030 = T_1368_27 & T_1368_26;
assign T_3031 = T_3030 & T_1368_25;
assign T_3033 = T_2834 | T_3031;
assign T_3037 = T_2840 | T_1368_7;
assign T_3041 = T_2844 | T_1368_15;
assign T_3062 = T_1368_14 & T_1368_13;
assign T_3064 = T_2866 | T_3062;
assign T_3067 = T_1368_9 & T_1368_8;
assign T_3069 = T_2871 | T_3067;
assign T_3111_0 = T_2954;
assign T_3111_1 = T_2959;
assign T_3111_2 = 1'h1;
assign T_3111_3 = 1'h1;
assign T_3111_4 = T_2969;
assign T_3111_5 = T_2976;
assign T_3111_6 = T_2980;
assign T_3111_7 = 1'h1;
assign T_3111_8 = 1'h1;
assign T_3111_9 = 1'h1;
assign T_3111_10 = T_2994;
assign T_3111_11 = T_2999;
assign T_3111_12 = 1'h1;
assign T_3111_13 = 1'h1;
assign T_3111_14 = 1'h1;
assign T_3111_15 = 1'h1;
assign T_3111_16 = T_3018;
assign T_3111_17 = 1'h1;
assign T_3111_18 = T_3027;
assign T_3111_19 = T_3033;
assign T_3111_20 = T_3037;
assign T_3111_21 = T_3041;
assign T_3111_22 = 1'h1;
assign T_3111_23 = 1'h1;
assign T_3111_24 = 1'h1;
assign T_3111_25 = 1'h1;
assign T_3111_26 = 1'h1;
assign T_3111_27 = 1'h1;
assign T_3111_28 = T_3064;
assign T_3111_29 = T_3069;
assign T_3111_30 = 1'h1;
assign T_3111_31 = 1'h1;
assign T_3149 = T_2757 | T_1373_0;
assign T_3152 = T_1373_11 & T_1373_10;
assign T_3154 = T_2761 | T_3152;
assign T_3164 = T_2772 | T_1373_28;
assign T_3167 = T_1373_4 & T_1373_3;
assign T_3168 = T_3167 & T_1373_2;
assign T_3169 = T_3168 & T_1373_1;
assign T_3171 = T_2776 | T_3169;
assign T_3175 = T_2783 | T_1373_12;
assign T_3187 = T_1373_6 & T_1373_5;
assign T_3189 = T_2796 | T_3187;
assign T_3192 = T_1373_24 & T_1373_23;
assign T_3194 = T_2801 | T_3192;
assign T_3209 = T_1373_22 & T_1373_21;
assign T_3210 = T_3209 & T_1373_20;
assign T_3211 = T_3210 & T_1373_19;
assign T_3213 = T_2818 | T_3211;
assign T_3219 = T_1373_18 & T_1373_17;
assign T_3220 = T_3219 & T_1373_16;
assign T_3222 = T_2828 | T_3220;
assign T_3225 = T_1373_27 & T_1373_26;
assign T_3226 = T_3225 & T_1373_25;
assign T_3228 = T_2834 | T_3226;
assign T_3232 = T_2840 | T_1373_7;
assign T_3236 = T_2844 | T_1373_15;
assign T_3257 = T_1373_14 & T_1373_13;
assign T_3259 = T_2866 | T_3257;
assign T_3262 = T_1373_9 & T_1373_8;
assign T_3264 = T_2871 | T_3262;
assign T_3306_0 = T_3149;
assign T_3306_1 = T_3154;
assign T_3306_2 = 1'h1;
assign T_3306_3 = 1'h1;
assign T_3306_4 = T_3164;
assign T_3306_5 = T_3171;
assign T_3306_6 = T_3175;
assign T_3306_7 = 1'h1;
assign T_3306_8 = 1'h1;
assign T_3306_9 = 1'h1;
assign T_3306_10 = T_3189;
assign T_3306_11 = T_3194;
assign T_3306_12 = 1'h1;
assign T_3306_13 = 1'h1;
assign T_3306_14 = 1'h1;
assign T_3306_15 = 1'h1;
assign T_3306_16 = T_3213;
assign T_3306_17 = 1'h1;
assign T_3306_18 = T_3222;
assign T_3306_19 = T_3228;
assign T_3306_20 = T_3232;
assign T_3306_21 = T_3236;
assign T_3306_22 = 1'h1;
assign T_3306_23 = 1'h1;
assign T_3306_24 = 1'h1;
assign T_3306_25 = 1'h1;
assign T_3306_26 = 1'h1;
assign T_3306_27 = 1'h1;
assign T_3306_28 = T_3259;
assign T_3306_29 = T_3264;
assign T_3306_30 = 1'h1;
assign T_3306_31 = 1'h1;
assign T_3344 = T_2757 | T_1378_0;
assign T_3347 = T_1378_11 & T_1378_10;
assign T_3349 = T_2761 | T_3347;
assign T_3359 = T_2772 | T_1378_28;
assign T_3362 = T_1378_4 & T_1378_3;
assign T_3363 = T_3362 & T_1378_2;
assign T_3364 = T_3363 & T_1378_1;
assign T_3366 = T_2776 | T_3364;
assign T_3370 = T_2783 | T_1378_12;
assign T_3382 = T_1378_6 & T_1378_5;
assign T_3384 = T_2796 | T_3382;
assign T_3387 = T_1378_24 & T_1378_23;
assign T_3389 = T_2801 | T_3387;
assign T_3404 = T_1378_22 & T_1378_21;
assign T_3405 = T_3404 & T_1378_20;
assign T_3406 = T_3405 & T_1378_19;
assign T_3408 = T_2818 | T_3406;
assign T_3414 = T_1378_18 & T_1378_17;
assign T_3415 = T_3414 & T_1378_16;
assign T_3417 = T_2828 | T_3415;
assign T_3420 = T_1378_27 & T_1378_26;
assign T_3421 = T_3420 & T_1378_25;
assign T_3423 = T_2834 | T_3421;
assign T_3427 = T_2840 | T_1378_7;
assign T_3431 = T_2844 | T_1378_15;
assign T_3452 = T_1378_14 & T_1378_13;
assign T_3454 = T_2866 | T_3452;
assign T_3457 = T_1378_9 & T_1378_8;
assign T_3459 = T_2871 | T_3457;
assign T_3501_0 = T_3344;
assign T_3501_1 = T_3349;
assign T_3501_2 = 1'h1;
assign T_3501_3 = 1'h1;
assign T_3501_4 = T_3359;
assign T_3501_5 = T_3366;
assign T_3501_6 = T_3370;
assign T_3501_7 = 1'h1;
assign T_3501_8 = 1'h1;
assign T_3501_9 = 1'h1;
assign T_3501_10 = T_3384;
assign T_3501_11 = T_3389;
assign T_3501_12 = 1'h1;
assign T_3501_13 = 1'h1;
assign T_3501_14 = 1'h1;
assign T_3501_15 = 1'h1;
assign T_3501_16 = T_3408;
assign T_3501_17 = 1'h1;
assign T_3501_18 = T_3417;
assign T_3501_19 = T_3423;
assign T_3501_20 = T_3427;
assign T_3501_21 = T_3431;
assign T_3501_22 = 1'h1;
assign T_3501_23 = 1'h1;
assign T_3501_24 = 1'h1;
assign T_3501_25 = 1'h1;
assign T_3501_26 = 1'h1;
assign T_3501_27 = 1'h1;
assign T_3501_28 = T_3454;
assign T_3501_29 = T_3459;
assign T_3501_30 = 1'h1;
assign T_3501_31 = 1'h1;
assign T_3536 = T_1141_bits_index[0];
assign T_3537 = T_1141_bits_index[1];
assign T_3538 = T_1141_bits_index[2];
assign T_3539 = T_1141_bits_index[3];
assign T_3540 = T_1141_bits_index[4];
assign T_3546 = {T_3537,T_3536};
assign T_3547 = {T_3540,T_3539};
assign T_3548 = {T_3547,T_3538};
assign T_3549 = {T_3548,T_3546};
assign GEN_0 = GEN_57;
assign GEN_27 = 5'h1 == T_3549 ? T_2916_1 : T_2916_0;
assign GEN_28 = 5'h2 == T_3549 ? T_2916_2 : GEN_27;
assign GEN_29 = 5'h3 == T_3549 ? T_2916_3 : GEN_28;
assign GEN_30 = 5'h4 == T_3549 ? T_2916_4 : GEN_29;
assign GEN_31 = 5'h5 == T_3549 ? T_2916_5 : GEN_30;
assign GEN_32 = 5'h6 == T_3549 ? T_2916_6 : GEN_31;
assign GEN_33 = 5'h7 == T_3549 ? T_2916_7 : GEN_32;
assign GEN_34 = 5'h8 == T_3549 ? T_2916_8 : GEN_33;
assign GEN_35 = 5'h9 == T_3549 ? T_2916_9 : GEN_34;
assign GEN_36 = 5'ha == T_3549 ? T_2916_10 : GEN_35;
assign GEN_37 = 5'hb == T_3549 ? T_2916_11 : GEN_36;
assign GEN_38 = 5'hc == T_3549 ? T_2916_12 : GEN_37;
assign GEN_39 = 5'hd == T_3549 ? T_2916_13 : GEN_38;
assign GEN_40 = 5'he == T_3549 ? T_2916_14 : GEN_39;
assign GEN_41 = 5'hf == T_3549 ? T_2916_15 : GEN_40;
assign GEN_42 = 5'h10 == T_3549 ? T_2916_16 : GEN_41;
assign GEN_43 = 5'h11 == T_3549 ? T_2916_17 : GEN_42;
assign GEN_44 = 5'h12 == T_3549 ? T_2916_18 : GEN_43;
assign GEN_45 = 5'h13 == T_3549 ? T_2916_19 : GEN_44;
assign GEN_46 = 5'h14 == T_3549 ? T_2916_20 : GEN_45;
assign GEN_47 = 5'h15 == T_3549 ? T_2916_21 : GEN_46;
assign GEN_48 = 5'h16 == T_3549 ? T_2916_22 : GEN_47;
assign GEN_49 = 5'h17 == T_3549 ? T_2916_23 : GEN_48;
assign GEN_50 = 5'h18 == T_3549 ? T_2916_24 : GEN_49;
assign GEN_51 = 5'h19 == T_3549 ? T_2916_25 : GEN_50;
assign GEN_52 = 5'h1a == T_3549 ? T_2916_26 : GEN_51;
assign GEN_53 = 5'h1b == T_3549 ? T_2916_27 : GEN_52;
assign GEN_54 = 5'h1c == T_3549 ? T_2916_28 : GEN_53;
assign GEN_55 = 5'h1d == T_3549 ? T_2916_29 : GEN_54;
assign GEN_56 = 5'h1e == T_3549 ? T_2916_30 : GEN_55;
assign GEN_57 = 5'h1f == T_3549 ? T_2916_31 : GEN_56;
assign GEN_1 = GEN_88;
assign GEN_58 = 5'h1 == T_3549 ? T_3111_1 : T_3111_0;
assign GEN_59 = 5'h2 == T_3549 ? T_3111_2 : GEN_58;
assign GEN_60 = 5'h3 == T_3549 ? T_3111_3 : GEN_59;
assign GEN_61 = 5'h4 == T_3549 ? T_3111_4 : GEN_60;
assign GEN_62 = 5'h5 == T_3549 ? T_3111_5 : GEN_61;
assign GEN_63 = 5'h6 == T_3549 ? T_3111_6 : GEN_62;
assign GEN_64 = 5'h7 == T_3549 ? T_3111_7 : GEN_63;
assign GEN_65 = 5'h8 == T_3549 ? T_3111_8 : GEN_64;
assign GEN_66 = 5'h9 == T_3549 ? T_3111_9 : GEN_65;
assign GEN_67 = 5'ha == T_3549 ? T_3111_10 : GEN_66;
assign GEN_68 = 5'hb == T_3549 ? T_3111_11 : GEN_67;
assign GEN_69 = 5'hc == T_3549 ? T_3111_12 : GEN_68;
assign GEN_70 = 5'hd == T_3549 ? T_3111_13 : GEN_69;
assign GEN_71 = 5'he == T_3549 ? T_3111_14 : GEN_70;
assign GEN_72 = 5'hf == T_3549 ? T_3111_15 : GEN_71;
assign GEN_73 = 5'h10 == T_3549 ? T_3111_16 : GEN_72;
assign GEN_74 = 5'h11 == T_3549 ? T_3111_17 : GEN_73;
assign GEN_75 = 5'h12 == T_3549 ? T_3111_18 : GEN_74;
assign GEN_76 = 5'h13 == T_3549 ? T_3111_19 : GEN_75;
assign GEN_77 = 5'h14 == T_3549 ? T_3111_20 : GEN_76;
assign GEN_78 = 5'h15 == T_3549 ? T_3111_21 : GEN_77;
assign GEN_79 = 5'h16 == T_3549 ? T_3111_22 : GEN_78;
assign GEN_80 = 5'h17 == T_3549 ? T_3111_23 : GEN_79;
assign GEN_81 = 5'h18 == T_3549 ? T_3111_24 : GEN_80;
assign GEN_82 = 5'h19 == T_3549 ? T_3111_25 : GEN_81;
assign GEN_83 = 5'h1a == T_3549 ? T_3111_26 : GEN_82;
assign GEN_84 = 5'h1b == T_3549 ? T_3111_27 : GEN_83;
assign GEN_85 = 5'h1c == T_3549 ? T_3111_28 : GEN_84;
assign GEN_86 = 5'h1d == T_3549 ? T_3111_29 : GEN_85;
assign GEN_87 = 5'h1e == T_3549 ? T_3111_30 : GEN_86;
assign GEN_88 = 5'h1f == T_3549 ? T_3111_31 : GEN_87;
assign T_3566 = T_1141_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_119;
assign GEN_89 = 5'h1 == T_3549 ? T_3306_1 : T_3306_0;
assign GEN_90 = 5'h2 == T_3549 ? T_3306_2 : GEN_89;
assign GEN_91 = 5'h3 == T_3549 ? T_3306_3 : GEN_90;
assign GEN_92 = 5'h4 == T_3549 ? T_3306_4 : GEN_91;
assign GEN_93 = 5'h5 == T_3549 ? T_3306_5 : GEN_92;
assign GEN_94 = 5'h6 == T_3549 ? T_3306_6 : GEN_93;
assign GEN_95 = 5'h7 == T_3549 ? T_3306_7 : GEN_94;
assign GEN_96 = 5'h8 == T_3549 ? T_3306_8 : GEN_95;
assign GEN_97 = 5'h9 == T_3549 ? T_3306_9 : GEN_96;
assign GEN_98 = 5'ha == T_3549 ? T_3306_10 : GEN_97;
assign GEN_99 = 5'hb == T_3549 ? T_3306_11 : GEN_98;
assign GEN_100 = 5'hc == T_3549 ? T_3306_12 : GEN_99;
assign GEN_101 = 5'hd == T_3549 ? T_3306_13 : GEN_100;
assign GEN_102 = 5'he == T_3549 ? T_3306_14 : GEN_101;
assign GEN_103 = 5'hf == T_3549 ? T_3306_15 : GEN_102;
assign GEN_104 = 5'h10 == T_3549 ? T_3306_16 : GEN_103;
assign GEN_105 = 5'h11 == T_3549 ? T_3306_17 : GEN_104;
assign GEN_106 = 5'h12 == T_3549 ? T_3306_18 : GEN_105;
assign GEN_107 = 5'h13 == T_3549 ? T_3306_19 : GEN_106;
assign GEN_108 = 5'h14 == T_3549 ? T_3306_20 : GEN_107;
assign GEN_109 = 5'h15 == T_3549 ? T_3306_21 : GEN_108;
assign GEN_110 = 5'h16 == T_3549 ? T_3306_22 : GEN_109;
assign GEN_111 = 5'h17 == T_3549 ? T_3306_23 : GEN_110;
assign GEN_112 = 5'h18 == T_3549 ? T_3306_24 : GEN_111;
assign GEN_113 = 5'h19 == T_3549 ? T_3306_25 : GEN_112;
assign GEN_114 = 5'h1a == T_3549 ? T_3306_26 : GEN_113;
assign GEN_115 = 5'h1b == T_3549 ? T_3306_27 : GEN_114;
assign GEN_116 = 5'h1c == T_3549 ? T_3306_28 : GEN_115;
assign GEN_117 = 5'h1d == T_3549 ? T_3306_29 : GEN_116;
assign GEN_118 = 5'h1e == T_3549 ? T_3306_30 : GEN_117;
assign GEN_119 = 5'h1f == T_3549 ? T_3306_31 : GEN_118;
assign GEN_3 = GEN_150;
assign GEN_120 = 5'h1 == T_3549 ? T_3501_1 : T_3501_0;
assign GEN_121 = 5'h2 == T_3549 ? T_3501_2 : GEN_120;
assign GEN_122 = 5'h3 == T_3549 ? T_3501_3 : GEN_121;
assign GEN_123 = 5'h4 == T_3549 ? T_3501_4 : GEN_122;
assign GEN_124 = 5'h5 == T_3549 ? T_3501_5 : GEN_123;
assign GEN_125 = 5'h6 == T_3549 ? T_3501_6 : GEN_124;
assign GEN_126 = 5'h7 == T_3549 ? T_3501_7 : GEN_125;
assign GEN_127 = 5'h8 == T_3549 ? T_3501_8 : GEN_126;
assign GEN_128 = 5'h9 == T_3549 ? T_3501_9 : GEN_127;
assign GEN_129 = 5'ha == T_3549 ? T_3501_10 : GEN_128;
assign GEN_130 = 5'hb == T_3549 ? T_3501_11 : GEN_129;
assign GEN_131 = 5'hc == T_3549 ? T_3501_12 : GEN_130;
assign GEN_132 = 5'hd == T_3549 ? T_3501_13 : GEN_131;
assign GEN_133 = 5'he == T_3549 ? T_3501_14 : GEN_132;
assign GEN_134 = 5'hf == T_3549 ? T_3501_15 : GEN_133;
assign GEN_135 = 5'h10 == T_3549 ? T_3501_16 : GEN_134;
assign GEN_136 = 5'h11 == T_3549 ? T_3501_17 : GEN_135;
assign GEN_137 = 5'h12 == T_3549 ? T_3501_18 : GEN_136;
assign GEN_138 = 5'h13 == T_3549 ? T_3501_19 : GEN_137;
assign GEN_139 = 5'h14 == T_3549 ? T_3501_20 : GEN_138;
assign GEN_140 = 5'h15 == T_3549 ? T_3501_21 : GEN_139;
assign GEN_141 = 5'h16 == T_3549 ? T_3501_22 : GEN_140;
assign GEN_142 = 5'h17 == T_3549 ? T_3501_23 : GEN_141;
assign GEN_143 = 5'h18 == T_3549 ? T_3501_24 : GEN_142;
assign GEN_144 = 5'h19 == T_3549 ? T_3501_25 : GEN_143;
assign GEN_145 = 5'h1a == T_3549 ? T_3501_26 : GEN_144;
assign GEN_146 = 5'h1b == T_3549 ? T_3501_27 : GEN_145;
assign GEN_147 = 5'h1c == T_3549 ? T_3501_28 : GEN_146;
assign GEN_148 = 5'h1d == T_3549 ? T_3501_29 : GEN_147;
assign GEN_149 = 5'h1e == T_3549 ? T_3501_30 : GEN_148;
assign GEN_150 = 5'h1f == T_3549 ? T_3501_31 : GEN_149;
assign T_3569 = T_1141_bits_read ? GEN_2 : GEN_3;
assign T_3570 = T_1141_ready & T_3566;
assign T_3571 = T_1066_valid & T_3566;
assign T_3572 = T_1105_ready & T_3569;
assign T_3573 = T_1141_valid & T_3569;
assign T_3575 = 32'h1 << T_3549;
assign T_3576 = {T_1273,T_1228};
assign T_3578 = {2'h3,T_3576};
assign T_3579 = {T_1237,T_1345};
assign T_3580 = {1'h1,T_1282};
assign T_3581 = {T_3580,T_3579};
assign T_3582 = {T_3581,T_3578};
assign T_3584 = {T_1327,T_1246};
assign T_3585 = {T_3584,2'h3};
assign T_3589 = {4'hf,T_3585};
assign T_3590 = {T_3589,T_3582};
assign T_3591 = {1'h1,T_1318};
assign T_3592 = {T_1336,T_1309};
assign T_3593 = {T_3592,T_3591};
assign T_3594 = {T_1300,T_1255};
assign T_3596 = {2'h3,T_3594};
assign T_3597 = {T_3596,T_3593};
assign T_3601 = {T_1264,T_1291};
assign T_3603 = {2'h3,T_3601};
assign T_3604 = {T_3603,4'hf};
assign T_3605 = {T_3604,T_3597};
assign T_3606 = {T_3605,T_3590};
assign T_3607 = T_3575 & T_3606;
assign T_3642 = T_1066_valid & T_1141_ready;
assign T_3643 = T_3642 & T_1141_bits_read;
assign T_3644 = T_3607[0];
assign T_3645 = T_3643 & T_3644;
assign T_3648 = T_1141_bits_read == 1'h0;
assign T_3649 = T_3642 & T_3648;
assign T_3651 = T_3649 & T_3644;
assign T_3652 = T_1141_valid & T_1105_ready;
assign T_3653 = T_3652 & T_1141_bits_read;
assign T_3655 = T_3653 & T_3644;
assign T_3659 = T_3652 & T_3648;
assign T_3661 = T_3659 & T_3644;
assign T_3664 = T_3607[1];
assign T_3665 = T_3643 & T_3664;
assign T_3671 = T_3649 & T_3664;
assign T_3675 = T_3653 & T_3664;
assign T_3681 = T_3659 & T_3664;
assign T_3724 = T_3607[4];
assign T_3725 = T_3643 & T_3724;
assign T_3731 = T_3649 & T_3724;
assign T_3735 = T_3653 & T_3724;
assign T_3741 = T_3659 & T_3724;
assign T_3744 = T_3607[5];
assign T_3745 = T_3643 & T_3744;
assign T_3751 = T_3649 & T_3744;
assign T_3755 = T_3653 & T_3744;
assign T_3761 = T_3659 & T_3744;
assign T_3764 = T_3607[6];
assign T_3765 = T_3643 & T_3764;
assign T_3771 = T_3649 & T_3764;
assign T_3775 = T_3653 & T_3764;
assign T_3781 = T_3659 & T_3764;
assign T_3844 = T_3607[10];
assign T_3845 = T_3643 & T_3844;
assign T_3851 = T_3649 & T_3844;
assign T_3855 = T_3653 & T_3844;
assign T_3861 = T_3659 & T_3844;
assign T_3864 = T_3607[11];
assign T_3865 = T_3643 & T_3864;
assign T_3871 = T_3649 & T_3864;
assign T_3875 = T_3653 & T_3864;
assign T_3881 = T_3659 & T_3864;
assign T_3964 = T_3607[16];
assign T_3965 = T_3643 & T_3964;
assign T_3971 = T_3649 & T_3964;
assign T_3975 = T_3653 & T_3964;
assign T_3981 = T_3659 & T_3964;
assign T_4004 = T_3607[18];
assign T_4005 = T_3643 & T_4004;
assign T_4011 = T_3649 & T_4004;
assign T_4015 = T_3653 & T_4004;
assign T_4021 = T_3659 & T_4004;
assign T_4024 = T_3607[19];
assign T_4025 = T_3643 & T_4024;
assign T_4031 = T_3649 & T_4024;
assign T_4035 = T_3653 & T_4024;
assign T_4041 = T_3659 & T_4024;
assign T_4044 = T_3607[20];
assign T_4045 = T_3643 & T_4044;
assign T_4051 = T_3649 & T_4044;
assign T_4055 = T_3653 & T_4044;
assign T_4061 = T_3659 & T_4044;
assign T_4064 = T_3607[21];
assign T_4065 = T_3643 & T_4064;
assign T_4071 = T_3649 & T_4064;
assign T_4075 = T_3653 & T_4064;
assign T_4081 = T_3659 & T_4064;
assign T_4204 = T_3607[28];
assign T_4205 = T_3643 & T_4204;
assign T_4211 = T_3649 & T_4204;
assign T_4215 = T_3653 & T_4204;
assign T_4221 = T_3659 & T_4204;
assign T_4224 = T_3607[29];
assign T_4225 = T_3643 & T_4224;
assign T_4231 = T_3649 & T_4224;
assign T_4235 = T_3653 & T_4224;
assign T_4241 = T_3659 & T_4224;
assign T_4286 = T_3745 & T_1363_4;
assign T_4287 = T_4286 & T_1363_3;
assign T_4288 = T_4287 & T_1363_2;
assign T_4290 = T_3751 & T_1368_4;
assign T_4291 = T_4290 & T_1368_3;
assign T_4292 = T_4291 & T_1368_2;
assign T_4294 = T_3755 & T_1373_4;
assign T_4295 = T_4294 & T_1373_3;
assign T_4296 = T_4295 & T_1373_2;
assign T_4298 = T_3761 & T_1378_4;
assign T_4299 = T_4298 & T_1378_3;
assign T_4300 = T_4299 & T_1378_2;
assign T_4304 = T_4287 & T_1363_1;
assign T_4308 = T_4291 & T_1368_1;
assign T_4312 = T_4295 & T_1373_1;
assign T_4316 = T_4299 & T_1378_1;
assign T_4319 = T_4286 & T_1363_2;
assign T_4320 = T_4319 & T_1363_1;
assign T_4323 = T_4290 & T_1368_2;
assign T_4324 = T_4323 & T_1368_1;
assign T_4327 = T_4294 & T_1373_2;
assign T_4328 = T_4327 & T_1373_1;
assign T_4331 = T_4298 & T_1378_2;
assign T_4332 = T_4331 & T_1378_1;
assign T_4334 = T_3745 & T_1363_3;
assign T_4335 = T_4334 & T_1363_2;
assign T_4336 = T_4335 & T_1363_1;
assign T_4338 = T_3751 & T_1368_3;
assign T_4339 = T_4338 & T_1368_2;
assign T_4340 = T_4339 & T_1368_1;
assign T_4342 = T_3755 & T_1373_3;
assign T_4343 = T_4342 & T_1373_2;
assign T_4344 = T_4343 & T_1373_1;
assign T_4346 = T_3761 & T_1378_3;
assign T_4347 = T_4346 & T_1378_2;
assign T_4348 = T_4347 & T_1378_1;
assign T_4350 = T_3845 & T_1363_6;
assign T_4352 = T_3851 & T_1368_6;
assign T_4354 = T_3855 & T_1373_6;
assign T_4356 = T_3861 & T_1378_6;
assign T_4358 = T_3845 & T_1363_5;
assign T_4360 = T_3851 & T_1368_5;
assign T_4362 = T_3855 & T_1373_5;
assign T_4364 = T_3861 & T_1378_5;
assign T_4370 = T_4225 & T_1363_9;
assign T_4372 = T_4231 & T_1368_9;
assign T_4374 = T_4235 & T_1373_9;
assign T_4376 = T_4241 & T_1378_9;
assign T_4378 = T_4225 & T_1363_8;
assign T_4380 = T_4231 & T_1368_8;
assign T_4382 = T_4235 & T_1373_8;
assign T_4384 = T_4241 & T_1378_8;
assign T_4386 = T_3665 & T_1363_11;
assign T_4388 = T_3671 & T_1368_11;
assign T_4390 = T_3675 & T_1373_11;
assign T_4392 = T_3681 & T_1378_11;
assign T_4394 = T_3665 & T_1363_10;
assign T_4396 = T_3671 & T_1368_10;
assign T_4398 = T_3675 & T_1373_10;
assign T_4400 = T_3681 & T_1378_10;
assign T_4406 = T_4205 & T_1363_14;
assign T_4408 = T_4211 & T_1368_14;
assign T_4410 = T_4215 & T_1373_14;
assign T_4412 = T_4221 & T_1378_14;
assign T_4414 = T_4205 & T_1363_13;
assign T_4416 = T_4211 & T_1368_13;
assign T_4418 = T_4215 & T_1373_13;
assign T_4420 = T_4221 & T_1378_13;
assign T_4426 = T_4005 & T_1363_18;
assign T_4427 = T_4426 & T_1363_17;
assign T_4429 = T_4011 & T_1368_18;
assign T_4430 = T_4429 & T_1368_17;
assign T_4432 = T_4015 & T_1373_18;
assign T_4433 = T_4432 & T_1373_17;
assign T_4435 = T_4021 & T_1378_18;
assign T_4436 = T_4435 & T_1378_17;
assign T_4439 = T_4426 & T_1363_16;
assign T_4442 = T_4429 & T_1368_16;
assign T_4445 = T_4432 & T_1373_16;
assign T_4448 = T_4435 & T_1378_16;
assign T_4450 = T_4005 & T_1363_17;
assign T_4451 = T_4450 & T_1363_16;
assign T_4453 = T_4011 & T_1368_17;
assign T_4454 = T_4453 & T_1368_16;
assign T_4456 = T_4015 & T_1373_17;
assign T_4457 = T_4456 & T_1373_16;
assign T_4459 = T_4021 & T_1378_17;
assign T_4460 = T_4459 & T_1378_16;
assign T_4462 = T_3965 & T_1363_22;
assign T_4463 = T_4462 & T_1363_21;
assign T_4464 = T_4463 & T_1363_20;
assign T_4466 = T_3971 & T_1368_22;
assign T_4467 = T_4466 & T_1368_21;
assign T_4468 = T_4467 & T_1368_20;
assign T_4470 = T_3975 & T_1373_22;
assign T_4471 = T_4470 & T_1373_21;
assign T_4472 = T_4471 & T_1373_20;
assign T_4474 = T_3981 & T_1378_22;
assign T_4475 = T_4474 & T_1378_21;
assign T_4476 = T_4475 & T_1378_20;
assign T_4480 = T_4463 & T_1363_19;
assign T_4484 = T_4467 & T_1368_19;
assign T_4488 = T_4471 & T_1373_19;
assign T_4492 = T_4475 & T_1378_19;
assign T_4495 = T_4462 & T_1363_20;
assign T_4496 = T_4495 & T_1363_19;
assign T_4499 = T_4466 & T_1368_20;
assign T_4500 = T_4499 & T_1368_19;
assign T_4503 = T_4470 & T_1373_20;
assign T_4504 = T_4503 & T_1373_19;
assign T_4507 = T_4474 & T_1378_20;
assign T_4508 = T_4507 & T_1378_19;
assign T_4510 = T_3965 & T_1363_21;
assign T_4511 = T_4510 & T_1363_20;
assign T_4512 = T_4511 & T_1363_19;
assign T_4514 = T_3971 & T_1368_21;
assign T_4515 = T_4514 & T_1368_20;
assign T_4516 = T_4515 & T_1368_19;
assign T_4518 = T_3975 & T_1373_21;
assign T_4519 = T_4518 & T_1373_20;
assign T_4520 = T_4519 & T_1373_19;
assign T_4522 = T_3981 & T_1378_21;
assign T_4523 = T_4522 & T_1378_20;
assign T_4524 = T_4523 & T_1378_19;
assign T_4526 = T_3865 & T_1363_24;
assign T_4528 = T_3871 & T_1368_24;
assign T_4530 = T_3875 & T_1373_24;
assign T_4532 = T_3881 & T_1378_24;
assign T_4534 = T_3865 & T_1363_23;
assign T_4536 = T_3871 & T_1368_23;
assign T_4538 = T_3875 & T_1373_23;
assign T_4540 = T_3881 & T_1378_23;
assign T_4542 = T_4025 & T_1363_27;
assign T_4543 = T_4542 & T_1363_26;
assign T_4545 = T_4031 & T_1368_27;
assign T_4546 = T_4545 & T_1368_26;
assign T_4548 = T_4035 & T_1373_27;
assign T_4549 = T_4548 & T_1373_26;
assign T_4551 = T_4041 & T_1378_27;
assign T_4552 = T_4551 & T_1378_26;
assign T_4555 = T_4542 & T_1363_25;
assign T_4558 = T_4545 & T_1368_25;
assign T_4561 = T_4548 & T_1373_25;
assign T_4564 = T_4551 & T_1378_25;
assign T_4566 = T_4025 & T_1363_26;
assign T_4567 = T_4566 & T_1363_25;
assign T_4569 = T_4031 & T_1368_26;
assign T_4570 = T_4569 & T_1368_25;
assign T_4572 = T_4035 & T_1373_26;
assign T_4573 = T_4572 & T_1373_25;
assign T_4575 = T_4041 & T_1378_26;
assign T_4576 = T_4575 & T_1378_25;
assign T_4617_0 = T_1228;
assign T_4617_1 = T_1273;
assign T_4617_2 = 1'h1;
assign T_4617_3 = 1'h1;
assign T_4617_4 = T_1345;
assign T_4617_5 = T_1237;
assign T_4617_6 = T_1282;
assign T_4617_7 = 1'h1;
assign T_4617_8 = 1'h1;
assign T_4617_9 = 1'h1;
assign T_4617_10 = T_1246;
assign T_4617_11 = T_1327;
assign T_4617_12 = 1'h1;
assign T_4617_13 = 1'h1;
assign T_4617_14 = 1'h1;
assign T_4617_15 = 1'h1;
assign T_4617_16 = T_1318;
assign T_4617_17 = 1'h1;
assign T_4617_18 = T_1309;
assign T_4617_19 = T_1336;
assign T_4617_20 = T_1255;
assign T_4617_21 = T_1300;
assign T_4617_22 = 1'h1;
assign T_4617_23 = 1'h1;
assign T_4617_24 = 1'h1;
assign T_4617_25 = 1'h1;
assign T_4617_26 = 1'h1;
assign T_4617_27 = 1'h1;
assign T_4617_28 = T_1291;
assign T_4617_29 = T_1264;
assign T_4617_30 = 1'h1;
assign T_4617_31 = 1'h1;
assign T_4688_0 = {{20'd0}, ctrl_sck_div};
assign T_4688_1 = {{30'd0}, T_2075};
assign T_4688_2 = 32'h0;
assign T_4688_3 = 32'h0;
assign T_4688_4 = {{30'd0}, ctrl_cs_id};
assign T_4688_5 = {{28'd0}, T_1795};
assign T_4688_6 = {{30'd0}, ctrl_cs_mode};
assign T_4688_7 = 32'h0;
assign T_4688_8 = 32'h0;
assign T_4688_9 = 32'h0;
assign T_4688_10 = {{8'd0}, T_1875};
assign T_4688_11 = {{8'd0}, T_2595};
assign T_4688_12 = 32'h0;
assign T_4688_13 = 32'h0;
assign T_4688_14 = 32'h0;
assign T_4688_15 = 32'h0;
assign T_4688_16 = {{12'd0}, T_2515};
assign T_4688_17 = 32'h0;
assign T_4688_18 = T_2351;
assign T_4688_19 = T_2715;
assign T_4688_20 = {{28'd0}, ctrl_wm_tx};
assign T_4688_21 = {{28'd0}, ctrl_wm_rx};
assign T_4688_22 = 32'h0;
assign T_4688_23 = 32'h0;
assign T_4688_24 = 32'h0;
assign T_4688_25 = 32'h0;
assign T_4688_26 = 32'h0;
assign T_4688_27 = 32'h0;
assign T_4688_28 = {{30'd0}, T_2195};
assign T_4688_29 = {{30'd0}, T_1995};
assign T_4688_30 = 32'h0;
assign T_4688_31 = 32'h0;
assign GEN_4 = GEN_181;
assign GEN_151 = 5'h1 == T_3549 ? T_4617_1 : T_4617_0;
assign GEN_152 = 5'h2 == T_3549 ? T_4617_2 : GEN_151;
assign GEN_153 = 5'h3 == T_3549 ? T_4617_3 : GEN_152;
assign GEN_154 = 5'h4 == T_3549 ? T_4617_4 : GEN_153;
assign GEN_155 = 5'h5 == T_3549 ? T_4617_5 : GEN_154;
assign GEN_156 = 5'h6 == T_3549 ? T_4617_6 : GEN_155;
assign GEN_157 = 5'h7 == T_3549 ? T_4617_7 : GEN_156;
assign GEN_158 = 5'h8 == T_3549 ? T_4617_8 : GEN_157;
assign GEN_159 = 5'h9 == T_3549 ? T_4617_9 : GEN_158;
assign GEN_160 = 5'ha == T_3549 ? T_4617_10 : GEN_159;
assign GEN_161 = 5'hb == T_3549 ? T_4617_11 : GEN_160;
assign GEN_162 = 5'hc == T_3549 ? T_4617_12 : GEN_161;
assign GEN_163 = 5'hd == T_3549 ? T_4617_13 : GEN_162;
assign GEN_164 = 5'he == T_3549 ? T_4617_14 : GEN_163;
assign GEN_165 = 5'hf == T_3549 ? T_4617_15 : GEN_164;
assign GEN_166 = 5'h10 == T_3549 ? T_4617_16 : GEN_165;
assign GEN_167 = 5'h11 == T_3549 ? T_4617_17 : GEN_166;
assign GEN_168 = 5'h12 == T_3549 ? T_4617_18 : GEN_167;
assign GEN_169 = 5'h13 == T_3549 ? T_4617_19 : GEN_168;
assign GEN_170 = 5'h14 == T_3549 ? T_4617_20 : GEN_169;
assign GEN_171 = 5'h15 == T_3549 ? T_4617_21 : GEN_170;
assign GEN_172 = 5'h16 == T_3549 ? T_4617_22 : GEN_171;
assign GEN_173 = 5'h17 == T_3549 ? T_4617_23 : GEN_172;
assign GEN_174 = 5'h18 == T_3549 ? T_4617_24 : GEN_173;
assign GEN_175 = 5'h19 == T_3549 ? T_4617_25 : GEN_174;
assign GEN_176 = 5'h1a == T_3549 ? T_4617_26 : GEN_175;
assign GEN_177 = 5'h1b == T_3549 ? T_4617_27 : GEN_176;
assign GEN_178 = 5'h1c == T_3549 ? T_4617_28 : GEN_177;
assign GEN_179 = 5'h1d == T_3549 ? T_4617_29 : GEN_178;
assign GEN_180 = 5'h1e == T_3549 ? T_4617_30 : GEN_179;
assign GEN_181 = 5'h1f == T_3549 ? T_4617_31 : GEN_180;
assign GEN_5 = GEN_212;
assign GEN_182 = 5'h1 == T_3549 ? T_4688_1 : T_4688_0;
assign GEN_183 = 5'h2 == T_3549 ? T_4688_2 : GEN_182;
assign GEN_184 = 5'h3 == T_3549 ? T_4688_3 : GEN_183;
assign GEN_185 = 5'h4 == T_3549 ? T_4688_4 : GEN_184;
assign GEN_186 = 5'h5 == T_3549 ? T_4688_5 : GEN_185;
assign GEN_187 = 5'h6 == T_3549 ? T_4688_6 : GEN_186;
assign GEN_188 = 5'h7 == T_3549 ? T_4688_7 : GEN_187;
assign GEN_189 = 5'h8 == T_3549 ? T_4688_8 : GEN_188;
assign GEN_190 = 5'h9 == T_3549 ? T_4688_9 : GEN_189;
assign GEN_191 = 5'ha == T_3549 ? T_4688_10 : GEN_190;
assign GEN_192 = 5'hb == T_3549 ? T_4688_11 : GEN_191;
assign GEN_193 = 5'hc == T_3549 ? T_4688_12 : GEN_192;
assign GEN_194 = 5'hd == T_3549 ? T_4688_13 : GEN_193;
assign GEN_195 = 5'he == T_3549 ? T_4688_14 : GEN_194;
assign GEN_196 = 5'hf == T_3549 ? T_4688_15 : GEN_195;
assign GEN_197 = 5'h10 == T_3549 ? T_4688_16 : GEN_196;
assign GEN_198 = 5'h11 == T_3549 ? T_4688_17 : GEN_197;
assign GEN_199 = 5'h12 == T_3549 ? T_4688_18 : GEN_198;
assign GEN_200 = 5'h13 == T_3549 ? T_4688_19 : GEN_199;
assign GEN_201 = 5'h14 == T_3549 ? T_4688_20 : GEN_200;
assign GEN_202 = 5'h15 == T_3549 ? T_4688_21 : GEN_201;
assign GEN_203 = 5'h16 == T_3549 ? T_4688_22 : GEN_202;
assign GEN_204 = 5'h17 == T_3549 ? T_4688_23 : GEN_203;
assign GEN_205 = 5'h18 == T_3549 ? T_4688_24 : GEN_204;
assign GEN_206 = 5'h19 == T_3549 ? T_4688_25 : GEN_205;
assign GEN_207 = 5'h1a == T_3549 ? T_4688_26 : GEN_206;
assign GEN_208 = 5'h1b == T_3549 ? T_4688_27 : GEN_207;
assign GEN_209 = 5'h1c == T_3549 ? T_4688_28 : GEN_208;
assign GEN_210 = 5'h1d == T_3549 ? T_4688_29 : GEN_209;
assign GEN_211 = 5'h1e == T_3549 ? T_4688_30 : GEN_210;
assign GEN_212 = 5'h1f == T_3549 ? T_4688_31 : GEN_211;
assign T_4725 = GEN_4 ? GEN_5 : 32'h0;
assign T_4726 = T_1105_bits_extra[9:8];
assign T_4728 = T_1105_bits_extra[7:3];
assign T_4729 = T_1105_bits_extra[2:0];
assign T_4740_opcode = 3'h0;
assign T_4740_param = 2'h0;
assign T_4740_size = T_4729;
assign T_4740_source = T_4728;
assign T_4740_sink = 1'h0;
assign T_4740_addr_lo = T_4726;
assign T_4740_data = 32'h0;
assign T_4740_error = 1'h0;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_fmt_proto <= T_955_fmt_proto;
end else begin
if (T_2375) begin
ctrl_fmt_proto <= T_2096;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_fmt_endian <= T_955_fmt_endian;
end else begin
if (T_2415) begin
ctrl_fmt_endian <= T_1736;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_fmt_iodir <= T_955_fmt_iodir;
end else begin
if (T_2455) begin
ctrl_fmt_iodir <= T_1776;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_fmt_len <= T_955_fmt_len;
end else begin
if (T_2495) begin
ctrl_fmt_len <= T_2496;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= T_955_sck_div;
end else begin
if (T_1615) begin
ctrl_sck_div <= T_1616;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_pol <= T_955_sck_pol;
end else begin
if (T_2055) begin
ctrl_sck_pol <= T_1696;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_pha <= T_955_sck_pha;
end else begin
if (T_2015) begin
ctrl_sck_pha <= T_1656;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_cs_id <= T_955_cs_id;
end else begin
if (T_2735) begin
ctrl_cs_id <= T_2096;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_cs_dflt_0 <= T_955_cs_dflt_0;
end else begin
if (T_1655) begin
ctrl_cs_dflt_0 <= T_1656;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_cs_dflt_1 <= T_955_cs_dflt_1;
end else begin
if (T_1695) begin
ctrl_cs_dflt_1 <= T_1696;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_cs_dflt_2 <= T_955_cs_dflt_2;
end else begin
if (T_1735) begin
ctrl_cs_dflt_2 <= T_1736;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_cs_dflt_3 <= T_955_cs_dflt_3;
end else begin
if (T_1775) begin
ctrl_cs_dflt_3 <= T_1776;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_cs_mode <= T_955_cs_mode;
end else begin
if (T_2095) begin
ctrl_cs_mode <= T_2096;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_dla_cssck <= T_955_dla_cssck;
end else begin
if (T_1815) begin
ctrl_dla_cssck <= T_1816;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_dla_sckcs <= T_955_dla_sckcs;
end else begin
if (T_1855) begin
ctrl_dla_sckcs <= T_1856;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_dla_intercs <= T_955_dla_intercs;
end else begin
if (T_2535) begin
ctrl_dla_intercs <= T_1816;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_dla_interxfr <= T_955_dla_interxfr;
end else begin
if (T_2575) begin
ctrl_dla_interxfr <= T_1856;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_wm_tx <= T_955_wm_tx;
end else begin
if (T_1895) begin
ctrl_wm_tx <= T_1896;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_wm_rx <= T_955_wm_rx;
end else begin
if (T_2215) begin
ctrl_wm_rx <= T_1896;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ie_txwm <= T_1024_txwm;
end else begin
if (T_2135) begin
ie_txwm <= T_1656;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ie_rxwm <= T_1024_rxwm;
end else begin
if (T_2175) begin
ie_rxwm <= T_1696;
end
end
endmodule |
module sky130_fd_sc_ls__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule |
module basic_rom (address, instruction, enable, rdl, clk);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "7S";
parameter integer C_RAM_SIZE_KWORDS = 1;
//
input clk;
input [11:0] address;
input enable;
output [17:0] instruction;
output rdl;
//
//
wire [15:0] address_a;
wire pipe_a11;
wire [35:0] data_in_a;
wire [35:0] data_out_a;
wire [35:0] data_out_a_l;
wire [35:0] data_out_a_h;
wire [35:0] data_out_a_ll;
wire [35:0] data_out_a_lh;
wire [35:0] data_out_a_hl;
wire [35:0] data_out_a_hh;
wire [15:0] address_b;
wire [35:0] data_in_b;
wire [35:0] data_in_b_l;
wire [35:0] data_in_b_ll;
wire [35:0] data_in_b_hl;
wire [35:0] data_out_b;
wire [35:0] data_out_b_l;
wire [35:0] data_out_b_ll;
wire [35:0] data_out_b_hl;
wire [35:0] data_in_b_h;
wire [35:0] data_in_b_lh;
wire [35:0] data_in_b_hh;
wire [35:0] data_out_b_h;
wire [35:0] data_out_b_lh;
wire [35:0] data_out_b_hh;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
wire [3:0] we_b_l;
wire [3:0] we_b_h;
//
wire [11:0] jtag_addr;
wire jtag_we;
wire jtag_clk;
wire [17:0] jtag_din;
wire [17:0] jtag_dout;
wire [17:0] jtag_dout_1;
wire [0:0] jtag_en;
//
wire [0:0] picoblaze_reset;
wire [0:0] rdl_bus;
//
parameter integer BRAM_ADDRESS_WIDTH = addr_width_calc(C_RAM_SIZE_KWORDS);
//
//
function integer addr_width_calc;
input integer size_in_k;
if (size_in_k == 1) begin addr_width_calc = 10; end
else if (size_in_k == 2) begin addr_width_calc = 11; end
else if (size_in_k == 4) begin addr_width_calc = 12; end
else begin
if (C_RAM_SIZE_KWORDS != 1 && C_RAM_SIZE_KWORDS != 2 && C_RAM_SIZE_KWORDS != 4) begin
//#0;
$display("Invalid BlockRAM size. Please set to 1, 2 or 4 K words..\n");
$finish;
end
end
endfunction
//
//
generate
if (C_RAM_SIZE_KWORDS == 1) begin : ram_1k_generate
//
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a[13:0] = {address[9:0], 4'b1111};
assign instruction = data_out_a[17:0];
assign data_in_a[17:0] = {16'b0000000000000000, address[11:10]};
assign jtag_dout = data_out_b[17:0];
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b[17:0] = data_out_b[17:0];
assign address_b[13:0] = 14'b11111111111111;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b[17:0] = jtag_din[17:0];
assign address_b[13:0] = {jtag_addr[9:0], 4'b1111};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB18E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (18'b000000000000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (18'b000000000000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (18'b000000000000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (18'b000000000000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'hD0011010D0011008D0011004D0011002D0011001D00B1000D0081000D00010FF),
.INIT_01 (256'h000000009001D101D10C910920198001D0011000D0011080D0011040D0011020),
.INIT_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h201A000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000000000000000000000000000000000000000000000000A8A888888888888),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h8000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRARDADDR (address_a[13:0]),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[15:0]),
.DOPADOP (data_out_a[17:16]),
.DIADI (data_in_a[15:0]),
.DIPADIP (data_in_a[17:16]),
.WEA (2'b00),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b[13:0]),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[15:0]),
.DOPBDOP (data_out_b[17:16]),
.DIBDI (data_in_b[15:0]),
.DIPBDIP (data_in_b[17:16]),
.WEBWE (we_b[3:0]),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0));
end // akv7;
//
end // ram_1k_generate;
endgenerate
//
generate
if (C_RAM_SIZE_KWORDS == 2) begin : ram_2k_generate
//
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b00000000000000000000000000000000000, address[11]};
assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b = {2'b00, data_out_b[33:32], 16'b0000000000000000, data_out_b[15:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b = {2'b00, jtag_din[17:16], 16'b0000000000000000, jtag_din[15:0]};
assign address_b = {1'b1, jtag_addr[10:0], 4'b1111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'hD0011010D0011008D0011004D0011002D0011001D00B1000D0081000D00010FF),
.INIT_01 (256'h000000009001D101D10C910920198001D0011000D0011080D0011040D0011020),
.INIT_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h201A000000000000000000000000000000000000000000000000000000000000),
.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000000000000000000000000000000000000000000000000A8A888888888888),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h8000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // akv7;
//
end // ram_2k_generate;
endgenerate
//
//
// JTAG Loader
//
generate
if (C_JTAG_LOADER_ENABLE == 1) begin: instantiate_loader
jtag_loader_6 #( .C_FAMILY (C_FAMILY),
.C_NUM_PICOBLAZE (1),
.C_JTAG_LOADER_ENABLE (C_JTAG_LOADER_ENABLE),
.C_BRAM_MAX_ADDR_WIDTH (BRAM_ADDRESS_WIDTH),
.C_ADDR_WIDTH_0 (BRAM_ADDRESS_WIDTH))
jtag_loader_6_inst(.picoblaze_reset (rdl_bus),
.jtag_en (jtag_en),
.jtag_din (jtag_din),
.jtag_addr (jtag_addr[BRAM_ADDRESS_WIDTH-1 : 0]),
.jtag_clk (jtag_clk),
.jtag_we (jtag_we),
.jtag_dout_0 (jtag_dout),
.jtag_dout_1 (jtag_dout), // ports 1-7 are not used
.jtag_dout_2 (jtag_dout), // in a 1 device debug
.jtag_dout_3 (jtag_dout), // session. However, Synplify
.jtag_dout_4 (jtag_dout), // etc require all ports are
.jtag_dout_5 (jtag_dout), // connected
.jtag_dout_6 (jtag_dout),
.jtag_dout_7 (jtag_dout));
end //instantiate_loader
endgenerate
//
//
endmodule |
module jtag_loader_6 (picoblaze_reset, jtag_en, jtag_din, jtag_addr, jtag_clk, jtag_we, jtag_dout_0, jtag_dout_1, jtag_dout_2, jtag_dout_3, jtag_dout_4, jtag_dout_5, jtag_dout_6, jtag_dout_7);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "V6";
parameter integer C_NUM_PICOBLAZE = 1;
parameter integer C_BRAM_MAX_ADDR_WIDTH = 10;
parameter integer C_PICOBLAZE_INSTRUCTION_DATA_WIDTH = 18;
parameter integer C_JTAG_CHAIN = 2;
parameter [4:0] C_ADDR_WIDTH_0 = 10;
parameter [4:0] C_ADDR_WIDTH_1 = 10;
parameter [4:0] C_ADDR_WIDTH_2 = 10;
parameter [4:0] C_ADDR_WIDTH_3 = 10;
parameter [4:0] C_ADDR_WIDTH_4 = 10;
parameter [4:0] C_ADDR_WIDTH_5 = 10;
parameter [4:0] C_ADDR_WIDTH_6 = 10;
parameter [4:0] C_ADDR_WIDTH_7 = 10;
//
output [C_NUM_PICOBLAZE-1:0] picoblaze_reset;
output [C_NUM_PICOBLAZE-1:0] jtag_en;
output [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din;
output [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr;
output jtag_clk ;
output jtag_we;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7;
//
//
wire [2:0] num_picoblaze;
wire [4:0] picoblaze_instruction_data_width;
//
wire drck;
wire shift_clk;
wire shift_din;
wire shift_dout;
wire shift;
wire capture;
//
reg control_reg_ce;
reg [C_NUM_PICOBLAZE-1:0] bram_ce;
wire [C_NUM_PICOBLAZE-1:0] bus_zero;
wire [C_NUM_PICOBLAZE-1:0] jtag_en_int;
wire [7:0] jtag_en_expanded;
reg [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr_int;
reg [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_din;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_dout;
reg [7:0] control_dout_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] bram_dout_int;
reg jtag_we_int;
wire jtag_clk_int;
wire bram_ce_valid;
reg din_load;
//
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7_masked;
reg [C_NUM_PICOBLAZE-1:0] picoblaze_reset_int;
//
initial picoblaze_reset_int = 0;
//
genvar i;
//
generate
for (i = 0; i <= C_NUM_PICOBLAZE-1; i = i+1)
begin : npzero_loop
assign bus_zero[i] = 1'b0;
end
endgenerate
//
generate
//
if (C_JTAG_LOADER_ENABLE == 1)
begin : jtag_loader_gen
//
// Insert BSCAN primitive for target device architecture.
//
if (C_FAMILY == "S6")
begin : BSCAN_SPARTAN6_gen
BSCAN_SPARTAN6 # (.JTAG_CHAIN (C_JTAG_CHAIN))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "V6")
begin : BSCAN_VIRTEX6_gen
BSCAN_VIRTEX6 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "7S")
begin : BSCAN_7SERIES_gen
BSCANE2 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
// Insert clock buffer to ensure reliable shift operations.
//
BUFG upload_clock (.I (drck), .O (shift_clk));
//
//
// Shift Register
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
control_reg_ce <= shift_din;
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[0] <= control_reg_ce;
end
end
//
for (i = 0; i <= C_NUM_PICOBLAZE-2; i = i+1)
begin : loop0
if (C_NUM_PICOBLAZE > 1) begin
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[i+1] <= bram_ce[i];
end
end
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_we_int <= bram_ce[C_NUM_PICOBLAZE-1];
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[0] <= jtag_we_int;
end
end
//
for (i = 0; i <= C_BRAM_MAX_ADDR_WIDTH-2; i = i+1)
begin : loop1
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[i+1] <= jtag_addr_int[i];
end
end
end
//
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[0] <= bram_dout_int[0];
end
else if (shift == 1'b1) begin
jtag_din_int[0] <= jtag_addr_int[C_BRAM_MAX_ADDR_WIDTH-1];
end
end
//
for (i = 0; i <= C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2; i = i+1)
begin : loop2
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[i+1] <= bram_dout_int[i+1];
end
if (shift == 1'b1) begin
jtag_din_int[i+1] <= jtag_din_int[i];
end
end
end
//
assign shift_dout = jtag_din_int[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1];
//
//
always @ (bram_ce or din_load or capture or bus_zero or control_reg_ce) begin
if ( bram_ce == bus_zero ) begin
din_load <= capture & control_reg_ce;
end else begin
din_load <= capture;
end
end
//
//
// Control Registers
//
assign num_picoblaze = C_NUM_PICOBLAZE-3'h1;
assign picoblaze_instruction_data_width = C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-5'h01;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b0 && control_reg_ce == 1'b1) begin
case (jtag_addr_int[3:0])
0 : // 0 = version - returns (7:4) illustrating number of PB
// and [3:0] picoblaze instruction data width
control_dout_int <= {num_picoblaze, picoblaze_instruction_data_width};
1 : // 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) begin
control_dout_int <= {picoblaze_reset_int[0], 2'b00, C_ADDR_WIDTH_0-5'h01};
end else begin
control_dout_int <= 8'h00;
end
2 : // 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) begin
control_dout_int <= {picoblaze_reset_int[1], 2'b00, C_ADDR_WIDTH_1-5'h01};
end else begin
control_dout_int <= 8'h00;
end
3 : // 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) begin
control_dout_int <= {picoblaze_reset_int[2], 2'b00, C_ADDR_WIDTH_2-5'h01};
end else begin
control_dout_int <= 8'h00;
end
4 : // 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) begin
control_dout_int <= {picoblaze_reset_int[3], 2'b00, C_ADDR_WIDTH_3-5'h01};
end else begin
control_dout_int <= 8'h00;
end
5: // 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) begin
control_dout_int <= {picoblaze_reset_int[4], 2'b00, C_ADDR_WIDTH_4-5'h01};
end else begin
control_dout_int <= 8'h00;
end
6 : // 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) begin
control_dout_int <= {picoblaze_reset_int[5], 2'b00, C_ADDR_WIDTH_5-5'h01};
end else begin
control_dout_int <= 8'h00;
end
7 : // 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) begin
control_dout_int <= {picoblaze_reset_int[6], 2'b00, C_ADDR_WIDTH_6-5'h01};
end else begin
control_dout_int <= 8'h00;
end
8 : // 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) begin
control_dout_int <= {picoblaze_reset_int[7], 2'b00, C_ADDR_WIDTH_7-5'h01};
end else begin
control_dout_int <= 8'h00;
end
15 : control_dout_int <= C_BRAM_MAX_ADDR_WIDTH -1;
default : control_dout_int <= 8'h00;
//
endcase
end else begin
control_dout_int <= 8'h00;
end
end
//
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8] = control_dout_int;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b1 && control_reg_ce == 1'b1) begin
picoblaze_reset_int[C_NUM_PICOBLAZE-1:0] <= control_din[C_NUM_PICOBLAZE-1:0];
end
end
//
//
// Assignments
//
if (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8) begin
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9:0] = 10'h000;
end
//
// Qualify the blockram CS signal with bscan select output
assign jtag_en_int = (bram_ce_valid) ? bram_ce : bus_zero;
//
assign jtag_en_expanded[C_NUM_PICOBLAZE-1:0] = jtag_en_int;
//
for (i = 7; i >= C_NUM_PICOBLAZE; i = i-1)
begin : loop4
if (C_NUM_PICOBLAZE < 8) begin : jtag_en_expanded_gen
assign jtag_en_expanded[i] = 1'b0;
end
end
//
assign bram_dout_int = control_dout | jtag_dout_0_masked | jtag_dout_1_masked | jtag_dout_2_masked | jtag_dout_3_masked | jtag_dout_4_masked | jtag_dout_5_masked | jtag_dout_6_masked | jtag_dout_7_masked;
//
assign control_din = jtag_din_int;
//
assign jtag_dout_0_masked = (jtag_en_expanded[0]) ? jtag_dout_0 : 18'h00000;
assign jtag_dout_1_masked = (jtag_en_expanded[1]) ? jtag_dout_1 : 18'h00000;
assign jtag_dout_2_masked = (jtag_en_expanded[2]) ? jtag_dout_2 : 18'h00000;
assign jtag_dout_3_masked = (jtag_en_expanded[3]) ? jtag_dout_3 : 18'h00000;
assign jtag_dout_4_masked = (jtag_en_expanded[4]) ? jtag_dout_4 : 18'h00000;
assign jtag_dout_5_masked = (jtag_en_expanded[5]) ? jtag_dout_5 : 18'h00000;
assign jtag_dout_6_masked = (jtag_en_expanded[6]) ? jtag_dout_6 : 18'h00000;
assign jtag_dout_7_masked = (jtag_en_expanded[7]) ? jtag_dout_7 : 18'h00000;
//
assign jtag_en = jtag_en_int;
assign jtag_din = jtag_din_int;
assign jtag_addr = jtag_addr_int;
assign jtag_clk = jtag_clk_int;
assign jtag_we = jtag_we_int;
assign picoblaze_reset = picoblaze_reset_int;
//
end
endgenerate
//
endmodule |
module sky130_fd_sc_ms__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule |
module win_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef SIMULATION
altsyncram_component.init_file = "../../dgn/rtl/altera/win_ram.mif",
`else //for syn
altsyncram_component.init_file = "../rtl/altera/win_ram.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module uart_v3 #(
parameter DEFAULT_BAUDRATE = 115200,
parameter STOP_BITS = 1
)(
input clk,
input rst,
output reg tx,
input transmit,
input [7:0] tx_byte,
output is_transmitting,
input rx,
output reg rx_error,
output reg [7:0] rx_byte,
output reg received,
output is_receiving,
output [31:0] prescaler, //output this so the user can use it to calculate a baudrate
input set_clock_div,
input [31:0] user_clock_div,
output [31:0] default_clock_div
);
//Local Parameters
//Receive State Machine
localparam RX_IDLE = 0;
localparam RX_CHECK_START = 1;
localparam RX_READING = 2;
localparam RX_CHECK_STOP = 3;
localparam RX_DELAY_RESTART = 4;
localparam RX_ERROR = 5;
localparam RX_RECEIVED = 6;
//Transmit State Machine
localparam TX_IDLE = 0;
localparam TX_SENDING = 1;
localparam TX_FINISHED = 2;
//Registers/Wires
//Receive Register
reg [2:0] rx_state;
reg [3:0] rx_bit_count;
reg [7:0] rx_data;
reg [31:0] rx_clock_div;
reg [31:0] rx_clock_div_count;
reg [31:0] rx_prescaler_count;
//Transmit Register
reg [2:0] tx_state;
reg [3:0] tx_bit_count;
reg [7:0] tx_data;
reg [31:0] tx_clock_div;
reg [31:0] tx_prescaler_count;
reg [31:0] tx_clock_div_count;
//Submodules
//Asynchronous Logic
assign prescaler = `CLOCK_RATE / (`PRESCALER_COUNT);
assign default_clock_div = `CLOCK_RATE / (`PRESCALER_COUNT * DEFAULT_BAUDRATE);
assign is_receiving = (rx_state != RX_IDLE);
assign is_transmitting = (tx_state != TX_IDLE);
//Synchronous Logic
always @ (posedge clk) begin
if (rst || set_clock_div) begin
rx_state <= RX_IDLE;
rx_bit_count <= 0;
rx_clock_div_count <= 0;
rx_clock_div <= `FULL_PERIOD;
rx_data <= 0;
rx_byte <= 0;
rx_error <= 0;
if (set_clock_div) begin
rx_clock_div <= user_clock_div;
end
else begin
rx_clock_div <= default_clock_div;
end
end
else begin
//Strobed
received <= 0;
rx_error <= 0;
//have we passed the clock divider count
rx_clock_div_count <= rx_clock_div_count + 1;
if (rx_clock_div_count >= rx_clock_div) begin
rx_prescaler_count <= rx_prescaler_count + 1;
rx_clock_div_count <= 0;
end
//Receive State Machine
case (rx_state)
RX_IDLE: begin
//--*__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
rx_prescaler_count <= 0;
rx_data <= 0;
rx_bit_count <= 0;
if (!rx) begin
rx_state <= RX_CHECK_START;
end
else begin
rx_clock_div_count <= 0;
end
end
RX_CHECK_START: begin
//--|__*__|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
if (rx_prescaler_count >= (`HALF_PERIOD)) begin
rx_prescaler_count <= 0;
if (!rx) begin
rx_state <= RX_READING;
end
else begin
rx_state <= RX_IDLE;
end
end
end
RX_READING: begin
//--|__ __|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|-- --
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
rx_data <= {rx, rx_data[7:1]};
rx_prescaler_count <= 0;
if (rx_bit_count >= 7) begin
//Finished
rx_state <= RX_CHECK_STOP;
end
else begin
rx_bit_count <= rx_bit_count + 1;
end
end
end
RX_CHECK_STOP: begin
//--|__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|--*--
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
if (rx) begin
rx_byte <= rx_data;
//$display ("FOUND DATA!!!: %h", rx_data);
received <= 1;
rx_state <= RX_IDLE;
end
else begin
rx_error <= 1;
rx_state <= RX_IDLE;
end
end
end
default: begin
rx_state <= RX_IDLE;
end
endcase
end
end
always @ (posedge clk) begin
if (rst || set_clock_div) begin
tx <= 1;
tx_state <= TX_IDLE;
tx_data <= 0;
tx_bit_count <= 0;
tx_clock_div_count <= 0;
tx_prescaler_count <= 0;
if (set_clock_div) begin
tx_clock_div <= user_clock_div;
end
else begin
tx_clock_div <= default_clock_div;
end
end
else begin
//have we passed the clock divider count
tx_clock_div_count <= tx_clock_div_count + 1;
if (tx_clock_div_count >= tx_clock_div) begin
tx_prescaler_count <= tx_prescaler_count + 1;
tx_clock_div_count <= 0;
end
case (tx_state)
TX_IDLE: begin
tx <= 1;
tx_clock_div_count <= 1;
tx_prescaler_count <= 0;
if (transmit) begin
tx <= 0;
tx_data <= tx_byte;
$display("UART_V3: sending 0x%h \"%s\"", tx_byte, tx_byte);
tx_bit_count <= 0;
tx_state <= TX_SENDING;
end
end
TX_SENDING: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_prescaler_count <= 0;
if (tx_bit_count < 8) begin
tx <= tx_data[0];
tx_data <= {1'b0, tx_data[7:1]};
tx_bit_count <= tx_bit_count + 1;
end
else begin
tx <= 1;
tx_state <= TX_FINISHED;
end
end
end
TX_FINISHED: begin
if (tx_prescaler_count >= (STOP_BITS * `FULL_PERIOD)) begin
tx_state <= TX_IDLE;
end
end
default: begin
tx_state <= TX_IDLE;
end
endcase
end
end
endmodule |
module axis_switch #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// tdest signal width
// must be wide enough to uniquely address outputs
parameter DEST_WIDTH = $clog2(M_COUNT),
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// Output interface routing base tdest selection
// Concatenate M_COUNT DEST_WIDTH sized constants
// Port selected if M_BASE <= tdest <= M_TOP
// set to zero for default routing with tdest MSBs as port index
parameter M_BASE = 0,
// Output interface routing top tdest selection
// Concatenate M_COUNT DEST_WIDTH sized constants
// Port selected if M_BASE <= tdest <= M_TOP
// set to zero to inherit from M_BASE
parameter M_TOP = 0,
// Interface connection control
// M_COUNT concatenated fields of S_COUNT bits
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
// Input interface register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter S_REG_TYPE = 0,
// Output interface register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_REG_TYPE = 2,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
input wire [M_COUNT-1:0] m_axis_tready,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter CL_M_COUNT = $clog2(M_COUNT);
integer i, j;
// check configuration
initial begin
if (DEST_WIDTH < CL_M_COUNT) begin
$error("Error: DEST_WIDTH too small for port count (instance %m)");
$finish;
end
if (M_BASE == 0) begin
// M_BASE is zero, route with tdest as port index
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x-%08x (connect mask %b)", i, i << (DEST_WIDTH-CL_M_COUNT), ((i+1) << (DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]);
end
end else if (M_TOP == 0) begin
// M_TOP is zero, assume equal to M_BASE
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]);
end
for (i = 0; i < M_COUNT; i = i + 1) begin
for (j = i+1; j < M_COUNT; j = j + 1) begin
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin
$display("%d: %08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH]);
$display("%d: %08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH]);
$error("Error: ranges overlap (instance %m)");
$finish;
end
end
end
end else begin
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]);
end
for (i = 0; i < M_COUNT; i = i + 1) begin
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
$error("Error: invalid range (instance %m)");
$finish;
end
end
for (i = 0; i < M_COUNT; i = i + 1) begin
for (j = i+1; j < M_COUNT; j = j + 1) begin
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[j*DEST_WIDTH +: DEST_WIDTH] && M_BASE[j*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
$display("%d: %08x-%08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH]);
$display("%d: %08x-%08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH], M_TOP[j*DEST_WIDTH +: DEST_WIDTH]);
$error("Error: ranges overlap (instance %m)");
$finish;
end
end
end
end
end
wire [S_COUNT*DATA_WIDTH-1:0] int_s_axis_tdata;
wire [S_COUNT*KEEP_WIDTH-1:0] int_s_axis_tkeep;
wire [S_COUNT-1:0] int_s_axis_tvalid;
wire [S_COUNT-1:0] int_s_axis_tready;
wire [S_COUNT-1:0] int_s_axis_tlast;
wire [S_COUNT*ID_WIDTH-1:0] int_s_axis_tid;
wire [S_COUNT*DEST_WIDTH-1:0] int_s_axis_tdest;
wire [S_COUNT*USER_WIDTH-1:0] int_s_axis_tuser;
wire [S_COUNT*M_COUNT-1:0] int_axis_tvalid;
wire [M_COUNT*S_COUNT-1:0] int_axis_tready;
generate
genvar m, n;
for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
// decoding
reg [CL_M_COUNT-1:0] select_reg = 0, select_next;
reg drop_reg = 1'b0, drop_next;
reg select_valid_reg = 1'b0, select_valid_next;
integer k;
always @* begin
select_next = select_reg;
drop_next = drop_reg && !(int_s_axis_tvalid[m] && int_s_axis_tready[m] && int_s_axis_tlast[m]);
select_valid_next = select_valid_reg && !(int_s_axis_tvalid[m] && int_s_axis_tready[m] && int_s_axis_tlast[m]);
if (int_s_axis_tvalid[m] && !select_valid_reg && !drop_reg) begin
select_next = 0;
select_valid_next = 1'b0;
drop_next = 1'b1;
for (k = 0; k < M_COUNT; k = k + 1) begin
if (M_BASE == 0) begin
if (M_COUNT == 1) begin
// M_BASE is zero with only one output port, ignore tdest
select_next = 0;
select_valid_next = 1'b1;
drop_next = 1'b0;
end else begin
// M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index
if (int_s_axis_tdest[m*DEST_WIDTH+(DEST_WIDTH-CL_M_COUNT) +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end
end else if (M_TOP == 0) begin
// M_TOP is zero, assume equal to M_BASE
if (int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] == M_BASE[k*DEST_WIDTH +: DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end else begin
if (int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] >= M_BASE[k*DEST_WIDTH +: DEST_WIDTH] && int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[k*DEST_WIDTH +: DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end
end
end
end
always @(posedge clk) begin
if (rst) begin
select_valid_reg <= 1'b0;
end else begin
select_valid_reg <= select_valid_next;
end
select_reg <= select_next;
drop_reg <= drop_next;
end
// forwarding
assign int_axis_tvalid[m*M_COUNT +: M_COUNT] = (int_s_axis_tvalid[m] && select_valid_reg && !drop_reg) << select_reg;
assign int_s_axis_tready[m] = int_axis_tready[select_reg*S_COUNT+m] || drop_reg;
// S side register
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(S_REG_TYPE)
)
reg_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata[m*DATA_WIDTH +: DATA_WIDTH]),
.s_axis_tkeep(s_axis_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH]),
.s_axis_tvalid(s_axis_tvalid[m]),
.s_axis_tready(s_axis_tready[m]),
.s_axis_tlast(s_axis_tlast[m]),
.s_axis_tid(s_axis_tid[m*ID_WIDTH +: ID_WIDTH]),
.s_axis_tdest(s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH]),
.s_axis_tuser(s_axis_tuser[m*USER_WIDTH +: USER_WIDTH]),
// AXI output
.m_axis_tdata(int_s_axis_tdata[m*DATA_WIDTH +: DATA_WIDTH]),
.m_axis_tkeep(int_s_axis_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH]),
.m_axis_tvalid(int_s_axis_tvalid[m]),
.m_axis_tready(int_s_axis_tready[m]),
.m_axis_tlast(int_s_axis_tlast[m]),
.m_axis_tid(int_s_axis_tid[m*ID_WIDTH +: ID_WIDTH]),
.m_axis_tdest(int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH]),
.m_axis_tuser(int_s_axis_tuser[m*USER_WIDTH +: USER_WIDTH])
);
end // s_ifaces
for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
// arbitration
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
// mux
wire [DATA_WIDTH-1:0] s_axis_tdata_mux = int_s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] s_axis_tkeep_mux = int_s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire s_axis_tvalid_mux = int_axis_tvalid[grant_encoded*M_COUNT+n] && grant_valid;
wire s_axis_tready_mux;
wire s_axis_tlast_mux = int_s_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] s_axis_tid_mux = int_s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] s_axis_tdest_mux = int_s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] s_axis_tuser_mux = int_s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
assign int_axis_tready[n*S_COUNT +: S_COUNT] = (grant_valid && s_axis_tready_mux) << grant_encoded;
for (m = 0; m < S_COUNT; m = m + 1) begin
assign request[m] = int_axis_tvalid[m*M_COUNT+n] && !grant[m];
assign acknowledge[m] = grant[m] && int_axis_tvalid[m*M_COUNT+n] && s_axis_tlast_mux && s_axis_tready_mux;
end
// M side register
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(M_REG_TYPE)
)
reg_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata_mux),
.s_axis_tkeep(s_axis_tkeep_mux),
.s_axis_tvalid(s_axis_tvalid_mux),
.s_axis_tready(s_axis_tready_mux),
.s_axis_tlast(s_axis_tlast_mux),
.s_axis_tid(s_axis_tid_mux),
.s_axis_tdest(s_axis_tdest_mux),
.s_axis_tuser(s_axis_tuser_mux),
// AXI output
.m_axis_tdata(m_axis_tdata[n*DATA_WIDTH +: DATA_WIDTH]),
.m_axis_tkeep(m_axis_tkeep[n*KEEP_WIDTH +: KEEP_WIDTH]),
.m_axis_tvalid(m_axis_tvalid[n]),
.m_axis_tready(m_axis_tready[n]),
.m_axis_tlast(m_axis_tlast[n]),
.m_axis_tid(m_axis_tid[n*ID_WIDTH +: ID_WIDTH]),
.m_axis_tdest(m_axis_tdest[n*DEST_WIDTH +: DEST_WIDTH]),
.m_axis_tuser(m_axis_tuser[n*USER_WIDTH +: USER_WIDTH])
);
end // m_ifaces
endgenerate
endmodule |
module blk_mem_gen_inputMem(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [16 : 0] addra;
input [7 : 0] dina;
input clkb;
input [16 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(17),
.C_ADDRB_WIDTH(17),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(131072),
.C_READ_DEPTH_B(131072),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(131072),
.C_WRITE_DEPTH_B(131072),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule |
module primogen #(
parameter WIDTH_LOG = 4
) (clk, go, rst, ready, error, res);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input clk;
input go;
input rst;
output reg ready;
output reg error;
output reg [HI:0] res;
localparam MAX = {WIDTH{1'b1}};
// Note that incrementing address width
// by 1 bit would double BRAM consumption
localparam ADDR_WIDTH = 8;
localparam ADDR_HI = ADDR_WIDTH - 1;
`ifdef SIM
// Use reduced RAM for tests
localparam ADDR_MAX = 4'd8;
`else
localparam ADDR_MAX = {ADDR_WIDTH{1'b1}};
`endif
localparam XW = {WIDTH{1'bx}};
localparam X7 = 7'bx;
localparam XA = {ADDR_WIDTH{1'bx}};
localparam READY = 4'd0;
localparam ERROR = 4'd1;
localparam NEXT_CANDIDATE = 4'd2;
localparam NEXT_PRIME_DIVISOR = 4'd3;
localparam PRIME_DIVIDE_START = 4'd4; // TODO: can we get rid of this?
localparam PRIME_DIVIDE_WAIT = 4'd5;
localparam NEXT_DIVISOR = 4'd6;
localparam DIVIDE_START = 4'd7; // TODO: can we get rid of this?
localparam DIVIDE_WAIT = 4'd8;
// Combinational logic for outputs
reg [HI:0] next_res;
wire next_ready;
wire next_error;
// State
reg [3:0] state;
reg [HI:0] res_squared;
// And it's combinational logic
reg [3:0] next_state;
reg [HI:0] next_res_squared;
// Submodule inputs
reg [HI:0] div;
reg [HI:0] div_squared;
reg div_go;
reg [ADDR_HI:0] addr;
reg [ADDR_HI:0] naddrs;
reg write_en;
// And their combinational logic
reg [HI:0] next_div;
reg [HI:0] next_div_squared;
reg next_div_go;
reg [ADDR_HI:0] next_addr;
reg [ADDR_HI:0] next_naddrs;
reg next_write_en;
// Submodule outputs
wire div_ready;
wire div_error;
wire [HI:0] rem;
wire [HI:0] dout;
wire [HI:0] dout_squared;
// We store both primes and their squares
ram #(.WIDTH(2*WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) primes(
.din({res, res_squared}),
.addr(addr),
.write_en(write_en),
.clk(clk),
.dout({dout, dout_squared})
);
divrem #(.WIDTH_LOG(WIDTH_LOG)) dr(
.clk(clk),
.go(div_go),
.rst(rst),
.num(res),
.den(div),
.ready(div_ready),
.error(div_error),
.rem(rem));
assign next_ready = next_state == READY || next_state == ERROR;
assign next_error = next_state == ERROR;
always @* begin
next_state = state;
next_res = res;
next_res_squared = res_squared;
next_div = div;
next_div_squared = div_squared;
next_div_go = 0;
next_addr = addr;
next_naddrs = naddrs;
next_write_en = 0;
case (state)
READY:
begin
if (go) begin
next_state = NEXT_CANDIDATE;
next_addr = 0;
end
end
ERROR:
; // Do nothing
NEXT_CANDIDATE: // TODO: can probably be merged with NEXT_PRIME_DIVISOR
begin
// Search for next prime
case (res)
1:
begin
next_res = 8'd2;
next_res_squared = 8'd4;
end
2:
begin
next_res = 8'd3;
next_res_squared = 8'd9;
end
default:
begin
next_res = res + 8'd2;
// Square is subject to overflow
if (next_res < (1'd1 << (WIDTH / 2))) begin
next_res_squared = res_squared + (res << 2) + 8'd4;
`assert_lt(res_squared, next_res_squared);
end else
next_res_squared = MAX;
end
endcase
next_addr = 0;
// Check for overflow
next_state = next_res > res ? NEXT_PRIME_DIVISOR : ERROR;
end
NEXT_PRIME_DIVISOR:
if (naddrs == 0 || dout_squared > res) begin
next_state = READY;
// Store found prime
if (res != 1'd1 && res != 2'd2) begin
next_write_en = 1'd1;
next_addr = naddrs;
next_naddrs = naddrs + 1'd1;
end
end else if (addr < naddrs) begin
next_state = PRIME_DIVIDE_START;
next_div = dout;
next_div_squared = dout_squared;
next_div_go = 1;
end else if (naddrs == ADDR_MAX) begin
// Prime table overflow => use slow check
next_state = NEXT_DIVISOR;
next_div = div + 8'd2;
next_div_squared = div_squared + (div << 2) + 8'd4;
`assert_lt(div_squared, next_div_squared);
end else begin
next_state = ERROR;
`unreachable;
end
PRIME_DIVIDE_START:
// Wait state to allow divrem to register inputs and update ready bit
next_state = PRIME_DIVIDE_WAIT;
PRIME_DIVIDE_WAIT:
if (div_error) begin
next_state = ERROR;
end else if (!div_ready)
; // Keep waiting
else if (rem == 0) begin
// Divisable => abort and try next candidate
next_state = NEXT_CANDIDATE;
next_addr = 0;
end else begin
// Not divisable => try next divisor
next_state = NEXT_PRIME_DIVISOR;
next_addr = addr + 1'd1;
end
NEXT_DIVISOR:
if (div_squared > res) begin
// None of potential divisors matched => number is prime!
next_state = READY;
end else begin
next_state = DIVIDE_START;
next_div_go = 1;
end
DIVIDE_START:
// Wait state to allow divrem to register inputs and update ready bit
next_state = DIVIDE_WAIT;
DIVIDE_WAIT:
if (div_error) begin
next_state = ERROR;
end else if (!div_ready)
; // Keep waiting
else if (rem == 0) begin
// Divisable => abort and try next candidate
next_state = NEXT_CANDIDATE;
end else begin
// Not divisable => try next divisor
case (div)
2:
begin
next_div = 8'd3;
next_div_squared = 8'd9;
end
7:
begin
next_div = 8'd11;
next_div_squared = 8'd121;
end
// 3, 5 and 11 are covered by default branch
default:
begin
next_div = div + 8'd2;
next_div_squared = div_squared + (div << 2) + 8'd4;
end
endcase
// div * div < res so shouldn't overflow
`assert_lt(next_div, div);
// Clamp square as it's subject to overflow
// TODO: this may not be necessary
if (next_div_squared <= div_squared)
next_div_squared = MAX;
next_state = NEXT_DIVISOR;
end
default:
begin
next_state = 3'bx;
next_res = XW;
next_res_squared = XW;
next_div = XW;
next_div_squared = XW;
next_div_go = 1'bx;
next_addr = XA;
end
endcase
end
always @(posedge clk)
if (rst) begin
// Start by outputting the very first prime...
state <= READY;
res_squared <= 1;
res <= 1;
ready <= 1;
error <= 0;
div <= XW;
div_squared <= XW;
div_go <= 0;
addr <= XA;
naddrs <= 0;
write_en <= 0;
end else begin
state <= next_state;
res_squared <= next_res_squared;
res <= next_res;
ready <= next_ready;
error <= next_error;
div <= next_div;
div_squared <= next_div_squared;
div_go <= next_div_go;
addr <= next_addr;
naddrs <= next_naddrs;
write_en <= next_write_en;
end
`ifdef SIM
always @(posedge clk) begin
// Precondition: core signals must always be valid
`assert_nox(rst);
`assert_nox(clk);
if (!rst) begin
// Invariant: output looks like prime
`assert(res[0] || (res == 2));
end
end
`endif
`ifdef SIM
// initial
// $monitor("%t: clk=%b, go=%b, state=%h, res=%0d, res_squared=%0d, addr=%0d, next_addr=%0d, naddrs=%0d, write_en=%0d, div=%0d, div_squared=%0d, div_go=%b, rem=%0d, div_ready=%b, dout=%0d, dout_squared=%0d", $time, clk, go, state, res, res_squared, addr, next_addr, naddrs, write_en, div, div_squared, div_go, rem, div_ready, dout, dout_squared);
`endif
endmodule |
module rf_2p_be (
clka ,
cena_i ,
addra_i ,
dataa_o ,
clkb ,
cenb_i ,
wenb_i ,
addrb_i ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=8;
parameter Byte_Width=(Word_Width>>3);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input [Addr_Width-1:0] addra_i; // address input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input [Byte_Width-1:0] wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_w;
wire [Word_Width-1:0] datab_m;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if (!cena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = dataa_r;
// -- B Port --//
assign datab_m = mem_array[addrb_i];
genvar j;
generate
for (j=0; j<Byte_Width; j=j+1) begin:j_n
always@(*) begin
datab_w[(j+1)*8-1:j*8] = wenb_i[j] ? datab_m[(j+1)*8-1:j*8]:datab_i[(j+1)*8-1:j*8];
end
end
endgenerate
always @(posedge clkb) begin
if(!cenb_i && !(&wenb_i))
mem_array[addrb_i] <= datab_w;
end
endmodule |
module zap_core #(
// Number of branch predictor entries.
parameter [31:0] BP_ENTRIES = 1024,
// Depth of FIFO.
parameter [31:0] FIFO_DEPTH = 4
)
(
// ------------------------------------------------
// Clock and reset. Reset is synchronous.
// ------------------------------------------------
input wire i_clk,
input wire i_reset,
// -------------------------------------------------
// Wishbone memory access for data.
// -------------------------------------------------
output wire o_data_wb_we,
output wire o_data_wb_cyc,
output wire o_data_wb_stb,
output wire[31:0] o_data_wb_adr,
input wire i_data_wb_ack,
input wire i_data_wb_err,
input wire [31:0] i_data_wb_dat,
output wire [31:0] o_data_wb_dat,
output wire [3:0] o_data_wb_sel,
// Next state stuff for Wishbone data.
output wire o_data_wb_we_nxt,
output wire o_data_wb_cyc_nxt,
output wire o_data_wb_stb_nxt,
output wire [31:0] o_data_wb_dat_nxt,
output wire [3:0] o_data_wb_sel_nxt,
output wire [31:0] o_data_wb_adr_nxt,
// Force user view.
output wire o_mem_translate,
// --------------------------------------------------
// Interrupts. Active high.
// --------------------------------------------------
input wire i_fiq, // FIQ signal.
input wire i_irq, // IRQ signal.
// ---------------------------------------------------
// Wishbone instruction access ports.
// ---------------------------------------------------
output wire [31:0] o_instr_wb_adr, // Code address.
output wire o_instr_wb_cyc, // Always 1.
output wire o_instr_wb_stb, // Always 1.
output wire o_instr_wb_we, // Always 0.
input wire [31:0] i_instr_wb_dat, // A 32-bit ZAP instruction.
input wire i_instr_wb_ack, // Instruction available.
input wire i_instr_wb_err, // Instruction abort fault. Given with ack = 1.
output wire [3:0] o_instr_wb_sel, // wishbone byte select.
// Instruction wishbone nxt ports.
output wire [31:0] o_instr_wb_adr_nxt,
// Determines user or supervisory mode. Cache must use this for VM.
output wire [31:0] o_cpsr,
// -----------------------------------------------------
// For MMU/cache connectivity.
// -----------------------------------------------------
input wire [31:0] i_fsr,
input wire [31:0] i_far,
output wire [31:0] o_dac,
output wire [31:0] o_baddr,
output wire o_mmu_en,
output wire [1:0] o_sr,
output wire [7:0] o_pid,
output wire o_dcache_inv,
output wire o_icache_inv,
output wire o_dcache_clean,
output wire o_icache_clean,
output wire o_dtlb_inv,
output wire o_itlb_inv,
output wire o_dcache_en,
output wire o_icache_en,
input wire i_dcache_inv_done,
input wire i_icache_inv_done,
input wire i_dcache_clean_done,
input wire i_icache_clean_done,
input wire i_icache_err2,
input wire i_dcache_err2
);
// ----------------------------------------------------------------------------
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
localparam ARCH_REGS = 32;
localparam ALU_OPS = 64;
localparam SHIFT_OPS = 8;
localparam PHY_REGS = TOTAL_PHY_REGS;
localparam FLAG_WDT = 32;
// ----------------------------------------------------------------------------
// Low Bandwidth Coprocessor (COP) I/F to CP15 control block.
wire copro_done; // COP done.
wire copro_dav; // COP command valid.
wire [31:0] copro_word; // COP command.
wire copro_reg_en; // COP controls registers.
wire [$clog2(PHY_REGS)-1:0] copro_reg_wr_index;// Reg. file write index.
wire [$clog2(PHY_REGS)-1:0] copro_reg_rd_index;// Reg. file read index.
wire [31:0] copro_reg_wr_data; // Reg. file write data.
wire [31:0] copro_reg_rd_data; // Reg. file read data.
wire reset; // Tied to i_reset.
wire shelve; // From writeback.
wire fiq; // Tied to FIQ.
wire irq; // Tied to IRQ.
// Clear and stall signals.
wire stall_from_decode;
wire clear_from_alu;
wire stall_from_issue;
wire clear_from_writeback;
wire data_stall;
wire code_stall;
wire instr_valid;
wire pipeline_is_not_empty;
// Fetch
wire [31:0] fetch_instruction; // Instruction from the fetch unit.
wire fetch_valid; // Instruction valid from the fetch unit.
wire fetch_instr_abort; // abort indicator.
wire [31:0] fetch_pc_plus_8_ff; // PC + 8 generated from the fetch unit.
wire [31:0] fetch_pc_ff; // PC generated from fetch unit.
wire [1:0] fetch_bp_state;
// FIFO.
wire [31:0] fifo_pc_plus_8;
wire fifo_valid;
wire fifo_instr_abort;
wire [31:0] fifo_instruction;
wire [1:0] fifo_bp_state;
// Predecode
wire [31:0] predecode_pc_plus_8;
wire [31:0] predecode_pc;
wire predecode_irq;
wire predecode_fiq;
wire predecode_abt;
wire [39:0] predecode_inst;
wire predecode_val;
wire predecode_force32;
wire predecode_und;
wire [1:0] predecode_taken;
// Compressed decoder.
wire thumb_irq;
wire thumb_fiq;
wire thumb_iabort;
wire [34:0] thumb_instruction;
wire thumb_valid;
wire thumb_und;
wire thumb_force32;
wire [1:0] thumb_bp_state;
wire [31:0] thumb_pc_ff;
wire [31:0] thumb_pc_plus_8_ff;
// Decode
wire [3:0] decode_condition_code;
wire [$clog2(PHY_REGS)-1:0] decode_destination_index;
wire [32:0] decode_alu_source_ff;
wire [$clog2(ALU_OPS)-1:0] decode_alu_operation_ff;
wire [32:0] decode_shift_source_ff;
wire [$clog2(SHIFT_OPS)-1:0] decode_shift_operation_ff;
wire [32:0] decode_shift_length_ff;
wire decode_flag_update_ff;
wire [$clog2(PHY_REGS)-1:0] decode_mem_srcdest_index_ff;
wire decode_mem_load_ff;
wire decode_mem_store_ff;
wire decode_mem_pre_index_ff;
wire decode_mem_unsigned_byte_enable_ff;
wire decode_mem_signed_byte_enable_ff;
wire decode_mem_signed_halfword_enable_ff;
wire decode_mem_unsigned_halfword_enable_ff;
wire decode_mem_translate_ff;
wire decode_irq_ff;
wire decode_fiq_ff;
wire decode_abt_ff;
wire decode_swi_ff;
wire [31:0] decode_pc_plus_8_ff;
wire [31:0] decode_pc_ff;
wire decode_switch_ff;
wire decode_force32_ff;
wire decode_und_ff;
wire clear_from_decode;
wire [31:0] pc_from_decode;
wire [1:0] decode_taken_ff;
// Issue
wire [$clog2(PHY_REGS)-1:0] issue_rd_index_0,
issue_rd_index_1,
issue_rd_index_2,
issue_rd_index_3;
wire [3:0] issue_condition_code_ff;
wire [$clog2(PHY_REGS)-1:0] issue_destination_index_ff;
wire [$clog2(ALU_OPS)-1:0] issue_alu_operation_ff;
wire [$clog2(SHIFT_OPS)-1:0] issue_shift_operation_ff;
wire issue_flag_update_ff;
wire [$clog2(PHY_REGS)-1:0] issue_mem_srcdest_index_ff;
wire issue_mem_load_ff;
wire issue_mem_store_ff;
wire issue_mem_pre_index_ff;
wire issue_mem_unsigned_byte_enable_ff;
wire issue_mem_signed_byte_enable_ff;
wire issue_mem_signed_halfword_enable_ff;
wire issue_mem_unsigned_halfword_enable_ff;
wire issue_mem_translate_ff;
wire issue_irq_ff;
wire issue_fiq_ff;
wire issue_abt_ff;
wire issue_swi_ff;
wire [31:0] issue_alu_source_value_ff;
wire [31:0] issue_shift_source_value_ff;
wire [31:0] issue_shift_length_value_ff;
wire [31:0] issue_mem_srcdest_value_ff;
wire [32:0] issue_alu_source_ff;
wire [32:0] issue_shift_source_ff;
wire [31:0] issue_pc_plus_8_ff;
wire [31:0] issue_pc_ff;
wire issue_shifter_disable_ff;
wire issue_switch_ff;
wire issue_force32_ff;
wire issue_und_ff;
wire [1:0] issue_taken_ff;
wire [$clog2(PHY_REGS)-1:0] rd_index_0;
wire [$clog2(PHY_REGS)-1:0] rd_index_1;
wire [$clog2(PHY_REGS)-1:0] rd_index_2;
wire [$clog2(PHY_REGS)-1:0] rd_index_3;
// Shift
wire [$clog2(PHY_REGS)-1:0] shifter_mem_srcdest_index_ff;
wire shifter_mem_load_ff;
wire shifter_mem_store_ff;
wire shifter_mem_pre_index_ff;
wire shifter_mem_unsigned_byte_enable_ff;
wire shifter_mem_signed_byte_enable_ff;
wire shifter_mem_signed_halfword_enable_ff;
wire shifter_mem_unsigned_halfword_enable_ff;
wire shifter_mem_translate_ff;
wire [3:0] shifter_condition_code_ff;
wire [$clog2(PHY_REGS)-1:0] shifter_destination_index_ff;
wire [$clog2(ALU_OPS)-1:0] shifter_alu_operation_ff;
wire shifter_nozero_ff;
wire shifter_flag_update_ff;
wire [31:0] shifter_mem_srcdest_value_ff;
wire [31:0] shifter_alu_source_value_ff;
wire [31:0] shifter_shifted_source_value_ff;
wire shifter_shift_carry_ff;
wire shifter_shift_sat_ff;
wire [31:0] shifter_pc_plus_8_ff;
wire [31:0] shifter_pc_ff;
wire shifter_irq_ff;
wire shifter_fiq_ff;
wire shifter_abt_ff;
wire shifter_swi_ff;
wire shifter_switch_ff;
wire shifter_force32_ff;
wire shifter_und_ff;
wire stall_from_shifter;
wire [1:0] shifter_taken_ff;
// ALU
wire [$clog2(SHIFT_OPS)-1:0] alu_shift_operation_ff;
wire [31:0] alu_alu_result_nxt;
wire [31:0] alu_alu_result_ff;
wire alu_abt_ff;
wire alu_irq_ff;
wire alu_fiq_ff;
wire alu_swi_ff;
wire alu_dav_ff;
wire alu_dav_nxt;
wire [31:0] alu_pc_plus_8_ff;
wire [31:0] pc_from_alu;
wire [$clog2(PHY_REGS)-1:0] alu_destination_index_ff;
wire [FLAG_WDT-1:0] alu_flags_ff;
wire [$clog2(PHY_REGS)-1:0] alu_mem_srcdest_index_ff;
wire alu_mem_load_ff;
wire alu_und_ff;
wire [31:0] alu_cpsr_nxt;
wire confirm_from_alu;
wire alu_sbyte_ff;
wire alu_ubyte_ff;
wire alu_shalf_ff;
wire alu_uhalf_ff;
wire [31:0] alu_address_ff;
wire [31:0] alu_address_nxt;
// Memory
wire [31:0] memory_alu_result_ff;
wire [$clog2(PHY_REGS)-1:0] memory_destination_index_ff;
wire [$clog2(PHY_REGS)-1:0] memory_mem_srcdest_index_ff;
wire memory_dav_ff;
wire [31:0] memory_pc_plus_8_ff;
wire memory_irq_ff;
wire memory_fiq_ff;
wire memory_swi_ff;
wire memory_instr_abort_ff;
wire memory_mem_load_ff;
wire [FLAG_WDT-1:0] memory_flags_ff;
wire [31:0] memory_mem_rd_data;
wire memory_und_ff;
wire [1:0] memory_data_abt_ff;
// Writeback
wire [31:0] rd_data_0;
wire [31:0] rd_data_1;
wire [31:0] rd_data_2;
wire [31:0] rd_data_3;
wire [31:0] cpsr_nxt, cpsr;
wire writeback_mask;
// Hijack interface - related to Writeback - ALU interaction.
wire wb_hijack;
wire [31:0] wb_hijack_op1;
wire [31:0] wb_hijack_op2;
wire wb_hijack_cin;
wire [31:0] alu_hijack_sum;
// Decompile chain for debugging.
wire [64*8-1:0] decode_decompile;
wire [64*8-1:0] issue_decompile;
wire [64*8-1:0] shifter_decompile;
wire [64*8-1:0] alu_decompile;
wire [64*8-1:0] memory_decompile;
wire [64*8-1:0] rb_decompile;
// ----------------------------------------------------------------------------
assign o_cpsr = alu_flags_ff;
assign o_data_wb_adr = {alu_address_ff[31:2], 2'd0};
assign o_data_wb_adr_nxt = {alu_address_nxt[31:2], 2'd0};
assign o_instr_wb_we = 1'd0;
assign o_instr_wb_sel = 4'b1111;
assign reset = i_reset;
assign irq = i_irq;
assign fiq = i_fiq;
assign data_stall = o_data_wb_stb && o_data_wb_cyc && !i_data_wb_ack;
assign code_stall = writeback_mask ? 1'd0 : ((!o_instr_wb_stb && !o_instr_wb_cyc) || !i_instr_wb_ack);
assign instr_valid = writeback_mask ? 1'd0 : (o_instr_wb_stb && o_instr_wb_cyc && i_instr_wb_ack & !shelve);
assign pipeline_is_not_empty = predecode_val ||
(decode_condition_code != NV) ||
(issue_condition_code_ff != NV) ||
(shifter_condition_code_ff!= NV) ||
alu_dav_ff ||
memory_dav_ff;
// ----------------------------------------------------------------------------
// =========================
// FETCH STAGE
// =========================
zap_fetch_main
#(
.BP_ENTRIES(BP_ENTRIES)
)
u_zap_fetch_main (
// Input.
.i_clk (i_clk),
.i_reset (reset),
.i_code_stall (code_stall),
.i_clear_from_writeback (clear_from_writeback),
.i_clear_from_decode (clear_from_decode),
.i_data_stall (1'd0),
.i_clear_from_alu (clear_from_alu),
.i_stall_from_shifter (1'd0),
.i_stall_from_issue (1'd0),
.i_stall_from_decode (1'd0),
.i_pc_ff (o_instr_wb_adr),
.i_instruction (writeback_mask ? 32'd0 : i_instr_wb_dat),
.i_valid (i_icache_err2 ? 1'd0 : instr_valid),
.i_instr_abort (i_icache_err2 ? 1'd0 : i_instr_wb_err),
.i_cpsr_ff_t (alu_flags_ff[T]),
// Output.
.o_instruction (fetch_instruction),
.o_valid (fetch_valid),
.o_instr_abort (fetch_instr_abort),
.o_pc_plus_8_ff (fetch_pc_plus_8_ff),
.o_pc_ff (fetch_pc_ff),
.i_confirm_from_alu (confirm_from_alu),
.i_pc_from_alu (shifter_pc_ff),
.i_taken (shifter_taken_ff),
.o_taken (fetch_bp_state)
);
// =========================
// FIFO to store commands.
// =========================
wire w_instr_wb_stb;
wire w_instr_wb_cyc;
zap_fifo #( .WDT(67), .DEPTH(FIFO_DEPTH) ) U_ZAP_FIFO (
.i_clk (i_clk),
.i_reset (i_reset),
.i_clear_from_writeback (clear_from_writeback),
.i_write_inhibit ( code_stall ),
.i_data_stall ( data_stall ),
.i_clear_from_alu (clear_from_alu),
.i_stall_from_shifter (stall_from_shifter),
.i_stall_from_issue (stall_from_issue),
.i_stall_from_decode (stall_from_decode),
.i_clear_from_decode (clear_from_decode),
.i_instr ({fetch_pc_plus_8_ff, fetch_instr_abort, fetch_instruction, fetch_bp_state}),
.i_valid (fetch_valid),
.o_instr ({fifo_pc_plus_8, fifo_instr_abort, fifo_instruction, fifo_bp_state}),
.o_valid (fifo_valid),
.o_wb_stb (w_instr_wb_stb),
.o_wb_cyc (w_instr_wb_cyc)
);
assign o_instr_wb_stb = writeback_mask ? 1'd0 : w_instr_wb_stb;
assign o_instr_wb_cyc = writeback_mask ? 1'd0 : w_instr_wb_cyc;
// =========================
// COMPRESSED DECODER STAGE
// =========================
zap_thumb_decoder_main u_zap_thumb_decoder (
.i_clk (i_clk),
.i_reset (i_reset),
.i_clear_from_writeback (clear_from_writeback),
.i_data_stall (data_stall),
.i_clear_from_alu (clear_from_alu),
.i_stall_from_shifter (stall_from_shifter),
.i_stall_from_issue (stall_from_issue),
.i_stall_from_decode (stall_from_decode),
.i_clear_from_decode (clear_from_decode),
.i_taken (fifo_bp_state),
.i_instruction (fifo_instruction),
.i_instruction_valid (fifo_valid),
.i_irq (fifo_valid ? irq && !alu_flags_ff[I] : 1'd0), // Pass interrupt only if mask = 0 and instruction exists.
.i_fiq (fifo_valid ? fiq && !alu_flags_ff[F] : 1'd0), // Pass interrupt only if mask = 0 and instruction exists.
.i_iabort (fifo_instr_abort),
.o_iabort (thumb_iabort),
.i_cpsr_ff_t (alu_flags_ff[T]),
.i_pc_ff (alu_flags_ff[T] ? fifo_pc_plus_8 - 32'd4 : fifo_pc_plus_8 - 32'd8),
.i_pc_plus_8_ff (fifo_pc_plus_8),
.o_instruction (thumb_instruction),
.o_instruction_valid (thumb_valid),
.o_und (thumb_und),
.o_force32_align (thumb_force32),
.o_pc_ff (thumb_pc_ff),
.o_pc_plus_8_ff (thumb_pc_plus_8_ff),
.o_irq (thumb_irq),
.o_fiq (thumb_fiq),
.o_taken_ff (thumb_bp_state)
);
// =========================
// PREDECODE STAGE
// =========================
zap_predecode_main #(
.ARCH_REGS(ARCH_REGS),
.PHY_REGS(PHY_REGS),
.SHIFT_OPS(SHIFT_OPS),
.ALU_OPS(ALU_OPS),
.COPROCESSOR_INTERFACE_ENABLE(1'd1),
.COMPRESSED_EN(1'd1)
)
u_zap_predecode (
// Input.
.i_clk (i_clk),
.i_reset (reset),
.i_clear_from_writeback (clear_from_writeback),
.i_data_stall (data_stall),
.i_clear_from_alu (clear_from_alu),
.i_stall_from_shifter (stall_from_shifter),
.i_stall_from_issue (stall_from_issue),
.i_irq (thumb_irq),
.i_fiq (thumb_fiq),
.i_abt (thumb_iabort),
.i_pc_plus_8_ff (thumb_pc_plus_8_ff),
.i_pc_ff (thumb_pc_plus_8_ff - 32'd8),
.i_cpu_mode_t (alu_flags_ff[T]),
.i_cpu_mode_mode (alu_flags_ff[`CPSR_MODE]),
.i_instruction (thumb_instruction),
.i_instruction_valid (thumb_valid),
.i_taken (thumb_bp_state),
.i_force32 (thumb_force32),
.i_und (thumb_und),
.i_copro_done (copro_done),
.i_pipeline_dav (pipeline_is_not_empty),
// Output.
.o_stall_from_decode (stall_from_decode),
.o_pc_plus_8_ff (predecode_pc_plus_8),
.o_pc_ff (predecode_pc),
.o_irq_ff (predecode_irq),
.o_fiq_ff (predecode_fiq),
.o_abt_ff (predecode_abt),
.o_und_ff (predecode_und),
.o_force32align_ff (predecode_force32),
.o_copro_dav_ff (copro_dav),
.o_copro_word_ff (copro_word),
.o_clear_from_decode (clear_from_decode),
.o_pc_from_decode (pc_from_decode),
.o_instruction_ff (predecode_inst),
.o_instruction_valid_ff (predecode_val),
.o_taken_ff (predecode_taken)
);
// =====================
// DECODE STAGE
// =====================
zap_decode_main #(
.ARCH_REGS(ARCH_REGS),
.PHY_REGS(PHY_REGS),
.SHIFT_OPS(SHIFT_OPS),
.ALU_OPS(ALU_OPS)
)
u_zap_decode_main (
.o_decompile (decode_decompile),
// Input.
.i_clk (i_clk),
.i_reset (reset),
.i_clear_from_writeback (clear_from_writeback),
.i_data_stall (data_stall),
.i_clear_from_alu (clear_from_alu),
.i_stall_from_shifter (stall_from_shifter),
.i_stall_from_issue (stall_from_issue),
.i_thumb_und (predecode_und),
.i_irq (predecode_irq),
.i_fiq (predecode_fiq),
.i_abt (predecode_abt),
.i_pc_plus_8_ff (predecode_pc_plus_8),
.i_pc_ff (predecode_pc),
.i_cpsr_ff_mode (alu_flags_ff[`CPSR_MODE]),
.i_cpsr_ff_i (alu_flags_ff[I]),
.i_cpsr_ff_f (alu_flags_ff[F]),
.i_instruction (predecode_inst),
.i_instruction_valid (predecode_val),
.i_taken (predecode_taken),
.i_force32align (predecode_force32),
// Output.
.o_condition_code_ff (decode_condition_code),
.o_destination_index_ff (decode_destination_index),
.o_alu_source_ff (decode_alu_source_ff),
.o_alu_operation_ff (decode_alu_operation_ff),
.o_shift_source_ff (decode_shift_source_ff),
.o_shift_operation_ff (decode_shift_operation_ff),
.o_shift_length_ff (decode_shift_length_ff),
.o_flag_update_ff (decode_flag_update_ff),
.o_mem_srcdest_index_ff (decode_mem_srcdest_index_ff),
.o_mem_load_ff (decode_mem_load_ff),
.o_mem_store_ff (decode_mem_store_ff),
.o_mem_pre_index_ff (decode_mem_pre_index_ff),
.o_mem_unsigned_byte_enable_ff (decode_mem_unsigned_byte_enable_ff),
.o_mem_signed_byte_enable_ff (decode_mem_signed_byte_enable_ff),
.o_mem_signed_halfword_enable_ff(decode_mem_signed_halfword_enable_ff),
.o_mem_unsigned_halfword_enable_ff (decode_mem_unsigned_halfword_enable_ff),
.o_mem_translate_ff (decode_mem_translate_ff),
.o_pc_plus_8_ff (decode_pc_plus_8_ff),
.o_pc_ff (decode_pc_ff),
.o_switch_ff (decode_switch_ff),
.o_irq_ff (decode_irq_ff),
.o_fiq_ff (decode_fiq_ff),
.o_abt_ff (decode_abt_ff),
.o_swi_ff (decode_swi_ff),
.o_und_ff (decode_und_ff),
.o_force32align_ff (decode_force32_ff),
.o_taken_ff (decode_taken_ff)
);
// ==================
// ISSUE
// ==================
zap_issue_main #(
.PHY_REGS(PHY_REGS),
.SHIFT_OPS(SHIFT_OPS),
.ALU_OPS(ALU_OPS)
)
u_zap_issue_main
(
.i_decompile(decode_decompile),
.o_decompile(issue_decompile),
.i_und_ff(decode_und_ff),
.o_und_ff(issue_und_ff),
.i_taken_ff(decode_taken_ff),
.o_taken_ff(issue_taken_ff),
.i_pc_ff(decode_pc_ff),
.o_pc_ff(issue_pc_ff),
// Inputs
.i_clk (i_clk),
.i_reset (reset),
.i_clear_from_writeback (clear_from_writeback),
.i_stall_from_shifter (stall_from_shifter),
.i_data_stall (data_stall),
.i_clear_from_alu (clear_from_alu),
.i_pc_plus_8_ff (decode_pc_plus_8_ff),
.i_condition_code_ff (decode_condition_code),
.i_destination_index_ff (decode_destination_index),
.i_alu_source_ff (decode_alu_source_ff),
.i_alu_operation_ff (decode_alu_operation_ff),
.i_shift_source_ff (decode_shift_source_ff),
.i_shift_operation_ff (decode_shift_operation_ff),
.i_shift_length_ff (decode_shift_length_ff),
.i_flag_update_ff (decode_flag_update_ff),
.i_mem_srcdest_index_ff (decode_mem_srcdest_index_ff),
.i_mem_load_ff (decode_mem_load_ff),
.i_mem_store_ff (decode_mem_store_ff),
.i_mem_pre_index_ff (decode_mem_pre_index_ff),
.i_mem_unsigned_byte_enable_ff (decode_mem_unsigned_byte_enable_ff),
.i_mem_signed_byte_enable_ff (decode_mem_signed_byte_enable_ff),
.i_mem_signed_halfword_enable_ff(decode_mem_signed_halfword_enable_ff),
.i_mem_unsigned_halfword_enable_ff(decode_mem_unsigned_halfword_enable_ff),
.i_mem_translate_ff (decode_mem_translate_ff),
.i_irq_ff (decode_irq_ff),
.i_fiq_ff (decode_fiq_ff),
.i_abt_ff (decode_abt_ff),
.i_swi_ff (decode_swi_ff),
.i_cpu_mode (alu_flags_ff),
// Needed to resolve CPSR refs.
.i_force32align_ff (decode_force32_ff),
.o_force32align_ff (issue_force32_ff),
// Register file.
.i_rd_data_0 (rd_data_0),
.i_rd_data_1 (rd_data_1),
.i_rd_data_2 (rd_data_2),
.i_rd_data_3 (rd_data_3),
// Feedback.
.i_shifter_destination_index_ff (shifter_destination_index_ff),
.i_alu_destination_index_ff (alu_destination_index_ff),
.i_memory_destination_index_ff (memory_destination_index_ff),
.i_alu_dav_nxt (alu_dav_nxt),
.i_alu_dav_ff (alu_dav_ff),
.i_memory_dav_ff (memory_dav_ff),
.i_alu_destination_value_nxt (alu_alu_result_nxt),
.i_alu_destination_value_ff (alu_alu_result_ff),
.i_memory_destination_value_ff (memory_alu_result_ff),
.i_shifter_mem_srcdest_index_ff (shifter_mem_srcdest_index_ff),
.i_alu_mem_srcdest_index_ff (alu_mem_srcdest_index_ff),
.i_memory_mem_srcdest_index_ff (memory_mem_srcdest_index_ff),
.i_shifter_mem_load_ff (shifter_mem_load_ff),
.i_alu_mem_load_ff (alu_mem_load_ff),
.i_memory_mem_load_ff (memory_mem_load_ff),
.i_memory_mem_srcdest_value_ff (memory_mem_rd_data),
// Switch indicator.
.i_switch_ff (decode_switch_ff),
.o_switch_ff (issue_switch_ff),
// Outputs.
.o_rd_index_0 (rd_index_0),
.o_rd_index_1 (rd_index_1),
.o_rd_index_2 (rd_index_2),
.o_rd_index_3 (rd_index_3),
.o_condition_code_ff (issue_condition_code_ff),
.o_destination_index_ff (issue_destination_index_ff),
.o_alu_operation_ff (issue_alu_operation_ff),
.o_shift_operation_ff (issue_shift_operation_ff),
.o_flag_update_ff (issue_flag_update_ff),
.o_mem_srcdest_index_ff (issue_mem_srcdest_index_ff),
.o_mem_load_ff (issue_mem_load_ff),
.o_mem_store_ff (issue_mem_store_ff),
.o_mem_pre_index_ff (issue_mem_pre_index_ff),
.o_mem_unsigned_byte_enable_ff (issue_mem_unsigned_byte_enable_ff),
.o_mem_signed_byte_enable_ff (issue_mem_signed_byte_enable_ff),
.o_mem_signed_halfword_enable_ff(issue_mem_signed_halfword_enable_ff),
.o_mem_unsigned_halfword_enable_ff(issue_mem_unsigned_halfword_enable_ff),
.o_mem_translate_ff (issue_mem_translate_ff),
.o_irq_ff (issue_irq_ff),
.o_fiq_ff (issue_fiq_ff),
.o_abt_ff (issue_abt_ff),
.o_swi_ff (issue_swi_ff),
.o_alu_source_value_ff (issue_alu_source_value_ff),
.o_shift_source_value_ff (issue_shift_source_value_ff),
.o_shift_length_value_ff (issue_shift_length_value_ff),
.o_mem_srcdest_value_ff (issue_mem_srcdest_value_ff),
.o_alu_source_ff (issue_alu_source_ff),
.o_shift_source_ff (issue_shift_source_ff),
.o_stall_from_issue (stall_from_issue),
.o_pc_plus_8_ff (issue_pc_plus_8_ff),
.o_shifter_disable_ff (issue_shifter_disable_ff)
);
// =======================
// SHIFTER STAGE
// =======================
zap_shifter_main #(
.PHY_REGS(PHY_REGS),
.ALU_OPS(ALU_OPS),
.SHIFT_OPS(SHIFT_OPS)
)
u_zap_shifter_main
(
.i_decompile (issue_decompile),
.o_decompile (shifter_decompile),
.i_pc_ff (issue_pc_ff),
.o_pc_ff (shifter_pc_ff),
.i_taken_ff (issue_taken_ff),
.o_taken_ff (shifter_taken_ff),
.i_und_ff (issue_und_ff),
.o_und_ff (shifter_und_ff),
.o_nozero_ff (shifter_nozero_ff),
.i_clk (i_clk),
.i_reset (reset),
.i_clear_from_writeback (clear_from_writeback),
.i_data_stall (data_stall),
.i_clear_from_alu (clear_from_alu),
.i_condition_code_ff (issue_condition_code_ff),
.i_destination_index_ff (issue_destination_index_ff),
.i_alu_operation_ff (issue_alu_operation_ff),
.i_shift_operation_ff (issue_shift_operation_ff),
.i_flag_update_ff (issue_flag_update_ff),
.i_mem_srcdest_index_ff (issue_mem_srcdest_index_ff),
.i_mem_load_ff (issue_mem_load_ff),
.i_mem_store_ff (issue_mem_store_ff),
.i_mem_pre_index_ff (issue_mem_pre_index_ff),
.i_mem_unsigned_byte_enable_ff (issue_mem_unsigned_byte_enable_ff),
.i_mem_signed_byte_enable_ff (issue_mem_signed_byte_enable_ff),
.i_mem_signed_halfword_enable_ff(issue_mem_signed_halfword_enable_ff),
.i_mem_unsigned_halfword_enable_ff(issue_mem_unsigned_halfword_enable_ff),
.i_mem_translate_ff (issue_mem_translate_ff),
.i_irq_ff (issue_irq_ff),
.i_fiq_ff (issue_fiq_ff),
.i_abt_ff (issue_abt_ff),
.i_swi_ff (issue_swi_ff),
.i_alu_source_ff (issue_alu_source_ff),
.i_shift_source_ff (issue_shift_source_ff),
.i_alu_source_value_ff (issue_alu_source_value_ff),
.i_shift_source_value_ff (issue_shift_source_value_ff),
.i_shift_length_value_ff (issue_shift_length_value_ff),
.i_mem_srcdest_value_ff (issue_mem_srcdest_value_ff),
.i_pc_plus_8_ff (issue_pc_plus_8_ff),
.i_disable_shifter_ff (issue_shifter_disable_ff),
// Next CPSR.
.i_cpsr_nxt (alu_cpsr_nxt),
.i_cpsr_ff (alu_flags_ff),
// Feedback
.i_alu_value_nxt (alu_alu_result_nxt),
.i_alu_dav_nxt (alu_dav_nxt),
// Switch indicator.
.i_switch_ff (issue_switch_ff),
.o_switch_ff (shifter_switch_ff),
// Force32
.i_force32align_ff (issue_force32_ff),
.o_force32align_ff (shifter_force32_ff),
// Outputs.
.o_mem_srcdest_value_ff (shifter_mem_srcdest_value_ff),
.o_alu_source_value_ff (shifter_alu_source_value_ff),
.o_shifted_source_value_ff (shifter_shifted_source_value_ff),
.o_shift_carry_ff (shifter_shift_carry_ff),
.o_shift_sat_ff (shifter_shift_sat_ff),
.o_pc_plus_8_ff (shifter_pc_plus_8_ff),
.o_mem_srcdest_index_ff (shifter_mem_srcdest_index_ff),
.o_mem_load_ff (shifter_mem_load_ff),
.o_mem_store_ff (shifter_mem_store_ff),
.o_mem_pre_index_ff (shifter_mem_pre_index_ff),
.o_mem_unsigned_byte_enable_ff (shifter_mem_unsigned_byte_enable_ff),
.o_mem_signed_byte_enable_ff (shifter_mem_signed_byte_enable_ff),
.o_mem_signed_halfword_enable_ff(shifter_mem_signed_halfword_enable_ff),
.o_mem_unsigned_halfword_enable_ff(shifter_mem_unsigned_halfword_enable_ff),
.o_mem_translate_ff (shifter_mem_translate_ff),
.o_condition_code_ff (shifter_condition_code_ff),
.o_destination_index_ff (shifter_destination_index_ff),
.o_alu_operation_ff (shifter_alu_operation_ff),
.o_flag_update_ff (shifter_flag_update_ff),
// Interrupts.
.o_irq_ff (shifter_irq_ff),
.o_fiq_ff (shifter_fiq_ff),
.o_abt_ff (shifter_abt_ff),
.o_swi_ff (shifter_swi_ff),
// Stall
.o_stall_from_shifter (stall_from_shifter)
);
// ===============
// ALU STAGE
// ===============
zap_alu_main #(
.PHY_REGS(PHY_REGS),
.SHIFT_OPS(SHIFT_OPS),
.ALU_OPS(ALU_OPS)
)
u_zap_alu_main
(
.i_decompile (shifter_decompile),
.o_decompile (alu_decompile),
.i_hijack ( wb_hijack ),
.i_hijack_op1 ( wb_hijack_op1 ),
.i_hijack_op2 ( wb_hijack_op2 ),
.i_hijack_cin ( wb_hijack_cin ),
.o_hijack_sum ( alu_hijack_sum ),
.i_taken_ff (shifter_taken_ff),
.o_confirm_from_alu (confirm_from_alu),
.i_pc_ff (shifter_pc_ff),
.i_und_ff (shifter_und_ff),
.o_und_ff (alu_und_ff),
.i_nozero_ff ( shifter_nozero_ff ),
.i_clk (i_clk),
.i_reset (reset),
.i_clear_from_writeback (clear_from_writeback),
.i_data_stall (data_stall),
.i_cpsr_nxt (cpsr_nxt),
.i_flag_update_ff (shifter_flag_update_ff),
.i_switch_ff (shifter_switch_ff),
.i_force32align_ff (shifter_force32_ff),
.i_mem_srcdest_value_ff (shifter_mem_srcdest_value_ff),
.i_alu_source_value_ff (shifter_alu_source_value_ff),
.i_shifted_source_value_ff (shifter_shifted_source_value_ff),
.i_shift_carry_ff (shifter_shift_carry_ff),
.i_shift_sat_ff (shifter_shift_sat_ff),
.i_pc_plus_8_ff (shifter_pc_plus_8_ff),
.i_abt_ff (shifter_abt_ff),
.i_irq_ff (shifter_irq_ff),
.i_fiq_ff (shifter_fiq_ff),
.i_swi_ff (shifter_swi_ff),
.i_mem_srcdest_index_ff (shifter_mem_srcdest_index_ff),
.i_mem_load_ff (shifter_mem_load_ff),
.i_mem_store_ff (shifter_mem_store_ff),
.i_mem_pre_index_ff (shifter_mem_pre_index_ff),
.i_mem_unsigned_byte_enable_ff (shifter_mem_unsigned_byte_enable_ff),
.i_mem_signed_byte_enable_ff (shifter_mem_signed_byte_enable_ff),
.i_mem_signed_halfword_enable_ff(shifter_mem_signed_halfword_enable_ff),
.i_mem_unsigned_halfword_enable_ff(shifter_mem_unsigned_halfword_enable_ff),
.i_mem_translate_ff (shifter_mem_translate_ff),
.i_condition_code_ff (shifter_condition_code_ff),
.i_destination_index_ff (shifter_destination_index_ff),
.i_alu_operation_ff (shifter_alu_operation_ff), // {OP,S}
.i_data_mem_fault (i_data_wb_err | i_dcache_err2),
.o_alu_result_nxt (alu_alu_result_nxt),
.o_alu_result_ff (alu_alu_result_ff),
.o_abt_ff (alu_abt_ff),
.o_irq_ff (alu_irq_ff),
.o_fiq_ff (alu_fiq_ff),
.o_swi_ff (alu_swi_ff),
.o_dav_ff (alu_dav_ff),
.o_dav_nxt (alu_dav_nxt),
.o_pc_plus_8_ff (alu_pc_plus_8_ff),
// Data access address. Ignore [1:0].
.o_mem_address_ff (alu_address_ff),
.o_clear_from_alu (clear_from_alu),
.o_pc_from_alu (pc_from_alu),
.o_destination_index_ff (alu_destination_index_ff),
.o_flags_ff (alu_flags_ff), // Output flags.
.o_flags_nxt (alu_cpsr_nxt),
.o_mem_srcdest_value_ff (),
.o_mem_srcdest_index_ff (alu_mem_srcdest_index_ff),
.o_mem_load_ff (alu_mem_load_ff),
.o_mem_store_ff (),
.o_ben_ff (),
.o_mem_unsigned_byte_enable_ff (alu_ubyte_ff),
.o_mem_signed_byte_enable_ff (alu_sbyte_ff),
.o_mem_signed_halfword_enable_ff (alu_shalf_ff),
.o_mem_unsigned_halfword_enable_ff(alu_uhalf_ff),
.o_mem_translate_ff (o_mem_translate),
.o_address_nxt ( alu_address_nxt ),
.o_data_wb_we_nxt (o_data_wb_we_nxt),
.o_data_wb_cyc_nxt (o_data_wb_cyc_nxt),
.o_data_wb_stb_nxt (o_data_wb_stb_nxt),
.o_data_wb_dat_nxt (o_data_wb_dat_nxt),
.o_data_wb_sel_nxt (o_data_wb_sel_nxt),
.o_data_wb_we_ff (o_data_wb_we),
.o_data_wb_cyc_ff (o_data_wb_cyc),
.o_data_wb_stb_ff (o_data_wb_stb),
.o_data_wb_dat_ff (o_data_wb_dat),
.o_data_wb_sel_ff (o_data_wb_sel)
);
// ====================
// MEMORY
// ====================
zap_memory_main #(
.PHY_REGS(PHY_REGS)
)
u_zap_memory_main
(
.i_decompile (alu_decompile),
.o_decompile (memory_decompile),
.i_und_ff (alu_und_ff),
.o_und_ff (memory_und_ff),
.i_mem_address_ff (alu_address_ff),
.i_clk (i_clk),
.i_reset (reset),
.i_sbyte_ff (alu_sbyte_ff), // Signed byte.
.i_ubyte_ff (alu_ubyte_ff), // Unsigned byte.
.i_shalf_ff (alu_shalf_ff), // Signed half word.
.i_uhalf_ff (alu_uhalf_ff), // Unsigned half word.
.i_clear_from_writeback (clear_from_writeback),
.i_data_stall (data_stall),
.i_alu_result_ff (alu_alu_result_ff),
.i_flags_ff (alu_flags_ff),
.i_mem_load_ff (alu_mem_load_ff),
.i_mem_rd_data (i_data_wb_dat),// From memory.
.i_mem_fault ({i_dcache_err2, i_data_wb_err}), // From cache.
.o_mem_fault (memory_data_abt_ff[1:0]),
.i_dav_ff (alu_dav_ff),
.i_pc_plus_8_ff (alu_pc_plus_8_ff),
.i_destination_index_ff (alu_destination_index_ff),
.i_irq_ff (alu_irq_ff),
.i_fiq_ff (alu_fiq_ff),
.i_instr_abort_ff (alu_abt_ff),
.i_swi_ff (alu_swi_ff),
// Used to speed up loads.
.i_mem_srcdest_index_ff (alu_mem_srcdest_index_ff),
// Can come in handy since this is reused for several other things.
.i_mem_srcdest_value_ff (o_data_wb_dat),
.o_alu_result_ff (memory_alu_result_ff),
.o_flags_ff (memory_flags_ff),
.o_destination_index_ff (memory_destination_index_ff),
.o_mem_srcdest_index_ff (memory_mem_srcdest_index_ff),
.o_dav_ff (memory_dav_ff),
.o_pc_plus_8_ff (memory_pc_plus_8_ff),
.o_irq_ff (memory_irq_ff),
.o_fiq_ff (memory_fiq_ff),
.o_swi_ff (memory_swi_ff),
.o_instr_abort_ff (memory_instr_abort_ff),
.o_mem_load_ff (memory_mem_load_ff),
.o_mem_rd_data (memory_mem_rd_data)
);
// ==================
// WRITEBACK
// ==================
zap_writeback #(
.PHY_REGS(PHY_REGS)
)
u_zap_writeback
(
.i_decompile (memory_decompile),
.o_decompile (rb_decompile),
.o_shelve (shelve),
.i_clk (i_clk), // ZAP clock.
.i_reset (reset), // ZAP reset.
.i_valid (memory_dav_ff),
.i_data_stall (data_stall),
.i_clear_from_alu (clear_from_alu),
.i_pc_from_alu (pc_from_alu),
.i_stall_from_decode (stall_from_decode),
.i_stall_from_issue (stall_from_issue),
.i_stall_from_shifter (stall_from_shifter),
.i_clear_from_icache (i_icache_err2),
.i_thumb (alu_flags_ff[T]), // To indicate thumb state.
.i_clear_from_decode (clear_from_decode),
.i_pc_from_decode (pc_from_decode),
.i_code_stall (code_stall),
// Used to valid writes on i_wr_index1.
.i_mem_load_ff (memory_mem_load_ff),
.i_rd_index_0 (rd_index_0),
.i_rd_index_1 (rd_index_1),
.i_rd_index_2 (rd_index_2),
.i_rd_index_3 (rd_index_3),
.i_wr_index (memory_destination_index_ff),
.i_wr_data (memory_alu_result_ff),
.i_flags (memory_flags_ff),
.i_wr_index_1 (memory_mem_srcdest_index_ff),// load index.
.i_wr_data_1 (memory_mem_rd_data), // load data.
.i_irq (memory_irq_ff),
.i_fiq (memory_fiq_ff),
.i_instr_abt (memory_instr_abort_ff),
.i_data_abt (memory_data_abt_ff[1:0]),
.i_swi (memory_swi_ff),
.i_und (memory_und_ff),
.i_pc_buf_ff (memory_pc_plus_8_ff),
.i_copro_reg_en (copro_reg_en),
.i_copro_reg_wr_index (copro_reg_wr_index),
.i_copro_reg_rd_index (copro_reg_rd_index),
.i_copro_reg_wr_data (copro_reg_wr_data),
.o_copro_reg_rd_data_ff (copro_reg_rd_data),
.o_rd_data_0 (rd_data_0),
.o_rd_data_1 (rd_data_1),
.o_rd_data_2 (rd_data_2),
.o_rd_data_3 (rd_data_3),
.o_pc (o_instr_wb_adr),
.o_pc_nxt (o_instr_wb_adr_nxt),
.o_cpsr_nxt (cpsr_nxt),
.o_clear_from_writeback (clear_from_writeback),
.o_hijack (wb_hijack),
.o_hijack_op1 (wb_hijack_op1),
.o_hijack_op2 (wb_hijack_op2),
.o_hijack_cin (wb_hijack_cin),
.i_hijack_sum (alu_hijack_sum),
.o_mask (writeback_mask)
);
// ==================================
// CP15 CB
// ==================================
zap_cp15_cb u_zap_cp15_cb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_cp_word (copro_word),
.i_cp_dav (copro_dav),
.o_cp_done (copro_done),
.i_cpsr (o_cpsr),
.o_reg_en (copro_reg_en),
.o_reg_wr_data (copro_reg_wr_data),
.i_reg_rd_data (copro_reg_rd_data),
.o_reg_wr_index (copro_reg_wr_index),
.o_reg_rd_index (copro_reg_rd_index),
.i_fsr (i_fsr),
.i_far (i_far),
.o_dac (o_dac),
.o_baddr (o_baddr),
.o_mmu_en (o_mmu_en),
.o_sr (o_sr),
.o_pid (o_pid),
.o_dcache_inv (o_dcache_inv),
.o_icache_inv (o_icache_inv),
.o_dcache_clean (o_dcache_clean),
.o_icache_clean (o_icache_clean),
.o_dtlb_inv (o_dtlb_inv),
.o_itlb_inv (o_itlb_inv),
.o_dcache_en (o_dcache_en),
.o_icache_en (o_icache_en),
.i_dcache_inv_done (i_dcache_inv_done),
.i_icache_inv_done (i_icache_inv_done),
.i_dcache_clean_done (i_dcache_clean_done),
.i_icache_clean_done (i_icache_clean_done)
);
reg [(8*8)-1:0] CPU_MODE; // Max 8 characters i.e. 64-bit string.
always @*
case(o_cpsr[`CPSR_MODE])
FIQ: CPU_MODE = "FIQ";
IRQ: CPU_MODE = "IRQ";
USR: CPU_MODE = "USR";
UND: CPU_MODE = "UND";
SVC: CPU_MODE = "SVC";
ABT: CPU_MODE = "ABT";
SYS: CPU_MODE = "SYS";
default: CPU_MODE = "???";
endcase
endmodule |
module's pkt waiting for transmit
input exe2disp_data_wr,
input [133:0] exe2disp_data,
input exe2disp_valid_wr,
input exe2disp_valid,
output reg disp2exe_alf,
//execute's tranmit direction request
input exe2disp_direction_req,
input exe2disp_direction,//0:up cpu 1: down port
//transmit to up cpu
output reg disp2up_data_wr,
output [133:0] disp2up_data,
output reg disp2up_valid_wr,
output disp2up_valid,
input up2disp_alf,
//transmit to down port
output reg disp2down_data_wr,
output [133:0] disp2down_data,
output reg disp2down_valid_wr,
output disp2down_valid,
input down2disp_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg [133:0] data_buff;
//only 1 stream path would be select at a time,so no need 2 set data registers
reg [1:0] disp_state;
//***************************************************
// Transmit Judge
//***************************************************
assign disp2up_data = data_buff;
assign disp2down_data = data_buff;
assign disp2up_valid = disp2up_valid_wr;
assign disp2down_valid = disp2down_valid_wr;
//receive controll ,ctrl by disp2exe_alf
//if set to 1,execute must not send pkt to dispatch
always @ * begin
if(exe2disp_direction_req == 1'b1) begin
if(exe2disp_direction == 1'b0) begin//request send to up cpu
disp2exe_alf = up2disp_alf;
end
else begin//request send to down port
disp2exe_alf = down2disp_alf;
end
end
else begin
disp2exe_alf = 1'b1;//don't permit execute send pkt
end
end
//pkt data transmit
localparam IDLE_S = 2'd0,
TRANS_UP_S = 2'd1,
TRANS_DOWN_S = 2'd2;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= IDLE_S;
end
else begin
case(disp_state)
IDLE_S: begin
if(exe2disp_data_wr == 1'b1) begin//trans start
data_buff <= exe2disp_data;
if(exe2disp_direction == 1'b0) begin//request send to up cpu
disp2up_data_wr <= exe2disp_data_wr;
disp2up_valid_wr <= exe2disp_valid_wr;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= TRANS_UP_S;
end
else begin//request send to down port
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= exe2disp_data_wr;
disp2down_valid_wr <= exe2disp_valid_wr;
disp_state <= TRANS_DOWN_S;
end
end
else begin
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= IDLE_S;
end
end
TRANS_UP_S: begin
data_buff <= exe2disp_data;
disp2up_data_wr <= exe2disp_data_wr;
disp2up_valid_wr <= exe2disp_valid_wr;
if(exe2disp_valid_wr == 1'b1) begin//trans end
disp_state <= IDLE_S;
end
else begin
disp_state <= TRANS_UP_S;
end
end
TRANS_DOWN_S: begin
data_buff <= exe2disp_data;
disp2down_data_wr <= exe2disp_data_wr;
disp2down_valid_wr <= exe2disp_valid_wr;
if(exe2disp_valid_wr == 1'b1) begin//trans end
disp_state <= IDLE_S;
end
else begin
disp_state <= TRANS_DOWN_S;
end
end
default: begin
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= IDLE_S;
end
endcase
end
end
endmodule |
module oh_memory
#(parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output
parameter AW = $clog2(DEPTH),// rd_count width (derived)
parameter TYPE = "soft", // hard=hard macro,soft=synthesizable
parameter DUALPORT= "1", // 1=dual port,0=single port
parameter CONFIG = "default", // hard macro user config pass through
parameter SHAPE = "square" // hard macro shape (square, tall, wide)
)
(// Memory interface (dual port)
input wr_clk, //write clock
input wr_en, //write enable
input [DW-1:0] wr_wem, //per bit write enable
input [AW-1:0] wr_addr,//write address
input [DW-1:0] wr_din, //write data
input rd_clk, //read clock
input rd_en, //read enable
input [AW-1:0] rd_addr,//read address (only used for dual port!)
output [DW-1:0] rd_dout,//read output data
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din, // data input
input [DW-1:0] bist_dout, // data input
// Power/repair (hard macro only)
input shutdown, // shutdown signal
input vss, // ground signal
input vdd, // memory array power
input vddio, // periphery/io power
input [7:0] memconfig, // generic memory config
input [7:0] memrepair // repair vector
);
generate
if(TYPE=="soft") begin: ram_soft
oh_ram #(.DW(DW),
.DEPTH(DEPTH),
.REG(REG),
.DUALPORT(DUALPORT))
oh_ram(/*AUTOINST*/
// Outputs
.rd_dout (rd_dout[DW-1:0]),
// Inputs
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
.wr_clk (wr_clk),
.wr_en (wr_en),
.wr_addr (wr_addr[AW-1:0]),
.wr_wem (wr_wem[DW-1:0]),
.wr_din (wr_din[DW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[DW-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[DW-1:0]),
.bist_dout (bist_dout[DW-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
end // block: soft
else begin: ram_hard
//#########################################
// Hard coded RAM Macros
//#########################################
asic_ram #(.DW(DW),
.DEPTH(DEPTH),
.REG(REG),
.DUALPORT(DUALPORT),
.CONFIG(CONFIG),
.SHAPE(SHAPE))
asic_ram(
// Outputs
.rd_dout (rd_dout[DW-1:0]),
// Inputs
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
.wr_clk (wr_clk),
.wr_en (wr_en),
.wr_addr (wr_addr[AW-1:0]),
.wr_wem (wr_wem[DW-1:0]),
.wr_din (wr_din[DW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[DW-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[DW-1:0]),
.bist_dout (bist_dout[DW-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
end // block: hard
endgenerate
endmodule |
module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SA_WIDTH = DR_WIDTH;
parameter SB_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter FS_WIDTH = 4;
parameter CNTRL_FLAGS_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SA_WIDTH+SB_WIDTH+FS_WIDTH+CNTRL_FLAGS_WIDTH;
wire RW = CNTRL_bus_in[4];
wire [SA_WIDTH-1:0] DA = CNTRL_bus_in[19:17];
wire [SA_WIDTH-1:0] AA = CNTRL_bus_in[16:14];
wire [SA_WIDTH-1:0] BA = CNTRL_bus_in[13:11];
reg [WORD_WIDTH-1:0] SYNC_RAM0 [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] SYNC_RAM1 [2**DR_WIDTH-1:0];
reg [DR_WIDTH-1:0] i;
always@(posedge CLK) begin
/*
if (!RST)
for (i=3'b0;i<2**DR_WIDTH-3'b1;i = i + 3'b1) begin
SYNC_RAM1[i] <= 0;
SYNC_RAM0[i] <= 0;
end
else if (RW) begin
*/
if(RW) begin
SYNC_RAM0[DA] <= D_bus_in;
SYNC_RAM1[DA] <= D_bus_in;
end
end
always@(*) begin
ADDR_bus_out <= SYNC_RAM0[AA];
B_data_out <= SYNC_RAM1[BA];
end
endmodule |
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mac_stall_r;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
`ifdef OR1200_MULT_IMPLEMENTED
reg [width-1:0] result;
reg [2*width-1:0] mul_prod_r;
`else
wire [width-1:0] result;
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [2*width-1:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [2*width-1:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div_divu;
wire alu_op_div;
reg div_free;
`ifdef OR1200_IMPL_DIV
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`endif
//
// Combinatorial logic
//
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
`ifdef OR1200_MULT_IMPLEMENTED
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b)
casex(alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV:
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL: begin
result = mul_prod_r[31:0];
end
default:
`ifdef OR1200_MAC_SHIFTBY
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
`else
result = mac_r[31:0];
`endif
endcase
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier and
// an optional divider
//
always @(posedge rst or posedge clk)
if (rst) begin
mul_prod_r <= #1 64'h0000_0000_0000_0000;
div_free <= #1 1'b1;
`ifdef OR1200_IMPL_DIV
div_cntr <= #1 6'b00_0000;
`endif
end
`ifdef OR1200_IMPL_DIV
else if (|div_cntr) begin
if (div_tmp[31])
mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= #1 div_cntr - 1'b1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
div_cntr <= #1 6'b10_0000;
div_free <= #1 1'b0;
end
`endif // OR1200_IMPL_DIV
else if (div_free | !ex_freeze) begin
mul_prod_r <= #1 mul_prod[63:0];
div_free <= #1 1'b1;
end
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= #1 mac_op;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= #1 mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= #1 mac_op_r2;
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
if (rst)
mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= #1 spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= #1 spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= #1 mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= #1 mac_r - mul_prod_r;
else if (macrc_op & !ex_freeze)
mac_r <= #1 64'h0000_0000_0000_0000;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
if (rst)
mac_stall_r <= #1 1'b0;
else
mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
`ifdef OR1200_IMPL_DIV
| (|div_cntr)
`endif
;
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
endmodule |
module sky130_fd_sc_hvl__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module system_microblaze_0_xlconcat_0(In0, In1, In2, In3, In4, In5, In6, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],dout[6:0]" */;
input [0:0]In0;
input [0:0]In1;
input [0:0]In2;
input [0:0]In3;
input [0:0]In4;
input [0:0]In5;
input [0:0]In6;
output [6:0]dout;
endmodule |
module sky130_fd_sc_ms__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hd__lpflow_decapkapwr (
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module pcie3_7x_0_pipe_user #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_USE_MODE = "3.0", // PCIe sim version
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
parameter RXVALID_MAX = 4'd15, // RXVALID max count
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
)
(
//---------- Input -------------------------------------
input USER_TXUSRCLK,
input USER_RXUSRCLK,
input USER_OOBCLK_IN,
input USER_RST_N,
input USER_RXUSRCLK_RST_N,
input USER_PCLK_SEL,
input USER_RESETOVRD_START,
input USER_TXRESETDONE,
input USER_RXRESETDONE,
input USER_TXELECIDLE,
input USER_TXCOMPLIANCE,
input USER_RXCDRLOCK_IN,
input USER_RXVALID_IN,
input USER_RXSTATUS_IN,
input USER_PHYSTATUS_IN,
input USER_RATE_DONE,
input USER_RST_IDLE,
input USER_RATE_RXSYNC,
input USER_RATE_IDLE,
input USER_RATE_GEN3,
input USER_RXEQ_ADAPT_DONE,
//---------- Output ------------------------------------
output USER_OOBCLK,
output USER_RESETOVRD,
output USER_TXPMARESET,
output USER_RXPMARESET,
output USER_RXCDRRESET,
output USER_RXCDRFREQRESET,
output USER_RXDFELPMRESET,
output USER_EYESCANRESET,
output USER_TXPCSRESET,
output USER_RXPCSRESET,
output USER_RXBUFRESET,
output USER_RESETOVRD_DONE,
output USER_RESETDONE,
output USER_ACTIVE_LANE,
output USER_RXCDRLOCK_OUT,
output USER_RXVALID_OUT,
output USER_PHYSTATUS_OUT,
output USER_PHYSTATUS_RST,
output USER_GEN3_RDY,
output USER_RX_CONVERGE
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 1:0] oobclk_cnt = 2'd0;
reg [ 7:0] reset_cnt = 8'd127;
reg [ 3:0] rxcdrlock_cnt = 4'd0;
reg [ 3:0] rxvalid_cnt = 4'd0;
reg [21:0] converge_cnt = 22'd0;
reg converge_gen3 = 1'd0;
//---------- Output Registers --------------------------
reg oobclk = 1'd0;
reg [ 7:0] reset = 8'h00;
reg gen3_rdy = 1'd0;
reg [ 1:0] fsm = 2'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 2'd0;
localparam FSM_RESETOVRD = 2'd1;
localparam FSM_RESET_INIT = 2'd2;
localparam FSM_RESET = 2'd3;
//---------- Simulation Speedup ------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= 1'd0;
resetovrd_start_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txelecidle_reg1 <= 1'd0;
txcompliance_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= 1'd0;
resetovrd_start_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txelecidle_reg2 <= 1'd0;
txcompliance_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= USER_PCLK_SEL;
resetovrd_start_reg1 <= USER_RESETOVRD_START;
txresetdone_reg1 <= USER_TXRESETDONE;
rxresetdone_reg1 <= USER_RXRESETDONE;
txelecidle_reg1 <= USER_TXELECIDLE;
txcompliance_reg1 <= USER_TXCOMPLIANCE;
rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
resetovrd_start_reg2 <= resetovrd_start_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txelecidle_reg2 <= txelecidle_reg1;
txcompliance_reg2 <= txcompliance_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
end
end
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= 1'd0;
rxstatus_reg1 <= 1'd0;
rst_idle_reg1 <= 1'd0;
rate_done_reg1 <= 1'd0;
rate_rxsync_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
rate_gen3_reg1 <= 1'd0;
rxeq_adapt_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= 1'd0;
rxstatus_reg2 <= 1'd0;
rst_idle_reg2 <= 1'd0;
rate_done_reg2 <= 1'd0;
rate_rxsync_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
rate_gen3_reg2 <= 1'd0;
rxeq_adapt_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= USER_RXVALID_IN;
rxstatus_reg1 <= USER_RXSTATUS_IN;
rst_idle_reg1 <= USER_RST_IDLE;
rate_done_reg1 <= USER_RATE_DONE;
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
rate_idle_reg1 <= USER_RATE_IDLE;
rate_gen3_reg1 <= USER_RATE_GEN3;
rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= rxvalid_reg1;
rxstatus_reg2 <= rxstatus_reg1;
rst_idle_reg2 <= rst_idle_reg1;
rate_done_reg2 <= rate_done_reg1;
rate_rxsync_reg2 <= rate_rxsync_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rate_gen3_reg2 <= rate_gen3_reg1;
rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
end
end
//---------- Generate Reset Override -------------------------------------------
generate if (PCIE_USE_MODE == "1.0")
begin : resetovrd
//---------- Reset Counter -------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset_cnt <= 8'd127;
else
//---------- Decrement Counter ---------------------
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
reset_cnt <= reset_cnt - 8'd1;
//---------- Reset Counter -------------------------
else
case (reset)
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
8'b10000000 : reset_cnt <= 8'd127;
default : reset_cnt <= 8'd127;
endcase
end
//---------- Reset Shift Register ------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset <= 8'h00;
else
//---------- Initialize Reset Register ---------
if (fsm == FSM_RESET_INIT)
reset <= 8'hFF;
//---------- Shift Reset Register --------------
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
reset <= {reset[6:0], 1'd0};
//---------- Hold Reset Register ---------------
else
reset <= reset;
end
//---------- Reset Override FSM --------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
fsm <= FSM_IDLE;
else
begin
case (fsm)
//---------- Idle State ------------------------
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
//---------- Assert RESETOVRD ------------------
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
//---------- Initialize Reset ------------------
FSM_RESET_INIT : fsm <= FSM_RESET;
//---------- Shift Reset -----------------------
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
//---------- Default State ---------------------
default : fsm <= FSM_IDLE;
endcase
end
end
end
//---------- Disable Reset Override --------------------------------------------
else
begin : resetovrd_disble
//---------- Generate Default Signals --------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
else
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
end
end
endgenerate
//---------- Generate OOB Clock Divider ------------------------
generate if (PCIE_OOBCLK_MODE == 1)
begin : oobclk_div
//---------- OOB Clock Divider -----------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= oobclk_cnt + 2'd1;
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
end
end
end
else
begin : oobclk_div_disable
//---------- OOB Clock Default -------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
end
end
endgenerate
//---------- RXCDRLOCK Filter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
rxcdrlock_cnt <= 4'd0;
else
//---------- Increment RXCDRLOCK Counter -----------
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
//---------- Hold RXCDRLOCK Counter ----------------
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt;
//---------- Reset RXCDRLOCK Counter ---------------
else
rxcdrlock_cnt <= 4'd0;
end
//---------- RXVALID Filter ----------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
rxvalid_cnt <= 4'd0;
else
//---------- Increment RXVALID Counter -------------
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
rxvalid_cnt <= rxvalid_cnt + 4'd1;
//---------- Hold RXVALID Counter ------------------
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
rxvalid_cnt <= rxvalid_cnt;
//---------- Reset RXVALID Counter -----------------
else
rxvalid_cnt <= 4'd0;
end
//---------- Converge Counter --------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
converge_cnt <= 22'd0;
else
//---------- Enter Gen1/Gen2 -----------------------
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
begin
//---------- Increment Converge Counter --------
if (converge_cnt < converge_max_cnt)
converge_cnt <= converge_cnt + 22'd1;
//---------- Hold Converge Counter -------------
else
converge_cnt <= converge_cnt;
end
//---------- Reset Converge Counter ----------------
else
converge_cnt <= 22'd0;
end
//---------- Converge ----------------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
converge_gen3 <= 1'd0;
else
//---------- Enter Gen3 ----------------------------
if (rate_gen3_reg2)
//---------- Wait for RX equalization adapt done
if (rxeq_adapt_done_reg2)
converge_gen3 <= 1'd1;
else
converge_gen3 <= converge_gen3;
//-------- Exit Gen3 -------------------------------
else
converge_gen3 <= 1'd0;
end
//---------- GEN3_RDY Generator ------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
gen3_rdy <= 1'd0;
else
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
end
//---------- PIPE User Override Reset Output -----------------------------------
assign USER_RESETOVRD = (fsm != FSM_IDLE);
assign USER_TXPMARESET = 1'd0;
assign USER_RXPMARESET = reset[0];
assign USER_RXCDRRESET = reset[1];
assign USER_RXCDRFREQRESET = reset[2];
assign USER_RXDFELPMRESET = reset[3];
assign USER_EYESCANRESET = reset[4];
assign USER_TXPCSRESET = 1'd0;
assign USER_RXPCSRESET = reset[5];
assign USER_RXBUFRESET = reset[6];
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
//---------- PIPE User Output --------------------------------------------------
assign USER_OOBCLK = oobclk;
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
//----------------------------------------------------------
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
//----------------------------------------------------------
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
rst_idle_reg2 && // Force RXVALID = 0 during reset
rate_idle_reg2); // Force RXVALID = 0 during rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
rate_done_reg2); // Gated PHYSTATUS for rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
//----------------------------------------------------------
assign USER_GEN3_RDY = gen3_rdy;
//----------------------------------------------------------
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
endmodule |
module Platform (
clk_clk,
dds_left_strobe_export,
dds_right_strobe_export,
hex0_2_export,
hex3_5_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
i2c_SDAT,
i2c_SCLK,
i2s_codec_iadcdat,
i2s_codec_iadclrc,
i2s_codec_ibclk,
i2s_codec_idaclrc,
i2s_codec_odacdat,
i2s_gpio_iadcdat,
i2s_gpio_iadclrc,
i2s_gpio_ibclk,
i2s_gpio_idaclrc,
i2s_gpio_odacdat,
keys_export,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
strobe_export,
switches_export,
white_noise_left_strobe_export,
white_noise_right_strobe_export,
xck_clk);
input clk_clk;
input dds_left_strobe_export;
input dds_right_strobe_export;
output [20:0] hex0_2_export;
output [20:0] hex3_5_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
inout i2c_SDAT;
output i2c_SCLK;
input i2s_codec_iadcdat;
input i2s_codec_iadclrc;
input i2s_codec_ibclk;
input i2s_codec_idaclrc;
output i2s_codec_odacdat;
input i2s_gpio_iadcdat;
input i2s_gpio_iadclrc;
input i2s_gpio_ibclk;
input i2s_gpio_idaclrc;
output i2s_gpio_odacdat;
input [2:0] keys_export;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
output strobe_export;
input [9:0] switches_export;
input white_noise_left_strobe_export;
input white_noise_right_strobe_export;
output xck_clk;
endmodule |
module sky130_fd_sc_ls__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module Judge_Test;
// Inputs
reg kind;
reg [15:0] data_in;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
Condition_Judge uut (
.data_out(data_out),
.kind(kind),
.data_in(data_in)
);
initial begin
// Initialize Inputs
kind = 0;
data_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
data_in = 1;
#100;
kind = 1;
data_in = 0;
#100;
kind = 1;
data_in = 1;
#100;
end
endmodule |
module pcx2mb_sm (
// Outputs
load_data,
shift_data,
entry1_active,
pcx_fsl_m_control,
pcx_fsl_m_write,
pcx_spc_grant_px,
// Inputs
rclk,
reset_l,
any_req_pq,
any_req_pa,
spc_pcx_atom_pq,
entry1_dest,
entry2_active,
entry2_atom,
fsl_pcx_m_full
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH = 5;
`else
parameter PCX_REQ_WIDTH = 2;
`endif
parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);
parameter PCX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -
(`PCX_WIDTH+PCX_REQ_WIDTH+1);
parameter [2:0] PCX_START_COUNT = PCX_GEAR_RATIO - 1;
parameter pFLS_IDLE = 0,
pFLS_LOAD = 1,
pFLS_SHIFT = 2,
pFLS_LDWAIT = 3,
pFLS_WAIT = 4;
parameter FLS_IDLE = 5'b00001,
FLS_LOAD = 5'b00010,
FLS_SHIFT = 5'b00100,
FLS_LDWAIT = 5'b01000,
FLS_WAIT = 5'b10000;
output load_data;
output shift_data;
output entry1_active;
output pcx_fsl_m_control;
output pcx_fsl_m_write;
output [4:0] pcx_spc_grant_px;
input rclk;
input reset_l;
input any_req_pq;
input any_req_pa;
input spc_pcx_atom_pq;
input [4:0] entry1_dest;
input entry2_active;
input entry2_atom;
input fsl_pcx_m_full;
wire pcx_fsl_m_control;
wire pcx_fsl_m_write;
// State machine to control the shifting out of the data.
reg [4:0] curr_state;
reg [4:0] next_state;
reg [2:0] curr_count;
reg [2:0] next_count;
reg data_write;
reg next_data_write;
reg [4:0] pcx_spc_grant_px;
reg next_grant;
reg atomic_first; // First part of an atomic txn
reg atomic_second; // Second part of an atomic txn
reg next_atomic_first;
reg next_atomic_second;
reg atomic_second_d1;
reg [4:0] entry1_dest_d1;
reg data_control;
reg next_control;
always @ (posedge rclk) begin // Start with a synchronous reset
if (!reset_l) begin
curr_state <= 5'b00001;
curr_count <= 3'b000;
data_write <= 1'b0;
pcx_spc_grant_px <= 5'b00000;
atomic_first <= 1'b0;
atomic_second <= 1'b0;
data_control <= 1'b0;
end
else begin
curr_state <= next_state;
curr_count <= next_count;
data_write <= next_data_write;
pcx_spc_grant_px <= {5{next_grant}} & entry1_dest_d1;
atomic_first <= next_atomic_first;
atomic_second <= next_atomic_second;
data_control <= next_control;
end
end
always @(posedge rclk) begin
atomic_second_d1 <= atomic_second;
entry1_dest_d1 <= entry1_dest;
end
always @ (curr_state or any_req_pq or any_req_pa or entry2_active or
curr_count or spc_pcx_atom_pq or atomic_first or atomic_second or
atomic_second_d1 or fsl_pcx_m_full or data_write or entry2_atom)
begin
case (1)
curr_state[pFLS_IDLE] : begin
next_count = 3'b000;
next_data_write = 1'b0;
next_grant = atomic_second_d1;
next_atomic_second = 1'b0;
next_control = 1'b0;
if (any_req_pq) begin
next_state = FLS_LOAD;
next_atomic_first = spc_pcx_atom_pq;
end
else begin
next_state = FLS_IDLE;
next_atomic_first = 1'b0;
end
end
curr_state[pFLS_LOAD] : begin
next_state = FLS_SHIFT;
next_count = PCX_START_COUNT;
next_grant = atomic_second_d1;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b1;
end
curr_state[pFLS_SHIFT] : begin
if (fsl_pcx_m_full) begin
next_state = FLS_SHIFT;
next_count = curr_count;
next_grant = atomic_second_d1 && !atomic_second;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = (curr_count == PCX_START_COUNT);
end
else if (curr_count > 3'd1) begin
next_state = FLS_SHIFT;
next_count = curr_count-3'b1;
next_grant = atomic_second_d1 && !atomic_second;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
else if (entry2_active || any_req_pa || any_req_pq) begin
next_state = FLS_LDWAIT;
next_count = curr_count-3'b1;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
else begin
next_state = FLS_WAIT;
next_count = curr_count-3'b1;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
end
// The last beat of the transaction, and a load is ready
// But we can't load until we know the last beat of the last
// txn has been accepted
curr_state[pFLS_LDWAIT] : begin
if (fsl_pcx_m_full) begin
next_state = FLS_LDWAIT;
next_count = curr_count;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
else begin
next_state = FLS_SHIFT;
next_count = PCX_START_COUNT;
next_grant = !atomic_first;
next_atomic_first = entry2_atom;
next_atomic_second = atomic_first;
next_data_write = 1'b1;
next_control = 1'b1;
end
end
// The last beat of the transaction: Don't go to IDLE or
// give grant to SPC until we know the beat was accepted.
curr_state[pFLS_WAIT] : begin
next_control = 1'b0;
if (fsl_pcx_m_full &&
(entry2_active || any_req_pa || any_req_pq) ) begin
next_state = FLS_LDWAIT;
next_count = curr_count;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
end
else if (fsl_pcx_m_full) begin
next_state = FLS_WAIT;
next_count = curr_count;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
end
else if (entry2_active || any_req_pa || any_req_pq) begin
next_state = FLS_LOAD;
next_grant = !atomic_first; // No grant on first atomic
next_atomic_first = 1'b0;
next_atomic_second = atomic_first;
next_count = curr_count-3'b1;
next_data_write = 1'b0;
end
else begin
next_state = FLS_IDLE;
next_grant = 1'b1;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
next_count = curr_count-3'b1;
next_data_write = 1'b0;
end
end
default : begin
next_state = FLS_IDLE;
next_data_write = 1'b0;
next_count = 3'b000;
next_grant = 1'b0;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
next_control = 1'b0;
end
endcase
end
// Outputs of the state machine
assign load_data = curr_state[pFLS_LOAD] ||
(curr_state[pFLS_LDWAIT] && !fsl_pcx_m_full);
assign shift_data = curr_state[pFLS_SHIFT] && !fsl_pcx_m_full;
assign entry1_active = !curr_state[pFLS_IDLE] ||
(data_write && fsl_pcx_m_full);
assign pcx_fsl_m_write = data_write && !fsl_pcx_m_full;
assign pcx_fsl_m_control = data_control;
endmodule |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:3];
reg [2:0] wp;
reg [3:0] rp;
wire [2:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 3'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 3'h1;
always @(posedge clk)
if(!en) rp <= #1 4'h0;
else
if(re & m16b) rp <= #1 rp + 4'h1;
else
if(re & !m16b) rp <= #1 rp + 4'h2;
always @(posedge clk)
status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
wire [3:0] rp_p1 = rp[3:0] + 4'h1;
always @(posedge clk)
empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);
// Fifo Output
assign dout_tmp = mem[ rp[2:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[1:0]] <= #1 din;
endmodule |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:7];
reg [3:0] wp;
reg [4:0] rp;
wire [3:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 4'h1;
always @(posedge clk)
if(!en) rp <= #1 5'h0;
else
if(re & m16b) rp <= #1 rp + 5'h1;
else
if(re & !m16b) rp <= #1 rp + 5'h2;
always @(posedge clk)
status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;
wire [4:0] rp_p1 = rp[4:0] + 5'h1;
always @(posedge clk)
empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);
// Fifo Output
assign dout_tmp = mem[ rp[3:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[2:0]] <= #1 din;
endmodule |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:15];
reg [4:0] wp;
reg [5:0] rp;
wire [4:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 5'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 4'h1;
always @(posedge clk)
if(!en) rp <= #1 6'h0;
else
if(re & m16b) rp <= #1 rp + 6'h1;
else
if(re & !m16b) rp <= #1 rp + 6'h2;
always @(posedge clk)
status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;
wire [5:0] rp_p1 = rp[5:0] + 6'h1;
always @(posedge clk)
empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);
// Fifo Output
assign dout_tmp = mem[ rp[4:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[3:0]] <= #1 din;
endmodule |
module lpm_ff_v1 (
clock,
data,
q);
input clock;
input [63:0] data;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
lpm_ff lpm_ff_component (
.clock (clock),
.data (data),
.q (sub_wire0)
// synopsys translate_off
,
.aclr (),
.aload (),
.aset (),
.enable (),
.sclr (),
.sload (),
.sset ()
// synopsys translate_on
);
defparam
lpm_ff_component.lpm_fftype = "DFF",
lpm_ff_component.lpm_type = "LPM_FF",
lpm_ff_component.lpm_width = 64;
endmodule |
module sky130_fd_sc_hdll__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module axi_ad9152_channel (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
input [63:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [63:0] dac_pn23_data = 'd0;
reg [63:0] dac_pn31_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_phase_2_0 = 'd0;
reg [15:0] dac_dds_phase_2_1 = 'd0;
reg [15:0] dac_dds_phase_3_0 = 'd0;
reg [15:0] dac_dds_phase_3_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [63:0] dac_dds_data = 'd0;
// internal signals
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_data_2_s;
wire [15:0] dac_dds_data_3_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
// pn7 function
function [63:0] pn7;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 7] ^ din[ 6];
dout[62] = din[ 6] ^ din[ 5];
dout[61] = din[ 5] ^ din[ 4];
dout[60] = din[ 4] ^ din[ 3];
dout[59] = din[ 3] ^ din[ 2];
dout[58] = din[ 2] ^ din[ 1];
dout[57] = din[ 1] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
dout[55] = din[ 7] ^ din[ 5];
dout[54] = din[ 6] ^ din[ 4];
dout[53] = din[ 5] ^ din[ 3];
dout[52] = din[ 4] ^ din[ 2];
dout[51] = din[ 3] ^ din[ 1];
dout[50] = din[ 2] ^ din[ 0];
dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
dout[39] = din[ 7] ^ din[ 3];
dout[38] = din[ 6] ^ din[ 2];
dout[37] = din[ 5] ^ din[ 1];
dout[36] = din[ 4] ^ din[ 0];
dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
dout[ 9] = din[ 7] ^ din[ 0];
dout[ 8] = din[ 7];
dout[ 7] = din[ 6];
dout[ 6] = din[ 5];
dout[ 5] = din[ 4];
dout[ 4] = din[ 3];
dout[ 3] = din[ 2];
dout[ 2] = din[ 1];
dout[ 1] = din[ 0];
dout[ 0] = din[ 7] ^ din[ 6];
pn7 = dout;
end
endfunction
// pn15 function
function [63:0] pn15;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[15] ^ din[14];
dout[62] = din[14] ^ din[13];
dout[61] = din[13] ^ din[12];
dout[60] = din[12] ^ din[11];
dout[59] = din[11] ^ din[10];
dout[58] = din[10] ^ din[ 9];
dout[57] = din[ 9] ^ din[ 8];
dout[56] = din[ 8] ^ din[ 7];
dout[55] = din[ 7] ^ din[ 6];
dout[54] = din[ 6] ^ din[ 5];
dout[53] = din[ 5] ^ din[ 4];
dout[52] = din[ 4] ^ din[ 3];
dout[51] = din[ 3] ^ din[ 2];
dout[50] = din[ 2] ^ din[ 1];
dout[49] = din[ 1] ^ din[ 0];
dout[48] = din[ 0] ^ din[15] ^ din[14];
dout[47] = din[15] ^ din[13];
dout[46] = din[14] ^ din[12];
dout[45] = din[13] ^ din[11];
dout[44] = din[12] ^ din[10];
dout[43] = din[11] ^ din[ 9];
dout[42] = din[10] ^ din[ 8];
dout[41] = din[ 9] ^ din[ 7];
dout[40] = din[ 8] ^ din[ 6];
dout[39] = din[ 7] ^ din[ 5];
dout[38] = din[ 6] ^ din[ 4];
dout[37] = din[ 5] ^ din[ 3];
dout[36] = din[ 4] ^ din[ 2];
dout[35] = din[ 3] ^ din[ 1];
dout[34] = din[ 2] ^ din[ 0];
dout[33] = din[ 1] ^ din[15] ^ din[14];
dout[32] = din[ 0] ^ din[14] ^ din[13];
dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
dout[16] = din[ 0] ^ din[15] ^ din[12];
dout[15] = din[15] ^ din[11];
dout[14] = din[14] ^ din[10];
dout[13] = din[13] ^ din[ 9];
dout[12] = din[12] ^ din[ 8];
dout[11] = din[11] ^ din[ 7];
dout[10] = din[10] ^ din[ 6];
dout[ 9] = din[ 9] ^ din[ 5];
dout[ 8] = din[ 8] ^ din[ 4];
dout[ 7] = din[ 7] ^ din[ 3];
dout[ 6] = din[ 6] ^ din[ 2];
dout[ 5] = din[ 5] ^ din[ 1];
dout[ 4] = din[ 4] ^ din[ 0];
dout[ 3] = din[ 3] ^ din[15] ^ din[14];
dout[ 2] = din[ 2] ^ din[14] ^ din[13];
dout[ 1] = din[ 1] ^ din[13] ^ din[12];
dout[ 0] = din[ 0] ^ din[12] ^ din[11];
pn15 = dout;
end
endfunction
// pn23 function
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[23] ^ din[18];
dout[62] = din[22] ^ din[17];
dout[61] = din[21] ^ din[16];
dout[60] = din[20] ^ din[15];
dout[59] = din[19] ^ din[14];
dout[58] = din[18] ^ din[13];
dout[57] = din[17] ^ din[12];
dout[56] = din[16] ^ din[11];
dout[55] = din[15] ^ din[10];
dout[54] = din[14] ^ din[ 9];
dout[53] = din[13] ^ din[ 8];
dout[52] = din[12] ^ din[ 7];
dout[51] = din[11] ^ din[ 6];
dout[50] = din[10] ^ din[ 5];
dout[49] = din[ 9] ^ din[ 4];
dout[48] = din[ 8] ^ din[ 3];
dout[47] = din[ 7] ^ din[ 2];
dout[46] = din[ 6] ^ din[ 1];
dout[45] = din[ 5] ^ din[ 0];
dout[44] = din[ 4] ^ din[23] ^ din[18];
dout[43] = din[ 3] ^ din[22] ^ din[17];
dout[42] = din[ 2] ^ din[21] ^ din[16];
dout[41] = din[ 1] ^ din[20] ^ din[15];
dout[40] = din[ 0] ^ din[19] ^ din[14];
dout[39] = din[23] ^ din[13];
dout[38] = din[22] ^ din[12];
dout[37] = din[21] ^ din[11];
dout[36] = din[20] ^ din[10];
dout[35] = din[19] ^ din[ 9];
dout[34] = din[18] ^ din[ 8];
dout[33] = din[17] ^ din[ 7];
dout[32] = din[16] ^ din[ 6];
dout[31] = din[15] ^ din[ 5];
dout[30] = din[14] ^ din[ 4];
dout[29] = din[13] ^ din[ 3];
dout[28] = din[12] ^ din[ 2];
dout[27] = din[11] ^ din[ 1];
dout[26] = din[10] ^ din[ 0];
dout[25] = din[ 9] ^ din[23] ^ din[18];
dout[24] = din[ 8] ^ din[22] ^ din[17];
dout[23] = din[ 7] ^ din[21] ^ din[16];
dout[22] = din[ 6] ^ din[20] ^ din[15];
dout[21] = din[ 5] ^ din[19] ^ din[14];
dout[20] = din[ 4] ^ din[18] ^ din[13];
dout[19] = din[ 3] ^ din[17] ^ din[12];
dout[18] = din[ 2] ^ din[16] ^ din[11];
dout[17] = din[ 1] ^ din[15] ^ din[10];
dout[16] = din[ 0] ^ din[14] ^ din[ 9];
dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
pn23 = dout;
end
endfunction
// pn31 function
function [63:0] pn31;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[31] ^ din[28];
dout[62] = din[30] ^ din[27];
dout[61] = din[29] ^ din[26];
dout[60] = din[28] ^ din[25];
dout[59] = din[27] ^ din[24];
dout[58] = din[26] ^ din[23];
dout[57] = din[25] ^ din[22];
dout[56] = din[24] ^ din[21];
dout[55] = din[23] ^ din[20];
dout[54] = din[22] ^ din[19];
dout[53] = din[21] ^ din[18];
dout[52] = din[20] ^ din[17];
dout[51] = din[19] ^ din[16];
dout[50] = din[18] ^ din[15];
dout[49] = din[17] ^ din[14];
dout[48] = din[16] ^ din[13];
dout[47] = din[15] ^ din[12];
dout[46] = din[14] ^ din[11];
dout[45] = din[13] ^ din[10];
dout[44] = din[12] ^ din[ 9];
dout[43] = din[11] ^ din[ 8];
dout[42] = din[10] ^ din[ 7];
dout[41] = din[ 9] ^ din[ 6];
dout[40] = din[ 8] ^ din[ 5];
dout[39] = din[ 7] ^ din[ 4];
dout[38] = din[ 6] ^ din[ 3];
dout[37] = din[ 5] ^ din[ 2];
dout[36] = din[ 4] ^ din[ 1];
dout[35] = din[ 3] ^ din[ 0];
dout[34] = din[ 2] ^ din[31] ^ din[28];
dout[33] = din[ 1] ^ din[30] ^ din[27];
dout[32] = din[ 0] ^ din[29] ^ din[26];
dout[31] = din[31] ^ din[25];
dout[30] = din[30] ^ din[24];
dout[29] = din[29] ^ din[23];
dout[28] = din[28] ^ din[22];
dout[27] = din[27] ^ din[21];
dout[26] = din[26] ^ din[20];
dout[25] = din[25] ^ din[19];
dout[24] = din[24] ^ din[18];
dout[23] = din[23] ^ din[17];
dout[22] = din[22] ^ din[16];
dout[21] = din[21] ^ din[15];
dout[20] = din[20] ^ din[14];
dout[19] = din[19] ^ din[13];
dout[18] = din[18] ^ din[12];
dout[17] = din[17] ^ din[11];
dout[16] = din[16] ^ din[10];
dout[15] = din[15] ^ din[ 9];
dout[14] = din[14] ^ din[ 8];
dout[13] = din[13] ^ din[ 7];
dout[12] = din[12] ^ din[ 6];
dout[11] = din[11] ^ din[ 5];
dout[10] = din[10] ^ din[ 4];
dout[ 9] = din[ 9] ^ din[ 3];
dout[ 8] = din[ 8] ^ din[ 2];
dout[ 7] = din[ 7] ^ din[ 1];
dout[ 6] = din[ 6] ^ din[ 0];
dout[ 5] = din[ 5] ^ din[31] ^ din[28];
dout[ 4] = din[ 4] ^ din[30] ^ din[27];
dout[ 3] = din[ 3] ^ din[29] ^ din[26];
dout[ 2] = din[ 2] ^ din[28] ^ din[25];
dout[ 1] = din[ 1] ^ din[27] ^ din[24];
dout[ 0] = din[ 0] ^ din[26] ^ din[23];
pn31 = dout;
end
endfunction
// dac data select
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h7: dac_data <= dac_pn31_data;
4'h6: dac_data <= dac_pn23_data;
4'h5: dac_data <= dac_pn15_data;
4'h4: dac_data <= dac_pn7_data;
4'h3: dac_data <= 64'd0;
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
dac_pat_data_2_s, dac_pat_data_1_s};
default: dac_data <= dac_dds_data;
endcase
end
// pn registers
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_pn7_data <= {64{1'd1}};
dac_pn15_data <= {64{1'd1}};
dac_pn23_data <= {64{1'd1}};
dac_pn31_data <= {64{1'd1}};
end else begin
dac_pn7_data <= pn7(dac_pn7_data);
dac_pn15_data <= pn15(dac_pn15_data);
dac_pn23_data <= pn23(dac_pn23_data);
dac_pn31_data <= pn31(dac_pn31_data);
end
end
// dds
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
dac_dds_data <= 64'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
dac_dds_data_1_s, dac_dds_data_0_s};
end
end
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_2_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_3_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_3_s));
end
endgenerate
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule |
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule |
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