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module sky130_fd_sc_ls__o32a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__o32a_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule |
module muladd_wrap (
input ck,
input [63:0] i_a, i_b, i_c,
input [6:0] i_htId,
input i_vld,
output [63:0] o_res,
output [6:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t19_res;
reg [6:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId, r_t7_htId, r_t8_htId, r_t9_htId, r_t10_htId, r_t11_htId, r_t12_htId, r_t13_htId, r_t14_htId, r_t15_htId, r_t16_htId, r_t17_htId, r_t18_htId, r_t19_htId, r_t20_htId;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld, r_t7_vld, r_t8_vld, r_t9_vld, r_t10_vld, r_t11_vld, r_t12_vld, r_t13_vld, r_t14_vld, r_t15_vld, r_t16_vld, r_t17_vld, r_t18_vld, r_t19_vld, r_t20_vld;
reg [63:0] r_t2_a, r_t3_a, r_t4_a, r_t5_a, r_t6_a, r_t7_a, r_t8_a, r_t9_a, r_t10_a, r_t11_a, r_t12_a, r_t13_a, r_t14_a, r_t15_a, r_t16_a, r_t17_a, r_t18_a, r_t19_a, r_t20_a;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_htId <= i_htId;
r_t2_vld <= i_vld;
r_t2_a <= i_a;
r_t3_htId <= r_t2_htId;
r_t3_vld <= r_t2_vld;
r_t3_a <= r_t2_a;
r_t4_htId <= r_t3_htId;
r_t4_vld <= r_t3_vld;
r_t4_a <= r_t3_a;
r_t5_htId <= r_t4_htId;
r_t5_vld <= r_t4_vld;
r_t5_a <= r_t4_a;
r_t6_htId <= r_t5_htId;
r_t6_vld <= r_t5_vld;
r_t6_a <= r_t5_a;
r_t7_htId <= r_t6_htId;
r_t7_vld <= r_t6_vld;
r_t7_a <= r_t6_a;
r_t8_htId <= r_t7_htId;
r_t8_vld <= r_t7_vld;
r_t8_a <= r_t7_a;
r_t9_htId <= r_t8_htId;
r_t9_vld <= r_t8_vld;
r_t9_a <= r_t8_a;
r_t10_htId <= r_t9_htId;
r_t10_vld <= r_t9_vld;
r_t10_a <= r_t9_a;
r_t11_htId <= r_t10_htId;
r_t11_vld <= r_t10_vld;
r_t11_a <= r_t10_a;
r_t12_htId <= r_t11_htId;
r_t12_vld <= r_t11_vld;
r_t12_a <= r_t11_a;
r_t13_htId <= r_t12_htId;
r_t13_vld <= r_t12_vld;
r_t13_a <= r_t12_a;
r_t14_htId <= r_t13_htId;
r_t14_vld <= r_t13_vld;
r_t14_a <= r_t13_a;
r_t15_htId <= r_t14_htId;
r_t15_vld <= r_t14_vld;
r_t15_a <= r_t14_a;
r_t16_htId <= r_t15_htId;
r_t16_vld <= r_t15_vld;
r_t16_a <= r_t15_a;
r_t17_htId <= r_t16_htId;
r_t17_vld <= r_t16_vld;
r_t17_a <= r_t16_a;
r_t18_htId <= r_t17_htId;
r_t18_vld <= r_t17_vld;
r_t18_a <= r_t17_a;
r_t19_htId <= r_t18_htId;
r_t19_vld <= r_t18_vld;
r_t19_a <= r_t18_a;
r_t20_htId <= r_t19_htId;
r_t20_vld <= r_t19_vld;
r_t20_a <= r_t19_a + c_t19_res;
end
// Black box instantiation
mul_64b_int multiplier (.clk(ck), .a(i_b), .b(i_c), .p(c_t19_res));
// Outputs
assign o_res = r_t20_a;
assign o_htId = r_t20_htId;
assign o_vld = r_t20_vld;
endmodule |
module OC_Buff(in, out);
input in;
output out;
assign out = in ? 1'bz : 1'b0;
endmodule |
module pluto_spi_stepper_opendrain(clk, SCK, MOSI, MISO, SSEL, nRESET, nPE, LED, nConfig, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig = 1'bZ, nPE;
output LED;
input [15:0] din;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
assign nPE = 1'b1;
reg Spolarity;
reg[13:0] real_dout;
output [13:0] dout = 14'bZ;
OC_Buff ocout[13:0](real_dout, dout);
wire[3:0] real_step;
output [3:0] step = 4'bZ;
OC_Buff ocstep[3:0](real_step ^ {4{Spolarity}}, step);
wire[3:0] real_dir;
output [3:0] dir = 4'bZ;
OC_Buff ocdir[3:0](real_dir, dir);
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
//**********************************************************************
// SPI zeugs
// synchronizing the handshakes
//
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
wire SCK_high = SCKr[1]; // SCK is high
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
wire MOSI_data = MOSI;
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
reg byte_received; // high when 8 bit has been received
reg [4:0] spibytecnt;
reg [7:0] data_recvd;
reg [7:0] data_sent;
reg [7:0] data_outbuf;
always @(posedge clk) begin
if(SSEL_startmessage) begin
//data_sent <= data_outbuf;
bitcnt <= 3'b000;
spibytecnt <= 5'b00000;
end
if(SSEL_active) begin
if(SCK_risingedge) begin
data_recvd <= {data_recvd[6:0], MOSI_data};
bitcnt <= bitcnt + 3'b001;
if(bitcnt==3'b000)
data_sent <= data_outbuf;
end
else if(SCK_fallingedge) begin
data_sent <= {data_sent[6:0], 1'b0};
if(bitcnt==3'b000) begin
spibytecnt <= spibytecnt + 5'b00001;
end
end
byte_received <= SCK_risingedge && (bitcnt==3'b111);
end
end
assign MISO = data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
reg [7:0] data_inbuf;
always @(posedge clk) begin
if(SSEL_active) begin
//------------------------------------------------- word 0
if(spibytecnt == 5'b00000) begin // 0
data_outbuf <= pos0[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel0[7:0]
end
else if(spibytecnt == 5'b00001) begin // 1
data_outbuf <= pos0[15:8];
if(byte_received)
vel0 <= {data_recvd,data_inbuf}; //vel0
end
else if(spibytecnt == 5'b00010) begin // 2
data_outbuf <= pos0[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel1[7:0]
end
else if(spibytecnt == 5'b00011) begin // 3
data_outbuf <= 8'b0;
if(byte_received)
vel1 <= {data_recvd,data_inbuf}; //vel1
end
//------------------------------------------------- word 1
else if(spibytecnt == 5'b00100) begin // 4
data_outbuf <= pos1[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel2[7:0]
end
else if(spibytecnt == 5'b00101) begin // 5
data_outbuf <= pos1[15:8];
if(byte_received)
vel2 <= {data_recvd,data_inbuf}; //vel2
end
else if(spibytecnt == 5'b00110) begin // 6
data_outbuf <= pos1[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel3[7:0]
end
else if(spibytecnt == 5'b00111) begin // 7
data_outbuf <= 8'b0;
if(byte_received)
vel3 <= {data_recvd,data_inbuf}; //vel3
end
//------------------------------------------------- word 2
else if(spibytecnt == 5'b01000) begin // 8
data_outbuf <= pos2[7:0];
if(byte_received)
data_inbuf <= data_recvd; //real_dout[7:0]
end
else if(spibytecnt == 5'b01001) begin // 9
data_outbuf <= pos2[15:8];
if(byte_received) begin
real_dout <= {data_recvd[5:0],data_inbuf}; //real_dout
end
end
else if(spibytecnt == 5'b01010) begin // 10
data_outbuf <= pos2[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd;
end
else if(spibytecnt == 5'b01011) begin // 11
data_outbuf <= 8'b0;
if(byte_received) begin
tap <= data_recvd[7:6];
steptime <= data_recvd[T-1:0];
Spolarity <= data_inbuf[7];
dirtime <= data_inbuf[T-1:0];
end
end
//------------------------------------------------- word 3
else if(spibytecnt == 5'b01100) data_outbuf <= pos3[7:0];
else if(spibytecnt == 5'b01101) data_outbuf <= pos3[15:8];
else if(spibytecnt == 5'b01110) data_outbuf <= pos3[W+F-1:16];
else if(spibytecnt == 5'b01111) data_outbuf <= 8'b0;
//------------------------------------------------- word 4
else if(spibytecnt == 5'b10000) data_outbuf <= din[7:0];
else if(spibytecnt == 5'b10001) data_outbuf <= din[15:8];
else if(spibytecnt == 5'b10010) data_outbuf <= 8'b0;
else if(spibytecnt == 5'b10011) data_outbuf <= 8'b0;
else data_outbuf <= spibytecnt;
end
end
assign LED = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign do_enable_wdt = data_recvd[6] & (spibytecnt == 5'b01001) & byte_received;
endmodule |
module RX_BITSLICE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CASCADE = "FALSE",
parameter DATA_TYPE = "DATA",
parameter integer DATA_WIDTH = 8,
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter integer DELAY_VALUE_EXT = 0,
parameter FIFO_SYNC_MODE = "FALSE",
parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REFCLK_FREQUENCY = 300.0,
parameter SIM_DEVICE = "ULTRASCALE",
parameter real SIM_VERSION = 2.0,
parameter UPDATE_MODE = "ASYNC",
parameter UPDATE_MODE_EXT = "ASYNC"
)(
output [8:0] CNTVALUEOUT,
output [8:0] CNTVALUEOUT_EXT,
output FIFO_EMPTY,
output FIFO_WRCLK_OUT,
output [7:0] Q,
output [39:0] RX_BIT_CTRL_OUT,
output [39:0] TX_BIT_CTRL_OUT,
input CE,
input CE_EXT,
input CLK,
input CLK_EXT,
input [8:0] CNTVALUEIN,
input [8:0] CNTVALUEIN_EXT,
input DATAIN,
input EN_VTC,
input EN_VTC_EXT,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input INC,
input INC_EXT,
input LOAD,
input LOAD_EXT,
input RST,
input RST_DLY,
input RST_DLY_EXT,
input [39:0] RX_BIT_CTRL_IN,
input [39:0] TX_BIT_CTRL_IN
);
// define constants
localparam MODULE_NAME = "RX_BITSLICE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
reg warning_flag = 1'b1;
`ifdef XIL_DR
`include "RX_BITSLICE_dr.v"
`else
localparam [40:1] CASCADE_REG = CASCADE;
localparam [112:1] DATA_TYPE_REG = DATA_TYPE;
localparam [31:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT;
localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE;
localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE;
localparam [31:0] DELAY_VALUE_EXT_REG = DELAY_VALUE_EXT;
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [0:0] IS_CLK_EXT_INVERTED_REG = IS_CLK_EXT_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_DLY_EXT_INVERTED_REG = IS_RST_DLY_EXT_INVERTED;
localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam real SIM_VERSION_REG = SIM_VERSION;
localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE;
localparam [48:1] UPDATE_MODE_EXT_REG = UPDATE_MODE_EXT;
`endif
localparam [0:0] DC_ADJ_EN_REG = 1'b0;
localparam [0:0] DC_ADJ_EN_EXT_REG = 1'b0;
localparam [40:1] DDR_DIS_DQS_REG = "TRUE";
localparam [40:1] FIFO_ENABLE_REG = "TRUE";
localparam [5:0] SPARE_REG = 6'b000000;
localparam [2:0] FDLY_REG = 3'b010;
localparam [2:0] FDLY_EXT_REG = 3'b010;
localparam [40:1] RX_Q4_ROUTETHRU_REG = "FALSE";
localparam [40:1] RX_Q5_ROUTETHRU_REG = "FALSE";
localparam [64:1] TBYTE_CTL_REG = "T";
localparam [40:1] TX_Q_ROUTETHRU_REG = "FALSE";
localparam [40:1] TX_T_OUT_ROUTETHRU_REG = "FALSE";
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
wire IS_CLK_EXT_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_DLY_EXT_INVERTED_BIN;
wire IS_RST_DLY_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire [63:0] REFCLK_FREQUENCY_BIN;
wire [63:0] SIM_VERSION_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire FIFO_EMPTY_out;
wire FIFO_WRCLK_OUT_out;
wire [39:0] RX_BIT_CTRL_OUT_out;
wire [39:0] TX_BIT_CTRL_OUT_out;
wire [7:0] Q_out;
wire [8:0] CNTVALUEOUT_EXT_out;
wire [8:0] CNTVALUEOUT_out;
wire FIFO_EMPTY_delay;
wire FIFO_WRCLK_OUT_delay;
wire [39:0] RX_BIT_CTRL_OUT_delay;
wire [39:0] TX_BIT_CTRL_OUT_delay;
wire [7:0] Q_delay;
wire [8:0] CNTVALUEOUT_EXT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CE_EXT_in;
wire CE_in;
wire CLK_EXT_in;
wire CLK_in;
wire DATAIN_in;
wire EN_VTC_EXT_in;
wire EN_VTC_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire INC_EXT_in;
wire INC_in;
wire LOAD_EXT_in;
wire LOAD_in;
wire OFD_CE_in;
wire RST_DLY_EXT_in;
wire RST_DLY_in;
wire RST_in;
wire RX_DATAIN1_in;
wire TX_RST_in;
wire T_in;
wire [39:0] RX_BIT_CTRL_IN_in;
wire [39:0] TX_BIT_CTRL_IN_in;
wire [7:0] TX_D_in;
wire [8:0] CNTVALUEIN_EXT_in;
wire [8:0] CNTVALUEIN_in;
wire CE_EXT_delay;
wire CE_delay;
wire CLK_EXT_delay;
wire CLK_delay;
wire DATAIN_delay;
wire EN_VTC_EXT_delay;
wire EN_VTC_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire INC_EXT_delay;
wire INC_delay;
wire LOAD_EXT_delay;
wire LOAD_delay;
wire RST_DLY_EXT_delay;
wire RST_DLY_delay;
wire RST_delay;
wire [39:0] RX_BIT_CTRL_IN_delay;
wire [39:0] TX_BIT_CTRL_IN_delay;
wire [8:0] CNTVALUEIN_EXT_delay;
wire [8:0] CNTVALUEIN_delay;
wire IDELAY_DATAIN0_out;
wire IDELAY_DATAOUT_out;
assign #(out_delay) CNTVALUEOUT = (EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : CNTVALUEOUT_delay;
assign #(out_delay) CNTVALUEOUT_EXT = CNTVALUEOUT_EXT_delay;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay;
assign #(out_delay) Q = Q_delay;
assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay;
assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_EXT_delay = CLK_EXT;
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) CE_EXT_delay = CE_EXT;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_EXT_delay = CNTVALUEIN_EXT;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(in_delay) INC_EXT_delay = INC_EXT;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_EXT_delay = LOAD_EXT;
assign #(in_delay) LOAD_delay = LOAD;
`endif
// inputs with no timing checks
assign #(in_delay) DATAIN_delay = DATAIN;
assign #(in_delay) EN_VTC_EXT_delay = EN_VTC_EXT;
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) RST_DLY_EXT_delay = RST_DLY_EXT;
assign #(in_delay) RST_DLY_delay = RST_DLY;
assign #(in_delay) RST_delay = RST;
assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN;
assign #(in_delay) TX_BIT_CTRL_IN_delay = TX_BIT_CTRL_IN;
assign CNTVALUEOUT_EXT_delay = CNTVALUEOUT_EXT_out;
assign CNTVALUEOUT_delay = CNTVALUEOUT_out;
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out;
assign Q_delay = Q_out;
assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out;
assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out;
assign CE_EXT_in = CE_EXT_delay;
assign CE_in = CE_delay;
assign CLK_EXT_in = CLK_EXT_delay ^ IS_CLK_EXT_INVERTED_BIN;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CNTVALUEIN_EXT_in = CNTVALUEIN_EXT_delay;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign DATAIN_in = DATAIN_delay;
assign EN_VTC_EXT_in = EN_VTC_EXT_delay;
assign EN_VTC_in = EN_VTC_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign INC_EXT_in = INC_EXT_delay;
assign INC_in = INC_delay;
assign LOAD_EXT_in = LOAD_EXT_delay;
assign LOAD_in = LOAD_delay;
assign RST_DLY_EXT_in = RST_DLY_EXT_delay ^ IS_RST_DLY_EXT_INVERTED_BIN;
assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay;
assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay;
assign IS_CLK_EXT_INVERTED_BIN = IS_CLK_EXT_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_DLY_EXT_INVERTED_BIN = IS_RST_DLY_EXT_INVERTED_REG;
assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @(EN_VTC_in) begin
if (EN_VTC_in ===0 && DELAY_FORMAT_REG == "TIME" && warning_flag === 1'b1 ) begin
$display("Warning: [Unisim %s-1] BISC Calibration : DELAY_FORMAT set to TIME with EN_VTC signal set to 0. In hardware, when the EN_VTC signal is low during the initial calibration process, the BISC will never complete and the DLY_RDY and VTC_RDY status signals from the BITSLICE_CONTROL remain low. Simulation will not reflect this behavior. In simulation, the DLY_RDY and VTC_RDY from the BITSLICE_CONTROL will assert high. You should ensure the EN_VTC signal is held high during initial BISC self calibration to ensure BISC completes in hardware. See Select IO Userguide UG571 for more information.Instance: %m", MODULE_NAME);
warning_flag = 1'b0;
end
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CASCADE_REG != "FALSE") &&
(CASCADE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-101] CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CASCADE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATA_TYPE_REG != "DATA") &&
(DATA_TYPE_REG != "CLOCK") &&
(DATA_TYPE_REG != "DATA_AND_CLOCK") &&
(DATA_TYPE_REG != "SERIAL"))) begin
$display("Error: [Unisim %s-102] DATA_TYPE attribute is set to %s. Legal values for this attribute are DATA, CLOCK, DATA_AND_CLOCK or SERIAL. Instance: %m", MODULE_NAME, DATA_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-103] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DELAY_FORMAT_REG != "TIME") &&
(DELAY_FORMAT_REG != "COUNT"))) begin
$display("Error: [Unisim %s-107] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DELAY_TYPE_REG != "FIXED") &&
(DELAY_TYPE_REG != "VAR_LOAD") &&
(DELAY_TYPE_REG != "VARIABLE"))) begin
$display("Error: [Unisim %s-108] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin
$display("Error: [Unisim %s-109] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin
$display("Error: [Unisim %s-109] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_EXT_REG < 0) || (DELAY_VALUE_EXT_REG > 1250)))) begin
$display("Error: [Unisim %s-110] DELAY_VALUE_EXT attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_EXT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_EXT_REG < 0) || (DELAY_VALUE_EXT_REG > 1100)))) begin
$display("Error: [Unisim %s-110] DELAY_VALUE_EXT attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_EXT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-113] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin
$display("Error: [Unisim %s-119] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin
$display("Error: [Unisim %s-119] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-122] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-123] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((UPDATE_MODE_REG != "ASYNC") &&
(UPDATE_MODE_REG != "MANUAL") &&
(UPDATE_MODE_REG != "SYNC"))) begin
$display("Error: [Unisim %s-127] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((UPDATE_MODE_EXT_REG != "ASYNC") &&
(UPDATE_MODE_EXT_REG != "MANUAL") &&
(UPDATE_MODE_EXT_REG != "SYNC"))) begin
$display("Error: [Unisim %s-128] UPDATE_MODE_EXT attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_EXT_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign IFD_CE_in = 1'b0; // tie off
assign OFD_CE_in = 1'b0; // tie off
assign RX_DATAIN1_in = 1'b0; // tie off
assign TX_D_in = 8'b00000000; // tie off
assign TX_RST_in = 1'b0; // tie off
assign T_in = 1'b1; // tie off
generate
if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1
SIP_RX_BITSLICE_D1 SIP_RX_BITSLICE_INST (
.CASCADE (CASCADE_REG),
.DATA_TYPE (DATA_TYPE_REG),
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DC_ADJ_EN_EXT (DC_ADJ_EN_EXT_REG),
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.DELAY_VALUE_EXT (DELAY_VALUE_EXT_REG),
.FDLY (FDLY_REG),
.FDLY_EXT (FDLY_EXT_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.TBYTE_CTL (TBYTE_CTL_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.UPDATE_MODE (UPDATE_MODE_REG),
.UPDATE_MODE_EXT (UPDATE_MODE_EXT_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.CNTVALUEOUT (CNTVALUEOUT_out),
.CNTVALUEOUT_EXT (CNTVALUEOUT_EXT_out),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.CE (CE_in),
.CE_EXT (CE_EXT_in),
.CLK (CLK_in),
.CLK_EXT (CLK_EXT_in),
.CNTVALUEIN (CNTVALUEIN_in),
.CNTVALUEIN_EXT (CNTVALUEIN_EXT_in),
.DATAIN (DATAIN_in),
.EN_VTC (EN_VTC_in),
.EN_VTC_EXT (EN_VTC_EXT_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.INC (INC_in),
.INC_EXT (INC_EXT_in),
.LOAD (LOAD_in),
.LOAD_EXT (LOAD_EXT_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.RST_DLY_EXT (RST_DLY_EXT_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.T (T_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_D (TX_D_in),
.TX_RST (TX_RST_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.SPARE(SPARE_REG),
.FIFO_ENABLE(FIFO_ENABLE_REG),
.GSR (glblGSR)
);
end else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1
SIP_RX_BITSLICE_K2 SIP_RX_BITSLICE_INST (
.CASCADE (CASCADE_REG),
.DATA_TYPE (DATA_TYPE_REG),
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DC_ADJ_EN_EXT (DC_ADJ_EN_EXT_REG),
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.DELAY_VALUE_EXT (DELAY_VALUE_EXT_REG),
.FDLY (FDLY_REG),
.FDLY_EXT (FDLY_EXT_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.SIM_VERSION (SIM_VERSION_BIN),
.TBYTE_CTL (TBYTE_CTL_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.UPDATE_MODE (UPDATE_MODE_REG),
.UPDATE_MODE_EXT (UPDATE_MODE_EXT_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.CNTVALUEOUT (CNTVALUEOUT_out),
.CNTVALUEOUT_EXT (CNTVALUEOUT_EXT_out),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.CE (CE_in),
.CE_EXT (CE_EXT_in),
.CLK (CLK_in),
.CLK_EXT (CLK_EXT_in),
.CNTVALUEIN (CNTVALUEIN_in),
.CNTVALUEIN_EXT (CNTVALUEIN_EXT_in),
.DATAIN (DATAIN_in),
.EN_VTC (EN_VTC_in),
.EN_VTC_EXT (EN_VTC_EXT_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.INC (INC_in),
.INC_EXT (INC_EXT_in),
.LOAD (LOAD_in),
.LOAD_EXT (LOAD_EXT_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.RST_DLY_EXT (RST_DLY_EXT_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.T (T_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_D (TX_D_in),
.TX_RST (TX_RST_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.GSR (glblGSR)
);
end
endgenerate
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
wire clk_ext_en_n;
wire clk_ext_en_p;
assign clk_en_n = IS_CLK_INVERTED_BIN;
assign clk_en_p = ~IS_CLK_INVERTED_BIN;
assign clk_ext_en_n = IS_CLK_EXT_INVERTED_BIN;
assign clk_ext_en_p = ~IS_CLK_EXT_INVERTED_BIN;
`endif
specify
(CLK *> CNTVALUEOUT) = (100:100:100, 100:100:100);
(CLK_EXT *> CNTVALUEOUT_EXT) = (100:100:100, 100:100:100);
(DATAIN *> Q) = (0:0:0, 0:0:0);
(DATAIN *> RX_BIT_CTRL_OUT) = (0:0:0, 0:0:0);
(FIFO_RD_CLK *> Q) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => FIFO_EMPTY) = (100:100:100, 100:100:100);
(RX_BIT_CTRL_IN *> FIFO_WRCLK_OUT) = (0:0:0, 0:0:0);
// (FIFO_WRCLK_OUT => FIFO_EMPTY) = (0:0:0, 0:0:0); // error prop output to output
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLK_EXT, 0:0:0, notifier);
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (negedge RX_BIT_CTRL_IN[20], 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLK_EXT, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge RX_BIT_CTRL_IN[20], 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay);
$setuphold (negedge CLK_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CE_EXT_delay);
$setuphold (negedge CLK_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (negedge CLK_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, INC_EXT_delay);
$setuphold (negedge CLK_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (negedge CLK_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CE_EXT_delay);
$setuphold (negedge CLK_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (negedge CLK_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, INC_EXT_delay);
$setuphold (negedge CLK_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay);
$setuphold (posedge CLK_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CE_EXT_delay);
$setuphold (posedge CLK_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (posedge CLK_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, INC_EXT_delay);
$setuphold (posedge CLK_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge CLK_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CE_EXT_delay);
$setuphold (posedge CLK_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (posedge CLK_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, INC_EXT_delay);
$setuphold (posedge CLK_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLK_EXT, 0:0:0, 0, notifier);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (negedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK_EXT, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module sky130_fd_sc_hs__nand4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__nand4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule |
module scorecopymux (
data0x,
data1x,
data2x,
data3x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input [3:0] data2x;
input [3:0] data3x;
input [1:0] sel;
output [3:0] result;
endmodule |
module sky130_fd_sc_hd__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module fifo(datain, rd, wr, rst, clk, full, empty,led_n,wei);
input [3:0] datain;
input rd, wr, rst, clk;
output [6:0] led_n;
output full, empty, wei;
reg [3:0] dataout;
reg full_in, empty_in,wei_in,div;
reg [3:0] mem [15:0];
reg [23:0]cnt;
reg [3:0] rp, wp;
reg [6:0] led_n;
assign full = full_in;
assign empty = empty_in;
assign wei=wei_in;
parameter
reg0=7'b0000001,
reg1=7'b1001111,
reg2=7'b0010010,
reg3=7'b0000110,
reg4=7'b1001100,
reg5=7'b0100100,
reg6=7'b0100000,
reg7=7'b0001101,
reg8=7'b0000000,
reg9=7'b0000100,
rega=7'b0001000,
regb=7'b1100000,
regc=7'b0110001,
regd=7'b1000010,
rege=7'b0110000,
regf=7'b0111000;
// memory read out
//assign dataout = mem[rp];
// memory write in
always@(posedge clk)
begin
if(cnt==24'b111111111111111111111111)
begin
div=~div;
cnt<=0;
end
else
begin
cnt<=cnt+1;
end
end
always@(posedge clk)
begin
wei_in<=1'b0;
end
always@(posedge div)
begin
if(~wr && ~full_in)
mem[wp]<=datain;
end
// memory write pointer increment
always@(posedge div)
begin
if(!rst)
wp<=0;
else
begin
if(~wr && ~full_in)
wp<= wp+1'b1;
end
end
// memory read pointer increment
always@(posedge div)
begin
if(!rst)
rp <= 0;
else
begin
if(~rd && ~empty_in)
rp <= rp + 1'b1;
end
end
// Full signal generate
always@(posedge div)
begin
if(!rst)
full_in <= 1'b0;
else
begin
if(rd && ~wr)
begin
if((wp==rp-1)||(rp==4'h0&&wp==4'hf))
full_in <= 1'b1;
end
else if(full_in && ~rd)
full_in <= 1'b0;
end
end
// Empty signal generate
always@(posedge div )
begin
if(!rst)
empty_in <= 1'b1;
else
begin
if(~rd&&wr)
begin
if(rp==wp-1 || (rp==4'hf&&wp==4'h0))
empty_in<=1'b1;
end
else if(empty_in && ~wr)
empty_in<=1'b0;
end
end
always@(posedge div)
begin
if(~rd && ~empty_in)
dataout<=mem[rp];
case(dataout)
4'h0: led_n<=reg0;
4'h1: led_n<=reg1;
4'h2: led_n<=reg2;
4'h3: led_n<=reg3;
4'h4: led_n<=reg4;
4'h5: led_n<=reg5;
4'h6: led_n<=reg6;
4'h7: led_n<=reg7;
4'h8: led_n<=reg8;
4'h9: led_n<=reg9;
4'ha: led_n<=rega;
4'hb: led_n<=regb;
4'hc: led_n<=regc;
4'hd: led_n<=regd;
4'he: led_n<=rege;
4'hf: led_n<=regf;
default:;
endcase
end
endmodule |
module outputs)
wire clear_spif; // From regs of spi_regs.v
wire clear_wcol; // From regs of spi_regs.v
wire rfre; // From regs of spi_regs.v
wire [7:0] spcr; // From regs of spi_regs.v
wire [7:0] sper; // From regs of spi_regs.v
wire [7:0] wfdin; // From regs of spi_regs.v
wire wfwe; // From regs of spi_regs.v
wire wr_spsr; // From regs of spi_regs.v
// End of automatics
spi_regs #(.BASE_ADDRESS(BASE_ADDRESS))
regs(/*AUTOINST*/
// Outputs
.temperature (temperature[15:0]),
.data_out (data_out[7:0]),
.wfwe (wfwe),
.rfre (rfre),
.wr_spsr (wr_spsr),
.clear_spif (clear_spif),
.clear_wcol (clear_wcol),
.wfdin (wfdin[7:0]),
.ncs_o (ncs_o),
.spcr (spcr[7:0]),
.sper (sper[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.port_id (port_id[7:0]),
.data_in (data_in[7:0]),
.read_strobe (read_strobe),
.write_strobe (write_strobe),
.rfdout (rfdout[7:0]),
.spsr (spsr[7:0]));
simple_spi_top_modified spi(
// Outputs
.spsr (spsr[7:0]),
.inta_o (interrupt),
.rfdout (rfdout[7:0]),
.sck_o (sck_o),
.mosi_o (mosi_o),
// Inputs
.clk_i (clk),
.nrst (~reset),
.spcr (spcr[7:0]),
.sper (sper[7:0]),
.wfwe (wfwe),
.rfre (rfre),
.wr_spsr (wr_spsr),
.clear_spif (clear_spif),
.clear_wcol (clear_wcol),
.wfdin (wfdin[7:0]),
.miso_i (miso_i));
endmodule |
module mig_7series_v2_0_data_gen_chk # (
parameter C_AXI_DATA_WIDTH = 32 // Width of the AXI write and read data
)
(
input clk,
input data_en,
input [2:0] data_pattern,
input pattern_init, // when high the patterns are initialized
input [31:0] prbs_seed_i,
input [C_AXI_DATA_WIDTH-1:0] rdata,
input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld,
input rdata_vld,
input wrd_cntr_rst,
output msmatch_err, // Indicates there is a mismatch error
output reg [7:0] wrd_cntr, // Word count output
output reg [31:0] data_o // generated data
);
reg [31:0] prbs;
reg [32:1] lfsr_q;
reg [31:0] walk0;
reg [31:0] walk1;
reg [C_AXI_DATA_WIDTH/32-1:0] msmatch_err_sig;
//*****************************************************************************
// Data generate segment
//*****************************************************************************
always @ (posedge clk) begin
if (pattern_init) begin
lfsr_q <= {prbs_seed_i + 32'h55555555};
end
else if (data_en) begin
lfsr_q[32:9] <= lfsr_q[31:8];
lfsr_q[8] <= lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= lfsr_q[5:3];
lfsr_q[3] <= lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= lfsr_q[1] ;
lfsr_q[1] <= lfsr_q[32];
end
end
always @(posedge clk)
if (pattern_init)
walk0 <= 32'hFFFF_FFFE;
else if (data_en)
walk0 <= {walk0[30:0],walk0[31]};
always @(posedge clk)
if (pattern_init)
walk1 <= 32'h0000_0001;
else if (data_en)
walk1 <= {walk1[30:0],walk1[31]};
always @(*) begin
prbs = lfsr_q[32:1];
end
always @(*) begin
case (data_pattern)
3'b001: data_o = prbs; // PRBS pattern
3'b010: data_o = walk0; // Walking zeros
3'b011: data_o = walk1; // Walking ones
3'b100: data_o = 32'hFFFF_FFFF; // All ones
3'b101: data_o = 32'h0000_0000; // All zeros
default: data_o = 32'h5A5A_A5A5;
endcase
end
//*****************************************************************************
// Data check segment
//*****************************************************************************
always @(posedge clk)
if (wrd_cntr_rst)
wrd_cntr <= 8'h00;
else if (rdata_vld)
wrd_cntr <= wrd_cntr + 8'h01;
genvar i;
generate
begin: data_check
for (i = 0; i <= (C_AXI_DATA_WIDTH/32-1); i=i+1) begin: gen_data_check
always @(posedge clk)
if (wrd_cntr_rst)
msmatch_err_sig[i] <= 1'b0;
else if (rdata_vld &
((rdata[((i*32)+7):i*32] != data_o[7:0] & rdata_bvld[(i*4)]) |
(rdata[((i*32)+15):((i*32)+8)] != data_o[15:8] & rdata_bvld[(i*4)+1]) |
(rdata[((i*32)+23):((i*32)+16)] != data_o[23:16] & rdata_bvld[(i*4)+2]) |
(rdata[((i*32)+31):((i*32)+24)] != data_o[31:24] & rdata_bvld[(i*4)+3])))
msmatch_err_sig[i] <= 1'b1;
else
msmatch_err_sig[i] <= 1'b0;
end
end
endgenerate
assign msmatch_err = |msmatch_err_sig;
// synthesis translate_off
//*****************************************************************************
// Simulation debug signals and messages
//*****************************************************************************
always @(posedge clk) begin
if (rdata_vld & ({{C_AXI_DATA_WIDTH/32}{data_o}} !== rdata)) begin
$display ("[ERROR] : Written data and read data does not match");
$display ("Data written : %h", {{C_AXI_DATA_WIDTH/32}{data_o}});
$display ("Data read : %h", rdata);
$display ("Word number : %h", wrd_cntr);
$display ("Simulation time : %t", $time);
end
end
// synthesis translate_on
endmodule |
module ps2_keyb(
input wire clk,
inout wire clkps2,
inout wire dataps2,
//---------------------------------
input wire [8:0] rows,
output wire [7:0] cols,
output wire rst_out_n,
output wire nmi_out_n,
output wire mrst_out_n,
output wire [1:0] user_toggles,
//---------------------------------
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire regaddr_changed,
input wire [7:0] din,
output wire [7:0] keymap_dout,
output wire oe_n_keymap,
output wire [7:0] scancode_dout,
output wire oe_n_scancode,
output reg [7:0] kbstatus_dout,
output wire oe_n_kbstatus
);
parameter SCANCODE = 8'h04;
parameter KBSTATUS = 8'h05;
parameter KEYMAP = 8'h07;
wire master_reset, user_reset, user_nmi;
assign mrst_out_n = ~master_reset;
assign rst_out_n = ~user_reset;
assign nmi_out_n = ~user_nmi;
assign oe_n_keymap = ~(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1);
assign oe_n_scancode = ~(zxuno_addr == SCANCODE && zxuno_regrd == 1'b1);
assign oe_n_kbstatus = ~(zxuno_addr == KBSTATUS && zxuno_regrd == 1'b1);
wire [7:0] kbcode;
wire ps2busy;
wire kberror;
wire nueva_tecla;
wire extended;
wire released;
assign scancode_dout = kbcode;
wire teclado_limpio;
/*
| BSY | x | x | x | ERR | RLS | EXT | PEN |
*/
reg reading_kbstatus = 1'b0;
always @(posedge clk) begin
kbstatus_dout[7:1] <= {ps2busy, 3'b000, kberror, released, extended};
if (nueva_tecla == 1'b1)
kbstatus_dout[0] <= 1'b1;
if (oe_n_kbstatus == 1'b0)
reading_kbstatus <= 1'b1;
else if (reading_kbstatus == 1'b1) begin
kbstatus_dout[0] <= 1'b0;
reading_kbstatus <= 1'b0;
end
end
ps2_port lectura_de_teclado (
.clk(clk),
.enable_rcv(~ps2busy),
.kb_or_mouse(1'b0),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(nueva_tecla),
.scancode(kbcode),
.released(released),
.extended(extended)
);
scancode_to_sam traductor (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scan(kbcode),
.extended(extended),
.released(released),
.kbclean(teclado_limpio),
.sam_row(rows),
.sam_col(cols),
.master_reset(master_reset),
.user_reset(user_reset),
.user_nmi(user_nmi),
.user_toggles(user_toggles),
.din(din),
.dout(keymap_dout),
.cpuwrite(zxuno_addr == KEYMAP && zxuno_regwr == 1'b1),
.cpuread(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1),
.rewind(regaddr_changed == 1'b1 && zxuno_addr == KEYMAP)
);
keyboard_pressed_status comprueba_teclado_limpio (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scancode(kbcode),
.extended(extended),
.released(released),
.kbclean(teclado_limpio)
);
ps2_host_to_kb escritura_a_teclado (
.clk(clk),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.data(din),
.dataload(zxuno_addr == SCANCODE && zxuno_regwr== 1'b1),
.ps2busy(ps2busy),
.ps2error(kberror)
);
endmodule |
module sky130_fd_sc_hs__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module *
* *
**********************************************************************************/
endmodule |
module SPImaster(
rst,
clk,
start,
rxdata,
done,
transmit,
txdata,
x_axis_data,
y_axis_data,
z_axis_data
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input rst;
input clk;
input start;
input [7:0] rxdata;
input done;
output transmit;
output [15:0] txdata;
output [9:0] x_axis_data;
output [9:0] y_axis_data;
output [9:0] z_axis_data;
// ====================================================================================
// Parameters, Register, and Wires
// ====================================================================================
reg [15:0] txdata;
reg [9:0] x_axis_data;
reg [9:0] y_axis_data;
reg [9:0] z_axis_data;
reg transmit;
// Define FSM states
parameter [2:0] state_type_idle = 3'd0,
state_type_configure = 3'd1,
state_type_transmitting = 3'd2,
state_type_recieving = 3'd3,
state_type_finished = 3'd4,
state_type_break = 3'd5,
state_type_holding = 3'd6;
// STATE reg
reg [2:0] STATE;
parameter [1:0] data_type_x_axis = 2'd0,
data_type_y_axis = 2'd1,
data_type_z_axis = 2'd2;
reg [1:0] DATA;
parameter [1:0] configure_type_powerCtl = 0,
configure_type_bwRate = 1,
configure_type_dataFormat = 2;
reg [1:0] CONFIGUREsel;
//Setting up Configuration Registers
//POWER_CTL Bits 0x2D
parameter [15:0] POWER_CTL = 16'h2D08;
//BW_RATE Bits 0x2C
parameter [15:0] BW_RATE = 16'h2C08;
//CONFIG Bits 0x31
parameter [15:0] DATA_FORMAT = 16'h3100;
//Axis registers set to only read and do it in single byte increments
parameter [15:0] xAxis0 = 16'hB200; //10110010;
parameter [15:0] xAxis1 = 16'hB300; //10110011;
parameter [15:0] yAxis0 = 16'hB400; //10110100;
parameter [15:0] yAxis1 = 16'hB500; //10110101;
parameter [15:0] zAxis0 = 16'hB600; //10110110;
parameter [15:0] zAxis1 = 16'hB700; //10110111;
reg [11:0] break_count;
reg [20:0] hold_count;
reg end_configure;
reg done_configure;
reg register_select;
reg finish;
reg sample_done;
reg [3:0] prevstart;
// ===================================================================================
// Implementation
// ===================================================================================
//-----------------------------------------------
// Master Controller
//-----------------------------------------------
always @(posedge clk)
begin: spi_masterProcess
begin
// Debounce Start Button
prevstart <= {prevstart[2:0], start};
//Reset Condition
if (rst == 1'b1) begin
transmit <= 1'b0;
STATE <= state_type_idle;
DATA <= data_type_x_axis;
break_count <= 12'h000;
hold_count <= 21'b000000000000000000000;
done_configure <= 1'b0;
CONFIGUREsel <= configure_type_powerCtl;
txdata <= 16'h0000;
register_select <= 1'b0;
sample_done <= 1'b0;
finish <= 1'b0;
x_axis_data <= 10'b0000000000;
y_axis_data <= 10'b0000000000;
z_axis_data <= 10'b0000000000;
end_configure <= 1'b0;
end
else
//Main State, selects what the overall system is doing
case (STATE)
state_type_idle :
//If the system has not been configured, enter the configure state
if (done_configure == 1'b0) begin
STATE <= state_type_configure;
txdata <= POWER_CTL;
transmit <= 1'b1;
end
//If the system has been configured, enter the transmission state when start is asserted
else if (prevstart == 4'b0011 & start == 1'b1 & done_configure == 1'b1) begin
STATE <= state_type_transmitting;
finish <= 1'b0;
txdata <= xAxis0;
sample_done <= 1'b0;
end
state_type_configure :
//Substate of configure selects what configuration is output
case (CONFIGUREsel)
//Send power control address with desired configuration bits
configure_type_powerCtl : begin
STATE <= state_type_finished;
CONFIGUREsel <= configure_type_bwRate;
transmit <= 1'b1;
end
//Send band width rate address with desired configuration bits
configure_type_bwRate : begin
txdata <= BW_RATE;
STATE <= state_type_finished;
CONFIGUREsel <= configure_type_dataFormat;
transmit <= 1'b1;
end
//Send data format address with desired configuration bits
configure_type_dataFormat : begin
txdata <= DATA_FORMAT;
STATE <= state_type_finished;
transmit <= 1'b1;
finish <= 1'b1;
end_configure <= 1'b1;
end
default :
;
endcase
//transmitting leads to the transmission of addresses of data to sample them
state_type_transmitting :
//Substate of transmitting selects which data register will be sampled
case (DATA)
//Selects the x_axis data
data_type_x_axis :
//register_select chooses which of the two registers for each axis
//will be sampled
case (register_select)
1'b0 :
begin
//in each case for data and register_select the state goes to
//recieving to accept data from SPIinterface and transmit goes
//high to begin the transmission of data to the ACL
STATE <= state_type_recieving;
transmit <= 1'b1;
end
default :
begin
STATE <= state_type_recieving;
transmit <= 1'b1;
end
endcase
data_type_y_axis :
case (register_select)
1'b0 :
begin
STATE <= state_type_recieving;
transmit <= 1'b1;
end
default :
begin
STATE <= state_type_recieving;
transmit <= 1'b1;
end
endcase
data_type_z_axis :
case (register_select)
1'b0 :
begin
STATE <= state_type_recieving;
transmit <= 1'b1;
end
default :
begin
STATE <= state_type_recieving;
transmit <= 1'b1;
end
endcase
default :
;
endcase
//recieving controls the flow of data into the spi_master
state_type_recieving :
//Substate of Recieving, DATA controls where data will be stored
case (DATA)
//Substate of DATA same as in transmitting
data_type_x_axis :
//register_select controls which half of the output register the
//collected data goes to
case (register_select)
1'b0 :
begin
//transmit de-asserted as transmission has already be begun
transmit <= 1'b0;
//when done is asserted, the register to be sampled next
//changes with txdata, data is assigned to the desired output,
//the overall state goes to finish, and register select is
//inverted to go to the other half. this same purpose is used
//throughout DATA in recieving
if (done == 1'b1)
begin
txdata <= xAxis1;
x_axis_data[7:0] <= rxdata[7:0];
STATE <= state_type_finished;
register_select <= 1'b1;
end
end
default :
begin
transmit <= 1'b0;
if (done == 1'b1)
begin
txdata <= yAxis0;
x_axis_data[9:8] <= rxdata[1:0];
register_select <= 1'b0;
DATA <= data_type_y_axis;
STATE <= state_type_finished;
end
end
endcase
data_type_y_axis :
case (register_select)
1'b0 :
begin
transmit <= 1'b0;
if (done == 1'b1)
begin
txdata <= yAxis1;
y_axis_data[7:0] <= rxdata[7:0];
register_select <= 1'b1;
STATE <= state_type_finished;
end
end
default :
begin
transmit <= 1'b0;
if (done == 1'b1)
begin
txdata <= zAxis0;
y_axis_data[9:8] <= rxdata[1:0];
register_select <= 1'b0;
DATA <= data_type_z_axis;
STATE <= state_type_finished;
end
end
endcase
data_type_z_axis :
case (register_select)
1'b0 :
begin
transmit <= 1'b0;
if (done == 1'b1)
begin
txdata <= zAxis1;
z_axis_data[7:0] <= rxdata[7:0];
register_select <= 1'b1;
STATE <= state_type_finished;
end
end
default :
begin
transmit <= 1'b0;
if (done == 1'b1)
begin
txdata <= xAxis0;
z_axis_data[9:8] <= rxdata[1:0];
register_select <= 1'b0;
DATA <= data_type_x_axis;
STATE <= state_type_finished;
sample_done <= 1'b1;
end
end
endcase
default :
;
endcase
//finished leads to the break state when transmission completed
state_type_finished :
begin
transmit <= 1'b0;
if (done == 1'b1)
begin
STATE <= state_type_break;
if (end_configure == 1'b1)
done_configure <= 1'b1;
end
end
//the break state keeps an idle state long enough between transmissions
//to satisfy timing requirements. break can be decreased if desired
state_type_break :
if (break_count == 12'hFFF)
begin
break_count <= 12'h000;
//only exit to idle if start has been de-asserted ( to keep from
//looping transmitting and recieving undesirably ) and finish and
//sample_done are high showing that the desired action has been
//completed
if ((finish == 1'b1 | sample_done == 1'b1) & start == 1'b0)
begin
STATE <= state_type_idle;
txdata <= xAxis0;
end
//if done configure is high, and sample done is low, the reception
//has not been completed so the state goes back to transmitting
else if (sample_done == 1'b1 & start == 1'b1)
STATE <= state_type_holding;
else if (done_configure == 1'b1 & sample_done == 1'b0)
begin
STATE <= state_type_transmitting;
transmit <= 1'b1;
end
//if the system has not finished configuration, then the state loops
//back to configure
else if (done_configure == 1'b0)
STATE <= state_type_configure;
end
else
break_count <= break_count + 1'b1;
state_type_holding :
if (hold_count == 24'h1FFFFF)
begin
hold_count <= 21'd0;
STATE <= state_type_transmitting;
sample_done <= 1'b0;
end
else if (start <= 1'b0)
begin
STATE <= state_type_idle;
hold_count <= 21'd0;
end
else begin
hold_count <= hold_count + 1'b1;
end
endcase
end
end
endmodule |
module mouse_painter(
input [4:0] line_number,
output reg [7:0] line_code
);
parameter [7:0] line00 = 8'h01;
parameter [7:0] line01 = 8'h03;
parameter [7:0] line02 = 8'h07;
parameter [7:0] line03 = 8'h0F;
parameter [7:0] line04 = 8'h1F;
parameter [7:0] line05 = 8'h3F;
parameter [7:0] line06 = 8'h7F;
parameter [7:0] line07 = 8'hFF;
parameter [7:0] line08 = 8'h07;
parameter [7:0] line09 = 8'h03;
parameter [7:0] line10 = 8'h01;
always @(*) begin
case(line_number)
4'b0000 : line_code = line00;
4'b0001 : line_code = line01;
4'b0010 : line_code = line02;
4'b0011 : line_code = line03;
4'b0100 : line_code = line04;
4'b0101 : line_code = line05;
4'b0110 : line_code = line06;
4'b0111 : line_code = line07;
4'b1000 : line_code = line08;
4'b1001 : line_code = line09;
4'b1010 : line_code = line10;
default : line_code = 1'b0;
endcase
end
endmodule |
module abc(
input clk,
input ce,
input [11:0] a,
input [11:0] b,
input [11:0] c,
output [24:0] y
);
wire signed [12:0] sum_ab;
wire signed [11:0] del_c;
// Latency = 2
delay_line #(
.DELAY(2),
.WIDTH(12)
) delay_c (
.clk(clk),
.ce(ce),
.in(c),
.out(del_c),
.rst(0)
);
// Latency = 2
sum summer_ab (
.a(a), // input [11 : 0] a
.b(b), // input [11 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(sum_ab) // output [12 : 0] s
);
//Latency = 3
mul multiplier_ab_c (
.a(del_c), // input [11 : 0] c
.b(sum_ab), // input [12 : 0] a + b
.clk(clk), // input clk
.ce(ce), // input ce
.p(y) // output [24 : 0] p
);
endmodule |
module level2arch (data_in,clk,nReset);
reg signed [15:0] cD_l2,cA_l2;
input [15:0] data_in;
input clk, nReset;
wire clk, nReset;
reg [15:0] data0, data1;
reg [2:0] count1;
reg [8:0] count2;
reg [8:0] count3;
reg [15:0] cD_store [0:`n2-2];
integer i;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
data0 <= #20 0;
data1 <= #20 0;
cD_l2 <= #20 0;
cA_l2 <= #20 0;
count1 <= #20 0;
count2 <= #20 `n2;
count3 <= #20 0;
for (i=0; i<=`n2-2; i=i+1)
cD_store[i] <= #20 0;
end
else
begin
if (count1 < 5 && count2 > 0)
begin
case (count1)
0 : begin
data0 <= #20 0;
data1 <= #20 0;
count1 <= #20 count1 + 1;
end
1 : begin
if (count2 > 0)
begin
count1 <= #20 count1 + 1;
data0 <= #20 data_in;
if (count3 != 0 && count3 < `n2)
cD_store[count3-1] <= #20 cD_l2;
else
cD_store[count3-1] <= #20 0;
end
end
2 : begin
if(count2 > 1)
begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
end
3 : begin
data1 <= #20 data_in;
count1 <= #20 count1 + 1;
end
4 : begin
cA_l2 <= #20 data0 + (data1 + data_in);
cD_l2 <= #20 data0 - (data1 + data_in);
count3 <= #20 count3 + 1;
count1 <= #20 1;
count2 <= #20 count2 - 1;
end
default : begin
data0 <= #20 0;
data1 <= #20 0;
end
endcase
end
else
count1 <= #20 1;
end
endmodule |
module LCD(
input clk,
input rst,
input [127:0] upRow,
input [127:0] doRow,
output e,
output rs,
output rw,
output [3:0] sf
);
reg [23:0] count = 0;
reg refresh;
reg [5:0] Code;
assign {e, rs, rw, sf} = {refresh, Code};
// count
always@(posedge clk, posedge rst)
begin
if(rst) count <= count;
else count <= (count[23:17] < 78) ? count+1 : 0;
end
// LCD
always@(posedge clk, posedge rst)
begin
if(rst) Code <= 6'h10;
else begin
case(count[23:17])
0 : Code <= 6'h03; // power-on
1 : Code <= 6'h03;
2 : Code <= 6'h03;
3 : Code <= 6'h02;
4 : Code <= 6'h02; // function set
5 : Code <= 6'h08;
6 : Code <= 6'h00; // entry
7 : Code <= 6'h06;
8 : Code <= 6'h00; // display on/off
9 : Code <= 6'h0C;
10: Code <= 6'h00; // clear display
11: Code <= 6'h01;
12: Code <= {2'b10,upRow[127:124]};
13: Code <= {2'b10,upRow[123:120]};
14: Code <= {2'b10,upRow[119:116]};
15: Code <= {2'b10,upRow[115:112]};
16: Code <= {2'b10,upRow[111:108]};
17: Code <= {2'b10,upRow[107:104]};
18: Code <= {2'b10,upRow[103:100]};
19: Code <= {2'b10,upRow[99 :96 ]};
20: Code <= {2'b10,upRow[95 :92 ]};
21: Code <= {2'b10,upRow[91 :88 ]};
22: Code <= {2'b10,upRow[87 :84 ]};
23: Code <= {2'b10,upRow[83 :80 ]};
24: Code <= {2'b10,upRow[79 :76 ]};
25: Code <= {2'b10,upRow[75 :72 ]};
26: Code <= {2'b10,upRow[71 :68 ]};
27: Code <= {2'b10,upRow[67 :64 ]};
28: Code <= {2'b10,upRow[63 :60 ]};
29: Code <= {2'b10,upRow[59 :56 ]};
30: Code <= {2'b10,upRow[55 :52 ]};
31: Code <= {2'b10,upRow[51 :48 ]};
32: Code <= {2'b10,upRow[47 :44 ]};
33: Code <= {2'b10,upRow[43 :40 ]};
34: Code <= {2'b10,upRow[39 :36 ]};
35: Code <= {2'b10,upRow[35 :32 ]};
36: Code <= {2'b10,upRow[31 :28 ]};
37: Code <= {2'b10,upRow[27 :24 ]};
38: Code <= {2'b10,upRow[23 :20 ]};
39: Code <= {2'b10,upRow[19 :16 ]};
40: Code <= {2'b10,upRow[15 :12 ]};
41: Code <= {2'b10,upRow[11 :8 ]};
42: Code <= {2'b10,upRow[7 :4 ]};
43: Code <= {2'b10,upRow[3 :0 ]};
44: Code <= 6'b001100;
45: Code <= 6'b000000;
46: Code <= {2'b10,doRow[127:124]};
47: Code <= {2'b10,doRow[123:120]};
48: Code <= {2'b10,doRow[119:116]};
49: Code <= {2'b10,doRow[115:112]};
50: Code <= {2'b10,doRow[111:108]};
51: Code <= {2'b10,doRow[107:104]};
52: Code <= {2'b10,doRow[103:100]};
53: Code <= {2'b10,doRow[99 :96 ]};
54: Code <= {2'b10,doRow[95 :92 ]};
55: Code <= {2'b10,doRow[91 :88 ]};
56: Code <= {2'b10,doRow[87 :84 ]};
57: Code <= {2'b10,doRow[83 :80 ]};
58: Code <= {2'b10,doRow[79 :76 ]};
59: Code <= {2'b10,doRow[75 :72 ]};
60: Code <= {2'b10,doRow[71 :68 ]};
61: Code <= {2'b10,doRow[67 :64 ]};
62: Code <= {2'b10,doRow[63 :60 ]};
63: Code <= {2'b10,doRow[59 :56 ]};
64: Code <= {2'b10,doRow[55 :52 ]};
65: Code <= {2'b10,doRow[51 :48 ]};
66: Code <= {2'b10,doRow[47 :44 ]};
67: Code <= {2'b10,doRow[43 :40 ]};
68: Code <= {2'b10,doRow[39 :36 ]};
69: Code <= {2'b10,doRow[35 :32 ]};
70: Code <= {2'b10,doRow[31 :28 ]};
71: Code <= {2'b10,doRow[27 :24 ]};
72: Code <= {2'b10,doRow[23 :20 ]};
73: Code <= {2'b10,doRow[19 :16 ]};
74: Code <= {2'b10,doRow[15 :12 ]};
75: Code <= {2'b10,doRow[11 :8 ]};
76: Code <= {2'b10,doRow[7 :4 ]};
77: Code <= {2'b10,doRow[3 :0 ]};
default: Code <= 6'h10;
endcase
end
end
// refresh
always@(posedge clk, posedge rst)
begin
if(rst) refresh <= 1;
else refresh <= count[16];
end
endmodule |
module cpu_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H0000000043c0000000000000416000000000000041200000),
.C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(3'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(3'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(3'H7),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module gpr_file(
input wire clock,
input wire reset,
input wire write_enable,
input wire[`REGS_ADDR_BUS] write_addr,
input wire[`REGS_DATA_BUS] write_data,
input wire read_enable1,
input wire[`REGS_ADDR_BUS] read_addr1,
output reg[`REGS_DATA_BUS] read_data1,
input wire read_enable2,
input wire[`REGS_ADDR_BUS] read_addr2,
output reg[`REGS_DATA_BUS] read_data2
);
reg[`REGS_DATA_BUS] regs[0:`REGS_NUM - 1];
always @ (posedge clock) begin
if (reset == `DISABLE && write_enable == `ENABLE && write_addr != `REGS_NUM_LOG'h0) begin
regs[write_addr] <= write_data;
end
end
always @ (*) begin
if (reset == `ENABLE) begin
read_data1 <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (read_addr1 == `REGS_NUM_LOG'h0) begin
read_data1 <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (write_enable == `ENABLE && read_enable1 == `ENABLE && read_addr1 == write_addr) begin
read_data1 <= write_data;
end else if (read_enable1 == `ENABLE) begin
read_data1 <= regs[read_addr1];
end else begin
read_data1 <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end
end
always @ (*) begin
if (reset == `ENABLE) begin
read_data2 <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (read_addr2 == `REGS_NUM_LOG'h0) begin
read_data2 <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (write_enable == `ENABLE && read_enable2 == `ENABLE && read_addr2 == write_addr) begin
read_data2 <= write_data;
end else if (read_enable2 == `ENABLE) begin
read_data2 <= regs[read_addr2];
end else begin
read_data2 <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end
end
endmodule |
module sky130_fd_sc_hvl__udp_pwrgood_pp$PG (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
endmodule |
module sumcomp_test;
// Inputs
reg xi;
reg yi;
reg ci;
// Outputs
wire Si;
wire Co;
// Instantiate the Unit Under Test (UUT)
sumcomp uut (
.xi(xi),
.yi(yi),
.ci(ci),
.Si(Si),
.Co(Co)
);
initial begin
$display("...");
// Initialize Inputs
xi = 0;
yi = 0;
ci = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
xi = 0; yi = 0; ci = 0; //000
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 0; ci = 1; //001
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 1; ci = 0; //010
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 1; ci = 1; //011
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 0; ci = 0; //100
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 0; ci = 1; //101
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 1; ci = 0; //110
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 1; ci = 1; //111
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
end
endmodule |
module sky130_fd_sc_ls__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule |
module GS_cpld(
output wire config_n, // ACEX1K config pins
input wire status_n, //
input wire conf_done, //
output wire cs, //
input wire init_done, //
input wire clk24in, // 24mhz in
input wire clk20in, // 20mhz in
input wire clksel0, // clock select 0 (1=divide by 2, 0=no divide)
input wire clksel1, // clock select 1 (1=clk20in, 0=clk24in)
output wire clkout, // clock out
input wire clkin, // input of clkout signal, buffered, same as for Z80
input wire coldres_n, // resets
output wire warmres_n,
input wire iorq_n, // Z80 control signals
input wire mreq_n,
input wire rd_n,
input wire wr_n,
inout wire [ 7:0] d, // Z80 data bus
input wire a6, // some Z80 addresses
input wire a7,
input wire a10,
input wire a11,
input wire a12,
input wire a13,
input wire a14,
input wire a15,
output wire mema14,
output wire mema15,
output wire mema19,
inout wire romcs_n,
inout wire memoe_n,
inout wire memwe_n,
input wire in_ramcs0_n,
input wire in_ramcs1_n,
input wire in_ramcs2_n,
input wire in_ramcs3_n,
output wire out_ramcs0_n,
output wire out_ramcs1_n,
output wire ra6, // some buffered memory addresses
output wire ra7,
output wire ra10,
output wire ra11,
output wire ra12,
output wire ra13,
inout wire [ 7:0] rd // memory data bus
);
// clock selector
clocker clk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout)
);
// memory control pins when running without configured FPGA
assign mema14 = 1'bZ;
assign mema15 = 1'bZ;
assign mema19 = 1'bZ;
assign romcs_n = 1'bZ;
assign memoe_n = 1'bZ;
assign memwe_n = 1'bZ;
assign cs = 1'b0;
assign out_ramcs0_n = 1'b1;
assign out_ramcs1_n = 1'b1;
assign rd = 8'bZZZZ_ZZZZ;
assign warmres_n = 1'bZ;
assign d = 8'bZZZZ_ZZZZ;
assign {ra6,ra7,ra10,ra11,ra12,ra13} = 6'd0;
// reset FPGA at cold reset
assign config_n = coldres_n;
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module LZD_48bit(in, out, valid
);
input [47:0]in;
output reg [5:0]out;
output reg valid;
wire v1,v2;
wire [4:0]l1;
wire [3:0]l2;
initial
begin
out<=5'b00000;
valid<=0;
end
LZD_32bit d9( .in(in[31:0]), .out(l1), .valid(v1)); //instantiation of 16bit and 32bit Leading zero detectors
LZD_16bit d10( .in(in[47:32]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2)
begin
if(v2==0&&v1==1)
begin
if(in>65535) // logic condition for accuracy when in lies in this set(2^32, 2^16]
begin
out<={{1'b0},{~v2},{l1[3:0]}};
end
else // when in lies in this set (2^16,0)
begin
out<={{~v2},{1'b0},{l1[3:0]}} ;
end
/*
IF CONDITION WHEN IN<32767
in[47:0] = 0000_0000_0000_0000___0100_1001_0000_0000_____0000_0000_1100_1001
v2=0, v1=1, l2= 0000, l1=00001
out= 010001
in[47:0] = 0000_0000_0000_0000___0000_0000_0100_1001_____0000_0000_1100_1001
v2=0, v1=1, l2= 0000, l1=01001
out = 011001= 25
ELSE CONDITION
in[47:0] = 0000_0000_0000_0000___0000_0000_0000_0000_____0100_0000_1100_1001
v2=0, v1=1, l2=0, l1=10001
out= 33= 100001
in[47:0] = 0000_0000_0000_0000___0000_0000_0000_0000_____0000_0100_1100_1001
v2=0, v1=1, l2=0, l1=10101
out= 37 = 100101
*/
end
else if( v2==0&&v1==0) // condition when both v2 and v1 are zero => in==0
begin
out<=0;
end
else
begin
out<={{1'b0},{{~v2},{l2}}}; // when v2==1 irrespective of v1 out={{~v2},{l2}};
end
valid<= v1|v2 ;
end
endmodule |
module sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$s (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule |
module execute_shift #(
parameter P_N = 32
)(
//Control
input wire [2:0] iCONTROL_MODE,
//iDATA
input wire [P_N-1:0] iDATA_0,
input wire [P_N-1:0] iDATA_1,
//oDATA
output wire [P_N-1:0] oDATA,
output wire oSF,
output wire oOF,
output wire oCF,
output wire oPF,
output wire oZF
);
function [31:0] func_sar;
input [31:0] func_sar_data;
input [4:0] func_sar_shift;
begin
case(func_sar_shift)
5'd0 : func_sar = func_sar_data;
5'd1 : func_sar = {{1{func_sar_data[31]}}, func_sar_data[31:1]};
5'd2 : func_sar = {{2{func_sar_data[31]}}, func_sar_data[31:2]};
5'd3 : func_sar = {{3{func_sar_data[31]}}, func_sar_data[31:3]};
5'd4 : func_sar = {{4{func_sar_data[31]}}, func_sar_data[31:4]};
5'd5 : func_sar = {{5{func_sar_data[31]}}, func_sar_data[31:5]};
5'd6 : func_sar = {{6{func_sar_data[31]}}, func_sar_data[31:6]};
5'd7 : func_sar = {{7{func_sar_data[31]}}, func_sar_data[31:7]};
5'd8 : func_sar = {{8{func_sar_data[31]}}, func_sar_data[31:8]};
5'd9 : func_sar = {{9{func_sar_data[31]}}, func_sar_data[31:9]};
5'd10 : func_sar = {{10{func_sar_data[31]}}, func_sar_data[31:10]};
5'd11 : func_sar = {{11{func_sar_data[31]}}, func_sar_data[31:11]};
5'd12 : func_sar = {{12{func_sar_data[31]}}, func_sar_data[31:12]};
5'd13 : func_sar = {{13{func_sar_data[31]}}, func_sar_data[31:13]};
5'd14 : func_sar = {{14{func_sar_data[31]}}, func_sar_data[31:14]};
5'd15 : func_sar = {{15{func_sar_data[31]}}, func_sar_data[31:15]};
5'd16 : func_sar = {{16{func_sar_data[31]}}, func_sar_data[31:16]};
5'd17 : func_sar = {{17{func_sar_data[31]}}, func_sar_data[31:17]};
5'd18 : func_sar = {{18{func_sar_data[31]}}, func_sar_data[31:18]};
5'd19 : func_sar = {{19{func_sar_data[31]}}, func_sar_data[31:19]};
5'd20 : func_sar = {{20{func_sar_data[31]}}, func_sar_data[31:20]};
5'd21 : func_sar = {{21{func_sar_data[31]}}, func_sar_data[31:21]};
5'd22 : func_sar = {{22{func_sar_data[31]}}, func_sar_data[31:22]};
5'd23 : func_sar = {{23{func_sar_data[31]}}, func_sar_data[31:23]};
5'd24 : func_sar = {{24{func_sar_data[31]}}, func_sar_data[31:24]};
5'd25 : func_sar = {{25{func_sar_data[31]}}, func_sar_data[31:25]};
5'd26 : func_sar = {{26{func_sar_data[31]}}, func_sar_data[31:26]};
5'd27 : func_sar = {{27{func_sar_data[31]}}, func_sar_data[31:27]};
5'd28 : func_sar = {{28{func_sar_data[31]}}, func_sar_data[31:28]};
5'd29 : func_sar = {{29{func_sar_data[31]}}, func_sar_data[31:29]};
5'd30 : func_sar = {{30{func_sar_data[31]}}, func_sar_data[31:30]};
5'd31 : func_sar = {{31{func_sar_data[31]}}, func_sar_data[31:31]};
endcase
end
endfunction
function [31:0] func_shr;
input [31:0] func_shr_data;
input [4:0] func_shr_shift;
begin
case(func_shr_shift)
5'd0 : func_shr = func_shr_data;
5'd1 : func_shr = {{1{1'b0}}, func_shr_data[31:1]};
5'd2 : func_shr = {{2{1'b0}}, func_shr_data[31:2]};
5'd3 : func_shr = {{3{1'b0}}, func_shr_data[31:3]};
5'd4 : func_shr = {{4{1'b0}}, func_shr_data[31:4]};
5'd5 : func_shr = {{5{1'b0}}, func_shr_data[31:5]};
5'd6 : func_shr = {{6{1'b0}}, func_shr_data[31:6]};
5'd7 : func_shr = {{7{1'b0}}, func_shr_data[31:7]};
5'd8 : func_shr = {{8{1'b0}}, func_shr_data[31:8]};
5'd9 : func_shr = {{9{1'b0}}, func_shr_data[31:9]};
5'd10 : func_shr = {{10{1'b0}}, func_shr_data[31:10]};
5'd11 : func_shr = {{11{1'b0}}, func_shr_data[31:11]};
5'd12 : func_shr = {{12{1'b0}}, func_shr_data[31:12]};
5'd13 : func_shr = {{13{1'b0}}, func_shr_data[31:13]};
5'd14 : func_shr = {{14{1'b0}}, func_shr_data[31:14]};
5'd15 : func_shr = {{15{1'b0}}, func_shr_data[31:15]};
5'd16 : func_shr = {{16{1'b0}}, func_shr_data[31:16]};
5'd17 : func_shr = {{17{1'b0}}, func_shr_data[31:17]};
5'd18 : func_shr = {{18{1'b0}}, func_shr_data[31:18]};
5'd19 : func_shr = {{19{1'b0}}, func_shr_data[31:19]};
5'd20 : func_shr = {{20{1'b0}}, func_shr_data[31:20]};
5'd21 : func_shr = {{21{1'b0}}, func_shr_data[31:21]};
5'd22 : func_shr = {{22{1'b0}}, func_shr_data[31:22]};
5'd23 : func_shr = {{23{1'b0}}, func_shr_data[31:23]};
5'd24 : func_shr = {{24{1'b0}}, func_shr_data[31:24]};
5'd25 : func_shr = {{25{1'b0}}, func_shr_data[31:25]};
5'd26 : func_shr = {{26{1'b0}}, func_shr_data[31:26]};
5'd27 : func_shr = {{27{1'b0}}, func_shr_data[31:27]};
5'd28 : func_shr = {{28{1'b0}}, func_shr_data[31:28]};
5'd29 : func_shr = {{29{1'b0}}, func_shr_data[31:29]};
5'd30 : func_shr = {{30{1'b0}}, func_shr_data[31:30]};
5'd31 : func_shr = {{31{1'b0}}, func_shr_data[31:31]};
endcase
end
endfunction
function [31:0] func_shl;
input [31:0] func_shl_data;
input [4:0] func_shl_shift;
begin
case(func_shl_shift)
5'd0 : func_shl = func_shl_data;
5'd1 : func_shl = {func_shl_data[30:0], 1'b0};
5'd2 : func_shl = {func_shl_data[29:0], {2{1'b0}}};
5'd3 : func_shl = {func_shl_data[28:0], {3{1'b0}}};
5'd4 : func_shl = {func_shl_data[27:0], {4{1'b0}}};
5'd5 : func_shl = {func_shl_data[26:0], {5{1'b0}}};
5'd6 : func_shl = {func_shl_data[25:0], {6{1'b0}}};
5'd7 : func_shl = {func_shl_data[24:0], {7{1'b0}}};
5'd8 : func_shl = {func_shl_data[23:0], {8{1'b0}}};
5'd9 : func_shl = {func_shl_data[22:0], {9{1'b0}}};
5'd10 : func_shl = {func_shl_data[21:0], {10{1'b0}}};
5'd11 : func_shl = {func_shl_data[20:0], {11{1'b0}}};
5'd12 : func_shl = {func_shl_data[19:0], {12{1'b0}}};
5'd13 : func_shl = {func_shl_data[18:0], {13{1'b0}}};
5'd14 : func_shl = {func_shl_data[17:0], {14{1'b0}}};
5'd15 : func_shl = {func_shl_data[16:0], {15{1'b0}}};
5'd16 : func_shl = {func_shl_data[15:0], {16{1'b0}}};
5'd17 : func_shl = {func_shl_data[14:0], {17{1'b0}}};
5'd18 : func_shl = {func_shl_data[13:0], {18{1'b0}}};
5'd19 : func_shl = {func_shl_data[12:0], {19{1'b0}}};
5'd20 : func_shl = {func_shl_data[11:0], {20{1'b0}}};
5'd21 : func_shl = {func_shl_data[10:0], {21{1'b0}}};
5'd22 : func_shl = {func_shl_data[9:0], {22{1'b0}}};
5'd23 : func_shl = {func_shl_data[8:0], {23{1'b0}}};
5'd24 : func_shl = {func_shl_data[7:0], {24{1'b0}}};
5'd25 : func_shl = {func_shl_data[6:0], {25{1'b0}}};
5'd26 : func_shl = {func_shl_data[5:0], {26{1'b0}}};
5'd27 : func_shl = {func_shl_data[4:0], {27{1'b0}}};
5'd28 : func_shl = {func_shl_data[3:0], {28{1'b0}}};
5'd29 : func_shl = {func_shl_data[2:0], {29{1'b0}}};
5'd30 : func_shl = {func_shl_data[1:0], {30{1'b0}}};
5'd31 : func_shl = {func_shl_data[0:0], {31{1'b0}}};
endcase
end
endfunction
function [31:0] func_rol;
input [31:0] func_rol_data;
input [4:0] func_rol_shift;
begin
case(func_rol_shift)
5'd0 : func_rol = func_rol_data;
5'd1 : func_rol = {func_rol_data[30:0], func_rol_data[31:31]};
5'd2 : func_rol = {func_rol_data[29:0], func_rol_data[31:30]};
5'd3 : func_rol = {func_rol_data[28:0], func_rol_data[31:29]};
5'd4 : func_rol = {func_rol_data[27:0], func_rol_data[31:28]};
5'd5 : func_rol = {func_rol_data[26:0], func_rol_data[31:27]};
5'd6 : func_rol = {func_rol_data[25:0], func_rol_data[31:26]};
5'd7 : func_rol = {func_rol_data[24:0], func_rol_data[31:25]};
5'd8 : func_rol = {func_rol_data[23:0], func_rol_data[31:24]};
5'd9 : func_rol = {func_rol_data[22:0], func_rol_data[31:23]};
5'd10 : func_rol = {func_rol_data[21:0], func_rol_data[31:22]};
5'd11 : func_rol = {func_rol_data[20:0], func_rol_data[31:21]};
5'd12 : func_rol = {func_rol_data[19:0], func_rol_data[31:20]};
5'd13 : func_rol = {func_rol_data[18:0], func_rol_data[31:19]};
5'd14 : func_rol = {func_rol_data[17:0], func_rol_data[31:18]};
5'd15 : func_rol = {func_rol_data[16:0], func_rol_data[31:17]};
5'd16 : func_rol = {func_rol_data[15:0], func_rol_data[31:16]};
5'd17 : func_rol = {func_rol_data[14:0], func_rol_data[31:15]};
5'd18 : func_rol = {func_rol_data[13:0], func_rol_data[31:14]};
5'd19 : func_rol = {func_rol_data[12:0], func_rol_data[31:13]};
5'd20 : func_rol = {func_rol_data[11:0], func_rol_data[31:12]};
5'd21 : func_rol = {func_rol_data[10:0], func_rol_data[31:11]};
5'd22 : func_rol = {func_rol_data[9:0], func_rol_data[31:10]};
5'd23 : func_rol = {func_rol_data[8:0], func_rol_data[31:9]};
5'd24 : func_rol = {func_rol_data[7:0], func_rol_data[31:8]};
5'd25 : func_rol = {func_rol_data[6:0], func_rol_data[31:7]};
5'd26 : func_rol = {func_rol_data[5:0], func_rol_data[31:6]};
5'd27 : func_rol = {func_rol_data[4:0], func_rol_data[31:5]};
5'd28 : func_rol = {func_rol_data[3:0], func_rol_data[31:4]};
5'd29 : func_rol = {func_rol_data[2:0], func_rol_data[31:3]};
5'd30 : func_rol = {func_rol_data[1:0], func_rol_data[31:2]};
5'd31 : func_rol = {func_rol_data[0:0], func_rol_data[31:1]};
endcase
end
endfunction
function [31:0] func_ror;
input [31:0] func_ror_data;
input [4:0] func_ror_shift;
begin
case(func_ror_shift)
5'd0 : func_ror = func_ror_data;
5'd1 : func_ror = {func_ror_data[0:0], func_ror_data[31:1]};
5'd2 : func_ror = {func_ror_data[1:0], func_ror_data[31:2]};
5'd3 : func_ror = {func_ror_data[2:0], func_ror_data[31:3]};
5'd4 : func_ror = {func_ror_data[3:0], func_ror_data[31:4]};
5'd5 : func_ror = {func_ror_data[4:0], func_ror_data[31:5]};
5'd6 : func_ror = {func_ror_data[5:0], func_ror_data[31:6]};
5'd7 : func_ror = {func_ror_data[6:0], func_ror_data[31:7]};
5'd8 : func_ror = {func_ror_data[7:0], func_ror_data[31:8]};
5'd9 : func_ror = {func_ror_data[8:0], func_ror_data[31:9]};
5'd10 : func_ror = {func_ror_data[9:0], func_ror_data[31:10]};
5'd11 : func_ror = {func_ror_data[10:0], func_ror_data[31:11]};
5'd12 : func_ror = {func_ror_data[11:0], func_ror_data[31:12]};
5'd13 : func_ror = {func_ror_data[12:0], func_ror_data[31:13]};
5'd14 : func_ror = {func_ror_data[13:0], func_ror_data[31:14]};
5'd15 : func_ror = {func_ror_data[14:0], func_ror_data[31:15]};
5'd16 : func_ror = {func_ror_data[15:0], func_ror_data[31:16]};
5'd17 : func_ror = {func_ror_data[16:0], func_ror_data[31:17]};
5'd18 : func_ror = {func_ror_data[17:0], func_ror_data[31:18]};
5'd19 : func_ror = {func_ror_data[18:0], func_ror_data[31:19]};
5'd20 : func_ror = {func_ror_data[19:0], func_ror_data[31:20]};
5'd21 : func_ror = {func_ror_data[20:0], func_ror_data[31:21]};
5'd22 : func_ror = {func_ror_data[21:0], func_ror_data[31:22]};
5'd23 : func_ror = {func_ror_data[22:0], func_ror_data[31:23]};
5'd24 : func_ror = {func_ror_data[23:0], func_ror_data[31:24]};
5'd25 : func_ror = {func_ror_data[24:0], func_ror_data[31:25]};
5'd26 : func_ror = {func_ror_data[25:0], func_ror_data[31:26]};
5'd27 : func_ror = {func_ror_data[26:0], func_ror_data[31:27]};
5'd28 : func_ror = {func_ror_data[27:0], func_ror_data[31:28]};
5'd29 : func_ror = {func_ror_data[28:0], func_ror_data[31:29]};
5'd30 : func_ror = {func_ror_data[29:0], func_ror_data[31:30]};
5'd31 : func_ror = {func_ror_data[30:0], func_ror_data[31:31]};
endcase
end
endfunction
//Output Selector
reg [31:0] data_out;
reg flag_cf;
always @* begin
case(iCONTROL_MODE)
3'h0 : //Buffer
begin
data_out = iDATA_0;
end
3'h1 : //Logic Left
begin
if(iDATA_1[5:0] < 6'd32)begin
data_out = func_shl(iDATA_0, iDATA_1[4:0]);
end
else begin
data_out = 32'h0;
end
end
3'h2 : //Logic Right
begin
if(iDATA_1[5:0] < 6'd32)begin
data_out = func_shr(iDATA_0, iDATA_1[4:0]);
end
else begin
data_out = 32'h0;
end
end
3'h3 : //Arithmetic Right
begin
if(iDATA_1[5:0] < 6'd32)begin
data_out = func_sar(iDATA_0, iDATA_1[4:0]);
end
else begin
data_out = {32{iDATA_0[31]}};
end
end
3'h4 : //Rotate Left
begin
data_out = func_rol(iDATA_0, iDATA_1[4:0]);
end
3'h5 : //Rotate Right
begin
data_out = func_ror(iDATA_0, iDATA_1[4:0]);
end
default: //Reserved (Buffer)
begin
data_out = iDATA_0;
end
endcase
end
always @* begin
case(iCONTROL_MODE)
3'h0 : //Buffer
begin
flag_cf = 1'b0;
end
3'h1 : //Logic Left
begin
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[31-(iDATA_1[5:0]-1)];
end
end
3'h2 : //Logic Right
begin
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[iDATA_1[5:0]-1];
end
end
3'h3 : //Arithmetic Right
begin
if(iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else if(iDATA_1[5:0] > 32)begin
flag_cf = iDATA_0[31];
end
else begin
flag_cf = iDATA_0[iDATA_1[5:0]-1];
end
end
3'h4 : //Rotate Left
begin
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[31-(iDATA_1[5:0]-1)];
end
end
3'h5 : //Rotate Right
begin
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[iDATA_1[5:0]-1];
end
end
default: //Reserved (Buffer)
begin
flag_cf = 1'b0;
end
endcase
end
assign oDATA = data_out;
assign oSF = data_out[P_N-1];
assign oOF = 1'b0;
assign oCF = flag_cf;
assign oPF = data_out[0];
assign oZF = (data_out == {32{1'b0}})? 1'b1 : 1'b0;
endmodule |
module sky130_fd_sc_hs__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter nRD_EN2CNFG_WR = 6,
parameter nWR_EN2CNFG_RD = 4,
parameter nWR_EN2CNFG_WR = 4,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, inhbt_wr_config, inhbt_rd_config,
rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en,
// Inputs
clk, rst, sent_col, col_size, io_config, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
input [RANK_WIDTH:0] io_config;
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && ~io_config[RANK_WIDTH];
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam nRD_EN2CNFG_WR_LOCAL = nRD_EN2CNFG_WR < 2 ? 0 : nRD_EN2CNFG_WR - 2;
localparam nWR_EN2CNFG_WR_LOCAL = nWR_EN2CNFG_WR < 2 ? 0 : nWR_EN2CNFG_WR - 2;
localparam WR_WAIT_CNT_WIDTH = clogb2(nRD_EN2CNFG_WR_LOCAL + 1);
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_r;
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_ns;
always @(/*AS*/cnfg_wr_wait_r or read_data_valid or rst or wrdata_en) begin
if (rst) cnfg_wr_wait_ns = {WR_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_wr_wait_ns = cnfg_wr_wait_r;
if (wrdata_en)
cnfg_wr_wait_ns = nWR_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (read_data_valid)
cnfg_wr_wait_ns = nRD_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_wr_wait_r)
cnfg_wr_wait_ns = cnfg_wr_wait_r - ONE[WR_WAIT_CNT_WIDTH-1:0];
end // else: !if(rst)
end
always @(posedge clk) cnfg_wr_wait_r <= #TCQ cnfg_wr_wait_ns;
localparam nWR_EN2CNFG_RD_LOCAL = nWR_EN2CNFG_RD < 2 ? 0 : nWR_EN2CNFG_RD - 2;
localparam RD_WAIT_CNT_WIDTH = clogb2(nWR_EN2CNFG_RD_LOCAL + 1);
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_r;
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_ns;
always @(/*AS*/cnfg_rd_wait_r or rst or wrdata_en) begin
if (rst) cnfg_rd_wait_ns = {RD_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_rd_wait_ns = cnfg_rd_wait_r;
if (wrdata_en)
cnfg_rd_wait_ns = nWR_EN2CNFG_RD_LOCAL[RD_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_rd_wait_r)
cnfg_rd_wait_ns = cnfg_rd_wait_r - ONE[RD_WAIT_CNT_WIDTH-1:0];
end
end
always @(posedge clk) cnfg_rd_wait_r <= #TCQ cnfg_rd_wait_ns;
// Finally, generate the inhbit signals. Do it in a way to help timing.
wire inhbt_wr_config_ns = (cnfg_wr_wait_ns != {WR_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_wr_config_r;
always @(posedge clk) inhbt_wr_config_r <= #TCQ inhbt_wr_config_ns;
output wire inhbt_wr_config;
assign inhbt_wr_config = sent_col || wrdata_en || inhbt_wr_config_r;
wire inhbt_rd_config_ns = (cnfg_rd_wait_ns != {RD_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_rd_config_r;
always @(posedge clk) inhbt_rd_config_r <= #TCQ inhbt_rd_config_ns;
output wire inhbt_rd_config;
assign inhbt_rd_config = sent_col || wrdata_en || inhbt_rd_config_r;
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
wire [11:0] col_a_full = {col_a[13], col_a[11], col_a[9:0]};
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule |
module sky130_fd_sc_ms__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule |
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H00000000430000000000000042c100000000000042c00000),
.C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(3'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(3'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(3'H7),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module sky130_fd_sc_lp__xnor2_m (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__xnor2_m (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule |
module ad_tdd_control(
// clock and reset
clk,
rst,
// TDD timming signals
tdd_enable,
tdd_secondary,
tdd_tx_only,
tdd_rx_only,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
// TDD control signals
tdd_tx_dp_en,
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
tdd_counter_status);
// parameters
localparam ON = 1;
localparam OFF = 0;
// input/output signals
input clk;
input rst;
input tdd_enable;
input tdd_secondary;
input tdd_tx_only;
input tdd_rx_only;
input [ 7:0] tdd_burst_count;
input [23:0] tdd_counter_init;
input [23:0] tdd_frame_length;
input [23:0] tdd_vco_rx_on_1;
input [23:0] tdd_vco_rx_off_1;
input [23:0] tdd_vco_tx_on_1;
input [23:0] tdd_vco_tx_off_1;
input [23:0] tdd_rx_on_1;
input [23:0] tdd_rx_off_1;
input [23:0] tdd_tx_on_1;
input [23:0] tdd_tx_off_1;
input [23:0] tdd_tx_dp_on_1;
input [23:0] tdd_tx_dp_off_1;
input [23:0] tdd_vco_rx_on_2;
input [23:0] tdd_vco_rx_off_2;
input [23:0] tdd_vco_tx_on_2;
input [23:0] tdd_vco_tx_off_2;
input [23:0] tdd_rx_on_2;
input [23:0] tdd_rx_off_2;
input [23:0] tdd_tx_on_2;
input [23:0] tdd_tx_off_2;
input [23:0] tdd_tx_dp_on_2;
input [23:0] tdd_tx_dp_off_2;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
output tdd_tx_vco_en; // power up RF Rx
output tdd_rx_rf_en; // power up RF Tx
output tdd_tx_rf_en; // enable Tx datapath
output [23:0] tdd_counter_status;
// tdd control related
reg tdd_tx_dp_en = 1'b0;
reg tdd_rx_vco_en = 1'b0;
reg tdd_tx_vco_en = 1'b0;
reg tdd_rx_rf_en = 1'b0;
reg tdd_tx_rf_en = 1'b0;
// tdd counter related
reg [23:0] tdd_counter = 24'h0;
reg [ 5:0] tdd_burst_counter = 6'h0;
reg tdd_cstate = OFF;
reg tdd_cstate_next = OFF;
reg counter_at_tdd_vco_rx_on_1 = 1'b0;
reg counter_at_tdd_vco_rx_off_1 = 1'b0;
reg counter_at_tdd_vco_tx_on_1 = 1'b0;
reg counter_at_tdd_vco_tx_off_1 = 1'b0;
reg counter_at_tdd_rx_on_1 = 1'b0;
reg counter_at_tdd_rx_off_1 = 1'b0;
reg counter_at_tdd_tx_on_1 = 1'b0;
reg counter_at_tdd_tx_off_1 = 1'b0;
reg counter_at_tdd_tx_dp_on_1 = 1'b0;
reg counter_at_tdd_tx_dp_off_1 = 1'b0;
reg counter_at_tdd_vco_rx_on_2 = 1'b0;
reg counter_at_tdd_vco_rx_off_2 = 1'b0;
reg counter_at_tdd_vco_tx_on_2 = 1'b0;
reg counter_at_tdd_vco_tx_off_2 = 1'b0;
reg counter_at_tdd_rx_on_2 = 1'b0;
reg counter_at_tdd_rx_off_2 = 1'b0;
reg counter_at_tdd_tx_on_2 = 1'b0;
reg counter_at_tdd_tx_off_2 = 1'b0;
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
reg counter_at_tdd_tx_dp_off_2 = 1'b0;
reg tdd_enable_d = 1'h0;
reg tdd_last_burst = 1'b0;
// internal signals
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire tdd_endof_frame;
wire tdd_endof_burst;
wire tdd_txrx_only_en_s;
assign tdd_counter_status = tdd_counter;
// ***************************************************************************
// tdd counter (state machine)
// ***************************************************************************
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_cstate <= OFF;
tdd_enable_d <= 0;
end else begin
tdd_cstate <= tdd_cstate_next;
tdd_enable_d <= tdd_enable;
end
end
always @* begin
tdd_cstate_next <= tdd_cstate;
case (tdd_cstate)
ON : begin
if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin
tdd_cstate_next <= OFF;
end
end
OFF : begin
if((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
tdd_cstate_next <= ON;
end
end
endcase
end
assign tdd_endof_frame = (tdd_counter == tdd_frame_length) ? 1'b1 : 1'b0;
assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_counter == tdd_frame_length)) ? 1'b1 : 1'b0;
// tdd free running counter
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_counter <= tdd_counter_init;
end else begin
if (tdd_cstate == ON) begin
tdd_counter <= (tdd_counter < tdd_frame_length) ? tdd_counter + 1 : 24'b0;
end else begin
tdd_counter <= tdd_counter_init;
end
end
end
// tdd burst counter
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_burst_counter <= tdd_burst_count;
end else begin
if (tdd_cstate == ON) begin
tdd_burst_counter <= ((tdd_burst_counter > 0) && (tdd_endof_frame == 1'b1)) ? tdd_burst_counter - 1 : tdd_burst_counter;
end else begin
tdd_burst_counter <= tdd_burst_count;
end
tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0;
end
end
// ***************************************************************************
// generate control signals
// ***************************************************************************
// start/stop rx vco
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_rx_on_1) begin
counter_at_tdd_vco_rx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2)) begin
counter_at_tdd_vco_rx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_rx_off_1) begin
counter_at_tdd_vco_rx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2)) begin
counter_at_tdd_vco_rx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end
end
// start/stop tx vco
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_tx_on_1) begin
counter_at_tdd_vco_tx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2)) begin
counter_at_tdd_vco_tx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_tx_off_1) begin
counter_at_tdd_vco_tx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2)) begin
counter_at_tdd_vco_tx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end
end
// start/stop rx rf path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_rx_on_1) begin
counter_at_tdd_rx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_rx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2)) begin
counter_at_tdd_rx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_rx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_rx_off_1) begin
counter_at_tdd_rx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_rx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2)) begin
counter_at_tdd_rx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_rx_off_2 <= 1'b0;
end
end
// start/stop tx rf path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_on_1) begin
counter_at_tdd_tx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2)) begin
counter_at_tdd_tx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_off_1) begin
counter_at_tdd_tx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2)) begin
counter_at_tdd_tx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_off_2 <= 1'b0;
end
end
// start/stop tx data path
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_dp_on_1_s) begin
counter_at_tdd_tx_dp_on_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
counter_at_tdd_tx_dp_on_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_dp_off_1_s) begin
counter_at_tdd_tx_dp_off_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
counter_at_tdd_tx_dp_off_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end
end
// internal datapath delay compensation
ad_addsub #(
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_on_1_comp (
.clk(clk),
.A(tdd_tx_dp_on_1),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_on_1_s),
.CE(1)
);
ad_addsub #(
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_on_2_comp (
.clk(clk),
.A(tdd_tx_dp_on_2),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_on_2_s),
.CE(1)
);
ad_addsub #(
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_off_1_comp (
.clk(clk),
.A(tdd_tx_dp_off_1),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_off_1_s),
.CE(1)
);
ad_addsub #(
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_off_2_comp (
.clk(clk),
.A(tdd_tx_dp_off_2),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_off_2_s),
.CE(1)
);
// output logic
assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_rx_vco_en <= 1'b0;
end
else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
tdd_rx_vco_en <= 1'b0;
end
else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
tdd_rx_vco_en <= 1'b1;
end
else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_vco_en <= tdd_rx_only;
end
else begin
tdd_rx_vco_en <= tdd_rx_vco_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_tx_vco_en <= 1'b0;
end
else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
tdd_tx_vco_en <= 1'b0;
end
else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
tdd_tx_vco_en <= 1'b1;
end
else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_vco_en <= tdd_tx_only;
end
else begin
tdd_tx_vco_en <= tdd_tx_vco_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_rx_rf_en <= 1'b0;
end
else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end
else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
tdd_rx_rf_en <= 1'b1;
end
else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_rf_en <= tdd_rx_only;
end
else begin
tdd_rx_rf_en <= tdd_rx_rf_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_tx_rf_en <= 1'b0;
end
else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end
else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
tdd_tx_rf_en <= 1'b1;
end
else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_rf_en <= tdd_tx_only;
end
else begin
tdd_tx_rf_en <= tdd_tx_rf_en;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_tx_dp_en <= 1'b0;
end
else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end
else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
tdd_tx_dp_en <= 1'b1;
end
else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_dp_en <= tdd_tx_only;
end
else begin
tdd_tx_dp_en <= tdd_tx_dp_en;
end
end
endmodule |
module sky130_fd_sc_hs__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module sky130_fd_sc_lp__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tapvgnd2 base ();
endmodule |
module system_vga_sync_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_0_0_vga_sync U0
(.active(active),
.clk(clk),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule |
module system_vga_sync_0_0_vga_sync
(xaddr,
yaddr,
active,
hsync,
vsync,
clk,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output active;
output hsync;
output vsync;
input clk;
input rst;
wire active;
wire active0;
wire active_i_3_n_0;
wire clear;
wire clk;
wire \h_count_reg[8]_i_1_n_0 ;
wire \h_count_reg[9]_i_2_n_0 ;
wire hsync;
wire hsync_i_1_n_0;
wire hsync_i_2_n_0;
wire [9:0]p_0_in;
wire [9:0]p_0_in__0;
wire rst;
wire sel;
wire \v_count_reg[3]_i_2_n_0 ;
wire \v_count_reg[6]_i_1_n_0 ;
wire \v_count_reg[9]_i_3_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire vsync;
wire vsync_i_1_n_0;
wire vsync_i_2_n_0;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT5 #(
.INIT(32'h0022002A))
active_i_1
(.I0(active_i_3_n_0),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(yaddr[9]),
.I4(xaddr[8]),
.O(active0));
LUT1 #(
.INIT(2'h1))
active_i_2
(.I0(rst),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7FFF))
active_i_3
(.I0(yaddr[6]),
.I1(yaddr[5]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.O(active_i_3_n_0));
FDCE #(
.INIT(1'b0))
active_reg
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(active0),
.Q(active));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h6AAA))
\h_count_reg[3]_i_1
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\h_count_reg[4]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h33332333CCCCCCCC))
\h_count_reg[5]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_2_n_0 ),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h6A))
\h_count_reg[6]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(\h_count_reg[9]_i_2_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\h_count_reg[7]_i_1
(.I0(xaddr[7]),
.I1(\h_count_reg[9]_i_2_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h3FFFFFF7C0000000))
\h_count_reg[8]_i_1
(.I0(xaddr[9]),
.I1(\h_count_reg[9]_i_2_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[7]),
.I4(xaddr[6]),
.I5(xaddr[8]),
.O(\h_count_reg[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7F80EF00FF00FF00))
\h_count_reg[9]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_2_n_0 ),
.O(p_0_in[9]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h80000000))
\h_count_reg[9]_i_2
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.I3(xaddr[4]),
.I4(xaddr[3]),
.O(\h_count_reg[9]_i_2_n_0 ));
FDCE \h_count_reg_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[0]),
.Q(xaddr[0]));
FDCE \h_count_reg_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[1]),
.Q(xaddr[1]));
FDCE \h_count_reg_reg[2]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[2]),
.Q(xaddr[2]));
FDCE \h_count_reg_reg[3]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[3]),
.Q(xaddr[3]));
FDCE \h_count_reg_reg[4]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[4]),
.Q(xaddr[4]));
FDCE \h_count_reg_reg[5]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[5]),
.Q(xaddr[5]));
FDCE \h_count_reg_reg[6]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[6]),
.Q(xaddr[6]));
FDCE \h_count_reg_reg[7]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[7]),
.Q(xaddr[7]));
FDCE \h_count_reg_reg[8]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(\h_count_reg[8]_i_1_n_0 ),
.Q(xaddr[8]));
FDCE \h_count_reg_reg[9]
(.C(clk),
.CE(1'b1),
.CLR(clear),
.D(p_0_in[9]),
.Q(xaddr[9]));
LUT6 #(
.INIT(64'hFFBFBFBFBFBFBFFF))
hsync_i_1
(.I0(xaddr[8]),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(hsync_i_2_n_0),
.I4(xaddr[5]),
.I5(xaddr[6]),
.O(hsync_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
hsync_i_2
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[3]),
.I3(xaddr[1]),
.I4(xaddr[0]),
.O(hsync_i_2_n_0));
FDPE #(
.INIT(1'b0))
hsync_reg
(.C(clk),
.CE(1'b1),
.D(hsync_i_1_n_0),
.PRE(clear),
.Q(hsync));
LUT6 #(
.INIT(64'h5555555545555555))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(p_0_in__0[1]));
LUT6 #(
.INIT(64'h55AA55AA45AA55AA))
\v_count_reg[2]_i_1
(.I0(\v_count_reg[3]_i_2_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in__0[2]));
LUT6 #(
.INIT(64'h55FFAA0045FFAA00))
\v_count_reg[3]_i_1
(.I0(\v_count_reg[3]_i_2_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\v_count_reg[3]_i_2
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(\v_count_reg[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[4]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\v_count_reg[5]_i_1
(.I0(yaddr[5]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[3]),
.I4(yaddr[2]),
.I5(yaddr[4]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h6A))
\v_count_reg[6]_i_1
(.I0(yaddr[6]),
.I1(\v_count_reg[9]_i_5_n_0 ),
.I2(yaddr[5]),
.O(\v_count_reg[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6AAA))
\v_count_reg[7]_i_1
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(\v_count_reg[9]_i_5_n_0 ),
.I3(yaddr[6]),
.O(p_0_in__0[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[8]_i_1
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_5_n_0 ),
.I3(yaddr[5]),
.I4(yaddr[7]),
.O(p_0_in__0[8]));
LUT6 #(
.INIT(64'h0000000000002000))
\v_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_2_n_0 ),
.I1(xaddr[7]),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[5]),
.I5(xaddr[6]),
.O(sel));
LUT5 #(
.INIT(32'hD0D00DD0))
\v_count_reg[9]_i_2
(.I0(\v_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(\v_count_reg[9]_i_5_n_0 ),
.I4(active_i_3_n_0),
.O(p_0_in__0[9]));
LUT4 #(
.INIT(16'h0080))
\v_count_reg[9]_i_3
(.I0(yaddr[9]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[7]),
.O(\v_count_reg[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\v_count_reg[9]_i_4
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.I4(yaddr[4]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h80000000))
\v_count_reg[9]_i_5
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(\v_count_reg[9]_i_5_n_0 ));
FDCE \v_count_reg_reg[0]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[0]),
.Q(yaddr[0]));
FDCE \v_count_reg_reg[1]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[1]),
.Q(yaddr[1]));
FDCE \v_count_reg_reg[2]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[2]),
.Q(yaddr[2]));
FDCE \v_count_reg_reg[3]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[3]),
.Q(yaddr[3]));
FDCE \v_count_reg_reg[4]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[4]),
.Q(yaddr[4]));
FDCE \v_count_reg_reg[5]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[5]),
.Q(yaddr[5]));
FDCE \v_count_reg_reg[6]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(\v_count_reg[6]_i_1_n_0 ),
.Q(yaddr[6]));
FDCE \v_count_reg_reg[7]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[7]),
.Q(yaddr[7]));
FDCE \v_count_reg_reg[8]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[8]),
.Q(yaddr[8]));
FDCE \v_count_reg_reg[9]
(.C(clk),
.CE(sel),
.CLR(clear),
.D(p_0_in__0[9]),
.Q(yaddr[9]));
LUT4 #(
.INIT(16'hE0EE))
vsync_i_1
(.I0(vsync),
.I1(rst),
.I2(active_i_3_n_0),
.I3(vsync_i_2_n_0),
.O(vsync_i_1_n_0));
LUT6 #(
.INIT(64'h0002000000000000))
vsync_i_2
(.I0(yaddr[1]),
.I1(yaddr[2]),
.I2(yaddr[4]),
.I3(yaddr[9]),
.I4(rst),
.I5(yaddr[3]),
.O(vsync_i_2_n_0));
FDRE #(
.INIT(1'b0))
vsync_reg
(.C(clk),
.CE(1'b1),
.D(vsync_i_1_n_0),
.Q(vsync),
.R(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hvl__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module led_capture(
led_input,clk,rst_n,tx_start,tx_data
);
input led_input;
input clk;
input rst_n;
output tx_start;
output[7:0] tx_data;
reg ready;
reg[31:0] counter;
reg[31:0] pos_counter;
reg[31:0] nextpos_counter;
reg[31:0] periodcounter;
reg pos_counter_flag;
reg nextpos_counter_flag;
wire pos_btn;
/*******************************************************************************
*counter
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n) begin
counter <= 'h0;
end
else begin
counter <= (counter < 32'hFFFFFFFF) ? (counter + 1'b1) : 'h0 ;
end
end
/*******************************************************************************
*Instance
*********************************************************************************/
pos_capture pos_capture_instance(
.led_input(led_input),
.clk(clk),
.rst_n(rst_n),
.pos_btn(pos_btn)
);
captuer_tx captuer_tx_instance(
.clk(clk),
.rst_n(rst_n),
.tx_start(tx_start),
.capture_ready(ready),
.periodcounter(periodcounter),
.tx_data(tx_data),
.counter(counter),
.led_input(led_input)
);
/*******************************************************************************
*Capture pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
pos_counter <= 'h0;
pos_counter_flag <= 'h0;
end
else if(pos_btn && (pos_counter_flag != 1'b1))begin
pos_counter <= counter;
pos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture next pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
nextpos_counter <= 'h0;
nextpos_counter_flag <= 'h0;
end
else if(pos_btn && pos_counter_flag && (nextpos_counter_flag != 1'b1))begin
nextpos_counter <= counter;
nextpos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Calculate the period
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
periodcounter <= 'h0;
ready <= 'h0;
end
else if(pos_counter_flag && nextpos_counter_flag)begin
periodcounter <= nextpos_counter - pos_counter;
ready <= 'h1;
end
end
endmodule |
module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module axi_interconnect #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
)(
//control signals
input clk,
input rst,
//bus write addr path
output [3:0] i_awid, //Write ID
output [ADDR_WIDTH - 1:0] i_awaddr, //Write Addr Path Address
output [3:0] i_awlen, //Write Addr Path Burst Length
output [2:0] i_awsize, //Write Addr Path Burst Size
output [1:0] i_awburst, //Write Addr Path Burst Type
// 0 = Fixed
// 1 = Incrementing
// 2 = wrap
output [1:0] i_awlock, //Write Addr Path Lock (atomic) information
// 0 = Normal
// 1 = Exclusive
// 2 = Locked
output [3:0] i_awcache, //Write Addr Path Cache Type
output [2:0] i_awprot, //Write Addr Path Protection Type
output i_awvalid, //Write Addr Path Address Valid
input o_awready, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output reg [3:0] i_wid, //Write ID
output reg [DATA_WIDTH - 1: 0] i_wdata, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output reg [DATA_WIDTH >> 3:0] i_wstrobe, //Write Strobe (a 1 in the write is associated with the byte to write)
output reg i_wlast, //Write Last transfer in a write burst
output reg i_wvalid, //Data through this bus is valid
input o_wready, //Slave is ready for data
//Write Response Channel
input [3:0] o_bid, //Response ID (this must match awid)
input [1:0] o_bresp, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input o_bvalid, //Write Response is:
// 1 = Available
// 0 = Not Available
output reg i_bready, //WBM Ready
//bus read addr path
output reg [3:0] i_arid, //Read ID
output [ADDR_WIDTH - 1:0] i_araddr, //Read Addr Path Address
output reg [3:0] i_arlen, //Read Addr Path Burst Length
output reg [2:0] i_arsize, //Read Addr Path Burst Size
output [1:0] i_arburst, //Read Addr Path Burst Type
output [1:0] i_arlock, //Read Addr Path Lock (atomic) information
output [3:0] i_arcache, //Read Addr Path Cache Type
output [2:0] i_arprot, //Read Addr Path Protection Type
output reg i_arvalid, //Read Addr Path Address Valid
input o_arready, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] o_rid, //Write ID
input [DATA_WIDTH - 1: 0] o_rdata, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
input [DATA_WIDTH >> 3:0] o_rstrobe, //Write Strobe (a 1 in the write is associated with the byte to write)
input o_rlast, //Write Last transfer in a write burst
input o_rvalid, //Data through this bus is valid
output reg i_rready, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
${PORTS}
);
${ADDRESSES}
localparam ADDR_NO_SEL = ((1 << ADDR_WIDTH) - 1);
//state
//axi slave signals
//this should be parameterized
wire [3:0]slave_select;
assign slave_select = i_m_adr[31:24];
${DATA}
${ACK}
${ASSIGN}
endmodule |
module sram (
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input clock;
input [71:0] data;
input [9:0] rdaddress;
input rden;
input [9:0] wraddress;
input wren;
output [71:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module sky130_fd_sc_lp__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule |
module simplez #(
parameter BAUD = `B115200, //-- Velocidad de comunicacion de la pantalla / Teclado
parameter WAIT_DELAY = `T_200ms, //-- Tiempo de espera para la instruccion WAIT (Debug)
parameter ROMFILE = "", //-- Fichero con el contenido de la RAM a cargar
parameter DEBUG_LEDS = 0 //-- Uso de los leds para depuracion
)(
input wire clk, //-- Reloj del sistema
input wire rstn_ini, //-- Reset
output wire [7:0] leds, //-- leds
output wire stop, //-- Indicador de stop
output wire tx, //-- Salida serie para la pantalla
input wire rx //-- Entrada serie del teclado
);
//-- Direcciones para los perifericos
localparam LEDS_ADR = 9'd507;
localparam PANTALLA_STATUS_ADR = 9'd508; //-- Pantalla: Unidad de transmision serie
localparam PANTALLA_DATA_ADR = 9'd509;
localparam TECLADO_STATUS_ADR = 9'd510; //-- Teclado: Unidad de recepcion serie
localparam TECLADO_DATA_ADR = 9'd511;
//-- Codigos de operacion de las instrucciones de simplez
localparam ST = 3'o0; //-- OK
localparam LD = 3'o1; //-- OK
localparam ADD = 3'o2; //-- OK
localparam BR = 3'o3; //-- OK
localparam BZ = 3'o4; //-- OK
localparam CLR = 3'o5; //-- OK
localparam DEC = 3'o6; //-- OK
localparam HALT = 3'o7; //-- OK
//-- Codigos de operacion extendidos
localparam HALTE = 4'hE; //-- Halt extended
localparam WAIT = 4'hF; //-- Wait
//-- Tamano de la memoria RAM a instanciar
localparam AW = 9; //-- Anchura del bus de direcciones
localparam DW = 12; //-- Anchura del bus de datos
//-- Instanciar la memoria RAM
wire [DW-1: 0] mem_dout;
wire [AW-1: 0] addr;
wire ram_cs ; //-- Chip select global para la ram
wire ram_inst_cs; //-- Chip select para lectura de instrucciones en RAM
wire ram_data_cs; //-- Chip select para el acceso a datos en RAM
//-- Chip select para el acceso a instrucciones
assign ram_inst_cs = (state == INIT) ? 1 : 0;
//-- Chip select global de la RAM
assign ram_cs = ram_inst_cs | ram_data_cs;
genram #(
.ROMFILE(ROMFILE),
.AW(AW),
.DW(DW))
ROM (
.clk(clk),
.cs(ram_cs),
.rw(rw),
.addr(addr),
.data_out(mem_dout),
.data_in(reg_a)
);
//-- Registrar la senal de reset
reg rstn = 0;
always @(posedge clk)
rstn <= rstn_ini;
//-- Declaracion de las microordenes
reg cp_inc = 0; //-- Incrementar contador de programa
reg cp_load = 0; //-- Cargar el contador de programa
reg cp_sel = 0; //-- Seleccion de la direccion del contador de programa
reg ri_load = 0; //-- Cargar el registro de instruccion
reg halt = 0; //-- Instruccion halt ejecutada
reg a_load = 0; //-- Cargar el acumulador
reg rw = 1; //-- Lectura / escritura en RAM
reg timer_ena = 0; //-- Habilitacion del temporizador
//-- Microordenes para la ALU
reg alu_op2 = 0; //-- Sacar el operando 2 por la salida (sin modificar)
reg alu_clr = 0; //-- Sacar un 0 por la salida
reg alu_add = 0; //-- Sumar al acumulador el operando 2
reg alu_dec = 0; //-- Decrementar operando 1 en una unidad
//-- Contador de programa
reg [AW-1: 0] cp = 0;
always @(posedge clk)
if (!rstn)
cp <= 0;
else if (cp_load)
cp <= CD;
else if (cp_inc)
cp <= cp + 1;
//-- Multiplexor de acceso a la direccion de memoria
//-- cp_sel = 1 ---> Se direcciona la memoria desde el CP
//-- cp_sel = 0 ---> Se direcciona la memoria desde el CD del RI
assign addr = (cp_sel) ? cp : CD;
//-- Registro de instruccion
reg [DW-1: 0] ri = 0;
//-- Descomponer la instruccion en los campos CO y CD
wire [2:0] CO = ri[11:9]; //-- Codigo de operacion
wire [8:0] CD = ri[8:0]; //-- Campo de direccion
wire [3:0] COE = ri[11:8]; //-- Código de operacion extendido
always @(posedge clk)
if (!rstn)
ri <= 0;
else if (ri_load)
ri <= mem_dout;
//-- Registro de stop
//-- Se pone a 1 cuando se ha ejecutado una instruccion de HALT
reg reg_stop = 0;
always @(posedge clk)
if (!rstn)
reg_stop <= 0;
else if (halt)
reg_stop <= 1;
//-- Registro acumulador
reg [DW-1: 0] reg_a = 0;
always @(posedge clk)
if (!rstn)
reg_a <= 0;
else if (a_load)
reg_a <= alu_out;
//-- Debug: Acceso a los leds
//-- Si DEBUG_LEDS, se saca directamente los 4 bits menos sig del registro A
//-- En caso contrario los leds estan mapeados y se accede a ellos como a cualquier
//-- otro periferico
assign leds = (DEBUG_LEDS == 1) ? reg_a[7:0] : leds_data;
//-- Debug: 8 bits menos significativos del registro A conectados a los leds rojos
//assign leds = reg_a[7:0];
//-- Debug: Sacar senal de stop por el led verde de la icestick
assign stop = reg_stop;
//----- ALU ----
reg [DW-1: 0] alu_out = 0;
reg flag_z = 0;
always @(*) begin
//-- Operacion: transferencia del operando 2 a la salida
if (alu_op2)
alu_out = alu_in;
//-- Sacar el valor 0
else if (alu_clr)
alu_out = 0;
//-- Suma de operador 1 + operador 2
else if (alu_add)
alu_out = reg_a + alu_in;
else if (alu_dec)
alu_out = reg_a - 1;
//-- Evitar latches
else
alu_out = 1;
end
//-- Captura del flag de z
//-- Se captura con la misma senal de carga del registro A
always @(posedge clk)
if (!rstn)
flag_z <= 0;
else if (a_load)
if (alu_out == 0)
flag_z <= 1;
else
flag_z <= 0;
//-- Multiplexor de acceso al bus de datos DATA_OUT
//-- Donde tanto la memoria como los perifericos depositan sus datos
wire [DW-1: 0] alu_in;
assign alu_in = (ram_cs == 1) ? mem_dout :
(pant_status_cs == 1) ? {4'b0, pant_status} :
(tecl_data_cs == 1) ? {4'b0, tecl_data} :
(tecl_status_cs == 1) ? {4'b0, tecl_status} : 12'b0;
//----------- PERIFERICOS --------
//-- Divisor para marcar la duracion de cada estado del automata
wire clk_tic;
dividerp1 #(WAIT_DELAY)
TIMER0 (
.clk(clk),
.clk_out(clk_tic),
.timer_ena(timer_ena)
);
//-- Chip select para la pantalla de simplez
wire pant_data_cs;
wire pant_status_cs;
//-- Otros cables para la pantalla
wire tx_ready;
reg [7:0] pant_status = 0;
//-- Chip select para el teclado de simplez
wire tecl_data_cs;
reg [7:0] tecl_data = 0;
wire tecl_status_cs;
reg [7:0] tecl_status = 0;
wire [7:0] rxdata;
wire rxrcv;
reg rcv_flag = 0;
//-- Chip select para el registro de LEDs
wire leds_cs = (CD == LEDS_ADR) ? 1 : 0;
//-- Logica de activacion del chip select de la memoria
//-- Direcciones desde 0 - 1F7 son de RAM
//-- Desde 1F8 a 1FF son para perifericos
assign ram_data_cs = (CD < 9'h1F8) ? 1 : 0;
assign pant_data_cs = (CD == PANTALLA_DATA_ADR) ? 1 : 0;
assign pant_status_cs = (CD == PANTALLA_STATUS_ADR) ? 1 : 0;
assign tecl_data_cs = (CD == TECLADO_DATA_ADR) ? 1 : 0;
assign tecl_status_cs = (CD == TECLADO_STATUS_ADR) ? 1: 0;
//-- Registro de status de la pantalla
always @(posedge clk)
if (!rstn)
pant_status <= 8'b0;
else if (pant_status_cs)
pant_status <= {7'b0, tx_ready};
//-- Registro de datos del teclado
always @(posedge clk)
if (!rstn)
tecl_data <= 8'b0;
else if (tecl_data_cs)
tecl_data <= rxdata;
//-- Registro de estado del teclado
always @(posedge clk)
if (!rstn)
tecl_status <= 8'b0;
else if (tecl_status_cs)
tecl_status <= {7'b0, rcv_flag};
//-- Capturar el flag de dato recibido
always @(posedge clk)
if (!rstn)
rcv_flag <= 0;
else if (rxrcv)
rcv_flag <= 1; //-- Al recibir un dato se pone a 1 el flag
else if (tecl_data_cs) //-- Al leer reg datos el flag se pone a 0
rcv_flag <= 0;
//-- Instanciar la Unidad de transmision
uart_tx #(.BAUDRATE(BAUD))
TX0 (
.clk(clk),
.rstn(rstn),
.data(reg_a[7:0]),
.start(pant_data_cs),
.ready(tx_ready),
.tx(tx)
);
//-- Instanciar la Unidad de recepcion
uart_rx #(BAUD)
RX0 (.clk(clk), //-- Reloj del sistema
.rstn(rstn), //-- Señal de reset
.rx(rx), //-- Linea de recepción de datos serie
.rcv(rxrcv), //-- Señal de dato recibido
.data(rxdata) //-- Datos recibidos
);
//-- Puerto de leds
reg [7:0] leds_data = 0;
always @(posedge clk)
if (!rstn)
leds_data <= 0;
else if (leds_cs)
leds_data <= reg_a[7:0];
//-------------------- UNIDAD DE CONTROL
localparam INIT = 0;
localparam FETCH = 1;
localparam EXEC1 = 2;
localparam EXEC2 = 3;
localparam END = 4;
//-- Estado del automata
reg [2:0] state = 0;
reg [2:0] next_state = 0;
//-- Transiciones de estados
always @(posedge clk)
if (!rstn)
state <= INIT;
else
state <= next_state;
//-- Generacion de microordenes
//-- y siguientes estados
always @(*) begin
//-- Valores por defecto
next_state = state; //-- Por defecto permanecer en el mismo estado
cp_inc = 0;
cp_load = 0;
cp_sel = 1;
ri_load = 0;
halt = 0;
a_load = 0;
rw = 1;
alu_op2 = 0;
alu_add = 0;
alu_clr = 0;
alu_dec = 0;
timer_ena = 0;
case(state)
//-- Estado inicial
INIT:
if (!rstn)
next_state = INIT;
else
next_state = FETCH;
FETCH: begin
next_state = EXEC1;
ri_load = 1;
end
EXEC1: begin
case (CO)
ST: begin
rw = 0; //-- Memoria en modo escritura
cp_sel = 0;
next_state = END;
end
BR: begin
cp_load = 1;
next_state = INIT;
end
BZ: begin
if (flag_z) begin
cp_load = 1;
next_state = INIT;
end
else
next_state = END;
end
LD: begin
cp_sel = 0;
next_state = EXEC2;
end
ADD: begin
cp_sel = 0;
next_state = EXEC2;
end
CLR: begin
a_load = 1;
alu_clr = 1;
next_state = END;
end
DEC: begin
a_load = 1;
alu_dec = 1;
next_state = END;
end
//-- Procesar codigos de operacion extendidos
HALT: begin
//-- Instrucciones extendidas
case (COE)
//-- Instruccion HALT de simplez
HALTE: begin
halt = 1;
next_state = EXEC1; //-- Permanecer en el mismo estado... para siempre...
end
//-- Instruccion WAIT de microbio
WAIT: begin
//-- Reiniciar temporizador
timer_ena = 1;
next_state = EXEC2;
end
default:
next_state = INIT;
endcase
end
endcase
end
EXEC2: begin
case (CO)
LD: begin
a_load = 1;
alu_op2 = 1;
next_state = END;
end
ADD: begin
a_load = 1;
alu_add = 1;
next_state = END;
end
//-- Procesar codigos de operacion extendidos
HALT: begin
//-- Instrucciones extendidas
case (COE)
//-- Instruccion WAIT de microbio
WAIT: begin
//-- Mientras no se active clk_tic, se sigue en el mismo
//-- estado de ejecucion
timer_ena = 1;
if (clk_tic) next_state = END;
else next_state = EXEC2;
end
default:
next_state = INIT;
endcase
end
default:
next_state = INIT;
endcase
end
END: begin
next_state = INIT;
cp_inc = 1;
end
endcase
end
endmodule |
module FIFO_DETECTION_YN (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [109:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [109:0] q;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
$dumpvars(12, t);
end
`endif
endmodule |
module One;
wire one = 1'b1;
endmodule |
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule |
module lpddr2_cntrlr_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
lpddr2_cntrlr_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
lpddr2_cntrlr_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
lpddr2_cntrlr_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
lpddr2_cntrlr_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module axilite2regctl #
(
// Width of S_AXI data bus
parameter integer C_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_ADDR_WIDTH = 10,
// Width of REG address
parameter integer C_REG_IDX_WIDTH = 8
)
(
input wire clk,
input wire resetn,
/// reg ctl interface
output rd_en,
output [C_REG_IDX_WIDTH-1:0] rd_addr,
input [C_DATA_WIDTH-1:0] rd_data,
output wr_en,
output [C_REG_IDX_WIDTH-1:0] wr_addr,
output [C_DATA_WIDTH-1:0] wr_data,
/// slave axi lite
input wire [C_ADDR_WIDTH-1 : 0] s_axi_awaddr,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [C_DATA_WIDTH-1 : 0] s_axi_wdata,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [1 : 0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [C_ADDR_WIDTH-1 : 0] s_axi_araddr,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [C_DATA_WIDTH-1 : 0] s_axi_rdata,
output wire [1 : 0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready
);
// AXI4LITE signals
reg [C_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg axi_bvalid;
reg axi_arready;
reg axi_rvalid;
wire slv_reg_rden;
wire slv_reg_wren;
integer byte_index;
reg aw_en;
/**
* read/write interface
*/
assign rd_en = slv_reg_rden;
assign rd_addr = s_axi_araddr[C_ADDR_WIDTH-1:C_ADDR_WIDTH-C_REG_IDX_WIDTH];
assign wr_addr = axi_awaddr[C_ADDR_WIDTH-1:C_ADDR_WIDTH-C_REG_IDX_WIDTH];
assign wr_en = slv_reg_wren;
assign wr_data = s_axi_wdata;
// I/O Connections assignments
assign s_axi_awready = axi_awready;
assign s_axi_wready = axi_wready;
assign s_axi_bresp = 0;
assign s_axi_bvalid = axi_bvalid;
assign s_axi_arready = axi_arready;
assign s_axi_rdata = rd_data;
assign s_axi_rresp = 0;
assign s_axi_rvalid = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one clk clock cycle when both
// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge clk )
begin
if ( resetn == 1'b0 ) begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) begin
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (s_axi_bready && axi_bvalid) begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else begin
axi_awready <= 1'b0;
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// s_axi_awvalid and s_axi_wvalid are valid.
always @( posedge clk )
begin
if ( resetn == 1'b0 )
axi_awaddr <= 0;
else if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en)
axi_awaddr <= s_axi_awaddr;
else
axi_awaddr <= axi_awaddr;
end
// Implement axi_wready generation
// axi_wready is asserted for one clk clock cycle when both
// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge clk ) begin
if ( resetn == 1'b0 )
axi_wready <= 1'b0;
else if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en )
axi_wready <= 1'b1;
else
axi_wready <= 1'b0;
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid;
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge clk )
begin
if ( resetn == 1'b0 )
axi_bvalid <= 0;
else if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid)
axi_bvalid <= 1'b1;
else if (s_axi_bready && axi_bvalid)
axi_bvalid <= 1'b0;
end
// Implement axi_arready generation
// axi_arready is asserted for one clk clock cycle when
// s_axi_arvalid is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when s_axi_arvalid is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge clk ) begin
if ( resetn == 1'b0 )
axi_arready <= 1'b0;
else if (~axi_arready && s_axi_arvalid)
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
else
axi_arready <= 1'b0;
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one clk clock cycle when both
// s_axi_arvalid and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge clk ) begin
if ( resetn == 1'b0 )
axi_rvalid <= 0;
else if (axi_arready && s_axi_arvalid && ~axi_rvalid)
axi_rvalid <= 1'b1;
else if (axi_rvalid && s_axi_rready)
axi_rvalid <= 1'b0;
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid;
endmodule |
module FBModule(
input clk,
input store_strb,
input [1:0] sel,
input signed[12:0] ai_in,
input signed [12:0] aq_in,
input signed [12:0] bi_in,
input signed [12:0] bq_in,
input signed [12:0] ci_in,
input signed [12:0] cq_in,
input [7:0] b1_strobe_b,
input [7:0] b2_strobe_b,
input signed [12:0] q_signal,
input delay_en,
input slow_clk,
input [6:0] bpm_lut_dinb,
input [14:0] bpm_lut_addrb,
input bpm1_i_lut_web,
input bpm1_q_lut_web,
input bpm2_i_lut_web,
input bpm2_q_lut_web,
input signed [12:0] banana_corr,
input const_dac_en,
input signed [12:0] const_dac,
input [1:0] no_bunches_b,
input [3:0] no_samples_b,
input [7:0] sample_spacing_b,
output reg [12:0] fb_sgnl,
output [6:0] bpm2_i_lut_doutb,
output [6:0] bpm2_q_lut_doutb,
output [6:0] bpm1_i_lut_doutb,
output [6:0] bpm1_q_lut_doutb,
output reg dac_cond
);
wire signed [14:0] bpm1_i_reg_int, bpm1_q_reg_int,bpm2_i_reg_int,bpm2_q_reg_int;
//reg dac_cond;
reg [1:0] no_bunches_a,no_bunches;
reg [3:0] no_samples_a, no_samples;
reg [7:0] sample_spacing_a, sample_spacing;
reg [7:0] b1_strobe_a, b1_strobe;
reg [7:0] b2_strobe_a, b2_strobe;
always @ (posedge clk) begin
no_bunches_a<=no_bunches_b;
no_bunches<=no_bunches_a;
no_samples_a<=no_samples_b;
no_samples<=no_samples_a;
sample_spacing_a<=sample_spacing_b;
sample_spacing<=sample_spacing_a;
b1_strobe_a<=b1_strobe_b;
b1_strobe<=b1_strobe_a;
b2_strobe_a<=b2_strobe_b;
b2_strobe<=b2_strobe_a;
end
//parameter NO_BUNCHES=2; // Number of bunches
//parameter NO_SAMPLES=1; // Number of samples
//parameter SAMPLE_SPACING=100; // Number of samples between consecutive bunches
Timing TimingStrobes(
.no_bunches(no_bunches),
.no_samples(no_samples),
.sample_spacing(sample_spacing),
.bunch_strb(bunch_strb),
.store_strb(store_strb),
.clk(clk),
.b1_strobe(b1_strobe), // For dipole signal
.b2_strobe(b2_strobe),
.LUTcond(LUTcond)
);
MuxModule Multiplexers(
.bunch_strb(bunch_strb),
.sel(sel),
.ai_in(ai_in),
.aq_in(aq_in),
.bi_in(bi_in),
.bq_in(bq_in),
.ci_in(ci_in),
.cq_in(cq_in),
.bpm1_q_reg_int_a(bpm1_q_reg_int),
.bpm1_i_reg_int_a(bpm1_i_reg_int),
.bpm2_q_reg_int_a(bpm2_q_reg_int),
.bpm2_i_reg_int_a(bpm2_i_reg_int),
.clk(clk), // static offset to be applied to I or Q
.dac_cond(dac_cond)
);
// ***** LUT to gain scale *****
// Read out LUT when store strobe goes low
wire signed [20:0] g1_inv_q,g2_inv_q,g3_inv_q,g4_inv_q;
////reg fb_cond;
//reg [6:0] bpm1_i_lut_dinb1, bpm1_i_lut_dinb2;
//always @ (posedge clk) begin
//bpm1_i_lut_dinb2<=bpm1_i_lut_dinb;
//bpm1_i_lut_dinb1<=bpm1_i_lut_dinb2;
//end
LUTCalc LookUpTableModule(
.clk(clk),
.slow_clk(slow_clk),
.bpm1_i_lut_dinb(bpm_lut_dinb),
.bpm1_i_lut_addrb(bpm_lut_addrb),
.bpm1_i_lut_web(bpm1_i_lut_web),
.bpm1_i_lut_doutb(bpm1_i_lut_doutb),
.bpm1_q_lut_dinb(bpm_lut_dinb),
.bpm1_q_lut_addrb(bpm_lut_addrb),
.bpm1_q_lut_web(bpm1_q_lut_web),
.bpm1_q_lut_doutb(bpm1_q_lut_doutb),
.bpm2_i_lut_dinb(bpm_lut_dinb),
.bpm2_i_lut_addrb(bpm_lut_addrb),
.bpm2_i_lut_web(bpm2_i_lut_web),
.bpm2_i_lut_doutb(bpm2_i_lut_doutb),
.bpm2_q_lut_dinb(bpm_lut_dinb),
.bpm2_q_lut_addrb(bpm_lut_addrb),
.bpm2_q_lut_web(bpm2_q_lut_web),
.bpm2_q_lut_doutb(bpm2_q_lut_doutb),
.q_signal(q_signal),
.bpm1_i_lut_out(g1_inv_q),
.bpm1_q_lut_out(g2_inv_q),
.bpm2_i_lut_out(g3_inv_q),
.bpm2_q_lut_out(g4_inv_q),
.store_strb(store_strb),
.b2_strobe(b2_strobe), // for reference signal
.LUTcond(LUTcond)
);
// ***** DSP48E modules *****
// Charge and dipole signals in
// I/q + Q/q + I/q + Q/q out
//wire signed [12:0] DSPout, DSPout2, DSPout3, DSPout4;
wire signed [12:0] pout, pout2, pout3, pout4;
//wire signed [47:0] pout_a, pout2_a, pout3_a, pout4_a;
DSPCalcModule DSPModule1(
.charge_in(g1_inv_q),
.signal_in(bpm1_i_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr),
.fb_cond(fb_cond)
);
DSPCalcModule DSPModule2(
.charge_in(g2_inv_q),
.signal_in(bpm1_q_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout2),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr)
);
DSPCalcModule DSPModule3(
.charge_in(g3_inv_q),
.signal_in(bpm2_i_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout3),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr)
);
DSPCalcModule DSPModule4(
.charge_in(g4_inv_q),
.signal_in(bpm2_q_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout4),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr)
);
// ***** Clock DAC/Assign fb_sgnl *****
reg signed [12:0] sum1, sum2;
reg output_cond1, output_cond2;
always @ (posedge clk)begin
dac_cond<=fb_cond;
sum1<=pout+pout2;
sum2<=pout3+pout4;
output_cond1<=dac_cond & !const_dac_en;
output_cond2<=dac_cond & const_dac_en;
if (output_cond1) fb_sgnl<=sum1+sum2; // If reference not delayed by two samples then increase j accordingly
else if (output_cond2) fb_sgnl<=const_dac;
//else if (output_cond2) fb_sgnl<=const_dac;
else fb_sgnl<=0;
end
endmodule |
module nios_tester_jtagdebug (
output wire [25:0] mm_write_address, // mm_write.address
output wire mm_write_write, // .write
output wire [7:0] mm_write_writedata, // .writedata
input wire mm_write_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_n_reset_n, // reset_n.reset_n
input wire [31:0] csr_writedata, // csr.writedata
input wire csr_write, // .write
input wire [3:0] csr_byteenable, // .byteenable
output wire [31:0] csr_readdata, // .readdata
input wire csr_read, // .read
input wire [2:0] csr_address, // .address
input wire descriptor_slave_write, // descriptor_slave.write
output wire descriptor_slave_waitrequest, // .waitrequest
input wire [127:0] descriptor_slave_writedata, // .writedata
input wire [15:0] descriptor_slave_byteenable, // .byteenable
output wire csr_irq_irq, // csr_irq.irq
input wire [7:0] st_sink_data, // st_sink.data
input wire st_sink_valid, // .valid
output wire st_sink_ready // .ready
);
wire dispatcher_internal_write_command_source_valid; // dispatcher_internal:src_write_master_valid -> write_mstr_internal:snk_command_valid
wire [255:0] dispatcher_internal_write_command_source_data; // dispatcher_internal:src_write_master_data -> write_mstr_internal:snk_command_data
wire dispatcher_internal_write_command_source_ready; // write_mstr_internal:snk_command_ready -> dispatcher_internal:src_write_master_ready
wire write_mstr_internal_response_source_valid; // write_mstr_internal:src_response_valid -> dispatcher_internal:snk_write_master_valid
wire [255:0] write_mstr_internal_response_source_data; // write_mstr_internal:src_response_data -> dispatcher_internal:snk_write_master_data
wire write_mstr_internal_response_source_ready; // dispatcher_internal:snk_write_master_ready -> write_mstr_internal:src_response_ready
dispatcher #(
.MODE (2),
.RESPONSE_PORT (2),
.DESCRIPTOR_INTERFACE (0),
.DESCRIPTOR_FIFO_DEPTH (8),
.ENHANCED_FEATURES (0),
.DESCRIPTOR_WIDTH (128),
.DESCRIPTOR_BYTEENABLE_WIDTH (16)
) dispatcher_internal (
.clk (clock_clk), // clock.clk
.reset (~reset_n_reset_n), // clock_reset.reset
.csr_writedata (csr_writedata), // CSR.writedata
.csr_write (csr_write), // .write
.csr_byteenable (csr_byteenable), // .byteenable
.csr_readdata (csr_readdata), // .readdata
.csr_read (csr_read), // .read
.csr_address (csr_address), // .address
.descriptor_write (descriptor_slave_write), // Descriptor_Slave.write
.descriptor_waitrequest (descriptor_slave_waitrequest), // .waitrequest
.descriptor_writedata (descriptor_slave_writedata), // .writedata
.descriptor_byteenable (descriptor_slave_byteenable), // .byteenable
.src_write_master_data (dispatcher_internal_write_command_source_data), // Write_Command_Source.data
.src_write_master_valid (dispatcher_internal_write_command_source_valid), // .valid
.src_write_master_ready (dispatcher_internal_write_command_source_ready), // .ready
.snk_write_master_data (write_mstr_internal_response_source_data), // Write_Response_Sink.data
.snk_write_master_valid (write_mstr_internal_response_source_valid), // .valid
.snk_write_master_ready (write_mstr_internal_response_source_ready), // .ready
.csr_irq (csr_irq_irq), // csr_irq.irq
.src_response_data (), // (terminated)
.src_response_valid (), // (terminated)
.src_response_ready (1'b0), // (terminated)
.snk_descriptor_data (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_descriptor_valid (1'b0), // (terminated)
.snk_descriptor_ready (), // (terminated)
.mm_response_waitrequest (), // (terminated)
.mm_response_byteenable (4'b0000), // (terminated)
.mm_response_address (1'b0), // (terminated)
.mm_response_readdata (), // (terminated)
.mm_response_read (1'b0), // (terminated)
.src_read_master_data (), // (terminated)
.src_read_master_valid (), // (terminated)
.src_read_master_ready (1'b0), // (terminated)
.snk_read_master_data (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_read_master_valid (1'b0), // (terminated)
.snk_read_master_ready () // (terminated)
);
write_master #(
.DATA_WIDTH (8),
.LENGTH_WIDTH (24),
.FIFO_DEPTH (256),
.STRIDE_ENABLE (0),
.BURST_ENABLE (0),
.PACKET_ENABLE (0),
.ERROR_ENABLE (0),
.ERROR_WIDTH (8),
.BYTE_ENABLE_WIDTH (1),
.BYTE_ENABLE_WIDTH_LOG2 (1),
.ADDRESS_WIDTH (26),
.FIFO_DEPTH_LOG2 (8),
.SYMBOL_WIDTH (8),
.NUMBER_OF_SYMBOLS (1),
.NUMBER_OF_SYMBOLS_LOG2 (1),
.MAX_BURST_COUNT_WIDTH (1),
.UNALIGNED_ACCESSES_ENABLE (0),
.ONLY_FULL_ACCESS_ENABLE (1),
.BURST_WRAPPING_SUPPORT (0),
.PROGRAMMABLE_BURST_ENABLE (0),
.MAX_BURST_COUNT (1),
.FIFO_SPEED_OPTIMIZATION (1),
.STRIDE_WIDTH (1),
.ACTUAL_BYTES_TRANSFERRED_WIDTH (32)
) write_mstr_internal (
.clk (clock_clk), // Clock.clk
.reset (~reset_n_reset_n), // Clock_reset.reset
.master_address (mm_write_address), // Data_Write_Master.address
.master_write (mm_write_write), // .write
.master_writedata (mm_write_writedata), // .writedata
.master_waitrequest (mm_write_waitrequest), // .waitrequest
.snk_data (st_sink_data), // Data_Sink.data
.snk_valid (st_sink_valid), // .valid
.snk_ready (st_sink_ready), // .ready
.snk_command_data (dispatcher_internal_write_command_source_data), // Command_Sink.data
.snk_command_valid (dispatcher_internal_write_command_source_valid), // .valid
.snk_command_ready (dispatcher_internal_write_command_source_ready), // .ready
.src_response_data (write_mstr_internal_response_source_data), // Response_Source.data
.src_response_valid (write_mstr_internal_response_source_valid), // .valid
.src_response_ready (write_mstr_internal_response_source_ready), // .ready
.master_byteenable (), // (terminated)
.master_burstcount (), // (terminated)
.snk_sop (1'b0), // (terminated)
.snk_eop (1'b0), // (terminated)
.snk_empty (1'b0), // (terminated)
.snk_error (8'b00000000) // (terminated)
);
endmodule |
module sky130_fd_sc_ms__nor4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule |
module supersaw (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../Samples/Supersaw/supersaw_8080.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module uart_light_tx_ctrl
#(
parameter STATE_COUNT = 2,
parameter IDLE = 2'b00,
parameter LOAD = 2'b01,
parameter TRANSMITTING = 2'b10
)(
input wire reset,
input wire clk_tx,
//Interfaces zum SPMC
input wire word_ready,
output wire fifo_tx_full,
output wire fifo_tx_empty,
//Interfaces zum Datenpfad-Module, welche durch clk_tx getrieben werden
input wire frame_done,
output reg transmit,
output reg clear,
output reg fifo_read_enable,
//Interfaces zum Datenpfad-Module, welche durch clk_peri getrieben werden
input wire fifo_full,
input wire fifo_empty,
output wire fifo_write_enable
);
reg [STATE_COUNT-1:0] state_cur, state_next;
assign fifo_tx_full = fifo_full;
assign fifo_tx_empty = fifo_empty;
assign fifo_write_enable = word_ready & (~fifo_full);
always @(*) begin
transmit = 1'b0;
clear = 1'b0;
fifo_read_enable = 1'b0;
state_next = IDLE;
case(state_cur)
IDLE:
if (fifo_empty == 1'b0) begin
state_next = LOAD;
end
LOAD:
begin
fifo_read_enable = 1'b1;
state_next = TRANSMITTING;
end
TRANSMITTING:
if(frame_done) begin
clear = 1'b1;
state_next = IDLE;
end
else begin
transmit = 1'b1;
state_next = TRANSMITTING;
end
default: state_next = IDLE;
endcase
end
always @(posedge clk_tx, posedge reset) begin
if(reset) begin
state_cur <= IDLE;
end
else begin
state_cur <= state_next;
end
end
endmodule |
module WcaLimeIF
(
input clock_dsp, //DSP Sampling Clock, which can be substantially faster than the other clocks.
input clock_rx, //Rx Clock Interface 2x Sample rate
input clock_tx, //Tx Clock Interface 2x Sample rate
input reset, //Resets configuration and clears state.
input aclr, //Clears state but not configuration
//Internal Bus I/O
input wire [23:0] tx_iq, //Transmit I/Q data stream input (12 bits each).
output reg [23:0] rx_iq, //Receive I/Q data stream output (12 bits each).
output wire rx_strobe, //Baseband processing receive sample strobe output.
output wire tx_strobe, //Baseband processing transmit sample strobe output.
// LIME Chip Baseband interface.
output wire rf_rxclk, //Lime receive ADC clock.
input wire rf_rxiqsel,
output wire rf_rxen,
input wire [11:0] rf_rxdata,
output wire rf_txclk, //Lime transmit ADC clock.
output wire rf_txiqsel,
output wire rf_txen,
output wire [11:0] rf_txdata,
//Control Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter CTRL_ADDR = 0;
parameter RSSI_ADDR = 0;
parameter RXBIAS_ADDR = 0;
//RF Interface. (WRITE)
// bit# | Description
//-------|----------------------------------------------------------
// 0-1 RX Input Mode
// 0 = tx_iq loopback
// 1 = rf_rxdata input (dc bias removed).
// 2 = rf_rxdata input (raw).
// 3 = Fixed Test Pattern i = 256, q = -256;
// 2-3 TX Ouput Mode
// 0 = rf_rxdata loopback
// 1 = rf_txdata input.
// 2 = Fixed Test Pattern i = 256, q = -256;
// 3 = Fixed Test Pattern i = 0, q = 0;
// 4 "rf_rxen" output line - set to 1 to enable, 0 to disable. Enables disables the
// Lime chip #1 receive ADC function.
//
// 5 "rf_txen" output pin state - set to 1 to enable, 0 to disable Enables / disables the
// Lime chip #1 transmit DAC function.
//
// 6 "rf_rxclk" enable (1) / (0). If enabled the rf_rxclk pin will turn on and provide clock
// signals to the receive functions of the Lime chips.
//
// 7 "rf_txclk" enable (1) / (0). If enabled the tx_rxclk pin will turn on and provide clock
// signals to the transmit functions of Lime chip #1. If disabled, clock output will be low.
wire [7:0] rf_ctrl;
//Control Register
WcaWriteByteReg #(CTRL_ADDR) wr_rf_ctrl
(.reset(reset), .out( rf_ctrl), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//------------------------------------------------------------
// Lime chip control.
//------------------------------------------------------------
WcaSynchEdgeDetect synchRxEnable ( .clk(clock_rx), .in(rf_ctrl[4]), .out(rf_rxen));
WcaSynchEdgeDetect synchTxEnable ( .clk(clock_rx), .in(rf_ctrl[4]), .out(rf_txen));
//Buffer the clock output so the internal clock
//fanout is not driving the output pins.
ODDR2 oddr2_rxclk ( .D0(1'b1), .D1(1'b0), .CE(rf_ctrl[6]), .C0(clock_rx), .C1(~clock_rx), .Q(rf_rxclk) );
ODDR2 oddr2_txclk ( .D0(1'b1), .D1(1'b0), .CE(rf_ctrl[7]), .C0(clock_tx), .C1(~clock_tx), .Q(rf_txclk) );
//------------------------------------------------------------
// Receiver Interface Selector.
//------------------------------------------------------------
wire clearState = reset | aclr;
wire [11:0] rx_DciBiasRemoved; //These are provided by the DC Offset calculation
reg [1:0] reg_rxstrobe;
//Shape RX strobe as a 1 clock pulse strobe.
always @(posedge clock_dsp)
begin
if( clearState)
begin
reg_rxstrobe[0] <= 1'b0;
reg_rxstrobe[1] <= 1'b0;
end
else
begin
reg_rxstrobe[0] <= ~rf_rxiqsel & ~reg_rxstrobe[1] &~reg_rxstrobe[0];
reg_rxstrobe[1] <= reg_rxstrobe[0];
//reg_rxstrobe[2] <= reg_rxstrobe[1];
//reg_rxstrobe[3] <= reg_rxstrobe[2];
end
end
assign rx_strobe = reg_rxstrobe[1] & rf_ctrl[6];
//Break out receive data into separate I/Q paths
//so we can process in dsp.
always @(posedge clock_dsp)
begin
case( { rf_ctrl[1:0]} )
2'b00 : // 0 is loop back.tx back on to rx.
begin
rx_iq <= #1 tx_iq;
end
2'b01 : //Rx data with DC Offset Removed.
begin
if( rf_rxiqsel )
rx_iq[11:0] <= #1 rx_DciBiasRemoved;
else
rx_iq[23:12] <= #1 rx_DciBiasRemoved;
end
2'b10 : //2 raw rx data,.
begin
if( rf_rxiqsel )
rx_iq[11:0] <= #1 rf_rxdata;
else
rx_iq[23:12] <= #1 rf_rxdata;
end
default: // 2 is fixed test pattern
begin
rx_iq <= #1 24'hF00100; //256,-256 I & Q.
end
endcase
end
//------------------------------------------------------------
// Transmitter Interface Selector.
//------------------------------------------------------------
reg [1:0] reg_txstrobe;
reg [23:0] txdata;
reg txiqsel;
// Generate TX IQ select clock.
always @(posedge clock_tx)
begin
if( clearState)
txiqsel <= 1'h0;
else
txiqsel <= ~txiqsel;
end
//disable IQ select when no clocking.
assign rf_txiqsel = txiqsel & rf_ctrl[7];
// Generate TX IQ select clock.
always @(posedge clock_dsp)
begin
if( clearState)
begin
reg_txstrobe[0] <= 1'b0;
reg_txstrobe[1] <= 1'b0;
txdata <= 24'h0;
end
else
begin
reg_txstrobe[0] <= ~rf_txiqsel & ~reg_txstrobe[1] &~reg_txstrobe[0];
reg_txstrobe[1] <= reg_txstrobe[0];
txdata <= (reg_txstrobe[0]) ? tx_iq : txdata;
end
end
assign tx_strobe = reg_txstrobe[1] & rf_ctrl[7];
assign rf_txdata = ( rf_ctrl[3:2] == 2'b00) // Loop back tx to rx
? rf_rxdata
: ((rf_ctrl[3:2] == 2'b01) // 1 tx.
? ((txiqsel)? txdata[11:00] : txdata[23:12] ) //When iqsel is 1
: ((rf_ctrl[3:2] == 2'b10) // test pattern
? ((txiqsel) ? 12'h100 : 12'hF00)
: 12'h0));
//------------------------------------------------------------
// RX RSSI Implementation
//------------------------------------------------------------
wire [7:0] rssi_q;
wire [7:0] rssi_i;
//Construct Inphase RSSI function
WcaRssi RssiInphase(
.clock(clock_dsp), .reset(clearState), .strobe(rx_strobe), .adc(rx_iq[11:00]), .rssi(rssi_i) );
//RSSI Quadrature Function
WcaRssi RssiQuadrature(
.clock(clock_dsp), .reset(clearState), .strobe(rx_strobe), .adc(rx_iq[23:12]), .rssi(rssi_q) );
//Place the RSSI values into a register for retrieval.
WcaReadWordReg #(RSSI_ADDR) RxRssiReadReg
( .reset(reset), .clock(clock_dsp), .enableIn(rx_strobe), .in( {rssi_q, rssi_i} ), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//------------------------------------------------------------
// RX DC Bias Detection.
//------------------------------------------------------------
wire [11:0] dcOffset;
WcaDcOffset DcOffsetRemove(
.clock(clock_rx), .reset(clearState), .strobe(1'h1), .iqSel(rf_rxiqsel), .sig_in(rf_rxdata), .dcoffset( dcOffset), .sigout(rx_DciBiasRemoved));
//Place the DCOffset values into registers for retrieval.
//WcaReadDwordReg #(RXBIAS_ADDR) RxBiasReadReg
//( .reset(reset), .clock(clock_dsp), .enableIn(rx_strobe), .in( {dcOffset_i, dcOffset_q} ), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
endmodule |
module
en, // if zero will reset transpose memory page njumbers
start, // single-cycle start pulse that goes with the first pixel data. Other 63 should follow
xin, // [7:0] - input data
last_in, // output high during input of the last of 64 pixels in a 8x8 block
pre_first_out,// 1 cycle ahead of the first output in a 64 block
dv, // data output valid. Will go high on the 94-th cycle after the start
d_out);// [8:0]output data
input clk;
input en,start;
input [9:0] xin;
output last_in;
output pre_first_out;
output dv;
output [12:0] d_out;
wire clk, en,start,dv,stage1_done, tm_page,tm_we;
wire [9:0] xin;
wire [12:0] d_out;
wire [6:0] tm_ra;
wire [6:0] tm_wa;
wire [15:0] tm_out;
wire [15:0] tm_di;
reg last_in;
wire pre_first_out;
always @ (posedge clk) last_in <= (tm_wa[5:0]== 6'h30);
dct_stage1 i_dct_stage1( .clk(clk),
.en(en),
.start(start),
.xin(xin), // [7:0]
.we(tm_we), // write to transpose memory
.wr_cntr(tm_wa), // [6:0] transpose memory write address
.z_out(tm_di[15:0]),
.page(tm_page),
.done(stage1_done));
dct_stage2 i_dct_stage2( .clk(clk),
.en(en),
.start(stage1_done), // stage 1 finished, data available in transpose memory
.page(tm_page), // transpose memory page finished, valid at start
.rd_cntr(tm_ra[6:0]), // [6:0] transpose memory read address
.tdin(tm_out[15:0]), // [7:0] - data from transpose memory
.endv(pre_first_out),
.dv(dv), // data output valid
.dct2_out(d_out[12:0]));// [10:0]output data
RAMB16_S18_S18 i_transpose_mem (
.DOA(), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA({3'b0,tm_wa[6:0]}), // Port A 10-bit Address Input
.CLKA(clk), // Port A Clock
// .DIA({6'b0,tm_di[9:0]}), // Port A 16-bit Data Input
.DIA(tm_di[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(tm_we), // Port A Write Enable Input
.DOB(tm_out[15:0]), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({3'b0,tm_ra[6:0]}), // Port B 10-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(16'b0), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(1'b1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule |
module dct_stage1 ( clk,
en,
start, // single-cycle start pulse to replace RST
xin, // [7:0]
we, // write to transpose memory
wr_cntr, // [6:0] transpose memory write address
z_out, //data to transpose memory
page, // transpose memory page just filled (valid @ done)
done); // last cycle writing to transpose memory - may use after it (move it earlier?)
input clk;
input en,start;
input [9:0] xin;
output we;
output [6:0] wr_cntr;
output [15:0] z_out;
output page;
output done;
/* constants */
parameter C3= 16'd54491;
parameter S3= 16'd36410;
parameter C4= 16'd46341;
parameter C6= 16'd25080;
parameter S6= 16'd60547;
parameter C7= 16'd12785;
parameter S7= 16'd64277;
reg[16:0] memory1a, memory2a, memory3a, memory4a;
/* 1D section */
/* The max value of a pixel after processing (to make their expected mean to zero)
is 127. If all the values in a row are 127, the max value of the product terms
would be (127*2)*(23170/256) and that of z_out_int would be (127*8)*23170/256.
This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of the value */
reg[9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in;
reg[9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg;
reg[9:0] addsub1a_comp,addsub2a_comp,addsub3a_comp,addsub4a_comp;
reg[10:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a;
reg save_sign1a, save_sign2a, save_sign3a, save_sign4a;
reg[17:0] p1a,p2a,p3a,p4a;
wire[35:0] p1a_all,p2a_all,p3a_all,p4a_all;
reg toggleA;
reg[18:0] z_out_int1,z_out_int2;
reg[18:0] z_out_int;
wire[15:0] z_out_prelatch;
reg [2:0] indexi;
/* clks and counters */
reg [6:0] wr_cntr_prelatch;
/* memory section */
reg done_prelatch;
reg we_prelatch;
wire enwe;
wire pre_sxregs;
reg sxregs;
reg page_prelatch;
// outputs from output latches to cross clock edge boundary
//wire[9:0] z_out;
//wire[6:0] wr_cntr;
//wire done;
//wire we;
//wire page;
// outputs from output latches to cross clock edge boundary
reg [15:0] z_out;
reg [ 6:0] wr_cntr;
reg done;
reg we;
reg page;
// to conserve energy by disabling toggleA
wire sxregs_d8;
reg enable_toggle;
SRL16_1 i_sxregs_d8 (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs)); // dly=7+1
always @ (negedge clk) enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
always @ (negedge clk) done_prelatch<= (wr_cntr_prelatch[5:0]==6'h3f);
always @ (negedge clk) if (wr_cntr_prelatch[5:0]==6'h3f) page_prelatch <= wr_cntr_prelatch[6];
always @ (negedge clk) we_prelatch<= enwe || (en && we_prelatch && (wr_cntr_prelatch[5:0]!=6'h3f));
always @ (negedge clk )
if (!en) wr_cntr_prelatch <= 7'b0;
else if (we_prelatch) wr_cntr_prelatch <= wr_cntr_prelatch + 1;
SRL16_1 i_pre_sxregs (.Q(pre_sxregs), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(start)); // dly=6+1
SRL16_1 i_enwe (.Q(enwe), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(pre_sxregs)); // dly=5+1
always @ (negedge clk ) sxregs <= pre_sxregs || ((wr_cntr_prelatch[2:0]==3'h1) && (wr_cntr_prelatch[5:3]!=3'h7));
always @ (negedge clk) toggleA <= sxregs || (enable_toggle && (~toggleA));
always @ (negedge clk)
if (sxregs) indexi <= 3'h7;
else if (enable_toggle) indexi<=indexi+1;
/* 1D-DCT BEGIN */
// store 1D-DCT constant coeeficient values for multipliers */
always @ (negedge clk)
begin
case (indexi)
0 : begin memory1a <= {1'b0,C4}; //8'd91
memory2a <= {1'b0,C4}; //8'd91
memory3a <= {1'b0,C4}; //8'd91
memory4a <= {1'b0,C4}; //8'd91
end
1 : begin memory1a <= {1'b0,S7}; //8'd126;
memory2a <= {1'b0,C3}; //8'd106;
memory3a <= {1'b0,S3}; //8'd71;
memory4a <= {1'b0,C7}; //8'd25;
end
2 : begin memory1a <= {1'b0,S6}; //8'd118;
memory2a <= {1'b0,C6}; //8'd49;
memory3a <= {1'b1,C6}; //-8'd49;
memory4a <= {1'b1,S6}; //-8'd118
end
3 : begin memory1a <= {1'b0,C3}; // 8'd106;
memory2a <= {1'b1,C7}; //-8'd25;
memory3a <= {1'b1,S7}; //-8'd126;
memory4a <= {1'b1,S3}; //-8'd71;
end
4 : begin memory1a <= {1'b0,C4}; // 8'd91;
memory2a <= {1'b1,C4}; //-8'd91;
memory3a <= {1'b1,C4}; //-8'd91;
memory4a <= {1'b0,C4}; // 8'd91;
end
5 : begin memory1a <= {1'b0,S3}; // 8'd71;
memory2a <= {1'b1,S7}; //-8'd126;
memory3a <= {1'b0,C7}; // 8'd25;
memory4a <= {1'b0,C3}; // 8'd106;
end
6 : begin memory1a <= {1'b0,C6}; // 8'd49;
memory2a <= {1'b1,S6}; //-8'd118;
memory3a <= {1'b0,S6}; // 8'd118;
memory4a <= {1'b1,C6}; //-8'd49;
end
7 : begin memory1a <= {1'b0,C7}; // 8'd25;
memory2a <= {1'b1,S3}; //-8'd71;
memory3a <= {1'b0,C3}; // 8'd106;
memory4a <= {1'b1,S7}; //-8'd126;
end
endcase
end
/* 8-bit input shifted 8 times thru a shift register*/
// xa0_in will see output registers from posedge, may be replaced by latches if needed - but currently delay is under 5ns
always @ (negedge clk)
begin
xa0_in <= xin; xa1_in <= xa0_in; xa2_in <= xa1_in; xa3_in <= xa2_in;
xa4_in <= xa3_in; xa5_in <= xa4_in; xa6_in <= xa5_in; xa7_in <= xa6_in;
end
/* shifted inputs registered every 8th clk (using cntr8)*/
always @ (negedge clk)
if (sxregs)
begin
xa0_reg <= {xa0_in}; xa1_reg <= {xa1_in};
xa2_reg <= {xa2_in}; xa3_reg <= {xa3_in};
xa4_reg <= {xa4_in}; xa5_reg <= {xa5_in};
xa6_reg <= {xa6_in}; xa7_reg <= {xa7_in};
end
/* adder / subtractor block */
always @ (negedge clk)
if (toggleA == 1'b1) begin
add_sub1a <= ({xa7_reg[9],xa7_reg[9:0]} + {xa0_reg[9],xa0_reg[9:0]});
add_sub2a <= ({xa6_reg[9],xa6_reg[9:0]} + {xa1_reg[9],xa1_reg[9:0]});
add_sub3a <= ({xa5_reg[9],xa5_reg[9:0]} + {xa2_reg[9],xa2_reg[9:0]});
add_sub4a <= ({xa4_reg[9],xa4_reg[9:0]} + {xa3_reg[9],xa3_reg[9:0]});
end else begin
add_sub1a <= ({xa7_reg[9],xa7_reg[9:0]} - {xa0_reg[9],xa0_reg[9:0]});
add_sub2a <= ({xa6_reg[9],xa6_reg[9:0]} - {xa1_reg[9],xa1_reg[9:0]});
add_sub3a <= ({xa5_reg[9],xa5_reg[9:0]} - {xa2_reg[9],xa2_reg[9:0]});
add_sub4a <= ({xa4_reg[9],xa4_reg[9:0]} - {xa3_reg[9],xa3_reg[9:0]});
end
// First valid add_sub appears at the 10th clk (8 clks for shifting inputs,
// 9th clk for registering shifted input and 10th clk for add_sub
// to synchronize the i value to the add_sub value, i value is incremented
// only after 10 clks
// Adding these wires to get rid of the MSB that is always 0
wire [10:0] addsub1a_comp_w = add_sub1a[10]? (-add_sub1a) : add_sub1a;
wire [10:0] addsub2a_comp_w = add_sub2a[10]? (-add_sub2a) : add_sub2a;
wire [10:0] addsub3a_comp_w = add_sub3a[10]? (-add_sub3a) : add_sub3a;
wire [10:0] addsub4a_comp_w = add_sub4a[10]? (-add_sub4a) : add_sub4a;
always @ (negedge clk) begin
save_sign1a <= add_sub1a[10];
save_sign2a <= add_sub2a[10];
save_sign3a <= add_sub3a[10];
save_sign4a <= add_sub4a[10];
addsub1a_comp <= addsub1a_comp_w[9:0]; //add_sub1a[10]? (-add_sub1a) : add_sub1a;
addsub2a_comp <= addsub2a_comp_w[9:0]; //add_sub2a[10]? (-add_sub2a) : add_sub2a;
addsub3a_comp <= addsub3a_comp_w[9:0]; //add_sub3a[10]? (-add_sub3a) : add_sub3a;
addsub4a_comp <= addsub4a_comp_w[9:0]; //add_sub4a[10]? (-add_sub4a) : add_sub4a;
end
assign p1a_all = addsub1a_comp * memory1a[15:0];
assign p2a_all = addsub2a_comp * memory2a[15:0];
assign p3a_all = addsub3a_comp * memory3a[15:0];
assign p4a_all = addsub4a_comp * memory4a[15:0];
always @ (negedge clk)
begin
p1a <= (save_sign1a ^ memory1a[16]) ? (-p1a_all[26:9]) :(p1a_all[26:9]);
p2a <= (save_sign2a ^ memory2a[16]) ? (-p2a_all[26:9]) :(p2a_all[26:9]);
p3a <= (save_sign3a ^ memory3a[16]) ? (-p3a_all[26:9]) :(p3a_all[26:9]);
p4a <= (save_sign4a ^ memory4a[16]) ? (-p4a_all[26:9]) :(p4a_all[26:9]);
end
//
/* Final adder. Adding the ouputs of the 4 multipliers */
always @ (negedge clk)
begin
z_out_int1 <= ({p1a[17],p1a} + {p2a[17],p2a});
z_out_int2 <= ({p3a[17],p3a} + {p4a[17],p4a});
z_out_int <= (z_out_int1 + z_out_int2);
end
// rounding of the value
//assign z_out_rnd[15:0] = z_out_int[17:2];
//assign z_out_prelatch[15:0] = z_out_int[17:2]+ z_out_int[1]; // correct rounding
assign z_out_prelatch[15:0] = z_out_int[18:3]+ z_out_int[2]; // correct rounding
//wire TEST_zout= z_out_int[17] ^z_out_int[16];
// outputs from output latches to cross clock edge boundary
always @ (posedge clk)
begin
z_out[15:0] <= z_out_prelatch[15:0];
wr_cntr[6:0] <= wr_cntr_prelatch[6:0];
done <= done_prelatch;
we <= we_prelatch;
page <= page_prelatch;
end
/* 1D-DCT END */
endmodule |
module dct_stage2 ( clk,
en,
start, // stage 1 finished, data available in transpose memory
page, // transpose memory page finished, valid at start
rd_cntr, // [6:0] transpose memory read address
tdin, // [15:0] - data from transpose memory
endv, // one cycle ahead of starting (continuing) dv
dv, // data output valid
dct2_out);// [8:0]output data
input clk;
input en,start,page;
// input [9:0] tdin;
input [15:0] tdin; //added 6 bit fractional part
output [6:0] rd_cntr;
// output [11:0] dct2_out;
output [12:0] dct2_out;
output dv;
output endv;
// wire [11:0] dct2_out;
wire [12:0] dct2_out;
/* constants */
parameter C3= 16'd54491;
parameter S3= 16'd36410;
parameter C4= 16'd46341;
parameter C6= 16'd25080;
parameter S6= 16'd60547;
parameter C7= 16'd12785;
parameter S7= 16'd64277;
//reg[7:0] memory1a, memory2a, memory3a, memory4a;
reg[16:0] memory1a, memory2a, memory3a, memory4a;
reg [2:0] indexi;
reg dv;
/* 2D section */
//reg[9:0] xb0_in, xb1_in, xb2_in, xb3_in, xb4_in, xb5_in, xb6_in, xb7_in;
//reg[9:0] xb0_reg, xb1_reg, xb2_reg, xb3_reg, xb4_reg, xb5_reg, xb6_reg, xb7_reg;
//reg[9:0] addsub1b_comp,addsub2b_comp,addsub3b_comp,addsub4b_comp;
//reg[10:0] add_sub1b,add_sub2b,add_sub3b,add_sub4b;
reg[15:0] xb0_in, xb1_in, xb2_in, xb3_in, xb4_in, xb5_in, xb6_in, xb7_in;
reg[15:0] xb0_reg, xb1_reg, xb2_reg, xb3_reg, xb4_reg, xb5_reg, xb6_reg, xb7_reg;
reg[16:0] add_sub1b,add_sub2b,add_sub3b,add_sub4b;
reg[15:0] addsub1b_comp,addsub2b_comp,addsub3b_comp,addsub4b_comp;
reg save_sign1b, save_sign2b, save_sign3b, save_sign4b;
//reg[17:0] p1b,p2b,p3b,p4b;
reg[18:0] p1b,p2b,p3b,p4b;
wire[35:0] p1b_all,p2b_all,p3b_all,p4b_all;
reg toggleB;
reg[19:0] dct2d_int1,dct2d_int2;
reg[20:0] dct_2d_int;
wire[12:0] dct_2d_rnd;
// transpose memory read address
wire [6:0] rd_cntr;
reg [5:0] rd_cntrs;
reg rd_page;
// start with the same as stage1
//wire pre_sxregs;
wire endv;
wire sxregs;
// to conserve energy by disabling toggleB
wire sxregs_d8;
reg enable_toggle;
reg en_started;
wire disdv;
SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1
SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1
SRL16 i_sxregs (.Q(sxregs), .A0(1'b0), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(clk),.D((rd_cntr[5:3]==3'h0) && en_started)); // dly=8+1
SRL16 i_sxregs_d8 (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs && en_started)); // dly=7+1
always @ (posedge clk) enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
always @ (posedge clk) en_started <= en && (start || en_started);
always @ (posedge clk) dv <= en && (endv || (dv && ~disdv));
// always @ (posedge clk) toggleB <= sxregs || (~toggleB);
always @ (posedge clk) toggleB <= sxregs || (enable_toggle && (~toggleB));
always @ (posedge clk)
if (sxregs) indexi <= 3'h7;
// else indexi<=indexi+1;
else if (enable_toggle) indexi<=indexi+1;
always @ (posedge clk) begin
if (start) rd_page <= page;
if (start) rd_cntrs[5:0] <=6'b0; // will always count, but that does not matter- What about saving energy ;-) ? Saved...
else if (rd_cntrs[5:0]!=6'h3f) rd_cntrs[5:0] <= rd_cntrs[5:0]+1;
// else rd_cntrs[5:0] <= rd_cntrs[5:0]+1;
end
assign rd_cntr[6:0]= {rd_page,rd_cntrs[2:0],rd_cntrs[5:3]};
// duplicate memory<i>a from stage 1
// store 1D-DCT constant coeeficient values for multipliers */
always @ (posedge clk)
begin
case (indexi)
0 : begin memory1a <= {1'b0,C4}; //8'd91
memory2a <= {1'b0,C4}; //8'd91
memory3a <= {1'b0,C4}; //8'd91
memory4a <= {1'b0,C4}; //8'd91
end
1 : begin memory1a <= {1'b0,S7}; //8'd126;
memory2a <= {1'b0,C3}; //8'd106;
memory3a <= {1'b0,S3}; //8'd71;
memory4a <= {1'b0,C7}; //8'd25;
end
2 : begin memory1a <= {1'b0,S6}; //8'd118;
memory2a <= {1'b0,C6}; //8'd49;
memory3a <= {1'b1,C6}; //-8'd49;
memory4a <= {1'b1,S6}; //-8'd118
end
3 : begin memory1a <= {1'b0,C3}; // 8'd106;
memory2a <= {1'b1,C7}; //-8'd25;
memory3a <= {1'b1,S7}; //-8'd126;
memory4a <= {1'b1,S3}; //-8'd71;
end
4 : begin memory1a <= {1'b0,C4}; // 8'd91;
memory2a <= {1'b1,C4}; //-8'd91;
memory3a <= {1'b1,C4}; //-8'd91;
memory4a <= {1'b0,C4}; // 8'd91;
end
5 : begin memory1a <= {1'b0,S3}; // 8'd71;
memory2a <= {1'b1,S7}; //-8'd126;
memory3a <= {1'b0,C7}; // 8'd25;
memory4a <= {1'b0,C3}; // 8'd106;
end
6 : begin memory1a <= {1'b0,C6}; // 8'd49;
memory2a <= {1'b1,S6}; //-8'd118;
memory3a <= {1'b0,S6}; // 8'd118;
memory4a <= {1'b1,C6}; //-8'd49;
end
7 : begin memory1a <= {1'b0,C7}; // 8'd25;
memory2a <= {1'b1,S3}; //-8'd71;
memory3a <= {1'b0,C3}; // 8'd106;
memory4a <= {1'b1,S7}; //-8'd126;
end
endcase
end
always @ (posedge clk)
begin
xb0_in <= tdin; xb1_in <= xb0_in; xb2_in <= xb1_in; xb3_in <= xb2_in;
xb4_in <= xb3_in; xb5_in <= xb4_in; xb6_in <= xb5_in; xb7_in <= xb6_in;
end
/* register inputs, inputs read in every eighth clk*/
always @ (posedge clk)
if (sxregs) begin
xb0_reg <= xb0_in; xb1_reg <= xb1_in;
xb2_reg <= xb2_in; xb3_reg <= xb3_in;
xb4_reg <= xb4_in; xb5_reg <= xb5_in;
xb6_reg <= xb6_in; xb7_reg <= xb7_in;
end
always @ (posedge clk)
if (toggleB == 1'b1) begin
// add_sub1b <= ({xb7_reg[9],xb7_reg[9:0]} + {xb0_reg[9],xb0_reg[9:0]});
// add_sub2b <= ({xb6_reg[9],xb6_reg[9:0]} + {xb1_reg[9],xb1_reg[9:0]});
// add_sub3b <= ({xb5_reg[9],xb5_reg[9:0]} + {xb2_reg[9],xb2_reg[9:0]});
// add_sub4b <= ({xb4_reg[9],xb4_reg[9:0]} + {xb3_reg[9],xb3_reg[9:0]});
add_sub1b <= ({xb7_reg[15],xb7_reg[15:0]} + {xb0_reg[15],xb0_reg[15:0]});
add_sub2b <= ({xb6_reg[15],xb6_reg[15:0]} + {xb1_reg[15],xb1_reg[15:0]});
add_sub3b <= ({xb5_reg[15],xb5_reg[15:0]} + {xb2_reg[15],xb2_reg[15:0]});
add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} + {xb3_reg[15],xb3_reg[15:0]});
end else begin
// add_sub1b <= ({xb7_reg[9],xb7_reg[9:0]} - {xb0_reg[9],xb0_reg[9:0]});
// add_sub2b <= ({xb6_reg[9],xb6_reg[9:0]} - {xb1_reg[9],xb1_reg[9:0]});
// add_sub3b <= ({xb5_reg[9],xb5_reg[9:0]} - {xb2_reg[9],xb2_reg[9:0]});
// add_sub4b <= ({xb4_reg[9],xb4_reg[9:0]} - {xb3_reg[9],xb3_reg[9:0]});
add_sub1b <= ({xb7_reg[15],xb7_reg[15:0]} - {xb0_reg[15],xb0_reg[15:0]});
add_sub2b <= ({xb6_reg[15],xb6_reg[15:0]} - {xb1_reg[15],xb1_reg[15:0]});
add_sub3b <= ({xb5_reg[15],xb5_reg[15:0]} - {xb2_reg[15],xb2_reg[15:0]});
add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]});
end
// Adding these wires to get rid of the MSB that is always 0
wire [16:0] addsub1b_comp_w = add_sub1b[16]? (-add_sub1b) : add_sub1b;
wire [16:0] addsub2b_comp_w = add_sub2b[16]? (-add_sub2b) : add_sub2b;
wire [16:0] addsub3b_comp_w = add_sub3b[16]? (-add_sub3b) : add_sub3b;
wire [16:0] addsub4b_comp_w = add_sub4b[16]? (-add_sub4b) : add_sub4b;
always @ (posedge clk) begin
// save_sign1b <= add_sub1b[10];
// save_sign2b <= add_sub2b[10];
// save_sign3b <= add_sub3b[10];
// save_sign4b <= add_sub4b[10];
// addsub1b_comp <= add_sub1b[10]? (-add_sub1b) : add_sub1b;
// addsub2b_comp <= add_sub2b[10]? (-add_sub2b) : add_sub2b;
// addsub3b_comp <= add_sub3b[10]? (-add_sub3b) : add_sub3b;
// addsub4b_comp <= add_sub4b[10]? (-add_sub4b) : add_sub4b;
save_sign1b <= add_sub1b[16];
save_sign2b <= add_sub2b[16];
save_sign3b <= add_sub3b[16];
save_sign4b <= add_sub4b[16];
addsub1b_comp <= addsub1b_comp_w[15:0]; // add_sub1b[16]? (-add_sub1b) : add_sub1b;
addsub2b_comp <= addsub2b_comp_w[15:0]; // add_sub2b[16]? (-add_sub2b) : add_sub2b;
addsub3b_comp <= addsub3b_comp_w[15:0]; // add_sub3b[16]? (-add_sub3b) : add_sub3b;
addsub4b_comp <= addsub4b_comp_w[15:0]; // add_sub4b[16]? (-add_sub4b) : add_sub4b;
end
// assign p1b_all = addsub1b_comp * memory1a[15:0];
// assign p2b_all = addsub2b_comp * memory2a[15:0];
// assign p3b_all = addsub3b_comp * memory3a[15:0];
// assign p4b_all = addsub4b_comp * memory4a[15:0];
///AF2015:
// assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
// assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
// assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
// assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
assign p1b_all = addsub1b_comp * memory1a;
assign p2b_all = addsub2b_comp * memory2a;
assign p3b_all = addsub3b_comp * memory3a;
assign p4b_all = addsub4b_comp * memory4a;
always @ (posedge clk)
begin
/// Next line was simulated differently in Icarus 0.9 (wrong?) than in Icarus 0.8 (right?)
/// Xilinx probably did as 0.8
/// p1b_all[31:14] - 18-bit number, p1b - 19-bit. in 0.9 (-p1b_all[31:14]) was also 18, not expand to 19 bits, 0.8 - did
/// p1b <= (save_sign1b ^ memory1a[16]) ? (-p1b_all[31:14]) :(p1b_all[31:14]);
p1b[18:0] <= (save_sign1b ^ memory1a[16]) ? (-p1b_all[32:14]) :(p1b_all[32:14]);
p2b[18:0] <= (save_sign2b ^ memory2a[16]) ? (-p2b_all[32:14]) :(p2b_all[32:14]);
p3b[18:0] <= (save_sign3b ^ memory3a[16]) ? (-p3b_all[32:14]) :(p3b_all[32:14]);
p4b[18:0] <= (save_sign4b ^ memory4a[16]) ? (-p4b_all[32:14]) :(p4b_all[32:14]);
end
/* multiply the outputs of the add/sub block with the 8 sets of stored coefficients */
/* Final adder. Adding the ouputs of the 4 multipliers */
always @ (posedge clk)
begin
dct2d_int1 <= ({p1b[18],p1b[18:0]} + {p2b[18],p2b[18:0]});
dct2d_int2 <= ({p3b[18],p3b[18:0]} + {p4b[18],p4b[18:0]});
dct_2d_int <= ({dct2d_int1[19],dct2d_int1[19:0]} + {dct2d_int2[19],dct2d_int2[19:0]});
end
assign dct_2d_rnd[12:0] = dct_2d_int[20:8];
assign dct2_out[12:0] = dct_2d_rnd[12:0] + dct_2d_int[7];
endmodule |
module mac_test();
reg reset;
reg [31:0] data_in;
reg data_in_clock;
reg data_in_enable;
reg data_in_start;
reg data_in_end;
reg tx_clock;
reg carrier_sense;
reg collision;
wire tx_enable;
wire [7:0] tx_data;
reg [31:0] packet [0:380];
integer i;
mac U_mac (
.reset(reset),
// IN PORT
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
.tx_clock(tx_clock),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,mac_test,U_mac,U_mac.U_tx_sm,U_mac.U_tx_sm.U_crc);
end
initial
begin
$monitor("TX ENABLE: %b, TX DATA: %x", tx_enable, tx_data);
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
tx_clock = 0;
data_in_start = 0;
$readmemh("tx.hex", packet);
#15 reset = 0;
// Send a packet
push(packet[0], 1, 0);
for(i = 1; i < 14; i = i + 1)
begin
push(packet[i], 0, 0);
end
push(packet[14], 0, 1);
#120 $finish;
end
always
#20 data_in_clock = ~data_in_clock;
always
#1 tx_clock = ~tx_clock;
task push;
input[31:0] data;
input data_start;
input data_end;
begin
data_in = data;
data_in_enable = 1;
data_in_start = data_start;
data_in_end = data_end;
@(posedge data_in_clock);
#1 data_in_enable = 0;
data_in_start = 0;
data_in_end = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
endmodule |
module ovl_always_on_edge (clock, reset, enable, sampling_event, test_expr, fire, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter edge_type = `OVL_EDGE_TYPE_DEFAULT;
//OVL_POSEDGE = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input sampling_event, test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
output [`OVL_FIRE_WIDTH-1:0] fire_comb;
// Parameters that should not be edited
parameter assert_name = "OVL_ALWAYS_ON_EDGE";
`ifdef SMV
`ifdef SUBDIR
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_init.h"
`else
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_init.h"
`endif
`else
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_task.h"
`include "ovl_ported/std_ovl_init.h"
`endif
`ifdef OVL_VERILOG
`ifdef SMV
`ifdef SUBDIR
`include "vlog95/ovl_always_on_edge_logic2.v"
`else
`include "ovl_ported/vlog95/ovl_always_on_edge_logic2.v"
`endif
`else
`include "./vlog95/ovl_always_on_edge_logic2.v"
`endif
assign fire = {1'b0, 1'b0, fire_2state};
assign fire_comb = {1'b0, 1'b0, fire_2state_comb};
`endif
//(cks)2state means only 0/1, as opp to X.
//fire_2state is what we care about. properties should be how its affected.
//other 2 wires -used for simulation only. first 2 bits of hte wire for simulation of multi-value output. removed during synthesis.
`ifdef OVL_SVA
`include "./sva05/assert_always_on_edge_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_always_on_edge_psl_logic.v"
`else
`endmodule |
module IDELAYCTRL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter SIM_DEVICE = "7SERIES"
)(
output RDY,
input REFCLK,
input RST
);
// define constants
localparam MODULE_NAME = "IDELAYCTRL";
// Parameter encodings and registers
localparam SIM_DEVICE_7SERIES = 0;
localparam SIM_DEVICE_ULTRASCALE = 1;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
//`ifdef XIL_DR
// `include "IDELAYCTRL_dr.v"
//`else
localparam [80:1] SIM_DEVICE_REG = SIM_DEVICE;
//`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
reg RDY_out = 0;
wire REFCLK_in;
wire RST_in;
`ifdef XIL_TIMING
wire REFCLK_delay;
wire RST_delay;
`endif
assign RDY = RDY_out;
`ifdef XIL_TIMING
assign REFCLK_in = REFCLK_delay;
assign RST_in = RST_delay;
`else
assign REFCLK_in = REFCLK;
assign RST_in = RST;
`endif
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg lost;
reg msg_flag = 1'b0;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "7SERIES") &&
(SIM_DEVICE_REG != "ULTRASCALE"))) begin
$display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
always @(RST_in, lost) begin
if (RST_in == 1'b1) begin
RDY_out <= 1'b0;
end else if (lost == 1)
RDY_out <= 1'b0;
else if (RST_in == 1'b0 && lost == 0)
RDY_out <= 1'b1;
end
always @(posedge RST_in) begin
if (SIM_DEVICE_REG == "ULTRASCALE" && msg_flag == 1'b0) begin
$display("Info: [Unisim %s-1] RST simulation behaviour for SIM_DEVICE %s may not match hardware behaviour when I/ODELAY DELAY_FORMAT = TIME if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
msg_flag <= 1'b1;
end
end
initial begin
clock_edge <= 0;
clock_high <= 0;
clock_low <= 0;
lost <= 1;
period <= 0;
end
always @(posedge REFCLK_in) begin
if(RST_in == 1'b0) begin
clock_edge <= $time;
if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
period <= $time - clock_edge;
else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
period <= 0;
else if ((period == 0) && (clock_edge != 0))
period <= $time - clock_edge;
end
end
always @(posedge REFCLK_in) begin
clock_low <= 1'b0;
clock_high <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_posedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_low != 1'b1) && (clock_posedge != 1'b1))
lost <= 1;
end
always @(posedge REFCLK_in) begin
clock_negedge <= 1'b1;
end
always @(negedge REFCLK_in) begin
clock_posedge <= 1'b1;
end
always @(negedge REFCLK_in) begin
clock_high <= 1'b0;
clock_low <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_negedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_high != 1'b1) && (clock_negedge != 1'b1))
lost <= 1;
end
//*** Timing Checks Start here
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(RST => RDY) = (0:0:0, 0:0:0);
(posedge RST => (RDY +: 0)) = (0:0:0, 0:0:0);
(REFCLK => RDY) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge REFCLK, 0:0:0, notifier);
$period (posedge REFCLK, 0:0:0, notifier);
$recrem (negedge RST, posedge REFCLK, 0:0:0, 0:0:0, notifier, , , RST_delay, REFCLK_delay);
$recrem (posedge RST, posedge REFCLK, 0:0:0, 0:0:0, notifier, , , RST_delay, REFCLK_delay);
$width (negedge REFCLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge REFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module vio_0(clk, probe_out0, probe_out1, probe_out2, probe_out3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0]" */;
input clk;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
endmodule |
module processing_system7_bfm_v2_0_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule |
module ZUMA_TB_wrapper
(
reset,
clk,
inputs,
outputs
);
parameter LUT_SIZE = ZUMA_LUT_SIZE;
parameter NUM_STAGES = NUM_CONFIG_STAGES;
input clk;
input reset;
input [NUM_INPUTS-1:0] inputs;
output [NUM_OUTPUTS-1:0] outputs;
reg [31:0] next_address;
reg [31:0] address;
wire [CONFIG_WIDTH-1:0] cfg;
wire [CONFIG_WIDTH-1:0] cfg_in;
reg write;
reg reset_done;
reg virtual_reset;
// Reprogram the virtual device after a reset
// Generate all required configuration addresses
// Reset the virtual device after configuration
always @ (posedge clk)
begin : COUNTER
// Data fetching required one cycle after address generation
// thus we lag the actual configuration address once cycle
address <= next_address;
if (reset) begin
// Start a new config process
next_address <= 32'b0;
write <= 1'b1;
reset_done <= 1'b0;
virtual_reset <= 1'b0;
end else if (write) begin
// Generate all addresses until we are done
next_address <= next_address + 1;
if (next_address > (2**LUT_SIZE)*NUM_STAGES) begin
write <= 1'b0;
end
end else if (~reset_done) begin
// If write is finished, reset the virtual device once
virtual_reset <= 1'b1;
reset_done <= 1'b1;
end else if (virtual_reset) begin
// Pull back the virtual reset, device should be running now
virtual_reset <= 1'b0;
end else begin
// No-op, we are done.
next_address <= next_address;
end
end
// Reverse the retrieved config data, as the
// overlay requires it in reverse direction as stored
generate
genvar i;
for (i = 0; i < CONFIG_WIDTH; i = i + 1)
begin: reverse
assign cfg_in[CONFIG_WIDTH-1-i] = cfg[i];
end
endgenerate
// Fetch config data for next address
fixed_config #(.LUT_SIZE(LUT_SIZE), .NUM_STAGES(NUM_STAGES)) config_data (
.address_in(next_address),
.clock(clk),
.q(cfg)
);
// Include the actual overlay
ZUMA_custom_generated XUM (
.clk(clk),
.fpga_inputs(inputs),
.fpga_outputs(outputs),
.config_data(cfg_in),
.config_en(write),
.progress(),
.config_addr(address),
.clk2(clk),
.ffrst(virtual_reset)
);
endmodule |
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A0 = 1'b1;
#140 A1 = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A0 = 1'b0;
#240 A1 = 1'b0;
#260 S = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 S = 1'b1;
#380 A1 = 1'b1;
#400 A0 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 S = 1'bx;
#480 A1 = 1'bx;
#500 A0 = 1'bx;
end
sky130_fd_sc_hs__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule |
module sky130_fd_sc_hdll__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule |
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82,
n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96,
n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119,
n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152,
n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163,
n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313;
NAND2X1TS U47 ( .A(n37), .B(n196), .Y(n197) );
NAND2X1TS U48 ( .A(n163), .B(n35), .Y(n160) );
NAND2X1TS U49 ( .A(n211), .B(n210), .Y(n212) );
NAND2X1TS U50 ( .A(n225), .B(n224), .Y(n226) );
NAND2X1TS U51 ( .A(n177), .B(n176), .Y(n178) );
NAND2X1TS U52 ( .A(n218), .B(n217), .Y(n219) );
NAND2X1TS U53 ( .A(n36), .B(n186), .Y(n187) );
INVX4TS U54 ( .A(n204), .Y(n231) );
INVX1TS U55 ( .A(n223), .Y(n225) );
INVX1TS U56 ( .A(n209), .Y(n211) );
NOR2X1TS U57 ( .A(n298), .B(in2[5]), .Y(n308) );
NOR2X2TS U58 ( .A(n191), .B(n150), .Y(n152) );
NAND2X1TS U59 ( .A(n295), .B(n294), .Y(n298) );
NAND2X2TS U60 ( .A(n36), .B(n41), .Y(n150) );
INVX2TS U61 ( .A(n253), .Y(n30) );
XNOR2X1TS U62 ( .A(n169), .B(in2[31]), .Y(n170) );
MX2X1TS U63 ( .A(in2[29]), .B(n155), .S0(n17), .Y(n156) );
NOR2X1TS U64 ( .A(n168), .B(in2[30]), .Y(n169) );
INVX2TS U65 ( .A(n199), .Y(n145) );
NOR2X6TS U66 ( .A(n120), .B(in1[22]), .Y(n223) );
NAND2X2TS U67 ( .A(n120), .B(in1[22]), .Y(n224) );
NOR2X4TS U68 ( .A(n121), .B(in1[23]), .Y(n216) );
NOR2X2TS U69 ( .A(n119), .B(in1[21]), .Y(n221) );
NAND2X2TS U70 ( .A(n143), .B(in1[26]), .Y(n196) );
MXI2X4TS U71 ( .A(n109), .B(n108), .S0(n139), .Y(n121) );
NOR2X6TS U72 ( .A(n90), .B(in1[18]), .Y(n244) );
NAND2X6TS U73 ( .A(n82), .B(n38), .Y(n31) );
NAND2X2TS U74 ( .A(n90), .B(in1[18]), .Y(n245) );
XNOR2X1TS U75 ( .A(n115), .B(in2[20]), .Y(n96) );
OR2X6TS U76 ( .A(n87), .B(in1[17]), .Y(n38) );
INVX6TS U77 ( .A(n251), .Y(n82) );
OR2X4TS U78 ( .A(n81), .B(in1[16]), .Y(n39) );
NAND2X1TS U79 ( .A(n134), .B(n133), .Y(n137) );
NAND2X4TS U80 ( .A(n81), .B(in1[16]), .Y(n251) );
NOR2X2TS U81 ( .A(in2[25]), .B(in2[24]), .Y(n134) );
AND2X2TS U82 ( .A(n95), .B(n94), .Y(n103) );
XNOR2X1TS U83 ( .A(n73), .B(in2[12]), .Y(n60) );
INVX2TS U84 ( .A(add_sub), .Y(n139) );
NAND2BX1TS U85 ( .AN(n49), .B(n48), .Y(n50) );
INVX4TS U86 ( .A(in2[9]), .Y(n303) );
INVX2TS U87 ( .A(in2[8]), .Y(n43) );
NOR2XLTS U88 ( .A(in2[19]), .B(in2[18]), .Y(n94) );
INVX6TS U89 ( .A(in2[7]), .Y(n33) );
CLKMX2X2TS U90 ( .A(n75), .B(in2[15]), .S0(n300), .Y(n76) );
CLKMX2X2TS U91 ( .A(in2[30]), .B(n158), .S0(n17), .Y(n159) );
INVX12TS U92 ( .A(in2[6]), .Y(n307) );
INVX2TS U93 ( .A(n244), .Y(n13) );
NOR2XLTS U94 ( .A(n26), .B(n25), .Y(n246) );
INVX6TS U95 ( .A(n189), .Y(n202) );
OAI21XLTS U96 ( .A0(n301), .A1(n300), .B0(n299), .Y(res[6]) );
NAND2X2TS U97 ( .A(n87), .B(in1[17]), .Y(n248) );
INVX2TS U98 ( .A(add_sub), .Y(n312) );
INVX4TS U99 ( .A(n139), .Y(n17) );
NAND2X2TS U100 ( .A(n34), .B(n173), .Y(n172) );
INVX2TS U101 ( .A(n196), .Y(n144) );
NAND2BX2TS U102 ( .AN(in2[29]), .B(n157), .Y(n168) );
NAND2X2TS U103 ( .A(n111), .B(n110), .Y(n112) );
MX2X2TS U104 ( .A(n60), .B(in2[12]), .S0(n310), .Y(n61) );
BUFX6TS U105 ( .A(n312), .Y(n310) );
BUFX6TS U106 ( .A(n312), .Y(n300) );
NOR2X4TS U107 ( .A(in2[21]), .B(in2[20]), .Y(n110) );
NAND2X2TS U108 ( .A(n35), .B(n177), .Y(n167) );
OR2X4TS U109 ( .A(n159), .B(in1[30]), .Y(n35) );
INVX2TS U110 ( .A(n216), .Y(n218) );
NAND2X4TS U111 ( .A(n119), .B(in1[21]), .Y(n228) );
MXI2X4TS U112 ( .A(n89), .B(n88), .S0(add_sub), .Y(n90) );
XOR2X2TS U113 ( .A(n116), .B(in2[21]), .Y(n117) );
NOR2X4TS U114 ( .A(n115), .B(in2[20]), .Y(n116) );
NOR2X4TS U115 ( .A(n76), .B(in1[15]), .Y(n255) );
NOR2X2TS U116 ( .A(in2[23]), .B(in2[22]), .Y(n102) );
XOR2X1TS U117 ( .A(n213), .B(n212), .Y(res[24]) );
XNOR2X2TS U118 ( .A(n188), .B(n187), .Y(res[28]) );
XOR2X1TS U119 ( .A(n243), .B(n242), .Y(res[19]) );
XOR2X1TS U120 ( .A(n247), .B(n246), .Y(res[18]) );
NAND2X1TS U121 ( .A(n14), .B(n39), .Y(n28) );
AOI21X2TS U122 ( .A0(n35), .A1(n165), .B0(n164), .Y(n166) );
OR2X2TS U123 ( .A(n171), .B(in1[31]), .Y(n34) );
INVX2TS U124 ( .A(n30), .Y(n14) );
NOR2X4TS U125 ( .A(n29), .B(n244), .Y(n24) );
NAND2X2TS U126 ( .A(n171), .B(in1[31]), .Y(n173) );
NAND2X6TS U127 ( .A(n37), .B(n200), .Y(n191) );
NOR2X2TS U128 ( .A(n239), .B(n234), .Y(n101) );
INVX2TS U129 ( .A(n176), .Y(n165) );
NAND2X2TS U130 ( .A(n159), .B(in1[30]), .Y(n163) );
NAND2X6TS U131 ( .A(n39), .B(n38), .Y(n29) );
MX2X2TS U132 ( .A(in2[31]), .B(n170), .S0(n17), .Y(n171) );
NAND2X4TS U133 ( .A(n146), .B(in1[27]), .Y(n192) );
XOR2X1TS U134 ( .A(n269), .B(n268), .Y(res[13]) );
XNOR2X2TS U135 ( .A(n128), .B(in2[26]), .Y(n129) );
INVX2TS U136 ( .A(n259), .Y(n268) );
MXI2X4TS U137 ( .A(n141), .B(n140), .S0(n139), .Y(n146) );
NAND2X2TS U138 ( .A(n99), .B(in1[20]), .Y(n235) );
XOR2X2TS U139 ( .A(n130), .B(in2[25]), .Y(n131) );
INVX4TS U140 ( .A(n154), .Y(n127) );
NOR2X6TS U141 ( .A(n83), .B(in2[16]), .Y(n84) );
NOR2X6TS U142 ( .A(n68), .B(in1[14]), .Y(n260) );
MXI2X4TS U143 ( .A(n66), .B(n71), .S0(n310), .Y(n68) );
OAI21X1TS U144 ( .A0(n313), .A1(n312), .B0(n311), .Y(res[7]) );
OAI21XLTS U145 ( .A0(n290), .A1(n300), .B0(n289), .Y(res[10]) );
OAI21XLTS U146 ( .A0(n306), .A1(n312), .B0(n305), .Y(res[9]) );
OAI21XLTS U147 ( .A0(n283), .A1(n312), .B0(n282), .Y(res[8]) );
OAI21XLTS U148 ( .A0(n297), .A1(n300), .B0(n296), .Y(res[5]) );
OAI21XLTS U149 ( .A0(n293), .A1(n300), .B0(n292), .Y(res[4]) );
OAI21XLTS U150 ( .A0(n287), .A1(n312), .B0(n286), .Y(res[3]) );
OAI21XLTS U151 ( .A0(n281), .A1(n300), .B0(n280), .Y(res[1]) );
OAI21XLTS U152 ( .A0(n279), .A1(n312), .B0(n278), .Y(res[2]) );
OR2X2TS U153 ( .A(n137), .B(in2[27]), .Y(n153) );
NOR2X2TS U154 ( .A(in2[17]), .B(in2[16]), .Y(n95) );
OR2X1TS U155 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X4TS U156 ( .A(n98), .B(in1[19]), .Y(n239) );
NOR2X4TS U157 ( .A(n99), .B(in1[20]), .Y(n234) );
NOR2X2TS U158 ( .A(n265), .B(n260), .Y(n70) );
XOR2X2TS U159 ( .A(n63), .B(in2[13]), .Y(n65) );
OAI21X4TS U160 ( .A0(n209), .A1(n217), .B0(n210), .Y(n123) );
NOR3BX2TS U161 ( .AN(n110), .B(n115), .C(in2[22]), .Y(n107) );
NAND2X4TS U162 ( .A(n121), .B(in1[23]), .Y(n217) );
NAND3X8TS U163 ( .A(n23), .B(n20), .C(n18), .Y(n232) );
NOR2X4TS U164 ( .A(n22), .B(n21), .Y(n20) );
NOR2X4TS U165 ( .A(n53), .B(n52), .Y(n54) );
NOR2X4TS U166 ( .A(n288), .B(in2[10]), .Y(n53) );
OR2X4TS U167 ( .A(n54), .B(in1[11]), .Y(n40) );
NAND2X4TS U168 ( .A(n54), .B(in1[11]), .Y(n275) );
XNOR2X2TS U169 ( .A(n161), .B(n160), .Y(res[30]) );
OAI21X2TS U170 ( .A0(n240), .A1(n234), .B0(n235), .Y(n100) );
NOR2X8TS U171 ( .A(n122), .B(in1[24]), .Y(n209) );
NAND2X4TS U172 ( .A(n122), .B(in1[24]), .Y(n210) );
AOI21X4TS U173 ( .A0(n124), .A1(n214), .B0(n123), .Y(n125) );
NOR2X6TS U174 ( .A(n209), .B(n216), .Y(n124) );
OR2X4TS U175 ( .A(n147), .B(in1[28]), .Y(n36) );
MX2X4TS U176 ( .A(in2[28]), .B(n136), .S0(n17), .Y(n147) );
XNOR2X1TS U177 ( .A(n179), .B(n178), .Y(res[29]) );
XNOR2X2TS U178 ( .A(in2[14]), .B(n77), .Y(n66) );
MXI2X4TS U179 ( .A(n106), .B(n105), .S0(n17), .Y(n122) );
OAI2BB1X4TS U180 ( .A0N(n17), .A1N(n65), .B0(n64), .Y(n67) );
INVX4TS U181 ( .A(n56), .Y(n57) );
MXI2X4TS U182 ( .A(n132), .B(n131), .S0(n17), .Y(n142) );
NOR2X4TS U183 ( .A(n154), .B(in2[24]), .Y(n130) );
CLKINVX12TS U184 ( .A(n59), .Y(n73) );
XNOR2X4TS U185 ( .A(n135), .B(in2[28]), .Y(n136) );
NOR2X4TS U186 ( .A(n154), .B(n153), .Y(n135) );
NOR3X4TS U187 ( .A(n154), .B(in2[28]), .C(n153), .Y(n157) );
NAND4X8TS U188 ( .A(n104), .B(n103), .C(n110), .D(n102), .Y(n154) );
NAND2X2TS U189 ( .A(n124), .B(n215), .Y(n126) );
NAND2X1TS U190 ( .A(n300), .B(in2[11]), .Y(n44) );
NAND2X2TS U191 ( .A(n76), .B(in1[15]), .Y(n256) );
INVX2TS U192 ( .A(n195), .Y(n200) );
OR2X4TS U193 ( .A(n143), .B(in1[26]), .Y(n37) );
OR2X4TS U194 ( .A(n146), .B(in1[27]), .Y(n41) );
NAND2X1TS U195 ( .A(n300), .B(in2[13]), .Y(n64) );
NAND2X1TS U196 ( .A(n73), .B(n62), .Y(n63) );
XOR2X1TS U197 ( .A(n104), .B(in2[16]), .Y(n79) );
MXI2X4TS U198 ( .A(n97), .B(n96), .S0(add_sub), .Y(n99) );
NAND2X4TS U199 ( .A(n19), .B(n13), .Y(n18) );
NAND2X4TS U200 ( .A(n253), .B(n24), .Y(n23) );
XNOR2X1TS U201 ( .A(n157), .B(in2[29]), .Y(n155) );
INVX2TS U202 ( .A(in2[2]), .Y(n284) );
INVX4TS U203 ( .A(n275), .Y(n55) );
NOR2X4TS U204 ( .A(n61), .B(in1[12]), .Y(n270) );
NAND2X2TS U205 ( .A(n61), .B(in1[12]), .Y(n271) );
NAND2X4TS U206 ( .A(n67), .B(in1[13]), .Y(n266) );
NOR2X4TS U207 ( .A(in1[13]), .B(n67), .Y(n265) );
NAND2X2TS U208 ( .A(n68), .B(in1[14]), .Y(n261) );
NOR2X1TS U209 ( .A(n30), .B(n29), .Y(n26) );
NAND2X1TS U210 ( .A(n31), .B(n248), .Y(n25) );
NAND2X2TS U211 ( .A(n142), .B(in1[25]), .Y(n199) );
NOR2X2TS U212 ( .A(n142), .B(in1[25]), .Y(n195) );
INVX2TS U213 ( .A(n162), .Y(n177) );
NOR2X2TS U214 ( .A(n156), .B(in1[29]), .Y(n162) );
NAND2X2TS U215 ( .A(n156), .B(in1[29]), .Y(n176) );
OAI21X2TS U216 ( .A0(n182), .A1(n150), .B0(n149), .Y(n151) );
NAND2X1TS U217 ( .A(in2[10]), .B(add_sub), .Y(n47) );
NAND2BX1TS U218 ( .AN(n47), .B(n56), .Y(n46) );
INVX2TS U219 ( .A(in2[10]), .Y(n58) );
NAND2X2TS U220 ( .A(n104), .B(n95), .Y(n91) );
INVX2TS U221 ( .A(n31), .Y(n19) );
NOR2X2TS U222 ( .A(n248), .B(n244), .Y(n22) );
INVX2TS U223 ( .A(n245), .Y(n21) );
INVX2TS U224 ( .A(n115), .Y(n111) );
NAND2X4TS U225 ( .A(n104), .B(n103), .Y(n115) );
XOR2X1TS U226 ( .A(n127), .B(in2[24]), .Y(n105) );
INVX2TS U227 ( .A(n192), .Y(n183) );
AOI21X1TS U228 ( .A0(n36), .A1(n183), .B0(n148), .Y(n149) );
INVX2TS U229 ( .A(n186), .Y(n148) );
INVX2TS U230 ( .A(n163), .Y(n164) );
NAND2X1TS U231 ( .A(n285), .B(n284), .Y(n291) );
INVX2TS U232 ( .A(in2[4]), .Y(n294) );
NAND2X2TS U233 ( .A(n49), .B(n57), .Y(n288) );
NAND2X2TS U234 ( .A(n98), .B(in1[19]), .Y(n240) );
INVX2TS U235 ( .A(n233), .Y(n243) );
CLKBUFX2TS U236 ( .A(n232), .Y(n233) );
INVX2TS U237 ( .A(n221), .Y(n229) );
INVX2TS U238 ( .A(n228), .Y(n222) );
NOR2X4TS U239 ( .A(n223), .B(n221), .Y(n215) );
OAI21X1TS U240 ( .A0(n206), .A1(n216), .B0(n217), .Y(n207) );
NOR2X1TS U241 ( .A(n205), .B(n216), .Y(n208) );
INVX2TS U242 ( .A(n215), .Y(n205) );
CLKBUFX2TS U243 ( .A(n203), .Y(n204) );
NAND2X2TS U244 ( .A(n147), .B(in1[28]), .Y(n186) );
INVX2TS U245 ( .A(n191), .Y(n181) );
AOI21X2TS U246 ( .A0(n184), .A1(n41), .B0(n183), .Y(n185) );
INVX2TS U247 ( .A(n190), .Y(n184) );
NOR2XLTS U248 ( .A(n302), .B(in2[8]), .Y(n304) );
NAND2X1TS U249 ( .A(n40), .B(n275), .Y(n276) );
NAND2X1TS U250 ( .A(n272), .B(n271), .Y(n274) );
INVX2TS U251 ( .A(n270), .Y(n272) );
NAND2X1TS U252 ( .A(n267), .B(n266), .Y(n269) );
INVX2TS U253 ( .A(n265), .Y(n267) );
NAND2X1TS U254 ( .A(n262), .B(n261), .Y(n263) );
INVX2TS U255 ( .A(n260), .Y(n262) );
NAND2X1TS U256 ( .A(n257), .B(n256), .Y(n258) );
INVX2TS U257 ( .A(n255), .Y(n257) );
NAND2X1TS U258 ( .A(n39), .B(n251), .Y(n252) );
NAND2X1TS U259 ( .A(n38), .B(n248), .Y(n249) );
NAND2X1TS U260 ( .A(n28), .B(n27), .Y(n250) );
INVX2TS U261 ( .A(n82), .Y(n27) );
NAND2X1TS U262 ( .A(n13), .B(n245), .Y(n247) );
NAND2X1TS U263 ( .A(n241), .B(n240), .Y(n242) );
INVX2TS U264 ( .A(n239), .Y(n241) );
XNOR2X1TS U265 ( .A(n238), .B(n237), .Y(res[20]) );
NAND2X1TS U266 ( .A(n236), .B(n235), .Y(n237) );
OAI21X1TS U267 ( .A0(n243), .A1(n239), .B0(n240), .Y(n238) );
INVX2TS U268 ( .A(n234), .Y(n236) );
XNOR2X1TS U269 ( .A(n231), .B(n230), .Y(res[21]) );
NAND2X1TS U270 ( .A(n229), .B(n228), .Y(n230) );
XOR2X1TS U271 ( .A(n202), .B(n201), .Y(res[25]) );
NAND2X1TS U272 ( .A(n200), .B(n199), .Y(n201) );
NAND2X1TS U273 ( .A(n41), .B(n192), .Y(n193) );
XNOR2X2TS U274 ( .A(n174), .B(n172), .Y(res[31]) );
AND2X2TS U275 ( .A(n181), .B(n41), .Y(n15) );
INVX2TS U276 ( .A(n302), .Y(n49) );
NAND2X2TS U277 ( .A(n43), .B(n303), .Y(n56) );
AND2X8TS U278 ( .A(n33), .B(n307), .Y(n16) );
XNOR2X1TS U279 ( .A(n264), .B(n263), .Y(res[14]) );
BUFX20TS U280 ( .A(n78), .Y(n104) );
MXI2X8TS U281 ( .A(n114), .B(n113), .S0(n17), .Y(n120) );
NOR2X2TS U282 ( .A(n154), .B(n137), .Y(n138) );
NOR2X8TS U283 ( .A(in2[0]), .B(in2[1]), .Y(n285) );
XNOR2X4TS U284 ( .A(n91), .B(in2[18]), .Y(n88) );
XNOR2X4TS U285 ( .A(n107), .B(n108), .Y(n109) );
XOR2X4TS U286 ( .A(n53), .B(in2[11]), .Y(n45) );
NAND2X8TS U287 ( .A(n42), .B(n32), .Y(n302) );
AND2X8TS U288 ( .A(n16), .B(n285), .Y(n32) );
XOR2X1TS U289 ( .A(n227), .B(n226), .Y(res[22]) );
XOR2X1TS U290 ( .A(n220), .B(n219), .Y(res[23]) );
XNOR2X1TS U291 ( .A(n250), .B(n249), .Y(res[17]) );
OAI21XLTS U292 ( .A0(n268), .A1(n265), .B0(n266), .Y(n264) );
XOR2X4TS U293 ( .A(n84), .B(in2[17]), .Y(n85) );
NOR4X8TS U294 ( .A(in2[5]), .B(in2[4]), .C(in2[3]), .D(in2[2]), .Y(n42) );
XOR2XLTS U295 ( .A(n274), .B(n273), .Y(res[12]) );
XNOR2X4TS U296 ( .A(n112), .B(in2[22]), .Y(n113) );
XNOR2X4TS U297 ( .A(n92), .B(in2[19]), .Y(n93) );
NOR2X4TS U298 ( .A(n91), .B(in2[18]), .Y(n92) );
XNOR2X1TS U299 ( .A(n277), .B(n276), .Y(res[11]) );
XNOR2X1TS U300 ( .A(n14), .B(n252), .Y(res[16]) );
XNOR2X4TS U301 ( .A(n138), .B(n140), .Y(n141) );
NAND2X2TS U302 ( .A(n127), .B(n134), .Y(n128) );
OAI21X4TS U303 ( .A0(n45), .A1(n300), .B0(n44), .Y(n277) );
OAI211X2TS U304 ( .A0(in2[10]), .A1(add_sub), .B0(n46), .C0(in1[10]), .Y(n51) );
INVX2TS U305 ( .A(n47), .Y(n48) );
NAND2BX4TS U306 ( .AN(n51), .B(n50), .Y(n52) );
AOI21X4TS U307 ( .A0(n277), .A1(n40), .B0(n55), .Y(n273) );
NAND4BBX4TS U308 ( .AN(n302), .BN(in2[11]), .C(n58), .D(n57), .Y(n59) );
OAI21X4TS U309 ( .A0(n273), .A1(n270), .B0(n271), .Y(n259) );
INVX2TS U310 ( .A(in2[12]), .Y(n62) );
NOR2X2TS U311 ( .A(in2[13]), .B(in2[12]), .Y(n72) );
NAND2X8TS U312 ( .A(n73), .B(n72), .Y(n77) );
INVX2TS U313 ( .A(in2[14]), .Y(n71) );
OAI21X4TS U314 ( .A0(n260), .A1(n266), .B0(n261), .Y(n69) );
AOI21X4TS U315 ( .A0(n259), .A1(n70), .B0(n69), .Y(n254) );
NAND3X1TS U316 ( .A(n73), .B(n72), .C(n71), .Y(n74) );
XOR2X1TS U317 ( .A(n74), .B(in2[15]), .Y(n75) );
OAI21X4TS U318 ( .A0(n254), .A1(n255), .B0(n256), .Y(n253) );
INVX2TS U319 ( .A(in2[16]), .Y(n80) );
NOR3X8TS U320 ( .A(n77), .B(in2[15]), .C(in2[14]), .Y(n78) );
MXI2X4TS U321 ( .A(n80), .B(n79), .S0(add_sub), .Y(n81) );
INVX2TS U322 ( .A(in2[17]), .Y(n86) );
INVX3TS U323 ( .A(n104), .Y(n83) );
MXI2X4TS U324 ( .A(n86), .B(n85), .S0(add_sub), .Y(n87) );
INVX2TS U325 ( .A(in2[18]), .Y(n89) );
MX2X4TS U326 ( .A(in2[19]), .B(n93), .S0(add_sub), .Y(n98) );
INVX2TS U327 ( .A(in2[20]), .Y(n97) );
AOI21X4TS U328 ( .A0(n232), .A1(n101), .B0(n100), .Y(n203) );
INVX2TS U329 ( .A(in2[24]), .Y(n106) );
INVX2TS U330 ( .A(in2[23]), .Y(n108) );
INVX2TS U331 ( .A(in2[22]), .Y(n114) );
INVX2TS U332 ( .A(in2[21]), .Y(n118) );
MXI2X4TS U333 ( .A(n118), .B(n117), .S0(add_sub), .Y(n119) );
OAI21X4TS U334 ( .A0(n223), .A1(n228), .B0(n224), .Y(n214) );
OAI21X4TS U335 ( .A0(n203), .A1(n126), .B0(n125), .Y(n180) );
INVX2TS U336 ( .A(in2[26]), .Y(n133) );
MXI2X4TS U337 ( .A(n133), .B(n129), .S0(n17), .Y(n143) );
INVX2TS U338 ( .A(in2[25]), .Y(n132) );
INVX2TS U339 ( .A(in2[27]), .Y(n140) );
AOI21X4TS U340 ( .A0(n37), .A1(n145), .B0(n144), .Y(n182) );
AOI21X4TS U341 ( .A0(n180), .A1(n152), .B0(n151), .Y(n175) );
OAI21X2TS U342 ( .A0(n175), .A1(n162), .B0(n176), .Y(n161) );
XOR2X1TS U343 ( .A(n168), .B(in2[30]), .Y(n158) );
OAI21X4TS U344 ( .A0(n167), .A1(n175), .B0(n166), .Y(n174) );
OAI2BB1X4TS U345 ( .A0N(n174), .A1N(n34), .B0(n173), .Y(res[32]) );
INVX2TS U346 ( .A(n175), .Y(n179) );
BUFX4TS U347 ( .A(n180), .Y(n189) );
BUFX4TS U348 ( .A(n182), .Y(n190) );
OAI2BB1X4TS U349 ( .A0N(n189), .A1N(n15), .B0(n185), .Y(n188) );
OAI21X4TS U350 ( .A0(n202), .A1(n191), .B0(n190), .Y(n194) );
XNOR2X2TS U351 ( .A(n194), .B(n193), .Y(res[27]) );
OAI21X4TS U352 ( .A0(n202), .A1(n195), .B0(n199), .Y(n198) );
XNOR2X2TS U353 ( .A(n198), .B(n197), .Y(res[26]) );
INVX2TS U354 ( .A(n214), .Y(n206) );
AOI21X4TS U355 ( .A0(n231), .A1(n208), .B0(n207), .Y(n213) );
AOI21X4TS U356 ( .A0(n231), .A1(n215), .B0(n214), .Y(n220) );
AOI21X4TS U357 ( .A0(n231), .A1(n229), .B0(n222), .Y(n227) );
XOR2XLTS U358 ( .A(n254), .B(n258), .Y(res[15]) );
XNOR2X1TS U359 ( .A(n285), .B(n284), .Y(n279) );
AOI21X1TS U360 ( .A0(n312), .A1(in2[2]), .B0(in1[2]), .Y(n278) );
XNOR2X1TS U361 ( .A(in2[0]), .B(in2[1]), .Y(n281) );
AOI21X1TS U362 ( .A0(n310), .A1(in2[1]), .B0(in1[1]), .Y(n280) );
XNOR2X1TS U363 ( .A(n302), .B(in2[8]), .Y(n283) );
AOI21X1TS U364 ( .A0(n310), .A1(in2[8]), .B0(in1[8]), .Y(n282) );
XNOR2X1TS U365 ( .A(n291), .B(in2[3]), .Y(n287) );
AOI21X1TS U366 ( .A0(n312), .A1(in2[3]), .B0(in1[3]), .Y(n286) );
XNOR2X1TS U367 ( .A(n288), .B(in2[10]), .Y(n290) );
AOI21X1TS U368 ( .A0(n310), .A1(in2[10]), .B0(in1[10]), .Y(n289) );
NOR2X1TS U369 ( .A(n291), .B(in2[3]), .Y(n295) );
XNOR2X1TS U370 ( .A(n295), .B(n294), .Y(n293) );
AOI21X1TS U371 ( .A0(n310), .A1(in2[4]), .B0(in1[4]), .Y(n292) );
XNOR2X1TS U372 ( .A(n298), .B(in2[5]), .Y(n297) );
AOI21X1TS U373 ( .A0(n310), .A1(in2[5]), .B0(in1[5]), .Y(n296) );
XNOR2X1TS U374 ( .A(n308), .B(n307), .Y(n301) );
AOI21X1TS U375 ( .A0(n310), .A1(in2[6]), .B0(in1[6]), .Y(n299) );
XNOR2X1TS U376 ( .A(n304), .B(n303), .Y(n306) );
AOI21X1TS U377 ( .A0(n310), .A1(in2[9]), .B0(in1[9]), .Y(n305) );
NAND2X1TS U378 ( .A(n308), .B(n307), .Y(n309) );
XNOR2X1TS U379 ( .A(n309), .B(in2[7]), .Y(n313) );
AOI21X1TS U380 ( .A0(n310), .A1(in2[7]), .B0(in1[7]), .Y(n311) );
initial $sdf_annotate("Approx_adder_LOALPL11_syn.sdf");
endmodule |
module sky130_fd_sc_lp__dlybuf4s25kapwr_1 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlybuf4s25kapwr base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__dlybuf4s25kapwr_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlybuf4s25kapwr base (
.X(X),
.A(A)
);
endmodule |
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule |
module PA (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module sdram_0_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 15: 0] q;
input [ 15: 0] data;
input [ 21: 0] rdaddress;
input rdclken;
input [ 21: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array [4194303: 0];
wire [ 15: 0] q;
reg [ 21: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("sdram_0.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 22,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule |
module sdram_0_test_component (
// inputs:
clk,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dqm,
zs_ras_n,
zs_we_n,
// outputs:
zs_dq
)
;
inout [ 15: 0] zs_dq;
input clk;
input [ 11: 0] zs_addr;
input [ 1: 0] zs_ba;
input zs_cas_n;
input zs_cke;
input zs_cs_n;
input [ 1: 0] zs_dqm;
input zs_ras_n;
input zs_we_n;
wire [ 23: 0] CODE;
wire [ 11: 0] a;
wire [ 7: 0] addr_col;
reg [ 13: 0] addr_crb;
wire [ 1: 0] ba;
wire cas_n;
wire cke;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 1: 0] dqm;
wire [ 2: 0] index;
reg [ 2: 0] latency;
wire [ 1: 0] mask;
wire [ 15: 0] mem_bytes;
wire ras_n;
reg [ 21: 0] rd_addr_pipe_0;
reg [ 21: 0] rd_addr_pipe_1;
reg [ 21: 0] rd_addr_pipe_2;
reg [ 1: 0] rd_mask_pipe_0;
reg [ 1: 0] rd_mask_pipe_1;
reg [ 1: 0] rd_mask_pipe_2;
reg [ 2: 0] rd_valid_pipe;
wire [ 21: 0] read_addr;
wire [ 15: 0] read_data;
wire [ 1: 0] read_mask;
wire [ 15: 0] read_temp;
wire read_valid;
wire [ 15: 0] rmw_temp;
wire [ 21: 0] test_addr;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 15: 0] zs_dq;
initial
begin
$write("\n");
$write("************************************************************\n");
$write("This testbench includes an SOPC Builder Generated Altera model:\n");
$write("'sdram_0_test_component.v', to simulate accesses to SDRAM.\n");
$write("Initial contents are loaded from the file: 'sdram_0.dat'.\n");
$write("************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
sdram_0_test_component_ram_module sdram_0_test_component_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress ((CODE == 24'h205752) ? test_addr : read_addr),
.rdclken (1'b1),
.wraddress (test_addr),
.wrclock (clk),
.wren (CODE == 24'h205752)
);
assign cke = zs_cke;
assign cs_n = zs_cs_n;
assign ras_n = zs_ras_n;
assign cas_n = zs_cas_n;
assign we_n = zs_we_n;
assign dqm = zs_dqm;
assign ba = zs_ba;
assign a = zs_addr;
assign cmd_code = {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[7 : 0];
assign test_addr = {addr_crb, addr_col};
assign mem_bytes = read_data;
assign rmw_temp[7 : 0] = dqm[0] ? mem_bytes[7 : 0] : zs_dq[7 : 0];
assign rmw_temp[15 : 8] = dqm[1] ? mem_bytes[15 : 8] : zs_dq[15 : 8];
// Handle Input.
always @(posedge clk)
begin
// No Activity of Clock Disabled
if (cke)
begin
// LMR: Get CAS_Latency.
if (CODE == 24'h4c4d52)
latency <= a[6 : 4];
// ACT: Get Row/Bank Address.
if (CODE == 24'h414354)
addr_crb <= {ba[1], a, ba[0]};
rd_valid_pipe[2] <= rd_valid_pipe[1];
rd_valid_pipe[1] <= rd_valid_pipe[0];
rd_valid_pipe[0] <= CODE == 24'h205244;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_addr_pipe_0 <= test_addr;
rd_mask_pipe_2 <= rd_mask_pipe_1;
rd_mask_pipe_1 <= rd_mask_pipe_0;
rd_mask_pipe_0 <= dqm;
end
end
assign read_temp[7 : 0] = mask[0] ? 8'bz : read_data[7 : 0];
assign read_temp[15 : 8] = mask[1] ? 8'bz : read_data[15 : 8];
//use index to select which pipeline stage drives addr
assign read_addr = (index == 0)? rd_addr_pipe_0 :
(index == 1)? rd_addr_pipe_1 :
rd_addr_pipe_2;
//use index to select which pipeline stage drives mask
assign read_mask = (index == 0)? rd_mask_pipe_0 :
(index == 1)? rd_mask_pipe_1 :
rd_mask_pipe_2;
//use index to select which pipeline stage drives valid
assign read_valid = (index == 0)? rd_valid_pipe[0] :
(index == 1)? rd_valid_pipe[1] :
rd_valid_pipe[2];
assign index = latency - 1'b1;
assign mask = read_mask;
assign zs_dq = read_valid ? read_temp : {16{1'bz}};
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module system_clock_splitter_1_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_1_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodule |
module system_clock_splitter_1_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edge),
.I2(clk_out),
.O(clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_reg
(.C(clk_in),
.CE(1'b1),
.D(clk_i_1_n_0),
.Q(clk_out),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_edge_reg
(.C(clk_in),
.CE(1'b1),
.D(latch_edge),
.Q(last_edge),
.R(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module Byte_to_rgb(color, r, g, b);
input [7:0] color;
output reg[2:0] r, g, b;
always @(color) begin
case(color)
8'b00000000: {r, g, b} = 9'b101000000;
8'b00000001: {r, g, b} = 9'b100011000;
8'b00000010: {r, g, b} = 9'b110000000;
8'b00000011: {r, g, b} = 9'b010110000;
8'b00000100: {r, g, b} = 9'b010010000;
8'b00000101: {r, g, b} = 9'b001101000;
8'b00000110: {r, g, b} = 9'b111000000;
8'b00000111: {r, g, b} = 9'b101100000;
8'b00001000: {r, g, b} = 9'b011101000;
8'b00001001: {r, g, b} = 9'b110101000;
8'b00001010: {r, g, b} = 9'b100110000;
8'b00001011: {r, g, b} = 9'b010000000;
8'b00001100: {r, g, b} = 9'b001100000;
8'b00001101: {r, g, b} = 9'b110011000;
8'b00001110: {r, g, b} = 9'b111110000;
8'b00001111: {r, g, b} = 9'b000010000;
8'b00010000: {r, g, b} = 9'b101111000;
8'b00010001: {r, g, b} = 9'b001000000;
8'b00010010: {r, g, b} = 9'b101010000;
8'b00010011: {r, g, b} = 9'b011100000;
8'b00010100: {r, g, b} = 9'b111011000;
8'b00010101: {r, g, b} = 9'b100000000;
8'b00010110: {r, g, b} = 9'b010111000;
8'b00010111: {r, g, b} = 9'b001001000;
8'b00011000: {r, g, b} = 9'b001010000;
8'b00011001: {r, g, b} = 9'b000100000;
8'b00011010: {r, g, b} = 9'b010001000;
8'b00011011: {r, g, b} = 9'b100010000;
8'b00011100: {r, g, b} = 9'b000001000;
8'b00011101: {r, g, b} = 9'b011111010;
8'b00011110: {r, g, b} = 9'b100111100;
8'b00011111: {r, g, b} = 9'b100111101;
8'b00100000: {r, g, b} = 9'b100111111;
8'b00100001: {r, g, b} = 9'b011110001;
8'b00100010: {r, g, b} = 9'b100101001;
8'b00100011: {r, g, b} = 9'b101110001;
8'b00100100: {r, g, b} = 9'b011100001;
8'b00100101: {r, g, b} = 9'b100110011;
8'b00100110: {r, g, b} = 9'b011110011;
8'b00100111: {r, g, b} = 9'b010101001;
8'b00101000: {r, g, b} = 9'b100011001;
8'b00101001: {r, g, b} = 9'b100101010;
8'b00101010: {r, g, b} = 9'b011101010;
8'b00101011: {r, g, b} = 9'b010111010;
8'b00101100: {r, g, b} = 9'b101100001;
8'b00101101: {r, g, b} = 9'b010100001;
8'b00101110: {r, g, b} = 9'b101011001;
8'b00101111: {r, g, b} = 9'b100010001;
8'b00110000: {r, g, b} = 9'b100110101;
8'b00110001: {r, g, b} = 9'b011110101;
8'b00110010: {r, g, b} = 9'b010010001;
8'b00110011: {r, g, b} = 9'b100001001;
8'b00110100: {r, g, b} = 9'b011100010;
8'b00110101: {r, g, b} = 9'b100110110;
8'b00110110: {r, g, b} = 9'b011110110;
8'b00110111: {r, g, b} = 9'b101001001;
8'b00111000: {r, g, b} = 9'b010001001;
8'b00111001: {r, g, b} = 9'b000111001;
8'b00111010: {r, g, b} = 9'b000110001;
8'b00111011: {r, g, b} = 9'b000101001;
8'b00111100: {r, g, b} = 9'b110101001;
8'b00111101: {r, g, b} = 9'b110011001;
8'b00111110: {r, g, b} = 9'b000010001;
8'b00111111: {r, g, b} = 9'b000001001;
8'b01000000: {r, g, b} = 9'b110001001;
8'b01000001: {r, g, b} = 9'b001100001;
8'b01000010: {r, g, b} = 9'b001010001;
8'b01000011: {r, g, b} = 9'b001001001;
8'b01000100: {r, g, b} = 9'b001000001;
8'b01000101: {r, g, b} = 9'b000000001;
8'b01000110: {r, g, b} = 9'b010000001;
8'b01000111: {r, g, b} = 9'b100110111;
8'b01001000: {r, g, b} = 9'b100011010;
8'b01001001: {r, g, b} = 9'b100101100;
8'b01001010: {r, g, b} = 9'b101110011;
8'b01001011: {r, g, b} = 9'b101100010;
8'b01001100: {r, g, b} = 9'b010100010;
8'b01001101: {r, g, b} = 9'b011100011;
8'b01001110: {r, g, b} = 9'b101011010;
8'b01001111: {r, g, b} = 9'b100010010;
8'b01010000: {r, g, b} = 9'b100101101;
8'b01010001: {r, g, b} = 9'b010111101;
8'b01010010: {r, g, b} = 9'b010101011;
8'b01010011: {r, g, b} = 9'b101110100;
8'b01010100: {r, g, b} = 9'b101010010;
8'b01010101: {r, g, b} = 9'b010010010;
8'b01010110: {r, g, b} = 9'b101111110;
8'b01010111: {r, g, b} = 9'b100011011;
8'b01011000: {r, g, b} = 9'b100101110;
8'b01011001: {r, g, b} = 9'b011101110;
8'b01011010: {r, g, b} = 9'b100001010;
8'b01011011: {r, g, b} = 9'b011100100;
8'b01011100: {r, g, b} = 9'b010100011;
8'b01011101: {r, g, b} = 9'b010001010;
8'b01011110: {r, g, b} = 9'b010101100;
8'b01011111: {r, g, b} = 9'b101111111;
8'b01100000: {r, g, b} = 9'b110111010;
8'b01100001: {r, g, b} = 9'b111110010;
8'b01100010: {r, g, b} = 9'b000100010;
8'b01100011: {r, g, b} = 9'b111100010;
8'b01100100: {r, g, b} = 9'b000010010;
8'b01100101: {r, g, b} = 9'b111010010;
8'b01100110: {r, g, b} = 9'b000001010;
8'b01100111: {r, g, b} = 9'b001110010;
8'b01101000: {r, g, b} = 9'b001101010;
8'b01101001: {r, g, b} = 9'b001100010;
8'b01101010: {r, g, b} = 9'b001010010;
8'b01101011: {r, g, b} = 9'b001001010;
8'b01101100: {r, g, b} = 9'b101000010;
8'b01101101: {r, g, b} = 9'b100000010;
8'b01101110: {r, g, b} = 9'b001000010;
8'b01101111: {r, g, b} = 9'b010000010;
8'b01110000: {r, g, b} = 9'b000000010;
8'b01110001: {r, g, b} = 9'b010111111;
8'b01110010: {r, g, b} = 9'b100010011;
8'b01110011: {r, g, b} = 9'b100100101;
8'b01110100: {r, g, b} = 9'b011011100;
8'b01110101: {r, g, b} = 9'b101100100;
8'b01110110: {r, g, b} = 9'b010100100;
8'b01110111: {r, g, b} = 9'b101010011;
8'b01111000: {r, g, b} = 9'b010101101;
8'b01111001: {r, g, b} = 9'b100001011;
8'b01111010: {r, g, b} = 9'b101001011;
8'b01111011: {r, g, b} = 9'b101110111;
8'b01111100: {r, g, b} = 9'b010011100;
8'b01111101: {r, g, b} = 9'b011010100;
8'b01111110: {r, g, b} = 9'b010100101;
8'b01111111: {r, g, b} = 9'b000110011;
8'b10000000: {r, g, b} = 9'b000101011;
8'b10000001: {r, g, b} = 9'b110101011;
8'b10000010: {r, g, b} = 9'b110100011;
8'b10000011: {r, g, b} = 9'b110011011;
8'b10000100: {r, g, b} = 9'b110001011;
8'b10000101: {r, g, b} = 9'b001101011;
8'b10000110: {r, g, b} = 9'b110000011;
8'b10000111: {r, g, b} = 9'b111000011;
8'b10001000: {r, g, b} = 9'b100000011;
8'b10001001: {r, g, b} = 9'b100100111;
8'b10001010: {r, g, b} = 9'b101010100;
8'b10001011: {r, g, b} = 9'b010010100;
8'b10001100: {r, g, b} = 9'b101101111;
8'b10001101: {r, g, b} = 9'b100011110;
8'b10001110: {r, g, b} = 9'b011011110;
8'b10001111: {r, g, b} = 9'b011001100;
8'b10010000: {r, g, b} = 9'b010101111;
8'b10010001: {r, g, b} = 9'b010011101;
8'b10010010: {r, g, b} = 9'b101100110;
8'b10010011: {r, g, b} = 9'b100010101;
8'b10010100: {r, g, b} = 9'b011010101;
8'b10010101: {r, g, b} = 9'b101001100;
8'b10010110: {r, g, b} = 9'b010001100;
8'b10010111: {r, g, b} = 9'b000111100;
8'b10011000: {r, g, b} = 9'b110111100;
8'b10011001: {r, g, b} = 9'b111110100;
8'b10011010: {r, g, b} = 9'b110110100;
8'b10011011: {r, g, b} = 9'b111101100;
8'b10011100: {r, g, b} = 9'b110101100;
8'b10011101: {r, g, b} = 9'b111100100;
8'b10011110: {r, g, b} = 9'b000100100;
8'b10011111: {r, g, b} = 9'b110100100;
8'b10100000: {r, g, b} = 9'b110011100;
8'b10100001: {r, g, b} = 9'b111010100;
8'b10100010: {r, g, b} = 9'b000010100;
8'b10100011: {r, g, b} = 9'b001110100;
8'b10100100: {r, g, b} = 9'b001100100;
8'b10100101: {r, g, b} = 9'b001010100;
8'b10100110: {r, g, b} = 9'b001001100;
8'b10100111: {r, g, b} = 9'b011000100;
8'b10101000: {r, g, b} = 9'b000000100;
8'b10101001: {r, g, b} = 9'b101000100;
8'b10101010: {r, g, b} = 9'b001000100;
8'b10101011: {r, g, b} = 9'b101011110;
8'b10101100: {r, g, b} = 9'b100001101;
8'b10101101: {r, g, b} = 9'b010001101;
8'b10101110: {r, g, b} = 9'b111111101;
8'b10101111: {r, g, b} = 9'b110111101;
8'b10110000: {r, g, b} = 9'b111110101;
8'b10110001: {r, g, b} = 9'b000101101;
8'b10110010: {r, g, b} = 9'b111101101;
8'b10110011: {r, g, b} = 9'b111100101;
8'b10110100: {r, g, b} = 9'b110100101;
8'b10110101: {r, g, b} = 9'b000011101;
8'b10110110: {r, g, b} = 9'b110011101;
8'b10110111: {r, g, b} = 9'b000001101;
8'b10111000: {r, g, b} = 9'b110001101;
8'b10111001: {r, g, b} = 9'b001101101;
8'b10111010: {r, g, b} = 9'b001011101;
8'b10111011: {r, g, b} = 9'b001010101;
8'b10111100: {r, g, b} = 9'b011000101;
8'b10111101: {r, g, b} = 9'b110000101;
8'b10111110: {r, g, b} = 9'b001000101;
8'b10111111: {r, g, b} = 9'b011010111;
8'b11000000: {r, g, b} = 9'b011001110;
8'b11000001: {r, g, b} = 9'b101001110;
8'b11000010: {r, g, b} = 9'b010010111;
8'b11000011: {r, g, b} = 9'b000110110;
8'b11000100: {r, g, b} = 9'b111101110;
8'b11000101: {r, g, b} = 9'b110100110;
8'b11000110: {r, g, b} = 9'b000011110;
8'b11000111: {r, g, b} = 9'b111010110;
8'b11001000: {r, g, b} = 9'b000001110;
8'b11001001: {r, g, b} = 9'b001110110;
8'b11001010: {r, g, b} = 9'b001100110;
8'b11001011: {r, g, b} = 9'b001010110;
8'b11001100: {r, g, b} = 9'b100000110;
8'b11001101: {r, g, b} = 9'b111000110;
8'b11001110: {r, g, b} = 9'b010000110;
8'b11001111: {r, g, b} = 9'b000111111;
8'b11010000: {r, g, b} = 9'b111101111;
8'b11010001: {r, g, b} = 9'b110101111;
8'b11010010: {r, g, b} = 9'b000100111;
8'b11010011: {r, g, b} = 9'b111100111;
8'b11010100: {r, g, b} = 9'b110100111;
8'b11010101: {r, g, b} = 9'b110010111;
8'b11010110: {r, g, b} = 9'b000001111;
8'b11010111: {r, g, b} = 9'b101000111;
8'b11011000: {r, g, b} = 9'b010000111;
8'b11011001: {r, g, b} = 9'b000000000;
8'b11011010: {r, g, b} = 9'b000000000;
8'b11011011: {r, g, b} = 9'b000000000;
8'b11011100: {r, g, b} = 9'b000000000;
8'b11011101: {r, g, b} = 9'b000000000;
8'b11011110: {r, g, b} = 9'b000000000;
8'b11011111: {r, g, b} = 9'b000000000;
8'b11100000: {r, g, b} = 9'b000000000;
8'b11100001: {r, g, b} = 9'b000000000;
8'b11100010: {r, g, b} = 9'b000000000;
8'b11100011: {r, g, b} = 9'b000000000;
8'b11100100: {r, g, b} = 9'b000000000;
8'b11100101: {r, g, b} = 9'b000000000;
8'b11100110: {r, g, b} = 9'b000000000;
8'b11100111: {r, g, b} = 9'b000000000;
8'b11101000: {r, g, b} = 9'b000000000;
8'b11101001: {r, g, b} = 9'b000000000;
8'b11101010: {r, g, b} = 9'b000000000;
8'b11101011: {r, g, b} = 9'b000000000;
8'b11101100: {r, g, b} = 9'b000000000;
8'b11101101: {r, g, b} = 9'b000000000;
8'b11101110: {r, g, b} = 9'b000000000;
8'b11101111: {r, g, b} = 9'b000000000;
8'b11110000: {r, g, b} = 9'b000000000;
8'b11110001: {r, g, b} = 9'b000000000;
8'b11110010: {r, g, b} = 9'b000000000;
8'b11110011: {r, g, b} = 9'b000000000;
8'b11110100: {r, g, b} = 9'b000000000;
8'b11110101: {r, g, b} = 9'b000000000;
8'b11110110: {r, g, b} = 9'b000000000;
8'b11110111: {r, g, b} = 9'b000000000;
8'b11111000: {r, g, b} = 9'b000000000;
8'b11111001: {r, g, b} = 9'b001001001;
8'b11111010: {r, g, b} = 9'b010010010;
8'b11111011: {r, g, b} = 9'b011011011;
8'b11111100: {r, g, b} = 9'b100100100;
8'b11111101: {r, g, b} = 9'b101101101;
8'b11111110: {r, g, b} = 9'b110110110;
8'b11111111: {r, g, b} = 9'b111111111;
endcase
end
endmodule |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule |
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
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