module_content
stringlengths 18
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module system_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule |
module sky130_fd_sc_ms__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module TB_CT;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
reg down;
reg chip_select;
// Outputs
wire signal_out;
wire [3:0] ciclo_actual;
// Instantiate the Unit Under Test (UUT)
Modificacion_Ciclo_Trabajo uut (
.clk_100MHz(clk_100MHz),
.clk_de_trabajo(clk_de_trabajo),
.rst(rst),
.up(up),
.down(down),
.chip_select(chip_select),
.signal_out(signal_out),
.ciclo_actual(ciclo_actual)
);
initial begin
forever #5 clk_100MHz = ~clk_100MHz;
end
initial begin
forever #10 clk_de_trabajo = ~clk_de_trabajo;
end
initial begin
// Initialize Inputs
clk_100MHz = 0;
clk_de_trabajo = 0;
rst = 1;
up = 0;
down = 0;
chip_select = 1;
// Wait 100 ns for global reset to finish
#10;
rst = 0;
/*
#10
up = 1;
#50
up = 0;
*/
// Add stimulus here
end
endmodule |
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_lp__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
parameter Tp = 1;
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
output sync_out;
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg sync_out;
wire z;
assign z = set2 | set2_q & ~clear2_q2;
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q <=#Tp 1'b0;
else
set2_q <=#Tp z;
end
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q2 <=#Tp 1'b0;
else
set2_q2 <=#Tp set2_q;
end
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q <=#Tp 1'b0;
else
set1_q <=#Tp set2_q2;
end
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q2 <=#Tp 1'b0;
else
set1_q2 <=#Tp set1_q;
end
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q <=#Tp 1'b0;
else
clear2_q <=#Tp set1_q2;
end
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q2 <=#Tp 1'b0;
else
clear2_q2 <=#Tp clear2_q;
end
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
sync_out <=#Tp 1'b0;
else
sync_out <=#Tp set1_q2;
end
endmodule |
module BIOS_ROM
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [7:0]douta;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [7:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.535699 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "BIOS_ROM.mem" *)
(* C_INIT_FILE_NAME = "BIOS_ROM.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "4096" *)
(* C_READ_DEPTH_B = "4096" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "4096" *)
(* C_WRITE_DEPTH_B = "4096" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
BIOS_ROM_blk_mem_gen_v8_2 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[7:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[7:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule |
module BIOS_ROM_blk_mem_gen_generic_cstr
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule |
module BIOS_ROM_blk_mem_gen_prim_width
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule |
module BIOS_ROM_blk_mem_gen_prim_wrapper_init
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00F46C48),
.INIT_01(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_02(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_11(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_13(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_15(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_16(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_18(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_20(256'hFFFD2DFFFCADF410CA88EAD0FD80D9FE00BD7FA2FFA0018516A926C24C26C24C),
.INIT_21(256'hF9ADC5D0F029F049FFF8ADCED0FFC9FE09FFF8ADD4F0FFFD0DFFFCADDCF0FFC9),
.INIT_22(256'hA9253620A7B0FFFDCD01E9AE9040C924068DEE85F029FFF9ADBCD003C90B29FF),
.INIT_23(256'hD0F8C088180099FF00B97FA048FAD0CA18009D8A00A2018516A9241B20F08500),
.INIT_24(256'h241B20EED0FFC92406AD2406EE4823FF2068241B20240A8D24A924098D2EA9F5),
.INIT_25(256'h06AD2406CE4823FF2068241B202406CE240A8D24A924098D36A9241220241220),
.INIT_26(256'h8D07291A00ADF110CA1A009D18885D18505D1800BD77A23C8560A9EEB0EEC524),
.INIT_27(256'hA226C24C26B94CF510CA06D01A00DD2000BD77A220009D1A009D04A200A91A00),
.INIT_28(256'h0C10F0C60860FAD0E818003E00A260F0D0E818009D2DD5B9A8FF007D18007D00),
.INIT_29(256'h918E5572B6626792D0E10983F7EECAAB65C76028018516A9FC30F0A5018502A9),
.INIT_2A(256'hEDB890FA94A38734FC17A98473FBD1383108C8AF45063DE6B7592078BE81C5DC),
.INIT_2B(256'hEC352656F6E3E741807FE4BC1011B9A7519D605A6D0DB38253F3D9430A5B3BCE),
.INIT_2C(256'h3E022B7718805805B18C42B01C4A971513A43FA2BFCFEF4652AC9EF47F0CDFD6),
.INIT_2D(256'h93DE0307F94B2EE80E762D2AF819579B9FD88B79144FF1EB8A0B6ECB6A1A49A8),
.INIT_2E(256'hC02F0FAD9689AA391FFE85361E2295A0235EE01DCCA1D2DA7A7DF0B2E5D47E16),
.INIT_2F(256'h54BD9986BB752C7B33D770A6CD7CC1DD2574AE8F401B5F21F5A5C3EA245D2747),
.INIT_30(256'h440164DB3A88C2E94D04E26B69D59C98C61237294EC4615CBA8D4C4832636C9A),
.INIT_31(256'h9DFF80BDE586E48677A2EE0965F7ABC783CAD3C96866B43C7150FD2830F2B56F),
.INIT_32(256'h10CA19019DFED5BDE48677A2F2C6257B20FB8420018502A9F410CA20009D1901),
.INIT_33(256'hE5A426392060F710CA20009D1800BD77A225728DE0A5F2C625E120E385E1A5F7),
.INIT_34(256'h7C8C26748C266E8CC818008DFAD0CA18009D26718D00A9AA48E2651898E184C8),
.INIT_35(256'h09F025D93D2000B9E1A41B30E1C62681CE267CCE2674CE266ECE00A226818C26),
.INIT_36(256'h4020100804020160E08501A9E1856825A44CE83008E0E8266A2026728D2662BD),
.INIT_37(256'h8E268C8E26A98ECA26AC8E268F8E18008E00A2E185E085E4E538E3A526392080),
.INIT_38(256'h2662BD1730E1C6269FEE269AEE2692EE268CEE26A9EE07A2269F8E269A8E2692),
.INIT_39(256'h00A0E286E8E4A660E185E3A526084CEC10CA268820039026A62026AD8D26908D),
.INIT_3A(256'h3007C0F610CA19009D2A1900BD18E2A626598D2662B9C826558D2662B919008C),
.INIT_3B(256'h00691700B90C90F410881800991900791800B918E2A4211F1E1D1C1B1A1960E2),
.INIT_3C(256'h009900E91700B90CB0F410881800991900F91800B938E2A46026794C88170099),
.INIT_3D(256'h6CF89A018616A226A84CC8FBF0E2C46001F01900D91800B900A06026974C8817),
.INIT_3E(256'hF9D02AE0E803950185AA00A904804CF710CA04809DF7D4BD7FA2018502A9FFFC),
.INIT_3F(256'h85EA0F851C851B85118504CB2004CB2001108D9AFD10CA04A22330EA04A90285),
.INIT_40(256'h608DF1188D068502A90C3002241ED0F1128D098502A9093003240430EA00A902),
.INIT_41(256'hFFFFFFFFFFFFFFEAFFFC6C0885FDA9D9300224EA04CB201B8508A92C850ED0F4),
.INIT_42(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_43(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_44(256'hA0F91DBD05A2208500A93C857FA9F48512A9F585FBA9018502A9D87801851DA9),
.INIT_45(256'h0BD080C520808D43A9E510CAEDD0881FD02100D921009927D02000D920009900),
.INIT_46(256'h4C02A0F8804C01A00AD01800CD18008DF8804C04A0F9384C03D00180CD21808D),
.INIT_47(256'hF91DBD05A2F385F92BB9F185F923B9F48407A0F285F08500A9F8804C03A0F880),
.INIT_48(256'h55FF00FB174CD710F4A4F4C6E910CAF1D088CFD0F2D1F291D0D0F0D1F09100A0),
.INIT_49(256'h0330F510F7F0AAA9F8804C00A01F1E1D1C1B1A191823222726252423220F69AA),
.INIT_4A(256'h00C9F9334C03F0F9334C0310DF30E1D000A9E5D0AAC5AA85F9334C03D0F9334C),
.INIT_4B(256'hB3D001AAEC01AA8EBBF056E055A2F9334C0390C6B001C9F9334C03B0CF90D1D0),
.INIT_4C(256'hAAC9984ED00155EC488A55D0AAC968E89ACAA5D00155CC01558CADF0ABC0AAA4),
.INIT_4D(256'h00D92DD055C5000099FF4936D0AAC93AD0AAC500B540D055C0A80100BDAA49D0),
.INIT_4E(256'h85EEA90ED02121CDF09115D0CCC54681F085CCA9F18520A923D020ABDD28D001),
.INIT_4F(256'h5569EDD0AAC9F1F0F310F5B0EA55691855A9F9334CF9EB4C00F06CF185F9A9F0),
.INIT_50(256'hE8AAFFA9CFD0D130D390AAE918D8D0ABC9DCF0DE10E0B055E9E4D0E630E890EA),
.INIT_51(256'hC619D0F0C41DD0F0E6F08523D0C826F08829D0C8A82DD0FFE0311033F0CA36D0),
.INIT_52(256'hB00AFA900AF9334C03F0AAC96A6A6A07D052C92A2A2A18AAA911D0F0C515F0F0),
.INIT_53(256'hC91B295529DDD05FC91B0955A9E5D00AC94AEAB04AED904A0549F2D050C90AF7),
.INIT_54(256'hB8D0FAC968BDD08DC968C2D052E0BAFA584CFA9120CDD04EC91B495509D5D011),
.INIT_55(256'h2485248502100650F3242285EFA50FA23C8543A9488AFA584C6048E6A948F8A9),
.INIT_56(256'h0609F029EFA527850E09F0293C8640A2EC10CA22850FE902B010C910E9382485),
.INIT_57(256'h0290106918EFA511906069F3A51910F1C6268503090F690290406918F0292585),
.INIT_58(256'hE80195AA00A99AFFA2FB144C4068AA68F08502A9F38500A9F185F2A5EF850F69),
.INIT_59(256'h00BD25009DF600BD24009DF500BD23009DF400BD208600A2018502A9F9D02CE0),
.INIT_5A(256'h19849DFCC6BD1F849DFC4BBD2A3000E022009DFBBEBD27009DF800BD26009DF7),
.INIT_5B(256'hD0CA1E849DFE96BD1D849DFE57BD1C849DFE18BD1B849DFDB4BD1A849DFD3DBD),
.INIT_5C(256'h852EA9268556A9258566A9EF8549A9F285F18503A932F00429FFF9AD23064CAB),
.INIT_5D(256'h1F84603C8543A92C851FA9308584A9FC102824FC302824F585FAA9F485AAA927),
.INIT_5E(256'h191B91000048191C8D00004A191C8900004A191C850000BB1F1940840000BB19),
.INIT_5F(256'hAF0000501C2CAF001C2CAF00003E1917A600003E19179D000042191996000046),
.INIT_60(256'h0028192DE8000028192DD5000028192DC2000028192DAF0000501D2CAF001D2C),
.INIT_61(256'hC20000281B2DAF0000281A2DE80000281A2DD50000281A2DC20000281A2DAF00),
.INIT_62(256'h1322050D228500220300220F00220F00220F06220F0000281B2DD50000281B2D),
.INIT_63(256'h22025122003722024B220037220100220F3122052B22052522051F2205192205),
.INIT_64(256'h003722026F22003722026922003722026322003722025D220037220257220037),
.INIT_65(256'h00220F00220F00220F4122018722003722028122003722027B22003722027522),
.INIT_66(256'h1FF87F807F80FF07FC817FE00F7EF8871FC08F7FFC808F7F7C0000220F00220F),
.INIT_67(256'hFF3F0000C000F0FFFFFF3F000C00003E0000807F0000001FFEFF03807F00F0FF),
.INIT_68(256'h0000FF0300C0FF0000FC03FCFFFF3F0000F003F0FFFFFF3F003F0000FC0300FF),
.INIT_69(256'h7F7C00FCC33F00F03F0000FF3F0000FF0300F0FF0300FCC3FF03F03F0000FC0F),
.INIT_6A(256'h1FFEFF07807F00F8FF1FE07F807F80FF01FC837FF00F7EF8871F808F7F7C808F),
.INIT_6B(256'h00FFC03F00FCC3FF00F03F00C03FFF0000FF0300FCF30F00FE0300807F0000F0),
.INIT_6C(256'h03C0FFF03F00FC03F00F00FF03C03F00FF00FC03FC3FF03F00F00FFC0300FF03),
.INIT_6D(256'hF8871F808F7F7C808F7F7C00FC03F03FF03F00FFFFFF3F00FF03F0FFFFFF03FC),
.INIT_6E(256'h0FFE0F00807F0000FC1FFEFF0F807F00FCFF1FC0FF807FC0FF00F8837FF0077E),
.INIT_6F(256'h3FF03F0000FF03FF03FF0300F03FFC03FC0FF03FC0FFFFFFFF00FF03FCFFFFFF),
.INIT_70(256'h8F7F7C808F7F7C00FCC3FF00F03FFC0F0000FC0FFFC3FF0000C0FFFC03FF03F0),
.INIT_71(256'h807F0000FF1FFEFF1F807F00FEFF1F80FF807FC07F00F8837FF0077CF8870F80),
.INIT_72(256'h808F7F7C808F7F7C005555555555555555555555555555555555555555FE3F00),
.INIT_73(256'h00807F00C0FF1FE0FF1F807F00FEFF0100FF817FE03F00F0837FF003FCF8C70F),
.INIT_74(256'h0F808F7F7C808F7F7C00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAFEFF),
.INIT_75(256'hFF01807F00E0FF1F00FE3F807F00FF1F0000FE817FE01F00F0877FF803FCF8C7),
.INIT_76(256'h8158601B0812B4C6C9CA095555555555555555555555555555555555555555FE),
.INIT_77(256'h9306CD8A2DAFECC53B000A8DFAE2E22FBC7C3B847932DC7BA025D9BFD801864B),
.INIT_78(256'hC855510C4723EF20B5066DF7E873D37168A20CCE8CEF3653B26AC4774614A56A),
.INIT_79(256'hBD870A801D8F71B388CC222D3B583CF86305D8C4E276B03867A7203FC458F4FE),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA3942806846ECD3E270E92359A1),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hF933F884F000F72D34383931294328434347FFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module BIOS_ROM_blk_mem_gen_top
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule |
module BIOS_ROM_blk_mem_gen_v8_2
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [7:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire [11:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [7:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
BIOS_ROM_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule |
module BIOS_ROM_blk_mem_gen_v8_2_synth
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module counter #(
parameter MAX = 15,
parameter START = 0,
parameter signed INC = 1
) (
input clk,
input reset,
input ce,
output reg [$clog2(MAX+1)-1:0] count = START
);
localparam TCQ = 1;
always @(posedge clk)
if (reset)
count <= #TCQ START;
else if (ce)
count <= #TCQ count + INC;
endmodule |
module pipeline_ce_reset #(
parameter STAGES = 0
) (
input clk,
input ce,
input reset,
input i,
output o
);
localparam TCQ = 1;
if (!STAGES)
assign o = i;
else begin
reg [STAGES-1:0] pipeline = 0;
assign o = pipeline[STAGES-1];
always @(posedge clk)
if (reset)
pipeline <= #TCQ pipeline << 1;
else if (ce)
pipeline <= #TCQ (pipeline << 1) | i;
end
endmodule |
module pipeline_ce #(
parameter STAGES = 0
) (
input clk,
input ce,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, ce, 1'b0, i, o);
endmodule |
module pipeline_reset #(
parameter STAGES = 0
) (
input clk,
input reset,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, 1'b1, reset, i, o);
endmodule |
module pipeline #(
parameter STAGES = 0
) (
input clk,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, 1'b1, 1'b0, i, o);
endmodule |
module reverse_words #(
parameter M = 4,
parameter WORDS = 1
) (
input [M*WORDS-1:0] in,
output [M*WORDS-1:0] out
);
genvar i;
for (i = 0; i < WORDS; i = i + 1) begin : REV
assign out[i*M+:M] = in[(WORDS-i-1)*M+:M];
end
endmodule |
module rotate_right #(
parameter M = 4,
parameter S = 0
) (
input [M-1:0] in,
output [M-1:0] out
);
wire [M*2-1:0] in2 = {in, in};
assign out = in2[S%M+:M];
endmodule |
module rotate_left #(
parameter M = 4,
parameter S = 0
) (
input [M-1:0] in,
output [M-1:0] out
);
wire [M*2-1:0] in2 = {in, in};
assign out = in2[M-(S%M)+:M];
endmodule |
module mux_one #(
parameter WIDTH = 2,
parameter WIDTH_SZ = $clog2(WIDTH+1)
) (
input [WIDTH-1:0] in,
input [WIDTH_SZ-1:0] sel,
output out
);
assign out = in[sel];
endmodule |
module mux_shuffle #(
parameter U = 2,
parameter V = 2
) (
input [U*V-1:0] in,
output [V*U-1:0] out
);
genvar u, v;
generate
for (u = 0; u < U; u = u + 1) begin : _U
for (v = 0; v < V; v = v + 1) begin : _V
assign out[v*U+u] = in[u*V+v];
end
end
endgenerate
endmodule |
module mux #(
parameter WIDTH = 2,
parameter BITS = 1,
parameter WIDTH_SZ = $clog2(WIDTH+1)
) (
input [BITS*WIDTH-1:0] in,
input [WIDTH_SZ-1:0] sel,
output [BITS-1:0] out
);
wire [WIDTH*BITS-1:0] shuffled;
mux_shuffle #(WIDTH, BITS) u_mux_shuffle(in, shuffled);
mux_one #(WIDTH) u_mux_one [BITS-1:0] (shuffled, sel, out);
endmodule |
module
//============================================================================
// vga_test debug_unit ( .clk(clk), .clr(clr), .hsync(hsync), .vsync(vsync), .red(red), .green(green), .blue(blue) );
//============================================================================
// Instantiation
//============================================================================
// Instantiate vga_sync circuit
wire clk25m, clk6400, clk200, clk100, clk50;
clkdiv div_unit (.clk(clk), .clr(clr), .clk25m(clk25m), .clk800(clk800), .clk200(clk200), .clk100(clk100), .clk50(clk50));
vga_sync sync_unit (
.clk(clk25m), .clr(clr), .hsync(hsync), .vsync(vsync), .video_on(video_on), .pixel_x(pixel_x), .pixel_y(pixel_y)
);
// Instantiate keyboard circuit
wire [15:0] xkey;
ps2_receiver keyboard (.clk(clk25m), .clr(clr), .ps2c(ps2c), .ps2d(ps2d), .xkey(xkey));
//===========================================================================
// Keyboard
//===========================================================================
// Output the signals we need according to the shift register
reg [3:0] direction;
always @ (posedge clk25m or posedge clr)
begin
if (clr)
begin
status <= prepare;
direction <= 4'b0;
btn_visible <= 1'b0;
end
else
begin
// prepare -> activate
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h29)
btn_visible <= 1'b1;
else if (xkey[15: 8] == 8'hF0 && xkey[ 7: 0] == 8'h29)
status <= activate;
// activate -> pause
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h76 && status == activate)
status <= pause;
// pause -> activate
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h29 && status == pause)
status <= activate;
// activate -> terminate
if (iscollide0 || iscollide1)
status <= terminate;
if (status == activate)
begin
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h1d)
direction <= 4'b1000; // Up
else if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h1b)
direction <= 4'b0100; // Down
else if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h1c)
direction <= 4'b0010; // Left
else if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h23)
direction <= 4'b0001; // Right
else if (xkey[15: 8] == 8'hF0)
direction <= 4'b0000;
end
end
end
//============================================================================
// Object's properity
//============================================================================
wire [9:0] back_x, back_y, btn_x, btn_y, side_x, side_y, mycar_x, mycar_y, game_over_x, game_over_y, score_x, score_y;
wire [9:0] explode_x, explode_y;
wire [9:0] obstacle_x [0:4], obstacle_y [0:4];
wire [9:0] digit_x [0:3], digit_y [0:3];
wire [10:0] back_xrom, back_yrom, btn_xrom, btn_yrom, side_xrom, side_yrom;
// Background's properties
assign back_x = pixel_x;
assign back_y = pixel_y;
assign back_xrom = {1'b0, back_x[9:1]};
assign back_yrom = {1'b0, back_y[9:1]};
assign back_addr = back_yrom * 320 + back_xrom;
// Start Button's properties
assign btn_x = pixel_x - 252;
assign btn_y = pixel_y - 379;
assign btn_xrom = {1'b0, btn_x[9:1]};
assign btn_yrom = {1'b0, btn_y[9:1]};
assign btn_pos = (pixel_x >= 252) && (pixel_x < 640) && (pixel_y >= 379) && (pixel_y < 480);
assign btn_addr = btn_yrom * 200 + btn_xrom;
// Side's properties
assign side_x = pixel_x;
assign side_y = pixel_y;
assign side_xrom = {1'b0, side_x[9:1]};
assign side_yrom = {1'b0, side_y[9:1]};
assign side_addr = side_yrom * 320 + side_xrom;
// My car's properties
parameter car_width = 60;
parameter car_height = 100;
parameter car_offset_left = 15;
parameter car_offset_right = 5;
assign mycar_x = pixel_x - mycar_pos_x;
assign mycar_y = pixel_y - mycar_pos_y;
assign mycar_pos = (pixel_x >= mycar_pos_x + car_offset_left) &&
(pixel_x < mycar_pos_x + car_width - car_offset_right) &&
(pixel_y >= mycar_pos_y) &&
(pixel_y < mycar_pos_y + car_height);
assign mycar_addr = mycar_y * 60 + mycar_x;
// Obstacles' properties
parameter police_width = 64;
parameter police_height = 100;
parameter police_offset_left = 5;
parameter police_offset_right = 5;
assign obstacle_x[0] = pixel_x - obstacle_pos_x[0];
assign obstacle_y[0] = pixel_y - obstacle_pos_y[0] + police_height;
assign obstacle_pos0 = (pixel_x >= obstacle_pos_x[0] + police_offset_left) &&
(pixel_x < obstacle_pos_x[0] + police_width - police_offset_right) &&
(pixel_y >= {obstacle_pos_y[0] > police_height ? obstacle_pos_y[0] - police_height : 0}) &&
(pixel_y < obstacle_pos_y[0]);
assign obstacle_addr0 = obstacle_y[0] * 64 + obstacle_x[0];
assign obstacle_x[1] = pixel_x - obstacle_pos_x[1];
assign obstacle_y[1] = pixel_y - obstacle_pos_y[1] + police_height;
assign obstacle_pos1 = (pixel_x >= obstacle_pos_x[1] + police_offset_left) &&
(pixel_x < obstacle_pos_x[1] + police_width - police_offset_right) &&
(pixel_y >= {obstacle_pos_y[1] > police_height ? obstacle_pos_y[1] - police_height : 0}) &&
(pixel_y < obstacle_pos_y[1]);
assign obstacle_addr1 = obstacle_y[1] * 64 + obstacle_x[1];
assign obstacle_x[2] = pixel_x - obstacle_pos_x[2];
assign obstacle_y[2] = pixel_y - obstacle_pos_y[2] + car_height;
assign obstacle_pos2 = (pixel_x >= obstacle_pos_x[2] + car_offset_left) &&
(pixel_x < obstacle_pos_x[2] + car_width - car_offset_right) &&
(pixel_y >= {obstacle_pos_y[2] > car_height ? obstacle_pos_y[2] - car_height : 0}) &&
(pixel_y < obstacle_pos_y[2]);
assign obstacle_addr2 = obstacle_y[2] * 60 + obstacle_x[2];
assign obstacle_x[3] = pixel_x - obstacle_pos_x[3];
assign obstacle_y[3] = pixel_y - obstacle_pos_y[3] + car_height;
assign obstacle_pos3 = (pixel_x >= obstacle_pos_x[3] + car_offset_left) &&
(pixel_x < obstacle_pos_x[3] + car_width - car_offset_right) &&
(pixel_y >= {obstacle_pos_y[3] > car_height ? obstacle_pos_y[3] - car_height : 0}) &&
(pixel_y < obstacle_pos_y[3]);
assign obstacle_addr3 = obstacle_y[3] * 60 + obstacle_x[3];
assign obstacle_x[4] = pixel_x - obstacle_pos_x[4];
assign obstacle_y[4] = pixel_y - obstacle_pos_y[4] + car_height;
assign obstacle_pos4 = (pixel_x >= obstacle_pos_x[4] + car_offset_left) &&
(pixel_x < obstacle_pos_x[4] + car_width - car_offset_right) &&
(pixel_y >= {obstacle_pos_y[4] > car_height ? obstacle_pos_y[4] - car_height : 0}) &&
(pixel_y < obstacle_pos_y[4]);
assign obstacle_addr4 = obstacle_y[4] * 60 + obstacle_x[4];
// Explosion's properties
parameter explode_width = 60;
parameter explode_height = 60;
assign explode_x = pixel_x - explode_pos_x;
assign explode_y = pixel_y - explode_pos_y + explode_height * num;
assign explode_pos = (pixel_x >= explode_pos_x) && (pixel_x < explode_pos_x + explode_width) &&
(pixel_y >= explode_pos_y) && (pixel_y < explode_pos_y + explode_height);
assign explode_addr = explode_y * 60 + explode_x;
// Game-Over prompt's properties
assign game_over_x = pixel_x - 160;
assign game_over_y = pixel_y - 120;
assign game_over_pos = (pixel_x >= 160) && (pixel_x < 480) && (pixel_y >= 120) && (pixel_y < 180);
assign game_over_addr = game_over_y * 320 + game_over_x;
// Score's properties
assign score_x = pixel_x - 120;
assign score_y = pixel_y - 240;
assign score_pos = (pixel_x >= 120) && (pixel_x < 320) && (pixel_y >= 240) && (pixel_y < 300);
assign score_addr = score_y * 200 + score_x;
// Digit's properties
wire [3:0] score [0:3];
parameter digit_width = 32;
parameter digit_height = 32;
assign digit_x[0] = pixel_x - (330 + digit_width * 3);
assign digit_y[0] = pixel_y - 260 + digit_height * score[0];
assign digit_pos0 = (pixel_x >= 330 + digit_width * 3) && (pixel_x < 330 + digit_width * 4) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr0 = digit_y[0] * 32 + digit_x[0];
assign digit_x[1] = pixel_x - (330 + digit_width * 2);
assign digit_y[1] = pixel_y - 260 + digit_height * score[1];
assign digit_pos1 = (pixel_x >= 330 + digit_width * 2) && (pixel_x < 330 + digit_width * 3) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr1 = digit_y[1] * 32 + digit_x[1];
assign digit_x[2] = pixel_x - (330 + digit_width);
assign digit_y[2] = pixel_y - 260 + digit_height * score[2];
assign digit_pos2 = (pixel_x >= 330 + digit_width) && (pixel_x < 330 + digit_width * 2) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr2 = digit_y[2] * 32 + digit_x[2];
assign digit_x[3] = pixel_x - 330;
assign digit_y[3] = pixel_y - 260 + digit_height * score[3];
assign digit_pos3 = (pixel_x >= 330) && (pixel_x < 330 + digit_width) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr3 = digit_y[3] * 32 + digit_x[3];
//=============================================================================
//Collision detector
//=============================================================================
Detector collision_detector (.mycar_pos_x(mycar_pos_x), .mycar_pos_y(mycar_pos_y),
.obstacle_pos_x0(obstacle_pos_x[0]),
.obstacle_pos_x1(obstacle_pos_x[1]),
.obstacle_pos_x2(obstacle_pos_x[2]),
.obstacle_pos_x3(obstacle_pos_x[3]),
.obstacle_pos_x4(obstacle_pos_x[4]),
.obstacle_pos_y0(obstacle_pos_y[0]),
.obstacle_pos_y1(obstacle_pos_y[1]),
.obstacle_pos_y2(obstacle_pos_y[2]),
.obstacle_pos_y3(obstacle_pos_y[3]),
.obstacle_pos_y4(obstacle_pos_y[4]),
.iscollide0(iscollide0),
.iscollide1(iscollide1),
.iscollide2(iscollide2),
.iscollide3(iscollide3),
.iscollide4(iscollide4)
);
//=============================================================================
// Procedure to deal with the random generation and collision
//=============================================================================
parameter lane_x = 96;
always @ (posedge clk100 or posedge clr)
begin
if (clr)
begin
obstacle_pos_x[0] = 101;
obstacle_pos_y[0] = 100;
obstacle_pos_x[1] = 485;
obstacle_pos_y[1] = 100;
obstacle_pos_x[2] = 197;
obstacle_pos_y[2] = 100;
obstacle_pos_x[3] = 293;
obstacle_pos_y[3] = 100;
obstacle_pos_x[4] = 389;
obstacle_pos_y[4] = 100;
car_on_road = 25'b00001_00100_01000_10000_00010;
cnt <= 32'b0;
explode_visible <= 1'b0;
end
else
begin
if (status == activate)
begin
//=============================================================================
// Random generator
//=============================================================================
if (direction != 4'b0)
cnt <= cnt + 1023;
else
cnt <= cnt + 1;
if (iscollide0 || obstacle_pos_y[0] > 480 + police_height)
begin
// Clear the flag signal
if (car_on_road[ 0] == 1'b1)
car_on_road[ 0] = 1'b0;
if (car_on_road[ 5] == 1'b1)
car_on_road[ 5] = 1'b0;
if (car_on_road[10] == 1'b1)
car_on_road[10] = 1'b0;
if (car_on_road[15] == 1'b1)
car_on_road[15] = 1'b0;
if (car_on_road[20] == 1'b1)
car_on_road[20] = 1'b0;
// Set explosion position signal
if (iscollide0)
begin
explode_pos_x <= mycar_pos_x + (car_width - explode_width) / 2;
explode_pos_y <= mycar_pos_y + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[ 0] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x * 3 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[ 5] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x * 5 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[10] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x * 7 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[15] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[0] = 79 + (lane_x * 9 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[20] = 1'b1;
end
end
if (iscollide1 || obstacle_pos_y[1] > 480 + police_height)
begin
// Clear the flag signal
if (car_on_road[ 1] == 1'b1)
car_on_road[ 1] = 1'b0;
if (car_on_road[ 6] == 1'b1)
car_on_road[ 6] = 1'b0;
if (car_on_road[11] == 1'b1)
car_on_road[11] = 1'b0;
if (car_on_road[16] == 1'b1)
car_on_road[16] = 1'b0;
if (car_on_road[21] == 1'b1)
car_on_road[21] = 1'b0;
// Set explosion position signal
if (iscollide1)
begin
explode_pos_x <= mycar_pos_x + (car_width - explode_width) / 2;
explode_pos_y <= mycar_pos_y + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[ 1] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9 :5] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x * 3 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[ 6] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x * 5 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[11] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x * 7 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[16] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[1] = 79 + (lane_x * 9 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[21] = 1'b1;
end
end
if (iscollide2 || obstacle_pos_y[2] > 480 + car_height)
begin
// Clear the flag signal
if (car_on_road[ 2] == 1'b1)
car_on_road[ 2] = 1'b0;
if (car_on_road[ 7] == 1'b1)
car_on_road[ 7] = 1'b0;
if (car_on_road[12] == 1'b1)
car_on_road[12] = 1'b0;
if (car_on_road[17] == 1'b1)
car_on_road[17] = 1'b0;
if (car_on_road[22] == 1'b1)
car_on_road[22] = 1'b0;
// Set explosion position signal
if (iscollide2)
begin
explode_pos_x <= obstacle_pos_x[2] + (car_width - explode_width) / 2;
explode_pos_y <= obstacle_pos_y[2] + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[ 2] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x * 3 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[ 7] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[14:10] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x * 5 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[12] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[19:15] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x * 7 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[17] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[24:20] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[2] = 79 + (lane_x * 9 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[22] = 1'b1;
end
end
if (iscollide3 || obstacle_pos_y[3] > 480 + car_height)
begin
// Clear the flag signal
if (car_on_road[ 3] == 1'b1)
car_on_road[ 3] = 1'b0;
if (car_on_road[ 8] == 1'b1)
car_on_road[ 8] = 1'b0;
if (car_on_road[13] == 1'b1)
car_on_road[13] = 1'b0;
if (car_on_road[18] == 1'b1)
car_on_road[18] = 1'b0;
if (car_on_road[23] == 1'b1)
car_on_road[23] = 1'b0;
// Set explosion position signal
if (iscollide3)
begin
explode_pos_x <= obstacle_pos_x[3] + (car_width - explode_width) / 2;
explode_pos_y <= obstacle_pos_y[3] + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[ 3] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x * 3 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[ 8] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > car_height + police_height ||
car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > car_height + police_height ||
car_on_road[14:10] == 5'b00100 && obstacle_pos_y[2] > car_height + police_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x * 5 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[13] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[19:15] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x * 7 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[18] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[24:20] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[3] = 79 + (lane_x * 9 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[23] = 1'b1;
end
end
if (iscollide4 || obstacle_pos_y[4] > 480 + car_height)
begin
// Clear the flag signal
if (car_on_road[ 4] == 1'b1)
car_on_road[ 4] = 1'b0;
if (car_on_road[ 9] == 1'b1)
car_on_road[ 9] = 1'b0;
if (car_on_road[14] == 1'b1)
car_on_road[14] = 1'b0;
if (car_on_road[19] == 1'b1)
car_on_road[19] = 1'b0;
if (car_on_road[24] == 1'b1)
car_on_road[24] = 1'b0;
// Set explosion position signal
if (iscollide4)
begin
explode_pos_x <= obstacle_pos_x[4] + (car_width - explode_width) / 2;
explode_pos_y <= obstacle_pos_y[4] + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[ 4] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x * 3 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[ 9] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[14:10] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[14:10] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x * 5 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[14] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[19:15] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[19:15] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x * 7 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[19] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[24:20] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[24:20] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[4] = 79 + (lane_x * 9 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[24] = 1'b1;
end
end
// Move obstacles
if (obstacle_pos_y[0] <= 480 + police_height)
obstacle_pos_y[0] = obstacle_pos_y[0] + 4;
if (obstacle_pos_y[1] <= 480 + police_height)
obstacle_pos_y[1] = obstacle_pos_y[1] + 4;
if (obstacle_pos_y[2] <= 480 + car_height)
obstacle_pos_y[2] = obstacle_pos_y[2] + 3;
if (obstacle_pos_y[3] <= 480 + car_height)
obstacle_pos_y[3] = obstacle_pos_y[3] + 3;
if (obstacle_pos_y[4] <= 480 + car_height)
obstacle_pos_y[4] = obstacle_pos_y[4] + 2;
end
//========================================================================
// The explosion animation
//========================================================================
// Disapear the animation
if (num == 0)
explode_visible <= 1'b0;
end
end
//=============================================================================
// Dynamic object's position calculation
//=============================================================================
// Scroll the road
always @ (posedge clk200 or posedge clr)
begin
if (clr)
begin
scroll <= 32'b0;
end
else
begin
if (status == activate)
scroll <= scroll - 2;
end
end
// Move the car and EDGE detection
always @(posedge clk800 or posedge clr)
begin
if (clr)
begin
mycar_pos_x <= 289;
mycar_pos_y <= 384;
end
else
begin
if (status == activate)
begin
if (direction == 4'b1000)
begin
if (mycar_pos_y >= 1)
mycar_pos_y <= mycar_pos_y - 1 ;
end
else if (direction == 4'b0100)
begin
if (mycar_pos_y < 380)
mycar_pos_y <= mycar_pos_y + 1;
end
else if (direction == 4'b0010)
begin
if (mycar_pos_x >= 79 - car_offset_left)
mycar_pos_x <= mycar_pos_x - 1;
end
else if (direction == 4'b0001)
begin
if (mycar_pos_x < 500 + car_offset_right)
mycar_pos_x <= mycar_pos_x + 1;
end
end
end
end
// Explosion
always @ (posedge clk50 or posedge clr)
begin
if (clr)
begin
num <= 4'b0;
end
else
begin
if (status == activate)
begin
num <= (num + 1) % 14;
if (iscollide0 || iscollide1 || iscollide2 || iscollide3 || iscollide4)
begin
num <= 1;
end
end
end
end
//==============================================================================
// Score Counter
//==============================================================================
wire plus;
Counter score_counter (
.clk(clk),
.clr(clr),
.plus(plus),
.score0(score[0]), .score1(score[1]), .score2(score[2]), .score3(score[3]),
.high_score0(high_score0), .high_score1(high_score1), .high_score2(high_score2), .high_score3(high_score3)
);
assign plus = iscollide2 || iscollide3 || iscollide4;
endmodule |
module sha2_sec_ti2_rm0_plain_nand(
input wire a,
input wire b,
output reg q
);
wire tmp;
assign tmp = ~(a&b);
wire tmp2 = tmp;
reg tmp3;
always @*tmp3 = tmp2;
always @* q = tmp3;
endmodule |
module sha2_sec_ti2_rm0_ti2_and_l0 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
output reg [1:0] o_y //WARNING: non uniform
);
wire [1:0] a = i_a^ NOTA[0];
wire [1:0] b = i_b^ NOTB[0];
wire n00,n10,n01;
wire n11;
sha2_sec_ti2_rm0_plain_nand nand00_ITK(.a(a[0]), .b(b[0]), .q(n00));
sha2_sec_ti2_rm0_plain_nand nand10_ITK(.a(a[1]), .b(b[0]), .q(n10));
sha2_sec_ti2_rm0_plain_nand nand01_ITK(.a(a[0]), .b(b[1]), .q(n01));
sha2_sec_ti2_rm0_plain_nand nand11_ITK(.a(a[1]), .b(b[1]), .q(n11));
always @* begin
o_y[0] = n00 ^ n11 ^ NOTY[0];
o_y[1] = n10 ^ n01;
end
endmodule |
module sha2_sec_ti2_rm0 (
input wire i_reset,
input wire i_clk,
input wire i_sha512,
input wire i_write,//1 cycle pulse each time i_dat is valid for message input.
input wire i_write_state,//1 cycle pulse each time i_dat is valid for state input.
input wire i_read,
input wire i_init_mask,//pulse must last at least two cycles
input wire [64-1:0] i_rnd,
input wire [64-1:0] i_dat_mdat,
input wire [64-1:0] i_dat_mask,//input message and state are fed serially word by word.
output reg [64-1:0] o_dat_mdat,
output reg [64-1:0] o_dat_mask,
output reg o_run,
output reg o_valid
);
//registers
reg [16*64-1:0] w;
reg [8*64-1:0] state;
reg [8*64-1:0] state_mask;
reg [8*64-1:0] initial_state;
reg [64-1:0] initial_state_mask_seed;
reg [64-1:0] initial_state_mask;
always @* o_dat_mdat = state[7*64+:64];
always @* o_dat_mask = state_mask[7*64+:64];
function [3:0] func_prince_sbox;
input [3:0] in;
begin
case(in)
4'h0: func_prince_sbox = 4'hB;
4'h1: func_prince_sbox = 4'hF;
4'h2: func_prince_sbox = 4'h3;
4'h3: func_prince_sbox = 4'h2;
4'h4: func_prince_sbox = 4'hA;
4'h5: func_prince_sbox = 4'hC;
4'h6: func_prince_sbox = 4'h9;
4'h7: func_prince_sbox = 4'h1;
4'h8: func_prince_sbox = 4'h6;
4'h9: func_prince_sbox = 4'h7;
4'hA: func_prince_sbox = 4'h8;
4'hB: func_prince_sbox = 4'h0;
4'hC: func_prince_sbox = 4'hE;
4'hD: func_prince_sbox = 4'h5;
4'hE: func_prince_sbox = 4'hD;
4'hF: func_prince_sbox = 4'h4;
endcase
end
endfunction
function [64-1:0] func_substitution;
input [64-1:0] in;
integer i;
reg [64-1:0] out;
begin
for(i=0;i<64/4;i=i+1) begin
out[i*4+:4] = func_prince_sbox(in[i*4+:4]);
end
func_substitution = out;
end
endfunction
function [64-1:0] func_permutation;
input [64-1:0] in;
integer i;
integer base4,rank,j;
reg [64-1:0] out;
begin
for(i=0;i<64;i=i+1) begin
base4 = 4*(i/4);
rank = i-base4;
case(rank)
0: begin
if(i==3*4) j = 1;
else j = base4 + 29*4;
end
1: begin
if(i==13*4+1) j = 2;
else j = base4 + 3*4 + 1;//0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13
end
2: begin
if(i==11*4+2) j = 3;
else j = base4 + 5*4 + 2;//0,5,10,15,4,9,14,3,8,13,2,7,12,1,6,11
end
3: begin
if(i==9*4+3) j = 0;
else j = base4 + 7*4 + 3;//0,7,14,5,12,3,10,1,8,15,6,13,4,11,2,9
end
endcase
j = j % 64;
out[j] = in[i];
end
func_permutation = out;
end
endfunction
//syndrom[4] and syndrom[5] manually modified to avoid duplicate
//extended_hamming_code_96_64_f
//Compute 32 bits Error Detection Code from a 64 bits input.
//The EDC is an extended hamming code capable of detecting any 1,2 and 3 bits errors in the input data or the EDC.
//There are 18446744073709551616 valid code words out of 79228162514264337593543950336 therefore 99% of errors are detected.
//Dot graphic view: in[0]...in[63]
// syndrom[ 0]: x xx xx x (6 inputs)
// syndrom[ 1]: x x x x x x (6 inputs)
// syndrom[ 2]: x xx x x x (6 inputs)
// syndrom[ 3]: x x x x x x (6 inputs)
// syndrom[ 4]: x x x x x X (6 inputs)
// syndrom[ 5]: x xx xx X (6 inputs)
// syndrom[ 6]: x x x x x x (6 inputs)
// syndrom[ 7]: x x x x x x (6 inputs)
// syndrom[ 8]: x x x x x x (6 inputs)
// syndrom[ 9]: x x x x x x (6 inputs)
// syndrom[10]: x x x x x x (6 inputs)
// syndrom[11]: x x x xx x (6 inputs)
// syndrom[12]: x x x x x x (6 inputs)
// syndrom[13]: x x x x x x (6 inputs)
// syndrom[14]: x x x x x x (6 inputs)
// syndrom[15]: x x x x x x (6 inputs)
// syndrom[16]: x x x x x x (6 inputs)
// syndrom[17]: x x x x x x (6 inputs)
// syndrom[18]: x x x x x x (6 inputs)
// syndrom[19]: x x x x x x (6 inputs)
// syndrom[20]: x x x x x x (6 inputs)
// syndrom[21]: x x x x x x (6 inputs)
// syndrom[22]: x x x x x x (6 inputs)
// syndrom[23]: x x x x x x (6 inputs)
// syndrom[24]: x x x x xx (6 inputs)
// syndrom[25]: x x x x x x (6 inputs)
// syndrom[26]: x x x x x x (6 inputs)
// syndrom[27]: xx x x x x (6 inputs)
// syndrom[28]: x x xx xx (6 inputs)
// syndrom[29]: x x x x x x (6 inputs)
// syndrom[30]: xx x x xx (6 inputs)
// syndrom[31]: xx xx x x (6 inputs)
//Input usage report:
// input bit 0 used 3 times (syndrom bits 0 1 2)
// input bit 1 used 3 times (syndrom bits 3 4 5)
// input bit 2 used 3 times (syndrom bits 6 7 8)
// input bit 3 used 3 times (syndrom bits 9 10 11)
// input bit 4 used 3 times (syndrom bits 12 13 14)
// input bit 5 used 3 times (syndrom bits 15 16 17)
// input bit 6 used 3 times (syndrom bits 18 19 20)
// input bit 7 used 3 times (syndrom bits 21 22 23)
// input bit 8 used 3 times (syndrom bits 24 25 26)
// input bit 9 used 3 times (syndrom bits 27 28 29)
// input bit 10 used 3 times (syndrom bits 27 30 31)
// input bit 11 used 3 times (syndrom bits 28 30 31)
// input bit 12 used 3 times (syndrom bits 24 25 29)
// input bit 13 used 3 times (syndrom bits 21 22 26)
// input bit 14 used 3 times (syndrom bits 18 19 23)
// input bit 15 used 3 times (syndrom bits 15 16 20)
// input bit 16 used 3 times (syndrom bits 12 13 17)
// input bit 17 used 3 times (syndrom bits 9 10 14)
// input bit 18 used 3 times (syndrom bits 6 7 11)
// input bit 19 used 3 times (syndrom bits 3 4 8)
// input bit 20 used 3 times (syndrom bits 0 1 5)
// input bit 21 used 3 times (syndrom bits 0 2 5)
// input bit 22 used 3 times (syndrom bits 1 2 8)
// input bit 23 used 3 times (syndrom bits 3 4 11)
// input bit 24 used 3 times (syndrom bits 6 7 14)
// input bit 25 used 3 times (syndrom bits 9 10 17)
// input bit 26 used 3 times (syndrom bits 12 13 20)
// input bit 27 used 3 times (syndrom bits 15 16 23)
// input bit 28 used 3 times (syndrom bits 18 19 26)
// input bit 29 used 3 times (syndrom bits 21 22 29)
// input bit 30 used 3 times (syndrom bits 24 25 30)
// input bit 31 used 3 times (syndrom bits 27 28 31)
// input bit 32 used 3 times (syndrom bits 24 28 31)
// input bit 33 used 3 times (syndrom bits 25 27 30)
// input bit 34 used 3 times (syndrom bits 18 21 22)
// input bit 35 used 3 times (syndrom bits 19 26 29)
// input bit 36 used 3 times (syndrom bits 12 15 16)
// input bit 37 used 3 times (syndrom bits 13 20 23)
// input bit 38 used 3 times (syndrom bits 6 9 10)
// input bit 39 used 3 times (syndrom bits 7 14 17)
// input bit 40 used 3 times (syndrom bits 2 3 4)
// input bit 41 used 3 times (syndrom bits 1 8 11)
// input bit 42 used 3 times (syndrom bits 0 5 11)
// input bit 43 used 3 times (syndrom bits 0 5 8)
// input bit 44 used 3 times (syndrom bits 1 3 4)
// input bit 45 used 3 times (syndrom bits 2 7 17)
// input bit 46 used 3 times (syndrom bits 6 9 14)
// input bit 47 used 3 times (syndrom bits 10 13 23)
// input bit 48 used 3 times (syndrom bits 12 15 20)
// input bit 49 used 3 times (syndrom bits 16 19 29)
// input bit 50 used 3 times (syndrom bits 18 21 26)
// input bit 51 used 3 times (syndrom bits 22 25 27)
// input bit 52 used 3 times (syndrom bits 24 30 31)
// input bit 53 used 3 times (syndrom bits 24 28 30)
// input bit 54 used 3 times (syndrom bits 22 28 31)
// input bit 55 used 3 times (syndrom bits 25 26 27)
// input bit 56 used 3 times (syndrom bits 16 18 21)
// input bit 57 used 3 times (syndrom bits 19 20 29)
// input bit 58 used 3 times (syndrom bits 10 12 15)
// input bit 59 used 3 times (syndrom bits 13 14 23)
// input bit 60 used 3 times (syndrom bits 2 6 9)
// input bit 61 used 3 times (syndrom bits 1 7 17)
// input bit 62 used 3 times (syndrom bits 0 3 5)
// input bit 63 used 3 times (syndrom bits 4 8 11)
function [32-1:0] extended_hamming_code_96_64_f;
input [64-1:0] in;
reg [32-1:0] syndrom;
begin
syndrom[ 0] = in[ 0]^in[20]^in[21]^in[42]^in[43]^in[62];//6 inputs
syndrom[ 1] = in[ 0]^in[20]^in[22]^in[41]^in[44]^in[61];//6 inputs
syndrom[ 2] = in[ 0]^in[21]^in[22]^in[40]^in[45]^in[60];//6 inputs
syndrom[ 3] = in[ 1]^in[19]^in[23]^in[40]^in[44]^in[62];//6 inputs
syndrom[ 4] = in[ 1]^in[19]^in[23]^in[40]^in[44]^in[63];//6 inputs
syndrom[ 5] = in[ 1]^in[20]^in[21]^in[42]^in[43]^in[62];//6 inputs
syndrom[ 6] = in[ 2]^in[18]^in[24]^in[38]^in[46]^in[60];//6 inputs
syndrom[ 7] = in[ 2]^in[18]^in[24]^in[39]^in[45]^in[61];//6 inputs
syndrom[ 8] = in[ 2]^in[19]^in[22]^in[41]^in[43]^in[63];//6 inputs
syndrom[ 9] = in[ 3]^in[17]^in[25]^in[38]^in[46]^in[60];//6 inputs
syndrom[10] = in[ 3]^in[17]^in[25]^in[38]^in[47]^in[58];//6 inputs
syndrom[11] = in[ 3]^in[18]^in[23]^in[41]^in[42]^in[63];//6 inputs
syndrom[12] = in[ 4]^in[16]^in[26]^in[36]^in[48]^in[58];//6 inputs
syndrom[13] = in[ 4]^in[16]^in[26]^in[37]^in[47]^in[59];//6 inputs
syndrom[14] = in[ 4]^in[17]^in[24]^in[39]^in[46]^in[59];//6 inputs
syndrom[15] = in[ 5]^in[15]^in[27]^in[36]^in[48]^in[58];//6 inputs
syndrom[16] = in[ 5]^in[15]^in[27]^in[36]^in[49]^in[56];//6 inputs
syndrom[17] = in[ 5]^in[16]^in[25]^in[39]^in[45]^in[61];//6 inputs
syndrom[18] = in[ 6]^in[14]^in[28]^in[34]^in[50]^in[56];//6 inputs
syndrom[19] = in[ 6]^in[14]^in[28]^in[35]^in[49]^in[57];//6 inputs
syndrom[20] = in[ 6]^in[15]^in[26]^in[37]^in[48]^in[57];//6 inputs
syndrom[21] = in[ 7]^in[13]^in[29]^in[34]^in[50]^in[56];//6 inputs
syndrom[22] = in[ 7]^in[13]^in[29]^in[34]^in[51]^in[54];//6 inputs
syndrom[23] = in[ 7]^in[14]^in[27]^in[37]^in[47]^in[59];//6 inputs
syndrom[24] = in[ 8]^in[12]^in[30]^in[32]^in[52]^in[53];//6 inputs
syndrom[25] = in[ 8]^in[12]^in[30]^in[33]^in[51]^in[55];//6 inputs
syndrom[26] = in[ 8]^in[13]^in[28]^in[35]^in[50]^in[55];//6 inputs
syndrom[27] = in[ 9]^in[10]^in[31]^in[33]^in[51]^in[55];//6 inputs
syndrom[28] = in[ 9]^in[11]^in[31]^in[32]^in[53]^in[54];//6 inputs
syndrom[29] = in[ 9]^in[12]^in[29]^in[35]^in[49]^in[57];//6 inputs
syndrom[30] = in[10]^in[11]^in[30]^in[33]^in[52]^in[53];//6 inputs
syndrom[31] = in[10]^in[11]^in[31]^in[32]^in[52]^in[54];//6 inputs
extended_hamming_code_96_64_f = syndrom;
end
endfunction
function [64-1:0] func_next_mask;
input [64-1:0] seed;
input [64-1:0] key;
reg [64-1:0] mixin;
begin
mixin = func_substitution(func_permutation(seed ^ key));
func_next_mask = {extended_hamming_code_96_64_f(func_permutation(mixin)),extended_hamming_code_96_64_f(mixin)};
end
endfunction
function [63:0] func_next_initial_state_mask;
input [63:0] seed;
func_next_initial_state_mask = func_next_mask(seed,64'hE56D24FA_7BC3D5AB);
endfunction
function [63:0] func_next_wi_mask;
input [63:0] seed;
func_next_wi_mask = func_next_mask(seed,64'hB2DD568E_019A3FBD);
endfunction
wire [64-1:0] next_initial_state_mask = func_next_initial_state_mask(initial_state_mask);
wire [64-1:0] w0_mdat = w[0+:64];
reg [64-1:0] w0_mask;
wire [64-1:0] next_w0_mask = func_next_wi_mask(w0_mask);
wire [64-1:0] w1_mdat = w[1*64+:64];
reg [64-1:0] w1_mask;
wire [64-1:0] next_w1_mask = func_next_wi_mask(w1_mask);
wire [64-1:0] w6_mdat = w[6*64+:64];
reg [64-1:0] w6_mask;
wire [64-1:0] next_w6_mask = func_next_wi_mask(w6_mask);
wire [64-1:0] w14_mdat = w[14*64+:64];
reg [64-1:0] w14_mask;
wire [64-1:0] next_w14_mask = func_next_wi_mask(w14_mask);
wire [64-1:0] w15_mdat = w[15*64+:64];
reg [64-1:0] w15_mask;
wire [64-1:0] next_w15_mask = func_next_wi_mask(w15_mask);
wire [64-1:0] initial_state_write_delta_mask = initial_state_mask ^ state_mask[7*64+:64];
wire [64-1:0] initial_state_write_mdat = state[7*64+:64] ^ initial_state_write_delta_mask;
wire [64-1:0] initial_a_mask = w[7*64+:64];
wire [64-1:0] initial_b_mask = w[6*64+:64];
wire [64-1:0] initial_c_mask = w[5*64+:64];
wire [64-1:0] initial_d_mask = w[4*64+:64];
wire [64-1:0] initial_e_mask = w[3*64+:64];
wire [64-1:0] initial_f_mask = w[2*64+:64];
wire [64-1:0] initial_g_mask = w[1*64+:64];
wire [64-1:0] initial_h_mask = w[0*64+:64];
//SHA256 funcs
function [31:0] sigma0_256;
input [31:0] x;
sigma0_256 = s_256(x,2) ^ s_256(x,13) ^ s_256(x,22);
endfunction
function [31:0] sigma1_256;
input [31:0] x;
sigma1_256 = s_256(x,6) ^ s_256(x,11) ^ s_256(x,25);
endfunction
function [31:0] s_256;
input [31:0] x;
input integer n;
s_256 = (x >> n) | (x<<(32-n));
endfunction
function [31:0] gamma0_256;
input [31:0] x;
gamma0_256 = s_256(x,7) ^ s_256(x,18) ^ (x>>3);
endfunction
function [31:0] gamma1_256;
input [31:0] x;
gamma1_256 = s_256(x,17) ^ s_256(x,19) ^ (x>>10);
endfunction
//SHA512 funcs
function [63:0] sigma0;//boolean
input [63:0] x;
sigma0 = s(x,28) ^ s(x,34) ^ s(x,39);
endfunction
function [63:0] sigma1;//boolean
input [63:0] x;
sigma1 = s(x,14) ^ s(x,18) ^ s(x,41);
endfunction
function [63:0] s;//boolean
input [63:0] x;
input integer n;
s = (x >> n) | (x<<(64-n));
endfunction
function [63:0] gamma0;//boolean
input [63:0] x;
gamma0 = s(x,1) ^ s(x,8) ^ (x>>7);
endfunction
function [63:0] gamma1;//boolean
input [63:0] x;
gamma1 = s(x,61) ^ s(x,19) ^ (x>>6);
endfunction
reg state_update;
reg [7:0] step;
reg [7:0] state_step;
wire state_stage_ready = state_step == step;
wire [7:0] step_incr = step + 1'b1;
wire [7:0] step_rounds_max = i_sha512 ? 80+15+1 : 64+15+1;
wire [7:0] step_max = step_rounds_max+4;
wire [6:0] adders_width = i_sha512 ? 64 : 32;
always @(posedge i_clk,posedge i_reset) begin: CONTROL
if(i_reset) begin
step <= 0;
o_run <= 0;
o_valid <= 0;
state_update <= 0;
end else begin
if(i_write) begin
step <= step_incr;
o_valid <= 0;
if(step==15) begin
o_run <= 1'b1;
state_update <= 1'b1;
end
end else if(o_run) begin
if(state_stage_ready) begin
if(step==step_max+1'b1) begin
state_update <= 1'b0;
o_valid <= 1'b1;
o_run <= 1'b0;
end else begin
state_update <= 1'b1;
end
step <= step_incr;
end
end else if(o_valid) begin
if(step==step_max+1+8) begin
o_valid <= 0;
step <= 0;
end else if(i_read) step <= step_incr;
end else begin
state_update <= 1'b0;
end
end
end
reg [64-1:0] gamma1_out_mdat;
reg [64-1:0] gamma1_out_mask;
reg [64-1:0] gamma0_out_mdat;
reg [64-1:0] gamma0_out_mask;
reg [64-1:0] w_wi_out_mdat;
reg [64-1:0] w_wi_out_mask;
wire w_wi_adder_out_mdat;
wire w_wi_adder_out_mask;
wire [64-1:0] w_wi_delta_mask;
sha2_sec_ti2_rm0_xor #(.WIDTH(64)) u_wi_delta_mask_xor_ITK(.a(w_wi_out_mask), .b(next_w0_mask), .y(w_wi_delta_mask));
wire [64-1:0] w_wi_write_to_w0 = w_wi_out_mdat ^ w_wi_delta_mask;
wire [64-1:0] i_dat_delta_mask;
sha2_sec_ti2_rm0_xor #(.WIDTH(64)) u_dat_delta_mask_xor_ITK(.a(i_dat_mask), .b(next_w0_mask), .y(i_dat_delta_mask));
wire [64-1:0] i_dat_write_to_w0 = i_dat_mdat ^ i_dat_delta_mask;
wire [64*64-1:0] k_256 = 2048'hc67178f2bef9a3f7a4506ceb90befffa8cc7020884c8781478a5636f748f82ee682e6ff35b9cca4f4ed8aa4a391c0cb334b0bcb52748774c1e376c0819a4c116106aa070f40e3585d6990624d192e819c76c51a3c24b8b70a81a664ba2bfe8a192722c8581c2c92e766a0abb650a735453380d134d2c6dfc2e1b213827b70a851429296706ca6351d5a79147c6e00bf3bf597fc7b00327c8a831c66d983e515276f988da5cb0a9dc4a7484aa2de92c6f240ca1cc0fc19dc6efbe4786e49b69c1c19bf1749bdc06a780deb1fe72be5d74550c7dc3243185be12835b01d807aa98ab1c5ed5923f82a459f111f13956c25be9b5dba5b5c0fbcf71374491428a2f98;
wire [80*64-1:0] k = 5120'h6c44198c4a4758175fcb6fab3ad6faec597f299cfc657e2a4cc5d4becb3e42b6431d67c49c100d4c3c9ebe0a15c9bebc32caab7b40c7249328db77f523047d841b710b35131c471b113f9804bef90dae0a637dc5a2c898a606f067aa72176fbaf57d4f7fee6ed178eada7dd6cde0eb1ed186b8c721c0c207ca273eceea26619cc67178f2e372532bbef9a3f7b2c67915a4506cebde82bde990befffa23631e288cc702081a6439ec84c87814a1f0ab7278a5636f43172f60748f82ee5defb2fc682e6ff3d6b2b8a35b9cca4f7763e3734ed8aa4ae3418acb391c0cb3c5c95a6334b0bcb5e19b48a82748774cdf8eeb991e376c085141ab5319a4c116b8d2d0c8106aa07032bbd1b8f40e35855771202ad69906245565a910d192e819d6ef5218c76c51a30654be30c24b8b70d0f89791a81a664bbc423001a2bfe8a14cf1036492722c851482353b81c2c92e47edaee6766a0abb3c77b2a8650a73548baf63de53380d139d95b3df4d2c6dfc5ac42aed2e1b21385c26c92627b70a8546d22ffc142929670a0e6e7006ca6351e003826fd5a79147930aa725c6e00bf33da88fc2bf597fc7beef0ee4b00327c898fb213fa831c66d2db43210983e5152ee66dfab76f988da831153b55cb0a9dcbd41fbd44a7484aa6ea6e4832de92c6f592b0275240ca1cc77ac9c650fc19dc68b8cd5b5efbe4786384f25e3e49b69c19ef14ad2c19bf174cf6926949bdc06a725c7123580deb1fe3b1696b172be5d74f27b896f550c7dc3d5ffb4e2243185be4ee4b28c12835b0145706fbed807aa98a3030242ab1c5ed5da6d8118923f82a4af194f9b59f111f1b605d0193956c25bf348b538e9b5dba58189dbbcb5c0fbcfec4d3b2f7137449123ef65cd428a2f98d728ae22;
reg [64-1:0] initial_a,initial_b,initial_c,initial_d,initial_e,initial_f,initial_g,initial_h;
always @* {initial_a,initial_b,initial_c,initial_d,initial_e,initial_f,initial_g,initial_h} = initial_state;
reg [64-1:0] a_mdat,b_mdat,c_mdat,d_mdat,e_mdat,f_mdat,g_mdat,h_mdat;
always @* {a_mdat,b_mdat,c_mdat,d_mdat,e_mdat,f_mdat,g_mdat,h_mdat} = state;
wire [31:0] a_256_mdat = a_mdat[31:0];
wire [31:0] b_256_mdat = b_mdat[31:0];
wire [31:0] c_256_mdat = c_mdat[31:0];
wire [31:0] d_256_mdat = d_mdat[31:0];
wire [31:0] e_256_mdat = e_mdat[31:0];
wire [31:0] f_256_mdat = f_mdat[31:0];
wire [31:0] g_256_mdat = g_mdat[31:0];
wire [31:0] h_256_mdat = h_mdat[31:0];
reg [64-1:0] a_mask,b_mask,c_mask,d_mask,e_mask,f_mask,g_mask,h_mask;
always @* {a_mask,b_mask,c_mask,d_mask,e_mask,f_mask,g_mask,h_mask} = state_mask;
wire [31:0] a_256_mask = a_mask[31:0];
wire [31:0] b_256_mask = b_mask[31:0];
wire [31:0] c_256_mask = c_mask[31:0];
wire [31:0] d_256_mask = d_mask[31:0];
wire [31:0] e_256_mask = e_mask[31:0];
wire [31:0] f_256_mask = f_mask[31:0];
wire [31:0] g_256_mask = g_mask[31:0];
wire [31:0] h_256_mask = h_mask[31:0];
reg [64-1:0] ki;
wire [31:0] ki_256 = ki[0+:32];
wire [31:0] sigma1_e_256_mdat = sigma1_256(e_256_mdat);
wire [31:0] sigma1_e_256_mask = sigma1_256(e_256_mask);
wire [31:0] gamma1_256_mdat = gamma1_256(w1_mdat[0+:32]);
wire [31:0] gamma1_256_mask = gamma1_256(w1_mask[0+:32]);
wire [31:0] gamma0_256_mdat = gamma0_256(w14_mdat[0+:32]);
wire [31:0] gamma0_256_mask = gamma0_256(w14_mask);
wire [31:0] sigma0_a_256_mdat = sigma0_256(a_256_mdat);
wire [31:0] sigma0_a_256_mask = sigma0_256(a_256_mask);
wire [63:0] sigma1_e_mdat = sigma1(e_mdat);
wire [63:0] sigma1_e_mask = sigma1(e_mask);
wire [63:0] gamma1_mdat = gamma1(w1_mdat);
wire [63:0] gamma1_mask = gamma1(w1_mask);
wire [63:0] gamma0_mdat = gamma0(w14_mdat);
wire [63:0] gamma0_mask = gamma0(w14_mask);
wire [63:0] sigma0_a_mdat = sigma0(a_mdat);
wire [63:0] sigma0_a_mask = sigma0(a_mask);
reg [64-1:0] t1_adder_sigma1_mdat;
reg [64-1:0] t1_adder_sigma1_mask;
reg [6-1:0] maj_rnd_in;
wire serial_maj_mdat;
wire serial_maj_mask;
sha2_sec_ti2_rm0_masked_maj u_serial_maj(
.i_clk(i_clk),.i_rnd(maj_rnd_in),
.i_x_mdat(b_mdat[0]),.i_y_mdat(c_mdat[0]),.i_z_mdat(d_mdat[0]),
.i_x_mask(b_mask[0]),.i_y_mask(c_mask[0]),.i_z_mask(d_mask[0]),
.o_mdat(serial_maj_mdat), .o_mask(serial_maj_mask)
);
wire ch_out_mdat;
wire ch_out_mask;
reg [2-1:0] ch_rnd_in;
sha2_sec_ti2_rm0_serial_masked_ch u_ch(
.i_clk(i_clk),.i_rnd(ch_rnd_in),
.i_x_mdat(f_mdat[0]),.i_y_mdat(g_mdat[0]),.i_z_mdat(h_mdat[0]),
.i_x_mask(f_mask[0]),.i_y_mask(g_mask[0]),.i_z_mask(h_mask[0]),
.o_mdat(ch_out_mdat), .o_mask(ch_out_mask)
);
reg [64-1:0] t2_adder_sigma0_mdat;
reg [64-1:0] t2_adder_sigma0_mask;
function [63:0] rr64;
input [63:0] in;
rr64 = {in[0],in[1+:63]};
endfunction
function [63:0] sr64;
input [63:0] in;
input msb;
sr64 = {msb,in[1+:63]};
endfunction
function [64-1:0] rr32;
input [64-1:0] in;
rr32 = {in[32+:32],in[0],in[1+:31]};
endfunction
function [64-1:0] sr32;
input [64-1:0] in;
input msb;
sr32 = {in[32+:32],msb,in[1+:31]};
endfunction
function [64-1:0] rr_word;
input [64-1:0] in;
rr_word = i_sha512 ? rr64(in) : rr32(in);
endfunction
function [64-1:0] sr_word;
input [64-1:0] in;
input msb;
sr_word = i_sha512 ? sr64(in,msb) : sr32(in,msb);
endfunction
//return {mdat,mask}
function [2*64-1:0] rr_masked_word;
input [64-1:0] in_mdat;
input [64-1:0] in_mask;
rr_masked_word = {rr_word(in_mdat),rr_word(in_mask)};
endfunction
localparam A_IDX = 3'h7;
localparam B_IDX = 3'h6;
localparam C_IDX = 3'h5;
localparam D_IDX = 3'h4;
localparam E_IDX = 3'h3;
localparam F_IDX = 3'h2;
localparam G_IDX = 3'h1;
localparam H_IDX = 3'h0;
function [2*64-1:0] rr_state_word;
input [2:0] word_idx;
rr_state_word = rr_masked_word(state[word_idx*64+:64],state_mask[word_idx*64+:64]);
endfunction
wire t1_adder_out_mdat,t1_adder_out_mask;
wire t2_adder_out_mdat,t2_adder_out_mask;
wire next_a_adder_out_mdat,next_a_adder_out_mask;
wire next_e_adder_out_mdat,next_e_adder_out_mask;
wire [64-1:0] next_a = h_mdat;//t1 + t2;
wire [64-1:0] next_b = a_mdat;
wire [64-1:0] next_c = b_mdat;
wire [64-1:0] next_d = c_mdat;
wire [64-1:0] next_e = d_mdat;//d + t1;
wire [64-1:0] next_f = e_mdat;
wire [64-1:0] next_g = f_mdat;
wire [64-1:0] next_h = g_mdat;
wire [64-1:0] next_a_mask = h_mask;
wire [64-1:0] next_b_mask = a_mask;
wire [64-1:0] next_c_mask = b_mask;
wire [64-1:0] next_d_mask = c_mask;
wire [64-1:0] next_e_mask = d_mask;
wire [64-1:0] next_f_mask = e_mask;
wire [64-1:0] next_g_mask = f_mask;
wire [64-1:0] next_h_mask = g_mask;
reg [6:0] adders_step;
reg adders_load_in;
wire maj_start = adders_step == 1;
wire maj_stop = adders_step == adders_width+1;
wire ch_stop = adders_step == adders_width-1;
wire t1_adder_start = adders_step == 1;
wire t1_adder_stop = adders_step == adders_width;
wire w_wi_adder_stop = adders_step == adders_width+2;
wire t2_adder_start = adders_step == 3;
wire t2_adder_stop = adders_step == adders_width+3;
wire next_e_adder_start = adders_step == 4;
wire next_e_adder_stop = adders_step == adders_width+4;
wire next_a_adder_start = next_e_adder_start;
wire next_a_adder_stop = next_e_adder_stop;
reg t1_adder_run,t2_adder_run,next_e_adder_run,adders_run,w_wi_adder_run;
wire next_a_adder_run = next_e_adder_run;
reg [12-1:0] w_wi_adder_rnd_in;
reg [2:0] w_wi_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_4op w_wi_adder (
.i_clk(i_clk),.i_start(t1_adder_start),.i_rnd(w_wi_adder_rnd_in),.i_c_mdat(w_wi_adder_ci_rnd),.i_c_mask(w_wi_adder_ci_rnd),
.i_op0_mdat(gamma0_out_mdat[0]), .i_op1_mdat(gamma1_out_mdat[0]), .i_op2_mdat(w15_mdat[0]), .i_op3_mdat(w6_mdat[0]),
.i_op0_mask(gamma0_out_mask[0]), .i_op1_mask(gamma1_out_mask[0]), .i_op2_mask(w15_mask[0]), .i_op3_mask(w6_mask[0]),
.o_dat_mdat(w_wi_adder_out_mdat), .o_dat_mask(w_wi_adder_out_mask)
);
reg [16-1:0] t1_adder_rnd_in;
reg [3:0] t1_adder_ci_rnd;//used to inject 0 in the carry input
reg ki0_mask_rnd;
wire ki0_mdat = ki[0] ^ ki0_mask_rnd;
sha2_sec_ti2_rm0_serial_masked_add_5op t1_adder (
.i_clk(i_clk),.i_start(t1_adder_start),.i_rnd(t1_adder_rnd_in),.i_c_mdat(t1_adder_ci_rnd),.i_c_mask(t1_adder_ci_rnd),
.i_op0_mdat(a_mdat[0]), .i_op1_mdat(t1_adder_sigma1_mdat[0]), .i_op2_mdat(ch_out_mdat), .i_op3_mdat(ki0_mdat), .i_op4_mdat(w0_mdat[0]),
.i_op0_mask(a_mask[0]), .i_op1_mask(t1_adder_sigma1_mask[0]), .i_op2_mask(ch_out_mask), .i_op3_mask(ki0_mask_rnd), .i_op4_mask(w0_mask[0]),
.o_dat_mdat(t1_adder_out_mdat), .o_dat_mask(t1_adder_out_mask)
);
reg [4-1:0] next_e_adder_rnd_in;
reg next_e_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op next_e_adder (
.i_clk(i_clk),.i_start(next_e_adder_start),.i_rnd(next_e_adder_rnd_in),.i_c_mdat(next_e_adder_ci_rnd),.i_c_mask(next_e_adder_ci_rnd),
.i_op0_mdat(t1_adder_out_mdat), .i_op1_mdat(e_mdat[0]),
.i_op0_mask(t1_adder_out_mask), .i_op1_mask(e_mask[0]),
.o_dat_mdat(next_e_adder_out_mdat), .o_dat_mask(next_e_adder_out_mask)
);
reg [4-1:0] t2_adder_rnd_in;
reg t2_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op t2_adder (
.i_clk(i_clk),.i_start(t2_adder_start),.i_rnd(t2_adder_rnd_in),.i_c_mdat(t2_adder_ci_rnd),.i_c_mask(t2_adder_ci_rnd),
.i_op0_mdat(t2_adder_sigma0_mdat[0]), .i_op1_mdat(serial_maj_mdat),
.i_op0_mask(t2_adder_sigma0_mask[0]), .i_op1_mask(serial_maj_mask),
.o_dat_mdat(t2_adder_out_mdat), .o_dat_mask(t2_adder_out_mask)
);
reg [4-1:0] next_a_adder_rnd_in;
reg next_a_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op next_a_adder (
.i_clk(i_clk),.i_start(next_a_adder_start),.i_rnd(next_a_adder_rnd_in),.i_c_mdat(next_a_adder_ci_rnd),.i_c_mask(next_a_adder_ci_rnd),
.i_op0_mdat(t1_adder_out_mdat), .i_op1_mdat(t2_adder_out_mdat),
.i_op0_mask(t1_adder_out_mask), .i_op1_mask(t2_adder_out_mask),
.o_dat_mdat(next_a_adder_out_mdat), .o_dat_mask(next_a_adder_out_mask)
);
reg [4-1:0] final_a_adder_rnd_in;
reg [4-1:0] final_b_adder_rnd_in;
reg [4-1:0] final_c_adder_rnd_in;
reg [4-1:0] final_d_adder_rnd_in;
reg [4-1:0] final_e_adder_rnd_in;
reg [4-1:0] final_f_adder_rnd_in;
reg [4-1:0] final_g_adder_rnd_in;
reg [4-1:0] final_h_adder_rnd_in;
reg final_adders_start;
wire final_a_adder_out_mdat,final_a_adder_out_mask;
reg final_a_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_a_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_a_adder_ci_rnd),.i_c_mask(final_a_adder_ci_rnd),.i_rnd(final_a_adder_rnd_in),
.i_op0_mdat(a_mdat[0]), .i_op1_mdat(initial_a[0]),
.i_op0_mask(a_mask[0]), .i_op1_mask(initial_a_mask[0]),
.o_dat_mdat(final_a_adder_out_mdat), .o_dat_mask(final_a_adder_out_mask)
);
wire final_b_adder_out_mdat,final_b_adder_out_mask;
reg final_b_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_b_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_b_adder_ci_rnd),.i_c_mask(final_b_adder_ci_rnd),.i_rnd(final_b_adder_rnd_in),
.i_op0_mdat(b_mdat[0]), .i_op1_mdat(initial_b[0]),
.i_op0_mask(b_mask[0]), .i_op1_mask(initial_b_mask[0]),
.o_dat_mdat(final_b_adder_out_mdat), .o_dat_mask(final_b_adder_out_mask)
);
wire final_c_adder_out_mdat,final_c_adder_out_mask;
reg final_c_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_c_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_c_adder_ci_rnd),.i_c_mask(final_c_adder_ci_rnd),.i_rnd(final_c_adder_rnd_in),
.i_op0_mdat(c_mdat[0]), .i_op1_mdat(initial_c[0]),
.i_op0_mask(c_mask[0]), .i_op1_mask(initial_c_mask[0]),
.o_dat_mdat(final_c_adder_out_mdat), .o_dat_mask(final_c_adder_out_mask)
);
wire final_d_adder_out_mdat,final_d_adder_out_mask;
reg final_d_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_d_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_d_adder_ci_rnd),.i_c_mask(final_d_adder_ci_rnd),.i_rnd(final_d_adder_rnd_in),
.i_op0_mdat(d_mdat[0]), .i_op1_mdat(initial_d[0]),
.i_op0_mask(d_mask[0]), .i_op1_mask(initial_d_mask[0]),
.o_dat_mdat(final_d_adder_out_mdat), .o_dat_mask(final_d_adder_out_mask)
);
wire final_e_adder_out_mdat,final_e_adder_out_mask;
reg final_e_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_e_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_e_adder_ci_rnd),.i_c_mask(final_e_adder_ci_rnd),.i_rnd(final_e_adder_rnd_in),
.i_op0_mdat(e_mdat[0]), .i_op1_mdat(initial_e[0]),
.i_op0_mask(e_mask[0]), .i_op1_mask(initial_e_mask[0]),
.o_dat_mdat(final_e_adder_out_mdat), .o_dat_mask(final_e_adder_out_mask)
);
wire final_f_adder_out_mdat,final_f_adder_out_mask;
reg final_f_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_f_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_f_adder_ci_rnd),.i_c_mask(final_f_adder_ci_rnd),.i_rnd(final_f_adder_rnd_in),
.i_op0_mdat(f_mdat[0]), .i_op1_mdat(initial_f[0]),
.i_op0_mask(f_mask[0]), .i_op1_mask(initial_f_mask[0]),
.o_dat_mdat(final_f_adder_out_mdat), .o_dat_mask(final_f_adder_out_mask)
);
wire final_g_adder_out_mdat,final_g_adder_out_mask;
reg final_g_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_g_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_g_adder_ci_rnd),.i_c_mask(final_g_adder_ci_rnd),.i_rnd(final_g_adder_rnd_in),
.i_op0_mdat(g_mdat[0]), .i_op1_mdat(initial_g[0]),
.i_op0_mask(g_mask[0]), .i_op1_mask(initial_g_mask[0]),
.o_dat_mdat(final_g_adder_out_mdat), .o_dat_mask(final_g_adder_out_mask)
);
wire final_h_adder_out_mdat,final_h_adder_out_mask;
reg final_h_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_h_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_h_adder_ci_rnd),.i_c_mask(final_h_adder_ci_rnd),.i_rnd(final_h_adder_rnd_in),
.i_op0_mdat(h_mdat[0]), .i_op1_mdat(initial_h[0]),
.i_op0_mask(h_mask[0]), .i_op1_mask(initial_h_mask[0]),
.o_dat_mdat(final_h_adder_out_mdat), .o_dat_mask(final_h_adder_out_mask)
);
reg sigma_step;
wire [64-1:0] w15_delta_mask;
sha2_sec_ti2_rm0_xor #(.WIDTH(64)) u_w15_delta_mask_xor_ITK(.a(w15_mask), .b(next_w0_mask), .y(w15_delta_mask));
wire [64-1:0] w15_write_to_w0 = w15_mdat ^ w15_delta_mask;
always @* begin
{
maj_rnd_in,
ch_rnd_in,
ki0_mask_rnd,
w_wi_adder_ci_rnd,t1_adder_ci_rnd,next_e_adder_ci_rnd,t2_adder_ci_rnd,next_a_adder_ci_rnd,
w_wi_adder_rnd_in,t1_adder_rnd_in,next_e_adder_rnd_in,t2_adder_rnd_in,next_a_adder_rnd_in
} = {{64{1'bx}},i_rnd};//x is there to make the sim fail if we have i_rnd too small
{
final_a_adder_ci_rnd,final_b_adder_ci_rnd,final_c_adder_ci_rnd,final_d_adder_ci_rnd,
final_e_adder_ci_rnd,final_f_adder_ci_rnd,final_g_adder_ci_rnd,final_h_adder_ci_rnd,
final_a_adder_rnd_in,final_b_adder_rnd_in,final_c_adder_rnd_in,final_d_adder_rnd_in,
final_e_adder_rnd_in,final_f_adder_rnd_in,final_g_adder_rnd_in,final_h_adder_rnd_in
} = {{64{1'bx}},i_rnd};//x is there to make the sim fail if we have i_rnd too small
end
reg maj_run;
reg ch_run;
always @(posedge i_clk,posedge i_reset) begin: STATE_STAGE
if(i_reset) begin
adders_step <= {7{1'b0}};
state_step <= 0;
{adders_load_in,t1_adder_run,t2_adder_run,next_e_adder_run,adders_run} <= 0;
sigma_step <= 1'b1;
ch_run <= 1'b0;
maj_run <= 1'b0;
final_adders_start <= 1'b1;
end else begin
if(state_update) begin
if(state_step==15) begin
state_step <= step;
w <= {w[0+:15*64],w15_write_to_w0};//let w schedule be 1 step ahead of the state, this way we compute w0 and state can be updated in parallel.
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};
end else if(state_step<step_rounds_max) begin
final_adders_start <= 1'b1;
case({sigma_step,adders_load_in,adders_run})
3'b100: begin
adders_load_in <= 1'b1;
sigma_step <= 1'b0;
t1_adder_sigma1_mdat <= {sigma1_e_mdat[32+:32], i_sha512 ? sigma1_e_mdat[0+:32] : sigma1_e_256_mdat};
t1_adder_sigma1_mask <= {sigma1_e_mask[32+:32], i_sha512 ? sigma1_e_mask[0+:32] : sigma1_e_256_mask};
t2_adder_sigma0_mdat <= {sigma0_a_mdat[32+:32], i_sha512 ? sigma0_a_mdat[0+:32] : sigma0_a_256_mdat};
t2_adder_sigma0_mask <= {sigma0_a_mask[32+:32], i_sha512 ? sigma0_a_mask[0+:32] : sigma0_a_256_mask};
state <= {next_a,next_b,next_c,next_d,next_e,next_f,next_g,next_h};
state_mask <= {next_a_mask,next_b_mask,next_c_mask,next_d_mask,next_e_mask,next_f_mask,next_g_mask,next_h_mask};
end
3'b010: begin
adders_load_in <= 1'b0;
adders_run <= 1'b1;
t1_adder_run <= 1'b1;
adders_step <= 1'b1;
w_wi_adder_run <= 1'b1;
//t1 operands
if(i_sha512) begin
ki <= k[(state_step-16)*64+:64];
end else begin
ki <= k_256[(state_step-16)*32+:32];
end
//wi_adder operands
gamma1_out_mdat <= i_sha512 ? gamma1_mdat : {{32{1'bx}},gamma1_256_mdat};
gamma1_out_mask <= i_sha512 ? gamma1_mask : {{32{1'bx}},gamma1_256_mask};
gamma0_out_mdat <= i_sha512 ? gamma0_mdat : {{32{1'bx}},gamma0_256_mdat};
gamma0_out_mask <= i_sha512 ? gamma0_mask : {{32{1'bx}},gamma0_256_mask};
ch_run <= 1'b1;
{state[F_IDX*64+:64],state_mask[F_IDX*64+:64]} <= rr_state_word(F_IDX);
{state[G_IDX*64+:64],state_mask[G_IDX*64+:64]} <= rr_state_word(G_IDX);
{state[H_IDX*64+:64],state_mask[H_IDX*64+:64]} <= rr_state_word(H_IDX);
end
3'b001: begin
if(next_a_adder_stop) begin
adders_run <= 1'b0;
adders_step <= {7{1'b0}};
state_step <= step;
sigma_step <= 1'b1;
end else adders_step <= adders_step + 1'b1;
if(ch_stop) ch_run <= 1'b0;
if(maj_start) maj_run <= 1'b1;
else if(maj_stop) maj_run <= 1'b0;
if(t1_adder_stop) t1_adder_run <= 1'b0;
if(w_wi_adder_stop) w_wi_adder_run <= 1'b0;
if(t2_adder_start) t2_adder_run <= 1'b1;
else if(t2_adder_stop) t2_adder_run <= 1'b0;
if(next_e_adder_start) next_e_adder_run <= 1'b1;
else if(next_e_adder_stop) next_e_adder_run <= 1'b0;
if(t1_adder_run) begin//t1 operands, w_wi operands
ki <= rr_word(ki);
t1_adder_sigma1_mdat <= rr_word(t1_adder_sigma1_mdat);
t1_adder_sigma1_mask <= rr_word(t1_adder_sigma1_mask);
w[0*64+:64] <= rr_word(w0_mdat);
w0_mask <= rr_word(w0_mask);
//w_wi operands
w[( 7-1)*64+:64] <= rr_word(w6_mdat);
w6_mask <= rr_word(w6_mask);
w[(16-1)*64+:64] <= rr_word(w15_mdat);
w15_mask <= rr_word(w15_mask);
gamma0_out_mdat <= rr_word(gamma0_out_mdat);
gamma0_out_mask <= rr_word(gamma0_out_mask);
gamma1_out_mdat <= rr_word(gamma1_out_mdat);
gamma1_out_mask <= rr_word(gamma1_out_mask);
end else begin
if(next_a_adder_stop) begin
if(state_step<32-1) w <= {w[0+:15*64],w15_write_to_w0};
else w <= {w[0+:15*64],w_wi_write_to_w0};
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};
end
end
if(w_wi_adder_run) begin
//w_wi out
w_wi_out_mdat <= sr_word(w_wi_out_mdat,w_wi_adder_out_mdat);
w_wi_out_mask <= sr_word(w_wi_out_mask,w_wi_adder_out_mask);
end
if(t1_adder_run | next_a_adder_run) begin//t1 operand / next_a out
state [A_IDX*64+:64] <= sr_word(a_mdat,next_a_adder_out_mdat);//h operand is stored in state[7*64+:64]
state_mask[A_IDX*64+:64] <= sr_word(a_mask,next_a_adder_out_mask);//h operand is stored in state[7*64+:64]
end
//t2 operands
if(t2_adder_start|t2_adder_run) begin
t2_adder_sigma0_mdat <= rr_word(t2_adder_sigma0_mdat);
t2_adder_sigma0_mask <= rr_word(t2_adder_sigma0_mask);
end
//next_e operand
if(next_e_adder_start | next_e_adder_run) begin
state [E_IDX*64+:64] <= sr_word(e_mdat,next_e_adder_out_mdat);//d operand is stored in state[3*64+:64]
state_mask[E_IDX*64+:64] <= sr_word(e_mask,next_e_adder_out_mask);//d operand is stored in state[3*64+:64]
end
if(ch_run) begin
{state[F_IDX*64+:64],state_mask[F_IDX*64+:64]} <= rr_state_word(F_IDX);
{state[G_IDX*64+:64],state_mask[G_IDX*64+:64]} <= rr_state_word(G_IDX);
{state[H_IDX*64+:64],state_mask[H_IDX*64+:64]} <= rr_state_word(H_IDX);
end
if(maj_run) begin
{state[B_IDX*64+:64],state_mask[B_IDX*64+:64]} <= rr_state_word(B_IDX);
{state[C_IDX*64+:64],state_mask[C_IDX*64+:64]} <= rr_state_word(C_IDX);
{state[D_IDX*64+:64],state_mask[D_IDX*64+:64]} <= rr_state_word(D_IDX);
end
end
endcase
initial_state_mask <= initial_state_mask_seed;
end else if(state_step<step_max) begin
w <= {w[0+:15*64],initial_state_mask};
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};//we don't use mask anymore, but still generate them to hide our activities
initial_state_mask <= next_initial_state_mask;
state_step <= step;
end else begin
final_adders_start <= 1'b0;
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};//we don't use mask anymore, but still generate them to hide our activities
state <= {
sr_word(a_mdat,final_a_adder_out_mdat),
sr_word(b_mdat,final_b_adder_out_mdat),
sr_word(c_mdat,final_c_adder_out_mdat),
sr_word(d_mdat,final_d_adder_out_mdat),
sr_word(e_mdat,final_e_adder_out_mdat),
sr_word(f_mdat,final_f_adder_out_mdat),
sr_word(g_mdat,final_g_adder_out_mdat),
sr_word(h_mdat,final_h_adder_out_mdat)
};
state_mask <= {
sr_word(a_mask,final_a_adder_out_mask),
sr_word(b_mask,final_b_adder_out_mask),
sr_word(c_mask,final_c_adder_out_mask),
sr_word(d_mask,final_d_adder_out_mask),
sr_word(e_mask,final_e_adder_out_mask),
sr_word(f_mask,final_f_adder_out_mask),
sr_word(g_mask,final_g_adder_out_mask),
sr_word(h_mask,final_h_adder_out_mask)
};
initial_state <= {
rr_word(initial_a),
rr_word(initial_b),
rr_word(initial_c),
rr_word(initial_d),
rr_word(initial_e),
rr_word(initial_f),
rr_word(initial_g),
rr_word(initial_h)
};
w <= { w[8*64+:8*64],
rr_word(w[7*64+:64]),
rr_word(w[6*64+:64]),
rr_word(w[5*64+:64]),
rr_word(w[4*64+:64]),
rr_word(w[3*64+:64]),
rr_word(w[2*64+:64]),
rr_word(w[1*64+:64]),
rr_word(w[0*64+:64])
};
if(adders_step==adders_width-1) begin
adders_step <= {7{1'b0}};
state_step <= step;
end else adders_step <= adders_step + 1'b1;
end
end else begin
adders_step <= {7{1'b0}};
if(i_write_state) begin
state <= {state[0+:7*64],i_dat_mdat^i_rnd[0+:64]};
state_mask <= {state_mask[0+:7*64],i_dat_mask^i_rnd[0+:64]};
end else if(i_read) begin
state <= {state[0+:7*64],state[7*64+:64]};
state_mask <= {state_mask[0+:7*64],state_mask[7*64+:64]};
end
if(i_write) begin
w <= {w[0+:15*64],i_dat_write_to_w0};
w0_mask <= next_w0_mask;
if(step>=1) w1_mask <= next_w1_mask;
if(step>=6) w6_mask <= next_w6_mask;
if(step>=14) w14_mask <= next_w14_mask;
if(step>=15) w15_mask <= next_w15_mask;
if(step[3]) begin//copy state to initial_state during the load of the last 8 words of the message
initial_state <= {initial_state[0+:7*64],initial_state_write_mdat};
initial_state_mask <= next_initial_state_mask;
state <= {state[0+:7*64],state[7*64+:64]};
state_mask <= {state_mask[0+:7*64],state_mask[7*64+:64]};
end
end
if(i_init_mask) begin
w0_mask <= i_rnd;
w1_mask <= i_rnd;
w6_mask <= i_rnd;
w14_mask <= i_rnd;
w15_mask <= i_rnd;
initial_state_mask_seed <= w0_mask;
initial_state_mask <= w0_mask;
end
state_step <= step;
end
end
end
wire [64-1:0] _dbg_i_dat = i_dat_mdat ^ i_dat_mask;
wire [64-1:0] _dbg_o_dat = o_dat_mdat ^ o_dat_mask;
wire [64-1:0] _dbg_w0 = w0_mdat ^ w0_mask;
wire [64-1:0] _dbg_w1 = w1_mdat ^ w1_mask;
wire [64-1:0] _dbg_w6 = w6_mdat ^ w6_mask;
wire [64-1:0] _dbg_w14 = w14_mdat ^ w14_mask;
wire [64-1:0] _dbg_w15 = w15_mdat ^ w15_mask;
wire _dbg_next_a_adder_out = next_a_adder_out_mdat ^ next_a_adder_out_mask;
wire _dbg_next_e_adder_out = next_e_adder_out_mdat ^ next_e_adder_out_mask;
wire _dbg_t1_adder_out = t1_adder_out_mdat ^ t1_adder_out_mask;
wire _dbg_t2_adder_out = t2_adder_out_mdat ^ t2_adder_out_mask;
wire [64-1:0] _dbg_a = a_mdat ^ a_mask;
wire [64-1:0] _dbg_b = b_mdat ^ b_mask;
wire [64-1:0] _dbg_c = c_mdat ^ c_mask;
wire [64-1:0] _dbg_d = d_mdat ^ d_mask;
wire [64-1:0] _dbg_e = e_mdat ^ e_mask;
wire [64-1:0] _dbg_f = f_mdat ^ f_mask;
wire [64-1:0] _dbg_g = g_mdat ^ g_mask;
wire [64-1:0] _dbg_h = h_mdat ^ h_mask;
wire [8*64-1:0] _dbg_initial_state_final_add = initial_state ^ w[0+:8*64];
wire [64-1:0] _dbg_initial_state_final_add_a = initial_a ^ initial_a_mask;
wire [64-1:0] _dbg_initial_state_final_add_b = initial_b ^ initial_b_mask;
wire [64-1:0] _dbg_initial_state_final_add_c = initial_c ^ initial_c_mask;
wire [64-1:0] _dbg_initial_state_final_add_d = initial_d ^ initial_d_mask;
wire [64-1:0] _dbg_initial_state_final_add_e = initial_e ^ initial_e_mask;
wire [64-1:0] _dbg_initial_state_final_add_f = initial_f ^ initial_f_mask;
wire [64-1:0] _dbg_initial_state_final_add_g = initial_g ^ initial_g_mask;
wire [64-1:0] _dbg_initial_state_final_add_h = initial_h ^ initial_h_mask;
reg [8*64-1:0] _dbg_initial_state;
reg [64-1:0] _dbg_initial_state_mask;
always @* begin: DGB_INITIAL_STATE
integer i;
_dbg_initial_state_mask = initial_state_mask_seed;
for(i=0;i<8;i=i+1) begin
_dbg_initial_state[(7-i)*64+:64] = initial_state[(7-i)*64+:64] ^ _dbg_initial_state_mask;
_dbg_initial_state_mask = func_next_initial_state_mask(_dbg_initial_state_mask);
end
end
reg [16*64-1:0] _dbg_w;
reg [64-1:0] _dbg_w_mask;
always @* begin: DGB_W
integer i;
_dbg_w_mask = w15_mask;
for(i=0;i<16;i=i+1) begin
_dbg_w[(15-i)*64+:64] = w[(15-i)*64+:64] ^ _dbg_w_mask;
_dbg_w_mask = func_next_wi_mask(_dbg_w_mask);
end
end
wire [64-1:0] _dbg_w0_ref = _dbg_w[0*64+:64];
wire [64-1:0] _dbg_w1_ref = _dbg_w[1*64+:64];
wire [64-1:0] _dbg_w2 = _dbg_w[2*64+:64];
wire [64-1:0] _dbg_w3 = _dbg_w[3*64+:64];
wire [64-1:0] _dbg_w4 = _dbg_w[4*64+:64];
wire [64-1:0] _dbg_w5 = _dbg_w[5*64+:64];
wire [64-1:0] _dbg_w6_ref = _dbg_w[6*64+:64];
wire [64-1:0] _dbg_w7 = _dbg_w[7*64+:64];
wire [64-1:0] _dbg_w8 = _dbg_w[8*64+:64];
wire [64-1:0] _dbg_w9 = _dbg_w[9*64+:64];
wire [64-1:0] _dbg_w10 = _dbg_w[10*64+:64];
wire [64-1:0] _dbg_w11 = _dbg_w[11*64+:64];
wire [64-1:0] _dbg_w12 = _dbg_w[12*64+:64];
wire [64-1:0] _dbg_w13 = _dbg_w[13*64+:64];
wire [64-1:0] _dbg_w14_ref = _dbg_w[14*64+:64];
wire [64-1:0] _dbg_w15_ref = _dbg_w[15*64+:64];
wire _dbg_w0_check = _dbg_w0_ref === _dbg_w0;
wire _dbg_w1_check = _dbg_w1_ref === _dbg_w1;
wire _dbg_w6_check = _dbg_w6_ref === _dbg_w6;
wire _dbg_w14_check = _dbg_w14_ref === _dbg_w14;
wire _dbg_w15_check = _dbg_w15_ref === _dbg_w15;
wire _dbg_final_a_adder_ina = a_mdat[0] ^ a_mask[0];
wire _dbg_final_a_adder_inb = initial_a[0] ^ initial_a_mask[0];
wire _dbg_final_a_adder_out = final_a_adder_out_mdat ^ final_a_adder_out_mask;
wire _dbg_final_b_adder_out = final_b_adder_out_mdat ^ final_b_adder_out_mask;
wire _dbg_final_c_adder_out = final_c_adder_out_mdat ^ final_c_adder_out_mask;
wire _dbg_final_d_adder_out = final_d_adder_out_mdat ^ final_d_adder_out_mask;
wire _dbg_final_e_adder_out = final_e_adder_out_mdat ^ final_e_adder_out_mask;
wire _dbg_final_f_adder_out = final_f_adder_out_mdat ^ final_f_adder_out_mask;
wire _dbg_final_g_adder_out = final_g_adder_out_mdat ^ final_g_adder_out_mask;
wire _dbg_final_h_adder_out = final_h_adder_out_mdat ^ final_h_adder_out_mask;
wire [31:0] _dbg_sigma1_256_e = sigma1_e_256_mdat ^ sigma1_e_256_mask;
wire [64-1:0] _dbg_sigma1_e = sigma1_e_mdat ^ sigma1_e_mask;
wire [64-1:0] _dbg_gamma1_out = gamma1_out_mdat ^ gamma1_out_mask;
wire [64-1:0] _dbg_gamma0_out = gamma0_out_mdat ^ gamma0_out_mask;
wire [64-1:0] _dbg_sigma0_a = sigma0_a_mdat ^ sigma0_a_mask;
wire [64-1:0] _dbg_t1_adder_sigma1 = t1_adder_sigma1_mdat ^ t1_adder_sigma1_mask;
wire _dbg_ch_out = ch_out_mdat ^ ch_out_mask;
wire _dbg_serial_maj = serial_maj_mdat ^ serial_maj_mask;
wire _dbg_maj = serial_maj_mdat ^ serial_maj_mask;
wire [64-1:0] _dbg_t2_adder_sigma0 = t2_adder_sigma0_mdat ^ t2_adder_sigma0_mask;
reg [64-1:0] _dbg_t1;
always @(posedge i_clk) begin
if(t1_adder_start) _dbg_t1 <= {64{1'b0}};
else _dbg_t1 <= {_dbg_t1_adder_out,_dbg_t1[1+:64-1]};
end
reg [64-1:0] _dbg_next_e;
always @(posedge i_clk) begin
if(next_e_adder_start) _dbg_next_e <= {64{1'b0}};
else _dbg_next_e <= {_dbg_next_e_adder_out,_dbg_next_e[1+:64-1]};
end
reg [64-1:0] _dbg_t2;
always @(posedge i_clk) begin
if(t2_adder_start) _dbg_t2 <= {64{1'b0}};
else _dbg_t2 <= {_dbg_t2_adder_out,_dbg_t2[1+:64-1]};
end
reg [64-1:0] _dbg_next_a;
always @(posedge i_clk) begin
if(next_a_adder_start) _dbg_next_a <= {64{1'b0}};
else _dbg_next_a <= {_dbg_next_a_adder_out,_dbg_next_a[1+:64-1]};
end
endmodule |
module sha2_sec_ti2_rm0_masked_maj #(
parameter WIDTH = 1
)(
input wire i_clk,
input wire [3*2*WIDTH-1:0] i_rnd,
input wire [WIDTH-1:0] i_x_mdat,
input wire [WIDTH-1:0] i_x_mask,
input wire [WIDTH-1:0] i_y_mdat,
input wire [WIDTH-1:0] i_y_mask,
input wire [WIDTH-1:0] i_z_mdat,//all inputs must be stable during computation (2 cycles)
input wire [WIDTH-1:0] i_z_mask,
output reg [WIDTH-1:0] o_mdat,
output reg [WIDTH-1:0] o_mask
);
wire [WIDTH-1:0] x0 = i_x_mask;
wire [WIDTH-1:0] x1 = i_x_mdat;
wire [WIDTH-1:0] y0 = i_y_mask;
wire [WIDTH-1:0] y1 = i_y_mdat;
wire [WIDTH-1:0] z0 = i_z_mask;
wire [WIDTH-1:0] z1 = i_z_mdat;
wire [WIDTH-1:0] xy_out0;
wire [WIDTH-1:0] xy_out1;
wire [WIDTH-1:0] xz_out0;
wire [WIDTH-1:0] xz_out1;
wire [WIDTH-1:0] yz_out0;
wire [WIDTH-1:0] yz_out1;
genvar i;
generate
for(i=0;i<WIDTH;i=i+1) begin: BIT
wire [1:0] xi = {x1[i],x0[i]};
wire [1:0] yi = {y1[i],y0[i]};
wire [1:0] zi = {z1[i],z0[i]};
sha2_sec_ti2_rm0_ti2_and u_xy(
.i_clk(i_clk),.i_rnd(i_rnd[i*2+:2]),
.i_a(xi),
.i_b(yi),
.o_y({xy_out1[i],xy_out0[i]}));
sha2_sec_ti2_rm0_ti2_and u_xz(
.i_clk(i_clk),.i_rnd(i_rnd[2*WIDTH+i*2+:2]),
.i_a(xi),
.i_b(zi),
.o_y({xz_out1[i],xz_out0[i]}));
sha2_sec_ti2_rm0_ti2_and u_yz(
.i_clk(i_clk),.i_rnd(i_rnd[4*WIDTH+i*2+:2]),
.i_a(zi),
.i_b(yi),
.o_y({yz_out1[i],yz_out0[i]}));
end
endgenerate
always @* begin
o_mdat = xy_out0 ^ xz_out0 ^ yz_out0;
o_mask = xy_out1 ^ xz_out1 ^ yz_out1;
end
endmodule |
module sha2_sec_ti2_rm0_serial_masked_ch(
input wire i_clk,
input wire [2-1:0] i_rnd,
input wire i_x_mdat,
input wire i_x_mask,
input wire i_y_mdat,
input wire i_y_mask,
input wire i_z_mdat,
input wire i_z_mask,
output reg o_mdat,
output reg o_mask
);
//ch_256 = z ^ (x & (y ^ z));
reg z_mdat_l1;
reg z_mask_l1;
wire temp0 = i_y_mdat ^ i_z_mdat;
wire temp1 = i_y_mask ^ i_z_mask;
wire x0 = i_x_mask;
wire x1 = i_x_mdat;
always @(posedge i_clk) {z_mdat_l1,z_mask_l1} <= {i_z_mdat,i_z_mask};
wire and_out0;
wire and_out1;
sha2_sec_ti2_rm0_ti2_and u(
.i_clk(i_clk),.i_rnd(i_rnd),
.i_a({x1,x0}),
.i_b({temp1,temp0}),
.o_y({and_out1,and_out0}));
always @* begin
o_mdat = and_out0 ^ z_mdat_l1;
o_mask = and_out1 ^ z_mask_l1;
end
endmodule |
module sha2_sec_ti2_rm0_serial_masked_add_5op (
input wire i_clk,
input wire i_start,
input wire [16-1:0] i_rnd,
input wire [3:0] i_c_mdat,
input wire [3:0] i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op2_mdat,
input wire i_op3_mdat,
input wire i_op4_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
input wire i_op2_mask,
input wire i_op3_mask,
input wire i_op4_mask,
output reg o_dat_mdat,
output reg o_dat_mask
);
wire [1:0] op0 = {i_op0_mask,i_op0_mdat};
wire [1:0] op1 = {i_op1_mask,i_op1_mdat};
wire [1:0] op2 = {i_op2_mask,i_op2_mdat};
wire [1:0] op3 = {i_op3_mask,i_op3_mdat};
wire [1:0] op4 = {i_op4_mask,i_op4_mdat};
wire [1:0] c0 = {i_c_mask[0],i_c_mdat[0]};
wire [1:0] c1 = {i_c_mask[1],i_c_mdat[1]};
wire [1:0] c2 = {i_c_mask[2],i_c_mdat[2]};
wire [1:0] c3 = {i_c_mask[3],i_c_mdat[3]};
reg [2-1:0] op4_l1,op4_l2;
reg start_l1,start_l2;
always @(posedge i_clk) begin
op4_l1 <= op4;
op4_l2 <= op4_l1;
start_l1 <= i_start;
start_l2 <= start_l1;
end
wire [2-1:0] q01,co01;
wire [2-1:0] ci01 = i_start ? c0 : co01;
sha2_sec_ti2_rm0_masked_full_adder_ti add01(
.i_clk(i_clk),.i_rnd(i_rnd[0*4+:4]),
.i_a(op0),.i_b(op1),.i_c(ci01),
.o_q(q01), .o_c(co01));
wire [2-1:0] q23,co23;
wire [2-1:0] ci23 = i_start ? c1 : co23;
sha2_sec_ti2_rm0_masked_full_adder_ti add23(
.i_clk(i_clk),.i_rnd(i_rnd[1*4+:4]),
.i_a(op2),.i_b(op3),.i_c(ci23),
.o_q(q23), .o_c(co23));
wire [2-1:0] q03,co03;
wire [2-1:0] ci03 = start_l1 ? c2 : co03;
sha2_sec_ti2_rm0_masked_full_adder_ti add03(
.i_clk(i_clk),.i_rnd(i_rnd[2*4+:4]),
.i_a(q01),.i_b(q23),.i_c(ci03),
.o_q(q03), .o_c(co03));
wire [2-1:0] q04,co04;
wire [2-1:0] ci04 = start_l2 ? c3 : co04;
sha2_sec_ti2_rm0_masked_full_adder_ti add04(
.i_clk(i_clk),.i_rnd(i_rnd[3*4+:4]),
.i_a(op4_l2),.i_b(q03),.i_c(ci04),
.o_q(q04), .o_c(co04));
always @* begin
o_dat_mdat = q04[0];
o_dat_mask = q04[1];
end
endmodule |
module sha2_sec_ti2_rm0_serial_masked_add_4op (
input wire i_clk,
input wire i_start,
input wire [12-1:0] i_rnd,
input wire [2:0] i_c_mdat,
input wire [2:0] i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op2_mdat,
input wire i_op3_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
input wire i_op2_mask,
input wire i_op3_mask,
output reg o_dat_mdat,
output reg o_dat_mask
);
wire [1:0] op0 = {i_op0_mask,i_op0_mdat};
wire [1:0] op1 = {i_op1_mask,i_op1_mdat};
wire [1:0] op2 = {i_op2_mask,i_op2_mdat};
wire [1:0] op3 = {i_op3_mask,i_op3_mdat};
wire [1:0] c0 = {i_c_mask[0],i_c_mdat[0]};
wire [1:0] c1 = {i_c_mask[1],i_c_mdat[1]};
wire [1:0] c2 = {i_c_mask[2],i_c_mdat[2]};
reg start_l1;
always @(posedge i_clk) begin
start_l1 <= i_start;
end
wire [2-1:0] q01,co01;
wire [2-1:0] ci01 = i_start ? c0 : co01;
sha2_sec_ti2_rm0_masked_full_adder_ti add01(
.i_clk(i_clk),.i_rnd(i_rnd[0*4+:4]),
.i_a(op0),.i_b(op1),.i_c(ci01),
.o_q(q01), .o_c(co01));
wire [2-1:0] q23,co23;
wire [2-1:0] ci23 = i_start ? c1 : co23;
sha2_sec_ti2_rm0_masked_full_adder_ti add23(
.i_clk(i_clk),.i_rnd(i_rnd[1*4+:4]),
.i_a(op2),.i_b(op3),.i_c(ci23),
.o_q(q23), .o_c(co23));
wire [2-1:0] q03,co03;
wire [2-1:0] ci03 = start_l1 ? c2 : co03;
sha2_sec_ti2_rm0_masked_full_adder_ti add03(
.i_clk(i_clk),.i_rnd(i_rnd[2*4+:4]),
.i_a(q01),.i_b(q23),.i_c(ci03),
.o_q(q03), .o_c(co03));
always @* begin
o_dat_mdat = q03[0];
o_dat_mask = q03[1];
end
endmodule |
module sha2_sec_ti2_rm0_serial_masked_add_2op (
input wire i_clk,
input wire i_start,
input wire [4-1:0] i_rnd,
input wire i_c_mdat,
input wire i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
output reg o_dat_mdat,
output reg o_dat_mask
);
wire [1:0] a = {i_op0_mask,i_op0_mdat};
wire [1:0] b = {i_op1_mask,i_op1_mdat};
wire [1:0] c = {i_c_mask,i_c_mdat};
wire [2-1:0] q,co;
wire [2-1:0] ci = i_start ? c : co;
sha2_sec_ti2_rm0_masked_full_adder_ti impl(
.i_clk(i_clk),.i_rnd(i_rnd[3:0]),
.i_a(a),.i_b(b),.i_c(ci),
.o_q(q), .o_c(co));
always @* begin
o_dat_mdat = q[0];
o_dat_mask = q[1];
end
endmodule |
module sha2_sec_ti2_rm0_masked_full_adder_ti(
input wire i_clk,
input wire [2-1:0] i_a,
input wire [2-1:0] i_b,
input wire [2-1:0] i_c,
input wire [3:0] i_rnd,
output reg [2-1:0] o_q,
output reg [2-1:0] o_c
);
wire [2-1:0] x0 = i_a ^ i_b;
wire [2-1:0] n0,n1;
sha2_sec_ti2_rm0_ti2_and u0(.i_clk(i_clk), .i_a(x0), .i_b(i_c), .i_rnd(i_rnd[0+:2]), .o_y(n0));
sha2_sec_ti2_rm0_ti2_and u1(.i_clk(i_clk), .i_a(i_a), .i_b(i_b), .i_rnd(i_rnd[2+:2]), .o_y(n1));
reg [2-1:0] x0_l1;
always @(posedge i_clk) x0_l1 <= x0;
reg [2-1:0] c_l1;
always @(posedge i_clk) c_l1 <= i_c;
always @* begin
o_q = x0_l1 ^ c_l1;
o_c = n0 ^ n1;
end
endmodule |
module sha2_sec_ti2_rm0_remask(
input wire [1:0] a,
input wire r,
output wire [1:0] y
);
sha2_sec_ti2_rm0_xor u0(.a(a[0]), .b(r), .y(y[0]));
sha2_sec_ti2_rm0_xor u1(.a(a[1]), .b(r), .y(y[1]));
endmodule |
module sha2_sec_ti2_rm0_xor_impl #(
parameter WIDTH = 1,
parameter NOTY = 0
)(
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output reg [WIDTH-1:0] y
);
always @* y = NOTY ^ a ^ b;
endmodule |
module sha2_sec_ti2_rm0_xor #(
parameter WIDTH = 1
)(
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output wire [WIDTH-1:0] y
);
sha2_sec_ti2_rm0_xor_impl #(.WIDTH(WIDTH)) u_ITK(.a(a), .b(b), .y(y));
endmodule |
module sha2_sec_ti2_rm0_plain_and(
input wire a,
input wire b,
output reg q
);
always @* q = a&b;
endmodule |
module sha2_sec_ti2_rm0_plain_nand(
input wire a,
input wire b,
output reg q
);
always @* q = ~(a&b);
endmodule |
module sha2_sec_ti2_rm0_ti2_and_l0 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
output reg [1:0] o_y //WARNING: non uniform
);
wire [1:0] a = i_a^ NOTA[0];
wire [1:0] b = i_b^ NOTB[0];
wire n00,n10,n01;
wire n11;
sha2_sec_ti2_rm0_plain_nand nand00_ITK(.a(a[0]), .b(b[0]), .q(n00));
sha2_sec_ti2_rm0_plain_nand nand10_ITK(.a(a[1]), .b(b[0]), .q(n10));
sha2_sec_ti2_rm0_plain_nand nand01_ITK(.a(a[0]), .b(b[1]), .q(n01));
sha2_sec_ti2_rm0_plain_nand nand11_ITK(.a(a[1]), .b(b[1]), .q(n11));
always @* begin
o_y[0] = n00 ^ n11 ^ NOTY[0];
o_y[1] = n10 ^ n01;
end
endmodule |
module sha2_sec_ti2_rm0_ti2_and_l1 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire i_clk,
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
input wire [1:0] i_rnd,
output wire [1:0] o_y //SAFE: this is uniform (remasked)
);
wire r0 = i_rnd[0];
wire r1 = i_rnd[1];
wire [1:0] a = i_a^ NOTA[0];
wire [1:0] b = i_b^ NOTB[0];
wire n00,n10,n01,n11;
sha2_sec_ti2_rm0_plain_nand nand00_ITK(.a(a[0]), .b(b[0]), .q(n00));
sha2_sec_ti2_rm0_plain_nand nand10_ITK(.a(a[1]), .b(b[0]), .q(n10));
sha2_sec_ti2_rm0_plain_nand nand01_ITK(.a(a[0]), .b(b[1]), .q(n01));
sha2_sec_ti2_rm0_plain_nand nand11_ITK(.a(a[1]), .b(b[1]), .q(n11));
reg tmp00,tmp01,tmp10,tmp11;
wire next_tmp00,next_tmp01,next_tmp10,next_tmp11;
sha2_sec_ti2_rm0_xor_impl xor00_ITK(.a(n00), .b(r0), .y(next_tmp00));
sha2_sec_ti2_rm0_xor_impl xor01_ITK(.a(n01), .b(r1), .y(next_tmp01));
sha2_sec_ti2_rm0_xor_impl xor10_ITK(.a(n10), .b(r0), .y(next_tmp10));
sha2_sec_ti2_rm0_xor_impl xor11_ITK(.a(n11), .b(r1), .y(next_tmp11));
always @(posedge i_clk) begin
tmp00 <= next_tmp00 ^ NOTY[0];
tmp01 <= next_tmp01;
tmp10 <= next_tmp10;
tmp11 <= next_tmp11;
end
sha2_sec_ti2_rm0_xor_impl u_y0_ITK(.a(tmp00), .b(tmp01), .y(o_y[0]));
sha2_sec_ti2_rm0_xor_impl u_y1_ITK(.a(tmp10), .b(tmp11), .y(o_y[1]));
endmodule |
module sha2_sec_ti2_rm0_ti2_and(
input wire i_clk,
input wire [1:0] i_a,
input wire [1:0] i_b,
input wire [1:0] i_rnd,
output wire[1:0] o_y
);
sha2_sec_ti2_rm0_ti2_and_l1 #(.NOTA(0), .NOTB(0), .NOTY(0)) impl_ITK(.i_clk(i_clk),.i_a(i_a),.i_b(i_b),.i_rnd(i_rnd),.o_y(o_y));
endmodule |
module dcfifo_32in_32out_8kb
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
wr_data_count);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [1:0]wr_data_count;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [7:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [7:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "8" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "32" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "253" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "252" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "8" *)
(* C_RD_DEPTH = "256" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "8" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *)
(* C_WR_DEPTH = "256" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "8" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
dcfifo_32in_32out_8kb_fifo_generator_v12_0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[7:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[7:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule |
module dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_blk_mem_gen_prim_width
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 ;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,\gc0.count_d1_reg[7] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,\gic0.gc0.count_d2_reg[7] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(rd_clk),
.CLKBWRCLK(wr_clk),
.DIADI(din[15:0]),
.DIBDI(din[31:16]),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(dout[15:0]),
.DOBDO(dout[31:16]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(WEBWE),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(Q),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({WEBWE,WEBWE,WEBWE,WEBWE}));
endmodule |
module dcfifo_32in_32out_8kb_blk_mem_gen_top
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_blk_mem_gen_v8_2
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_clk_x_pntrs
(ram_empty_i_reg,
WR_PNTR_RD,
ram_empty_i_reg_0,
RD_PNTR_WR,
ram_full_i,
Q,
\gic0.gc0.count_reg[7] ,
\gic0.gc0.count_d1_reg[7] ,
rst_full_gen_i,
\rd_pntr_bin_reg[0]_0 ,
\gic0.gc0.count_d2_reg[7] ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output ram_empty_i_reg;
output [7:0]WR_PNTR_RD;
output ram_empty_i_reg_0;
output [7:0]RD_PNTR_WR;
output ram_full_i;
input [7:0]Q;
input [5:0]\gic0.gc0.count_reg[7] ;
input [7:0]\gic0.gc0.count_d1_reg[7] ;
input rst_full_gen_i;
input \rd_pntr_bin_reg[0]_0 ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]Q;
wire [7:0]RD_PNTR_WR;
wire [7:0]WR_PNTR_RD;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire [5:0]\gic0.gc0.count_reg[7] ;
wire \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1 ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_5 ;
wire \gsync_stage[2].wr_stg_inst_n_6 ;
wire \gsync_stage[2].wr_stg_inst_n_7 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [6:0]p_0_in;
wire [6:0]p_0_in6_out;
wire [7:7]p_0_out;
wire [7:7]p_1_out;
wire [7:0]p_2_out;
wire [7:0]p_3_out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_full_i;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_4_n_0;
wire ram_full_i_i_6_n_0;
wire ram_full_i_i_7_n_0;
wire rd_clk;
wire \rd_pntr_bin_reg[0]_0 ;
wire [7:0]rd_pntr_gc;
wire \rd_pntr_gc[0]_i_1_n_0 ;
wire \rd_pntr_gc[1]_i_1_n_0 ;
wire \rd_pntr_gc[2]_i_1_n_0 ;
wire \rd_pntr_gc[3]_i_1_n_0 ;
wire \rd_pntr_gc[4]_i_1_n_0 ;
wire \rd_pntr_gc[5]_i_1_n_0 ;
wire \rd_pntr_gc[6]_i_1_n_0 ;
wire rst_full_gen_i;
wire wr_clk;
wire [7:0]wr_pntr_gc;
dcfifo_32in_32out_8kb_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
dcfifo_32in_32out_8kb_synchronizer_ff_0 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.wr_clk(wr_clk));
dcfifo_32in_32out_8kb_synchronizer_ff_1 \gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_1_out),
.rd_clk(rd_clk),
.\wr_pntr_bin_reg[6] (p_0_in));
dcfifo_32in_32out_8kb_synchronizer_ff_2 \gsync_stage[2].wr_stg_inst
(.D(p_2_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.out(p_0_out),
.\rd_pntr_bin_reg[6] ({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 ,\gsync_stage[2].wr_stg_inst_n_5 ,\gsync_stage[2].wr_stg_inst_n_6 ,\gsync_stage[2].wr_stg_inst_n_7 }),
.wr_clk(wr_clk));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_2
(.I0(WR_PNTR_RD[6]),
.I1(Q[6]),
.I2(WR_PNTR_RD[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(WR_PNTR_RD[0]),
.O(ram_empty_i_reg_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_3
(.I0(WR_PNTR_RD[5]),
.I1(Q[5]),
.I2(WR_PNTR_RD[4]),
.I3(Q[4]),
.I4(Q[7]),
.I5(WR_PNTR_RD[7]),
.O(ram_empty_i_reg));
LUT5 #(
.INIT(32'h55554000))
ram_full_i_i_1
(.I0(rst_full_gen_i),
.I1(ram_full_i_i_2_n_0),
.I2(\rd_pntr_bin_reg[0]_0 ),
.I3(ram_full_i_i_4_n_0),
.I4(\gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1 ),
.O(ram_full_i));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2
(.I0(RD_PNTR_WR[5]),
.I1(\gic0.gc0.count_reg[7] [3]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_reg[7] [5]),
.I4(\gic0.gc0.count_reg[7] [4]),
.I5(RD_PNTR_WR[6]),
.O(ram_full_i_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_reg[7] [0]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_reg[7] [1]),
.I4(\gic0.gc0.count_reg[7] [2]),
.I5(RD_PNTR_WR[4]),
.O(ram_full_i_i_4_n_0));
LUT6 #(
.INIT(64'h9009000000000000))
ram_full_i_i_5
(.I0(RD_PNTR_WR[7]),
.I1(\gic0.gc0.count_d1_reg[7] [7]),
.I2(RD_PNTR_WR[6]),
.I3(\gic0.gc0.count_d1_reg[7] [6]),
.I4(ram_full_i_i_6_n_0),
.I5(ram_full_i_i_7_n_0),
.O(\gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1 ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_6
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_d1_reg[7] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_d1_reg[7] [1]),
.I4(\gic0.gc0.count_d1_reg[7] [2]),
.I5(RD_PNTR_WR[2]),
.O(ram_full_i_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_7
(.I0(RD_PNTR_WR[3]),
.I1(\gic0.gc0.count_d1_reg[7] [3]),
.I2(RD_PNTR_WR[4]),
.I3(\gic0.gc0.count_d1_reg[7] [4]),
.I4(\gic0.gc0.count_d1_reg[7] [5]),
.I5(RD_PNTR_WR[5]),
.O(ram_full_i_i_7_n_0));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_out),
.Q(RD_PNTR_WR[7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\rd_pntr_gc[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\rd_pntr_gc[6]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_1_out),
.Q(WR_PNTR_RD[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [0]),
.I1(\gic0.gc0.count_d2_reg[7] [1]),
.O(p_0_in6_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [1]),
.I1(\gic0.gc0.count_d2_reg[7] [2]),
.O(p_0_in6_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [2]),
.I1(\gic0.gc0.count_d2_reg[7] [3]),
.O(p_0_in6_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [3]),
.I1(\gic0.gc0.count_d2_reg[7] [4]),
.O(p_0_in6_out[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [4]),
.I1(\gic0.gc0.count_d2_reg[7] [5]),
.O(p_0_in6_out[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [5]),
.I1(\gic0.gc0.count_d2_reg[7] [6]),
.O(p_0_in6_out[5]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [6]),
.I1(\gic0.gc0.count_d2_reg[7] [7]),
.O(p_0_in6_out[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gic0.gc0.count_d2_reg[7] [7]),
.Q(wr_pntr_gc[7]));
endmodule |
module dcfifo_32in_32out_8kb_fifo_generator_ramfifo
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
wire RD_RST;
wire WR_RST;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.wr_n_1 ;
wire \gntv_or_sync_fifo.gl0.wr_n_8 ;
wire \gwas.wsts/ram_full_i ;
wire [7:0]p_0_out;
wire p_18_out;
wire [7:0]p_1_out;
wire [7:0]p_20_out;
wire [7:0]p_8_out;
wire [7:0]p_9_out;
wire rd_clk;
wire rd_en;
wire [1:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire [7:2]wr_pntr_plus2;
wire [0:0]wr_rst_i;
dcfifo_32in_32out_8kb_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.Q(p_20_out),
.RD_PNTR_WR(p_0_out),
.WR_PNTR_RD(p_1_out),
.\gic0.gc0.count_d1_reg[7] (p_8_out),
.\gic0.gc0.count_d2_reg[7] (p_9_out),
.\gic0.gc0.count_reg[7] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (wr_rst_i),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_i(\gwas.wsts/ram_full_i ),
.rd_clk(rd_clk),
.\rd_pntr_bin_reg[0]_0 (\gntv_or_sync_fifo.gl0.wr_n_1 ),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk));
dcfifo_32in_32out_8kb_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (p_20_out),
.Q(RD_RST),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\wr_pntr_bin_reg[5] (\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.\wr_pntr_bin_reg[6] (\gntv_or_sync_fifo.gcx.clkx_n_9 ));
dcfifo_32in_32out_8kb_wr_logic \gntv_or_sync_fifo.gl0.wr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (p_9_out),
.Q(wr_pntr_plus2),
.RD_PNTR_WR(p_0_out),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_8 ),
.full(full),
.\gic0.gc0.count_d2_reg[7] (p_8_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (WR_RST),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.ram_full_i(\gwas.wsts/ram_full_i ),
.rst_full_ff_i(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
dcfifo_32in_32out_8kb_memory \gntv_or_sync_fifo.mem
(.Q(rd_rst_i[0]),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_8 ),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (p_20_out),
.\gic0.gc0.count_d2_reg[7] (p_9_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
dcfifo_32in_32out_8kb_reset_blk_ramfifo rstblk
(.Q({RD_RST,rd_rst_i}),
.\gic0.gc0.count_reg[0] ({WR_RST,wr_rst_i}),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_fifo_generator_top
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_8kb_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule |
module dcfifo_32in_32out_8kb_fifo_generator_v12_0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [31:0]din;
input wr_en;
input rd_en;
input [7:0]prog_empty_thresh;
input [7:0]prog_empty_thresh_assert;
input [7:0]prog_empty_thresh_negate;
input [7:0]prog_full_thresh;
input [7:0]prog_full_thresh_assert;
input [7:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [31:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [7:0]data_count;
output [7:0]rd_data_count;
output [1:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [7:0]prog_empty_thresh;
wire [7:0]prog_empty_thresh_assert;
wire [7:0]prog_empty_thresh_negate;
wire [7:0]prog_full_thresh;
wire [7:0]prog_full_thresh_assert;
wire [7:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule |
module dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_8kb_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule |
module dcfifo_32in_32out_8kb_memory
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_v8_2 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module dcfifo_32in_32out_8kb_rd_bin_cntr
(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
ram_empty_i_reg,
WR_PNTR_RD,
rd_en,
p_18_out,
\wr_pntr_bin_reg[6] ,
\wr_pntr_bin_reg[5] ,
E,
rd_clk,
Q);
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output ram_empty_i_reg;
input [7:0]WR_PNTR_RD;
input rd_en;
input p_18_out;
input \wr_pntr_bin_reg[6] ;
input \wr_pntr_bin_reg[5] ;
input [0:0]E;
input rd_clk;
input [0:0]Q;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [0:0]Q;
wire [7:0]WR_PNTR_RD;
wire \gc0.count[7]_i_2_n_0 ;
wire p_18_out;
wire [7:0]plusOp;
wire ram_empty_i_i_4_n_0;
wire ram_empty_i_i_5_n_0;
wire ram_empty_i_i_6_n_0;
wire ram_empty_i_i_7_n_0;
wire ram_empty_i_reg;
wire rd_clk;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire \wr_pntr_bin_reg[5] ;
wire \wr_pntr_bin_reg[6] ;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(rd_pntr_plus1[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.I2(rd_pntr_plus1[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[3]_i_1
(.I0(rd_pntr_plus1[3]),
.I1(rd_pntr_plus1[0]),
.I2(rd_pntr_plus1[1]),
.I3(rd_pntr_plus1[2]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[4]_i_1
(.I0(rd_pntr_plus1[4]),
.I1(rd_pntr_plus1[2]),
.I2(rd_pntr_plus1[1]),
.I3(rd_pntr_plus1[0]),
.I4(rd_pntr_plus1[3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(rd_pntr_plus1[5]),
.I1(rd_pntr_plus1[3]),
.I2(rd_pntr_plus1[0]),
.I3(rd_pntr_plus1[1]),
.I4(rd_pntr_plus1[2]),
.I5(rd_pntr_plus1[4]),
.O(plusOp[5]));
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[6]_i_1
(.I0(rd_pntr_plus1[6]),
.I1(rd_pntr_plus1[4]),
.I2(\gc0.count[7]_i_2_n_0 ),
.I3(rd_pntr_plus1[3]),
.I4(rd_pntr_plus1[5]),
.O(plusOp[6]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[7]_i_1
(.I0(rd_pntr_plus1[7]),
.I1(rd_pntr_plus1[5]),
.I2(rd_pntr_plus1[3]),
.I3(\gc0.count[7]_i_2_n_0 ),
.I4(rd_pntr_plus1[4]),
.I5(rd_pntr_plus1[6]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h80))
\gc0.count[7]_i_2
(.I0(rd_pntr_plus1[2]),
.I1(rd_pntr_plus1[1]),
.I2(rd_pntr_plus1[0]),
.O(\gc0.count[7]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(Q),
.Q(rd_pntr_plus1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[1]),
.Q(rd_pntr_plus1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[2]),
.Q(rd_pntr_plus1[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[3]),
.Q(rd_pntr_plus1[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[4]),
.Q(rd_pntr_plus1[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[5]),
.Q(rd_pntr_plus1[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[6]),
.Q(rd_pntr_plus1[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[7]),
.Q(rd_pntr_plus1[7]));
LUT6 #(
.INIT(64'hFF80808080808080))
ram_empty_i_i_1
(.I0(\wr_pntr_bin_reg[6] ),
.I1(\wr_pntr_bin_reg[5] ),
.I2(ram_empty_i_i_4_n_0),
.I3(ram_empty_i_i_5_n_0),
.I4(ram_empty_i_i_6_n_0),
.I5(ram_empty_i_i_7_n_0),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I1(WR_PNTR_RD[2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I3(WR_PNTR_RD[3]),
.O(ram_empty_i_i_4_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_5
(.I0(rd_pntr_plus1[6]),
.I1(WR_PNTR_RD[6]),
.I2(rd_pntr_plus1[7]),
.I3(WR_PNTR_RD[7]),
.I4(WR_PNTR_RD[2]),
.I5(rd_pntr_plus1[2]),
.O(ram_empty_i_i_5_n_0));
LUT6 #(
.INIT(64'h0090000000000090))
ram_empty_i_i_6
(.I0(rd_pntr_plus1[5]),
.I1(WR_PNTR_RD[5]),
.I2(rd_en),
.I3(p_18_out),
.I4(WR_PNTR_RD[4]),
.I5(rd_pntr_plus1[4]),
.O(ram_empty_i_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_7
(.I0(rd_pntr_plus1[3]),
.I1(WR_PNTR_RD[3]),
.I2(rd_pntr_plus1[0]),
.I3(WR_PNTR_RD[0]),
.I4(WR_PNTR_RD[1]),
.I5(rd_pntr_plus1[1]),
.O(ram_empty_i_i_7_n_0));
endmodule |
module dcfifo_32in_32out_8kb_rd_logic
(empty,
p_18_out,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
rd_clk,
Q,
WR_PNTR_RD,
rd_en,
\wr_pntr_bin_reg[6] ,
\wr_pntr_bin_reg[5] );
output empty;
output p_18_out;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
input rd_clk;
input [0:0]Q;
input [7:0]WR_PNTR_RD;
input rd_en;
input \wr_pntr_bin_reg[6] ;
input \wr_pntr_bin_reg[5] ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]Q;
wire [7:0]WR_PNTR_RD;
wire empty;
wire p_14_out;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rpntr_n_8;
wire \wr_pntr_bin_reg[5] ;
wire \wr_pntr_bin_reg[6] ;
dcfifo_32in_32out_8kb_rd_status_flags_as \gras.rsts
(.E(p_14_out),
.Q(Q),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\wr_pntr_bin_reg[6] (rpntr_n_8));
dcfifo_32in_32out_8kb_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.E(p_14_out),
.Q(Q),
.WR_PNTR_RD(WR_PNTR_RD),
.p_18_out(p_18_out),
.ram_empty_i_reg(rpntr_n_8),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\wr_pntr_bin_reg[5] (\wr_pntr_bin_reg[5] ),
.\wr_pntr_bin_reg[6] (\wr_pntr_bin_reg[6] ));
endmodule |
module dcfifo_32in_32out_8kb_rd_status_flags_as
(empty,
p_18_out,
E,
\wr_pntr_bin_reg[6] ,
rd_clk,
Q,
rd_en);
output empty;
output p_18_out;
output [0:0]E;
input \wr_pntr_bin_reg[6] ;
input rd_clk;
input [0:0]Q;
input rd_en;
wire [0:0]E;
wire [0:0]Q;
wire empty;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire \wr_pntr_bin_reg[6] ;
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[7]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\wr_pntr_bin_reg[6] ),
.PRE(Q),
.Q(p_18_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\wr_pntr_bin_reg[6] ),
.PRE(Q),
.Q(empty));
endmodule |
module dcfifo_32in_32out_8kb_reset_blk_ramfifo
(rst_full_ff_i,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_reg[0] ,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_full_ff_i;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]\gic0.gc0.count_reg[0] ;
input wr_clk;
input rst;
input rd_clk;
input p_18_out;
input rd_en;
wire [2:0]Q;
wire [1:0]\gic0.gc0.count_reg[0] ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire rst_rd_reg1;
wire rst_rd_reg2;
wire rst_wr_reg1;
wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
assign rst_full_ff_i = rst_d2;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [1]));
endmodule |
module dcfifo_32in_32out_8kb_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [7:0]D;
input [7:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]Q;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[7:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
endmodule |
module dcfifo_32in_32out_8kb_synchronizer_ff_0
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [7:0]D;
input [7:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]Q;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign D[7:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[7]),
.Q(Q_reg[7]));
endmodule |
module dcfifo_32in_32out_8kb_synchronizer_ff_1
(out,
\wr_pntr_bin_reg[6] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [6:0]\wr_pntr_bin_reg[6] ;
input [7:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]D;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
wire [6:0]\wr_pntr_bin_reg[6] ;
assign out[0] = Q_reg[7];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[0]),
.I3(\wr_pntr_bin_reg[6] [3]),
.O(\wr_pntr_bin_reg[6] [0]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(\wr_pntr_bin_reg[6] [3]),
.O(\wr_pntr_bin_reg[6] [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[7]),
.I2(Q_reg[5]),
.I3(Q_reg[6]),
.I4(Q_reg[4]),
.I5(Q_reg[2]),
.O(\wr_pntr_bin_reg[6] [2]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[6]),
.I2(Q_reg[5]),
.I3(Q_reg[7]),
.I4(Q_reg[3]),
.O(\wr_pntr_bin_reg[6] [3]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[4]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[4]),
.O(\wr_pntr_bin_reg[6] [4]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[5]),
.I2(Q_reg[7]),
.O(\wr_pntr_bin_reg[6] [5]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[6]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[7]),
.O(\wr_pntr_bin_reg[6] [6]));
endmodule |
module dcfifo_32in_32out_8kb_synchronizer_ff_2
(out,
\rd_pntr_bin_reg[6] ,
D,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [6:0]\rd_pntr_bin_reg[6] ;
input [7:0]D;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]D;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [6:0]\rd_pntr_bin_reg[6] ;
wire wr_clk;
assign out[0] = Q_reg[7];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[7]),
.Q(Q_reg[7]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[0]),
.I3(\rd_pntr_bin_reg[6] [3]),
.O(\rd_pntr_bin_reg[6] [0]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(\rd_pntr_bin_reg[6] [3]),
.O(\rd_pntr_bin_reg[6] [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[7]),
.I2(Q_reg[5]),
.I3(Q_reg[6]),
.I4(Q_reg[4]),
.I5(Q_reg[2]),
.O(\rd_pntr_bin_reg[6] [2]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[6]),
.I2(Q_reg[5]),
.I3(Q_reg[7]),
.I4(Q_reg[3]),
.O(\rd_pntr_bin_reg[6] [3]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[4]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[4]),
.O(\rd_pntr_bin_reg[6] [4]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[5]),
.I2(Q_reg[7]),
.O(\rd_pntr_bin_reg[6] [5]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[6]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[7]),
.O(\rd_pntr_bin_reg[6] [6]));
endmodule |
module dcfifo_32in_32out_8kb_wr_bin_cntr
(ram_full_fb_i_reg,
\wr_data_count_i_reg[7] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
S,
Q,
\gic0.gc0.count_d2_reg[7]_0 ,
RD_PNTR_WR,
wr_en,
p_1_out,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output ram_full_fb_i_reg;
output [3:0]\wr_data_count_i_reg[7] ;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output [3:0]S;
output [5:0]Q;
output [7:0]\gic0.gc0.count_d2_reg[7]_0 ;
input [7:0]RD_PNTR_WR;
input wr_en;
input p_1_out;
input [0:0]E;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [5:0]Q;
wire [7:0]RD_PNTR_WR;
wire [3:0]S;
wire \gic0.gc0.count[7]_i_2_n_0 ;
wire [7:0]\gic0.gc0.count_d2_reg[7]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire p_1_out;
wire [7:0]plusOp__0;
wire ram_full_fb_i_reg;
wire wr_clk;
wire [3:0]\wr_data_count_i_reg[7] ;
wire wr_en;
wire [1:0]wr_pntr_plus2;
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(Q[0]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(Q[0]),
.I3(Q[1]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(Q[0]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[1]),
.I3(Q[1]),
.I4(Q[2]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(Q[1]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[0]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[3]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[7]_i_2_n_0 ),
.I1(Q[4]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[7]_i_2_n_0 ),
.I1(Q[4]),
.I2(Q[5]),
.O(plusOp__0[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\gic0.gc0.count[7]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[0]),
.I4(Q[0]),
.I5(Q[2]),
.O(\gic0.gc0.count[7]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(\gic0.gc0.count_d2_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[1]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[0]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[4]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[5]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[2]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[3]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[4]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[5]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[6]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[7]),
.Q(Q[5]));
LUT6 #(
.INIT(64'h0090000000000090))
ram_full_i_i_3
(.I0(RD_PNTR_WR[0]),
.I1(wr_pntr_plus2[0]),
.I2(wr_en),
.I3(p_1_out),
.I4(wr_pntr_plus2[1]),
.I5(RD_PNTR_WR[1]),
.O(ram_full_fb_i_reg));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_10
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_8
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_9
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
endmodule |
module dcfifo_32in_32out_8kb_wr_dc_as
(wr_data_count,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
\gic0.gc0.count_d2_reg[6] ,
S,
\gic0.gc0.count_d2_reg[7] );
output [1:0]wr_data_count;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [6:0]\gic0.gc0.count_d2_reg[6] ;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [3:0]S;
wire [6:0]\gic0.gc0.count_d2_reg[6] ;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [7:0]minusOp;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire wr_clk;
wire [1:0]wr_data_count;
wire \wr_data_count_i_reg[7]_i_1_n_1 ;
wire \wr_data_count_i_reg[7]_i_1_n_2 ;
wire \wr_data_count_i_reg[7]_i_1_n_3 ;
wire \wr_data_count_i_reg[7]_i_2_n_0 ;
wire \wr_data_count_i_reg[7]_i_2_n_1 ;
wire \wr_data_count_i_reg[7]_i_2_n_2 ;
wire \wr_data_count_i_reg[7]_i_2_n_3 ;
wire [3:3]\NLW_wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(minusOp[6]),
.Q(wr_data_count[0]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(minusOp[7]),
.Q(wr_data_count[1]));
CARRY4 \wr_data_count_i_reg[7]_i_1
(.CI(\wr_data_count_i_reg[7]_i_2_n_0 ),
.CO({\NLW_wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED [3],\wr_data_count_i_reg[7]_i_1_n_1 ,\wr_data_count_i_reg[7]_i_1_n_2 ,\wr_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\gic0.gc0.count_d2_reg[6] [6:4]}),
.O(minusOp[7:4]),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 \wr_data_count_i_reg[7]_i_2
(.CI(1'b0),
.CO({\wr_data_count_i_reg[7]_i_2_n_0 ,\wr_data_count_i_reg[7]_i_2_n_1 ,\wr_data_count_i_reg[7]_i_2_n_2 ,\wr_data_count_i_reg[7]_i_2_n_3 }),
.CYINIT(1'b1),
.DI(\gic0.gc0.count_d2_reg[6] [3:0]),
.O(minusOp[3:0]),
.S(S));
endmodule |
module dcfifo_32in_32out_8kb_wr_logic
(full,
ram_full_fb_i_reg,
Q,
WEBWE,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
\gic0.gc0.count_d2_reg[7] ,
wr_data_count,
ram_full_i,
wr_clk,
rst_full_ff_i,
RD_PNTR_WR,
wr_en,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output full;
output ram_full_fb_i_reg;
output [5:0]Q;
output [0:0]WEBWE;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output [7:0]\gic0.gc0.count_d2_reg[7] ;
output [1:0]wr_data_count;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input [7:0]RD_PNTR_WR;
input wr_en;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [5:0]Q;
wire [7:0]RD_PNTR_WR;
wire [0:0]WEBWE;
wire full;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire p_1_out;
wire ram_full_fb_i_reg;
wire ram_full_i;
wire rst_full_ff_i;
wire wpntr_n_1;
wire wpntr_n_13;
wire wpntr_n_14;
wire wpntr_n_15;
wire wpntr_n_16;
wire wpntr_n_2;
wire wpntr_n_3;
wire wpntr_n_4;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_8kb_wr_dc_as \gwas.gwdc0.wdc
(.S({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}),
.\gic0.gc0.count_d2_reg[6] (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6:0]),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_1,wpntr_n_2,wpntr_n_3,wpntr_n_4}),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
dcfifo_32in_32out_8kb_wr_status_flags_as \gwas.wsts
(.E(WEBWE),
.full(full),
.p_1_out(p_1_out),
.ram_full_i(ram_full_i),
.rst_full_ff_i(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_en(wr_en));
dcfifo_32in_32out_8kb_wr_bin_cntr wpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.E(WEBWE),
.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}),
.\gic0.gc0.count_d2_reg[7]_0 (\gic0.gc0.count_d2_reg[7] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.p_1_out(p_1_out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[7] ({wpntr_n_1,wpntr_n_2,wpntr_n_3,wpntr_n_4}),
.wr_en(wr_en));
endmodule |
module dcfifo_32in_32out_8kb_wr_status_flags_as
(full,
p_1_out,
E,
ram_full_i,
wr_clk,
rst_full_ff_i,
wr_en);
output full;
output p_1_out;
output [0:0]E;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input wr_en;
wire [0:0]E;
wire full;
wire p_1_out;
wire ram_full_i;
wire rst_full_ff_i;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(p_1_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(full));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule |
module BLE_v3_10_0 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("43b32828-1bc6-4f60-8661-55e8e3c70c20/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule |
module SCB_P4_v3_20_1 (
interrupt,
clock,
rx_tr_out,
tx_tr_out,
s_mosi,
s_sclk,
s_ss,
m_miso,
m_mosi,
m_sclk,
m_ss0,
m_ss1,
m_ss2,
m_ss3,
s_miso,
rx_in,
cts_in,
tx_out,
rts_out);
output interrupt;
input clock;
output rx_tr_out;
output tx_tr_out;
input s_mosi;
input s_sclk;
input s_ss;
input m_miso;
output m_mosi;
output m_sclk;
output m_ss0;
output m_ss1;
output m_ss2;
output m_ss3;
output s_miso;
input rx_in;
input cts_in;
output tx_out;
output rts_out;
wire uncfg_rx_irq;
wire sclk_m_wire;
wire Net_1264;
wire Net_1258;
wire rx_irq;
wire [3:0] select_m_wire;
wire Net_1099;
wire Net_1090;
wire Net_467;
wire Net_1316;
wire Net_252;
wire Net_1089;
wire Net_1320;
wire Net_1257;
wire sclk_s_wire;
wire Net_1268;
wire Net_1297;
wire Net_547;
wire Net_1001;
wire mosi_s_wire;
wire rts_wire;
wire mosi_m_wire;
wire Net_891;
wire Net_1263;
wire miso_s_wire;
wire cts_wire;
wire Net_899;
wire tx_wire;
wire Net_1028;
wire rx_wire;
wire Net_916;
wire Net_1000;
wire scl_wire;
wire miso_m_wire;
wire Net_1172;
wire Net_1170;
wire select_s_wire;
wire sda_wire;
wire Net_847;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/2dc2d7a8-ce2b-43c7-af4a-821c8cd73ccf"),
.source_clock_id(""),
.divisor(0),
.period("542534722.222222"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_847));
// select_s_VM (cy_virtualmux_v1_0)
assign select_s_wire = s_ss;
// rx_VM (cy_virtualmux_v1_0)
assign rx_wire = Net_1268;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_1257 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_1170 = Net_847;
// sclk_s_VM (cy_virtualmux_v1_0)
assign sclk_s_wire = s_sclk;
// mosi_s_VM (cy_virtualmux_v1_0)
assign mosi_s_wire = s_mosi;
// miso_m_VM (cy_virtualmux_v1_0)
assign miso_m_wire = m_miso;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
tx
(.oe(tmpOE__tx_net),
.y({tx_wire}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_1099));
assign Net_1258 = Net_847 | Net_1099;
cy_isr_v1_0
#(.int_type(2'b10))
SCB_IRQ
(.int_signal(interrupt));
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_1268}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// cts_VM (cy_virtualmux_v1_0)
assign cts_wire = Net_1264;
cy_m0s8_scb_v2_0 SCB (
.rx(rx_wire),
.miso_m(miso_m_wire),
.select_m(select_m_wire[3:0]),
.sclk_m(sclk_m_wire),
.mosi_s(mosi_s_wire),
.select_s(select_s_wire),
.sclk_s(sclk_s_wire),
.mosi_m(mosi_m_wire),
.scl(scl_wire),
.sda(sda_wire),
.tx(tx_wire),
.miso_s(miso_s_wire),
.interrupt(interrupt),
.cts(cts_wire),
.rts(rts_wire),
.tx_req(tx_tr_out),
.rx_req(rx_tr_out),
.clock(Net_1170));
defparam SCB.scb_mode = 2;
wire [0:0] tmpOE__cts_net;
wire [0:0] tmpIO_0__cts_net;
wire [0:0] tmpINTERRUPT_0__cts_net;
electrical [0:0] tmpSIOVREF__cts_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/d6cdce57-6174-4335-bfac-214115fde1eb"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
cts
(.oe(tmpOE__cts_net),
.y({1'b0}),
.fb({Net_1264}),
.io({tmpIO_0__cts_net[0:0]}),
.siovref(tmpSIOVREF__cts_net),
.interrupt({tmpINTERRUPT_0__cts_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__cts_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__rts_net;
wire [0:0] tmpFB_0__rts_net;
wire [0:0] tmpIO_0__rts_net;
wire [0:0] tmpINTERRUPT_0__rts_net;
electrical [0:0] tmpSIOVREF__rts_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/b2cd7ba8-7018-4355-962d-598e7769bbf3"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
rts
(.oe(tmpOE__rts_net),
.y({rts_wire}),
.fb({tmpFB_0__rts_net[0:0]}),
.io({tmpIO_0__rts_net[0:0]}),
.siovref(tmpSIOVREF__rts_net),
.interrupt({tmpINTERRUPT_0__rts_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rts_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// Device_VM4 (cy_virtualmux_v1_0)
assign uncfg_rx_irq = Net_1000;
assign m_mosi = mosi_m_wire;
assign m_sclk = sclk_m_wire;
assign m_ss0 = select_m_wire[0];
assign m_ss1 = select_m_wire[1];
assign m_ss2 = select_m_wire[2];
assign m_ss3 = select_m_wire[3];
assign s_miso = miso_s_wire;
assign tx_out = tx_wire;
assign rts_out = rts_wire;
endmodule |
module top ;
wire Net_3181;
electrical Net_3175;
wire Net_3180;
wire Net_3179;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3701;
electrical Net_3702;
electrical Net_2323;
electrical Net_290;
wire Net_3182;
wire Net_3183;
wire Net_3176;
wire Net_3177;
wire Net_3184;
wire Net_3185;
wire Net_3186;
wire Net_3187;
wire Net_3188;
wire Net_3189;
wire Net_3190;
wire Net_3191;
wire Net_3192;
wire Net_3193;
wire Net_3194;
wire Net_3195;
wire Net_3196;
wire Net_3197;
electrical Net_3171;
cy_annotation_universal_v1_0 C_1 (
.connect({
Net_3701,
Net_3702
})
);
defparam C_1.comp_name = "Capacitor_v1_0";
defparam C_1.port_names = "T1, T2";
defparam C_1.width = 2;
cy_annotation_universal_v1_0 GND_1 (
.connect({
Net_3172
})
);
defparam GND_1.comp_name = "Gnd_v1_0";
defparam GND_1.port_names = "T1";
defparam GND_1.width = 1;
BLE_v3_10_0 BLE (
.clk(Net_3179),
.pa_en(Net_3180));
cy_annotation_universal_v1_0 PWR_2 (
.connect({
Net_3173
})
);
defparam PWR_2.comp_name = "Power_v1_0";
defparam PWR_2.port_names = "T1";
defparam PWR_2.width = 1;
cy_annotation_universal_v1_0 R_3 (
.connect({
Net_3174,
Net_3175
})
);
defparam R_3.comp_name = "Resistor_v1_0";
defparam R_3.port_names = "T1, T2";
defparam R_3.width = 2;
wire [0:0] tmpOE__Conn_LED_net;
wire [0:0] tmpFB_0__Conn_LED_net;
wire [0:0] tmpIO_0__Conn_LED_net;
wire [0:0] tmpINTERRUPT_0__Conn_LED_net;
electrical [0:0] tmpSIOVREF__Conn_LED_net;
cy_psoc3_pins_v1_10
#(.id("8af192ab-4b9a-4fb3-b8ab-550f42242b6c"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b1),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Conn_LED
(.oe(tmpOE__Conn_LED_net),
.y({1'b0}),
.fb({tmpFB_0__Conn_LED_net[0:0]}),
.io({tmpIO_0__Conn_LED_net[0:0]}),
.siovref(tmpSIOVREF__Conn_LED_net),
.interrupt({tmpINTERRUPT_0__Conn_LED_net[0:0]}),
.annotation({Net_3175}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Conn_LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
SCB_P4_v3_20_1 UART (
.cts_in(1'b0),
.tx_out(Net_3182),
.rts_out(Net_3183),
.interrupt(Net_3176),
.clock(1'b0),
.rx_tr_out(Net_3184),
.tx_tr_out(Net_3185),
.s_mosi(1'b0),
.s_sclk(1'b0),
.s_ss(1'b0),
.m_miso(1'b0),
.m_mosi(Net_3190),
.m_sclk(Net_3191),
.m_ss0(Net_3192),
.m_ss1(Net_3193),
.m_ss2(Net_3194),
.m_ss3(Net_3195),
.s_miso(Net_3196),
.rx_in(1'b0));
cy_annotation_universal_v1_0 LED1_2 (
.connect({
Net_3173,
Net_3174
})
);
defparam LED1_2.comp_name = "LED_v1_0";
defparam LED1_2.port_names = "A, K";
defparam LED1_2.width = 2;
cy_annotation_universal_v1_0 L_1 (
.connect({
Net_3172,
Net_3701
})
);
defparam L_1.comp_name = "Inductor_v1_0";
defparam L_1.port_names = "T1, T2";
defparam L_1.width = 2;
cy_annotation_universal_v1_0 R_2 (
.connect({
Net_290,
Net_3171
})
);
defparam R_2.comp_name = "Resistor_v1_0";
defparam R_2.port_names = "T1, T2";
defparam R_2.width = 2;
cy_annotation_universal_v1_0 PWR (
.connect({
Net_2323
})
);
defparam PWR.comp_name = "Power_v1_0";
defparam PWR.port_names = "T1";
defparam PWR.width = 1;
cy_annotation_universal_v1_0 LED1 (
.connect({
Net_2323,
Net_290
})
);
defparam LED1.comp_name = "LED_v1_0";
defparam LED1.port_names = "A, K";
defparam LED1.width = 2;
endmodule |
module image_filter_AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_din,
img_data_stream_0_V_full_n,
img_data_stream_0_V_write,
img_data_stream_1_V_din,
img_data_stream_1_V_full_n,
img_data_stream_1_V_write,
img_data_stream_2_V_din,
img_data_stream_2_V_full_n,
img_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 7'b1;
parameter ap_ST_st2_fsm_1 = 7'b10;
parameter ap_ST_st3_fsm_2 = 7'b100;
parameter ap_ST_st4_fsm_3 = 7'b1000;
parameter ap_ST_pp1_stg0_fsm_4 = 7'b10000;
parameter ap_ST_st7_fsm_5 = 7'b100000;
parameter ap_ST_st8_fsm_6 = 7'b1000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [31:0] INPUT_STREAM_TDATA;
input INPUT_STREAM_TVALID;
output INPUT_STREAM_TREADY;
input [3:0] INPUT_STREAM_TKEEP;
input [3:0] INPUT_STREAM_TSTRB;
input [0:0] INPUT_STREAM_TUSER;
input [0:0] INPUT_STREAM_TLAST;
input [0:0] INPUT_STREAM_TID;
input [0:0] INPUT_STREAM_TDEST;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
output [7:0] img_data_stream_0_V_din;
input img_data_stream_0_V_full_n;
output img_data_stream_0_V_write;
output [7:0] img_data_stream_1_V_din;
input img_data_stream_1_V_full_n;
output img_data_stream_1_V_write;
output [7:0] img_data_stream_2_V_din;
input img_data_stream_2_V_full_n;
output img_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg INPUT_STREAM_TREADY;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [6:0] ap_CS_fsm = 7'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_26;
reg [0:0] eol_1_reg_184;
reg [31:0] axi_data_V_1_reg_195;
reg [11:0] p_1_reg_206;
reg [0:0] eol_reg_217;
reg [0:0] axi_last_V_2_reg_229;
reg [31:0] p_Val2_s_reg_241;
reg [0:0] eol_2_reg_253;
reg ap_sig_bdd_75;
reg [31:0] tmp_data_V_reg_402;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_87;
reg [0:0] tmp_last_V_reg_410;
wire [0:0] exitcond1_fu_319_p2;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_101;
wire [11:0] i_V_fu_324_p2;
reg [11:0] i_V_reg_426;
wire [0:0] exitcond2_fu_330_p2;
reg [0:0] exitcond2_reg_431;
reg ap_sig_cseq_ST_pp1_stg0_fsm_4;
reg ap_sig_bdd_112;
wire [0:0] brmerge_fu_344_p2;
reg ap_sig_bdd_120;
reg ap_reg_ppiten_pp1_it0 = 1'b0;
reg ap_sig_bdd_133;
reg ap_reg_ppiten_pp1_it1 = 1'b0;
wire [11:0] j_V_fu_335_p2;
wire [7:0] tmp_71_fu_363_p1;
reg [7:0] tmp_71_reg_444;
reg [7:0] tmp_12_reg_449;
reg [7:0] tmp_14_reg_454;
reg ap_sig_cseq_ST_st7_fsm_5;
reg ap_sig_bdd_158;
reg ap_sig_bdd_163;
reg [0:0] axi_last_V_3_reg_264;
reg [0:0] axi_last_V1_reg_153;
reg ap_sig_cseq_ST_st8_fsm_6;
reg ap_sig_bdd_181;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_188;
reg [31:0] axi_data_V_3_reg_276;
reg [31:0] axi_data_V1_reg_163;
reg [11:0] p_s_reg_173;
reg [0:0] eol_1_phi_fu_187_p4;
reg [31:0] axi_data_V_1_phi_fu_198_p4;
reg [0:0] eol_phi_fu_221_p4;
wire [0:0] ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
wire [31:0] ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
reg [31:0] p_Val2_s_phi_fu_245_p4;
wire [0:0] ap_reg_phiprechg_eol_2_reg_253pp1_it0;
wire [0:0] axi_last_V_1_mux_fu_356_p2;
reg [0:0] eol_3_reg_288;
reg [0:0] sof_1_fu_98;
wire [0:0] not_sof_2_fu_350_p2;
wire [0:0] tmp_user_V_fu_310_p1;
reg [6:0] ap_NS_fsm;
reg ap_sig_bdd_119;
reg ap_sig_bdd_211;
reg ap_sig_bdd_144;
reg ap_sig_bdd_229;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
axi_data_V1_reg_163 <= tmp_data_V_reg_402;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
axi_data_V1_reg_163 <= axi_data_V_3_reg_276;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
axi_data_V_1_reg_195 <= p_Val2_s_reg_241;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
axi_data_V_1_reg_195 <= axi_data_V1_reg_163;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
axi_data_V_3_reg_276 <= axi_data_V_1_phi_fu_198_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
axi_data_V_3_reg_276 <= INPUT_STREAM_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
axi_last_V1_reg_153 <= tmp_last_V_reg_410;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
axi_last_V1_reg_153 <= axi_last_V_3_reg_264;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_144) begin
if (ap_sig_bdd_211) begin
axi_last_V_2_reg_229 <= eol_1_phi_fu_187_p4;
end else if (ap_sig_bdd_119) begin
axi_last_V_2_reg_229 <= INPUT_STREAM_TLAST;
end else if ((ap_true == ap_true)) begin
axi_last_V_2_reg_229 <= ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
axi_last_V_3_reg_264 <= eol_1_phi_fu_187_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
axi_last_V_3_reg_264 <= INPUT_STREAM_TLAST;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
eol_1_reg_184 <= axi_last_V_2_reg_229;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
eol_1_reg_184 <= axi_last_V1_reg_153;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_144) begin
if (ap_sig_bdd_211) begin
eol_2_reg_253 <= axi_last_V_1_mux_fu_356_p2;
end else if (ap_sig_bdd_119) begin
eol_2_reg_253 <= INPUT_STREAM_TLAST;
end else if ((ap_true == ap_true)) begin
eol_2_reg_253 <= ap_reg_phiprechg_eol_2_reg_253pp1_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
eol_3_reg_288 <= eol_phi_fu_221_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
eol_3_reg_288 <= INPUT_STREAM_TLAST;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
eol_reg_217 <= eol_2_reg_253;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
eol_reg_217 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
p_1_reg_206 <= j_V_fu_335_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
p_1_reg_206 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_144) begin
if (ap_sig_bdd_211) begin
p_Val2_s_reg_241 <= axi_data_V_1_phi_fu_198_p4;
end else if (ap_sig_bdd_119) begin
p_Val2_s_reg_241 <= INPUT_STREAM_TDATA;
end else if ((ap_true == ap_true)) begin
p_Val2_s_reg_241 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
p_s_reg_173 <= ap_const_lv12_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
p_s_reg_173 <= i_V_reg_426;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
sof_1_fu_98 <= ap_const_lv1_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
sof_1_fu_98 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
exitcond2_reg_431 <= exitcond2_fu_330_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
i_V_reg_426 <= i_V_fu_324_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
tmp_12_reg_449 <= {{p_Val2_s_phi_fu_245_p4[ap_const_lv32_F : ap_const_lv32_8]}};
tmp_14_reg_454 <= {{p_Val2_s_phi_fu_245_p4[ap_const_lv32_17 : ap_const_lv32_10]}};
tmp_71_reg_444 <= tmp_71_fu_363_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(INPUT_STREAM_TVALID == ap_const_logic_0))) begin
tmp_data_V_reg_402 <= INPUT_STREAM_TDATA;
tmp_last_V_reg_410 <= INPUT_STREAM_TLAST;
end
end
/// INPUT_STREAM_TREADY assign process. ///
always @ (INPUT_STREAM_TVALID or ap_sig_cseq_ST_st2_fsm_1 or exitcond2_fu_330_p2 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or brmerge_fu_344_p2 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1 or ap_sig_cseq_ST_st7_fsm_5 or ap_sig_bdd_163 or eol_3_reg_288)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(INPUT_STREAM_TVALID == ap_const_logic_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_344_p2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))))) begin
INPUT_STREAM_TREADY = ap_const_logic_1;
end else begin
INPUT_STREAM_TREADY = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond1_fu_319_p2 or ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_319_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond1_fu_319_p2 or ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. ///
always @ (ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) begin
ap_sig_cseq_ST_pp1_stg0_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp1_stg0_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_188)
begin
if (ap_sig_bdd_188) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_101)
begin
if (ap_sig_bdd_101) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st7_fsm_5 assign process. ///
always @ (ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st8_fsm_6 assign process. ///
always @ (ap_sig_bdd_181)
begin
if (ap_sig_bdd_181) begin
ap_sig_cseq_ST_st8_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st8_fsm_6 = ap_const_logic_0;
end
end
/// axi_data_V_1_phi_fu_198_p4 assign process. ///
always @ (axi_data_V_1_reg_195 or p_Val2_s_reg_241 or exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
axi_data_V_1_phi_fu_198_p4 = p_Val2_s_reg_241;
end else begin
axi_data_V_1_phi_fu_198_p4 = axi_data_V_1_reg_195;
end
end
/// eol_1_phi_fu_187_p4 assign process. ///
always @ (eol_1_reg_184 or axi_last_V_2_reg_229 or exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
eol_1_phi_fu_187_p4 = axi_last_V_2_reg_229;
end else begin
eol_1_phi_fu_187_p4 = eol_1_reg_184;
end
end
/// eol_phi_fu_221_p4 assign process. ///
always @ (eol_reg_217 or eol_2_reg_253 or exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
eol_phi_fu_221_p4 = eol_2_reg_253;
end else begin
eol_phi_fu_221_p4 = eol_reg_217;
end
end
/// img_data_stream_0_V_write assign process. ///
always @ (exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
img_data_stream_0_V_write = ap_const_logic_1;
end else begin
img_data_stream_0_V_write = ap_const_logic_0;
end
end
/// img_data_stream_1_V_write assign process. ///
always @ (exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
img_data_stream_1_V_write = ap_const_logic_1;
end else begin
img_data_stream_1_V_write = ap_const_logic_0;
end
end
/// img_data_stream_2_V_write assign process. ///
always @ (exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
img_data_stream_2_V_write = ap_const_logic_1;
end else begin
img_data_stream_2_V_write = ap_const_logic_0;
end
end
/// p_Val2_s_phi_fu_245_p4 assign process. ///
always @ (INPUT_STREAM_TDATA or brmerge_fu_344_p2 or axi_data_V_1_phi_fu_198_p4 or ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 or ap_sig_bdd_229)
begin
if (ap_sig_bdd_229) begin
if (~(ap_const_lv1_0 == brmerge_fu_344_p2)) begin
p_Val2_s_phi_fu_245_p4 = axi_data_V_1_phi_fu_198_p4;
end else if ((ap_const_lv1_0 == brmerge_fu_344_p2)) begin
p_Val2_s_phi_fu_245_p4 = INPUT_STREAM_TDATA;
end else begin
p_Val2_s_phi_fu_245_p4 = ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end
end else begin
p_Val2_s_phi_fu_245_p4 = ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or INPUT_STREAM_TVALID or ap_sig_bdd_75 or exitcond1_fu_319_p2 or exitcond2_fu_330_p2 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1 or ap_sig_bdd_163 or eol_3_reg_288 or tmp_user_V_fu_310_p1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_75) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if ((~(INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == tmp_user_V_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~(INPUT_STREAM_TVALID == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_user_V_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
ap_ST_st4_fsm_3 :
begin
if (~(exitcond1_fu_319_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end
end
ap_ST_pp1_stg0_fsm_4 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end
end
ap_ST_st7_fsm_5 :
begin
if (((ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else if ((~ap_sig_bdd_163 & ~(ap_const_lv1_0 == eol_3_reg_288))) begin
ap_NS_fsm = ap_ST_st8_fsm_6;
end else begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end
end
ap_ST_st8_fsm_6 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 = 'bx;
assign ap_reg_phiprechg_eol_2_reg_253pp1_it0 = 'bx;
assign ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 = 'bx;
/// ap_sig_bdd_101 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_101 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_112 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_112 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_119 assign process. ///
always @ (exitcond2_fu_330_p2 or brmerge_fu_344_p2)
begin
ap_sig_bdd_119 = ((exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_344_p2));
end
/// ap_sig_bdd_120 assign process. ///
always @ (INPUT_STREAM_TVALID or exitcond2_fu_330_p2 or brmerge_fu_344_p2)
begin
ap_sig_bdd_120 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_344_p2));
end
/// ap_sig_bdd_133 assign process. ///
always @ (img_data_stream_0_V_full_n or img_data_stream_1_V_full_n or img_data_stream_2_V_full_n or exitcond2_reg_431)
begin
ap_sig_bdd_133 = (((img_data_stream_0_V_full_n == ap_const_logic_0) & (exitcond2_reg_431 == ap_const_lv1_0)) | ((exitcond2_reg_431 == ap_const_lv1_0) & (img_data_stream_1_V_full_n == ap_const_logic_0)) | ((exitcond2_reg_431 == ap_const_lv1_0) & (img_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_144 assign process. ///
always @ (ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_144 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))));
end
/// ap_sig_bdd_158 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_158 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_163 assign process. ///
always @ (INPUT_STREAM_TVALID or eol_3_reg_288)
begin
ap_sig_bdd_163 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == eol_3_reg_288));
end
/// ap_sig_bdd_181 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_181 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_188 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_188 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_211 assign process. ///
always @ (exitcond2_fu_330_p2 or brmerge_fu_344_p2)
begin
ap_sig_bdd_211 = ((exitcond2_fu_330_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == brmerge_fu_344_p2));
end
/// ap_sig_bdd_229 assign process. ///
always @ (exitcond2_fu_330_p2 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it0)
begin
ap_sig_bdd_229 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0));
end
/// ap_sig_bdd_26 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_26 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_75 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_75 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_87 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_87 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
assign axi_last_V_1_mux_fu_356_p2 = (eol_1_phi_fu_187_p4 | not_sof_2_fu_350_p2);
assign brmerge_fu_344_p2 = (sof_1_fu_98 | eol_phi_fu_221_p4);
assign exitcond1_fu_319_p2 = (p_s_reg_173 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond2_fu_330_p2 = (p_1_reg_206 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_324_p2 = (p_s_reg_173 + ap_const_lv12_1);
assign img_data_stream_0_V_din = tmp_71_reg_444;
assign img_data_stream_1_V_din = tmp_12_reg_449;
assign img_data_stream_2_V_din = tmp_14_reg_454;
assign j_V_fu_335_p2 = (p_1_reg_206 + ap_const_lv12_1);
assign not_sof_2_fu_350_p2 = (sof_1_fu_98 ^ ap_const_lv1_1);
assign tmp_71_fu_363_p1 = p_Val2_s_phi_fu_245_p4[7:0];
assign tmp_user_V_fu_310_p1 = INPUT_STREAM_TUSER;
endmodule |
module sky130_fd_sc_hdll__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_lp__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule |
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hdll__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module eg_step_ram(
input [2:0] state_V,
input [5:0] rate_V,
input [2:0] cnt_V,
output reg step_V
);
localparam ATTACK=3'd0, DECAY1=3'd1, DECAY2=3'd2, RELEASE=3'd7, HOLD=3'd3;
reg [7:0] step_idx;
reg [7:0] step_ram;
always @(*)
case( { rate_V[5:4]==2'b11, rate_V[1:0]} )
3'd0: step_ram = 8'b00000000;
3'd1: step_ram = 8'b10001000; // 2
3'd2: step_ram = 8'b10101010; // 4
3'd3: step_ram = 8'b11101110; // 6
3'd4: step_ram = 8'b10101010; // 4
3'd5: step_ram = 8'b11101010; // 5
3'd6: step_ram = 8'b11101110; // 6
3'd7: step_ram = 8'b11111110; // 7
endcase
always @(*) begin : rate_step
if( rate_V[5:2]==4'hf && state_V == ATTACK)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
if( rate_V[5:2]==4'd0 && state_V != ATTACK)
step_idx = 8'b11111110; // limit slowest decay rate_IV
else
step_idx = step_ram;
// a rate_IV of zero keeps the level still
step_V = rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
end
endmodule |
module soc
(
// General - Clocking & Reset
clk_i,
rst_i,
ext_intr_i,
intr_o,
// Memory interface
io_addr_i,
io_data_i,
io_data_o,
io_we_i,
io_stb_i,
io_ack_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = 12288;
parameter [31:0] EXTERNAL_INTERRUPTS = 1;
parameter SYSTICK_INTR_MS = 1;
parameter ENABLE_SYSTICK_TIMER = "ENABLED";
parameter ENABLE_HIGHRES_TIMER = "ENABLED";
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input [(EXTERNAL_INTERRUPTS - 1):0] ext_intr_i /*verilator public*/;
output intr_o /*verilator public*/;
// Memory Port
input [31:0] io_addr_i /*verilator public*/;
input [31:0] io_data_i /*verilator public*/;
output [31:0] io_data_o /*verilator public*/;
input io_we_i /*verilator public*/;
input io_stb_i /*verilator public*/;
output io_ack_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [7:0] timer_addr;
wire [31:0] timer_data_o;
wire [31:0] timer_data_i;
wire timer_we;
wire timer_stb;
wire timer_intr_systick;
wire timer_intr_hires;
wire [7:0] intr_addr;
wire [31:0] intr_data_o;
wire [31:0] intr_data_i;
wire intr_we;
wire intr_stb;
//-----------------------------------------------------------------
// Peripheral Interconnect
//-----------------------------------------------------------------
soc_pif8
u2_soc
(
// General - Clocking & Reset
.clk_i(clk_i),
.rst_i(rst_i),
// I/O bus (from mem_mux)
// 0x12000000 - 0x12FFFFFF
.io_addr_i(io_addr_i),
.io_data_i(io_data_i),
.io_data_o(io_data_o),
.io_we_i(io_we_i),
.io_stb_i(io_stb_i),
.io_ack_o(io_ack_o),
// Peripherals
// Unused = 0x12000000 - 0x120000FF
.periph0_addr_o(/*open*/),
.periph0_data_o(/*open*/),
.periph0_data_i(32'h00000000),
.periph0_we_o(/*open*/),
.periph0_stb_o(/*open*/),
// Timer = 0x12000100 - 0x120001FF
.periph1_addr_o(timer_addr),
.periph1_data_o(timer_data_o),
.periph1_data_i(timer_data_i),
.periph1_we_o(timer_we),
.periph1_stb_o(timer_stb),
// Interrupt Controller = 0x12000200 - 0x120002FF
.periph2_addr_o(intr_addr),
.periph2_data_o(intr_data_o),
.periph2_data_i(intr_data_i),
.periph2_we_o(intr_we),
.periph2_stb_o(intr_stb),
// Unused = 0x12000300 - 0x120003FF
.periph3_addr_o(/*open*/),
.periph3_data_o(/*open*/),
.periph3_data_i(32'h00000000),
.periph3_we_o(/*open*/),
.periph3_stb_o(/*open*/),
// Unused = 0x12000400 - 0x120004FF
.periph4_addr_o(/*open*/),
.periph4_data_o(/*open*/),
.periph4_data_i(32'h00000000),
.periph4_we_o(/*open*/),
.periph4_stb_o(/*open*/),
// Unused = 0x12000500 - 0x120005FF
.periph5_addr_o(/*open*/),
.periph5_data_o(/*open*/),
.periph5_data_i(32'h00000000),
.periph5_we_o(/*open*/),
.periph5_stb_o(/*open*/),
// Unused = 0x12000600 - 0x120006FF
.periph6_addr_o(/*open*/),
.periph6_data_o(/*open*/),
.periph6_data_i(32'h00000000),
.periph6_we_o(/*open*/),
.periph6_stb_o(/*open*/),
// Unused = 0x12000700 - 0x120007FF
.periph7_addr_o(/*open*/),
.periph7_data_o(/*open*/),
.periph7_data_i(32'h00000000),
.periph7_we_o(/*open*/),
.periph7_stb_o(/*open*/)
);
//-----------------------------------------------------------------
// Timer
//-----------------------------------------------------------------
timer_periph
#(
.CLK_KHZ(CLK_KHZ),
.SYSTICK_INTR_MS(SYSTICK_INTR_MS),
.ENABLE_SYSTICK_TIMER(ENABLE_SYSTICK_TIMER),
.ENABLE_HIGHRES_TIMER(ENABLE_HIGHRES_TIMER)
)
u5_timer
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_systick_o(timer_intr_systick),
.intr_hires_o(timer_intr_hires),
.addr_i(timer_addr),
.data_o(timer_data_i),
.data_i(timer_data_o),
.we_i(timer_we),
.stb_i(timer_stb)
);
//-----------------------------------------------------------------
// Interrupt Controller
//-----------------------------------------------------------------
intr_periph
#(
.EXTERNAL_INTERRUPTS(EXTERNAL_INTERRUPTS)
)
u6_intr
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(intr_o),
.intr0_i(1'b0),
.intr1_i(timer_intr_systick),
.intr2_i(timer_intr_hires),
.intr3_i(1'b0),
.intr4_i(1'b0),
.intr5_i(1'b0),
.intr6_i(1'b0),
.intr7_i(1'b0),
.intr_ext_i(ext_intr_i),
.addr_i(intr_addr),
.data_o(intr_data_i),
.data_i(intr_data_o),
.we_i(intr_we),
.stb_i(intr_stb)
);
//-------------------------------------------------------------------
// Hooks for debug
//-------------------------------------------------------------------
`ifdef verilator
function [0:0] get_uart_wr;
// verilator public
get_uart_wr = 1'b0;
endfunction
function [7:0] get_uart_data;
// verilator public
get_uart_data = 8'b0;
endfunction
`endif
endmodule |
module DSP_OUT_REGISTERED (clk, a, b, m, out);
localparam DATA_WIDTH = 4;
input wire clk;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
output wire [DATA_WIDTH-1:0] out;
/* Combinational logic */
(* pack="DSP-DFF" *)
wire [DATA_WIDTH-1:0] c_out;
DSP_COMBINATIONAL comb (.a(a), .b(b), .m(m), .out(c_out));
/* Output register on clk */
genvar j;
for (j=0; j<DATA_WIDTH; j=j+1) begin: output_dffs_gen
DFF q_out_ff(.D(c_out[j]), .Q(out[j]), .CLK(clk));
end
endmodule |
module sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module spu_maaeqb (
/*outputs*/
spu_maaeqb_memren,
spu_maaeqb_memwen,
spu_maaeqb_rst_iptr,
spu_maaeqb_rst_jptr,
spu_maaeqb_incr_iptr,
spu_maaeqb_incr_jptr,
spu_maaeqb_a_rd_oprnd_sel,
spu_maaeqb_ax_rd_oprnd_sel,
spu_maaeqb_m_rd_oprnd_sel,
spu_maaeqb_me_rd_oprnd_sel,
spu_maaeqb_n_rd_oprnd_sel,
spu_maaeqb_m_wr_oprnd_sel,
spu_maaeqb_me_wr_oprnd_sel,
spu_maaeqb_iminus1_ptr_sel,
spu_maaeqb_j_ptr_sel,
spu_maaeqb_iminusj_ptr_sel,
spu_maaeqb_iminuslenminus1_sel,
spu_maaeqb_irshft_sel,
spu_maaeqb_jjptr_wen,
spu_maaeqb_oprnd2_wen,
spu_maaeqb_oprnd2_bypass,
spu_maaeqb_a_leftshft,
spu_maaeqb_oprnd1_mxsel,
spu_maaeqb_oprnd1_wen,
spu_maaeqb_mul_req_vld,
spu_maaeqb_mul_areg_shf,
spu_maaeqb_mul_acc,
spu_maaeqb_mul_areg_rst,
spu_maaeqb_mul_done,
spu_maaeqb_jjptr_sel,
/*inputs*/
spu_mactl_mulop,
spu_maaddr_iequtwolenplus2,
spu_maaddr_iequtwolenplus1,
spu_maaddr_jequiminus1,
spu_maaddr_jequlen,
spu_maaddr_halfpnt_set,
spu_mactl_iss_pulse_dly,
mul_spu_ack,
mul_spu_shf_ack,
spu_maexp_start_mulred_aequb,
spu_mactl_expop,
spu_maaddr_jequiminus1rshft,
spu_maaddr_iequtwolen,
spu_maaddr_ieven,
spu_maaddr_ieq0,
spu_maaddr_aequb,
spu_mactl_kill_op,
spu_mactl_stxa_force_abort,
se,
reset,
rclk);
// ---------------------------------------------------------------
input reset;
input rclk;
input se;
input spu_maaddr_iequtwolenplus2;
input spu_maaddr_iequtwolenplus1;
input spu_maaddr_jequiminus1;
input spu_maaddr_jequlen;
input spu_maaddr_halfpnt_set;
input mul_spu_ack;
input mul_spu_shf_ack;
input spu_mactl_mulop;
input spu_mactl_iss_pulse_dly;
input spu_maexp_start_mulred_aequb;
input spu_mactl_expop;
input spu_maaddr_jequiminus1rshft;
input spu_maaddr_iequtwolen;
input spu_maaddr_ieven;
input spu_maaddr_ieq0;
input spu_maaddr_aequb;
input spu_mactl_kill_op;
input spu_mactl_stxa_force_abort;
// ---------------------------------------------------------------
output spu_maaeqb_memwen;
output spu_maaeqb_memren;
output spu_maaeqb_rst_iptr;
output spu_maaeqb_rst_jptr;
output spu_maaeqb_incr_iptr;
output spu_maaeqb_incr_jptr;
output spu_maaeqb_a_rd_oprnd_sel;
output spu_maaeqb_ax_rd_oprnd_sel;
output spu_maaeqb_m_rd_oprnd_sel;
output spu_maaeqb_me_rd_oprnd_sel;
output spu_maaeqb_n_rd_oprnd_sel;
output spu_maaeqb_m_wr_oprnd_sel;
output spu_maaeqb_me_wr_oprnd_sel;
output spu_maaeqb_iminus1_ptr_sel;
output spu_maaeqb_j_ptr_sel;
output spu_maaeqb_iminusj_ptr_sel;
output spu_maaeqb_iminuslenminus1_sel;
output spu_maaeqb_irshft_sel;
output spu_maaeqb_jjptr_wen;
output spu_maaeqb_oprnd2_wen;
output spu_maaeqb_oprnd2_bypass;
output spu_maaeqb_a_leftshft;
output [1:0] spu_maaeqb_oprnd1_mxsel;
output spu_maaeqb_oprnd1_wen;
output spu_maaeqb_mul_req_vld;
output spu_maaeqb_mul_areg_shf;
output spu_maaeqb_mul_acc;
output spu_maaeqb_mul_areg_rst;
output spu_maaeqb_mul_done;
output spu_maaeqb_jjptr_sel;
// ---------------------------------------------------------------
wire tr2mwrite_frm_accumshft_pre;
wire tr2mwrite_frm_accumshft;
wire spu_maaeqb_rd_aj,spu_maaeqb_rd_mj,
spu_maaeqb_rd_niminusj,spu_maaeqb_rd_ai,
spu_maaeqb_wr_mi,spu_maaeqb_wr_miminuslenminus1,
spu_maaeqb_rd_n0;
wire spu_maaeqb_rd_aiminusj;
wire tr2accumshft_frm_mwrite;
wire tr2accumshft_frm_iloopn;
wire nxt_mwrite_state;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire local_stxa_abort = nxt_mwrite_state & spu_mactl_stxa_force_abort;
wire state_reset = reset | spu_mactl_kill_op | local_stxa_abort;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
dff_s #(1) idle_state_ff (
.din(nxt_idle_state) ,
.q(cur_idle_state),
.clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopa_state_ff (
.din(nxt_jloopa_state) ,
.q(cur_jloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) ijloopa_state_ff (
.din(nxt_ijloopa_state) ,
.q(cur_ijloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopn_state_ff (
.din(nxt_jloopn_state) ,
.q(cur_jloopn_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopm_state_ff (
.din(nxt_jloopm_state) ,
.q(cur_jloopm_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopa1_state_ff (
.din(nxt_iloopa1_state) ,
.q(cur_iloopa1_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopa_state_ff (
.din(nxt_iloopa_state) ,
.q(cur_iloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) nprime_state_ff (
.din(nxt_nprime_state) ,
.q(cur_nprime_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) mwrite_state_ff (
.din(nxt_mwrite_state) ,
.q(cur_mwrite_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopn_state_ff (
.din(nxt_iloopn_state) ,
.q(cur_iloopn_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) accumshft_state_ff (
.din(nxt_accumshft_state) ,
.q(cur_accumshft_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire spu_maaddr_aequb_q;
dff_s #(1) spu_maaddr_aequb_ff (
.din(spu_maaddr_aequb) ,
.q(spu_maaddr_aequb_q),
.clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
// 5 cycle delay for mul result coming back.
// ---------------------------------------------------------------
wire tr2mwrite_frm_jloopn = cur_jloopn_state & mul_spu_ack & spu_maaddr_halfpnt_set &
spu_maaddr_jequlen;
wire mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5;
//assign mul_result_c0 = (cur_nprime_state & mul_spu_ack & ~spu_maaddr_halfpnt_set) |
assign mul_result_c0 = (cur_nprime_state & mul_spu_ack) |
( tr2mwrite_frm_jloopn );
dffr_s #(5) mul_res_ff (
.din({mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4}) ,
.q({mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5}),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ----------------------------------------------------------------
// ----------------------------------------------------------------
// ---------------------------------------------------------------
wire tr2idle_frm_accumshft = cur_accumshft_state & spu_maaddr_iequtwolenplus2 &
mul_spu_shf_ack;
wire spu_maaeqb_mul_done_pre = tr2idle_frm_accumshft;
wire spu_maaeqb_mul_done_q;
dff_s #(1) muldone_dly_ff (
.din(spu_maaeqb_mul_done_pre) ,
.q(spu_maaeqb_mul_done_q),
.clk (rclk), .se(se), .si(), .so());
assign spu_maaeqb_mul_done = spu_maaeqb_mul_done_q | local_stxa_abort;
assign spu_maaeqb_rst_iptr = tr2idle_frm_accumshft;
// ----------------------------------------------------------------
// transition to idle state
wire mulop_start = (spu_mactl_iss_pulse_dly & spu_mactl_mulop & spu_maaddr_aequb_q) |
spu_maexp_start_mulred_aequb;
assign spu_maaeqb_mul_areg_rst = mulop_start;
assign nxt_idle_state = (
state_reset |
tr2idle_frm_accumshft |
(cur_idle_state & ~mulop_start));
// ----------------------------------------------------------------
// transition to jloopa state(rdA[j])
wire tr2jloopa_frm_ijloopa = cur_ijloopa_state & mul_spu_ack & ~spu_maaddr_jequiminus1rshft;
wire tr2jloopa_frm_accumshft = cur_accumshft_state & ~spu_maaddr_iequtwolenplus2 &
~spu_maaddr_iequtwolenplus1 & ~spu_maaddr_iequtwolen &
mul_spu_shf_ack;
wire tr2jloopa_frm_accumshft_dly;
dffr_s #(1) tr2jloopa_frm_accumshft_dly_ff (
.din(tr2jloopa_frm_accumshft) ,
.q(tr2jloopa_frm_accumshft_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_jloopa_state = (
tr2jloopa_frm_ijloopa |
tr2jloopa_frm_accumshft_dly );
//assign spu_maaeqb_rd_aj = nxt_jloopa_state;
assign spu_maaeqb_rd_aj = (cur_ijloopa_state & ~spu_maaddr_jequiminus1rshft) |
tr2jloopa_frm_accumshft_dly;
// ----------------------------------------------------------------
// transition to jloopa state(rdA[i-j])
assign nxt_ijloopa_state = (
cur_jloopa_state |
(cur_ijloopa_state & ~mul_spu_ack));
assign spu_maaeqb_a_leftshft = cur_ijloopa_state;
//assign spu_maaeqb_rd_aiminusj = nxt_ijloopa_state | cur_ijloopa_state;
assign spu_maaeqb_rd_aiminusj = cur_jloopa_state;
// ----------------------------------------------------------------
// transition to iloopa state(rdA[i/2])
wire tr2iloopa1_frm_ijloopa = cur_ijloopa_state & mul_spu_ack & spu_maaddr_ieven &
spu_maaddr_jequiminus1rshft;
wire tr2iloopa1_frm_accumshft = spu_maaddr_ieven & cur_accumshft_state & mul_spu_shf_ack &
//(spu_maaddr_iequtwolenplus1 | spu_maaddr_iequtwolenplus2 |
(spu_maaddr_iequtwolenplus1 |
spu_maaddr_iequtwolen);
wire tr2iloopa1_frm_accumshft_dly;
dffr_s #(1) tr2iloopa1_frm_accumshft_dly_ff (
.din(tr2iloopa1_frm_accumshft) ,
.q(tr2iloopa1_frm_accumshft_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
wire tr2iloopa1_frm_idle = cur_idle_state & mulop_start;
wire tr2iloopa1_frm_idle_dly;
dffr_s #(1) tr2iloopa1_frm_idle_ff (
.din(tr2iloopa1_frm_idle) ,
.q(tr2iloopa1_frm_idle_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_iloopa1_state = (
tr2iloopa1_frm_accumshft_dly |
tr2iloopa1_frm_ijloopa |
tr2iloopa1_frm_idle_dly) ;
wire cur_iloopa1_state_dly;
dffr_s #(1) cur_iloopa1_state_dly_ff (
.din(cur_iloopa1_state) ,
.q(cur_iloopa1_state_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_iloopa_state = (
cur_iloopa1_state_dly |
(cur_iloopa_state & ~mul_spu_ack));
//assign spu_maaeqb_rd_ai = cur_iloopa1_state | nxt_iloopa_state | cur_iloopa_state;
assign spu_maaeqb_rd_ai = (cur_ijloopa_state & spu_maaddr_ieven & spu_maaddr_jequiminus1rshft) |
tr2iloopa1_frm_idle_dly |
//(cur_accumshft_state & spu_maaddr_ieven & (spu_maaddr_iequtwolenplus1 | spu_maaddr_iequtwolen)) |
tr2iloopa1_frm_accumshft_dly |
// above are for iloopa1 and below are for iloopa.
(cur_iloopa1_state_dly);
// ----------------------------------------------------------------
// transition to jloopm state(rdM[j])
wire tr2jloopm_frm_ijloopa = cur_ijloopa_state & mul_spu_ack & ~spu_maaddr_ieven &
spu_maaddr_jequiminus1rshft;
// the following is needed to reset jptr on the transition
// from ijloopa to jloopm.
wire tr2jloopm_frm_ijloopa_dly;
dffr_s #(1) tr2jloopm_frm_ijloopa_dly_ff (
.din(tr2jloopm_frm_ijloopa) ,
.q(tr2jloopm_frm_ijloopa_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
wire tr2jloopm_frm_iloopa = cur_iloopa_state & mul_spu_ack & ~spu_maaddr_ieq0 ;
wire tr2jloopm_frm_iloopa_dly;
dffr_s #(1) tr2jloopm_frm_iloopa_dly_ff (
.din(tr2jloopm_frm_iloopa) ,
.q(tr2jloopm_frm_iloopa_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
wire tr2jloopm_frm_jloopn = cur_jloopn_state & mul_spu_ack &
((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set)) ;
assign nxt_jloopm_state = (
tr2jloopm_frm_jloopn |
tr2jloopm_frm_ijloopa_dly |
tr2jloopm_frm_iloopa_dly);
//assign spu_maaeqb_rd_mj = nxt_jloopm_state;
assign spu_maaeqb_rd_mj = tr2jloopm_frm_ijloopa_dly | tr2jloopm_frm_iloopa_dly |
cur_jloopn_state &
((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set)) ;
// ----------------------------------------------------------------
// transition to jloopn state(rdN[j])
assign nxt_jloopn_state = (
cur_jloopm_state |
(cur_jloopn_state & ~mul_spu_ack));
assign spu_maaeqb_jjptr_wen = cur_jloopa_state | cur_jloopm_state;
assign spu_maaeqb_incr_jptr = tr2jloopa_frm_ijloopa | tr2jloopm_frm_jloopn;
assign spu_maaeqb_jjptr_sel = cur_ijloopa_state | cur_jloopn_state;
//assign spu_maaeqb_rd_niminusj = nxt_jloopn_state;
assign spu_maaeqb_rd_niminusj = cur_jloopm_state;
// ----------------------------------------------------------------
// transition to nprime state
wire tr2nprime_frm_jloopn = cur_jloopn_state & mul_spu_ack &
spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set;
wire tr2nprime_frm_iloopa = cur_iloopa_state & mul_spu_ack & spu_maaddr_ieq0;
assign nxt_nprime_state = (
tr2nprime_frm_jloopn |
tr2nprime_frm_iloopa |
(cur_nprime_state & ~mul_spu_ack));
// the following is to reset jptr on the 1st half.
wire tr2nprime_frm_jloopn_dly;
dffr_s #(1) tr2nprime_frm_jloopn_dly_ff (
.din(tr2nprime_frm_jloopn) ,
.q(tr2nprime_frm_jloopn_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ----------------------------------------------------------------
// transition to mwrite state
assign tr2mwrite_frm_accumshft_pre = cur_accumshft_state & mul_spu_shf_ack &
spu_maaddr_iequtwolenplus1;
// delaying for one cycle to allow time to do i ptr increment
// and calculate i-len-1(M[i-len-1]).This is due to skipping jloop on last
// i iteration, not enough time to do both.
dffr_s #(1) tr2mwrite_frm_accumshft_ff (
.din(tr2mwrite_frm_accumshft_pre) ,
.q(tr2mwrite_frm_accumshft),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_mwrite_state = (
tr2mwrite_frm_accumshft |
(mul_result_c5));
//assign spu_maaeqb_memwen = nxt_mwrite_state;
wire spu_maaeqb_wr_mi_oprnd2_wenbyp = nxt_mwrite_state & ~spu_maaddr_halfpnt_set;
wire spu_maaeqb_wr_miminuslenminus1_oprnd2_wenbyp = nxt_mwrite_state & spu_maaddr_halfpnt_set;
// ---------------------------------------------------------------
// transition to iloopn state
assign nxt_iloopn_state = (
(cur_mwrite_state & ~spu_maaddr_halfpnt_set) |
(cur_iloopn_state & ~mul_spu_ack));
//assign spu_maaeqb_rd_n0 = nxt_iloopn_state | cur_iloopn_state;
assign spu_maaeqb_rd_n0 = cur_mwrite_state;
// ---------------------------------------------------------------
// transition to accumshft state
assign tr2accumshft_frm_mwrite = cur_mwrite_state & spu_maaddr_halfpnt_set;
assign tr2accumshft_frm_iloopn = cur_iloopn_state & mul_spu_ack;
assign nxt_accumshft_state = (
tr2accumshft_frm_mwrite |
tr2accumshft_frm_iloopn |
(cur_accumshft_state & ~mul_spu_shf_ack));
assign spu_maaeqb_incr_iptr = tr2accumshft_frm_mwrite | tr2accumshft_frm_iloopn;
dff_s #(1) memwen_dly_ff (
.din(spu_maaeqb_incr_iptr) ,
.q(spu_maaeqb_memwen),
.clk (rclk), .se(se), .si(), .so());
assign spu_maaeqb_wr_mi = spu_maaeqb_memwen & ~spu_maaddr_halfpnt_set;
assign spu_maaeqb_wr_miminuslenminus1 = spu_maaeqb_memwen & spu_maaddr_halfpnt_set;
// ---------------------------------------------------------------
wire cur_accumshft_pulse,cur_accumshft_q;
dff_s #(1) cur_accumshft_pulse_ff (
.din(cur_accumshft_state) ,
.q(cur_accumshft_q),
.clk (rclk), .se(se), .si(), .so());
assign cur_accumshft_pulse = ~cur_accumshft_q & cur_accumshft_state;
assign spu_maaeqb_rst_jptr = mulop_start | tr2nprime_frm_jloopn_dly |
tr2jloopm_frm_ijloopa | tr2iloopa1_frm_ijloopa |
(cur_accumshft_pulse &
spu_maaddr_halfpnt_set & ~spu_maaddr_iequtwolenplus2 &
~spu_maaddr_iequtwolenplus1);
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// send selects to spu_maaddr.v
// ---------------------------------------------------------------
// ---------------------------------------------------------------
assign spu_maaeqb_memren = spu_maaeqb_rd_aj |
spu_maaeqb_rd_aiminusj |
spu_maaeqb_rd_mj |
spu_maaeqb_rd_niminusj |
spu_maaeqb_rd_ai | spu_maaeqb_rd_n0;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
assign spu_maaeqb_a_rd_oprnd_sel = (spu_maaeqb_rd_aj | spu_maaeqb_rd_ai |
spu_maaeqb_rd_aiminusj) & ~spu_mactl_expop ;
assign spu_maaeqb_ax_rd_oprnd_sel = (spu_maaeqb_rd_aj | spu_maaeqb_rd_ai |
spu_maaeqb_rd_aiminusj) & spu_mactl_expop ;
assign spu_maaeqb_m_rd_oprnd_sel = spu_maaeqb_rd_mj & ~spu_mactl_expop;
assign spu_maaeqb_me_rd_oprnd_sel = spu_maaeqb_rd_mj & spu_mactl_expop ;
assign spu_maaeqb_n_rd_oprnd_sel = (spu_maaeqb_rd_niminusj & ~spu_maaeqb_rd_mj) |
spu_maaeqb_rd_n0;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
assign spu_maaeqb_m_wr_oprnd_sel = (spu_maaeqb_wr_mi | spu_maaeqb_wr_miminuslenminus1) &
~spu_mactl_expop;
assign spu_maaeqb_me_wr_oprnd_sel = (spu_maaeqb_wr_mi | spu_maaeqb_wr_miminuslenminus1) &
spu_mactl_expop;
wire spu_maaeqb_m_wr_oprnd2_wen = (spu_maaeqb_wr_mi_oprnd2_wenbyp |
spu_maaeqb_wr_miminuslenminus1_oprnd2_wenbyp) &
~spu_mactl_expop;
wire spu_maaeqb_me_wr_oprnd2_wen = (spu_maaeqb_wr_mi_oprnd2_wenbyp |
spu_maaeqb_wr_miminuslenminus1_oprnd2_wenbyp) &
spu_mactl_expop;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
assign spu_maaeqb_iminus1_ptr_sel = spu_maaeqb_wr_mi;
assign spu_maaeqb_j_ptr_sel = spu_maaeqb_rd_aj | spu_maaeqb_rd_mj;
assign spu_maaeqb_iminusj_ptr_sel =
(spu_maaeqb_rd_aiminusj | spu_maaeqb_rd_niminusj) &
~(spu_maaeqb_rd_aj | spu_maaeqb_rd_mj);
assign spu_maaeqb_iminuslenminus1_sel = spu_maaeqb_wr_miminuslenminus1;
assign spu_maaeqb_irshft_sel = spu_maaeqb_rd_ai;
// ---------------------------------------------------------------
// request to mul unit when asserted
wire spu_maaeqb_mul_req_vld_pre = nxt_ijloopa_state | nxt_jloopn_state |
nxt_nprime_state | nxt_iloopn_state |
nxt_iloopa_state;
dffr_s #(1) spu_maaeqb_mul_req_vld_ff (
.din(spu_maaeqb_mul_req_vld_pre) ,
.q(spu_maaeqb_mul_req_vld),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
/*
assign spu_maaeqb_mul_req_vld = cur_ijloopa_state | cur_jloopn_state |
cur_nprime_state | cur_iloopn_state |
cur_iloopa_state;
*/
// ---------------------------------------------------------------
assign spu_maaeqb_mul_areg_shf = cur_accumshft_state;
// ---------------------------------------------------------------
/*
wire oprnd2_sel = (spu_maaeqb_rd_aj | spu_maaeqb_rd_ai |
spu_maaeqb_m_rd_oprnd_sel | spu_maaeqb_me_rd_oprnd_sel) ;
*/
//wire oprnd2_sel = nxt_jloopa_state | cur_iloopa1_state | nxt_iloopa_state | nxt_jloopm_state ;
wire oprnd2_sel = nxt_jloopa_state | nxt_iloopa1_state | nxt_jloopm_state ;
wire oprnd2_sel_q;
dff_s #(1) oprnd2_wen_ff (
.din(oprnd2_sel) ,
.q(oprnd2_sel_q),
.clk (rclk), .se(se), .si(), .so());
assign spu_maaeqb_oprnd2_wen = oprnd2_sel_q | spu_maaeqb_m_wr_oprnd2_wen |
spu_maaeqb_me_wr_oprnd2_wen ;
assign spu_maaeqb_oprnd2_bypass = spu_maaeqb_m_wr_oprnd2_wen | spu_maaeqb_me_wr_oprnd2_wen ;
//assign spu_maaeqb_oprnd1_sel = cur_nprime_state; // only select nprime if set
// ---------------------------------------------------------------
assign spu_maaeqb_mul_acc = spu_maaeqb_mul_req_vld & ~cur_nprime_state;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire spu_maaeqb_memrd4op1 = spu_maaeqb_rd_aiminusj |
//spu_maaeqb_rd_ai |
cur_iloopa1_state_dly |
spu_maaeqb_rd_niminusj | spu_maaeqb_rd_n0;
wire spu_maaeqb_memrd4op1_q;
dff_s #(1) spu_maaeqb_memrd4op1_ff (
.din(spu_maaeqb_memrd4op1) ,
.q(spu_maaeqb_memrd4op1_q),
.clk (rclk), .se(se), .si(), .so());
wire [1:0] spu_maaeqb_oprnd1_mxsel;
assign spu_maaeqb_oprnd1_mxsel[0] = ~cur_nprime_state & ~spu_maaeqb_memrd4op1_q;
assign spu_maaeqb_oprnd1_mxsel[1] = ~cur_nprime_state & spu_maaeqb_memrd4op1_q;
//assign spu_maaeqb_oprnd1_mxsel[2] = cur_nprime_state;
assign spu_maaeqb_oprnd1_wen = spu_maaeqb_memrd4op1_q;
endmodule |
module sky130_fd_sc_ms__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule |
module rj45_led_controller(
input wire clk, // 150 MHz
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire write_req,
input wire read_req,
input wire [31:0] data_write,
output reg [31:0] data_read,
input wire [25:0] address,
output wire busy,
//--------------------------------------------------------------------------
//---------------------------HW INTERFACE-----------------------------------
//--------------------------------------------------------------------------
output wire rj45_led_sck,
output wire rj45_led_sin,
output wire rj45_led_lat,
output wire rj45_led_blk
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
localparam IDLE = 3'd0,
READ = 3'd1,
WRITE = 4'd2;
localparam CLK_DIV = 3;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire update_out;
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [CLK_DIV:0] clk_div1;
reg [CLK_DIV:0] clk_div2;
reg clk_enable;
reg [15:0] output_shifter;
reg [4:0] write_counter;
reg latch;
reg [2:0] state;
reg busy_int;
reg [31:0] value_cache;
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
assign rj45_led_sck = clk_div2[CLK_DIV] & clk_enable;
assign rj45_led_sin = output_shifter[15];
assign rj45_led_lat = latch;
assign rj45_led_blk = 0;
assign update_out = ~clk_div1[CLK_DIV] & clk_div2[CLK_DIV]; // negedge serial clock
assign busy = busy_int | read_req | write_req;
//----------------------------------------------------------------------------
// Clock Division
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
clk_div1 <= 0;
clk_div2 <= 0;
end
else begin
clk_div2 <= clk_div1;
clk_div1 <= clk_div1 + 1;
end
end
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
state <= IDLE;
clk_enable <= 0;
output_shifter <= 16'h0000;
write_counter <= 5'h00;
latch <= 0;
busy_int <= 1;
value_cache <= 32'd0;
end
else begin
case ( state )
IDLE: begin
data_read <= 32'd0;
if ( write_req ) begin
state <= WRITE;
busy_int <= 1;
output_shifter <= {1'b0, data_write[0], 1'b0, data_write[1],
1'b0, data_write[2], 1'b0, data_write[3],
1'b0, data_write[4], 1'b0, data_write[5],
1'b0, data_write[6], 1'b0, data_write[7]};
value_cache <= {24'd0, data_write[7:0]};
write_counter <= 0;
end
else if ( read_req ) begin
state <= READ;
busy_int <= 1;
end
else begin
busy_int <= 0;
end
end
WRITE: begin
if ( update_out ) begin
write_counter <= write_counter + 5'd1;
if ( write_counter == 0 ) begin
clk_enable <= 1;
end
else if ( write_counter < 5'd16) begin
output_shifter <= {output_shifter[14:0], 1'b0};
end
else if ( write_counter == 5'd16 ) begin
clk_enable <= 0;
latch <= 1;
end
else begin
state <= IDLE;
latch <= 0;
busy_int <= 0;
end
end
end
READ: begin
state <= IDLE;
busy_int <= 0;
data_read <= value_cache;
end
endcase
end
end
endmodule |
module sky130_fd_sc_hdll__diode_4 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__diode_4 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE)
);
endmodule |
module sky130_fd_sc_ls__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_ls__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule |
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
enable_traffic_tracking_check ( .error(1'b1) );
end
endgenerate
altera_avlmm_slv_freeze_bridge #(
.ENABLE_FREEZE_FROM_PR_REGION (0),
.ENABLE_TRAFFIC_TRACKING (0),
.ENABLED_BACKPRESSURE_BRIDGE (0),
.USE_BURSTCOUNT (1),
.USE_READ_DATA_VALID (1),
.USE_READ_WAIT_TIME (0),
.USE_WRITE_WAIT_TIME (0),
.USE_WRRESPONSEVALID (1),
.SLV_BRIDGE_ADDR_WIDTH (10),
.SLV_BRIDGE_BYTEEN_WIDTH (4),
.SLV_BRIDGE_MAX_RDTRANS_WIDTH (3),
.SLV_BRIDGE_MAX_WRTRANS_WIDTH (3),
.SLV_BRIDGE_RWT_WIDTH (1),
.SLV_BRIDGE_WWT_WIDTH (1),
.SLV_BRIDGE_FIX_RDLATENCY_WIDTH (1),
.SLV_BRIDGE_BURSTCOUNT_WIDTH (3),
.SLV_BRIDGE_WRDATA_WIDTH (32),
.SLV_BRIDGE_RDDATA_WIDTH (32),
.SLV_BRIDGE_FIX_READ_LATENCY (0),
.SLV_BRIDGE_READ_WAIT_TIME (1),
.SLV_BRIDGE_WRITE_WAIT_TIME (0)
) avlmm_slv_freeze_bridge (
.clk (clock), // input, width = 1, clock_sink.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.freeze (freeze_conduit_freeze), // input, width = 1, freeze_conduit.freeze
.illegal_request (freeze_conduit_illegal_request), // output, width = 1, .illegal_request
.slv_bridge_to_pr_read (slv_bridge_to_pr_read), // output, width = 1, slv_bridge_to_pr.read
.slv_bridge_to_pr_waitrequest (slv_bridge_to_pr_waitrequest), // input, width = 1, .waitrequest
.slv_bridge_to_pr_write (slv_bridge_to_pr_write), // output, width = 1, .write
.slv_bridge_to_pr_addr (slv_bridge_to_pr_address), // output, width = 10, .address
.slv_bridge_to_pr_byteenable (slv_bridge_to_pr_byteenable), // output, width = 4, .byteenable
.slv_bridge_to_pr_wrdata (slv_bridge_to_pr_writedata), // output, width = 32, .writedata
.slv_bridge_to_pr_rddata (slv_bridge_to_pr_readdata), // input, width = 32, .readdata
.slv_bridge_to_pr_burstcount (slv_bridge_to_pr_burstcount), // output, width = 3, .burstcount
.slv_bridge_to_pr_rddata_valid (slv_bridge_to_pr_readdatavalid), // input, width = 1, .readdatavalid
.slv_bridge_to_pr_beginbursttransfer (slv_bridge_to_pr_beginbursttransfer), // output, width = 1, .beginbursttransfer
.slv_bridge_to_pr_debugaccess (slv_bridge_to_pr_debugaccess), // output, width = 1, .debugaccess
.slv_bridge_to_pr_response (slv_bridge_to_pr_response), // input, width = 2, .response
.slv_bridge_to_pr_lock (slv_bridge_to_pr_lock), // output, width = 1, .lock
.slv_bridge_to_pr_writeresponsevalid (slv_bridge_to_pr_writeresponsevalid), // input, width = 1, .writeresponsevalid
.slv_bridge_to_sr_read (slv_bridge_to_sr_read), // input, width = 1, slv_bridge_to_sr.read
.slv_bridge_to_sr_waitrequest (slv_bridge_to_sr_waitrequest), // output, width = 1, .waitrequest
.slv_bridge_to_sr_write (slv_bridge_to_sr_write), // input, width = 1, .write
.slv_bridge_to_sr_addr (slv_bridge_to_sr_address), // input, width = 10, .address
.slv_bridge_to_sr_byteenable (slv_bridge_to_sr_byteenable), // input, width = 4, .byteenable
.slv_bridge_to_sr_wrdata (slv_bridge_to_sr_writedata), // input, width = 32, .writedata
.slv_bridge_to_sr_rddata (slv_bridge_to_sr_readdata), // output, width = 32, .readdata
.slv_bridge_to_sr_burstcount (slv_bridge_to_sr_burstcount), // input, width = 3, .burstcount
.slv_bridge_to_sr_rddata_valid (slv_bridge_to_sr_readdatavalid), // output, width = 1, .readdatavalid
.slv_bridge_to_sr_beginbursttransfer (slv_bridge_to_sr_beginbursttransfer), // input, width = 1, .beginbursttransfer
.slv_bridge_to_sr_debugaccess (slv_bridge_to_sr_debugaccess), // input, width = 1, .debugaccess
.slv_bridge_to_sr_response (slv_bridge_to_sr_response), // output, width = 2, .response
.slv_bridge_to_sr_lock (slv_bridge_to_sr_lock), // input, width = 1, .lock
.slv_bridge_to_sr_writeresponsevalid (slv_bridge_to_sr_writeresponsevalid), // output, width = 1, .writeresponsevalid
.pr_freeze (1'b0) // (terminated),
);
endmodule |
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xnor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule |
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module fabric2_decoder #(
parameter PORTNO_WIDTH = 11
)
(
i_addr,
o_addr,
o_portno
);
localparam PORT_BITS = PORTNO_WIDTH + 1;
input wire [`ADDR_WIDTH-1:0] i_addr;
output wire [`ADDR_WIDTH-1:0] o_addr;
output wire [PORTNO_WIDTH-1:0] o_portno;
/* Decode address */
assign o_addr = (!i_addr[`ADDR_WIDTH-1] ? { 1'b0, i_addr[`ADDR_WIDTH-2:0] } :
{ {(PORT_BITS){1'b0}}, i_addr[`ADDR_WIDTH-PORT_BITS-1:0] });
/* Decode port number */
assign o_portno = (i_addr[`ADDR_WIDTH-1] ? i_addr[`ADDR_WIDTH-2:`ADDR_WIDTH-PORT_BITS] + 1'b1 :
{(PORT_BITS-1){1'b0}});
endmodule |
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module quick_fifo #(
parameter FIFO_WIDTH = 32,
parameter FIFO_DEPTH_BITS = 8,
parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4
) (
input wire clk,
input wire reset_n,
input wire we, // input write enable
input wire [FIFO_WIDTH - 1:0] din, // input write data with configurable width
input wire re, // input read enable
output reg valid, // dout valid
output reg [FIFO_WIDTH - 1:0] dout, // output read data with configurable width
output reg [FIFO_DEPTH_BITS - 1:0] count, // output FIFOcount
output reg empty, // output FIFO empty
output reg full, // output FIFO full
output reg almostfull // output configurable programmable full/ almost full
);
reg [FIFO_DEPTH_BITS - 1:0] rp = 0;
reg [FIFO_DEPTH_BITS - 1:0] wp = 0;
reg [FIFO_DEPTH_BITS - 1:0] mem_count = 0; // output FIFOcount
reg mem_empty = 1'b1;
reg valid_t1 = 0, valid_t2 = 0;
reg valid0 = 0;
wire remem;
wire wemem;
wire remem_valid;
wire [FIFO_WIDTH-1:0] dout_mem;
assign remem = (re & valid_t1 & valid_t2) | ~(valid_t1 & valid_t2);
assign wemem = we & ~full;
assign remem_valid = remem & ~mem_empty;
spl_sdp_mem #(.DATA_WIDTH(FIFO_WIDTH),
.ADDR_WIDTH(FIFO_DEPTH_BITS)) fifo_mem(
.clk (clk),
.we (wemem),
.re (remem),
.raddr (rp),
.waddr (wp),
.din (din),
.dout (dout_mem)
);
// data
always @(posedge clk) begin
dout <= (valid_t2)? ((re)? dout_mem : dout) : dout_mem;
end
// valids, flags
always @(posedge clk) begin
if (~reset_n) begin
empty <= 1'b1;
full <= 1'b0;
almostfull <= 1'b0;
count <= 0; //32'b0;
rp <= 0;
wp <= 0;
valid_t2 <= 1'b0;
valid_t1 <= 1'b0;
mem_empty <= 1'b1;
mem_count <= 'b0;
//dout <= 0;
valid <= 0;
valid0 <= 0;
end
else begin
valid <= (valid)? ((re)? valid0 : 1'b1) : valid0;
valid0 <= (remem)? ~mem_empty : valid0;
valid_t2 <= (valid_t2)? ((re)? valid_t1 : 1'b1) : valid_t1;
valid_t1 <= (remem)? ~mem_empty : valid_t1;
rp <= (remem & ~mem_empty)? (rp + 1'b1) : rp;
wp <= (wemem)? (wp + 1'b1) : wp;
// mem_empty
if (we) mem_empty <= 1'b0;
else if(remem & (mem_count == 1'b1)) mem_empty <= 1'b1;
// mem_count
if( wemem & ~remem_valid) mem_count <= mem_count + 1'b1;
else if (~wemem & remem_valid) mem_count <= mem_count - 1'b1;
// empty
if (we) empty <= 1'b0;
else if((re & valid_t2 & ~valid_t1) & (count == 1'b1)) empty <= 1'b1;
// count
if( wemem & (~(re & valid_t2) | ~re) ) count <= count + 1'b1;
else if (~wemem & (re & valid_t2)) count <= count - 1'b1;
//
if (we & ~re) begin
if (count == (2**FIFO_DEPTH_BITS-1))
full <= 1'b1;
if (count == (FIFO_ALMOSTFULL_THRESHOLD-1))
almostfull <= 1'b1;
end
//
if ((~we | full) & re) begin //
full <= 1'b0;
if (count == FIFO_ALMOSTFULL_THRESHOLD)
almostfull <= 1'b0;
end
end
end
endmodule |
module or1200_dpram
(
// Generic synchronous double-port RAM interface
clk_a, ce_a, addr_a, do_a,
clk_b, ce_b, we_b, addr_b, di_b
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
//
// Generic synchronous double-port RAM interface
//
input clk_a; // Clock
input ce_a; // Chip enable input
input [aw-1:0] addr_a; // address bus inputs
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input ce_b; // Chip enable input
input we_b; // Write enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
//
// Internal wires and registers
//
//
// Generic double-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
reg [aw-1:0] addr_a_reg; // RAM address registered
// Function to access GPRs (for use by Verilator). No need to hide this one
// from the simulator, since it has an input (as required by IEEE 1364-2001).
function [31:0] get_gpr;
// verilator public
input [aw-1:0] gpr_no;
get_gpr = mem[gpr_no];
endfunction // get_gpr
function [31:0] set_gpr;
// verilator public
input [aw-1:0] gpr_no;
input [dw-1:0] value;
begin
mem[gpr_no] = value;
set_gpr = 0;
end
endfunction // get_gpr
//
// Data output drivers
//
//assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_a = mem[addr_a_reg];
integer k;
initial begin
for(k = 0; k < (1 << aw); k = k + 1) begin
mem[k] = 0;
end
end
//
// RAM read
//
always @(posedge clk_a)
if (ce_a)
addr_a_reg <= addr_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b & we_b)
mem[addr_b] <= di_b;
endmodule |
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