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module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module altera_avalon_dc_fifo(
in_clk,
in_reset_n,
out_clk,
out_reset_n,
// sink
in_data,
in_valid,
in_ready,
in_startofpacket,
in_endofpacket,
in_empty,
in_error,
in_channel,
// source
out_data,
out_valid,
out_ready,
out_startofpacket,
out_endofpacket,
out_empty,
out_error,
out_channel,
// in csr
in_csr_address,
in_csr_write,
in_csr_read,
in_csr_readdata,
in_csr_writedata,
// out csr
out_csr_address,
out_csr_write,
out_csr_read,
out_csr_readdata,
out_csr_writedata,
// streaming in status
almost_full_valid,
almost_full_data,
// streaming out status
almost_empty_valid,
almost_empty_data,
// (internal, experimental interface) space available st source
space_avail_data
);
// ---------------------------------------------------------------------
// Parameters
// ---------------------------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FIFO_DEPTH = 16;
parameter CHANNEL_WIDTH = 0;
parameter ERROR_WIDTH = 0;
parameter USE_PACKETS = 0;
parameter USE_IN_FILL_LEVEL = 0;
parameter USE_OUT_FILL_LEVEL = 0;
parameter WR_SYNC_DEPTH = 2;
parameter RD_SYNC_DEPTH = 2;
parameter STREAM_ALMOST_FULL = 0;
parameter STREAM_ALMOST_EMPTY = 0;
parameter BACKPRESSURE_DURING_RESET = 0;
// optimizations
parameter LOOKAHEAD_POINTERS = 0;
parameter PIPELINE_POINTERS = 0;
// experimental, internal parameter
parameter USE_SPACE_AVAIL_IF = 0;
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
localparam EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT);
localparam PACKET_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// ---------------------------------------------------------------------
// Input/Output Signals
// ---------------------------------------------------------------------
input in_clk;
input in_reset_n;
input out_clk;
input out_reset_n;
input [DATA_WIDTH - 1 : 0] in_data;
input in_valid;
input in_startofpacket;
input in_endofpacket;
input [((EMPTY_WIDTH > 0) ? EMPTY_WIDTH - 1 : 0) : 0] in_empty;
input [((ERROR_WIDTH > 0) ? ERROR_WIDTH - 1 : 0) : 0] in_error;
input [((CHANNEL_WIDTH > 0) ? CHANNEL_WIDTH - 1 : 0) : 0] in_channel;
output in_ready;
output [DATA_WIDTH - 1 : 0] out_data;
output reg out_valid;
output out_startofpacket;
output out_endofpacket;
output [((EMPTY_WIDTH > 0) ? EMPTY_WIDTH - 1 : 0) : 0] out_empty;
output [((ERROR_WIDTH > 0) ? ERROR_WIDTH - 1 : 0) : 0] out_error;
output [((CHANNEL_WIDTH > 0) ? CHANNEL_WIDTH - 1 : 0) : 0] out_channel;
input out_ready;
input in_csr_address;
input in_csr_read;
input in_csr_write;
input [31 : 0] in_csr_writedata;
output reg [31 : 0] in_csr_readdata;
input out_csr_address;
input out_csr_read;
input out_csr_write;
input [31 : 0] out_csr_writedata;
output reg [31 : 0] out_csr_readdata;
output reg almost_full_valid;
output reg almost_full_data;
output reg almost_empty_valid;
output reg almost_empty_data;
output [ADDR_WIDTH : 0] space_avail_data;
// ---------------------------------------------------------------------
// Memory Pointers
// ---------------------------------------------------------------------
(* ramstyle="no_rw_check" *) reg [PAYLOAD_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
wire [ADDR_WIDTH - 1 : 0] mem_wr_ptr;
wire [ADDR_WIDTH - 1 : 0] mem_rd_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr_lookahead;
reg [ADDR_WIDTH : 0] out_rd_ptr;
reg [ADDR_WIDTH : 0] out_rd_ptr_lookahead;
// ---------------------------------------------------------------------
// Internal Signals
// ---------------------------------------------------------------------
wire [ADDR_WIDTH : 0] next_out_wr_ptr;
wire [ADDR_WIDTH : 0] next_in_wr_ptr;
wire [ADDR_WIDTH : 0] next_out_rd_ptr;
wire [ADDR_WIDTH : 0] next_in_rd_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
wire [ADDR_WIDTH : 0] out_wr_ptr_gray;
reg [ADDR_WIDTH : 0] out_rd_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
wire [ADDR_WIDTH : 0] in_rd_ptr_gray;
reg [ADDR_WIDTH : 0] out_wr_ptr_gray_reg;
reg [ADDR_WIDTH : 0] in_rd_ptr_gray_reg;
reg full;
reg empty;
wire [PAYLOAD_WIDTH - 1 : 0] in_payload;
reg [PAYLOAD_WIDTH - 1 : 0] out_payload;
reg [PAYLOAD_WIDTH - 1 : 0] internal_out_payload;
wire [PACKET_SIGNALS_WIDTH - 1 : 0] in_packet_signals;
wire [PACKET_SIGNALS_WIDTH - 1 : 0] out_packet_signals;
wire internal_out_ready;
wire internal_out_valid;
wire [ADDR_WIDTH : 0] out_fill_level;
reg [ADDR_WIDTH : 0] out_fifo_fill_level;
reg [ADDR_WIDTH : 0] in_fill_level;
reg [ADDR_WIDTH : 0] in_space_avail;
reg [23 : 0] almost_empty_threshold;
reg [23 : 0] almost_full_threshold;
reg sink_in_reset;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign in_payload = in_data;
assign out_data = out_payload;
end
end
assign out_packet_signals = 'b0;
end
endgenerate
// ---------------------------------------------------------------------
// Memory
//
// Infers a simple dual clock memory with unregistered outputs
// ---------------------------------------------------------------------
always @(posedge in_clk) begin
if (in_valid && in_ready)
mem[mem_wr_ptr] <= in_payload;
end
always @(posedge out_clk) begin
internal_out_payload <= mem[mem_rd_ptr];
end
assign mem_rd_ptr = next_out_rd_ptr;
assign mem_wr_ptr = in_wr_ptr;
// ---------------------------------------------------------------------
// Pointer Management
//
// Increment our good old read and write pointers on their native
// clock domains.
// ---------------------------------------------------------------------
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_wr_ptr <= 0;
in_wr_ptr_lookahead <= 1;
end
else begin
in_wr_ptr <= next_in_wr_ptr;
in_wr_ptr_lookahead <= (in_valid && in_ready) ? in_wr_ptr_lookahead + 1'b1 : in_wr_ptr_lookahead;
end
end
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_rd_ptr <= 0;
out_rd_ptr_lookahead <= 1;
end
else begin
out_rd_ptr <= next_out_rd_ptr;
out_rd_ptr_lookahead <= (internal_out_valid && internal_out_ready) ? out_rd_ptr_lookahead + 1'b1 : out_rd_ptr_lookahead;
end
end
generate if (LOOKAHEAD_POINTERS) begin : lookahead_pointers
assign next_in_wr_ptr = (in_ready && in_valid) ? in_wr_ptr_lookahead : in_wr_ptr;
assign next_out_rd_ptr = (internal_out_ready && internal_out_valid) ? out_rd_ptr_lookahead : out_rd_ptr;
end
else begin : non_lookahead_pointers
assign next_in_wr_ptr = (in_ready && in_valid) ? in_wr_ptr + 1'b1 : in_wr_ptr;
assign next_out_rd_ptr = (internal_out_ready && internal_out_valid) ? out_rd_ptr + 1'b1 : out_rd_ptr;
end
endgenerate
// ---------------------------------------------------------------------
// Empty/Full Signal Generation
//
// We keep read and write pointers that are one bit wider than
// required, and use that additional bit to figure out if we're
// full or empty.
// ---------------------------------------------------------------------
always @(posedge out_clk or negedge out_reset_n) begin
if(!out_reset_n)
empty <= 1;
else
empty <= (next_out_rd_ptr == next_out_wr_ptr);
end
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
full <= 0;
sink_in_reset <= 1'b1;
end
else begin
full <= (next_in_rd_ptr[ADDR_WIDTH - 1 : 0] == next_in_wr_ptr[ADDR_WIDTH - 1 : 0]) && (next_in_rd_ptr[ADDR_WIDTH] != next_in_wr_ptr[ADDR_WIDTH]);
sink_in_reset <= 1'b0;
end
end
// ---------------------------------------------------------------------
// Write Pointer Clock Crossing
//
// Clock crossing is done with gray encoding of the pointers. What? You
// want to know more? We ensure a one bit change at sampling time,
// and then metastable harden the sampled gray pointer.
// ---------------------------------------------------------------------
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
in_wr_ptr_gray <= 0;
else
in_wr_ptr_gray <= bin2gray(in_wr_ptr);
end
altera_dcfifo_synchronizer_bundle #(.WIDTH(ADDR_WIDTH+1), .DEPTH(WR_SYNC_DEPTH))
write_crosser (
.clk(out_clk),
.reset_n(out_reset_n),
.din(in_wr_ptr_gray),
.dout(out_wr_ptr_gray)
);
// ---------------------------------------------------------------------
// Optionally pipeline the gray to binary conversion for the write pointer.
// Doing this will increase the latency of the FIFO, but increase fmax.
// ---------------------------------------------------------------------
generate if (PIPELINE_POINTERS) begin : wr_ptr_pipeline
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n)
out_wr_ptr_gray_reg <= 0;
else
out_wr_ptr_gray_reg <= gray2bin(out_wr_ptr_gray);
end
assign next_out_wr_ptr = out_wr_ptr_gray_reg;
end
else begin : no_wr_ptr_pipeline
assign next_out_wr_ptr = gray2bin(out_wr_ptr_gray);
end
endgenerate
// ---------------------------------------------------------------------
// Read Pointer Clock Crossing
//
// Go the other way, go the other way...
// ---------------------------------------------------------------------
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n)
out_rd_ptr_gray <= 0;
else
out_rd_ptr_gray <= bin2gray(out_rd_ptr);
end
altera_dcfifo_synchronizer_bundle #(.WIDTH(ADDR_WIDTH+1), .DEPTH(RD_SYNC_DEPTH))
read_crosser (
.clk(in_clk),
.reset_n(in_reset_n),
.din(out_rd_ptr_gray),
.dout(in_rd_ptr_gray)
);
// ---------------------------------------------------------------------
// Optionally pipeline the gray to binary conversion of the read pointer.
// Doing this will increase the pessimism of the FIFO, but increase fmax.
// ---------------------------------------------------------------------
generate if (PIPELINE_POINTERS) begin : rd_ptr_pipeline
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
in_rd_ptr_gray_reg <= 0;
else
in_rd_ptr_gray_reg <= gray2bin(in_rd_ptr_gray);
end
assign next_in_rd_ptr = in_rd_ptr_gray_reg;
end
else begin : no_rd_ptr_pipeline
assign next_in_rd_ptr = gray2bin(in_rd_ptr_gray);
end
endgenerate
// ---------------------------------------------------------------------
// Avalon ST Signals
// ---------------------------------------------------------------------
assign in_ready = BACKPRESSURE_DURING_RESET ? !(full || sink_in_reset) : !full;
assign internal_out_valid = !empty;
// --------------------------------------------------
// Output Pipeline Stage
//
// We do this on the single clock FIFO to keep fmax
// up because the memory outputs are kind of slow.
// Therefore, this stage is even more critical on a dual clock
// FIFO, wouldn't you say? No one wants a slow dcfifo.
// --------------------------------------------------
assign internal_out_ready = out_ready || !out_valid;
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid;
out_payload <= internal_out_payload;
end
end
end
// ---------------------------------------------------------------------
// Out Fill Level
//
// As in the SCFIFO, we account for the output stage as well in the
// fill level calculations. This means that the out fill level always
// gives the most accurate fill level report.
//
// On a full 16-deep FIFO, the out fill level will read 17. Funny, but
// accurate.
//
// That's essential on the output side, because a downstream component
// might want to know the exact amount of data in the FIFO at any time.
// ---------------------------------------------------------------------
generate
if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_fifo_fill_level <= 0;
end
else begin
out_fifo_fill_level <= next_out_wr_ptr - next_out_rd_ptr;
end
end
assign out_fill_level = out_fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
endgenerate
// ---------------------------------------------------------------------
// Almost Empty Streaming Status & Out CSR
//
// This is banal by now, but where's the empty signal? The output side.
// Where's the almost empty status? The output side.
//
// The almost empty signal is asserted when the output fill level
// in the FIFO falls below the user-specified threshold.
//
// Output CSR address map:
//
// | Addr | RW | 31 - 24 | 23 - 0 |
// | 0 | R | Reserved | Out fill level |
// | 1 | RW | Reserved | Almost empty threshold |
// ---------------------------------------------------------------------
generate
if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_csr_readdata <= 0;
if (STREAM_ALMOST_EMPTY)
almost_empty_threshold <= 0;
end
else begin
if (out_csr_write) begin
if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
almost_empty_threshold <= out_csr_writedata[23 : 0];
end
else if (out_csr_read) begin
out_csr_readdata <= 0;
if (out_csr_address == 0)
out_csr_readdata[23 : 0] <= out_fill_level;
else if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
out_csr_readdata[23 : 0] <= almost_empty_threshold;
end
end
end
end
if (STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
almost_empty_valid <= 0;
almost_empty_data <= 0;
end
else begin
almost_empty_valid <= 1'b1;
almost_empty_data <= (out_fill_level <= almost_empty_threshold);
end
end
end
endgenerate
// ---------------------------------------------------------------------
// In Fill Level & In Status Connection Point
//
// Note that the input fill level does not account for the output
// stage i.e it is only the fifo fill level.
//
// Is this a problem? No, because the input fill is usually used to
// see how much data can still be pushed into this FIFO. The FIFO
// fill level gives exactly this information, and there's no need to
// make our lives more difficult by including the output stage here.
//
// One might ask: why not just report a space available level on the
// input side? Well, I'd like to make this FIFO be as similar as possible
// to its single clock cousin, and that uses fill levels and
// fill thresholds with nary a mention of space available.
// ---------------------------------------------------------------------
generate
if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_fill_level <= 0;
end
else begin
in_fill_level <= next_in_wr_ptr - next_in_rd_ptr;
end
end
end
endgenerate
generate
if (USE_SPACE_AVAIL_IF) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_space_avail <= FIFO_DEPTH;
end
else begin
// -------------------------------------
// space = DEPTH-fill = DEPTH-(wr-rd) = DEPTH+rd-wr
// Conveniently, DEPTH requires the same number of bits
// as the pointers, e.g. a dcfifo with depth = 8
// requires 4-bit pointers.
//
// Adding 8 to a 4-bit pointer is simply negating the
// first bit... as is done below.
// -------------------------------------
in_space_avail <= {~next_in_rd_ptr[ADDR_WIDTH],
next_in_rd_ptr[ADDR_WIDTH-1:0]} -
next_in_wr_ptr;
end
end
assign space_avail_data = in_space_avail;
end
else begin : gen_blk13_else
assign space_avail_data = 'b0;
end
endgenerate
// ---------------------------------------------------------------------
// Almost Full Streaming Status & In CSR
//
// Where's the full signal? The input side.
// Where's the almost full status? The input side.
//
// The almost full data bit is asserted when the input fill level
// in the FIFO goes above the user-specified threshold.
//
// Input csr port address map:
//
// | Addr | RW | 31 - 24 | 23 - 0 |
// | 0 | R | Reserved | In fill level |
// | 1 | RW | Reserved | Almost full threshold |
// ---------------------------------------------------------------------
generate
if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_csr_readdata <= 0;
if (STREAM_ALMOST_FULL)
almost_full_threshold <= 0;
end
else begin
if (in_csr_write) begin
if (STREAM_ALMOST_FULL && (in_csr_address == 1))
almost_full_threshold <= in_csr_writedata[23 : 0];
end
else if (in_csr_read) begin
in_csr_readdata <= 0;
if (in_csr_address == 0)
in_csr_readdata[23 : 0] <= in_fill_level;
else if (STREAM_ALMOST_FULL && (in_csr_address == 1))
in_csr_readdata[23 : 0] <= almost_full_threshold;
end
end
end
end
if (STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
almost_full_valid <= 0;
almost_full_data <= 0;
end
else begin
almost_full_valid <= 1'b1;
almost_full_data <= (in_fill_level >= almost_full_threshold);
end
end
end
endgenerate
// ---------------------------------------------------------------------
// Gray Functions
//
// These are real beasts when you look at them. But they'll be
// tested thoroughly.
// ---------------------------------------------------------------------
function [ADDR_WIDTH : 0] bin2gray;
input [ADDR_WIDTH : 0] bin_val;
integer i;
for (i = 0; i <= ADDR_WIDTH; i = i + 1)
begin
if (i == ADDR_WIDTH)
bin2gray[i] = bin_val[i];
else
bin2gray[i] = bin_val[i+1] ^ bin_val[i];
end
endfunction
function [ADDR_WIDTH : 0] gray2bin;
input [ADDR_WIDTH : 0] gray_val;
integer i;
integer j;
for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin
gray2bin[i] = gray_val[i];
for (j = ADDR_WIDTH; j > i; j = j - 1) begin
gray2bin[i] = gray2bin[i] ^ gray_val[j];
end
end
endfunction
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_ireq_tvalid,
s_axis_ireq_tready, s_axis_ireq_tlast, s_axis_ireq_tdata, s_axis_ireq_tkeep,
s_axis_ireq_tuser, m_axis_iresp_tvalid, m_axis_iresp_tready, m_axis_iresp_tlast,
m_axis_iresp_tdata, m_axis_iresp_tkeep, m_axis_iresp_tuser, m_axis_treq_tvalid,
m_axis_treq_tready, m_axis_treq_tlast, m_axis_treq_tdata, m_axis_treq_tkeep,
m_axis_treq_tuser, s_axis_tresp_tvalid, s_axis_tresp_tready, s_axis_tresp_tlast,
s_axis_tresp_tdata, s_axis_tresp_tkeep, s_axis_tresp_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_ireq_tvalid,s_axis_ireq_tready,s_axis_ireq_tlast,s_axis_ireq_tdata[63:0],s_axis_ireq_tkeep[7:0],s_axis_ireq_tuser[31:0],m_axis_iresp_tvalid,m_axis_iresp_tready,m_axis_iresp_tlast,m_axis_iresp_tdata[63:0],m_axis_iresp_tkeep[7:0],m_axis_iresp_tuser[31:0],m_axis_treq_tvalid,m_axis_treq_tready,m_axis_treq_tlast,m_axis_treq_tdata[63:0],m_axis_treq_tkeep[7:0],m_axis_treq_tuser[31:0],s_axis_tresp_tvalid,s_axis_tresp_tready,s_axis_tresp_tlast,s_axis_tresp_tdata[63:0],s_axis_tresp_tkeep[7:0],s_axis_tresp_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_ireq_tvalid;
output s_axis_ireq_tready;
input s_axis_ireq_tlast;
input [63:0]s_axis_ireq_tdata;
input [7:0]s_axis_ireq_tkeep;
input [31:0]s_axis_ireq_tuser;
output m_axis_iresp_tvalid;
input m_axis_iresp_tready;
output m_axis_iresp_tlast;
output [63:0]m_axis_iresp_tdata;
output [7:0]m_axis_iresp_tkeep;
output [31:0]m_axis_iresp_tuser;
output m_axis_treq_tvalid;
input m_axis_treq_tready;
output m_axis_treq_tlast;
output [63:0]m_axis_treq_tdata;
output [7:0]m_axis_treq_tkeep;
output [31:0]m_axis_treq_tuser;
input s_axis_tresp_tvalid;
output s_axis_tresp_tready;
input s_axis_tresp_tlast;
input [63:0]s_axis_tresp_tdata;
input [7:0]s_axis_tresp_tkeep;
input [31:0]s_axis_tresp_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule |
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule |
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule |
module axis_mux #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_axis_tvalid[select_reg];
wire current_s_tready = s_axis_tready[select_reg];
wire current_s_tlast = s_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_axis_tready_next = 0;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && (s_axis_tvalid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
// generate ready signal on selected port
s_axis_tready_next = (m_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_axis_tdata_int = current_s_tdata;
m_axis_tkeep_int = current_s_tkeep;
m_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_axis_tlast_int = current_s_tlast;
m_axis_tid_int = current_s_tid;
m_axis_tdest_int = current_s_tdest;
m_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_axis_tready_reg <= s_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule |
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
output wire VGA_HSYNC,
output wire VGA_VSYNC,
output wire VGA_RED,
output wire VGA_GREEN,
output wire VGA_BLUE
);
wire [15:0] wIP,wIP_temp,wIP_return;
reg rWriteEnable,rBranchTaken,rReturn,rCall;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestinationPrev;
wire [15:0] wSourceData0,wSourceData1,wSourceData0_RAM,wSourceData1_RAM,wResultPrev,wIPInitialValue,wDestinationJump,wImmediateValue;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate,wPushAddr;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0_RAM ),
.oDataOut1( wSourceData1_RAM )
);
assign wDestinationJump = (rReturn) ? wIP_return : wDestination;
assign wIPInitialValue = (Reset) ? 8'b0 : wDestinationJump;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
/////////////////////////////////
// CALL RET //
// assign wPushAddr = (wInstruction[27:24] == `CALL);
//assign wPushAddr = (wOperation == `CALL);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FF_RET
(
.Clock(~Clock),
.Reset(Reset),
.Enable( rCall ),
.D( wIP_temp ),
.Q( wIP_return )
);
// //
/////////////////////////////////
//////////////////////////////
// VGA Controler and Memory //
VGA_Controller vga (
.Clock(Clock),
.Enable(1'b1),
.Reset(Reset),
.iPixel(`RED),
.oHorizontalSync(VGA_HSYNC),
.oVerticalSync(VGA_VSYNC),
.oRed(VGA_RED),
.oGreen(VGA_GREEN),
.oBlue(VGA_BLUE)
);
// Instanciar memoria aqui
// //
//////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b1;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b1;
rCall <= 1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
`WRITE_ROM :
begin
if (row <= 200){
}else if(row <= 400){
}else if (row <= 600) {
}else if(row <= 800) {}
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule |
module PLL (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.locked (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "FAST",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_enable0 = "PORT_UNUSED",
altpll_component.port_enable1 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.port_extclkena0 = "PORT_UNUSED",
altpll_component.port_extclkena1 = "PORT_UNUSED",
altpll_component.port_extclkena2 = "PORT_UNUSED",
altpll_component.port_extclkena3 = "PORT_UNUSED",
altpll_component.port_sclkout0 = "PORT_UNUSED",
altpll_component.port_sclkout1 = "PORT_UNUSED";
endmodule |
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module
fifo_wrapper(
// Clock and depth
input wire clk_in,
output wire[7:0] depth_out,
// Data is clocked into the FIFO on each clock edge where both valid & ready are high
input wire[7:0] inputData_in,
input wire inputValid_in,
output wire inputReady_out,
// Data is clocked out of the FIFO on each clock edge where both valid & ready are high
output wire[7:0] outputData_out,
output wire outputValid_out,
input wire outputReady_in
);
wire inputFull;
wire outputEmpty;
// Invert "full/empty" signals to give "ready/valid" signals
assign inputReady_out = !inputFull;
assign outputValid_out = !outputEmpty;
// The encapsulated FIFO
altera_fifo fifo(
.clock(clk_in),
.usedw(depth_out),
// Production end
.data(inputData_in),
.wrreq(inputValid_in),
.full(inputFull),
// Consumption end
.q(outputData_out),
.empty(outputEmpty),
.rdreq(outputReady_in)
);
endmodule |
module tb_fifo9togmii();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [8:0] dout;
reg empty;
wire rd_en;
wire rd_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
fifo9togmii fifo9togmii_tb (
.sys_rst(sys_rst),
.dout(dout),
.empty(empty),
.rd_en(rd_en),
.rd_clk(rd_clk),
.gmii_tx_clk(phy_tx_clk),
.gmii_tx_en(gmii_tx_en),
.gmii_txd(gmii_txd)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge rd_clk) begin
if (gmii_tx_en == 1'b1)
$display("gmii_tx_out: %x", gmii_txd);
end
reg [11:0] counter;
reg [8:0] rom [0:4091];
always #1
{empty,dout} <= rom[ counter ];
always @(posedge phy_tx_clk) begin
if (rd_en == 1'b1)
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_fifo9togmii);
$readmemh("./fifo9.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule |
module sky130_fd_sc_lp__and4_lp (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__and4_lp (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule |
module mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter IODELAY_GRP = "IODELAY_MIG",
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000
)
(
input rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output [1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
// input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [RANKS-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n
);
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
// Temporary method to force MC_PHY to generate ODDR associated with
// CK/CK# output only for a single byte lane in the design. All banks
// that won't be generating the CK/CK# will have "UNUSED" as their
// PHY_GENERATE_DDR_CK parameter
localparam TMP_PHY_0_GENERATE_DDR_CK
= (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
localparam TMP_PHY_1_GENERATE_DDR_CK
= (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
localparam TMP_PHY_2_GENERATE_DDR_CK
= (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameter from data mask map parameter
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
localparam PO_OCLKDELAY_INV = "TRUE";
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 2500 ? "DIV2" : "NONE";
localparam real FREQ_REF_MHZ
= 1.0/((tCK/(PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1) /
1000.0) / 1000) ;
localparam real MC_OCLK_DELAY2 = FREQ_REF_MHZ/10000.0 + 0.4548;
localparam real MC_OCLK_DELAY3
= ((0.25 * (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)) -
MC_OCLK_DELAY2 - (PO_OCLKDELAY_INV == "TRUE" ? 1 : 0) * 0.5) ;
localparam real MC_OCLK_DELAY4
= (MC_OCLK_DELAY3 + (MC_OCLK_DELAY3 < 0 )+0) * 64;
localparam real MC_OCLK_DELAY
= MC_OCLK_DELAY4 + ((tCK < 1900 ) || tCK > 3000) ;
// Value expressed as fraction of a full tCK period
localparam real SHIFT = (1 + 0.3);
// Value expressed as fraction of a full tCK period
localparam real OCLK_INTRINSIC_DELAY
= (tCK < 1000) ? 0.708 :
((tCK < 1100) ? 0.748 :
((tCK < 1300) ? 0.742 :
((tCK < 1600) ? 0.709 :
((tCK < 2500) ? 0.637 : 0.425))));
// OCLK_DELAYED due to inversion
localparam real OCLK_DELAY_INV_DELAY
= (PO_OCLKDELAY_INV == "TRUE") ? 0.5 : 0;
localparam real OCLK_DELAY_PERCENT
= (SHIFT - OCLK_INTRINSIC_DELAY - OCLK_DELAY_INV_DELAY) * 100;
localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY + 0.5;
// IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE
= (tCK < 1000) ? 0 :
((tCK < 1330) ? 1 :
((tCK < 2300) ? 3 :
((tCK < 2500) ? 5 : 6)));
/*localparam PHY_0_A_IDELAYE2_IDELAY_VALUE
= (tCK < 1000) ? 4 :
((tCK < 1330) ? 5 :
((tCK < 2300) ? 7 :
((tCK < 2500) ? 9 : 10)));*/
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10; //8
localparam PHY_0_RD_CMD_OFFSET_1 = 10; //8
localparam PHY_0_RD_CMD_OFFSET_2 = 10; //8
localparam PHY_0_RD_CMD_OFFSET_3 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_0 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_1 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_2 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_3 = 10; //8
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if (RANKS == 1) begin : gen_cke_odt
assign ddr_cke = aux_out[0];
if (USE_ODT_PORT == 1) begin: gen_use_odt
assign ddr_odt = aux_out[1];
end else begin
assign ddr_odt = 1'b0;
end
end else begin: gen_2rank_cke_odt
assign ddr_cke = {aux_out[2],aux_out[0]};
if (USE_ODT_PORT == 1) begin: gen_use_odt
assign ddr_odt = {aux_out[3],aux_out[1]};
end else begin
assign ddr_odt = 2'b00;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
mc_phy #
(
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_SYNC_MODE ("TRUE"),
.PHY_DISABLE_SEQ_MATCH ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
.DDR_CLK_SELECT_BANK (TMP_DDR_CLK_SELECT_BANK),
.PHY_0_GENERATE_DDR_CK (TMP_PHY_0_GENERATE_DDR_CK),
.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
.PHY_EVENTS_DELAY (63),
.PHY_FOUR_WINDOW_CLOCKS (18),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_DURATION_0 (6),
.PHY_0_WR_DURATION_1 (6),
.PHY_0_WR_DURATION_2 (6),
.PHY_0_WR_DURATION_3 (6),
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_CMD_OFFSET (10),//for CKE
.IODELAY_GRP (IODELAY_GRP)
)
u_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_ctl_wd (phy_ctl_wd),
.phy_ctl_wr (phy_ctl_wr),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.of_ctl_a_full (phy_cmd_full),
.of_data_a_full (phy_data_full),
.of_ctl_full (),
.of_data_full (),
.idelay_ld (1'b0),
.idelay_ce (1'b0),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (phy_ctl_full),
.phy_ctl_full (),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
);
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
bmod bsub3 (.clk, .n(3));
bmod bsub2 (.clk, .n(2));
bmod bsub1 (.clk, .n(1));
bmod bsub0 (.clk, .n(0));
endmodule |
module bmod
(input clk,
input [31:0] n);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
cmod csub (.clk, .n);
endmodule |
module cmod
(input clk, input [31:0] n);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] clocal;
always @ (posedge clk) clocal <= n;
dmod dsub (.clk, .n);
endmodule |
module dmod (input clk, input [31:0] n);
`ifdef INLINE_D //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] dlocal;
always @ (posedge clk) dlocal <= n;
int cyc;
always @(posedge clk) begin
cyc <= cyc+1;
end
always @(posedge clk) begin
if (cyc>10) begin
`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif
if (csub.clocal !== n) $stop;
if (dlocal !== n) $stop;
end
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule |
module LAG_pl_buffers (push, pop, data_in,
data_out, flags,
clk, rst_n);
// length of PL FIFOs
parameter size = 3;
// number of physical channels
parameter n = 4;
input [n-1:0] push;
input [n-1:0] pop;
input fifo_elements_t data_in [n-1:0];
output fifo_elements_t data_out [n-1:0];
output fifov_flags_t flags [n-1:0];
input clk, rst_n;
genvar i;
generate
for (i=0; i<n; i++) begin:plbufs
// **********************************
// SINGLE FIFO holds complete flit
// **********************************
LAG_fifo_v #(.size(size)
) pl_fifo
(.push(push[i]),
.pop(pop[i]),
.data_in(data_in[i]),
.data_out(data_out[i]),
.flags(flags[i]),
.clk, .rst_n);
end
endgenerate
endmodule |
module ff_sub (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
input [255:0] rx_p,
output reg tx_done = 1'b0,
output reg [255:0] tx_a = 256'd0
);
reg carry;
always @ (posedge clk)
begin
if (!tx_done)
begin
if (carry)
tx_a <= tx_a + rx_p;
tx_done <= 1'b1;
end
if (reset)
begin
{carry, tx_a} <= rx_a - rx_b;
tx_done <= 1'b0;
end
end
endmodule |
module axis_stat_counter #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16,
parameter TICK_COUNT_ENABLE = 1,
parameter TICK_COUNT_WIDTH = 32,
parameter BYTE_COUNT_ENABLE = 1,
parameter BYTE_COUNT_WIDTH = 32,
parameter FRAME_COUNT_ENABLE = 1,
parameter FRAME_COUNT_WIDTH = 32
)
(
input wire clk,
input wire rst,
/*
* AXI monitor
*/
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
/*
* AXI status data output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
input wire trigger,
/*
* Status
*/
output wire busy
);
localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
localparam TICK_COUNT_BYTE_WIDTH = (TICK_COUNT_WIDTH + 7) / 8;
localparam BYTE_COUNT_BYTE_WIDTH = (BYTE_COUNT_WIDTH + 7) / 8;
localparam FRAME_COUNT_BYTE_WIDTH = (FRAME_COUNT_WIDTH + 7) / 8;
localparam TOTAL_LENGTH = TAG_BYTE_WIDTH + TICK_COUNT_BYTE_WIDTH + BYTE_COUNT_BYTE_WIDTH + FRAME_COUNT_BYTE_WIDTH;
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_OUTPUT_DATA = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [TICK_COUNT_WIDTH-1:0] tick_count_reg = 0, tick_count_next;
reg [BYTE_COUNT_WIDTH-1:0] byte_count_reg = 0, byte_count_next;
reg [FRAME_COUNT_WIDTH-1:0] frame_count_reg = 0, frame_count_next;
reg frame_reg = 0, frame_next;
reg store_output;
reg [$clog2(TOTAL_LENGTH)-1:0] frame_ptr_reg = 0, frame_ptr_next;
reg [TICK_COUNT_WIDTH-1:0] tick_count_output_reg = 0;
reg [BYTE_COUNT_WIDTH-1:0] byte_count_output_reg = 0;
reg [FRAME_COUNT_WIDTH-1:0] frame_count_output_reg = 0;
reg busy_reg = 0;
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign busy = busy_reg;
integer offset, i, bit_cnt;
always @* begin
state_next = 2'bz;
tick_count_next = tick_count_reg;
byte_count_next = byte_count_reg;
frame_count_next = frame_count_reg;
frame_next = frame_reg;
output_axis_tdata_int = 0;
output_axis_tvalid_int = 0;
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
store_output = 0;
frame_ptr_next = frame_ptr_reg;
// data readout
case (state_reg)
STATE_IDLE: begin
if (trigger) begin
store_output = 1;
tick_count_next = 0;
byte_count_next = 0;
frame_count_next = 0;
frame_ptr_next = 0;
if (output_axis_tready_int) begin
frame_ptr_next = 1;
if (TAG_ENABLE) begin
output_axis_tdata_int = tag[(TAG_BYTE_WIDTH-1)*8 +: 8];
end else if (TICK_COUNT_ENABLE) begin
output_axis_tdata_int = tick_count_reg[(TICK_COUNT_BYTE_WIDTH-1)*8 +: 8];
end else if (BYTE_COUNT_ENABLE) begin
output_axis_tdata_int = byte_count_reg[(BYTE_COUNT_BYTE_WIDTH-1)*8 +: 8];
end else if (FRAME_COUNT_ENABLE) begin
output_axis_tdata_int = frame_count_reg[(FRAME_COUNT_BYTE_WIDTH-1)*8 +: 8];
end
output_axis_tvalid_int = 1;
end
state_next = STATE_OUTPUT_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_OUTPUT_DATA: begin
if (output_axis_tready_int) begin
state_next = STATE_OUTPUT_DATA;
frame_ptr_next = frame_ptr_reg + 1;
output_axis_tvalid_int = 1;
offset = 0;
if (TAG_ENABLE) begin
for (i = TAG_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tag[i*8 +: 8];
end
offset = offset + 1;
end
end
if (TICK_COUNT_ENABLE) begin
for (i = TICK_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tick_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (BYTE_COUNT_ENABLE) begin
for (i = BYTE_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = byte_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (FRAME_COUNT_ENABLE) begin
for (i = FRAME_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = frame_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (frame_ptr_reg == offset-1) begin
output_axis_tlast_int = 1;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_OUTPUT_DATA;
end
end
endcase
// stats collection
// increment tick count by number of words that can be transferred per cycle
tick_count_next = tick_count_next + KEEP_WIDTH;
if (monitor_axis_tready & monitor_axis_tvalid) begin
// valid transfer cycle
// increment byte count by number of words transferred
bit_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
byte_count_next = byte_count_next + bit_cnt;
// count frames
if (monitor_axis_tlast) begin
// end of frame
frame_next = 0;
end else if (~frame_reg) begin
// first word after end of frame
frame_count_next = frame_count_next + 1;
frame_next = 1;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
tick_count_reg <= 0;
byte_count_reg <= 0;
frame_count_reg <= 0;
frame_reg <= 0;
frame_ptr_reg <= 0;
busy_reg <= 0;
tick_count_output_reg <= 0;
byte_count_output_reg <= 0;
frame_count_output_reg <= 0;
end else begin
state_reg <= state_next;
tick_count_reg <= tick_count_next;
byte_count_reg <= byte_count_next;
frame_count_reg <= frame_count_next;
frame_reg <= frame_next;
frame_ptr_reg <= frame_ptr_next;
busy_reg <= state_next != STATE_IDLE;
if (store_output) begin
tick_count_output_reg <= tick_count_reg;
byte_count_output_reg <= byte_count_reg;
frame_count_output_reg <= frame_count_reg;
end
end
end
// output datapath logic
reg [7:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [7:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule |
module calc(
// clock
input wire clk,
// pushbuttons
input wire start_in, pause_in,
input wire record_in, recall_mode_in,
// switchs
input wire display_mode, // 0 is min/sec
input wire[3:0] reg_address,
// seven seg
output wire[3:0] anode,
output wire[7:0] segment,
// LEDs
output wire started_LED,
output wire paused_LED,
output wire write_LED,
output wire mode_LED);
// wire seven seg
reg[15:0] display_num;
initial begin
display_num = 16'b0;
end
display_16 seven_seg(clk, display_num, anode[3:0], segment[7:0]);
// debounce push buttons
wire start_stop, pause_resume, record_recall, recall_mode;
pbdebounce p0(clk, start_in, start_stop);
pbdebounce p1(clk, pause_in, pause_resume);
pbdebounce p2(clk, record_in, record_recall);
pbdebounce p3(clk, recall_mode_in, recall_mode);
// the stopwatch
wire[23:0] result;
wire reg_exceed;
stop_watch sw(clk,
start_stop, pause_resume,
record_recall, recall_mode,
reg_address,
reg_exceed,
started_LED, paused_LED,
write_LED, mode_LED,
result);
// choose display
always @* begin
if (reg_exceed)
display_num = 16'hEFFD; // F will display "r", D will display "."
else
case(display_mode)
1'b0: display_num = result[23:8];
1'b1: display_num = result[15:0];
endcase
end
endmodule |
module
BFM_MAIN
(
SYSCLK
,
SYSRSTN
,
PCLK
,
HCLK
,
HRESETN
,
HADDR
,
HBURST
,
HMASTLOCK
,
HPROT
,
HSIZE
,
HTRANS
,
HWRITE
,
HWDATA
,
HRDATA
,
HREADY
,
HRESP
,
HSEL
,
INTERRUPT
,
GP_OUT
,
GP_IN
,
EXT_WR
,
EXT_RD
,
EXT_ADDR
,
EXT_DATA
,
EXT_WAIT
,
CON_ADDR
,
CON_DATA
,
CON_RD
,
CON_WR
,
CON_BUSY
,
INSTR_OUT
,
INSTR_IN
,
FINISHED
,
FAILED
)
;
parameter
OPMODE
=
0
;
parameter
VECTFILE
=
"test.vec"
;
parameter
MAX_INSTRUCTIONS
=
16384
;
parameter
MAX_STACK
=
1024
;
parameter
MAX_MEMTEST
=
65536
;
parameter
TPD
=
1
;
parameter
DEBUGLEVEL
=
-
1
;
parameter
CON_SPULSE
=
0
;
parameter
ARGVALUE0
=
0
;
parameter
ARGVALUE1
=
0
;
parameter
ARGVALUE2
=
0
;
parameter
ARGVALUE3
=
0
;
parameter
ARGVALUE4
=
0
;
parameter
ARGVALUE5
=
0
;
parameter
ARGVALUE6
=
0
;
parameter
ARGVALUE7
=
0
;
parameter
ARGVALUE8
=
0
;
parameter
ARGVALUE9
=
0
;
parameter
ARGVALUE10
=
0
;
parameter
ARGVALUE11
=
0
;
parameter
ARGVALUE12
=
0
;
parameter
ARGVALUE13
=
0
;
parameter
ARGVALUE14
=
0
;
parameter
ARGVALUE15
=
0
;
parameter
ARGVALUE16
=
0
;
parameter
ARGVALUE17
=
0
;
parameter
ARGVALUE18
=
0
;
parameter
ARGVALUE19
=
0
;
parameter
ARGVALUE20
=
0
;
parameter
ARGVALUE21
=
0
;
parameter
ARGVALUE22
=
0
;
parameter
ARGVALUE23
=
0
;
parameter
ARGVALUE24
=
0
;
parameter
ARGVALUE25
=
0
;
parameter
ARGVALUE26
=
0
;
parameter
ARGVALUE27
=
0
;
parameter
ARGVALUE28
=
0
;
parameter
ARGVALUE29
=
0
;
parameter
ARGVALUE30
=
0
;
parameter
ARGVALUE31
=
0
;
parameter
ARGVALUE32
=
0
;
parameter
ARGVALUE33
=
0
;
parameter
ARGVALUE34
=
0
;
parameter
ARGVALUE35
=
0
;
parameter
ARGVALUE36
=
0
;
parameter
ARGVALUE37
=
0
;
parameter
ARGVALUE38
=
0
;
parameter
ARGVALUE39
=
0
;
parameter
ARGVALUE40
=
0
;
parameter
ARGVALUE41
=
0
;
parameter
ARGVALUE42
=
0
;
parameter
ARGVALUE43
=
0
;
parameter
ARGVALUE44
=
0
;
parameter
ARGVALUE45
=
0
;
parameter
ARGVALUE46
=
0
;
parameter
ARGVALUE47
=
0
;
parameter
ARGVALUE48
=
0
;
parameter
ARGVALUE49
=
0
;
parameter
ARGVALUE50
=
0
;
parameter
ARGVALUE51
=
0
;
parameter
ARGVALUE52
=
0
;
parameter
ARGVALUE53
=
0
;
parameter
ARGVALUE54
=
0
;
parameter
ARGVALUE55
=
0
;
parameter
ARGVALUE56
=
0
;
parameter
ARGVALUE57
=
0
;
parameter
ARGVALUE58
=
0
;
parameter
ARGVALUE59
=
0
;
parameter
ARGVALUE60
=
0
;
parameter
ARGVALUE61
=
0
;
parameter
ARGVALUE62
=
0
;
parameter
ARGVALUE63
=
0
;
parameter
ARGVALUE64
=
0
;
parameter
ARGVALUE65
=
0
;
parameter
ARGVALUE66
=
0
;
parameter
ARGVALUE67
=
0
;
parameter
ARGVALUE68
=
0
;
parameter
ARGVALUE69
=
0
;
parameter
ARGVALUE70
=
0
;
parameter
ARGVALUE71
=
0
;
parameter
ARGVALUE72
=
0
;
parameter
ARGVALUE73
=
0
;
parameter
ARGVALUE74
=
0
;
parameter
ARGVALUE75
=
0
;
parameter
ARGVALUE76
=
0
;
parameter
ARGVALUE77
=
0
;
parameter
ARGVALUE78
=
0
;
parameter
ARGVALUE79
=
0
;
parameter
ARGVALUE80
=
0
;
parameter
ARGVALUE81
=
0
;
parameter
ARGVALUE82
=
0
;
parameter
ARGVALUE83
=
0
;
parameter
ARGVALUE84
=
0
;
parameter
ARGVALUE85
=
0
;
parameter
ARGVALUE86
=
0
;
parameter
ARGVALUE87
=
0
;
parameter
ARGVALUE88
=
0
;
parameter
ARGVALUE89
=
0
;
parameter
ARGVALUE90
=
0
;
parameter
ARGVALUE91
=
0
;
parameter
ARGVALUE92
=
0
;
parameter
ARGVALUE93
=
0
;
parameter
ARGVALUE94
=
0
;
parameter
ARGVALUE95
=
0
;
parameter
ARGVALUE96
=
0
;
parameter
ARGVALUE97
=
0
;
parameter
ARGVALUE98
=
0
;
parameter
ARGVALUE99
=
0
;
localparam
[
1
:
(
3
)
*
8
]
BFMA1O
=
"2.1"
;
localparam
[
1
:
(
7
)
*
8
]
BFMA1I
=
"22Dec08"
;
input
SYSCLK
;
input
SYSRSTN
;
output
PCLK
;
wire
PCLK
;
output
HCLK
;
wire
HCLK
;
output
HRESETN
;
wire
#
TPD
HRESETN
;
output
[
31
:
0
]
HADDR
;
wire
[
31
:
0
]
#
TPD
HADDR
;
output
[
2
:
0
]
HBURST
;
wire
[
2
:
0
]
#
TPD
HBURST
;
output
HMASTLOCK
;
wire
#
TPD
HMASTLOCK
;
output
[
3
:
0
]
HPROT
;
wire
[
3
:
0
]
#
TPD
HPROT
;
output
[
2
:
0
]
HSIZE
;
wire
[
2
:
0
]
#
TPD
HSIZE
;
output
[
1
:
0
]
HTRANS
;
wire
[
1
:
0
]
#
TPD
HTRANS
;
output
HWRITE
;
wire
#
TPD
HWRITE
;
output
[
31
:
0
]
HWDATA
;
wire
[
31
:
0
]
#
TPD
HWDATA
;
input
[
31
:
0
]
HRDATA
;
input
HREADY
;
input
HRESP
;
output
[
15
:
0
]
HSEL
;
wire
[
15
:
0
]
#
TPD
HSEL
;
input
[
255
:
0
]
INTERRUPT
;
output
[
31
:
0
]
GP_OUT
;
wire
[
31
:
0
]
#
TPD
GP_OUT
;
input
[
31
:
0
]
GP_IN
;
output
EXT_WR
;
wire
#
TPD
EXT_WR
;
output
EXT_RD
;
wire
#
TPD
EXT_RD
;
output
[
31
:
0
]
EXT_ADDR
;
wire
[
31
:
0
]
#
TPD
EXT_ADDR
;
inout
[
31
:
0
]
EXT_DATA
;
wire
[
31
:
0
]
#
TPD
EXT_DATA
;
input
EXT_WAIT
;
input
[
15
:
0
]
CON_ADDR
;
inout
[
31
:
0
]
CON_DATA
;
wire
[
31
:
0
]
#
TPD
CON_DATA
;
wire
[
31
:
0
]
BFMA1l
;
input
CON_RD
;
input
CON_WR
;
output
CON_BUSY
;
reg
CON_BUSY
;
output
[
31
:
0
]
INSTR_OUT
;
reg
[
31
:
0
]
INSTR_OUT
;
input
[
31
:
0
]
INSTR_IN
;
output
FINISHED
;
wire
#
TPD
FINISHED
;
output
FAILED
;
wire
#
TPD
FAILED
;
localparam
BFMA1OI
=
0
;
wire
BFMA1II
;
integer
BFMA1lI
[
0
:
255
]
;
integer
BFMA1Ol
[
0
:
MAX_INSTRUCTIONS
-
1
]
;
reg
BFMA1Il
;
reg
[
2
:
0
]
BFMA1ll
;
reg
BFMA1O0
;
reg
[
3
:
0
]
BFMA1I0
;
reg
[
1
:
0
]
BFMA1l0
;
reg
BFMA1O1
;
wire
[
31
:
0
]
BFMA1I1
;
reg
[
31
:
0
]
BFMA1l1
;
reg
[
31
:
0
]
BFMA1OOI
;
reg
[
2
:
0
]
BFMA1IOI
;
reg
[
2
:
0
]
BFMA1lOI
;
reg
[
15
:
0
]
BFMA1OII
;
reg
BFMA1III
;
reg
BFMA1lII
;
reg
BFMA1OlI
;
reg
BFMA1IlI
;
reg
BFMA1llI
;
reg
BFMA1O0I
;
reg
BFMA1I0I
;
reg
BFMA1l0I
;
reg
[
31
:
0
]
BFMA1O1I
;
reg
[
31
:
0
]
BFMA1I1I
;
reg
[
31
:
0
]
BFMA1l1I
;
reg
[
31
:
0
]
BFMA1OOl
;
reg
[
31
:
0
]
BFMA1IOl
;
reg
[
31
:
0
]
BFMA1lOl
;
reg
[
31
:
0
]
BFMA1OIl
;
reg
[
31
:
0
]
BFMA1IIl
;
integer
BFMA1lIl
;
reg
BFMA1Oll
;
reg
BFMA1Ill
;
reg
[
31
:
0
]
BFMA1lll
;
reg
[
31
:
0
]
BFMA1O0l
;
integer
BFMA1I0l
;
reg
BFMA1l0l
;
reg
BFMA1O1l
;
reg
BFMA1I1l
;
reg
BFMA1l1l
;
reg
BFMA1OO0
;
wire
[
31
:
0
]
BFMA1IO0
;
reg
[
31
:
0
]
BFMA1lO0
;
reg
[
31
:
0
]
BFMA1OI0
;
reg
[
31
:
0
]
BFMA1II0
;
wire
[
31
:
0
]
BFMA1lI0
;
reg
[
31
:
0
]
BFMA1Ol0
;
reg
BFMA1Il0
;
reg
BFMA1ll0
;
integer
BFMA1O00
;
integer
BFMA1I00
;
reg
BFMA1l00
=
1
'b
0
;
reg
[
31
:
0
]
BFMA1O10
;
reg
[
1
:
(
80
)
*
8
]
BFMA1I10
;
reg
BFMA1l10
;
reg
BFMA1OO1
;
reg
BFMA1IO1
;
reg
BFMA1lO1
;
reg
BFMA1OI1
;
reg
BFMA1II1
;
parameter
[
31
:
0
]
BFMA1lI1
=
{
32
{
1
'b
0
}
}
;
parameter
[
255
:
0
]
BFMA1Ol1
=
{
256
{
1
'b
0
}
}
;
parameter
BFMA1Il1
=
TPD
*
1
;
assign
BFMA1II
=
SYSCLK
;
integer
BFMA1ll1
[
0
:
MAX_STACK
-
1
]
;
integer
BFMA1O01
;
integer
BFMA1I01
;
integer
BFMA1l01
;
integer
DEBUG
;
integer
BFMA1O11
;
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
localparam
BFMA1I11
=
22
;
localparam
BFMA1l11
=
0
;
localparam
BFMA1OOOI
=
4
;
localparam
BFMA1IOOI
=
8
;
localparam
BFMA1lOOI
=
12
;
localparam
BFMA1OIOI
=
16
;
localparam
BFMA1IIOI
=
20
;
localparam
BFMA1lIOI
=
24
;
localparam
BFMA1OlOI
=
28
;
localparam
BFMA1IlOI
=
32
;
localparam
BFMA1llOI
=
36
;
localparam
BFMA1O0OI
=
40
;
localparam
BFMA1I0OI
=
44
;
localparam
BFMA1l0OI
=
48
;
localparam
BFMA1O1OI
=
52
;
localparam
BFMA1I1OI
=
56
;
localparam
BFMA1l1OI
=
60
;
localparam
BFMA1OOII
=
64
;
localparam
BFMA1IOII
=
68
;
localparam
BFMA1lOII
=
72
;
localparam
BFMA1OIII
=
76
;
localparam
BFMA1IIII
=
80
;
localparam
BFMA1lIII
=
100
;
localparam
BFMA1OlII
=
101
;
localparam
BFMA1IlII
=
102
;
localparam
BFMA1llII
=
103
;
localparam
BFMA1O0II
=
104
;
localparam
BFMA1I0II
=
105
;
localparam
BFMA1l0II
=
106
;
localparam
BFMA1O1II
=
107
;
localparam
BFMA1I1II
=
108
;
localparam
BFMA1l1II
=
109
;
localparam
BFMA1OOlI
=
110
;
localparam
BFMA1IOlI
=
111
;
localparam
BFMA1lOlI
=
112
;
localparam
BFMA1OIlI
=
113
;
localparam
BFMA1IIlI
=
114
;
localparam
BFMA1lIlI
=
115
;
localparam
BFMA1OllI
=
128
;
localparam
BFMA1IllI
=
129
;
localparam
BFMA1lllI
=
130
;
localparam
BFMA1O0lI
=
131
;
localparam
BFMA1I0lI
=
132
;
localparam
BFMA1l0lI
=
133
;
localparam
BFMA1O1lI
=
134
;
localparam
BFMA1I1lI
=
135
;
localparam
BFMA1l1lI
=
136
;
localparam
BFMA1OO0I
=
137
;
localparam
BFMA1IO0I
=
138
;
localparam
BFMA1lO0I
=
139
;
localparam
BFMA1OI0I
=
140
;
localparam
BFMA1II0I
=
141
;
localparam
BFMA1lI0I
=
142
;
localparam
BFMA1Ol0I
=
150
;
localparam
BFMA1Il0I
=
151
;
localparam
BFMA1ll0I
=
152
;
localparam
BFMA1O00I
=
153
;
localparam
BFMA1I00I
=
154
;
localparam
BFMA1l00I
=
160
;
localparam
BFMA1O10I
=
161
;
localparam
BFMA1I10I
=
162
;
localparam
BFMA1l10I
=
163
;
localparam
BFMA1OO1I
=
164
;
localparam
BFMA1IO1I
=
165
;
localparam
BFMA1lO1I
=
166
;
localparam
BFMA1OI1I
=
167
;
localparam
BFMA1II1I
=
168
;
localparam
BFMA1lI1I
=
169
;
localparam
BFMA1Ol1I
=
170
;
localparam
BFMA1Il1I
=
171
;
localparam
BFMA1ll1I
=
172
;
localparam
BFMA1O01I
=
200
;
localparam
BFMA1I01I
=
201
;
localparam
BFMA1l01I
=
202
;
localparam
BFMA1O11I
=
203
;
localparam
BFMA1I11I
=
204
;
localparam
BFMA1l11I
=
205
;
localparam
BFMA1OOOl
=
206
;
localparam
BFMA1IOOl
=
207
;
localparam
BFMA1lOOl
=
208
;
localparam
BFMA1OIOl
=
209
;
localparam
BFMA1IIOl
=
210
;
localparam
BFMA1lIOl
=
211
;
localparam
BFMA1OlOl
=
212
;
localparam
BFMA1IlOl
=
213
;
localparam
BFMA1llOl
=
214
;
localparam
BFMA1O0Ol
=
215
;
localparam
BFMA1I0Ol
=
216
;
localparam
BFMA1l0Ol
=
217
;
localparam
BFMA1O1Ol
=
218
;
localparam
BFMA1I1Ol
=
219
;
localparam
BFMA1l1Ol
=
220
;
localparam
BFMA1OOIl
=
221
;
localparam
BFMA1IOIl
=
222
;
localparam
BFMA1lOIl
=
250
;
localparam
BFMA1OIIl
=
251
;
localparam
BFMA1IIIl
=
252
;
localparam
BFMA1lIIl
=
253
;
localparam
BFMA1OlIl
=
254
;
localparam
BFMA1IlIl
=
255
;
localparam
BFMA1llIl
=
1001
;
localparam
BFMA1O0Il
=
1002
;
localparam
BFMA1I0Il
=
1003
;
localparam
BFMA1l0Il
=
1004
;
localparam
BFMA1O1Il
=
1005
;
localparam
BFMA1I1Il
=
1006
;
localparam
BFMA1l1Il
=
1007
;
localparam
BFMA1OOll
=
1008
;
localparam
BFMA1IOll
=
1009
;
localparam
BFMA1lOll
=
1010
;
localparam
BFMA1OIll
=
1011
;
localparam
BFMA1IIll
=
1012
;
localparam
BFMA1lIll
=
1013
;
localparam
BFMA1Olll
=
1014
;
localparam
BFMA1Illl
=
1015
;
localparam
BFMA1llll
=
1016
;
localparam
BFMA1O0ll
=
1017
;
localparam
BFMA1I0ll
=
1018
;
localparam
BFMA1l0ll
=
1019
;
localparam
BFMA1O1ll
=
1020
;
localparam
BFMA1I1ll
=
1021
;
localparam
BFMA1l1ll
=
1022
;
localparam
BFMA1OO0l
=
1023
;
localparam
BFMA1IO0l
=
0
;
localparam
BFMA1lO0l
=
1
;
localparam
BFMA1OI0l
=
2
;
localparam
BFMA1II0l
=
3
;
localparam
BFMA1lI0l
=
4
;
localparam
BFMA1Ol0l
=
5
;
localparam
BFMA1Il0l
=
6
;
localparam
BFMA1ll0l
=
7
;
localparam
BFMA1O00l
=
8
;
localparam
BFMA1I00l
=
0
;
localparam
BFMA1l00l
=
1
;
localparam
BFMA1O10l
=
2
;
localparam
BFMA1I10l
=
3
;
localparam
BFMA1l10l
=
4
;
localparam
BFMA1OO1l
=
32
'h
00000000
;
localparam
BFMA1IO1l
=
32
'h
00002000
;
localparam
BFMA1lO1l
=
32
'h
00004000
;
localparam
BFMA1OI1l
=
32
'h
00006000
;
localparam
BFMA1II1l
=
32
'h
00008000
;
localparam
[
1
:
0
]
BFMA1lI1l
=
0
;
localparam
[
1
:
0
]
BFMA1Ol1l
=
1
;
localparam
[
1
:
0
]
BFMA1Il1l
=
2
;
localparam
[
1
:
0
]
BFMA1ll1l
=
3
;
function
integer
BFMA1O01l
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
BFMA1O01l
=
BFMA1ll1l
;
end
endfunction
function
integer
to_int_unsigned
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
to_int_unsigned
=
BFMA1ll1l
;
end
endfunction
function
integer
to_int_signed
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
to_int_signed
=
BFMA1ll1l
;
end
endfunction
function
[
31
:
0
]
to_slv32
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
reg
[
31
:
0
]
BFMA1I01l
;
begin
BFMA1I01l
=
BFMA1ll1l
;
to_slv32
=
BFMA1I01l
;
end
endfunction
function
[
31
:
0
]
BFMA1l01l
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
reg
BFMA1lOO0
;
begin
BFMA1IOO0
=
{
32
{
1
'b
0
}
}
;
case
(
BFMA1OOO0
)
0
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
10
:
begin
BFMA1IOO0
[
23
:
16
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
31
:
24
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'b
001
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
$display
(
"BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
BFMA1IOO0
[
31
:
16
]
=
BFMA1l11l
[
15
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
31
:
16
]
=
BFMA1l11l
[
15
:
0
]
;
$display
(
"BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
3
'b
010
:
begin
BFMA1IOO0
=
BFMA1l11l
;
case
(
BFMA1I11l
)
2
'b
00
:
begin
end
2
'b
01
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)"
)
;
end
2
'b
11
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
1
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
10
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'b
001
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
case
(
BFMA1I11l
)
2
'b
00
:
begin
end
2
'b
01
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)"
)
;
end
2
'b
11
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
2
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
8
:
begin
BFMA1IOO0
=
BFMA1l11l
;
end
default
:
begin
$display
(
"Illegal Alignment mode (ERROR)"
)
;
end
endcase
BFMA1l01l
=
BFMA1IOO0
;
end
endfunction
function
[
31
:
0
]
BFMA1OIO0
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
begin
BFMA1IOO0
=
BFMA1l01l
(
BFMA1O11l
,
BFMA1I11l
,
BFMA1l11l
,
BFMA1OOO0
)
;
BFMA1OIO0
=
BFMA1IOO0
;
end
endfunction
function
[
31
:
0
]
BFMA1IIO0
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
reg
BFMA1lOO0
;
begin
if
(
BFMA1OOO0
==
8
)
begin
BFMA1IOO0
=
BFMA1l11l
;
end
else
begin
BFMA1IOO0
=
0
;
BFMA1lOO0
=
BFMA1I11l
[
1
]
;
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
2
'b
01
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
15
:
8
]
;
2
'b
10
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
23
:
16
]
;
2
'b
11
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
31
:
24
]
;
default
:
begin
end
endcase
end
3
'b
001
:
begin
case
(
BFMA1lOO0
)
1
'b
0
:
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
1
'b
1
:
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
31
:
16
]
;
default
:
begin
end
endcase
end
3
'b
010
:
begin
BFMA1IOO0
=
BFMA1l11l
;
end
default
:
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
endcase
end
BFMA1IIO0
=
BFMA1IOO0
;
end
endfunction
function
integer
BFMA1lIO0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1OlO0
;
begin
BFMA1OlO0
=
BFMA1ll1l
;
BFMA1lIO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1IlO0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
'h
62
;
end
1
:
begin
BFMA1OlO0
=
'h
68
;
end
2
:
begin
BFMA1OlO0
=
'h
77
;
end
3
:
begin
BFMA1OlO0
=
'h
78
;
end
default
:
begin
BFMA1OlO0
=
'h
3f
;
end
endcase
BFMA1IlO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1llO0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
input
BFMA1O0O0
;
integer
BFMA1O0O0
;
integer
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
1
;
end
1
:
begin
BFMA1OlO0
=
2
;
end
2
:
begin
BFMA1OlO0
=
4
;
end
3
:
begin
BFMA1OlO0
=
BFMA1O0O0
;
end
default
:
begin
BFMA1OlO0
=
0
;
end
endcase
BFMA1llO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1I0O0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
input
BFMA1l0O0
;
integer
BFMA1l0O0
;
reg
[
2
:
0
]
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
3
'b
000
;
end
1
:
begin
BFMA1OlO0
=
3
'b
001
;
end
2
:
begin
BFMA1OlO0
=
3
'b
010
;
end
3
:
begin
BFMA1OlO0
=
BFMA1l0O0
;
end
default
:
begin
BFMA1OlO0
=
3
'b
XXX
;
end
endcase
BFMA1I0O0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1O1O0
;
input
BFMA1I1O0
;
integer
BFMA1I1O0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
input
BFMA1l1O0
;
integer
BFMA1l1O0
;
input
BFMA1OOI0
;
integer
BFMA1OOI0
;
integer
BFMA1IOI0
;
reg
[
31
:
0
]
BFMA1lOI0
;
reg
[
31
:
0
]
BFMA1OII0
;
reg
[
31
:
0
]
BFMA1III0
;
integer
BFMA1lII0
;
reg
[
63
:
0
]
BFMA1OlI0
;
localparam
[
31
:
0
]
BFMA1IlI0
=
0
;
localparam
[
31
:
0
]
BFMA1llI0
=
1
;
begin
BFMA1lOI0
=
BFMA1ll1l
;
BFMA1OII0
=
BFMA1l1O0
;
BFMA1lII0
=
BFMA1l1O0
;
BFMA1III0
=
{
32
{
1
'b
0
}
}
;
case
(
BFMA1I1O0
)
BFMA1llIl
:
begin
BFMA1III0
=
0
;
end
BFMA1O0Il
:
begin
BFMA1III0
=
BFMA1lOI0
+
BFMA1OII0
;
end
BFMA1I0Il
:
begin
BFMA1III0
=
BFMA1lOI0
-
BFMA1OII0
;
end
BFMA1l0Il
:
begin
BFMA1OlI0
=
BFMA1lOI0
*
BFMA1OII0
;
BFMA1III0
=
BFMA1OlI0
[
31
:
0
]
;
end
BFMA1O1Il
:
begin
BFMA1III0
=
BFMA1lOI0
/
BFMA1OII0
;
end
BFMA1OOll
:
begin
BFMA1III0
=
BFMA1lOI0
&
BFMA1OII0
;
end
BFMA1IOll
:
begin
BFMA1III0
=
BFMA1lOI0
|
BFMA1OII0
;
end
BFMA1lOll
:
begin
BFMA1III0
=
BFMA1lOI0
^
BFMA1OII0
;
end
BFMA1OIll
:
begin
BFMA1III0
=
BFMA1lOI0
^
BFMA1OII0
;
end
BFMA1lIll
:
begin
if
(
BFMA1lII0
==
0
)
begin
BFMA1III0
=
BFMA1lOI0
;
end
else
begin
BFMA1III0
=
BFMA1lOI0
>>
BFMA1lII0
;
end
end
BFMA1IIll
:
begin
if
(
BFMA1lII0
==
0
)
begin
BFMA1III0
=
BFMA1lOI0
;
end
else
begin
BFMA1III0
=
BFMA1lOI0
<<
BFMA1lII0
;
end
end
BFMA1l1Il
:
begin
BFMA1OlI0
=
{
BFMA1IlI0
,
BFMA1llI0
}
;
if
(
BFMA1lII0
>
0
)
begin
begin
:
BFMA1O0I0
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
1
;
BFMA1I0I0
<=
BFMA1lII0
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OlI0
=
BFMA1OlI0
[
31
:
0
]
*
BFMA1lOI0
;
end
end
end
BFMA1III0
=
BFMA1OlI0
[
31
:
0
]
;
end
BFMA1Olll
:
begin
if
(
BFMA1lOI0
==
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1Illl
:
begin
if
(
BFMA1lOI0
!=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1llll
:
begin
if
(
BFMA1lOI0
>
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1O0ll
:
begin
if
(
BFMA1lOI0
<
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1I0ll
:
begin
if
(
BFMA1lOI0
>=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1l0ll
:
begin
if
(
BFMA1lOI0
<=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1I1Il
:
begin
BFMA1III0
=
BFMA1lOI0
%
BFMA1OII0
;
end
BFMA1O1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
1
'b
1
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1I1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
1
'b
0
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1l1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
~
BFMA1III0
[
BFMA1l1O0
]
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1OO0l
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
0
;
BFMA1III0
[
0
]
=
BFMA1lOI0
[
BFMA1l1O0
]
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
default
:
begin
$display
(
"Illegal Maths Operator (FAILURE)"
)
;
$stop
;
end
endcase
BFMA1IOI0
=
BFMA1III0
;
if
(
BFMA1OOI0
>=
4
)
begin
$display
(
"Calculated %d = %d (%d) %d"
,
BFMA1IOI0
,
BFMA1ll1l
,
BFMA1I1O0
,
BFMA1l1O0
)
;
end
BFMA1O1O0
=
BFMA1IOI0
;
end
endfunction
function
[
31
:
0
]
BFMA1l0I0
;
input
[
31
:
0
]
BFMA1ll1l
;
reg
[
31
:
0
]
BFMA1O1I0
;
begin
BFMA1O1I0
=
BFMA1ll1l
;
BFMA1O1I0
=
0
;
begin
:
BFMA1I1I0
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
31
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
if
(
(
BFMA1ll1l
[
BFMA1I0I0
]
)
==
1
'b
1
)
begin
BFMA1O1I0
[
BFMA1I0I0
]
=
1
'b
1
;
end
end
end
BFMA1l0I0
=
BFMA1O1I0
;
end
endfunction
function
integer
BFMA1l1I0
;
input
BFMA1OOl0
;
integer
BFMA1OOl0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IOl0
;
integer
BFMA1lOl0
;
begin
BFMA1lOl0
=
BFMA1OOl0
/
BFMA1ll1l
;
BFMA1IOl0
=
BFMA1OOl0
-
BFMA1lOl0
*
BFMA1ll1l
;
BFMA1l1I0
=
BFMA1IOl0
;
end
endfunction
function
integer
BFMA1OIl0
;
input
BFMA1OOl0
;
integer
BFMA1OOl0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IOl0
;
integer
BFMA1lOl0
;
begin
BFMA1lOl0
=
BFMA1OOl0
/
BFMA1ll1l
;
BFMA1IOl0
=
BFMA1OOl0
-
BFMA1lOl0
*
BFMA1ll1l
;
BFMA1OIl0
=
BFMA1lOl0
;
end
endfunction
function
integer
to_boolean
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IIl0
;
begin
BFMA1IIl0
=
0
;
if
(
BFMA1ll1l
!=
0
)
BFMA1IIl0
=
1
;
to_boolean
=
BFMA1IIl0
;
end
endfunction
function
integer
BFMA1lIl0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
reg
[
31
:
0
]
BFMA1Ill0
;
reg
[
31
:
0
]
BFMA1lll0
;
reg
BFMA1O0l0
;
begin
BFMA1Ill0
=
BFMA1Oll0
;
BFMA1O0l0
=
1
'b
1
;
BFMA1lll0
[
0
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
;
BFMA1lll0
[
1
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
0
]
;
BFMA1lll0
[
2
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
1
]
;
BFMA1lll0
[
3
]
=
BFMA1Ill0
[
2
]
;
BFMA1lll0
[
4
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
3
]
;
BFMA1lll0
[
5
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
4
]
;
BFMA1lll0
[
6
]
=
BFMA1Ill0
[
5
]
;
BFMA1lll0
[
7
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
6
]
;
BFMA1lll0
[
8
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
7
]
;
BFMA1lll0
[
9
]
=
BFMA1Ill0
[
8
]
;
BFMA1lll0
[
10
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
9
]
;
BFMA1lll0
[
11
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
10
]
;
BFMA1lll0
[
12
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
11
]
;
BFMA1lll0
[
13
]
=
BFMA1Ill0
[
12
]
;
BFMA1lll0
[
14
]
=
BFMA1Ill0
[
13
]
;
BFMA1lll0
[
15
]
=
BFMA1Ill0
[
14
]
;
BFMA1lll0
[
16
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
15
]
;
BFMA1lll0
[
17
]
=
BFMA1Ill0
[
16
]
;
BFMA1lll0
[
18
]
=
BFMA1Ill0
[
17
]
;
BFMA1lll0
[
19
]
=
BFMA1Ill0
[
18
]
;
BFMA1lll0
[
20
]
=
BFMA1Ill0
[
19
]
;
BFMA1lll0
[
21
]
=
BFMA1Ill0
[
20
]
;
BFMA1lll0
[
22
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
21
]
;
BFMA1lll0
[
23
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
22
]
;
BFMA1lll0
[
24
]
=
BFMA1Ill0
[
23
]
;
BFMA1lll0
[
25
]
=
BFMA1Ill0
[
24
]
;
BFMA1lll0
[
26
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
25
]
;
BFMA1lll0
[
27
]
=
BFMA1Ill0
[
26
]
;
BFMA1lll0
[
28
]
=
BFMA1Ill0
[
27
]
;
BFMA1lll0
[
29
]
=
BFMA1Ill0
[
28
]
;
BFMA1lll0
[
30
]
=
BFMA1Ill0
[
29
]
;
BFMA1lll0
[
31
]
=
BFMA1Ill0
[
30
]
;
BFMA1lIl0
=
BFMA1lll0
;
end
endfunction
function
integer
BFMA1I0l0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1l0l0
;
integer
BFMA1I0I0
;
reg
[
31
:
0
]
BFMA1Ill0
;
begin
BFMA1Ill0
=
BFMA1Oll0
;
for
(
BFMA1I0I0
=
31
;
BFMA1I0I0
>=
BFMA1O11l
;
BFMA1I0I0
=
BFMA1I0I0
-
1
)
BFMA1Ill0
[
BFMA1I0I0
]
=
0
;
BFMA1l0l0
=
BFMA1Ill0
;
BFMA1I0l0
=
BFMA1l0l0
;
end
endfunction
function
integer
BFMA1O1l0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1l0l0
;
reg
[
31
:
0
]
BFMA1Ill0
;
integer
BFMA1I1l0
;
integer
BFMA1I0I0
;
begin
case
(
BFMA1O11l
)
1
:
begin
BFMA1I1l0
=
0
;
end
2
:
begin
BFMA1I1l0
=
1
;
end
4
:
begin
BFMA1I1l0
=
2
;
end
8
:
begin
BFMA1I1l0
=
3
;
end
16
:
begin
BFMA1I1l0
=
4
;
end
32
:
begin
BFMA1I1l0
=
5
;
end
64
:
begin
BFMA1I1l0
=
6
;
end
128
:
begin
BFMA1I1l0
=
7
;
end
256
:
begin
BFMA1I1l0
=
8
;
end
512
:
begin
BFMA1I1l0
=
9
;
end
1024
:
begin
BFMA1I1l0
=
10
;
end
2048
:
begin
BFMA1I1l0
=
11
;
end
4096
:
begin
BFMA1I1l0
=
12
;
end
8192
:
begin
BFMA1I1l0
=
13
;
end
16384
:
begin
BFMA1I1l0
=
14
;
end
32768
:
begin
BFMA1I1l0
=
15
;
end
65536
:
begin
BFMA1I1l0
=
16
;
end
131072
:
BFMA1I1l0
=
17
;
262144
:
BFMA1I1l0
=
18
;
524288
:
BFMA1I1l0
=
19
;
1048576
:
BFMA1I1l0
=
20
;
2097152
:
BFMA1I1l0
=
21
;
4194304
:
BFMA1I1l0
=
22
;
8388608
:
BFMA1I1l0
=
23
;
16777216
:
BFMA1I1l0
=
24
;
33554432
:
BFMA1I1l0
=
25
;
67108864
:
BFMA1I1l0
=
26
;
134217728
:
BFMA1I1l0
=
27
;
268435456
:
BFMA1I1l0
=
28
;
536870912
:
BFMA1I1l0
=
29
;
1073741824
:
BFMA1I1l0
=
30
;
default
:
begin
$display
(
"Random function error (FAILURE)"
)
;
$finish
;
end
endcase
BFMA1Ill0
=
to_slv32
(
BFMA1Oll0
)
;
if
(
BFMA1I1l0
<
31
)
begin
for
(
BFMA1I0I0
=
31
;
BFMA1I0I0
>=
BFMA1I1l0
;
BFMA1I0I0
=
BFMA1I0I0
-
1
)
BFMA1Ill0
[
BFMA1I0I0
]
=
0
;
end
BFMA1l0l0
=
to_int_signed
(
BFMA1Ill0
)
;
BFMA1O1l0
=
BFMA1l0l0
;
end
endfunction
function
bound1k
;
input
BFMA1l1l0
;
integer
BFMA1l1l0
;
input
BFMA1OO00
;
integer
BFMA1OO00
;
reg
[
31
:
0
]
BFMA1IO00
;
reg
BFMA1lO00
;
begin
BFMA1IO00
=
BFMA1OO00
;
BFMA1lO00
=
0
;
case
(
BFMA1l1l0
)
0
:
begin
if
(
BFMA1IO00
[
9
:
0
]
==
10
'b
0000000000
)
begin
BFMA1lO00
=
1
;
end
end
1
:
begin
BFMA1lO00
=
1
;
end
2
:
begin
end
default
:
begin
$display
(
"Illegal Burst Boundary Set (FAILURE)"
)
;
$finish
;
end
endcase
bound1k
=
BFMA1lO00
;
end
endfunction
function
integer
BFMA1OI00
;
input
BFMA1II00
;
integer
BFMA1II00
;
integer
BFMA1lI00
;
integer
BFMA1Ol00
;
integer
BFMA1Il00
;
begin
BFMA1Ol00
=
BFMA1II00
/
65536
;
BFMA1lI00
=
BFMA1II00
%
65536
;
BFMA1Il00
=
2
+
BFMA1lI00
+
1
+
(
(
BFMA1Ol00
-
1
)
/
4
)
;
BFMA1OI00
=
BFMA1Il00
;
end
endfunction
function
[
1
:
(
256
)
*
8
]
BFMA1ll00
;
input
BFMA1O000
;
integer
BFMA1O000
;
reg
[
1
:
(
256
)
*
8
]
BFMA1I000
;
reg
[
1
:
(
256
)
*
8
]
BFMA1l000
;
integer
BFMA1I0I0
;
integer
BFMA1O100
;
integer
BFMA1I100
;
reg
[
31
:
0
]
BFMA1l100
;
integer
BFMA1lI00
;
integer
BFMA1Ol00
;
integer
BFMA1II00
;
integer
BFMA1OO10
;
begin
BFMA1Ol00
=
BFMA1Ol
[
BFMA1O000
+
1
]
/
65536
;
BFMA1lI00
=
BFMA1Ol
[
BFMA1O000
+
1
]
%
65536
;
BFMA1II00
=
2
+
BFMA1lI00
+
1
+
(
(
BFMA1Ol00
-
1
)
/
4
)
;
for
(
BFMA1O100
=
1
;
BFMA1O100
<=
256
*
8
;
BFMA1O100
=
BFMA1O100
+
1
)
BFMA1I000
[
BFMA1O100
]
=
0
;
BFMA1I0I0
=
BFMA1O000
+
2
+
BFMA1lI00
;
BFMA1I100
=
3
;
begin
:
BFMA1IO10
integer
BFMA1O100
;
for
(
BFMA1O100
=
1
;
BFMA1O100
<=
BFMA1Ol00
;
BFMA1O100
=
BFMA1O100
+
1
)
begin
BFMA1l100
=
BFMA1Ol
[
BFMA1I0I0
]
;
for
(
BFMA1OO10
=
1
;
BFMA1OO10
<=
8
;
BFMA1OO10
=
BFMA1OO10
+
1
)
BFMA1I000
[
(
BFMA1O100
-
1
)
*
8
+
BFMA1OO10
]
=
BFMA1l100
[
BFMA1I100
*
8
+
8
-
BFMA1OO10
]
;
if
(
BFMA1I100
==
0
)
begin
BFMA1I0I0
=
BFMA1I0I0
+
1
;
BFMA1I100
=
4
;
end
BFMA1I100
=
BFMA1I100
-
1
;
end
end
case
(
BFMA1lI00
)
0
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
)
;
end
1
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
)
;
end
2
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
end
3
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
)
;
end
4
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
)
;
end
5
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
BFMA1lI
[
6
]
)
;
end
6
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
BFMA1lI
[
6
]
,
BFMA1lI
[
7
]
)
;
end
7
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
BFMA1lI
[
6
]
,
BFMA1lI
[
7
]
,
BFMA1lI
[
8
]
)
;
end
default
:
begin
$display
(
"String Error (FAILURE)"
)
;
end
endcase
BFMA1ll00
=
BFMA1l000
;
end
endfunction
integer
BFMA1lO10
;
integer
BFMA1OI10
;
integer
BFMA1II10
;
integer
BFMA1lI10
;
parameter
[
2
:
0
]
BFMA1Ol10
=
0
;
parameter
[
2
:
0
]
BFMA1Il10
=
1
;
parameter
[
2
:
0
]
BFMA1ll10
=
2
;
parameter
[
2
:
0
]
BFMA1O010
=
3
;
parameter
[
2
:
0
]
BFMA1I010
=
4
;
parameter
[
2
:
0
]
BFMA1l010
=
5
;
integer
BFMA1O110
;
integer
BFMA1I110
;
integer
BFMA1l110
;
integer
BFMA1OOO1
;
integer
BFMA1IOO1
;
reg
[
2
:
0
]
BFMA1lOO1
;
integer
BFMA1OIO1
[
0
:
MAX_MEMTEST
-
1
]
;
integer
BFMA1IIO1
;
integer
BFMA1lIO1
;
integer
BFMA1OlO1
;
integer
BFMA1IlO1
;
reg
BFMA1llO1
;
integer
BFMA1O0O1
;
integer
BFMA1I0O1
;
integer
BFMA1l0O1
;
integer
BFMA1O1O1
;
integer
BFMA1I1O1
;
integer
BFMA1l1O1
;
reg
BFMA1OOI1
;
reg
BFMA1IOI1
;
reg
BFMA1lOI1
;
reg
BFMA1OII1
;
integer
BFMA1III1
;
function
automatic
integer
BFMA1lII1
;
input
BFMA1OlI1
;
input
BFMA1IlI1
;
integer
BFMA1IlI1
;
integer
BFMA1llI1
;
integer
BFMA1O0I1
;
integer
BFMA1I0I1
;
integer
BFMA1l0I1
;
integer
BFMA1O1I1
;
integer
BFMA1I1I1
;
reg
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1l1I1
;
begin
if
(
BFMA1OlI1
)
begin
BFMA1I01l
=
BFMA1IlI1
;
BFMA1O0I1
=
BFMA1I01l
[
30
:
16
]
;
BFMA1I0I1
=
BFMA1I01l
[
14
:
13
]
;
BFMA1l0I1
=
BFMA1I01l
[
12
:
0
]
;
BFMA1O1I1
=
BFMA1I01l
[
12
:
8
]
;
BFMA1I1I1
=
BFMA1I01l
[
7
:
0
]
;
BFMA1l1I1
=
0
;
if
(
(
BFMA1I01l
[
15
]
)
==
1
'b
1
)
begin
BFMA1l1I1
=
BFMA1lII1
(
1
,
BFMA1O0I1
)
;
end
case
(
BFMA1I0I1
)
3
:
begin
case
(
BFMA1O1I1
)
BFMA1I00l
:
begin
case
(
BFMA1I1I1
)
BFMA1lO0l
:
begin
BFMA1llI1
=
BFMA1O01
;
end
BFMA1OI0l
:
begin
BFMA1llI1
=
(
$time
/
1
)
;
end
BFMA1II0l
:
begin
BFMA1llI1
=
DEBUG
;
end
BFMA1lI0l
:
begin
BFMA1llI1
=
BFMA1l01
;
end
BFMA1Ol0l
:
begin
BFMA1llI1
=
BFMA1II10
;
end
BFMA1Il0l
:
begin
BFMA1llI1
=
BFMA1l1O1
-
1
;
end
BFMA1ll0l
:
begin
BFMA1llI1
=
BFMA1O1O1
;
end
BFMA1O00l
:
begin
BFMA1llI1
=
BFMA1I1O1
;
end
default
:
begin
$display
(
"Illegal Parameter P0 (FAILURE)"
)
;
end
endcase
end
BFMA1l00l
:
begin
case
(
BFMA1I1I1
)
0
:
BFMA1llI1
=
ARGVALUE0
;
1
:
BFMA1llI1
=
ARGVALUE1
;
2
:
BFMA1llI1
=
ARGVALUE2
;
3
:
BFMA1llI1
=
ARGVALUE3
;
4
:
BFMA1llI1
=
ARGVALUE4
;
5
:
BFMA1llI1
=
ARGVALUE5
;
6
:
BFMA1llI1
=
ARGVALUE6
;
7
:
BFMA1llI1
=
ARGVALUE7
;
8
:
BFMA1llI1
=
ARGVALUE8
;
9
:
BFMA1llI1
=
ARGVALUE9
;
10
:
BFMA1llI1
=
ARGVALUE10
;
11
:
BFMA1llI1
=
ARGVALUE11
;
12
:
BFMA1llI1
=
ARGVALUE12
;
13
:
BFMA1llI1
=
ARGVALUE13
;
14
:
BFMA1llI1
=
ARGVALUE14
;
15
:
BFMA1llI1
=
ARGVALUE15
;
16
:
BFMA1llI1
=
ARGVALUE16
;
17
:
BFMA1llI1
=
ARGVALUE17
;
18
:
BFMA1llI1
=
ARGVALUE18
;
19
:
BFMA1llI1
=
ARGVALUE19
;
20
:
BFMA1llI1
=
ARGVALUE20
;
21
:
BFMA1llI1
=
ARGVALUE21
;
22
:
BFMA1llI1
=
ARGVALUE22
;
23
:
BFMA1llI1
=
ARGVALUE23
;
24
:
BFMA1llI1
=
ARGVALUE24
;
25
:
BFMA1llI1
=
ARGVALUE25
;
26
:
BFMA1llI1
=
ARGVALUE26
;
27
:
BFMA1llI1
=
ARGVALUE27
;
28
:
BFMA1llI1
=
ARGVALUE28
;
29
:
BFMA1llI1
=
ARGVALUE29
;
30
:
BFMA1llI1
=
ARGVALUE30
;
31
:
BFMA1llI1
=
ARGVALUE31
;
32
:
BFMA1llI1
=
ARGVALUE32
;
33
:
BFMA1llI1
=
ARGVALUE33
;
34
:
BFMA1llI1
=
ARGVALUE34
;
35
:
BFMA1llI1
=
ARGVALUE35
;
36
:
BFMA1llI1
=
ARGVALUE36
;
37
:
BFMA1llI1
=
ARGVALUE37
;
38
:
BFMA1llI1
=
ARGVALUE38
;
39
:
BFMA1llI1
=
ARGVALUE39
;
40
:
BFMA1llI1
=
ARGVALUE40
;
41
:
BFMA1llI1
=
ARGVALUE41
;
42
:
BFMA1llI1
=
ARGVALUE42
;
43
:
BFMA1llI1
=
ARGVALUE43
;
44
:
BFMA1llI1
=
ARGVALUE44
;
45
:
BFMA1llI1
=
ARGVALUE45
;
46
:
BFMA1llI1
=
ARGVALUE46
;
47
:
BFMA1llI1
=
ARGVALUE47
;
48
:
BFMA1llI1
=
ARGVALUE48
;
49
:
BFMA1llI1
=
ARGVALUE49
;
50
:
BFMA1llI1
=
ARGVALUE50
;
51
:
BFMA1llI1
=
ARGVALUE51
;
52
:
BFMA1llI1
=
ARGVALUE52
;
53
:
BFMA1llI1
=
ARGVALUE53
;
54
:
BFMA1llI1
=
ARGVALUE54
;
55
:
BFMA1llI1
=
ARGVALUE55
;
56
:
BFMA1llI1
=
ARGVALUE56
;
57
:
BFMA1llI1
=
ARGVALUE57
;
58
:
BFMA1llI1
=
ARGVALUE58
;
59
:
BFMA1llI1
=
ARGVALUE59
;
60
:
BFMA1llI1
=
ARGVALUE60
;
61
:
BFMA1llI1
=
ARGVALUE61
;
62
:
BFMA1llI1
=
ARGVALUE62
;
63
:
BFMA1llI1
=
ARGVALUE63
;
64
:
BFMA1llI1
=
ARGVALUE64
;
65
:
BFMA1llI1
=
ARGVALUE65
;
66
:
BFMA1llI1
=
ARGVALUE66
;
67
:
BFMA1llI1
=
ARGVALUE67
;
68
:
BFMA1llI1
=
ARGVALUE68
;
69
:
BFMA1llI1
=
ARGVALUE69
;
70
:
BFMA1llI1
=
ARGVALUE70
;
71
:
BFMA1llI1
=
ARGVALUE71
;
72
:
BFMA1llI1
=
ARGVALUE72
;
73
:
BFMA1llI1
=
ARGVALUE73
;
74
:
BFMA1llI1
=
ARGVALUE74
;
75
:
BFMA1llI1
=
ARGVALUE75
;
76
:
BFMA1llI1
=
ARGVALUE76
;
77
:
BFMA1llI1
=
ARGVALUE77
;
78
:
BFMA1llI1
=
ARGVALUE78
;
79
:
BFMA1llI1
=
ARGVALUE79
;
80
:
BFMA1llI1
=
ARGVALUE80
;
81
:
BFMA1llI1
=
ARGVALUE81
;
82
:
BFMA1llI1
=
ARGVALUE82
;
83
:
BFMA1llI1
=
ARGVALUE83
;
84
:
BFMA1llI1
=
ARGVALUE84
;
85
:
BFMA1llI1
=
ARGVALUE85
;
86
:
BFMA1llI1
=
ARGVALUE86
;
87
:
BFMA1llI1
=
ARGVALUE87
;
88
:
BFMA1llI1
=
ARGVALUE88
;
89
:
BFMA1llI1
=
ARGVALUE89
;
90
:
BFMA1llI1
=
ARGVALUE90
;
91
:
BFMA1llI1
=
ARGVALUE91
;
92
:
BFMA1llI1
=
ARGVALUE92
;
93
:
BFMA1llI1
=
ARGVALUE93
;
94
:
BFMA1llI1
=
ARGVALUE94
;
95
:
BFMA1llI1
=
ARGVALUE95
;
96
:
BFMA1llI1
=
ARGVALUE96
;
97
:
BFMA1llI1
=
ARGVALUE97
;
98
:
BFMA1llI1
=
ARGVALUE98
;
99
:
BFMA1llI1
=
ARGVALUE99
;
default
:
begin
$display
(
"Illegal Parameter P1 (FAILURE)"
)
;
end
endcase
end
BFMA1O10l
:
begin
BFMA1lO10
=
BFMA1lIl0
(
BFMA1lO10
)
;
BFMA1llI1
=
BFMA1I0l0
(
BFMA1lO10
,
BFMA1I1I1
)
;
end
BFMA1I10l
:
begin
BFMA1OI10
=
BFMA1lO10
;
BFMA1lO10
=
BFMA1lIl0
(
BFMA1lO10
)
;
BFMA1llI1
=
BFMA1I0l0
(
BFMA1lO10
,
BFMA1I1I1
)
;
end
BFMA1l10l
:
begin
BFMA1lO10
=
BFMA1OI10
;
BFMA1lO10
=
BFMA1lIl0
(
BFMA1lO10
)
;
BFMA1llI1
=
BFMA1I0l0
(
BFMA1lO10
,
BFMA1I1I1
)
;
end
default
:
begin
$display
(
"Illegal Parameter P2 (FAILURE)"
)
;
end
endcase
end
2
:
begin
BFMA1llI1
=
BFMA1ll1
[
BFMA1I01
-
BFMA1l0I1
+
BFMA1l1I1
]
;
end
1
:
begin
BFMA1llI1
=
BFMA1ll1
[
BFMA1l0I1
+
BFMA1l1I1
]
;
end
0
:
begin
BFMA1llI1
=
BFMA1l0I1
;
end
default
:
begin
$display
(
"Illegal Parameter P3 (FAILURE)"
)
;
end
endcase
end
else
begin
BFMA1llI1
=
BFMA1IlI1
;
end
BFMA1lII1
=
BFMA1llI1
;
end
endfunction
function
integer
BFMA1OOl1
;
input
BFMA1IlI1
;
integer
BFMA1IlI1
;
input
BFMA1I01
;
integer
BFMA1I01
;
integer
BFMA1IOl1
;
integer
BFMA1O0I1
;
integer
BFMA1I0I1
;
integer
BFMA1l0I1
;
integer
BFMA1O1I1
;
integer
BFMA1I1I1
;
reg
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1l1I1
;
begin
BFMA1I01l
=
BFMA1IlI1
;
BFMA1O0I1
=
BFMA1I01l
[
30
:
16
]
;
BFMA1I0I1
=
BFMA1I01l
[
14
:
13
]
;
BFMA1l0I1
=
BFMA1I01l
[
12
:
0
]
;
BFMA1O1I1
=
BFMA1I01l
[
12
:
8
]
;
BFMA1I1I1
=
BFMA1I01l
[
7
:
0
]
;
BFMA1l1I1
=
0
;
if
(
(
BFMA1I01l
[
15
]
)
==
1
'b
1
)
begin
BFMA1l1I1
=
BFMA1lII1
(
1
,
BFMA1O0I1
)
;
end
case
(
BFMA1I0I1
)
3
:
begin
$display
(
"$Variables not allowed (FAILURE)"
)
;
end
2
:
begin
BFMA1IOl1
=
BFMA1I01
-
BFMA1l0I1
+
BFMA1l1I1
;
end
1
:
begin
BFMA1IOl1
=
BFMA1l0I1
+
BFMA1l1I1
;
end
0
:
begin
$display
(
"Immediate data not allowed (FAILURE)"
)
;
end
default
:
begin
$display
(
"Illegal Parameter P3 (FAILURE)"
)
;
end
endcase
BFMA1OOl1
=
BFMA1IOl1
;
end
endfunction
always
@
(
posedge
BFMA1II
or
negedge
SYSRSTN
)
begin
:
BFMA1lOl1
parameter
[
0
:
0
]
BFMA1OIl1
=
0
;
parameter
[
0
:
0
]
BFMA1IIl1
=
1
;
integer
BFMA1lIl1
;
reg
BFMA1Oll1
;
integer
BFMA1Ill1
[
0
:
4
]
;
reg
[
31
:
0
]
BFMA1lll1
[
0
:
255
]
;
integer
BFMA1O0l1
;
integer
BFMA1O000
;
integer
BFMA1I0l1
;
integer
BFMA1l0l1
;
integer
BFMA1O1l1
;
reg
[
31
:
0
]
BFMA1I1l1
;
reg
[
1
:
0
]
BFMA1l1l1
;
integer
BFMA1OO01
;
integer
BFMA1IO01
;
integer
BFMA1lO01
;
integer
BFMA1OI01
;
integer
BFMA1II01
;
reg
[
2
:
0
]
BFMA1lI01
;
reg
[
31
:
0
]
BFMA1Ol01
;
reg
[
31
:
0
]
BFMA1Il01
;
reg
[
31
:
0
]
BFMA1ll01
;
reg
BFMA1O001
;
reg
BFMA1I001
;
reg
BFMA1l001
;
reg
BFMA1O101
;
reg
BFMA1I101
;
reg
BFMA1l101
;
reg
BFMA1OO11
;
reg
BFMA1IO11
;
reg
BFMA1lO11
;
reg
BFMA1OI11
;
reg
BFMA1II11
;
integer
BFMA1lI11
;
integer
BFMA1Ol11
;
integer
BFMA1Il11
;
integer
BFMA1Il00
;
integer
BFMA1I0I0
;
integer
BFMA1I100
;
integer
BFMA1IlI1
;
integer
BFMA1llI1
;
integer
BFMA1ll11
;
reg
[
1
:
(
256
)
*
8
]
BFMA1l000
;
reg
[
1
:
(
256
)
*
8
]
BFMA1O011
;
reg
[
1
:
(
256
)
*
8
]
BFMA1I011
;
integer
BFMA1l011
;
integer
BFMA1O111
;
integer
BFMA1I111
;
integer
BFMA1l111
;
integer
BFMA1OOOOI
[
0
:
8191
]
;
reg
[
1
:
(
8
)
*
8
]
BFMA1IOOOI
;
reg
BFMA1lOOOI
;
reg
BFMA1OIOOI
;
reg
BFMA1IIOOI
;
integer
BFMA1lIOOI
;
integer
BFMA1OlOOI
;
integer
BFMA1IlOOI
;
integer
BFMA1llOOI
;
integer
BFMA1O0OOI
;
integer
BFMA1I0OOI
;
integer
BFMA1lI00
;
integer
BFMA1l0OOI
;
integer
BFMA1O1OOI
;
integer
BFMA1I1OOI
;
integer
BFMA1l1OOI
;
integer
BFMA1OOIOI
;
integer
BFMA1IOIOI
;
integer
BFMA1lOIOI
;
integer
BFMA1OIIOI
;
reg
[
31
:
0
]
BFMA1IIIOI
;
reg
[
31
:
0
]
BFMA1lIIOI
;
reg
BFMA1OlIOI
;
reg
BFMA1IlIOI
;
reg
BFMA1llIOI
;
reg
BFMA1O0IOI
;
reg
[
0
:
0
]
BFMA1I0IOI
;
reg
[
1
:
(
10
)
*
8
]
BFMA1l0IOI
;
reg
BFMA1O1IOI
;
reg
[
3
:
0
]
BFMA1I1IOI
;
reg
[
2
:
0
]
BFMA1l1IOI
;
integer
BFMA1OOlOI
;
reg
BFMA1IOlOI
;
reg
[
1
:
(
256
)
*
8
]
BFMA1lOlOI
[
0
:
100
]
;
integer
BFMA1OIlOI
;
integer
BFMA1IIlOI
;
reg
[
1
:
0
]
BFMA1lIlOI
;
reg
[
5
:
0
]
BFMA1OllOI
;
reg
[
16
:
0
]
BFMA1IllOI
;
reg
BFMA1lllOI
;
integer
BFMA1O0lOI
;
reg
BFMA1I0lOI
;
reg
BFMA1l0lOI
;
reg
BFMA1O1lOI
;
reg
BFMA1I1lOI
;
reg
BFMA1l1lOI
;
integer
BFMA1OO0OI
;
reg
BFMA1IO0OI
;
reg
BFMA1lO0OI
;
reg
BFMA1OI0OI
;
reg
BFMA1II0OI
;
reg
BFMA1lI0OI
;
integer
BFMA1Ol0OI
;
integer
BFMA1Il0OI
;
integer
BFMA1ll0OI
;
integer
BFMA1O00OI
;
reg
BFMA1I00OI
;
reg
[
1
:
0
]
BFMA1l00OI
;
reg
[
3
:
0
]
BFMA1O10OI
;
reg
[
2
:
0
]
BFMA1I10OI
;
reg
BFMA1l10OI
;
reg
BFMA1OO1OI
;
reg
[
256
*
8
:
0
]
BFMA1IO1OI
;
integer
BFMA1OlO0
;
integer
BFMA1OO10
;
integer
BFMA1lO1OI
;
reg
BFMA1OI1OI
;
integer
BFMA1OOI1
;
integer
BFMA1II1OI
[
0
:
15
]
;
integer
BFMA1lI1OI
;
integer
BFMA1Ol1OI
[
0
:
255
]
;
reg
[
8
:
0
]
BFMA1Il1OI
;
reg
[
8
:
0
]
BFMA1ll1OI
;
integer
BFMA1O01OI
[
0
:
255
]
;
integer
BFMA1I01OI
;
if
(
SYSRSTN
==
1
'b
0
)
begin
BFMA1OOIOI
=
0
;
BFMA1IOIOI
=
0
;
BFMA1II10
=
0
;
BFMA1OIlOI
=
0
;
BFMA1IIlOI
=
65536
;
BFMA1I0IOI
=
BFMA1OIl1
;
BFMA1lI10
=
0
;
BFMA1O1O1
=
0
;
BFMA1I1O1
=
0
;
BFMA1l00
<=
1
'b
0
;
DEBUG
<=
DEBUGLEVEL
;
BFMA1l1
<=
{
32
{
1
'b
0
}
}
;
BFMA1ll
<=
{
3
{
1
'b
0
}
}
;
BFMA1O0
<=
1
'b
0
;
BFMA1I0
<=
{
4
{
1
'b
0
}
}
;
BFMA1IOI
<=
{
3
{
1
'b
0
}
}
;
BFMA1l0
<=
{
2
{
1
'b
0
}
}
;
BFMA1O1
<=
1
'b
0
;
BFMA1O10
<=
{
32
{
1
'b
0
}
}
;
INSTR_OUT
<=
{
32
{
1
'b
0
}
}
;
BFMA1lII
<=
1
'b
0
;
BFMA1OlI
<=
1
'b
0
;
BFMA1O1I
<=
{
32
{
1
'b
0
}
}
;
BFMA1I1I
<=
{
32
{
1
'b
0
}
}
;
BFMA1l1I
<=
{
32
{
1
'b
0
}
}
;
BFMA1l1l
<=
1
'b
0
;
BFMA1l0l
<=
1
'b
0
;
BFMA1O1l
<=
1
'b
0
;
BFMA1OI0
<=
{
32
{
1
'b
0
}
}
;
BFMA1lO0
<=
{
32
{
1
'b
0
}
}
;
BFMA1l10
<=
1
'b
0
;
BFMA1I10
[
1
:
8
]
<=
{
"UNKNOWN"
,
8
'b
0
}
;
BFMA1IlI
<=
1
'b
0
;
BFMA1OOl
<=
{
32
{
1
'b
0
}
}
;
BFMA1IOl
<=
{
32
{
1
'b
0
}
}
;
BFMA1I00
<=
0
;
BFMA1OOI
<=
{
32
{
1
'b
0
}
}
;
BFMA1OO1
<=
1
'b
0
;
BFMA1Il
<=
1
'b
0
;
CON_BUSY
<=
1
'b
0
;
BFMA1I00
<=
0
;
BFMA1llI
<=
1
'b
0
;
BFMA1O0I
<=
1
'b
0
;
BFMA1IO1
<=
0
;
BFMA1lO1
<=
0
;
BFMA1OI1
<=
0
;
BFMA1II1
<=
0
;
BFMA1Oll1
=
0
;
BFMA1O000
=
0
;
BFMA1OI11
=
0
;
BFMA1l1OOI
=
0
;
BFMA1O001
=
0
;
BFMA1OO11
=
0
;
BFMA1I101
=
0
;
BFMA1I001
=
0
;
BFMA1l001
=
0
;
BFMA1O101
=
0
;
BFMA1l101
=
0
;
BFMA1IO11
=
0
;
BFMA1I01
=
0
;
BFMA1I1OOI
=
0
;
BFMA1II01
=
512
;
BFMA1IOlOI
=
0
;
BFMA1II10
=
0
;
BFMA1O0IOI
=
0
;
BFMA1O1IOI
=
1
'b
0
;
BFMA1I1IOI
=
4
'b
0011
;
BFMA1l1IOI
=
3
'b
001
;
BFMA1lOOOI
=
0
;
BFMA1lIlOI
=
2
;
BFMA1OllOI
=
4
;
BFMA1IllOI
=
0
;
BFMA1lllOI
=
0
;
BFMA1I0lOI
=
0
;
BFMA1l1lOI
=
0
;
BFMA1O01
=
0
;
BFMA1l0lOI
=
0
;
BFMA1OO0OI
=
0
;
BFMA1lO0OI
=
0
;
BFMA1OI0OI
=
0
;
BFMA1II0OI
=
0
;
BFMA1lI0OI
=
0
;
BFMA1O11
=
BFMA1OI
;
BFMA1IO0OI
=
0
;
BFMA1O00OI
=
0
;
BFMA1lO10
=
1
;
BFMA1OI10
=
1
;
BFMA1O11
=
1
;
BFMA1lI1OI
=
0
;
BFMA1Il1OI
=
0
;
BFMA1ll1OI
=
0
;
BFMA1I01OI
=
0
;
BFMA1O0lOI
=
0
;
end
else
begin
BFMA1Il0
<=
CON_RD
;
BFMA1ll0
<=
CON_WR
;
BFMA1l0l
<=
1
'b
0
;
BFMA1O1l
<=
1
'b
0
;
BFMA1l1l
<=
1
'b
0
;
BFMA1OO0
<=
1
'b
0
;
BFMA1lO11
=
0
;
if
(
~
BFMA1Oll1
)
begin
$display
(
" "
)
;
$display
(
"###########################################################################"
)
;
$display
(
"AMBA BFM Model"
)
;
$display
(
"Version %s %s"
,
BFMA1O
,
BFMA1I
)
;
$display
(
" "
)
;
$display
(
"Opening BFM Script file %0s"
,
VECTFILE
)
;
if
(
~
BFMA1Oll1
&
OPMODE
!=
2
)
begin
$readmemh
(
VECTFILE
,
BFMA1Ol
)
;
BFMA1ll11
=
3000
;
BFMA1Oll1
=
1
;
BFMA1O0l1
=
BFMA1Ol
[
4
]
;
BFMA1Ol0OI
=
BFMA1Ol
[
0
]
%
65536
;
BFMA1ll0OI
=
BFMA1Ol
[
0
]
/
65536
;
$display
(
"Read %0d Vectors - Compiler Version %0d.%0d"
,
BFMA1O0l1
,
BFMA1ll0OI
,
BFMA1Ol0OI
)
;
if
(
BFMA1ll0OI
!=
BFMA1I11
)
begin
$display
(
"Incorrect vectors file format for this BFM %0s (FAILURE) == "
,
VECTFILE
)
;
$stop
;
end
BFMA1O000
=
BFMA1Ol
[
1
]
;
BFMA1l0l1
=
BFMA1Ol
[
2
]
;
BFMA1I01
=
BFMA1Ol
[
3
]
;
BFMA1ll1
[
BFMA1I01
]
=
0
;
BFMA1I01
=
BFMA1I01
+
1
;
if
(
BFMA1O000
==
0
)
begin
$display
(
"BFM Compiler reported errors (FAILURE)"
)
;
$stop
;
end
$display
(
"BFM:Filenames referenced in Vectors"
)
;
BFMA1I1l1
=
BFMA1Ol
[
BFMA1l0l1
]
;
BFMA1OO01
=
BFMA1Ol
[
BFMA1l0l1
]
%
256
;
while
(
BFMA1OO01
==
BFMA1ll0I
)
begin
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1l0l1
+
1
]
)
;
BFMA1l000
=
BFMA1ll00
(
BFMA1l0l1
)
;
$display
(
" %0s"
,
BFMA1l000
)
;
begin
:
BFMA1l01OI
integer
BFMA1I0I0
,
BFMA1OO10
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<
256
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
for
(
BFMA1OO10
=
1
;
BFMA1OO10
<=
8
;
BFMA1OO10
=
BFMA1OO10
+
1
)
BFMA1lOlOI
[
BFMA1OIlOI
]
[
BFMA1I0I0
*
8
+
BFMA1OO10
]
=
BFMA1l000
[
BFMA1I0I0
*
8
+
BFMA1OO10
]
;
end
BFMA1OIlOI
=
BFMA1OIlOI
+
1
;
BFMA1l0l1
=
BFMA1l0l1
+
BFMA1OI01
;
BFMA1I1l1
=
to_slv32
(
BFMA1Ol
[
BFMA1l0l1
]
)
;
BFMA1OO01
=
BFMA1Ol
[
BFMA1l0l1
]
%
256
;
end
BFMA1IIlOI
=
65536
;
if
(
BFMA1OIlOI
>
1
)
BFMA1IIlOI
=
32768
;
if
(
BFMA1OIlOI
>
2
)
BFMA1IIlOI
=
16384
;
if
(
BFMA1OIlOI
>
4
)
BFMA1IIlOI
=
8912
;
if
(
BFMA1OIlOI
>
8
)
BFMA1IIlOI
=
4096
;
if
(
BFMA1OIlOI
>
16
)
BFMA1IIlOI
=
2048
;
if
(
BFMA1OIlOI
>
32
)
BFMA1IIlOI
=
1024
;
BFMA1l0lOI
=
(
OPMODE
==
0
)
;
end
end
if
(
OPMODE
==
2
&
~
BFMA1Oll1
)
begin
BFMA1IIlOI
=
65536
;
BFMA1Oll1
=
1
;
BFMA1l0lOI
=
0
;
BFMA1I01
=
BFMA1Ol
[
3
]
+
1
;
BFMA1ll1
[
BFMA1I01
]
=
0
;
BFMA1I01
=
BFMA1I01
+
1
;
end
if
(
BFMA1lI10
<=
1
)
begin
BFMA1Il
<=
1
'b
1
;
end
else
begin
BFMA1lI10
=
BFMA1lI10
-
1
;
end
case
(
BFMA1I0IOI
)
BFMA1OIl1
:
begin
if
(
HRESP
==
1
'b
1
&
HREADY
==
1
'b
1
)
begin
$display
(
"BFM: HRESP Signaling Protocol Error T2 (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
if
(
HRESP
==
1
'b
1
&
HREADY
==
1
'b
0
)
begin
BFMA1I0IOI
=
BFMA1IIl1
;
end
end
BFMA1IIl1
:
begin
if
(
HRESP
==
1
'b
0
|
HREADY
==
1
'b
0
)
begin
$display
(
"BFM: HRESP Signaling Protocol Error T3 (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
if
(
HRESP
==
1
'b
1
&
HREADY
==
1
'b
1
)
begin
BFMA1I0IOI
=
BFMA1OIl1
;
end
case
(
BFMA1I1OOI
)
0
:
begin
$display
(
"BFM: Unexpected HRESP Signaling Occured (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
1
:
begin
BFMA1O0IOI
=
1
;
end
default
:
begin
$display
(
"BFM: HRESP mode is not correctly set (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
endcase
end
endcase
if
(
OPMODE
>
0
)
begin
if
(
(
CON_WR
==
1
'b
1
)
&&
(
BFMA1ll0
==
1
'b
0
||
CON_SPULSE
==
1
)
)
begin
BFMA1Il00
=
BFMA1O01l
(
CON_ADDR
)
;
case
(
BFMA1Il00
)
0
:
begin
BFMA1l0lOI
=
(
(
BFMA1lI0
[
0
]
)
==
1
'b
1
)
;
BFMA1O1lOI
=
(
(
BFMA1lI0
[
1
]
)
==
1
'b
1
)
;
BFMA1lOOOI
=
0
;
if
(
BFMA1l0lOI
&
~
BFMA1O1lOI
)
begin
BFMA1ll1
[
BFMA1I01
]
=
0
;
BFMA1I01
=
BFMA1I01
+
1
;
end
if
(
DEBUG
>=
2
&
BFMA1l0lOI
&
~
BFMA1O1lOI
)
begin
$display
(
"BFM: Starting script at %08x (%0d parameters)"
,
BFMA1O000
,
BFMA1lI1OI
)
;
end
if
(
DEBUG
>=
2
&
BFMA1l0lOI
&
BFMA1O1lOI
)
begin
$display
(
"BFM: Starting instruction at %08x"
,
BFMA1O000
)
;
end
if
(
BFMA1l0lOI
)
begin
if
(
BFMA1lI1OI
>
0
)
begin
begin
:
BFMA1O11OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1lI1OI
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1ll1
[
BFMA1I01
]
=
BFMA1II1OI
[
BFMA1I0I0
]
;
BFMA1I01
=
BFMA1I01
+
1
;
end
end
BFMA1lI1OI
=
0
;
end
BFMA1Il1OI
=
0
;
BFMA1ll1OI
=
0
;
end
end
1
:
begin
BFMA1O000
=
BFMA1lI0
;
end
2
:
begin
BFMA1II1OI
[
BFMA1lI1OI
]
=
BFMA1lI0
;
BFMA1lI1OI
=
BFMA1lI1OI
+
1
;
end
default
:
begin
BFMA1Ol
[
BFMA1Il00
]
=
to_int_signed
(
BFMA1lI0
)
;
end
endcase
end
if
(
(
CON_RD
==
1
'b
1
)
&&
(
BFMA1Il0
==
1
'b
0
||
CON_SPULSE
==
1
)
)
begin
BFMA1Il00
=
BFMA1O01l
(
CON_ADDR
)
;
case
(
BFMA1Il00
)
0
:
begin
BFMA1Ol0
<=
{
32
{
1
'b
0
}
}
;
BFMA1Ol0
[
2
]
<=
BFMA1l0lOI
;
BFMA1Ol0
[
3
]
<=
(
BFMA1II10
>
0
)
;
end
1
:
begin
BFMA1Ol0
<=
BFMA1O000
;
end
2
:
begin
BFMA1Ol0
<=
BFMA1O01
;
BFMA1lI1OI
=
0
;
end
3
:
begin
if
(
BFMA1Il1OI
>
BFMA1ll1OI
)
begin
BFMA1Ol0
<=
BFMA1Ol1OI
[
BFMA1ll1OI
]
;
BFMA1ll1OI
=
BFMA1ll1OI
+
1
;
end
else
begin
$display
(
"BFM: Overread Control return stack"
)
;
BFMA1Ol0
<=
{
32
{
1
'b
0
}
}
;
end
end
default
:
begin
BFMA1Ol0
<=
{
32
{
1
'b
0
}
}
;
end
endcase
end
end
BFMA1OOIOI
=
BFMA1OOIOI
+
1
;
BFMA1l1O1
=
BFMA1l1O1
+
1
;
BFMA1OI1OI
=
1
;
while
(
BFMA1OI1OI
)
begin
BFMA1OI1OI
=
0
;
if
(
~
BFMA1OI11
&
BFMA1l0lOI
)
begin
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
7
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
BFMA1lI
[
BFMA1I0I0
]
=
0
;
BFMA1I1l1
=
BFMA1Ol
[
BFMA1O000
]
;
BFMA1l1l1
=
BFMA1I1l1
[
1
:
0
]
;
BFMA1OO01
=
BFMA1I1l1
[
7
:
0
]
;
BFMA1lO01
=
BFMA1I1l1
[
15
:
8
]
;
BFMA1l01
=
BFMA1I1l1
[
31
:
16
]
;
BFMA1Il11
=
BFMA1II01
;
BFMA1IOIOI
=
BFMA1IOIOI
+
1
;
BFMA1OI01
=
1
;
BFMA1OOlOI
=
-
1
;
BFMA1OO0OI
=
0
;
if
(
DEBUG
>=
5
)
$display
(
"BFM: Instruction %0d Line Number %0d Command %0d"
,
BFMA1O000
,
BFMA1l01
,
BFMA1OO01
)
;
if
(
BFMA1lI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d BF %4d %4d %3d"
,
$time
,
BFMA1O000
,
BFMA1l01
,
BFMA1OO01
)
;
end
if
(
BFMA1OO01
>=
100
)
begin
BFMA1IO01
=
BFMA1OO01
;
end
else
begin
BFMA1IO01
=
4
*
(
BFMA1OO01
/
4
)
;
end
if
(
BFMA1OO01
!=
BFMA1OI1I
)
begin
BFMA1OOIOI
=
0
;
end
case
(
BFMA1IO01
)
BFMA1Ol0I
,
BFMA1Il0I
,
BFMA1ll0I
,
BFMA1OIIl
:
BFMA1Il00
=
8
;
BFMA1IlOI
,
BFMA1l0OI
:
BFMA1Il00
=
4
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
BFMA1l0lI
:
BFMA1Il00
=
3
+
BFMA1Ol
[
BFMA1O000
+
2
]
;
BFMA1I0lI
:
BFMA1Il00
=
3
;
BFMA1II0I
:
BFMA1Il00
=
2
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
BFMA1I11I
:
BFMA1Il00
=
3
+
BFMA1Ol
[
BFMA1O000
+
2
]
;
BFMA1OlIl
:
BFMA1Il00
=
2
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
BFMA1lIlI
:
BFMA1Il00
=
3
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
default
:
BFMA1Il00
=
8
;
endcase
if
(
BFMA1Il00
>
0
)
begin
begin
:
BFMA1I11OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1Il00
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
if
(
BFMA1I0I0
>=
1
&
BFMA1I0I0
<=
8
)
begin
BFMA1lI
[
BFMA1I0I0
]
=
BFMA1lII1
(
(
(
BFMA1I1l1
[
7
+
BFMA1I0I0
]
)
==
1
'b
1
)
,
BFMA1Ol
[
BFMA1O000
+
BFMA1I0I0
]
)
;
end
else
begin
BFMA1lI
[
BFMA1I0I0
]
=
BFMA1Ol
[
BFMA1O000
+
BFMA1I0I0
]
;
end
BFMA1lll1
[
BFMA1I0I0
]
=
to_slv32
(
BFMA1lI
[
BFMA1I0I0
]
)
;
end
end
end
case
(
BFMA1IO01
)
BFMA1IlIl
:
begin
$display
(
"BFM Compiler reported an error (FAILURE)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1ll1I
:
begin
BFMA1OI01
=
2
;
BFMA1OI1OI
=
1
;
BFMA1Ol1OI
[
BFMA1Il1OI
]
=
BFMA1lI
[
1
]
;
BFMA1Il1OI
=
BFMA1Il1OI
+
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:conifpush %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
BFMA1OOOl
:
begin
BFMA1OI01
=
2
;
BFMA1Il
<=
1
'b
0
;
BFMA1lI10
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:RESET %0d"
,
BFMA1l01
,
BFMA1lI10
)
;
end
BFMA1IOOl
:
begin
BFMA1OI01
=
2
;
BFMA1l00
<=
BFMA1lll1
[
1
]
[
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:STOPCLK %0d "
,
BFMA1l01
,
BFMA1lll1
[
1
]
[
0
]
)
;
end
BFMA1l00I
:
begin
BFMA1OI01
=
2
;
BFMA1l1OOI
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:mode %0d (No effect in this version)"
,
BFMA1l01
,
BFMA1l1OOI
)
;
end
BFMA1O10I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1Il00
=
BFMA1lI
[
1
]
;
BFMA1IlI1
=
BFMA1lI
[
2
]
;
BFMA1llI1
=
BFMA1lI
[
3
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:setup %0d %0d %0d "
,
BFMA1l01
,
BFMA1Il00
,
BFMA1IlI1
,
BFMA1llI1
)
;
case
(
BFMA1Il00
)
1
:
begin
BFMA1OI01
=
4
;
BFMA1lIlOI
=
BFMA1IlI1
;
BFMA1OllOI
=
BFMA1llI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Memory Cycle Transfer Size %0s %0d"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1lIlOI
)
,
BFMA1OllOI
)
;
end
2
:
begin
BFMA1OI01
=
3
;
BFMA1lllOI
=
to_boolean
(
BFMA1IlI1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Automatic Flush %0d"
,
BFMA1l01
,
BFMA1lllOI
)
;
end
3
:
begin
BFMA1OI01
=
3
;
BFMA1IllOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- XRATE %0d"
,
BFMA1l01
,
BFMA1IllOI
)
;
end
4
:
begin
BFMA1OI01
=
3
;
BFMA1O0lOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Burst Mode %0d"
,
BFMA1l01
,
BFMA1O0lOI
)
;
end
5
:
begin
BFMA1OI01
=
3
;
BFMA1I0lOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Alignment %0d"
,
BFMA1l01
,
BFMA1I0lOI
)
;
if
(
BFMA1I0lOI
==
1
|
BFMA1I0lOI
==
2
)
begin
$display
(
"BFM: Untested 8 or 16 Bit alignment selected (WARNING)"
)
;
end
end
6
:
begin
BFMA1OI01
=
3
;
end
7
:
begin
BFMA1OI01
=
3
;
BFMA1l1lOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- End Sim Action %0d"
,
BFMA1l01
,
BFMA1l1lOI
)
;
if
(
BFMA1l1lOI
>
2
)
begin
$display
(
"BFM: Unexpected End Simulation value (WARNING)"
)
;
end
end
default
:
begin
$display
(
"BFM Unknown Setup Command (FAILURE)"
)
;
end
endcase
end
BFMA1IOIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1OI1
<=
(
(
BFMA1lll1
[
1
]
[
0
]
)
==
1
'b
1
)
;
BFMA1II1
<=
(
(
BFMA1lll1
[
1
]
[
1
]
)
==
1
'b
1
)
;
BFMA1lO1
<=
(
(
BFMA1lll1
[
1
]
[
2
]
)
==
1
'b
1
)
;
BFMA1IO1
<=
(
(
BFMA1lll1
[
1
]
[
3
]
)
==
1
'b
1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:drivex %0d "
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
BFMA1IO1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:error %0d %0d (No effect in this version)"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
)
;
end
BFMA1l10I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I1IOI
=
BFMA1lll1
[
1
]
[
3
:
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:prot %0d "
,
BFMA1l01
,
BFMA1I1IOI
)
;
end
BFMA1OO1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1O1IOI
=
BFMA1lll1
[
1
]
[
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:lock %0d "
,
BFMA1l01
,
BFMA1O1IOI
)
;
end
BFMA1lO1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1l1IOI
=
BFMA1lll1
[
1
]
[
2
:
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:burst %0d "
,
BFMA1l01
,
BFMA1l1IOI
)
;
end
BFMA1OO0I
:
begin
BFMA1OI01
=
2
;
BFMA1lI11
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:wait %0d starting at %0d ns"
,
BFMA1l01
,
BFMA1lI11
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1OOIl
:
begin
BFMA1OI01
=
2
;
BFMA1O00OI
=
BFMA1lI
[
1
]
*
1000
+
(
$time
/
1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitus %0d starting at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1l1Ol
:
begin
BFMA1OI01
=
2
;
BFMA1O00OI
=
BFMA1lI
[
1
]
*
1
+
(
$time
/
1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitns %0d starting at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1OI1I
:
begin
BFMA1OI01
=
3
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktime %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1lI1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
BFMA1l1O1
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:starttimer at %0d ns"
,
BFMA1l01
,
$time
)
;
end
BFMA1Ol1I
:
begin
BFMA1OI01
=
3
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktimer %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1l11
:
begin
BFMA1OI01
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:nop"
,
BFMA1l01
)
;
end
BFMA1OOOI
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:write %c %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1I101
=
1
;
end
BFMA1lOII
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1I00OI
=
BFMA1lll1
[
4
]
[
0
]
;
BFMA1l00OI
=
BFMA1lll1
[
4
]
[
5
:
4
]
;
BFMA1I10OI
=
BFMA1lll1
[
4
]
[
10
:
8
]
;
BFMA1l10OI
=
BFMA1lll1
[
4
]
[
12
]
;
BFMA1O10OI
=
BFMA1lll1
[
4
]
[
19
:
16
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:idle %c %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1lll1
[
4
]
,
$time
)
;
BFMA1IO11
=
1
;
end
BFMA1IOOI
:
begin
BFMA1OI01
=
3
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:read %c %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
$time
)
;
BFMA1I001
=
1
;
end
BFMA1IOII
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1OOlOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
3
]
,
BFMA1I01
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readstore %c %08x @%0d at %0d ns "
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1OOlOI
,
$time
)
;
BFMA1I001
=
1
;
BFMA1OO11
=
1
;
end
BFMA1lOOI
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readcheck %c %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1I001
=
1
;
end
BFMA1OIOI
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
BFMA1lll1
[
4
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readmask %c %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1I001
=
1
;
end
BFMA1IIOI
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:poll %c %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1OI11
=
1
;
BFMA1l101
=
1
;
BFMA1l101
=
1
;
end
BFMA1lIOI
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
BFMA1lll1
[
4
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:pollmask %c %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1l101
=
1
;
end
BFMA1OlOI
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1Ol11
=
BFMA1lI
[
3
]
;
BFMA1ll01
[
BFMA1Ol11
]
=
1
'b
1
;
BFMA1Il01
[
BFMA1Ol11
]
=
BFMA1lll1
[
4
]
[
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:pollbit %c %08x %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Ol11
,
BFMA1Il01
[
BFMA1Ol11
]
,
$time
)
;
BFMA1l101
=
1
;
end
BFMA1IlOI
:
begin
BFMA1O111
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
4
+
BFMA1O111
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
2
]
+
BFMA1lI
[
3
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
begin
:
BFMA1l11OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1lI
[
BFMA1I0I0
+
4
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:writemultiple %c %08x %08x ... at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1OOOOI
[
0
]
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1llOI
:
begin
BFMA1O111
=
BFMA1lI
[
3
]
;
BFMA1OI01
=
6
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1l0OOI
=
BFMA1lI
[
4
]
;
BFMA1O1OOI
=
BFMA1lI
[
5
]
;
begin
:
BFMA1OOOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1l0OOI
;
BFMA1l0OOI
=
BFMA1l0OOI
+
BFMA1O1OOI
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:fill %c %08x %0d %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1O111
,
BFMA1lI
[
4
]
,
BFMA1lI
[
4
]
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1O0OI
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lIOOI
=
BFMA1lI
[
3
]
;
begin
:
BFMA1IOOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1Ol
[
2
+
BFMA1lIOOI
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:writetable %c %08x %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lIOOI
,
BFMA1O111
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1OIII
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
3
]
,
BFMA1I01
)
;
begin
:
BFMA1lOOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1ll1
[
BFMA1lOIOI
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:writearray %c %08x %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lOIOI
,
BFMA1O111
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1I0OI
:
begin
BFMA1O111
=
BFMA1lI
[
3
]
;
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readmult %c %08x %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1O111
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1l0OI
:
begin
BFMA1O111
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
4
+
BFMA1O111
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
2
]
+
BFMA1lI
[
3
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
begin
:
BFMA1OIOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1lI
[
BFMA1I0I0
+
4
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readmultchk %c %08x %08x ... at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1OOOOI
[
0
]
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1O1OI
:
begin
BFMA1O111
=
BFMA1lI
[
3
]
;
BFMA1OI01
=
6
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1l0OOI
=
BFMA1lI
[
4
]
;
BFMA1O1OOI
=
BFMA1lI
[
5
]
;
begin
:
BFMA1IIOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1l0OOI
;
BFMA1l0OOI
=
BFMA1l0OOI
+
BFMA1O1OOI
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:fillcheck %c %08x %0d %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1O111
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1I1OI
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lIOOI
=
BFMA1lI
[
3
]
;
begin
:
BFMA1lIOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1Ol
[
BFMA1lIOOI
+
2
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readtable %c %08x %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lIOOI
,
BFMA1O111
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1IIII
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
3
]
,
BFMA1I01
)
;
begin
:
BFMA1OlOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1ll1
[
BFMA1lOIOI
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readtable %c %08x %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lOIOI
,
BFMA1O111
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1O00I
:
begin
BFMA1OI01
=
7
;
BFMA1O001
=
1
;
BFMA1lOO1
=
BFMA1Il10
;
end
BFMA1I00I
:
begin
BFMA1OI01
=
7
;
BFMA1O001
=
1
;
BFMA1lOO1
=
BFMA1Il10
;
end
BFMA1O1II
:
begin
BFMA1OI01
=
1
;
BFMA1IlOOI
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitfiq at %0d ns "
,
BFMA1l01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1I1II
:
begin
BFMA1OI01
=
1
;
BFMA1IlOOI
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitirq at %0d ns "
,
BFMA1l01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1l0II
:
begin
BFMA1OI01
=
2
;
BFMA1IlOOI
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitint %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlOOI
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1lIII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
BFMA1lll1
[
1
]
;
BFMA1O10
<=
BFMA1Il01
;
BFMA1OO0
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iowrite %08x at %0d ns "
,
BFMA1l01
,
BFMA1Il01
,
$time
)
;
end
BFMA1OlII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1OOlOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ioread @%0d at %0d ns"
,
BFMA1l01
,
BFMA1OOlOI
,
$time
)
;
BFMA1l1l
<=
1
'b
1
;
BFMA1O001
=
1
;
BFMA1OO11
=
1
;
BFMA1lO11
=
1
;
end
BFMA1IlII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
BFMA1lll1
[
1
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1l1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iocheck %08x at %0d ns "
,
BFMA1l01
,
BFMA1Il01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1llII
:
begin
BFMA1OI01
=
3
;
BFMA1Il01
=
BFMA1lll1
[
1
]
;
BFMA1ll01
=
BFMA1lll1
[
2
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iomask %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1l1l
<=
1
'b
1
;
BFMA1O001
=
1
;
end
BFMA1l1OI
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1Il01
[
BFMA1Ol11
]
=
BFMA1I1l1
[
0
]
;
BFMA1ll01
[
BFMA1Ol11
]
=
1
'b
1
;
BFMA1l1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iotest %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1Ol11
,
BFMA1I1l1
[
0
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1O0II
:
begin
BFMA1OI01
=
2
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1O10
[
BFMA1Ol11
]
<=
1
'b
1
;
BFMA1OO0
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ioset %0d at %0d ns"
,
BFMA1l01
,
BFMA1Ol11
,
$time
)
;
end
BFMA1I0II
:
begin
BFMA1OI01
=
2
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1O10
[
BFMA1Ol11
]
<=
1
'b
0
;
BFMA1OO0
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ioclr %0d at %0d ns"
,
BFMA1l01
,
BFMA1Ol11
,
$time
)
;
end
BFMA1OOII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1Il01
[
BFMA1Ol11
]
=
BFMA1I1l1
[
0
]
;
BFMA1ll01
[
BFMA1Ol11
]
=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iowait %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1Ol11
,
BFMA1I1l1
[
0
]
,
$time
)
;
BFMA1l1l
<=
1
'b
1
;
BFMA1O001
=
1
;
end
BFMA1OOlI
:
begin
BFMA1OI01
=
3
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extwrite %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1IOlI
:
begin
BFMA1OI01
=
3
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1OOlOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
2
]
,
BFMA1I01
)
;
BFMA1O1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extread @%0d %08x at %0d ns "
,
BFMA1l01
,
BFMA1OOlOI
,
BFMA1Ol01
,
$time
)
;
BFMA1O001
=
1
;
BFMA1OO11
=
1
;
BFMA1lO11
=
1
;
end
BFMA1lIlI
:
begin
BFMA1O111
=
BFMA1lI
[
1
]
;
BFMA1l011
=
BFMA1lI
[
2
]
;
BFMA1OI01
=
BFMA1O111
+
3
;
begin
:
BFMA1IlOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<
BFMA1O111
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1lI
[
BFMA1I0I0
+
3
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extwrite %08x %0d Words at %0t ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1O111
,
$time
)
;
BFMA1I111
=
0
;
BFMA1O001
=
1
;
end
BFMA1lOlI
:
begin
BFMA1OI01
=
3
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1OI11
=
1
;
BFMA1O1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extcheck %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1OIlI
:
begin
BFMA1OI01
=
4
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
BFMA1lll1
[
3
]
;
BFMA1O1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extmask %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1IIlI
:
begin
BFMA1OI01
=
1
;
BFMA1lI11
=
1
;
BFMA1OI11
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extwait "
,
BFMA1l01
)
;
BFMA1O001
=
1
;
end
BFMA1OllI
:
begin
$display
(
"LABEL instructions not allowed in vector files (FAILURE)"
)
;
end
BFMA1II0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
+
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:table %08x ... (length=%0d)"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1OI01
-
2
)
;
end
BFMA1IllI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:jump"
,
BFMA1l01
)
;
end
BFMA1lllI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
if
(
BFMA1lI
[
2
]
==
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:jumpz %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
)
;
end
BFMA1lOOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
3
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
,
DEBUG
)
;
if
(
BFMA1OIIOI
==
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
+
2
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:if %08x func %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1OIOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
3
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
,
DEBUG
)
;
if
(
BFMA1OIIOI
!=
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
+
2
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ifnot %08x func %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1lIOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
BFMA1I0OOI
+
2
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:else "
,
BFMA1l01
)
;
end
BFMA1OlOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endif "
,
BFMA1l01
)
;
end
BFMA1IIOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
+
2
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
3
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
,
DEBUG
)
;
if
(
BFMA1OIIOI
==
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:while %08x func %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1IlOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endwhile"
,
BFMA1l01
)
;
end
BFMA1O0Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1I0OOI
=
BFMA1lI
[
3
]
;
if
(
BFMA1lI
[
1
]
!=
BFMA1lI
[
2
]
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
else
begin
BFMA1O01OI
[
BFMA1I01OI
]
=
1
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:when %08x=%08x %08x"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
end
BFMA1l0Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1I0OOI
=
BFMA1lI
[
3
]
;
if
(
BFMA1O01OI
[
BFMA1I01OI
]
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
else
begin
BFMA1O01OI
[
BFMA1I01OI
]
=
0
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:default %08x=%08x %08x"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
end
BFMA1llOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
BFMA1I01OI
=
BFMA1I01OI
+
1
;
BFMA1O01OI
[
BFMA1I01OI
]
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:case"
,
BFMA1l01
)
;
end
BFMA1I0Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
BFMA1I01OI
=
BFMA1I01OI
-
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endcase"
,
BFMA1l01
)
;
end
BFMA1O0lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
if
(
BFMA1lI
[
2
]
!=
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:jumpnz %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
)
;
end
BFMA1l11I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
BFMA1lll1
[
3
]
;
BFMA1Il0OI
=
(
BFMA1lll1
[
1
]
^
BFMA1Il01
)
&
BFMA1ll01
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:compare %08x==%08x Mask=%08x (RES=%08x) at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1Il01
,
BFMA1ll01
,
BFMA1Il0OI
,
$time
)
;
if
(
BFMA1Il0OI
!=
0
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: compare failed %08x==%08x Mask=%08x (RES=%08x) "
,
BFMA1lI
[
1
]
,
BFMA1Il01
,
BFMA1ll01
,
BFMA1Il0OI
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Data Compare Error (ERROR)"
)
;
$stop
;
end
end
BFMA1O1Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
BFMA1lll1
[
3
]
;
if
(
BFMA1lI
[
1
]
>=
BFMA1lI
[
2
]
&
BFMA1lI
[
1
]
<=
BFMA1lI
[
3
]
)
begin
BFMA1Il0OI
=
1
;
end
else
begin
BFMA1Il0OI
=
0
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:cmprange %0d in %0d to %0d at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
$time
)
;
if
(
BFMA1Il0OI
==
0
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: cmprange failed %0d in %0d to %0d"
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Data Compare Error (ERROR)"
)
;
$stop
;
end
end
BFMA1O11I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1lI00
=
BFMA1lI
[
1
]
;
BFMA1I01
=
BFMA1I01
+
BFMA1lI00
;
BFMA1ll1
[
BFMA1I01
]
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:int %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
BFMA1I0lI
,
BFMA1l0lI
:
begin
BFMA1OI1OI
=
1
;
if
(
BFMA1OO01
==
BFMA1I0lI
)
begin
BFMA1OI01
=
2
;
BFMA1lI00
=
0
;
end
else
begin
BFMA1lI00
=
BFMA1lI
[
2
]
;
BFMA1OI01
=
3
+
BFMA1lI00
;
end
BFMA1llOOI
=
BFMA1lI
[
1
]
;
BFMA1O0OOI
=
BFMA1O000
+
BFMA1OI01
;
BFMA1OI01
=
BFMA1llOOI
-
BFMA1O000
;
BFMA1ll1
[
BFMA1I01
]
=
BFMA1O0OOI
;
BFMA1I01
=
BFMA1I01
+
1
;
if
(
BFMA1lI00
>
0
)
begin
begin
:
BFMA1llOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1lI00
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1ll1
[
BFMA1I01
]
=
BFMA1lI
[
3
+
BFMA1I0I0
]
;
BFMA1I01
=
BFMA1I01
+
1
;
end
end
end
if
(
DEBUG
>=
2
&
BFMA1OO01
==
BFMA1I0lI
)
$display
(
"BFM:%0d:call %0d"
,
BFMA1l01
,
BFMA1llOOI
)
;
if
(
DEBUG
>=
2
&
BFMA1OO01
==
BFMA1l0lI
)
$display
(
"BFM:%0d:call %0d %08x ..."
,
BFMA1l01
,
BFMA1llOOI
,
BFMA1lI
[
3
]
)
;
end
BFMA1O1lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I01
=
BFMA1I01
-
BFMA1lI
[
1
]
;
BFMA1O0OOI
=
0
;
if
(
BFMA1I01
>
0
)
begin
BFMA1I01
=
BFMA1I01
-
1
;
BFMA1O0OOI
=
BFMA1ll1
[
BFMA1I01
]
;
end
if
(
BFMA1O0OOI
==
0
)
begin
BFMA1lOOOI
=
1
;
BFMA1OO11
=
1
;
BFMA1OI1OI
=
0
;
end
else
begin
BFMA1OI01
=
BFMA1O0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:return"
,
BFMA1l01
)
;
end
BFMA1I1Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1I01
=
BFMA1I01
-
BFMA1lI
[
1
]
;
BFMA1O0OOI
=
0
;
if
(
BFMA1I01
>
0
)
begin
BFMA1I01
=
BFMA1I01
-
1
;
BFMA1O0OOI
=
BFMA1ll1
[
BFMA1I01
]
;
end
BFMA1O01
=
BFMA1lI
[
2
]
;
if
(
BFMA1O0OOI
==
0
)
begin
BFMA1lOOOI
=
1
;
BFMA1OO11
=
1
;
BFMA1OI1OI
=
0
;
end
else
begin
BFMA1OI01
=
BFMA1O0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:return %08x"
,
BFMA1l01
,
BFMA1O01
)
;
end
BFMA1I1lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
BFMA1OIIOI
=
BFMA1lI
[
2
]
;
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1OIIOI
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:loop %0d %0d %0d %0d "
,
BFMA1l01
,
BFMA1lOIOI
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1l1lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0l1
=
BFMA1lI
[
1
]
;
begin
:
BFMA1O0OII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
2
;
BFMA1I0I0
<=
4
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1Ill1
[
BFMA1I0I0
]
=
BFMA1lII1
(
(
to_slv32
(
BFMA1Ol
[
BFMA1I0l1
]
[
7
+
BFMA1I0I0
]
)
==
1
'b
1
)
,
BFMA1Ol
[
BFMA1I0l1
+
BFMA1I0I0
]
)
;
end
end
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1I0l1
+
1
]
,
BFMA1I01
)
;
BFMA1Il00
=
BFMA1Ill1
[
4
]
;
BFMA1I100
=
BFMA1Ill1
[
3
]
;
BFMA1O1l1
=
BFMA1ll1
[
BFMA1lOIOI
]
;
BFMA1O1l1
=
BFMA1O1l1
+
BFMA1Il00
;
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1O1l1
;
BFMA1I0OOI
=
BFMA1I0l1
+
5
;
if
(
(
BFMA1Il00
>=
0
&
BFMA1O1l1
<=
BFMA1I100
)
|
(
BFMA1Il00
<
0
&
BFMA1O1l1
>=
BFMA1I100
)
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endloop (Next Loop=%0d)"
,
BFMA1l01
,
BFMA1O1l1
)
;
end
else
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endloop (Finished)"
,
BFMA1l01
)
;
end
end
BFMA1OI0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1II01
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:timeout %0d"
,
BFMA1l01
,
BFMA1II01
)
;
end
BFMA1Il1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1lO10
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:rand %0d"
,
BFMA1l01
,
BFMA1lO10
)
;
end
BFMA1Ol0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1O000
+
1
]
)
;
BFMA1l000
=
BFMA1ll00
(
BFMA1O000
)
;
$display
(
"BFM:%0s"
,
BFMA1l000
)
;
end
BFMA1Il0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1O000
+
1
]
)
;
BFMA1l000
=
BFMA1ll00
(
BFMA1O000
)
;
$display
(
"################################################################"
)
;
$display
(
"BFM:%0s"
,
BFMA1l000
)
;
end
BFMA1ll0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OlOOI
=
BFMA1O01l
(
BFMA1I1l1
[
15
:
8
]
)
;
BFMA1OI01
=
(
BFMA1OlOOI
-
1
)
/
4
+
2
;
end
BFMA1I10I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
if
(
DEBUGLEVEL
>=
0
&
DEBUGLEVEL
<=
5
)
begin
$display
(
"BFM:%0d: DEBUG - ignored due to DEBUGLEVEL generic setting"
,
BFMA1l01
)
;
end
else
begin
DEBUG
<=
BFMA1lI
[
1
]
;
$display
(
"BFM:%0d: DEBUG %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
end
BFMA1l1II
:
begin
BFMA1OI1OI
=
0
;
BFMA1OI01
=
2
;
BFMA1I1OOI
=
BFMA1lI
[
1
]
;
BFMA1l0IOI
[
1
]
=
BFMA1OI
;
if
(
BFMA1I1OOI
==
2
)
begin
if
(
BFMA1O0IOI
)
begin
BFMA1l0IOI
[
1
:
9
]
=
{
"OCCURRED"
,
BFMA1OI
}
;
end
else
begin
$display
(
"BFM: HRESP Did Not Occur When Expected (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1I1OOI
=
0
;
end
BFMA1O0IOI
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:hresp %0d %0s"
,
BFMA1l01
,
BFMA1I1OOI
,
BFMA1l0IOI
)
;
end
BFMA1IO0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:stop %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
case
(
BFMA1lI
[
1
]
)
0
:
begin
$display
(
"BFM Script Stop Command (NOTE)"
)
;
end
1
:
begin
$display
(
"BFM Script Stop Command (WARNING)"
)
;
end
3
:
begin
$display
(
"BFM Script Stop Command (FAILURE)"
)
;
$stop
;
end
default
:
begin
$display
(
"BFM Script Stop Command (ERROR)"
)
;
$stop
;
end
endcase
end
BFMA1lO0I
:
begin
BFMA1lOOOI
=
1
;
end
BFMA1OlIl
:
begin
BFMA1OI1OI
=
1
;
if
(
DEBUG
>=
1
)
$display
(
"BFM:%0d:echo at %0d ns"
,
BFMA1l01
,
$time
)
;
BFMA1OI01
=
2
+
BFMA1lI
[
1
]
;
$display
(
"BFM Parameter values are"
)
;
begin
:
BFMA1I0OII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1OI01
-
3
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
$display
(
" Para %0d=0x%08x (%0d)"
,
BFMA1I0I0
+
1
,
BFMA1lll1
[
2
+
BFMA1I0I0
]
,
BFMA1lll1
[
2
+
BFMA1I0I0
]
)
;
end
end
end
BFMA1lI0I
:
begin
BFMA1OI01
=
2
;
BFMA1lI11
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:flush %0d at %0d ns"
,
BFMA1l01
,
BFMA1lI11
,
$time
)
;
BFMA1OO11
=
1
;
BFMA1O001
=
1
;
end
BFMA1II1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1II10
=
BFMA1II10
+
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:setfail"
,
BFMA1l01
)
;
$display
(
"BFM: User Script detected ERROR (ERROR)"
)
;
$stop
;
end
BFMA1I01I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
BFMA1OIIOI
=
BFMA1lI
[
2
]
;
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1OIIOI
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:set %0d= 0x%08x (%0d)"
,
BFMA1l01
,
BFMA1lOIOI
,
BFMA1OIIOI
,
BFMA1OIIOI
)
;
end
BFMA1I11I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
BFMA1lI
[
2
]
+
3
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
4
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
5
]
,
DEBUG
)
;
BFMA1I0I0
=
6
;
while
(
BFMA1I0I0
<
BFMA1OI01
)
begin
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
BFMA1I0I0
]
,
BFMA1OIIOI
,
BFMA1lI
[
BFMA1I0I0
+
1
]
,
DEBUG
)
;
BFMA1I0I0
=
BFMA1I0I0
+
2
;
end
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1OIIOI
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:set %0d= 0x%08x (%0d)"
,
BFMA1l01
,
BFMA1lOIOI
,
BFMA1OIIOI
,
BFMA1OIIOI
)
;
end
BFMA1OIIl
:
begin
BFMA1OI1OI
=
1
;
if
(
BFMA1O11
)
begin
$fflush
(
BFMA1lIl1
)
;
$fclose
(
BFMA1lIl1
)
;
end
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1O000
+
1
]
)
;
BFMA1I011
=
BFMA1ll00
(
BFMA1O000
)
;
$display
(
"BFM:%0d:LOGFILE %0s"
,
BFMA1l01
,
BFMA1I011
)
;
BFMA1lIl1
=
$fopen
(
BFMA1I011
,
"w"
)
;
BFMA1O11
=
1
;
end
BFMA1IIIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
$display
(
"BFM:%0d:LOGSTART %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
if
(
BFMA1O11
==
0
)
begin
$display
(
"Logfile not defined, ignoring command (ERROR)"
)
;
end
else
begin
BFMA1lO0OI
=
(
(
BFMA1lll1
[
1
]
[
0
]
)
==
1
'b
1
)
;
BFMA1OI0OI
=
(
(
BFMA1lll1
[
1
]
[
1
]
)
==
1
'b
1
)
;
BFMA1II0OI
=
(
(
BFMA1lll1
[
1
]
[
2
]
)
==
1
'b
1
)
;
BFMA1lI0OI
=
(
(
BFMA1lll1
[
1
]
[
3
]
)
==
1
'b
1
)
;
end
end
BFMA1lIIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
$display
(
"BFM:%0d:LOGSTOP"
,
BFMA1l01
)
;
BFMA1lO0OI
=
0
;
BFMA1OI0OI
=
0
;
BFMA1II0OI
=
0
;
BFMA1lI0OI
=
0
;
end
BFMA1lOIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
$display
(
"BFM:%0d:VERSION"
,
BFMA1l01
)
;
$display
(
" BFM Verilog Version %0s"
,
BFMA1O
)
;
$display
(
" BFM Date %0s"
,
BFMA1I
)
;
$display
(
" SVN Revision $Revision: 11864 $"
)
;
$display
(
" SVN Date $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $"
)
;
$display
(
" Compiler Version %0d"
,
BFMA1Ol0OI
)
;
$display
(
" Vectors Version %0d"
,
BFMA1ll0OI
)
;
$display
(
" No of Vectors %0d"
,
BFMA1O0l1
)
;
if
(
BFMA1O11
!=
BFMA1OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d VR %0s %0s %0d %0d %0d"
,
$time
,
BFMA1O
,
BFMA1I
,
BFMA1Ol0OI
,
BFMA1ll0OI
,
BFMA1O0l1
)
;
end
end
default
:
begin
$display
(
"BFM: Instruction %0d Line Number %0d Command %0d"
,
BFMA1O000
,
BFMA1l01
,
BFMA1OO01
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
$display
(
"Instruction not yet implemented (ERROR)"
)
;
$stop
;
end
endcase
end
if
(
BFMA1OI1OI
)
begin
BFMA1OI11
=
0
;
BFMA1O000
=
BFMA1O000
+
BFMA1OI01
;
BFMA1OI01
=
0
;
end
end
BFMA1OlIOI
=
0
;
BFMA1IlIOI
=
0
;
BFMA1llIOI
=
0
;
if
(
BFMA1IlI
==
1
'b
1
)
begin
BFMA1IIIOI
=
BFMA1OOl
&
BFMA1IOl
;
BFMA1lIIOI
=
HRDATA
&
BFMA1IOl
;
BFMA1OlIOI
=
(
BFMA1IIIOI
===
BFMA1lIIOI
)
;
end
if
(
BFMA1I1l
==
1
'b
1
)
begin
BFMA1IIIOI
=
BFMA1lll
&
BFMA1O0l
;
BFMA1lIIOI
=
BFMA1IO0
&
BFMA1O0l
;
BFMA1IlIOI
=
(
BFMA1IIIOI
===
BFMA1lIIOI
)
;
end
if
(
BFMA1l1l
==
1
'b
1
)
begin
BFMA1IIIOI
=
BFMA1OIl
&
BFMA1IIl
;
BFMA1lIIOI
=
GP_IN
&
BFMA1IIl
;
BFMA1llIOI
=
(
BFMA1IIIOI
===
BFMA1lIIOI
)
;
end
BFMA1IOlOI
=
BFMA1I001
|
BFMA1I101
|
BFMA1l001
|
BFMA1O101
|
BFMA1l101
|
BFMA1IO11
|
BFMA1lO11
|
to_boolean
(
BFMA1IlI
|
BFMA1OlI
|
BFMA1lII
|
BFMA1III
|
BFMA1O1l
|
BFMA1I1l
|
BFMA1l1l
)
;
if
(
BFMA1O001
)
begin
case
(
BFMA1IO01
)
BFMA1lI0I
:
begin
if
(
~
BFMA1IOlOI
)
begin
if
(
BFMA1lI11
<=
1
)
begin
BFMA1O001
=
0
;
end
else
begin
BFMA1lI11
=
BFMA1lI11
-
1
;
end
end
end
BFMA1OO0I
:
begin
if
(
BFMA1lI11
<=
1
)
begin
BFMA1O001
=
0
;
end
else
begin
BFMA1lI11
=
BFMA1lI11
-
1
;
end
end
BFMA1l1Ol
,
BFMA1OOIl
:
begin
if
(
$time
>=
BFMA1O00OI
)
begin
BFMA1O001
=
0
;
end
end
BFMA1I1II
,
BFMA1O1II
,
BFMA1l0II
:
begin
if
(
BFMA1IlOOI
==
256
)
begin
BFMA1I1lOI
=
(
INTERRUPT
!=
BFMA1Ol1
)
;
end
else
begin
BFMA1I1lOI
=
(
(
INTERRUPT
[
BFMA1IlOOI
]
)
===
1
'b
1
)
;
end
if
(
BFMA1I1lOI
)
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:Interrupt Wait Time %0d cycles"
,
BFMA1OOIOI
)
;
BFMA1O001
=
0
;
end
end
BFMA1OOlI
:
begin
BFMA1OI0
<=
BFMA1Ol01
;
BFMA1lO0
<=
BFMA1Il01
;
BFMA1l0l
<=
1
'b
1
;
BFMA1O001
=
0
;
end
BFMA1lIlI
:
begin
BFMA1OI0
<=
BFMA1l011
+
BFMA1I111
;
BFMA1lO0
<=
BFMA1OOOOI
[
BFMA1I111
]
;
BFMA1l0l
<=
1
'b
1
;
BFMA1I111
=
BFMA1I111
+
1
;
if
(
BFMA1I111
>=
BFMA1O111
)
begin
BFMA1O001
=
0
;
end
end
BFMA1IOlI
,
BFMA1lOlI
,
BFMA1OIlI
:
begin
BFMA1OI0
<=
BFMA1Ol01
;
BFMA1OIl
<=
BFMA1Il01
;
BFMA1IIl
<=
BFMA1ll01
;
BFMA1lIl
<=
BFMA1l01
;
BFMA1Oll
<=
1
'b
1
;
if
(
BFMA1I1l
==
1
'b
1
)
begin
BFMA1O001
=
0
;
end
end
BFMA1IIlI
:
begin
if
(
EXT_WAIT
==
1
'b
0
&
BFMA1lI11
==
0
)
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:Exteral Wait Time %0d cycles"
,
BFMA1OOIOI
)
;
BFMA1O001
=
0
;
end
if
(
BFMA1lI11
>=
1
)
begin
BFMA1lI11
=
BFMA1lI11
-
1
;
end
end
BFMA1IlII
,
BFMA1llII
,
BFMA1l1OI
,
BFMA1OlII
:
begin
BFMA1Oll
<=
1
'b
1
;
BFMA1OIl
<=
BFMA1Il01
;
BFMA1IIl
<=
BFMA1ll01
;
BFMA1lIl
<=
BFMA1l01
;
BFMA1O001
=
0
;
end
BFMA1OOII
:
begin
BFMA1OIl
<=
BFMA1Il01
;
BFMA1IIl
<=
BFMA1ll01
;
BFMA1lIl
<=
BFMA1l01
;
BFMA1l1l
<=
1
'b
1
;
BFMA1Oll
<=
1
'b
0
;
if
(
BFMA1l1l
==
1
'b
1
&
BFMA1llIOI
)
begin
BFMA1l1l
<=
1
'b
0
;
BFMA1O001
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:GP IO Wait Time %0d cycles"
,
BFMA1OOIOI
)
;
end
end
BFMA1O00I
,
BFMA1I00I
:
begin
case
(
BFMA1lOO1
)
BFMA1Ol10
:
BFMA1O001
=
0
;
BFMA1Il10
:
begin
BFMA1OlO1
=
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
;
BFMA1I110
=
BFMA1lI
[
3
]
;
BFMA1l110
=
BFMA1lI
[
4
]
%
65536
;
BFMA1IOI1
=
(
(
BFMA1lll1
[
4
]
[
16
]
)
==
1
'b
1
)
;
BFMA1lOI1
=
(
(
BFMA1lll1
[
4
]
[
17
]
)
==
1
'b
1
)
;
BFMA1OII1
=
(
(
BFMA1lll1
[
4
]
[
18
]
)
==
1
'b
1
)
;
BFMA1OOO1
=
BFMA1lI
[
5
]
;
BFMA1IOO1
=
BFMA1lI
[
6
]
;
if
(
~
BFMA1OII1
)
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<
MAX_MEMTEST
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
BFMA1OIO1
[
BFMA1I0I0
]
=
0
;
BFMA1O0O1
=
0
;
BFMA1I0O1
=
0
;
BFMA1l0O1
=
0
;
BFMA1OOI1
=
0
;
BFMA1III1
=
0
;
if
(
BFMA1IO01
==
BFMA1I00I
)
begin
BFMA1OlO1
=
BFMA1lI
[
1
]
;
BFMA1IlO1
=
BFMA1lI
[
2
]
-
BFMA1I110
;
BFMA1I110
=
2
*
BFMA1I110
;
BFMA1OOI1
=
1
;
end
if
(
BFMA1IO01
==
BFMA1O00I
)
begin
$display
(
"BFM:%0d: memtest Started at %0d ns"
,
BFMA1l01
,
$time
)
;
$display
(
"BFM: Address %08x Size %0d Cycles %5d"
,
BFMA1OlO1
,
BFMA1I110
,
BFMA1OOO1
)
;
end
else
begin
$display
(
"BFM:%0d: dual memtest Started at %0d ns"
,
BFMA1l01
,
$time
)
;
$display
(
"BFM: Address %08x %08x Size %0d Cycles %5d"
,
BFMA1OlO1
,
BFMA1IlO1
+
BFMA1I110
/
2
,
BFMA1I110
/
2
,
BFMA1OOO1
)
;
end
case
(
BFMA1l110
)
0
:
begin
end
1
:
$display
(
"BFM: Transfers are APB Byte aligned"
)
;
2
:
$display
(
"BFM: Transfers are APB Half Word aligned"
)
;
3
:
$display
(
"BFM: Transfers are APB Word aligned"
)
;
4
:
$display
(
"BFM: Byte Writes Suppressed"
)
;
default
:
$display
(
"Illegal Align on memtest (FAILURE)"
)
;
endcase
if
(
BFMA1OII1
)
begin
$display
(
"BFM: memtest restarted"
)
;
end
if
(
BFMA1IOI1
)
begin
$display
(
"BFM: Memtest Filling Memory"
)
;
BFMA1lOO1
=
BFMA1I010
;
end
else
if
(
BFMA1OOO1
>
0
)
begin
$display
(
"BFM: Memtest Random Read Writes"
)
;
BFMA1lOO1
=
BFMA1ll10
;
end
else
if
(
BFMA1lOI1
)
begin
$display
(
"BFM: Memtest Verifying Memory Content"
)
;
BFMA1lOO1
=
BFMA1l010
;
end
else
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
BFMA1ll10
,
BFMA1I010
,
BFMA1l010
:
begin
if
(
~
(
BFMA1I101
|
BFMA1I001
)
)
begin
case
(
BFMA1lOO1
)
BFMA1ll10
:
begin
BFMA1IOO1
=
BFMA1lIl0
(
BFMA1IOO1
)
;
BFMA1IIO1
=
BFMA1O1l0
(
BFMA1IOO1
,
BFMA1I110
)
;
BFMA1IOO1
=
BFMA1lIl0
(
BFMA1IOO1
)
;
BFMA1lIO1
=
BFMA1O1l0
(
BFMA1IOO1
,
8
)
;
end
BFMA1I010
:
begin
BFMA1IIO1
=
BFMA1III1
;
BFMA1lIO1
=
6
;
end
BFMA1l010
:
begin
BFMA1IIO1
=
BFMA1III1
;
BFMA1lIO1
=
2
;
end
default
:
begin
end
endcase
case
(
BFMA1l110
)
0
:
begin
end
1
:
begin
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
case
(
BFMA1lIO1
)
0
,
4
:
begin
BFMA1lIO1
=
BFMA1lIO1
;
end
1
,
5
:
begin
BFMA1lIO1
=
BFMA1lIO1
-
1
;
end
2
,
6
:
begin
BFMA1lIO1
=
BFMA1lIO1
-
2
;
end
default
:
begin
end
endcase
end
2
:
begin
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
case
(
BFMA1lIO1
)
0
,
4
:
begin
BFMA1lIO1
=
BFMA1lIO1
+
1
;
end
1
,
5
:
begin
BFMA1lIO1
=
BFMA1lIO1
;
end
2
,
6
:
begin
BFMA1lIO1
=
BFMA1lIO1
-
1
;
end
default
:
begin
end
endcase
end
3
:
begin
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
case
(
BFMA1lIO1
)
0
,
4
:
begin
BFMA1lIO1
=
BFMA1lIO1
+
2
;
end
1
,
5
:
begin
BFMA1lIO1
=
BFMA1lIO1
+
1
;
end
2
,
6
:
begin
BFMA1lIO1
=
BFMA1lIO1
;
end
default
:
begin
end
endcase
end
4
:
begin
case
(
BFMA1lIO1
)
4
:
begin
BFMA1IIO1
=
2
*
(
BFMA1IIO1
/
2
)
;
BFMA1lIO1
=
5
;
end
default
:
begin
end
endcase
end
default
:
begin
end
endcase
if
(
BFMA1lIO1
>=
0
&
BFMA1lIO1
<=
2
)
begin
case
(
BFMA1lIO1
)
0
:
begin
BFMA1lI01
=
3
'b
000
;
BFMA1IIO1
=
BFMA1IIO1
;
BFMA1llO1
=
(
BFMA1OIO1
[
BFMA1IIO1
+
0
]
>=
256
)
;
end
1
:
begin
BFMA1lI01
=
3
'b
001
;
BFMA1IIO1
=
2
*
(
BFMA1IIO1
/
2
)
;
BFMA1llO1
=
(
(
BFMA1OIO1
[
BFMA1IIO1
+
0
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
1
]
>=
256
)
)
;
end
2
:
begin
BFMA1lI01
=
3
'b
010
;
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
BFMA1llO1
=
(
(
BFMA1OIO1
[
BFMA1IIO1
+
0
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
1
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
2
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
3
]
>=
256
)
)
;
end
default
:
begin
end
endcase
if
(
BFMA1llO1
)
begin
BFMA1I001
=
1
;
BFMA1O0O1
=
BFMA1O0O1
+
1
;
if
(
BFMA1OOI1
==
1
&
BFMA1IIO1
>=
BFMA1I110
/
2
)
begin
BFMA1Ol01
=
BFMA1IlO1
+
BFMA1IIO1
;
end
else
begin
BFMA1Ol01
=
BFMA1OlO1
+
BFMA1IIO1
;
end
case
(
BFMA1lIO1
)
0
:
begin
BFMA1Il01
=
{
BFMA1lI1
[
31
:
8
]
,
BFMA1OIO1
[
BFMA1IIO1
+
0
]
[
7
:
0
]
}
;
end
1
:
begin
BFMA1Il01
=
{
BFMA1lI1
[
31
:
16
]
,
BFMA1OIO1
[
BFMA1IIO1
+
1
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
0
]
[
7
:
0
]
}
;
end
2
:
begin
BFMA1Il01
=
{
BFMA1OIO1
[
BFMA1IIO1
+
3
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
2
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
1
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
0
]
[
7
:
0
]
}
;
end
default
:
begin
BFMA1Il01
=
BFMA1lI1
[
31
:
0
]
;
end
endcase
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
end
else
begin
BFMA1lIO1
=
BFMA1lIO1
+
4
;
if
(
BFMA1lIO1
==
4
&
BFMA1l110
==
4
)
begin
BFMA1lIO1
=
5
;
end
end
end
if
(
BFMA1lIO1
>=
4
&
BFMA1lIO1
<=
6
)
begin
BFMA1I101
=
1
;
BFMA1I0O1
=
BFMA1I0O1
+
1
;
BFMA1IOO1
=
BFMA1lIl0
(
BFMA1IOO1
)
;
BFMA1Il01
=
BFMA1IOO1
;
case
(
BFMA1lIO1
)
4
:
begin
BFMA1lI01
=
3
'b
000
;
BFMA1IIO1
=
BFMA1IIO1
;
BFMA1OIO1
[
BFMA1IIO1
+
0
]
=
256
+
BFMA1Il01
[
7
:
0
]
;
end
5
:
begin
BFMA1lI01
=
3
'b
001
;
BFMA1IIO1
=
2
*
(
BFMA1IIO1
/
2
)
;
BFMA1OIO1
[
BFMA1IIO1
+
0
]
=
256
+
BFMA1Il01
[
7
:
0
]
;
BFMA1OIO1
[
BFMA1IIO1
+
1
]
=
256
+
BFMA1Il01
[
15
:
8
]
;
end
6
:
begin
BFMA1lI01
=
3
'b
010
;
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
BFMA1OIO1
[
BFMA1IIO1
+
0
]
=
256
+
BFMA1Il01
[
7
:
0
]
;
BFMA1OIO1
[
BFMA1IIO1
+
1
]
=
256
+
BFMA1Il01
[
15
:
8
]
;
BFMA1OIO1
[
BFMA1IIO1
+
2
]
=
256
+
BFMA1Il01
[
23
:
16
]
;
BFMA1OIO1
[
BFMA1IIO1
+
3
]
=
256
+
BFMA1Il01
[
31
:
24
]
;
end
default
:
begin
end
endcase
if
(
BFMA1OOI1
==
1
&
BFMA1IIO1
>=
BFMA1I110
/
2
)
begin
BFMA1Ol01
=
BFMA1IlO1
+
BFMA1IIO1
;
end
else
begin
BFMA1Ol01
=
BFMA1OlO1
+
BFMA1IIO1
;
end
end
if
(
BFMA1lIO1
==
3
|
BFMA1lIO1
==
7
)
begin
BFMA1l0O1
=
BFMA1l0O1
+
1
;
end
BFMA1III1
=
BFMA1III1
+
4
;
case
(
BFMA1lOO1
)
BFMA1ll10
:
begin
if
(
BFMA1OOO1
>
0
)
begin
BFMA1OOO1
=
BFMA1OOO1
-
1
;
end
else
if
(
BFMA1lOI1
)
begin
BFMA1III1
=
0
;
BFMA1lOO1
=
BFMA1l010
;
$display
(
"BFM: Memtest Verifying Memory Content"
)
;
end
else
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
BFMA1I010
:
begin
if
(
BFMA1III1
>=
BFMA1I110
)
begin
if
(
BFMA1OOO1
==
0
)
begin
if
(
BFMA1lOI1
)
begin
BFMA1III1
=
0
;
BFMA1lOO1
=
BFMA1l010
;
$display
(
"BFM: Memtest Verifying Memory Content"
)
;
end
else
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
else
begin
BFMA1lOO1
=
BFMA1ll10
;
$display
(
"BFM: Memtest Random Read Writes"
)
;
end
end
end
BFMA1l010
:
begin
if
(
BFMA1III1
>=
BFMA1I110
)
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
default
:
begin
end
endcase
BFMA1Il11
=
BFMA1II01
;
end
end
BFMA1O010
:
begin
if
(
~
BFMA1IOlOI
)
begin
BFMA1lOO1
=
BFMA1Ol10
;
$display
(
"BFM: bfmtest complete Writes %0d Reads %0d Nops %0d"
,
BFMA1I0O1
,
BFMA1O0O1
,
BFMA1l0O1
)
;
end
end
endcase
end
default
:
begin
end
endcase
end
if
(
BFMA1OO0OI
==
0
)
begin
BFMA1IO0OI
=
0
;
BFMA1OO0OI
=
BFMA1IllOI
;
end
else
begin
BFMA1OO0OI
=
BFMA1OO0OI
-
1
;
BFMA1IO0OI
=
1
;
end
if
(
HREADY
==
1
'b
1
)
begin
BFMA1l0
<=
2
'b
00
;
BFMA1O1
<=
1
'b
0
;
BFMA1lII
<=
1
'b
0
;
BFMA1OlI
<=
1
'b
0
;
BFMA1llI
<=
1
'b
0
;
if
(
BFMA1lII
==
1
'b
1
|
BFMA1OlI
==
1
'b
1
)
begin
BFMA1I0I
<=
1
'b
0
;
end
if
(
BFMA1I101
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
1
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1l0
<=
2
'b
10
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1l1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1lII
<=
1
'b
1
;
BFMA1O00
<=
BFMA1l01
;
BFMA1I101
=
0
;
end
if
(
BFMA1I001
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
0
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1l0
<=
2
'b
10
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1I1I
<=
BFMA1OIO0
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1ll01
,
BFMA1I0lOI
)
;
BFMA1O00
<=
BFMA1l01
;
BFMA1OlI
<=
1
'b
1
;
BFMA1I0I
<=
1
'b
1
;
BFMA1I001
=
0
;
end
if
(
BFMA1IO11
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
BFMA1I00OI
;
BFMA1ll
<=
BFMA1I10OI
;
BFMA1l0
<=
BFMA1l00OI
;
BFMA1O0
<=
BFMA1l10OI
;
BFMA1I0
<=
BFMA1O10OI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1l1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1lII
<=
1
'b
1
;
BFMA1O00
<=
BFMA1l01
;
BFMA1IO11
=
0
;
end
if
(
BFMA1l101
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
0
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1I1I
<=
BFMA1OIO0
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1ll01
,
BFMA1I0lOI
)
;
BFMA1O00
<=
BFMA1l01
;
if
(
BFMA1OlI
==
1
'b
1
|
BFMA1IlI
==
1
'b
1
)
begin
BFMA1l0
<=
2
'b
00
;
end
else
begin
BFMA1l0
<=
2
'b
10
;
BFMA1OlI
<=
1
'b
1
;
BFMA1llI
<=
1
'b
1
;
end
if
(
BFMA1O0I
==
1
'b
1
&
BFMA1OlIOI
)
begin
BFMA1l101
=
0
;
end
end
if
(
BFMA1l001
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
1
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O00
<=
BFMA1l01
;
if
(
BFMA1IO0OI
)
begin
BFMA1l0
<=
2
'b
01
;
end
else
begin
BFMA1l1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
to_slv32
(
BFMA1OOOOI
[
BFMA1I111
]
)
,
BFMA1I0lOI
)
;
BFMA1lII
<=
1
'b
1
;
if
(
BFMA1I111
==
0
|
BFMA1l1l1
==
3
|
bound1k
(
BFMA1O0lOI
,
BFMA1Ol01
)
)
begin
BFMA1l0
<=
2
'b
10
;
end
else
begin
BFMA1l0
<=
2
'b
11
;
end
BFMA1Ol01
=
BFMA1Ol01
+
BFMA1l111
;
BFMA1I111
=
BFMA1I111
+
1
;
if
(
BFMA1I111
==
BFMA1O111
)
begin
BFMA1l001
=
0
;
end
end
end
if
(
BFMA1O101
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
0
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O00
<=
BFMA1l01
;
if
(
BFMA1IO0OI
)
begin
BFMA1l0
<=
2
'b
01
;
end
else
begin
BFMA1O1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
to_slv32
(
BFMA1OOOOI
[
BFMA1I111
]
)
,
BFMA1I0lOI
)
;
BFMA1I1I
<=
BFMA1OIO0
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1ll01
,
BFMA1I0lOI
)
;
BFMA1OlI
<=
1
'b
1
;
BFMA1I0I
<=
1
'b
1
;
if
(
BFMA1I111
==
0
|
BFMA1l1l1
==
3
|
bound1k
(
BFMA1O0lOI
,
BFMA1Ol01
)
)
begin
BFMA1l0
<=
2
'b
10
;
end
else
begin
BFMA1l0
<=
2
'b
11
;
end
BFMA1Ol01
=
BFMA1Ol01
+
BFMA1l111
;
BFMA1I111
=
BFMA1I111
+
1
;
if
(
BFMA1I111
==
BFMA1O111
)
begin
BFMA1O101
=
0
;
end
end
end
end
if
(
HREADY
==
1
'b
1
)
begin
BFMA1III
<=
BFMA1lII
;
BFMA1IlI
<=
BFMA1OlI
;
BFMA1O0I
<=
BFMA1llI
;
BFMA1l0I
<=
BFMA1I0I
;
BFMA1OOl
<=
BFMA1O1I
;
BFMA1IOl
<=
BFMA1I1I
;
BFMA1I00
<=
BFMA1O00
;
BFMA1OOI
<=
BFMA1l1
;
BFMA1lOI
<=
BFMA1IOI
;
end
BFMA1I1l
<=
BFMA1O1l
;
BFMA1II0
<=
BFMA1OI0
;
BFMA1Ill
<=
BFMA1Oll
;
BFMA1lll
<=
BFMA1OIl
;
BFMA1O0l
<=
BFMA1IIl
;
BFMA1I0l
<=
BFMA1lIl
;
if
(
HREADY
==
1
'b
1
)
begin
if
(
BFMA1lII
==
1
'b
1
)
begin
BFMA1lOl
<=
BFMA1l1I
;
end
else
begin
BFMA1lOl
<=
{
32
{
1
'b
0
}
}
;
end
if
(
BFMA1III
==
1
'b
1
&
DEBUG
>=
3
)
begin
$display
(
"BFM: Data Write %08x %08x"
,
BFMA1OOI
,
BFMA1lOl
)
;
end
if
(
BFMA1lO0OI
&
BFMA1III
==
1
'b
1
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d AW %c %08x %08x"
,
$time
,
BFMA1IlO0
(
BFMA1lOI
)
,
BFMA1OOI
,
BFMA1lOl
)
;
end
end
if
(
BFMA1OO0
==
1
'b
1
&
BFMA1II0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d GW %08x "
,
$time
,
BFMA1O10
)
;
end
if
(
BFMA1l0l
==
1
'b
1
&
BFMA1OI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d EW %08x %08x"
,
$time
,
BFMA1OI0
,
BFMA1lO0
)
;
end
if
(
HREADY
==
1
'b
1
)
begin
if
(
BFMA1IlI
==
1
'b
1
)
begin
if
(
DEBUG
>=
3
)
begin
if
(
BFMA1IOl
==
BFMA1lI1
)
begin
$display
(
"BFM: Data Read %08x %08x"
,
BFMA1OOI
,
HRDATA
)
;
end
else
begin
$display
(
"BFM: Data Read %08x %08x MASK:%08x"
,
BFMA1OOI
,
HRDATA
,
BFMA1IOl
)
;
end
end
if
(
BFMA1lO0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d AR %c %08x %08x"
,
$time
,
BFMA1IlO0
(
BFMA1lOI
)
,
BFMA1OOI
,
HRDATA
)
;
end
if
(
BFMA1OOlOI
>=
0
)
begin
BFMA1ll1
[
BFMA1OOlOI
]
=
BFMA1O01l
(
BFMA1IIO0
(
BFMA1lOI
,
BFMA1OOI
[
1
:
0
]
,
HRDATA
,
BFMA1I0lOI
)
)
;
end
if
(
BFMA1l0I
==
1
'b
1
&
~
BFMA1OlIOI
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: AHB Data Read Comparison failed Addr:%08x Got:%08x EXP:%08x (MASK:%08x)"
,
BFMA1OOI
,
HRDATA
,
BFMA1OOl
,
BFMA1IOl
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Data Compare Error (ERROR)"
)
;
$stop
;
if
(
BFMA1lO0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d ERROR Addr:%08x Got:%08x EXP:%08x (MASK:%08x)"
,
$time
,
BFMA1OOI
,
HRDATA
,
BFMA1OOl
,
BFMA1IOl
)
;
end
end
end
end
if
(
BFMA1l1l
==
1
'b
1
)
begin
if
(
DEBUG
>=
3
)
begin
if
(
BFMA1IIl
==
BFMA1lI1
)
begin
$display
(
"BFM: GP IO Data Read %08x"
,
GP_IN
)
;
end
else
begin
$display
(
"BFM: GP IO Data Read %08x MASK:%08x"
,
GP_IN
,
BFMA1IIl
)
;
end
end
if
(
BFMA1II0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d GR %08x "
,
$time
,
BFMA1OIl
)
;
end
if
(
BFMA1OOlOI
>=
0
)
begin
BFMA1ll1
[
BFMA1OOlOI
]
=
GP_IN
;
end
if
(
BFMA1Oll
==
1
'b
1
&
~
BFMA1llIOI
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"GPIO input not as expected Got:%08x EXP:%08x (MASK:%08x)"
,
GP_IN
,
BFMA1OIl
,
BFMA1IIl
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1lIl
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1lIl
,
BFMA1IIlOI
)
)
;
$display
(
"BFM GPIO Compare Error (ERROR)"
)
;
$stop
;
if
(
BFMA1II0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"ERROR Got:%08x EXP:%08x (MASK:%08x)"
,
GP_IN
,
BFMA1OIl
,
BFMA1IIl
)
;
end
end
end
if
(
BFMA1I1l
==
1
'b
1
)
begin
if
(
DEBUG
>=
3
)
begin
if
(
BFMA1O0l
==
BFMA1lI1
)
begin
$display
(
"BFM: Extention Data Read %08x %08x"
,
BFMA1II0
,
BFMA1IO0
)
;
end
else
begin
$display
(
"BFM: Extention Data Read %08x %08x MASK:%08x"
,
BFMA1II0
,
BFMA1IO0
,
BFMA1O0l
)
;
end
end
if
(
BFMA1OI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d ER %08x %08x"
,
$time
,
BFMA1II0
,
BFMA1lll
)
;
end
if
(
BFMA1OOlOI
>=
0
)
begin
BFMA1ll1
[
BFMA1OOlOI
]
=
BFMA1O01l
(
BFMA1IO0
)
;
end
if
(
BFMA1Ill
==
1
'b
1
&
~
BFMA1IlIOI
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: Extention Data Read Comparison FAILED Got:%08x EXP:%08x (MASK:%08x)"
,
BFMA1IO0
,
BFMA1lll
,
BFMA1O0l
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I0l
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I0l
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Extention Data Compare Error (ERROR)"
)
;
$stop
;
if
(
BFMA1OI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"ERROR Got:%08x EXP:%08x (MASK:%08x)"
,
BFMA1IO0
,
BFMA1lll
,
BFMA1O0l
)
;
end
end
end
BFMA1OO1OI
=
BFMA1I001
|
BFMA1I101
|
BFMA1l001
|
BFMA1O101
|
BFMA1l101
|
BFMA1IO11
|
to_boolean
(
BFMA1OlI
|
BFMA1lII
|
BFMA1O1l
|
BFMA1l1l
)
|
(
to_boolean
(
(
BFMA1IlI
|
BFMA1III
)
&
~
HREADY
)
)
;
if
(
BFMA1O001
)
begin
case
(
BFMA1IO01
)
BFMA1OI1I
:
begin
if
(
~
BFMA1OO1OI
)
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktime was %0d cycles "
,
BFMA1l01
,
BFMA1OOIOI
)
;
if
(
BFMA1OOIOI
<
BFMA1lI
[
1
]
|
BFMA1OOIOI
>
BFMA1lI
[
2
]
)
begin
$display
(
"BFM: ERROR checktime %0d %0d Actual %0d"
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1OOIOI
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
$display
(
"BFM checktime failure (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1O001
=
0
;
BFMA1I1O1
=
BFMA1OOIOI
;
end
end
BFMA1Ol1I
:
begin
if
(
~
BFMA1OO1OI
)
begin
BFMA1l1O1
=
BFMA1l1O1
-
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktimer was %0d cycles "
,
BFMA1l01
,
BFMA1l1O1
)
;
if
(
BFMA1l1O1
<
BFMA1lI
[
1
]
|
BFMA1l1O1
>
BFMA1lI
[
2
]
)
begin
$display
(
"BFM: ERROR checktimer %0d %0d Actual %0d"
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1l1O1
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
$display
(
"BFM checktimer failure (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1O001
=
0
;
BFMA1O1O1
=
BFMA1l1O1
;
end
end
default
:
begin
end
endcase
end
if
(
BFMA1l0lOI
)
begin
if
(
BFMA1Il11
>
0
)
begin
BFMA1Il11
=
BFMA1Il11
-
1
;
end
else
begin
BFMA1Il11
=
BFMA1II01
;
$display
(
"BFM Command Timeout Occured"
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
if
(
~
BFMA1lOOOI
)
$display
(
"BFM Command timeout occured (ERROR)"
)
;
if
(
BFMA1lOOOI
)
$display
(
"BFM Completed and timeout occured (ERROR)"
)
;
$stop
;
end
end
else
begin
BFMA1Il11
=
BFMA1II01
;
end
if
(
BFMA1II10
>
0
)
begin
BFMA1OO1
<=
1
'b
1
;
end
if
(
BFMA1O001
|
BFMA1I001
|
BFMA1I101
|
BFMA1l001
|
BFMA1O101
|
BFMA1l101
|
BFMA1IO11
|
(
(
BFMA1OO11
|
BFMA1lllOI
)
&
BFMA1IOlOI
)
)
begin
BFMA1OI11
=
1
;
end
else
begin
BFMA1OO11
=
0
;
if
(
~
BFMA1lOOOI
)
begin
BFMA1OI11
=
0
;
end
BFMA1O000
=
BFMA1O000
+
BFMA1OI01
;
BFMA1OI01
=
0
;
if
(
OPMODE
>
0
)
begin
if
(
BFMA1O1lOI
|
BFMA1lOOOI
)
begin
BFMA1l0lOI
=
0
;
BFMA1OI11
=
0
;
end
end
end
if
(
BFMA1l10
==
1
'b
0
&
OPMODE
==
0
&
BFMA1lOOOI
&
~
BFMA1IOlOI
)
begin
$display
(
"###########################################################"
)
;
$display
(
" "
)
;
if
(
BFMA1II10
==
0
)
begin
$display
(
"BFM Simulation Complete - %0d Instructions - NO ERRORS"
,
BFMA1IOIOI
)
;
end
else
begin
$display
(
"BFM Simulation Complete - %0d Instructions - %0d ERRORS OCCURED"
,
BFMA1IOIOI
,
BFMA1II10
)
;
end
$display
(
" "
)
;
$display
(
"###########################################################"
)
;
$display
(
" "
)
;
BFMA1l10
<=
1
'b
1
;
BFMA1OI11
=
1
;
BFMA1l0lOI
=
0
;
if
(
BFMA1O11
)
begin
$fflush
(
BFMA1lIl1
)
;
$fclose
(
BFMA1lIl1
)
;
end
if
(
BFMA1l1lOI
==
1
)
$stop
;
if
(
BFMA1l1lOI
==
2
)
$finish
;
end
CON_BUSY
<=
(
BFMA1l0lOI
|
BFMA1IOlOI
)
;
INSTR_OUT
<=
to_slv32
(
BFMA1O000
)
;
end
end
assign
#
TPD
GP_OUT
=
BFMA1O10
;
assign
#
TPD
EXT_WR
=
BFMA1l0l
;
assign
#
TPD
EXT_RD
=
BFMA1O1l
;
assign
#
TPD
EXT_ADDR
=
BFMA1OI0
;
assign
#
TPD
EXT_DATA
=
(
BFMA1l0l
==
1
'b
1
)
?
BFMA1lO0
:
{
32
{
1
'b
z
}
}
;
assign
BFMA1IO0
=
EXT_DATA
;
always
@
(
BFMA1l1
)
begin
begin
:
BFMA1l0OII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OII
[
BFMA1I0I0
]
<=
(
BFMA1l1
[
31
:
28
]
==
BFMA1I0I0
)
;
end
end
end
assign
HCLK
=
(
BFMA1IO1
)
?
1
'b
x
:
(
SYSCLK
|
BFMA1l00
)
;
assign
PCLK
=
(
BFMA1IO1
)
?
1
'b
x
:
(
SYSCLK
|
BFMA1l00
)
;
assign
#
TPD
HRESETN
=
(
BFMA1lO1
)
?
1
'b
x
:
BFMA1Il
;
assign
#
TPD
HADDR
=
(
BFMA1OI1
)
?
{
32
{
1
'b
x
}
}
:
BFMA1l1
;
assign
#
TPD
HWDATA
=
(
BFMA1II1
)
?
{
32
{
1
'b
x
}
}
:
BFMA1lOl
;
assign
#
TPD
HBURST
=
(
BFMA1OI1
)
?
{
3
{
1
'b
x
}
}
:
BFMA1ll
;
assign
#
TPD
HMASTLOCK
=
(
BFMA1OI1
)
?
1
'b
x
:
BFMA1O0
;
assign
#
TPD
HPROT
=
(
BFMA1OI1
)
?
{
4
{
1
'b
x
}
}
:
BFMA1I0
;
assign
#
TPD
HSIZE
=
(
BFMA1OI1
)
?
{
3
{
1
'b
x
}
}
:
BFMA1IOI
;
assign
#
TPD
HTRANS
=
(
BFMA1OI1
)
?
{
2
{
1
'b
x
}
}
:
BFMA1l0
;
assign
#
TPD
HWRITE
=
(
BFMA1OI1
)
?
1
'b
x
:
BFMA1O1
;
assign
#
TPD
HSEL
=
(
BFMA1OI1
)
?
{
16
{
1
'b
x
}
}
:
BFMA1OII
;
assign
#
TPD
CON_DATA
=
(
BFMA1Il0
==
1
'b
1
)
?
BFMA1Ol0
:
{
32
{
1
'b
z
}
}
;
assign
BFMA1lI0
=
CON_DATA
;
assign
#
TPD
FINISHED
=
BFMA1l10
;
assign
#
TPD
FAILED
=
BFMA1OO1
;
endmodule |
module signature as counter.v, which implements a period counter with inversion to give the frequency counter.
The frequency counter counts edges of the RF signal input in a register, and gates this counting with a fixed time period as measured by counting of clock edges. The +- count error of this scheme is associated with the RF signal, as opposed to the clock, so when the RF signal is slower than the clock, the period counter will have a smaller error for the same measurement time (i.e. a longer measurement time would be needed with the frequency counter, so that the error is reduced by averaging, in order to achieve the same error from the period counter).
PARAMETER SELECTION:
F_rf = #cnts/time period +-1 / (time period)
=> error= +- 1/time period = 500 Hz = acceptable error
=> time period = 1/500 Hz = 0.002 s
With 4 MHz clock => 2E-3*4E6=8E3 clock posedges count in time period.
Ted Golfinopoulos, 25 Oct 2011
*/
`define CLK_COUNTER_SIZE 14 //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 10 //Number of bits in signal edge counter.
input clk, sig;
output reg [13:0] f; //Allows frequency count up to 819.2 kHz.
reg [13:0] n_clk; //Counter for clock positive edges.
reg [9:0] n_sig; //Counter for signal positive edges.
reg reset; //Reset flag set every NUM_CNTS_AVG clock cycles to re-compute frequency and restart counters.
parameter F_CLK=40000; //Clock frequency in HUNDREDS OF Hz.
parameter ERR=5; //Allowable frequency measurement error, HUNDREDS OF Hz.
parameter NUM_CNTS_AVG=F_CLK/ERR; //Number of clock edge counts required such that averaging reduces +-1 count error to acceptable levels.
parameter F_SCALE=ERR; //Scale rf signal counter by this amount to give a frequency measurement in HUNDREDS OF Hz.
parameter N_SIG_MAX=`SIG_COUNTER_SIZE'b1111111111; //Maximum value sig edge counter can reach.
initial begin
reset=1'b1; //Initialize reset signal counter flag low so that counting only starts when gate is actually opened.
n_clk=`CLK_COUNTER_SIZE'b0; //Initialize clock counter.
n_sig=`SIG_COUNTER_SIZE'b0; //Initialize signal counter.
end
always @(posedge clk) begin
//As for period counter, but swap gate and registered count, n_sig and n_clk, so that now, n_clk is the gate.
//n_sig is not counted when n_clk is between 0 and 1.
//The gate is open between n_clk Edges 1 and (NUM_CNTS_AVG+1) (which is also Edge 0), corresponding to
// NUM_CNTS_AVG clock intervals.
//Then f=(n_sig+-1)/(tau_clk*NUM_CNTS_AVG) = (n_sig+-1)*f_clk/NUM_CNTS_AVG => error = +-1*f_clk/NUM_CNTS_AVG.
if(n_clk>=NUM_CNTS_AVG) begin //Close frequency counter gate. Subtract one from count because actually start counting signal edges at n_clk=1.
f=F_SCALE*n_sig; //Compute frequency.
reset = 1'b1; //Set flag to re-compute the frequency and restart the frequency counter.
n_clk = 1'b0; //Restart clock positive edge counter.
end else begin
//Keep reset flag low (turn off on next clock cycle).
reset = 1'b0;
n_clk=n_clk+`CLK_COUNTER_SIZE'b1; //Increment clock cycle counter.
end
end
always @(posedge sig or posedge reset) begin
if(reset==1) begin
n_sig=`SIG_COUNTER_SIZE'b0; //Reset RF signal counter.
end else if(n_sig<=N_SIG_MAX) begin //Handle overflow gracefully - stop counting when register is saturated.
n_sig=n_sig+`SIG_COUNTER_SIZE'b1; //Increment frequency counter.
end
end
endmodule |
module design_1_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(1),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(4'H0),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(2'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule |
module amm_master_qsys_with_pcie_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule |
module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule |
module sky130_fd_sc_ms__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
$write("P0%d(%d)|P1%d(%d)|P2%d(%d)|P3%d(%d)",
c.phase_a[2:0], c.pchange_a, c.phase_b[2:0], c.pchange_b,
c.phase_c[2:0], c.pchange_c, c.phase_d[2:0], c.pchange_d);
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
if (c.F01_deq2) $write("%d", c.F01_dot2); else $write(" ");
if (c.F01_deq3) $write("%d", c.F01_dot3); else $write(" ");
if (c.F01_deq4) $write("%d", c.F01_dot4); else $write(" ");
if (c.F01_deq5) $write("%d", c.F01_dot5); else $write(" ");
if (c.F01_deq6) $write("%d", c.F01_dot6); else $write(" ");
if (c.F01_deq7) $write("%d", c.F01_dot7); else $write(" ");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if(c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase0: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase1: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule |
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule |
module tb;
// Inputs
reg rxd;
reg rst;
reg clk;
// Outputs
wire txd;
// Instantiate the Unit Under Test (UUT)
top uut (
.txd(txd),
.rxd(rxd),
.rst(rst),
.clk(clk)
);
initial begin
// Initialize Inputs
rxd = 0;
rst = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rxd = 1;
rst = 1;
#100;
rst = 0;
#10000;
rxd = 0;
#9500;
rxd = 1; // bit 0 (LSB)
#9500;
rxd = 0; // bit 1
#9500;
rxd = 1; // bit 2
#9500;
rxd = 0; // bit 3
#9500;
rxd = 1; // bit 4
#9500;
rxd = 0; // bit 5
#9500;
rxd = 1; // bit 6
#9500;
rxd = 0; // bit 7
#9500;
rxd = 1;
#9500;
// sent 0101 0101
#100000;
rxd=0;
#9500;
rxd=1;
#100000;
end
always begin
#20 clk = ~clk;
end
endmodule |
module bw_clk_gclk_inv_r90_256x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule |
module diffiodelay
#(
parameter NINPUT = 20,
parameter NOUTPUT = 1,
parameter INPUT_DIFF_TERM = "TRUE",
parameter IODELAY_GROUP_NAME = "iodelay_grp"
)
(
input RESET,
input CLK, //% DELAY_* must be synchronous to this clock
input [7:0] DELAY_CHANNEL,
input [4:0] DELAY_VALUE,
input DELAY_UPDATE, //% a pulse to update the delay value
output [NINPUT-1:0] INPUTS_OUT,
input [NINPUT-1:0] INPUTS_P,
input [NINPUT-1:0] INPUTS_N,
input [NOUTPUT-1:0] OUTPUTS_IN,
output [NOUTPUT-1:0] OUTPUTS_P,
output [NOUTPUT-1:0] OUTPUTS_N
);
reg [(NINPUT+NOUTPUT)-1:0] delay_update_v;
wire du;
reg du_prev, du_prev1;
wire [NINPUT-1:0] inputs_out_i;
wire [NOUTPUT-1:0] outputs_in_i;
// select which channel to write the delay_value to
always @ (DELAY_CHANNEL, du) begin
delay_update_v <= 0;
delay_update_v[DELAY_CHANNEL] <= du;
end
// capture the rising edge
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
du_prev <= 0;
du_prev1 <= 0;
end
else begin
du_prev <= DELAY_UPDATE;
du_prev1 <= du_prev;
end
end
assign du = (~du_prev1)&(du_prev);
genvar i;
generate
for (i=0; i<NINPUT; i=i+1) begin
IBUFDS
#(
.DIFF_TERM(INPUT_DIFF_TERM), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
)
ibufds_inst
(
.O(inputs_out_i[i]), // Buffer output
.I(INPUTS_P[i]), // Diff_p buffer input (connect directly to top-level port)
.IB(INPUTS_N[i]) // Diff_n buffer input (connect directly to top-level port)
);
(* IODELAY_GROUP = IODELAY_GROUP_NAME *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2
#(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
idelaye2_inst
(
.CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(INPUTS_OUT[i]), // 1-bit output: Delayed data output
.C(CLK), // 1-bit input: Clock input
.CE(0), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(DELAY_VALUE), // 5-bit input: Counter value input
.DATAIN(0), // 1-bit input: Internal delay data input
.IDATAIN(inputs_out_i[i]), // 1-bit input: Data input from the I/O
.INC(0), // 1-bit input: Increment / Decrement tap delay input
.LD(delay_update_v[i]), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(0) // 1-bit input: Active-high reset tap-delay input
);
end
for (i=0; i<NOUTPUT; i=i+1) begin
// ODELAYE2 only exists in HP banks!
(* IODELAY_GROUP = IODELAY_GROUP_NAME *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
ODELAYE2
#(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.ODELAY_VALUE(0), // Output delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
odelaye2_inst
(
.CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(outputs_in_i[i]), // 1-bit output: Delayed data/clock output
.C(CLK), // 1-bit input: Clock input
.CE(0), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
.CLKIN(0), // 1-bit input: Clock delay input
.CNTVALUEIN(DELAY_VALUE), // 5-bit input: Counter value input
.INC(0), // 1-bit input: Increment / Decrement tap delay input
.LD(delay_update_v[i+NINPUT]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode,
// in VAR_LOAD or VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
.LDPIPEEN(0), // 1-bit input: Enables the pipeline register to load data
.ODATAIN(OUTPUTS_IN[i]), // 1-bit input: Output delay data input
.REGRST(0) // 1-bit input: Active-high reset tap-delay input
);
OBUFDS
#(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
obufds_inst
(
.O(OUTPUTS_P[i]), // Diff_p output (connect directly to top-level port)
.OB(OUTPUTS_N[i]), // Diff_n output (connect directly to top-level port)
.I(outputs_in_i[i]) // Buffer input
);
end
endgenerate
endmodule |
module axi_adcfifo_dma (
axi_clk,
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready,
axi_xfer_status,
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter DMA_DATA_WIDTH = 64;
parameter DMA_READY_ENABLE = 1;
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDR_WIDTH = 8;
localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
// adc write
input axi_clk;
input axi_drst;
input axi_dvalid;
input [AXI_DATA_WIDTH-1:0] axi_ddata;
output axi_dready;
input [ 3:0] axi_xfer_status;
// dma read
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// internal registers
reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0;
reg axi_dready = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_waddr <= 'd0;
axi_waddr_rel_count <= 'd0;
axi_waddr_rel_t <= 'd0;
axi_waddr_rel <= 'd0;
end else begin
if (axi_dvalid == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
if (axi_waddr_rel_count == 3'd7) begin
axi_waddr_rel_t <= ~axi_waddr_rel_t;
axi_waddr_rel <= axi_waddr;
end
end
end
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_raddr_rel_t_m <= 'd0;
axi_raddr_rel <= 'd0;
axi_addr_diff <= 'd0;
axi_dready <= 'd0;
end else begin
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
axi_dready <= 1'b1;
end
end
end
// read interface
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= axi_waddr_rel;
end
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
dma_raddr_rel_count <= 'd0;
dma_raddr_rel_t <= 'd0;
dma_raddr_rel <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
if (dma_raddr_rel_count == 3'd7) begin
dma_raddr_rel_t <= ~dma_raddr_rel_t;
dma_raddr_rel <= dma_raddr;
end
end
end
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (AXI_ADDR_WIDTH),
.DATA_WIDTH_A (AXI_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),
.addra (axi_waddr),
.dina (axi_ddata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~dma_rst),
.up_clk (dma_clk),
.up_data_status (dma_xfer_status),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule |
module dmac_dest_mm_axi (
input m_axi_aclk,
input m_axi_aresetn,
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [3:0] req_last_burst_length,
input [2:0] req_last_beat_bytes,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
output response_valid,
input response_ready,
output [1:0] response_resp,
output response_resp_eot,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
output [C_ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
input response_eot,
input fifo_valid,
output fifo_ready,
input [C_M_AXI_DATA_WIDTH-1:0] fifo_data,
// Write address
input m_axi_awready,
output m_axi_awvalid,
output [31:0] m_axi_awaddr,
output [ 7:0] m_axi_awlen,
output [ 2:0] m_axi_awsize,
output [ 1:0] m_axi_awburst,
output [ 2:0] m_axi_awprot,
output [ 3:0] m_axi_awcache,
// Write data
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
// Write response
input m_axi_bvalid,
input [ 1:0] m_axi_bresp,
output m_axi_bready
);
parameter C_ID_WIDTH = 3;
parameter C_M_AXI_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 24;
wire [C_ID_WIDTH-1:0] data_id;
wire [C_ID_WIDTH-1:0] address_id;
reg [(C_M_AXI_DATA_WIDTH/8)-1:0] wstrb;
wire address_req_valid;
wire address_req_ready;
wire data_req_valid;
wire data_req_ready;
wire address_enabled;
wire data_enabled;
assign sync_id_ret = sync_id;
splitter #(
.C_NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
);
dmac_address_generator #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_ID_WIDTH(C_ID_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.id(address_id),
.wait_id(request_id),
.sync_id(sync_id),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.eot(address_eot),
.addr_ready(m_axi_awready),
.addr_valid(m_axi_awvalid),
.addr(m_axi_awaddr),
.len(m_axi_awlen),
.size(m_axi_awsize),
.burst(m_axi_awburst),
.prot(m_axi_awprot),
.cache(m_axi_awcache)
);
wire _fifo_ready;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(address_enabled),
.enabled(data_enabled),
.request_id(address_id),
.response_id(data_id),
.sync_id(sync_id),
.eot(data_eot),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_valid(fifo_valid),
.s_axi_ready(_fifo_ready),
.s_axi_data(fifo_data),
.m_axi_valid(m_axi_wvalid),
.m_axi_ready(m_axi_wready),
.m_axi_data(m_axi_wdata),
.m_axi_last(m_axi_wlast)
);
assign fifo_ready = _fifo_ready | ~enabled;
always @(*)
begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= 8'b11111111;
end
end
assign m_axi_wstrb = wstrb;
dmac_response_handler #(
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_handler (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.bvalid(m_axi_bvalid),
.bready(m_axi_bready),
.bresp(m_axi_bresp),
.enable(data_enabled),
.enabled(enabled),
.id(response_id),
.wait_id(data_id),
.sync_id(sync_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_resp(response_resp),
.resp_eot(response_resp_eot)
);
endmodule |
module pcieCore_gt_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lane
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
(
//---------- GT User Ports -----------------------------
input GT_MASTER,
input GT_GEN3,
input GT_RX_CONVERGE,
//---------- GT Clock Ports ----------------------------
input GT_GTREFCLK0,
input GT_QPLLCLK,
input GT_QPLLREFCLK,
input GT_TXUSRCLK,
input GT_RXUSRCLK,
input GT_TXUSRCLK2,
input GT_RXUSRCLK2,
input GT_OOBCLK,
input [ 1:0] GT_TXSYSCLKSEL,
input [ 1:0] GT_RXSYSCLKSEL,
output GT_TXOUTCLK,
output GT_RXOUTCLK,
output GT_CPLLLOCK,
output GT_RXCDRLOCK,
//---------- GT Reset Ports ----------------------------
input GT_CPLLPD,
input GT_CPLLRESET,
input GT_TXUSERRDY,
input GT_RXUSERRDY,
input GT_RESETOVRD,
input GT_GTTXRESET,
input GT_GTRXRESET,
input GT_TXPMARESET,
input GT_RXPMARESET,
input GT_RXCDRRESET,
input GT_RXCDRFREQRESET,
input GT_RXDFELPMRESET,
input GT_EYESCANRESET,
input GT_TXPCSRESET,
input GT_RXPCSRESET,
input GT_RXBUFRESET,
output GT_TXRESETDONE,
output GT_RXRESETDONE,
output GT_RXPMARESETDONE,
//---------- GT TX Data Ports --------------------------
input [31:0] GT_TXDATA,
input [ 3:0] GT_TXDATAK,
output GT_TXP,
output GT_TXN,
//---------- GT RX Data Ports --------------------------
input GT_RXN,
input GT_RXP,
output [31:0] GT_RXDATA,
output [ 3:0] GT_RXDATAK,
//---------- GT Command Ports --------------------------
input GT_TXDETECTRX,
input GT_TXELECIDLE,
input GT_TXCOMPLIANCE,
input GT_RXPOLARITY,
input [ 1:0] GT_TXPOWERDOWN,
input [ 1:0] GT_RXPOWERDOWN,
input [ 2:0] GT_TXRATE,
input [ 2:0] GT_RXRATE,
//---------- GT Electrical Command Ports ---------------
input [ 2:0] GT_TXMARGIN,
input GT_TXSWING,
input GT_TXDEEMPH,
input [ 4:0] GT_TXPRECURSOR,
input [ 6:0] GT_TXMAINCURSOR,
input [ 4:0] GT_TXPOSTCURSOR,
//---------- GT Status Ports ---------------------------
output GT_RXVALID,
output GT_PHYSTATUS,
output GT_RXELECIDLE,
output [ 2:0] GT_RXSTATUS,
output [ 2:0] GT_RXBUFSTATUS,
output GT_TXRATEDONE,
output GT_RXRATEDONE,
//---------- GT DRP Ports ------------------------------
input GT_DRPCLK,
input [ 8:0] GT_DRPADDR,
input GT_DRPEN,
input [15:0] GT_DRPDI,
input GT_DRPWE,
output [15:0] GT_DRPDO,
output GT_DRPRDY,
//---------- GT TX Sync Ports --------------------------
input GT_TXPHALIGN,
input GT_TXPHALIGNEN,
input GT_TXPHINIT,
input GT_TXDLYBYPASS,
input GT_TXDLYSRESET,
input GT_TXDLYEN,
output GT_TXDLYSRESETDONE,
output GT_TXPHINITDONE,
output GT_TXPHALIGNDONE,
input GT_TXPHDLYRESET,
input GT_TXSYNCMODE, // GTH
input GT_TXSYNCIN, // GTH
input GT_TXSYNCALLIN, // GTH
output GT_TXSYNCOUT, // GTH
output GT_TXSYNCDONE, // GTH
//---------- GT RX Sync Ports --------------------------
input GT_RXPHALIGN,
input GT_RXPHALIGNEN,
input GT_RXDLYBYPASS,
input GT_RXDLYSRESET,
input GT_RXDLYEN,
input GT_RXDDIEN,
output GT_RXDLYSRESETDONE,
output GT_RXPHALIGNDONE,
input GT_RXSYNCMODE, // GTH
input GT_RXSYNCIN, // GTH
input GT_RXSYNCALLIN, // GTH
output GT_RXSYNCOUT, // GTH
output GT_RXSYNCDONE, // GTH
//---------- GT Comma Alignment Ports ------------------
input GT_RXSLIDE,
output GT_RXCOMMADET,
output [ 3:0] GT_RXCHARISCOMMA,
output GT_RXBYTEISALIGNED,
output GT_RXBYTEREALIGN,
//---------- GT Channel Bonding Ports ------------------
input GT_RXCHBONDEN,
input [ 4:0] GT_RXCHBONDI,
input [ 2:0] GT_RXCHBONDLEVEL,
input GT_RXCHBONDMASTER,
input GT_RXCHBONDSLAVE,
output GT_RXCHANISALIGNED,
output [ 4:0] GT_RXCHBONDO,
//---------- GT PRBS/Loopback Ports --------------------
input [ 2:0] GT_TXPRBSSEL,
input [ 2:0] GT_RXPRBSSEL,
input GT_TXPRBSFORCEERR,
input GT_RXPRBSCNTRESET,
input [ 2:0] GT_LOOPBACK,
output GT_RXPRBSERR,
//---------- GT Debug Ports ----------------------------
output [14:0] GT_DMONITOROUT
);
//---------- Internal Signals --------------------------
wire [ 2:0] txoutclksel;
wire [ 2:0] rxoutclksel;
wire [63:0] rxdata;
wire [ 7:0] rxdatak;
wire [ 7:0] rxchariscomma;
wire rxlpmen;
wire [14:0] dmonitorout;
wire dmonitorclk;
//---------- Select CPLL and Clock Dividers ------------
localparam CPLL_REFCLK_DIV = 1;
localparam CPLL_FBDIV_45 = 5;
localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 :
(PCIE_REFCLK_FREQ == 1) ? 4 : 5;
localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2;
localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 :
(PCIE_REFCLK_FREQ == 1) ? 5 : 4;
//---------- Select IES vs. GES ------------------------
localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1;
//---------- Select GTP CPLL configuration -------------
// PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units
// PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000
// (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100
// (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100
// (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100
// (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100
// (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100
// (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000
//---------- Select GTX CPLL configuration -------------
// CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units
// CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (9/3=3) = 1010_0100_0000_0111_1100_1100
//------------------------------------------------------
localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC;
//---------- Select TX XCLK ----------------------------
// TXOUT for TX Buffer Use
// TXUSR for TX Buffer Bypass
//------------------------------------------------------
localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR";
//---------- Select TX Receiver Detection Configuration
localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 :
(PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100;
localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011;
//---------- Select PCS_RSVD_ATTR ----------------------
// [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer
// [1]: 1 = enable manual TX sync, 0 = enable auto TX sync
// [2]: 1 = enable manual RX sync, 0 = enable auto RX sync
// [3]: 1 = select external clock for OOB 0 = select reference clock for OOB
// [6]: 1 = enable DMON 0 = disable DMON
// [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle
// [8]: 1 = power up OOB 0 = power down OOB
//------------------------------------------------------
localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX
localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP
localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7};
//---------- Select RXCDR_CFG --------------------------
//---------- GTX Note ----------------------------------
// For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin
// Async 72'h03_8000_23FF_1040_0020
// Sync: 72'h03_0000_23FF_1040_0020
//------------------------------------------------------
localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ?
((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000
: 72'h11_07FE_4060_0104_0000): // IES setting
((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 //
: 72'h03_0000_23FF_1020_0020); // optimized for GES silicon
localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ?
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010
: 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018
: 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon
localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010
: 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon
//---------- Select TX and RX Sync Mode ----------------
localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
//---------- Select Clock Correction Min and Max Latency
// CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11)
// = 13 when PCIE_LANE = 1
// CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1
// = CLK_COR_MIN_LAT + 2
//------------------------------------------------------
//---------- CLK_COR_MIN_LAT Look-up Table -------------
// Lane | One-Hop | Daisy-Chain | Binary-Tree
//------------------------------------------------------
// 0 | 13 | 13 | 13
// 1 | 15 to 18 | 15 to 18 | 15 to 18
// 2 | 15 to 18 | 17 to 18 | 15 to 18
// 3 | 15 to 18 | 19 | 17 to 18
// 4 | 15 to 18 | 21 | 17 to 18
// 5 | 15 to 18 | 23 | 19
// 6 | 15 to 18 | 25 | 19
// 7 | 15 to 18 | 27 | 21
//------------------------------------------------------
localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) :
((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) :
((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) :
((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) :
((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) :
((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18;
localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2;
//---------- Simulation Speedup ------------------------
//localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK
//localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK
//---------- Select [TX/RX]OUTCLK ----------------------
assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0;
assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0;
//---------- Select DFE vs. LPM ------------------------
// Gen1/2 = Use LPM by default. Option to use DFE.
// Gen3 = Use DFE by default. Option to use LPM.
//------------------------------------------------------
assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0);
//---------- Generate DMONITOR Clock Buffer for Debug ------
generate if (PCIE_DEBUG_MODE == 1)
begin : dmonitorclk_i
//---------- DMONITOR CLK ------------------------------
BUFG dmonitorclk_i
(
//---------- Input ---------------------------------
.I (dmonitorout[7]),
//---------- Output --------------------------------
.O (dmonitorclk)
);
end
else
begin : dmonitorclk_i_disable
assign dmonitorclk = 1'd0;
end
endgenerate
//---------- Select GTX or GTH or GTP ------------------------------------------
// Notes : Attributes that are commented out always use the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTP")
begin : gtp_channel
//---------- GTP Channel Module --------------------------------------------
GTPE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
//.TX_CLKMUX_EN ( 1'b1), // GTP rename
//.RX_CLKMUX_EN ( 1'b1), // GTP rename
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
//.OUTREFCLK_SEL_INV ( 2'b11), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME ( 5'b00001), //
.RXPCSRESET_TIME ( 5'b00001), //
.TXPMARESET_TIME ( 5'b00011), //
.RXPMARESET_TIME ( 5'b00011), // Optimized for sim
//.RXISCANRESET_TIME ( 5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim
.TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTP
//---------- Status Attributes -----------------------------------------
//.RX_SIG_VALID_DLY ( 4), // CHECK
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up
//---------- PMA Attributes -------------------------------------------
//.CLK_COMMON_SWING ( 1'b0), // GTP new
//.PMA_RSV (32'd0), //
.PMA_RSV2 (32'h00002040), // Optimized for GES
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits
//.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit
//.PMA_RSV6 ( 1'd0), // GTP new
//.PMA_RSV7 ( 1'd0), // GTP new
.RX_BIAS_CFG (16'h0F33), // Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Optimized for IES
//---------- TX PI ----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), //
//.TXPI_CFG1 ( 2'd0), //
//.TXPI_CFG2 ( 2'd0), //
//.TXPI_CFG3 ( 1'd0), //
//.TXPI_CFG4 ( 1'd0), //
//.TXPI_CFG5 ( 3'd000), //
//.TXPI_GREY_SEL ( 1'd0), //
//.TXPI_INVSTROBE_SEL ( 1'd0), //
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), //
//.TXPI_PPM_CFG ( 8'd0), //
//.TXPI_SYNFREQ_PPM ( 3'd0), //
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES
.RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
.RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
//---------- CDR Attributes ---------------------------------------------
//.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK
.RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
//.RXLPMRESET_TIME ( 7'b0001111), // GTP new
//.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new
.RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES
//.RXLPM_CFG1 ( 1'b0), // GTP new
//.RXLPM_CM_CFG ( 1'b0), // GTP new
.RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES
.RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES
//.RXLPM_HF_CFG (14'b00001111110000), //
.RXLPM_HF_CFG2 ( 5'b01010), // GTP new
//.RXLPM_HF_CFG3 ( 4'b0000), // GTP new
.RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new
.RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES
.RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES
//.RXLPM_LF_CFG (18'b000000001111110000), //
.RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES
.RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // CHECK
.RXOSCALRESET_TIME (5'b00011), // Optimized for IES
.RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'b0), //
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), //
//.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
.TXDLY_CFG (16'h001F), //
.TXDLY_LCFG ( 9'h030), //
.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), //
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), //
.TXSYNC_SKIP_DA (1'b0), //
//---------- RX Sync Attributes ----------------------------------------
.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
.RXDLY_CFG (16'h001F), //
.RXDLY_LCFG ( 9'h030), //
.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), //
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), //
.RXSYNC_SKIP_DA (1'b0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE (4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE ( 3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes ---------------------------------
.LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes --------------------------------------
.TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_PLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), //
.RX_DEBUG_CFG (14'h0000), // Optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
//---------- GTP -------------------------------------------------------
//.ACJTAG_DEBUG_MODE (1'd0), //
//.ACJTAG_MODE (1'd0), //
//.ACJTAG_RESET (1'd0), //
//.ADAPT_CFG0 (20'd0), //
.CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES
.CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES
.CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES
.CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES
)
gtpe2_channel_i
(
//---------- Clock -----------------------------------------------------
.PLL0CLK (GT_QPLLCLK), //
.PLL1CLK (1'd0), //
.PLL0REFCLK (GT_QPLLREFCLK), //
.PLL1REFCLK (1'd0), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CLKRSVD0 (1'd0), //
.CLKRSVD1 (1'd0), //
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
//---------- Reset -----------------------------------------------------
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA (GT_TXDATA), //
.TXCHARISK (GT_TXDATAK), //
.GTPTXP (GT_TXP), // GTP
.GTPTXN (GT_TXN), // GTP
//---------- RX Data ---------------------------------------------------
.GTPRXP (GT_RXP), // GTP
.GTPRXN (GT_RXN), // GTP
.RXDATA (rxdata[31:0]), //
.RXCHARISK (rxdatak[3:0]), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits
.TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'b0), //
.RXRATEMODE (1'b0), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMRESET ( 1'd0), // GTP new
.RXLPMOSINTNTRLEN ( 1'd0), // GTP new
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFOVRDEN ( 1'd0), //
.PMARSVDIN0 ( 1'd0), // GTP new
.PMARSVDIN1 ( 1'd0), // GTP new
.PMARSVDIN2 ( 1'd0), // GTP new
.PMARSVDIN3 ( 1'd0), // GTP new
.PMARSVDIN4 ( 1'd0), // GTP new
.GTRSVD (16'd0), //
.PMARSVDOUT0 (), // GTP new
.PMARSVDOUT1 (), // GTP new
.DMONITOROUT (dmonitorout), // GTP 15-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), //
.TXPIPPMOVRDEN (1'd0), //
.TXPIPPMPD (1'd0), //
.TXPIPPMSEL (1'd0), //
.TXPIPPMSTEPSIZE (5'd0), //
.TXPISOPD (1'd0), // GTP new
//---------- DFE -------------------------------------------------------
.RXDFEXYDEN (1'd0), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // Optimized for IES
.RXOSOVRDEN (1'd0), // Optimized for IES
.RXOSINTEN (1'd1), // Optimized for IES
.RXOSINTHOLD (1'd0), // Optimized for IES
.RXOSINTNTRLEN (1'd0), // Optimized for IES
.RXOSINTOVRDEN (1'd0), // Optimized for IES
.RXOSINTPD (1'd0), // GTP new, Optimized for IES
.RXOSINTSTROBE (1'd0), // Optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // Optimized for IES
.RXOSINTCFG (4'b0010), // Optimized for IES
.RXOSINTID0 (4'd0), // Optimized for IES
.RXOSINTDONE (), //
.RXOSINTSTARTED (), //
.RXOSINTSTROBEDONE (), //
.RXOSINTSTROBESTARTED (), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), //
.TXSYNCIN (GT_TXSYNCIN), //
.TXSYNCALLIN (GT_TXSYNCALLIN), //
.TXSYNCDONE (GT_TXSYNCDONE), //
.TXSYNCOUT (GT_TXSYNCOUT), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), //
.RXSYNCIN (GT_RXSYNCIN), //
.RXSYNCALLIN (GT_RXSYNCALLIN), //
.RXSYNCDONE (GT_RXSYNCDONE), //
.RXSYNCOUT (GT_RXSYNCOUT), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN (1'd1), //
.RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXSLIDE (GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma[3:0]), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI[3:0]), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO[3:0]), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (4'd0), //
.TX8B10BEN (1'b1), // No Gen3 support in GTP
.RX8B10BEN (1'b1), // No Gen3 support in GTP
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // Optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTP -------------------------------------------------------
.RXADAPTSELTEST (14'd0), //
.DMONFIFORESET ( 1'd0), //
.DMONITORCLK (dmonitorclk), //
.RXOSCALRESET ( 1'd0), //
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTP
.TXPMARESETDONE () //
);
assign GT_CPLLLOCK = 1'b0;
end
else if (PCIE_GT_DEVICE == "GTH")
begin : gth_channel
//---------- GTH Channel Module --------------------------------------------
GTHE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION ("2.0"), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD ( 1'b1), // GTH
.RX_CLKMUX_PD ( 1'b1), // GTH
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW
.CPLL_INIT_CFG (24'h00001E), // Optimized for IES
.CPLL_LOCK_CFG (16'h01E8), // Optimized for IES
//.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits
.TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00000080), // Optimized for IES
.PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES
//.PMA_RSV3 ( 2'h0), //
.PMA_RSV4 (15'h0008), // GTH new, Optimized for IES
//.PMA_RSV5 ( 4'h00), // GTH new
.RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES
//---------- TX PI -----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), // GTH new
//.TXPI_CFG1 ( 2'd0), // GTH new
//.TXPI_CFG2 ( 2'd0), // GTH new
//.TXPI_CFG3 ( 1'd0), // GTH new
//.TXPI_CFG4 ( 1'd0), // GTH new
//.TXPI_CFG5 ( 3'b100), // GTH new
//.TXPI_GREY_SEL ( 1'd0), // GTH new
//.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new
//.TXPI_PPM_CFG ( 8'd0), // GTH new
//.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 (2'b00), // GTH new
.RXPI_CFG1 (2'b11), // GTH new
.RXPI_CFG2 (2'b11), // GTH new
.RXPI_CFG3 (2'b11), // GTH new
.RXPI_CFG4 (1'b0), // GTH new
.RXPI_CFG5 (1'b0), // GTH new
.RXPI_CFG6 (3'b100), // GTH new
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTH), //
//.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1)
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES
//.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h0200), // Optimized for IES
.RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES
//---------- DFE Attributes --------------------------------------------
.RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES
.RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES
.RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE
.RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES
.RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES
.RX_DFE_H2_CFG (12'h000), // Optimized for IES
.RX_DFE_H3_CFG (12'h040), // Optimized for IES
.RX_DFE_H4_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H5_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES
.RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES
.RX_DFE_LPM_CFG (16'h0080), // Optimized for IES
.RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES
.RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES
.RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode
.RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES
.RX_DFE_UT_CFG (17'h03800), // Optimized for IES
.RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // Optimized for IES
.A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES
.RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES
.RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'd0), // GTH new
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), // Optimized for IES
.ES_HORZ_OFFSET (12'h000), // Optimized for IES
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), // GTH new
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new
.TXSYNC_SKIP_DA (1'b0), // GTH new
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), // GTH new
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new
.RXSYNC_SKIP_DA (1'b0), // GTH new
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
.TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC
//.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM
.RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0), //
//---------- GTH -------------------------------------------------------
//.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new
//.ACJTAG_MODE ( 1'd0), // GTH new
//.ACJTAG_RESET ( 1'd0), // GTH new
.ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES
.CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK
.CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES
.CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES
)
gthe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD0 (1'd0), // GTH
.CLKRSVD1 (1'd0), // GTH
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (GT_CPLLPD), //
.CPLLRESET (GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTHTXP (GT_TXP), // GTH
.GTHTXN (GT_TXN), // GTH
//---------- RX Data ---------------------------------------------------
.GTHRXP (GT_RXP), // GTH
.GTHRXN (GT_RXN), // GTH
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'd0), // GTH
.RXRATEMODE (1'd0), // GTH
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1111), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), // ***
.RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), // Optimized for IES
.PMARSVDIN ( 5'd0), //
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout), // GTH 15-bits.
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), // GTH new
.TXPIPPMOVRDEN (1'd0), // GTH new
.TXPIPPMPD (1'd0), // GTH new
.TXPIPPMSEL (1'd0), // GTH new
.TXPIPPMSTEPSIZE (5'd0), // GTH new
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFETAP6HOLD (1'd0), // GTH new
.RXDFETAP6OVRDEN (1'd0), // GTH new
.RXDFETAP7HOLD (1'd0), // GTH new
.RXDFETAP7OVRDEN (1'd0), // GTH new
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFEAGCOVRDEN (rxlpmen), //
.RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFELFOVRDEN (1'd0), //
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd1), // Optimized for IES
.RXMONITORSEL (2'd0), //
.RXDFESLIDETAP (5'd0), // GTH new
.RXDFESLIDETAPID (6'd0), // GTH new
.RXDFESLIDETAPHOLD (1'd0), // GTH new
.RXDFESLIDETAPOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPSTROBE (1'd0), // GTH new
.RXMONITOROUT (), //
.RXDFESLIDETAPSTARTED (), // GTH new
.RXDFESLIDETAPSTROBEDONE (), // GTH new
.RXDFESLIDETAPSTROBESTARTED (), // GTH new
.RXDFESTADAPTDONE (), // GTH new
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // optimized for IES
.RXOSOVRDEN (1'd0), // optimized for IES
.RXOSINTEN (1'd1), // GTH new, optimized for IES
.RXOSINTHOLD (1'd0), // GTH new, optimized for IES
.RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES
.RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTSTROBE (1'd0), // GTH new, optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTCFG (4'b0110), // GTH new, optimized for IES
.RXOSINTID0 (4'b0000), // GTH new, optimized for IES
.RXOSCALRESET ( 1'd0), // GTH, optimized for IES
.RSOSINTDONE (), // GTH new
.RXOSINTSTARTED (), // GTH new
.RXOSINTSTROBEDONE (), // GTH new
.RXOSINTSTROBESTARTED (), // GTH new
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), // GTH
.TXSYNCIN (GT_TXSYNCIN), // GTH
.TXSYNCALLIN (GT_TXSYNCALLIN), // GTH
.TXSYNCDONE (GT_TXSYNCDONE), // GTH
.TXSYNCOUT (GT_TXSYNCOUT), // GTH
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), // GTH
.RXSYNCIN (GT_RXSYNCIN), // GTH
.RXSYNCALLIN (GT_RXSYNCALLIN), // GTH
.RXSYNCDONE (GT_RXSYNCDONE), // GTH
.RXSYNCOUT (GT_RXSYNCOUT), // GTH
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS & Loopback -------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTH -------------------------------------------------------
.RXADAPTSELTEST (14'd0), // GTH new
.DMONFIFORESET ( 1'd0), // GTH
.DMONITORCLK (dmonitorclk), // GTH, optimized for debug
//.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTH
.TXPMARESETDONE () // GTH
);
end
else
begin : gtx_channel
//---------- GTX Channel Module --------------------------------------------
GTXE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD (CLKMUX_PD), // GTX
.RX_CLKMUX_PD (CLKMUX_PD), // GTX
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (CPLL_CFG), // Optimized for silicon
//.CPLL_INIT_CFG (24'h00001E), //
//.CPLL_LOCK_CFG (16'h01E8), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF (TX_RXDETECT_REF), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 3'b010), // Select 800mV
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTX
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (PCS_RSVD_ATTR), //
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2
.PMA_RSV2 (16'h2070), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 (32'd0), // GTX 3.0 new
.RX_BIAS_CFG (12'b000000000100), // Optimized for GES
//.TERM_RCAL_CFG ( 5'b10000), //
//.TERM_RCAL_OVRD ( 1'd0), //
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTX), //
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h00F0), // Optimized for silicon
.RXLPM_LF_CFG (14'h00F0), // Optimized for silicon
//---------- DFE Attributes --------------------------------------------
//.RXDFELPMRESET_TIME ( 7'b0001111), //
.RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A
.RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES
.RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES
.RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES
.RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES
.RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES
.RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C
.RX_DFE_LPM_CFG (16'h0954), // Optimized for GES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe
.RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00
.RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES
.RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'b0000010000000), // Optimized for GES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), //
.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), //
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // Optimized for sim
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.RXPRBS_ERR_LOOPBACK (1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
//.RXOOB_CFG ( 7'b0000110), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), // Optimized for debug
.RX_DEBUG_CFG (12'd0) // Optimized for GES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
)
gtxe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (GT_CPLLPD), //
.CPLLRESET (GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTXTXP (GT_TXP), // GTX
.GTXTXN (GT_TXN), // GTX
//---------- RX Data ---------------------------------------------------
.GTXRXP (GT_RXP), // GTX
.GTXRXN (GT_RXN), // GTX
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), //
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), //
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), //
.PMARSVDIN ( 5'd0), //
.PMARSVDIN2 ( 5'd0), // GTX
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence
.RXDFEAGCOVRDEN (1'd0), //
.RXDFELFHOLD (1'd0), //
.RXDFELFOVRDEN (1'd1), // Optimized for GES
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd0), //
.RXDFEXYDHOLD (1'd0), // GTX
.RXDFEXYDOVRDEN (1'd0), // GTX
.RXMONITORSEL (2'd0), //
.RXMONITOROUT (), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), //
.RXOSOVRDEN (1'd0), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (1'd0), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
.TSTOUT () // GTX
);
//---------- Default -------------------------------------------------------
assign dmonitorout[14:8] = 7'd0; // GTH GTP
assign GT_TXSYNCOUT = 1'd0; // GTH GTP
assign GT_TXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXSYNCOUT = 1'd0; // GTH GTP
assign GT_RXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXPMARESETDONE = 1'd0; // GTH GTP
end
endgenerate
//---------- GT Wrapper Outputs ------------------------------------------------
assign GT_RXDATA = rxdata [31:0];
assign GT_RXDATAK = rxdatak[ 3:0];
assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0];
assign GT_DMONITOROUT = dmonitorout;
endmodule |
module master #(
parameter id = 0,
parameter nreads = 128,
parameter nwrites = 128,
parameter p = 4
) (
input sys_clk,
input sys_rst,
output reg [31:0] dat_w,
input [31:0] dat_r,
output reg [31:0] adr,
output [2:0] cti,
output reg we,
output reg [3:0] sel,
output cyc,
output stb,
input ack,
output reg tend
);
integer rcounter;
integer wcounter;
reg active;
assign cyc = active;
assign stb = active;
assign cti = 0;
always @(posedge sys_clk) begin
if(sys_rst) begin
dat_w = 0;
adr = 0;
we = 0;
sel = 0;
active = 0;
rcounter = 0;
wcounter = 0;
tend = 0;
end else begin
if(ack) begin
if(~active)
$display("[M%d] Spurious ack", id);
else begin
if(we)
$display("[M%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
else
$display("[M%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
end
active = 1'b0;
end else if(~active) begin
if(($random % p) == 0) begin
adr = $random;
adr = adr % 5;
adr = (adr << (32-3)) + id;
sel = sel + 1;
active = 1'b1;
if(($random % 2) == 0) begin
/* Read */
we = 1'b0;
rcounter = rcounter + 1;
end else begin
/* Write */
we = 1'b1;
dat_w = ($random << 16) + id;
wcounter = wcounter + 1;
end
end
end
tend = (rcounter >= nreads) && (wcounter >= nwrites);
end
end
endmodule |
module rotate
#(
parameter C_DIRECTION = "LEFT",
parameter C_WIDTH = 4
)
(
input [C_WIDTH-1:0] WR_DATA,
input [clog2s(C_WIDTH)-1:0] WR_SHIFTAMT,
output [C_WIDTH-1:0] RD_DATA
);
`include "functions.vh"
wire [2*C_WIDTH-1:0] wPreShiftR;
wire [2*C_WIDTH-1:0] wPreShiftL;
wire [2*C_WIDTH-1:0] wShiftR;
wire [2*C_WIDTH-1:0] wShiftL;
assign wPreShiftL = {WR_DATA,WR_DATA};
assign wPreShiftR = {WR_DATA,WR_DATA};
assign wShiftL = wPreShiftL << WR_SHIFTAMT;
assign wShiftR = wPreShiftR >> WR_SHIFTAMT;
generate
if(C_DIRECTION == "LEFT") begin
assign RD_DATA = wShiftL[2*C_WIDTH-1:C_WIDTH];
end else if (C_DIRECTION == "RIGHT") begin
assign RD_DATA = wShiftR[C_WIDTH-1:0];
end
endgenerate
endmodule |
module sky130_fd_sc_hs__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module MAX6682(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, MAX6682CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$773.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$768.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$768.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$extract$\Counter32_RV1_Timer$768.Overflow_s ;
(* src = "../../verilog/max6682.v:323" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682.v:184" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682.v:185" *)
wire [7:0] Byte1;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/max6682.v:137" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/max6682.v:141" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/max6682.v:139" *)
input Enable_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/max6682.v:143" *)
output MAX6682CS_n_o;
(* src = "../../verilog/max6682.v:9" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Done ;
(* src = "../../verilog/max6682.v:4" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Start ;
(* src = "../../verilog/max6682.v:24" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/max6682.v:23" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/max6682.v:159" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/max6682.v:161" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/max6682.v:135" *)
input Reset_n_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/max6682.v:169" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/max6682.v:167" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/max6682.v:145" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/max6682.v:151" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/max6682.v:155" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/max6682.v:153" *)
input SPI_FIFOFull_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/max6682.v:171" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/max6682.v:149" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/max6682.v:157" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/max6682.v:147" *)
output SPI_Write_o;
(* src = "../../verilog/max6682.v:216" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682.v:214" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682.v:212" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682.v:213" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682.v:321" *)
wire [15:0] SensorValue;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/max6682.v:163" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/max6682.v:165" *)
input [15:0] Threshold_i;
AbsDiff \$extract$\AbsDiff$769 (
.A_i(SensorValue),
.B_i(SensorValue_o),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$773.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$773.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$773.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$773.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$773.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$773.Zero_s )
);
(* src = "../../../../byte2wordsel/verilog/byte2wordsel_11msb.v:10" *)
Byte2WordSel \$extract$\Byte2WordSel_11MSB_Direct$781.DUT (
.H_i(Byte1),
.L_i(Byte0),
.Mask_i(4'b1011),
.Shift_i(4'b0101),
.Y_o(SensorValue)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$extract$\Counter32_RV1_Timer$768.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$extract$\Counter32_RV1_Timer$768.DH_s ),
.DL_o(\$extract$\Counter32_RV1_Timer$768.DL_s ),
.Direction_i(1'b1),
.Enable_i(SensorFSM_TimerEnable),
.Overflow_o(\$extract$\Counter32_RV1_Timer$768.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(SensorFSM_TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(SensorFSM_TimerOvfl)
);
WordRegister \$extract$\WordRegister$770 (
.Clk_i(Clk_i),
.D_i(SensorValue),
.Enable_i(SensorFSM_StoreNewValue),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:210" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000101),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000101),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000010),
.STATE_NUM(32'b00000000000000000000000000000100),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(8'b11011000),
.TRANS_NUM(32'b00000000000000000000000000001010),
.TRANS_TABLE(160'b011zzzzz01011000010zz0z101000100010zz1z100100101010zzzz00000010000101z1z011001100011zz1z0100100000100z1z01001000001zzz0z00101000000zzzz101000100000zzzz000001000)
) \$fsm$\SensorFSM_State$738 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ \$extract$\AddSubCmp_Greater_Direct$773.Zero_s , \$extract$\AddSubCmp_Greater_Direct$773.Carry_s , SensorFSM_TimerOvfl, \MAX6682_SPI_FSM_1.SPI_FSM_Done , Enable_i }),
.CTRL_OUT({ CpuIntr_o, SensorFSM_TimerPreset, SensorFSM_TimerEnable, SensorFSM_StoreNewValue, \MAX6682_SPI_FSM_1.SPI_FSM_Start })
);
ByteRegister \$techmap\MAX6682_SPI_FSM_1.$extract$\ByteRegister$771 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ),
.Q_o(Byte0),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\MAX6682_SPI_FSM_1.$extract$\ByteRegister$772 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ),
.Q_o(Byte1),
.Reset_n_i(Reset_n_i)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:21" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000010),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000110),
.NAME("\\SPI_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000111),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(21'b011101001110010100000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(126'b1101z1100000001100z001001100101zz011010010100zz010100000011zz000010010010zz110000000001zz101001001000z1100100000000z0000010000)
) \$techmap\MAX6682_SPI_FSM_1.$fsm$\SPI_FSM_State$743 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SPI_Transmission_i, \MAX6682_SPI_FSM_1.SPI_FSM_Start }),
.CTRL_OUT({ SPI_Write_o, MAX6682CS_n_o, SPI_ReadNext_o, \MAX6682_SPI_FSM_1.SPI_FSM_Wr1 , \MAX6682_SPI_FSM_1.SPI_FSM_Done , \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 })
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
endmodule |
module.
* The flag input is used to preserve/force flags to
* a specific state.
*/
task clear ( input [31:0] flags );
begin
o_dav_ff <= 0;
flags_ff <= flags;
o_abt_ff <= 0;
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_swi_ff <= 0;
o_und_ff <= 0;
sleep_ff <= 0;
o_mem_load_ff <= 0;
o_mem_store_ff <= 0;
end
endtask
/*
* The reason we use the duplicate function is to copy value over the memory
* bus for memory stores. If we have a byte write to address 1, then the
* memory controller basically takes address 0 and byte enable 0010 and writes
* to address 1. This enables implementation of a 32-bit memory controller
* with byte enables to control updates as is commonly done. Basically this
* is to faciliate byte and halfword based writes on a 32-bit aligned memory
* bus using byte enables. The rules are simple:
* For a byte access - duplicate the lower byte of the register 4 times.
* For halfword access - duplicate the lower 16-bit of the register twice.
*/
function [31:0] duplicate ( input ub, // Unsigned byte.
input sb, // Signed byte.
input uh, // Unsigned halfword.
input sh, // Signed halfword.
input [31:0] val );
reg [31:0] x;
begin
if ( ub || sb)
begin
// Byte.
x = {val[7:0], val[7:0], val[7:0], val[7:0]};
end
else if (uh || sh)
begin
// Halfword.
x = {val[15:0], val[15:0]};
end
else
begin
x = val;
end
duplicate = x;
end
endfunction
/*
* Generate byte enables based on access mode.
* This function is similar in spirit to the previous one. The
* byte enables are generated in such a way that along with
* duplicate - byte and halfword accesses are possible.
* Rules -
* For a byte access, generate a byte enable with a 1 at the
* position that the lower 2-bits read (0,1,2,3).
* For a halfword access, based on lower 2-bits, if it is 00,
* make no change to byte enable (0011) else if it is 10, then
* make byte enable as (1100) which is basically the 32-bit
* address + 2 (and 3) which will be written.
*/
function [3:0] generate_ben ( input ub, // Unsigned byte.
input sb, // Signed byte.
input uh, // Unsigned halfword.
input sh, // Signed halfword.
input [31:0] addr );
reg [3:0] x;
begin
if ( ub || sb ) // Byte oriented.
begin
case ( addr[1:0] ) // Based on address lower 2-bits.
0: x = 1;
1: x = 1 << 1;
2: x = 1 << 2;
3: x = 1 << 3;
endcase
end
else if ( uh || sh ) // Halfword. A word = 2 half words.
begin
case ( addr[1] )
0: x = 4'b0011;
1: x = 4'b1100;
endcase
end
else
begin
x = 4'b1111; // Word oriented.
end
generate_ben = x;
end
endfunction // generate_ben
task reset;
begin
o_alu_result_ff <= 0;
o_dav_ff <= 0;
o_pc_plus_8_ff <= 0;
o_destination_index_ff <= 0;
flags_ff <= 0;
o_abt_ff <= 0;
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_swi_ff <= 0;
o_mem_srcdest_index_ff <= 0;
o_mem_srcdest_index_ff <= 0;
o_mem_load_ff <= 0;
o_mem_store_ff <= 0;
o_mem_unsigned_byte_enable_ff <= 0;
o_mem_signed_byte_enable_ff <= 0;
o_mem_signed_halfword_enable_ff <= 0;
o_mem_unsigned_halfword_enable_ff<= 0;
o_mem_translate_ff <= 0;
o_mem_srcdest_value_ff <= 0;
o_ben_ff <= 0;
o_decompile <= 0;
end
endtask
endmodule |
module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module tb_cmsdk_mcu;
`include "tb_defines.v"
parameter ROM_ADDRESS_SIZE = 16;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
wire NRST; // active low reset
wire [15:0] P0; // Port 0
wire [15:0] P1; // Port 1
//Debug tester signals
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire TDO;
wire PCLK; // Clock for UART capture device
wire [5:0] debug_command; // used to drive debug tester
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
parameter BE = 0; // Big or little endian
parameter BKPT = 4; // Number of breakpoint comparators
parameter DBG = 1; // Debug configuration
parameter NUMIRQ = 32; // NUM of IRQ
parameter SMUL = 0; // Multiplier configuration
parameter SYST = 1; // SysTick
parameter WIC = 1; // Wake-up interrupt controller support
parameter WICLINES = 34; // Supported WIC lines
parameter WPT = 2; // Number of DWT comparators
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
cmsdk_mcu
#(.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT) // Number of DWT comparators
)
u_cmsdk_mcu (
.XTAL1 (XTAL1), // input
.XTAL2 (XTAL2), // output
.NRST (NRST), // active low reset
.P0 (P0),
.P1 (P1),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (TDI), // Not needed if serial-wire debug is used
.TDO (TDO), // Not needed if serial-wire debug is used
.SWDIOTMS (SWDIOTMS),
.SWCLKTCK (SWCLKTCK)
);
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
cmsdk_clkreset u_cmsdk_clkreset(
.CLK (XTAL1),
.NRST (NRST)
);
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
assign PCLK = XTAL2;
cmsdk_uart_capture u_cmsdk_uart_capture(
.RESETn (NRST),
.CLK (PCLK),
.RXD (P1[5]), // UART 2 use for StdOut
.DEBUG_TESTER_ENABLE (debug_test_en),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
// UART connection cross over for UART test
assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
// --------------------------------------------------------------------------------
// Debug tester connection -
// --------------------------------------------------------------------------------
// No debug connection for Cortex-M0 DesignStart
assign nTRST = NRST;
assign TDI = 1'b1;
assign SWDIOTMS = 1'b1;
assign SWCLKTCK = 1'b1;
bufif1 (P0[31-16], debug_running, debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
pullup (debug_running);
pullup (debug_err);
// --------------------------------------------------------------------------------
// Misc
// --------------------------------------------------------------------------------
`ifndef SDF_SIM
task load_program_memory;
reg [1024:0] filename;
reg [7:0] memory [1<<ROM_ADDRESS_SIZE:0]; // byte type memory
integer i;
reg [31:0] tmp;
integer dummy;
begin
filename = 0;
dummy = $value$plusargs("program_memory=%s", filename);
if(filename ==0) begin
$display("WARNING! No content specified for program memory");
end
else begin
$display("-I- Loading <%s>",filename);
$readmemh (filename, memory);
for(i=0; i<((1<<ROM_ADDRESS_SIZE)/4); i=i+1) begin
tmp[7:0] = memory[i*4+0];
tmp[15:8] = memory[i*4+1];
tmp[23:16] = memory[i*4+2];
tmp[31:24] = memory[i*4+3];
u_cmsdk_mcu.u_ahb_rom.U_RAM.RAM[i] = tmp;
end
end
end
endtask // load_program_memory
`endif
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
`ifdef IVERILOG
initial begin
load_program_memory;
$dumpfile("tb_cmsdk_mcu.vcd");
$dumpvars(0,tb_cmsdk_mcu);
end
`endif
always@(posedge `hclk) begin
if(`pc === (32'h00000100 + 4)) begin
$write("%t -I- Test Ended - Return value : %d \n",$time,`r0);
$finish(`r0);
end
end
endmodule |
module triangle_intersect_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(0),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(32'H00000000),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(3'H0),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awvalid(1'H0),
.s_axi_awready(),
.s_axi_wdata(32'H00000000),
.s_axi_wstrb(4'HF),
.s_axi_wlast(1'H1),
.s_axi_wvalid(1'H0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'H0),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awvalid(),
.m_axi_awready(1'H0),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'H0),
.m_axi_bresp(2'H0),
.m_axi_bvalid(1'H0),
.m_axi_bready(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module rcn_fifo
(
input rst,
input clk,
input [68:0] rcn_in,
input push,
output full,
output [68:0] rcn_out,
input pop,
output empty
);
parameter DEPTH = 4; // max 32
reg [4:0] head;
reg [4:0] tail;
reg [5:0] cnt;
wire fifo_full = (cnt == DEPTH);
wire fifo_empty = (cnt == 0);
always @ (posedge clk or posedge rst)
if (rst)
begin
head <= 5'd0;
tail <= 5'd0;
cnt <= 6'd0;
end
else
begin
if (push)
head <= (head == (DEPTH - 1)) ? 5'd0 : head + 5'd1;
if (pop)
tail <= (tail == (DEPTH - 1)) ? 5'd0 : tail + 5'd1;
case ({push, pop})
2'b10: cnt <= cnt + 6'd1;
2'b01: cnt <= cnt - 6'd1;
default: ;
endcase
end
reg [67:0] fifo[(DEPTH - 1):0];
always @ (posedge clk)
if (push)
fifo[head] <= rcn_in[67:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign rcn_out = {!fifo_empty, fifo[tail]};
endmodule |
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
// Status and control signals
.locked(locked)
);
endmodule |
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module fb_rxstatem (MRxClk, Reset, MRxDV, MRxDEq5, MRxDEqDataSoC, MRxDEqNumbSoC, MRxDEqDistSoC, MRxDEqDelaySoC,MRxDEqDelayDistSoC,
DelayFrameEnd, DataFrameEnd, FrmCrcStateEnd, StateIdle, StateFFS, StatePreamble,
StateNumb, StateDist, StateDelay, StateData, StateFrmCrc
);
input MRxClk;
input Reset;
input MRxDV;
input MRxDEq5;
input MRxDEqDataSoC;
input MRxDEqNumbSoC;
input MRxDEqDistSoC;
input MRxDEqDelaySoC;
input MRxDEqDelayDistSoC;
input DelayFrameEnd;
input DataFrameEnd;
input FrmCrcStateEnd;
output StateIdle;
output StateFFS;
output StatePreamble;
output [1:0] StateNumb;
output [1:0] StateDist;
output [1:0] StateDelay;
output [1:0] StateData;
output StateFrmCrc;
reg StateIdle;
reg StateFFS;
reg StatePreamble;
reg [1:0] StateNumb;
reg [1:0] StateDist;
reg [1:0] StateDelay;
reg [1:0] StateData;
reg StateFrmCrc;
wire StartIdle;
wire StartFFS;
wire StartPreamble;
wire [1:0] StartNumb;
wire [1:0] StartDist;
wire [1:0] StartDelay;
wire [1:0] StartData;
wire StartFrmCrc;
// Defining the next state
assign StartIdle = ~MRxDV & ( StatePreamble | StateFFS | (|StateData) ) | StateFrmCrc & FrmCrcStateEnd;
assign StartFFS = MRxDV & ~MRxDEq5 & StateIdle;
assign StartPreamble = MRxDV & MRxDEq5 & (StateIdle | StateFFS);
assign StartNumb[0] = MRxDV & (StatePreamble & MRxDEqNumbSoC);
assign StartNumb[1] = MRxDV & StateNumb[0];
assign StartDist[0] = MRxDV & (StatePreamble & (MRxDEqDistSoC | MRxDEqDelayDistSoC ));
assign StartDist[1] = MRxDV & StateDist[0];
assign StartDelay[0] = MRxDV & (StatePreamble & MRxDEqDelaySoC | StateDelay[1] & ~DelayFrameEnd);
assign StartDelay[1] = MRxDV & StateDelay[0];
assign StartData[0] = MRxDV & (StatePreamble & MRxDEqDataSoC | (StateData[1] & ~DataFrameEnd));
assign StartData[1] = MRxDV & StateData[0] ;
assign StartFrmCrc = MRxDV & (StateNumb[1] | StateData[1] & DataFrameEnd | StateDist[1] | StateDelay[1] & DelayFrameEnd);
/*assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame);*/
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b1;
StatePreamble <= 1'b0;
StateFFS <= 1'b0;
StateNumb <= 2'b0;
StateDist <= 2'b0;
StateDelay <= 2'b0;
StateData <= 2'b0;
StateFrmCrc <= 1'b0;
end
else
begin
if(StartPreamble | StartFFS)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartPreamble | StartIdle)
StateFFS <= 1'b0;
else
if(StartFFS)
StateFFS <= 1'b1;
if(StartDelay[0] | StartDist[0] |StartNumb[0] | StartData[0] | StartIdle )
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartNumb[1])
StateNumb[0] <= 1'b0;
else
if(StartNumb[0])
StateNumb[0] <= 1'b1;
if(StartFrmCrc)
StateNumb[1] <= 1'b0;
else
if(StartNumb[1])
StateNumb[1] <= 1'b1;
//
if(StartDist[1])
StateDist[0] <= 1'b0;
else
if(StartDist[0])
StateDist[0] <= 1'b1;
if(StartFrmCrc)
StateDist[1] <= 1'b0;
else
if(StartDist[1])
StateDist[1] <= 1'b1;
if(StartDelay[1])
StateDelay[0] <= 1'b0;
else
if(StartDelay[0])
StateDelay[0] <= 1'b1;
if(StartFrmCrc | StartDelay[0])
StateDelay[1] <= 1'b0;
else
if(StartDelay[1])
StateDelay[1] <= 1'b1;
if(StartIdle | StartData[1])
StateData[0] <= 1'b0;
else
if(StartData[0])
StateData[0] <= 1'b1;
if(StartIdle | StartData[0] | StartFrmCrc)
StateData[1] <= 1'b0;
else
if(StartData[1])
StateData[1] <= 1'b1;
if(StartIdle)
StateFrmCrc <= 1'b0;
else
if(StartFrmCrc)
StateFrmCrc <= 1'b1;
end
end
endmodule |
module sky130_fd_sc_ms__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule |
module main
(
//////////////////// Clock Input ////////////////////
CLOCK_27, // On Board 27 MHz
CLOCK_50, // On Board 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
HEX4, // Seven Segment Digit 4
HEX5, // Seven Segment Digit 5
HEX6, // Seven Segment Digit 6
HEX7, // Seven Segment Digit 7
//////////////////////// LED ////////////////////////
LEDG, // LED Green[8:0]
LEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
//////////////////////// IRDA ////////////////////////
IRDA_TXD, // IRDA Transmitter
IRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 1
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////
OTG_DATA, // ISP1362 Data bus 16 Bits
OTG_ADDR, // ISP1362 Address 2 Bits
OTG_CS_N, // ISP1362 Chip Select
OTG_RD_N, // ISP1362 Write
OTG_WR_N, // ISP1362 Read
OTG_RST_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0, // ISP1362 Interrupt 0
OTG_INT1, // ISP1362 Interrupt 1
OTG_DREQ0, // ISP1362 DMA Request 0
OTG_DREQ1, // ISP1362 DMA Request 1
OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_WP_N, // SD Write protect
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (Data in)
TCK, // CPLD -> FPGA (Clock)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (Data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_DATA, // DM9000A DATA bus 16Bits
ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N, // DM9000A Chip Select
ENET_WR_N, // DM9000A Write
ENET_RD_N, // DM9000A Read
ENET_RST_N, // DM9000A Reset
ENET_INT, // DM9000A Interrupt
ENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
TD_DATA, // TV Decoder Data bus 8 bits
TD_HS, // TV Decoder H_SYNC
TD_VS, // TV Decoder V_SYNC
TD_RESET, // TV Decoder Reset
TD_CLK, // TV Decoder Line Locked Clock
//iTD_CLK, // TV Decoder Line Locked Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] SW; // Toggle Switch[17:0]
//////////////////////// 7-SEG Display ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
output [6:0] HEX4; // Seven Segment Digit 4
output [6:0] HEX5; // Seven Segment Digit 5
output [6:0] HEX6; // Seven Segment Digit 6
output [6:0] HEX7; // Seven Segment Digit 7
//////////////////////////// LED ////////////////////////////
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
//////////////////////////// IRDA ////////////////////////////
output IRDA_TXD; // IRDA Transmitter
input IRDA_RXD; // IRDA Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////////////
inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
output OTG_CS_N; // ISP1362 Chip Select
output OTG_RD_N; // ISP1362 Write
output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout [3:0] SD_DAT; // SD Card Data
input SD_WP_N; // SD write protect
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
input TD_CLK; // TV Decoder Line Locked Clock
//input iTD_CLK; // TV Decoder Line Locked Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
// Flash
assign FL_RST_N = 1'b1;
wire FL_16BIT_IP_A0;
// 16*2 LCD Module
assign LCD_ON = 1'b1; // LCD ON
assign LCD_BLON = 1'b1; // LCD Back Light
// All inout port turn to tri-state
assign SD_DAT[0] = 1'bz;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// Disable USB speed select
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
// Turn On TV Decoder
assign TD_RESET = KEY[0];
// Set SD Card to SD Mode
wire [3:1] SD_DAT_dummy;
assign SD_DAT_dummy = 3'bzzz;
assign SD_DAT[3] = 1'b1;
//========== SSRAM
wire [1:0] SRAM_DUMMY_ADDR; // used to ignore the A0/A1 pin from Cypress SSRAM IP core
wire [15:0] SRAM_DUMMY_DQ;
//========== SDRAM
assign DRAM_CLK = pll_c1_memory;
wire CPU_RESET_N;
wire pll_c0_system, pll_c1_memory, pll_c2_audio;
// Reset
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET_N));
///////////////////////// adding your SoPC here ////////////////////////////////
DE2_SoPC DE2_SoPC_inst
(
// globe signals
.clk_50 (CLOCK_50),
.reset_n (CPU_RESET_N),
//.pll_c0_system (pll_c0_system),
//.pll_c1_memory (pll_c1_memory),
//.pll_c2_audio (pll_c2_audio),
//sdram
/*
.zs_addr_from_the_sdram (DRAM_ADDR),
.zs_ba_from_the_sdram ({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram (DRAM_CAS_N),
.zs_cke_from_the_sdram (DRAM_CKE),
.zs_cs_n_from_the_sdram (DRAM_CS_N),
.zs_dq_to_and_from_the_sdram (DRAM_DQ),
.zs_dqm_from_the_sdram ({DRAM_UDQM,DRAM_LDQM}),
.zs_ras_n_from_the_sdram (DRAM_RAS_N),
.zs_we_n_from_the_sdram (DRAM_WE_N),
*/
//ssram
.SRAM_ADDR_from_the_sram (SRAM_ADDR),
.SRAM_CE_N_from_the_sram (SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram (SRAM_DQ),
.SRAM_LB_N_from_the_sram (SRAM_LB_N),
.SRAM_OE_N_from_the_sram (SRAM_OE_N),
.SRAM_UB_N_from_the_sram (SRAM_UB_N),
.SRAM_WE_N_from_the_sram (SRAM_WE_N),
//flash
.tri_state_bridge_flash_address (FL_ADDR),
.tri_state_bridge_flash_readn (FL_OE_N),
.write_n_to_the_cfi_flash_0 (FL_WE_N),
.select_n_to_the_cfi_flash_0 (FL_CE_N),
.tri_state_bridge_flash_data (FL_DQ),
//lcd
.LCD_E_from_the_lcd (LCD_EN),
.LCD_RS_from_the_lcd (LCD_RS),
.LCD_RW_from_the_lcd (LCD_RW),
.LCD_data_to_and_from_the_lcd (LCD_DATA),
//i2c
.scl_pad_io_to_and_from_the_i2c (I2C_SCLK),//(I2C_SCLK),
.sda_pad_io_to_and_from_the_i2c (I2C_SDAT),//(I2C_SDAT),
/*
//sd card
.out_port_from_the_SD_CLK (SD_CLK),
.bidir_port_to_and_from_the_SD_CMD (SD_CMD),
.bidir_port_to_and_from_the_SD_DAT ({SD_DAT_dummy,SD_DAT[0]}),
//.bidir_port_to_and_from_the_sd_dat3 (SD_DAT[3]),
//swtich
.in_port_to_the_pio_button (KEY[3:1]),
.in_port_to_the_pio_switch (SW[17:0]),
//hex
.oSEG0_from_the_seg7 (HEX0),
.oSEG1_from_the_seg7 (HEX1),
.oSEG2_from_the_seg7 (HEX2),
.oSEG3_from_the_seg7 (HEX3),
.oSEG4_from_the_seg7 (HEX4),
.oSEG5_from_the_seg7 (HEX5),
.oSEG6_from_the_seg7 (HEX6),
.oSEG7_from_the_seg7 (HEX7),
//led
.out_port_from_the_pio_green_led (LEDG),
.out_port_from_the_pio_red_led (LEDR),
*/
//the_uart
.rxd_to_the_uart (UART_RXD),
.txd_from_the_uart (UART_TXD),
//vga
.VGA_BLANK_from_the_vga_0 (VGA_BLANK),
.VGA_B_from_the_vga_0 (VGA_B),
.VGA_CLK_from_the_vga_0 (VGA_CLK),
.VGA_G_from_the_vga_0 (VGA_G),
.VGA_HS_from_the_vga_0 (VGA_HS),
.VGA_R_from_the_vga_0 (VGA_R),
.VGA_SYNC_from_the_vga_0 (VGA_SYNC),
.VGA_VS_from_the_vga_0 (VGA_VS),
.iCLK_25_to_the_vga_0 (CLOCK_27)
);
///////////////////////////////////////////////////////////////////////////////////
endmodule |
module Reset_Delay(iRST,iCLK,oRESET);
input iCLK;
input iRST;
output reg oRESET;
reg [27:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oRESET <= 1'b0;
Cont <= 28'h0000000;
end
else
begin
if(Cont!=28'h4FFFFFF) // about 300ms at 50MHz
begin
Cont <= Cont+1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
end
endmodule |
module tg68_ram #(
parameter MS = 512
)(
input wire clk,
input wire tg68_as,
input wire [ 32-1:0] tg68_adr,
input wire tg68_rw,
input wire tg68_lds,
input wire tg68_uds,
input wire [ 16-1:0] tg68_dat_out,
output wire [ 16-1:0] tg68_dat_in,
output wire tg68_dtack
);
// memory
reg [8-1:0] mem0 [0:MS-1];
reg [8-1:0] mem1 [0:MS-1];
// internal signals
reg [16-1:0] mem_do = 0;
reg trn = 1;
reg ack = 1;
// clear on start
integer i;
initial begin
for (i=0; i<MS; i=i+1) begin
mem1[i] = 0;
mem0[i] = 0;
end
end
// read
always @ (posedge clk) begin
if (!tg68_as && tg68_rw) mem_do <= #1 {mem1[tg68_adr[31:1]], mem0[tg68_adr[31:1]]};
end
//write
always @ (posedge clk) begin
if (!tg68_as && !tg68_rw) begin
if (!tg68_uds) mem1[tg68_adr[31:1]] <= #1 tg68_dat_out[15:8];
if (!tg68_lds) mem0[tg68_adr[31:1]] <= #1 tg68_dat_out[7:0];
end
end
// acknowledge
always @ (posedge clk) begin
trn <= #1 tg68_as;
ack <= #1 trn;
end
// outputs
assign tg68_dat_in = mem_do;
assign tg68_dtack = ack || tg68_as; // TODO
// load task
task load;
input [1024*8-1:0] file;
reg [16-1:0] memory[0:MS-1];
reg [16-1:0] dat;
integer i;
begin
$readmemh(file, memory);
for (i=0; i<MS; i=i+1) begin
dat = memory[i];
mem1[i] = dat[15:8];
mem0[i] = dat[7:0];
end
end
endtask
endmodule |
module lm32_interrupt (
// ----- Inputs -------
clk_i,
rst_i,
// From external devices
interrupt,
// From pipeline
stall_x,
`ifdef CFG_DEBUG_ENABLED
non_debug_exception,
debug_exception,
`else
exception,
`endif
eret_q_x,
`ifdef CFG_DEBUG_ENABLED
bret_q_x,
`endif
csr,
csr_write_data,
csr_write_enable,
// ----- Outputs -------
interrupt_exception,
// To pipeline
csr_read_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [interrupts-1:0] interrupt; // Interrupt pins, active-low
input stall_x; // Stall X pipeline stage
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception; // Non-debug related exception has been raised
input debug_exception; // Debug-related exception has been raised
`else
input exception; // Exception has been raised
`endif
input eret_q_x; // Return from exception
`ifdef CFG_DEBUG_ENABLED
input bret_q_x; // Return from breakpoint
`endif
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output interrupt_exception; // Request to raide an interrupt exception
wire interrupt_exception;
output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
reg [`LM32_WORD_RNG] csr_read_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
reg ie; // Interrupt enable
reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
reg [interrupts-1:0] ip; // Interrupt pending
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted (active-low) or are already pending
assign asserted = ip | interrupt;
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
if (interrupts > 1)
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
`LM32_CSR_IM: csr_read_data = im;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
else
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
endgenerate
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
end
end
else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
ip <= {interrupts{1'b0}};
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
end
end
endgenerate
endmodule |
module adapter_axi_stream_2_block_fifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
)(
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [DATA_WIDTH - 1:0] i_axi_data,
input [STROBE_WIDTH - 1:0] i_axi_keep,
input i_axi_last,
input i_axi_valid,
//Ping Pong FIFO Write Controller
output o_block_fifo_clk,
input i_block_fifo_rdy,
output reg o_block_fifo_act,
input [23:0] i_block_fifo_size,
output reg o_block_fifo_stb,
output reg [DATA_WIDTH - 1:0] o_block_fifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
wire clk; //Convenience Signal
reg [3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
//This is a little strange to just connect the output clock with the input clock but if this is done
//Users do not need to figure out how to hook up the clocks
assign o_block_fifo_clk = i_axi_clk;
assign clk = i_axi_clk;
assign o_axi_ready = o_block_fifo_act && (r_count < i_block_fifo_size);
//synchronous logic
always @ (posedge clk) begin
o_block_fifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_block_fifo_act <= 0;
o_block_fifo_data <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_block_fifo_act <= 0;
if (i_block_fifo_rdy && !o_block_fifo_act) begin
r_count <= 0;
o_block_fifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_block_fifo_size) begin
if (i_axi_valid) begin
o_block_fifo_stb <= 1;
o_block_fifo_data <= i_axi_data;
r_count <= r_count + 1;
end
end
//Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (i_axi_last) begin
state <= RELEASE;
end
end
RELEASE: begin
o_block_fifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule |
module mux4 #(parameter WIREWIDTH = 1) (input wire [1:0] s,
input wire [WIREWIDTH:0] d0, d1, d2,d3,
output reg [WIREWIDTH:0] o);
initial begin
$schematic_boundingbox(40,200);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(30,30);
$schematic_coord(30,170);
$schematic_coord(10,190);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(20,19);
$schematic_coord(20,10);
$schematic_lineend;
$schematic_connector(d0,0,40);
$schematic_connector(d1,0,80);
$schematic_connector(d2,0,120);
$schematic_connector(d3,0,160);
$schematic_connector(o,40,100);
$schematic_connector(s,20,0);
$schematic_symboltext("0", 20,40);
$schematic_symboltext("1", 20,80);
$schematic_symboltext("2", 20,120);
$schematic_symboltext("3", 20,160);
end
always @* begin
case(s)
0: o = d0;
1: o = d1;
2: o = d2;
3: o = d3;
endcase
end
endmodule |
module sky130_fd_sc_lp__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule |
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module ad_dds (
// interface
clk,
dds_format,
dds_phase_0,
dds_scale_0,
dds_phase_1,
dds_scale_1,
dds_data);
// interface
input clk;
input dds_format;
input [15:0] dds_phase_0;
input [15:0] dds_scale_0;
input [15:0] dds_phase_1;
input [15:0] dds_scale_1;
output [15:0] dds_data;
// internal registers
reg [15:0] dds_data_int = 'd0;
reg [15:0] dds_data = 'd0;
reg [15:0] dds_scale_0_r = 'd0;
reg [15:0] dds_scale_1_r = 'd0;
// internal signals
wire [15:0] dds_data_0_s;
wire [15:0] dds_data_1_s;
// dds channel output
always @(posedge clk) begin
dds_data_int <= dds_data_0_s + dds_data_1_s;
dds_data[15:15] <= dds_data_int[15] ^ dds_format;
dds_data[14: 0] <= dds_data_int[14:0];
end
always @(posedge clk) begin
dds_scale_0_r <= dds_scale_0;
dds_scale_1_r <= dds_scale_1;
end
// dds-1
ad_dds_1 i_dds_1_0 (
.clk (clk),
.angle (dds_phase_0),
.scale (dds_scale_0_r),
.dds_data (dds_data_0_s));
// dds-2
ad_dds_1 i_dds_1_1 (
.clk (clk),
.angle (dds_phase_1),
.scale (dds_scale_1_r),
.dds_data (dds_data_1_s));
endmodule |
module Data_Mem(
a,
d,
clk,
we,
spo);
input [5 : 0] a;
input [31 : 0] d;
input clk;
input we;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("spartan3"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("Data_Mem.mif"),
.C_MEM_TYPE(1),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32))
inst (
.A(a),
.D(d),
.CLK(clk),
.WE(we),
.SPO(spo),
.DPRA(),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of Data_Mem is "black_box"
endmodule |
module sky130_fd_sc_ls__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hdll__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module tx_sm_tb ();
`include "dut.v"
integer i;
initial
begin
//$dumpfile("test.vcd");
//$dumpvars(0,tx_sm_tb,U_tx_sm);
end
initial
begin
#15 reset = 0;
// Will initially wait IFG before making any transmissions
// Set fifo_count to 1 and check IFG delay before tx_enable is asserted
// Clock flips every 5ns -> 10ns period
// tx_enable_monitor will take care of these checks
fifo_count = 1;
#110
expected_tx_enable = 1;
// MAC should then start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
// Assert Carrier Sense - Should have no effect in Full Duplex
carrier_sense = 1;
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Assert a collision - Should have no effect in Full Duplex
collision = 1;
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
$finish;
end
endmodule |
module LowPassFilter(clk, new_sample, input_sample, output_sample);
input clk;
input new_sample;
reg enable_systolic;
wire clk_systolic;
input [15:0] input_sample;
output [15:0] output_sample;
reg [2:0] state;
localparam IDLE = 3'd0,
CLK_A = 3'd1,
CLK_B = 3'd2,
CLK_C = 3'd3,
CLK_D = 3'd4;
initial begin
state <= IDLE;
enable_systolic <= 1'b0;
end
always @ (posedge clk) begin
case(state)
IDLE: begin
if(new_sample)
state <= CLK_A;
else
state <= IDLE;
end
CLK_A: begin
enable_systolic <= 1'b1;
state <= CLK_B;
end
CLK_B: begin
enable_systolic <= 1'b1;
state <= CLK_C;
end
CLK_C: begin
enable_systolic <= 1'b0;
state <= IDLE;
end
endcase
end
localparam NUM_COEFFS = 99; // 57
localparam BITS_COEFF = 8;
localparam NUM_COEFFS_BITS = NUM_COEFFS * BITS_COEFF;
/*
// Simulator coefficients
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd1,
8'sd1,
8'sd1,
-8'sd1
};
*/
/*
// Low pass coefficients
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
6'd0,
6'd0,
6'd0,
6'd1,
6'd1,
6'd2,
6'd3,
6'd5,
6'd7,
6'd10,
6'd12,
6'd15,
6'd19,
6'd22,
6'd25,
6'd28,
6'd31,
6'd33,
6'd34,
6'd34,
6'd34,
6'd33,
6'd31,
6'd28,
6'd25,
6'd22,
6'd19,
6'd15,
6'd12,
6'd10,
6'd7,
6'd5,
6'd3,
6'd2,
6'd1,
6'd1,
6'd0,
6'd0,
6'd0
};
*/
// low pass 99 coeff, 100 Hz stop freq, 60 dB attenuate, 48 khz sampling freq, multiplier: 4926
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd0,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd2,
8'sd2,
8'sd2,
8'sd2,
8'sd3,
8'sd3,
8'sd4,
8'sd4,
8'sd4,
8'sd5,
8'sd5,
8'sd6,
8'sd6,
8'sd7,
8'sd8,
8'sd8,
8'sd9,
8'sd9,
8'sd10,
8'sd11,
8'sd11,
8'sd12,
8'sd12,
8'sd13,
8'sd14,
8'sd14,
8'sd15,
8'sd15,
8'sd16,
8'sd16,
8'sd17,
8'sd17,
8'sd18,
8'sd18,
8'sd19,
8'sd19,
8'sd19,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd21,
8'sd21,
8'sd21,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd19,
8'sd19,
8'sd19,
8'sd18,
8'sd18,
8'sd17,
8'sd17,
8'sd16,
8'sd16,
8'sd15,
8'sd15,
8'sd14,
8'sd14,
8'sd13,
8'sd12,
8'sd12,
8'sd11,
8'sd11,
8'sd10,
8'sd9,
8'sd9,
8'sd8,
8'sd8,
8'sd7,
8'sd6,
8'sd6,
8'sd5,
8'sd5,
8'sd4,
8'sd4,
8'sd4,
8'sd3,
8'sd3,
8'sd2,
8'sd2,
8'sd2,
8'sd2,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd0
};
wire [31:0] a_out [0:NUM_COEFFS];
wire [31:0] b_out [0:NUM_COEFFS];
genvar j;
generate
for(j = 0; j < NUM_COEFFS; j = j+1) begin: GEN
processingUnit #(COEFFS[NUM_COEFFS_BITS-1-(j*BITS_COEFF):NUM_COEFFS_BITS-(j*BITS_COEFF)-BITS_COEFF]) gen_proc(
.clk(clk),
.a_in(a_out[j]),
.a_out(a_out[j+1]),
.b_out(b_out[j]),
.b_in(b_out[j+1]),
.enable(enable_systolic)
);
end
endgenerate
assign a_out[0] = {{16{input_sample[15]}}, input_sample}; // sign extend to 32 bits
assign b_out[NUM_COEFFS] = 32'h0;
assign output_sample = b_out[0][26:10]; // divide by 1024
endmodule |
module top(
output reg serial_tx,
input serial_rx,
input cpu_reset,
input clk100
);
wire ctrl_reset_reset_re;
wire ctrl_reset_reset_r;
wire ctrl_reset_reset_we;
reg ctrl_reset_reset_w = 1'd0;
reg [31:0] ctrl_storage = 32'd305419896;
reg ctrl_re = 1'd0;
wire [31:0] ctrl_bus_errors_status;
wire ctrl_bus_errors_we;
wire ctrl_reset;
wire ctrl_bus_error;
reg [31:0] ctrl_bus_errors = 32'd0;
wire vexriscv_reset;
wire [29:0] vexriscv_ibus_adr;
wire [31:0] vexriscv_ibus_dat_w;
wire [31:0] vexriscv_ibus_dat_r;
wire [3:0] vexriscv_ibus_sel;
wire vexriscv_ibus_cyc;
wire vexriscv_ibus_stb;
wire vexriscv_ibus_ack;
wire vexriscv_ibus_we;
wire [2:0] vexriscv_ibus_cti;
wire [1:0] vexriscv_ibus_bte;
wire vexriscv_ibus_err;
wire [29:0] vexriscv_dbus_adr;
wire [31:0] vexriscv_dbus_dat_w;
wire [31:0] vexriscv_dbus_dat_r;
wire [3:0] vexriscv_dbus_sel;
wire vexriscv_dbus_cyc;
wire vexriscv_dbus_stb;
wire vexriscv_dbus_ack;
wire vexriscv_dbus_we;
wire [2:0] vexriscv_dbus_cti;
wire [1:0] vexriscv_dbus_bte;
wire vexriscv_dbus_err;
reg [31:0] vexriscv_interrupt = 32'd0;
wire [29:0] interface0_soc_bus_adr;
wire [31:0] interface0_soc_bus_dat_w;
wire [31:0] interface0_soc_bus_dat_r;
wire [3:0] interface0_soc_bus_sel;
wire interface0_soc_bus_cyc;
wire interface0_soc_bus_stb;
wire interface0_soc_bus_ack;
wire interface0_soc_bus_we;
wire [2:0] interface0_soc_bus_cti;
wire [1:0] interface0_soc_bus_bte;
wire interface0_soc_bus_err;
wire [29:0] interface1_soc_bus_adr;
wire [31:0] interface1_soc_bus_dat_w;
wire [31:0] interface1_soc_bus_dat_r;
wire [3:0] interface1_soc_bus_sel;
wire interface1_soc_bus_cyc;
wire interface1_soc_bus_stb;
wire interface1_soc_bus_ack;
wire interface1_soc_bus_we;
wire [2:0] interface1_soc_bus_cti;
wire [1:0] interface1_soc_bus_bte;
wire interface1_soc_bus_err;
wire [29:0] rom_bus_adr;
wire [31:0] rom_bus_dat_w;
wire [31:0] rom_bus_dat_r;
wire [3:0] rom_bus_sel;
wire rom_bus_cyc;
wire rom_bus_stb;
reg rom_bus_ack = 1'd0;
wire rom_bus_we;
wire [2:0] rom_bus_cti;
wire [1:0] rom_bus_bte;
reg rom_bus_err = 1'd0;
wire [12:0] rom_adr;
wire [31:0] rom_dat_r;
wire [29:0] sram_bus_adr;
wire [31:0] sram_bus_dat_w;
wire [31:0] sram_bus_dat_r;
wire [3:0] sram_bus_sel;
wire sram_bus_cyc;
wire sram_bus_stb;
reg sram_bus_ack = 1'd0;
wire sram_bus_we;
wire [2:0] sram_bus_cti;
wire [1:0] sram_bus_bte;
reg sram_bus_err = 1'd0;
wire [12:0] sram_adr;
wire [31:0] sram_dat_r;
reg [3:0] sram_we = 4'd0;
wire [31:0] sram_dat_w;
reg [31:0] uart_phy_storage = 32'd4947802;
reg uart_phy_re = 1'd0;
wire uart_phy_sink_valid;
reg uart_phy_sink_ready = 1'd0;
wire uart_phy_sink_first;
wire uart_phy_sink_last;
wire [7:0] uart_phy_sink_payload_data;
reg uart_phy_uart_clk_txen = 1'd0;
reg [31:0] uart_phy_phase_accumulator_tx = 32'd0;
reg [7:0] uart_phy_tx_reg = 8'd0;
reg [3:0] uart_phy_tx_bitcount = 4'd0;
reg uart_phy_tx_busy = 1'd0;
reg uart_phy_source_valid = 1'd0;
wire uart_phy_source_ready;
reg uart_phy_source_first = 1'd0;
reg uart_phy_source_last = 1'd0;
reg [7:0] uart_phy_source_payload_data = 8'd0;
reg uart_phy_uart_clk_rxen = 1'd0;
reg [31:0] uart_phy_phase_accumulator_rx = 32'd0;
wire uart_phy_rx;
reg uart_phy_rx_r = 1'd0;
reg [7:0] uart_phy_rx_reg = 8'd0;
reg [3:0] uart_phy_rx_bitcount = 4'd0;
reg uart_phy_rx_busy = 1'd0;
wire uart_rxtx_re;
wire [7:0] uart_rxtx_r;
wire uart_rxtx_we;
wire [7:0] uart_rxtx_w;
wire uart_txfull_status;
wire uart_txfull_we;
wire uart_rxempty_status;
wire uart_rxempty_we;
wire uart_irq;
wire uart_tx_status;
reg uart_tx_pending = 1'd0;
wire uart_tx_trigger;
reg uart_tx_clear = 1'd0;
reg uart_tx_old_trigger = 1'd0;
wire uart_rx_status;
reg uart_rx_pending = 1'd0;
wire uart_rx_trigger;
reg uart_rx_clear = 1'd0;
reg uart_rx_old_trigger = 1'd0;
wire uart_eventmanager_status_re;
wire [1:0] uart_eventmanager_status_r;
wire uart_eventmanager_status_we;
reg [1:0] uart_eventmanager_status_w = 2'd0;
wire uart_eventmanager_pending_re;
wire [1:0] uart_eventmanager_pending_r;
wire uart_eventmanager_pending_we;
reg [1:0] uart_eventmanager_pending_w = 2'd0;
reg [1:0] uart_eventmanager_storage = 2'd0;
reg uart_eventmanager_re = 1'd0;
wire uart_tx_fifo_sink_valid;
wire uart_tx_fifo_sink_ready;
reg uart_tx_fifo_sink_first = 1'd0;
reg uart_tx_fifo_sink_last = 1'd0;
wire [7:0] uart_tx_fifo_sink_payload_data;
wire uart_tx_fifo_source_valid;
wire uart_tx_fifo_source_ready;
wire uart_tx_fifo_source_first;
wire uart_tx_fifo_source_last;
wire [7:0] uart_tx_fifo_source_payload_data;
wire uart_tx_fifo_re;
reg uart_tx_fifo_readable = 1'd0;
wire uart_tx_fifo_syncfifo_we;
wire uart_tx_fifo_syncfifo_writable;
wire uart_tx_fifo_syncfifo_re;
wire uart_tx_fifo_syncfifo_readable;
wire [9:0] uart_tx_fifo_syncfifo_din;
wire [9:0] uart_tx_fifo_syncfifo_dout;
reg [4:0] uart_tx_fifo_level0 = 5'd0;
reg uart_tx_fifo_replace = 1'd0;
reg [3:0] uart_tx_fifo_produce = 4'd0;
reg [3:0] uart_tx_fifo_consume = 4'd0;
reg [3:0] uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_tx_fifo_wrport_dat_r;
wire uart_tx_fifo_wrport_we;
wire [9:0] uart_tx_fifo_wrport_dat_w;
wire uart_tx_fifo_do_read;
wire [3:0] uart_tx_fifo_rdport_adr;
wire [9:0] uart_tx_fifo_rdport_dat_r;
wire uart_tx_fifo_rdport_re;
wire [4:0] uart_tx_fifo_level1;
wire [7:0] uart_tx_fifo_fifo_in_payload_data;
wire uart_tx_fifo_fifo_in_first;
wire uart_tx_fifo_fifo_in_last;
wire [7:0] uart_tx_fifo_fifo_out_payload_data;
wire uart_tx_fifo_fifo_out_first;
wire uart_tx_fifo_fifo_out_last;
wire uart_rx_fifo_sink_valid;
wire uart_rx_fifo_sink_ready;
wire uart_rx_fifo_sink_first;
wire uart_rx_fifo_sink_last;
wire [7:0] uart_rx_fifo_sink_payload_data;
wire uart_rx_fifo_source_valid;
wire uart_rx_fifo_source_ready;
wire uart_rx_fifo_source_first;
wire uart_rx_fifo_source_last;
wire [7:0] uart_rx_fifo_source_payload_data;
wire uart_rx_fifo_re;
reg uart_rx_fifo_readable = 1'd0;
wire uart_rx_fifo_syncfifo_we;
wire uart_rx_fifo_syncfifo_writable;
wire uart_rx_fifo_syncfifo_re;
wire uart_rx_fifo_syncfifo_readable;
wire [9:0] uart_rx_fifo_syncfifo_din;
wire [9:0] uart_rx_fifo_syncfifo_dout;
reg [4:0] uart_rx_fifo_level0 = 5'd0;
reg uart_rx_fifo_replace = 1'd0;
reg [3:0] uart_rx_fifo_produce = 4'd0;
reg [3:0] uart_rx_fifo_consume = 4'd0;
reg [3:0] uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_rx_fifo_wrport_dat_r;
wire uart_rx_fifo_wrport_we;
wire [9:0] uart_rx_fifo_wrport_dat_w;
wire uart_rx_fifo_do_read;
wire [3:0] uart_rx_fifo_rdport_adr;
wire [9:0] uart_rx_fifo_rdport_dat_r;
wire uart_rx_fifo_rdport_re;
wire [4:0] uart_rx_fifo_level1;
wire [7:0] uart_rx_fifo_fifo_in_payload_data;
wire uart_rx_fifo_fifo_in_first;
wire uart_rx_fifo_fifo_in_last;
wire [7:0] uart_rx_fifo_fifo_out_payload_data;
wire uart_rx_fifo_fifo_out_first;
wire uart_rx_fifo_fifo_out_last;
reg uart_reset = 1'd0;
reg [31:0] timer0_load_storage = 32'd0;
reg timer0_load_re = 1'd0;
reg [31:0] timer0_reload_storage = 32'd0;
reg timer0_reload_re = 1'd0;
reg timer0_en_storage = 1'd0;
reg timer0_en_re = 1'd0;
reg timer0_update_value_storage = 1'd0;
reg timer0_update_value_re = 1'd0;
reg [31:0] timer0_value_status = 32'd0;
wire timer0_value_we;
wire timer0_irq;
wire timer0_zero_status;
reg timer0_zero_pending = 1'd0;
wire timer0_zero_trigger;
reg timer0_zero_clear = 1'd0;
reg timer0_zero_old_trigger = 1'd0;
wire timer0_eventmanager_status_re;
wire timer0_eventmanager_status_r;
wire timer0_eventmanager_status_we;
wire timer0_eventmanager_status_w;
wire timer0_eventmanager_pending_re;
wire timer0_eventmanager_pending_r;
wire timer0_eventmanager_pending_we;
wire timer0_eventmanager_pending_w;
reg timer0_eventmanager_storage = 1'd0;
reg timer0_eventmanager_re = 1'd0;
reg [31:0] timer0_value = 32'd0;
reg [13:0] interface_adr = 14'd0;
reg interface_we = 1'd0;
wire [7:0] interface_dat_w;
wire [7:0] interface_dat_r;
wire [29:0] bus_wishbone_adr;
wire [31:0] bus_wishbone_dat_w;
wire [31:0] bus_wishbone_dat_r;
wire [3:0] bus_wishbone_sel;
wire bus_wishbone_cyc;
wire bus_wishbone_stb;
reg bus_wishbone_ack = 1'd0;
wire bus_wishbone_we;
wire [2:0] bus_wishbone_cti;
wire [1:0] bus_wishbone_bte;
reg bus_wishbone_err = 1'd0;
(* dont_touch = "true" *) wire sys_clk;
wire sys_rst;
wire reset;
wire locked;
wire clkin;
wire clkout;
wire clkout_buf;
reg state = 1'd0;
reg next_state = 1'd0;
wire pll_fb;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
reg [31:0] shared_dat_r = 32'd0;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
reg shared_ack = 1'd0;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire [1:0] request;
reg grant = 1'd0;
reg [2:0] slave_sel = 3'd0;
reg [2:0] slave_sel_r = 3'd0;
reg error = 1'd0;
wire wait_1;
wire done;
reg [19:0] count = 20'd1000000;
wire [13:0] csrbankarray_interface0_bank_bus_adr;
wire csrbankarray_interface0_bank_bus_we;
wire [7:0] csrbankarray_interface0_bank_bus_dat_w;
reg [7:0] csrbankarray_interface0_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank0_scratch3_re;
wire [7:0] csrbankarray_csrbank0_scratch3_r;
wire csrbankarray_csrbank0_scratch3_we;
wire [7:0] csrbankarray_csrbank0_scratch3_w;
wire csrbankarray_csrbank0_scratch2_re;
wire [7:0] csrbankarray_csrbank0_scratch2_r;
wire csrbankarray_csrbank0_scratch2_we;
wire [7:0] csrbankarray_csrbank0_scratch2_w;
wire csrbankarray_csrbank0_scratch1_re;
wire [7:0] csrbankarray_csrbank0_scratch1_r;
wire csrbankarray_csrbank0_scratch1_we;
wire [7:0] csrbankarray_csrbank0_scratch1_w;
wire csrbankarray_csrbank0_scratch0_re;
wire [7:0] csrbankarray_csrbank0_scratch0_r;
wire csrbankarray_csrbank0_scratch0_we;
wire [7:0] csrbankarray_csrbank0_scratch0_w;
wire csrbankarray_csrbank0_bus_errors3_re;
wire [7:0] csrbankarray_csrbank0_bus_errors3_r;
wire csrbankarray_csrbank0_bus_errors3_we;
wire [7:0] csrbankarray_csrbank0_bus_errors3_w;
wire csrbankarray_csrbank0_bus_errors2_re;
wire [7:0] csrbankarray_csrbank0_bus_errors2_r;
wire csrbankarray_csrbank0_bus_errors2_we;
wire [7:0] csrbankarray_csrbank0_bus_errors2_w;
wire csrbankarray_csrbank0_bus_errors1_re;
wire [7:0] csrbankarray_csrbank0_bus_errors1_r;
wire csrbankarray_csrbank0_bus_errors1_we;
wire [7:0] csrbankarray_csrbank0_bus_errors1_w;
wire csrbankarray_csrbank0_bus_errors0_re;
wire [7:0] csrbankarray_csrbank0_bus_errors0_r;
wire csrbankarray_csrbank0_bus_errors0_we;
wire [7:0] csrbankarray_csrbank0_bus_errors0_w;
wire csrbankarray_csrbank0_sel;
wire [13:0] csrbankarray_sram_bus_adr;
wire csrbankarray_sram_bus_we;
wire [7:0] csrbankarray_sram_bus_dat_w;
reg [7:0] csrbankarray_sram_bus_dat_r = 8'd0;
wire [3:0] csrbankarray_adr;
wire [7:0] csrbankarray_dat_r;
wire csrbankarray_sel;
reg csrbankarray_sel_r = 1'd0;
wire [13:0] csrbankarray_interface1_bank_bus_adr;
wire csrbankarray_interface1_bank_bus_we;
wire [7:0] csrbankarray_interface1_bank_bus_dat_w;
reg [7:0] csrbankarray_interface1_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank1_load3_re;
wire [7:0] csrbankarray_csrbank1_load3_r;
wire csrbankarray_csrbank1_load3_we;
wire [7:0] csrbankarray_csrbank1_load3_w;
wire csrbankarray_csrbank1_load2_re;
wire [7:0] csrbankarray_csrbank1_load2_r;
wire csrbankarray_csrbank1_load2_we;
wire [7:0] csrbankarray_csrbank1_load2_w;
wire csrbankarray_csrbank1_load1_re;
wire [7:0] csrbankarray_csrbank1_load1_r;
wire csrbankarray_csrbank1_load1_we;
wire [7:0] csrbankarray_csrbank1_load1_w;
wire csrbankarray_csrbank1_load0_re;
wire [7:0] csrbankarray_csrbank1_load0_r;
wire csrbankarray_csrbank1_load0_we;
wire [7:0] csrbankarray_csrbank1_load0_w;
wire csrbankarray_csrbank1_reload3_re;
wire [7:0] csrbankarray_csrbank1_reload3_r;
wire csrbankarray_csrbank1_reload3_we;
wire [7:0] csrbankarray_csrbank1_reload3_w;
wire csrbankarray_csrbank1_reload2_re;
wire [7:0] csrbankarray_csrbank1_reload2_r;
wire csrbankarray_csrbank1_reload2_we;
wire [7:0] csrbankarray_csrbank1_reload2_w;
wire csrbankarray_csrbank1_reload1_re;
wire [7:0] csrbankarray_csrbank1_reload1_r;
wire csrbankarray_csrbank1_reload1_we;
wire [7:0] csrbankarray_csrbank1_reload1_w;
wire csrbankarray_csrbank1_reload0_re;
wire [7:0] csrbankarray_csrbank1_reload0_r;
wire csrbankarray_csrbank1_reload0_we;
wire [7:0] csrbankarray_csrbank1_reload0_w;
wire csrbankarray_csrbank1_en0_re;
wire csrbankarray_csrbank1_en0_r;
wire csrbankarray_csrbank1_en0_we;
wire csrbankarray_csrbank1_en0_w;
wire csrbankarray_csrbank1_update_value0_re;
wire csrbankarray_csrbank1_update_value0_r;
wire csrbankarray_csrbank1_update_value0_we;
wire csrbankarray_csrbank1_update_value0_w;
wire csrbankarray_csrbank1_value3_re;
wire [7:0] csrbankarray_csrbank1_value3_r;
wire csrbankarray_csrbank1_value3_we;
wire [7:0] csrbankarray_csrbank1_value3_w;
wire csrbankarray_csrbank1_value2_re;
wire [7:0] csrbankarray_csrbank1_value2_r;
wire csrbankarray_csrbank1_value2_we;
wire [7:0] csrbankarray_csrbank1_value2_w;
wire csrbankarray_csrbank1_value1_re;
wire [7:0] csrbankarray_csrbank1_value1_r;
wire csrbankarray_csrbank1_value1_we;
wire [7:0] csrbankarray_csrbank1_value1_w;
wire csrbankarray_csrbank1_value0_re;
wire [7:0] csrbankarray_csrbank1_value0_r;
wire csrbankarray_csrbank1_value0_we;
wire [7:0] csrbankarray_csrbank1_value0_w;
wire csrbankarray_csrbank1_ev_enable0_re;
wire csrbankarray_csrbank1_ev_enable0_r;
wire csrbankarray_csrbank1_ev_enable0_we;
wire csrbankarray_csrbank1_ev_enable0_w;
wire csrbankarray_csrbank1_sel;
wire [13:0] csrbankarray_interface2_bank_bus_adr;
wire csrbankarray_interface2_bank_bus_we;
wire [7:0] csrbankarray_interface2_bank_bus_dat_w;
reg [7:0] csrbankarray_interface2_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank2_txfull_re;
wire csrbankarray_csrbank2_txfull_r;
wire csrbankarray_csrbank2_txfull_we;
wire csrbankarray_csrbank2_txfull_w;
wire csrbankarray_csrbank2_rxempty_re;
wire csrbankarray_csrbank2_rxempty_r;
wire csrbankarray_csrbank2_rxempty_we;
wire csrbankarray_csrbank2_rxempty_w;
wire csrbankarray_csrbank2_ev_enable0_re;
wire [1:0] csrbankarray_csrbank2_ev_enable0_r;
wire csrbankarray_csrbank2_ev_enable0_we;
wire [1:0] csrbankarray_csrbank2_ev_enable0_w;
wire csrbankarray_csrbank2_sel;
wire [13:0] csrbankarray_interface3_bank_bus_adr;
wire csrbankarray_interface3_bank_bus_we;
wire [7:0] csrbankarray_interface3_bank_bus_dat_w;
reg [7:0] csrbankarray_interface3_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank3_tuning_word3_re;
wire [7:0] csrbankarray_csrbank3_tuning_word3_r;
wire csrbankarray_csrbank3_tuning_word3_we;
wire [7:0] csrbankarray_csrbank3_tuning_word3_w;
wire csrbankarray_csrbank3_tuning_word2_re;
wire [7:0] csrbankarray_csrbank3_tuning_word2_r;
wire csrbankarray_csrbank3_tuning_word2_we;
wire [7:0] csrbankarray_csrbank3_tuning_word2_w;
wire csrbankarray_csrbank3_tuning_word1_re;
wire [7:0] csrbankarray_csrbank3_tuning_word1_r;
wire csrbankarray_csrbank3_tuning_word1_we;
wire [7:0] csrbankarray_csrbank3_tuning_word1_w;
wire csrbankarray_csrbank3_tuning_word0_re;
wire [7:0] csrbankarray_csrbank3_tuning_word0_r;
wire csrbankarray_csrbank3_tuning_word0_we;
wire [7:0] csrbankarray_csrbank3_tuning_word0_w;
wire csrbankarray_csrbank3_sel;
wire [13:0] csrcon_adr;
wire csrcon_we;
wire [7:0] csrcon_dat_w;
wire [7:0] csrcon_dat_r;
reg [29:0] array_muxed0 = 30'd0;
reg [31:0] array_muxed1 = 32'd0;
reg [3:0] array_muxed2 = 4'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 3'd0;
reg [1:0] array_muxed7 = 2'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg regs1 = 1'd0;
wire xilinxasyncresetsynchronizerimpl;
wire xilinxasyncresetsynchronizerimpl_rst_meta;
assign vexriscv_reset = ctrl_reset;
assign ctrl_bus_error = error;
always @(*) begin
vexriscv_interrupt <= 32'd0;
vexriscv_interrupt[1] <= timer0_irq;
vexriscv_interrupt[0] <= uart_irq;
end
assign ctrl_reset = ctrl_reset_reset_re;
assign ctrl_bus_errors_status = ctrl_bus_errors;
assign interface0_soc_bus_adr = vexriscv_ibus_adr;
assign interface0_soc_bus_dat_w = vexriscv_ibus_dat_w;
assign vexriscv_ibus_dat_r = interface0_soc_bus_dat_r;
assign interface0_soc_bus_sel = vexriscv_ibus_sel;
assign interface0_soc_bus_cyc = vexriscv_ibus_cyc;
assign interface0_soc_bus_stb = vexriscv_ibus_stb;
assign vexriscv_ibus_ack = interface0_soc_bus_ack;
assign interface0_soc_bus_we = vexriscv_ibus_we;
assign interface0_soc_bus_cti = vexriscv_ibus_cti;
assign interface0_soc_bus_bte = vexriscv_ibus_bte;
assign vexriscv_ibus_err = interface0_soc_bus_err;
assign interface1_soc_bus_adr = vexriscv_dbus_adr;
assign interface1_soc_bus_dat_w = vexriscv_dbus_dat_w;
assign vexriscv_dbus_dat_r = interface1_soc_bus_dat_r;
assign interface1_soc_bus_sel = vexriscv_dbus_sel;
assign interface1_soc_bus_cyc = vexriscv_dbus_cyc;
assign interface1_soc_bus_stb = vexriscv_dbus_stb;
assign vexriscv_dbus_ack = interface1_soc_bus_ack;
assign interface1_soc_bus_we = vexriscv_dbus_we;
assign interface1_soc_bus_cti = vexriscv_dbus_cti;
assign interface1_soc_bus_bte = vexriscv_dbus_bte;
assign vexriscv_dbus_err = interface1_soc_bus_err;
assign rom_adr = rom_bus_adr[12:0];
assign rom_bus_dat_r = rom_dat_r;
always @(*) begin
sram_we <= 4'd0;
sram_we[0] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[0]);
sram_we[1] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[1]);
sram_we[2] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[2]);
sram_we[3] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[3]);
end
assign sram_adr = sram_bus_adr[12:0];
assign sram_bus_dat_r = sram_dat_r;
assign sram_dat_w = sram_bus_dat_w;
assign uart_tx_fifo_sink_valid = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
assign uart_phy_sink_valid = uart_tx_fifo_source_valid;
assign uart_tx_fifo_source_ready = uart_phy_sink_ready;
assign uart_phy_sink_first = uart_tx_fifo_source_first;
assign uart_phy_sink_last = uart_tx_fifo_source_last;
assign uart_phy_sink_payload_data = uart_tx_fifo_source_payload_data;
assign uart_tx_trigger = (~uart_tx_fifo_sink_ready);
assign uart_rx_fifo_sink_valid = uart_phy_source_valid;
assign uart_phy_source_ready = uart_rx_fifo_sink_ready;
assign uart_rx_fifo_sink_first = uart_phy_source_first;
assign uart_rx_fifo_sink_last = uart_phy_source_last;
assign uart_rx_fifo_sink_payload_data = uart_phy_source_payload_data;
assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ready = uart_rx_clear;
assign uart_rx_trigger = (~uart_rx_fifo_source_valid);
always @(*) begin
uart_tx_clear <= 1'd0;
if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[0])) begin
uart_tx_clear <= 1'd1;
end
end
always @(*) begin
uart_eventmanager_status_w <= 2'd0;
uart_eventmanager_status_w[0] <= uart_tx_status;
uart_eventmanager_status_w[1] <= uart_rx_status;
end
always @(*) begin
uart_rx_clear <= 1'd0;
if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[1])) begin
uart_rx_clear <= 1'd1;
end
end
always @(*) begin
uart_eventmanager_pending_w <= 2'd0;
uart_eventmanager_pending_w[0] <= uart_tx_pending;
uart_eventmanager_pending_w[1] <= uart_rx_pending;
end
assign uart_irq = ((uart_eventmanager_pending_w[0] & uart_eventmanager_storage[0]) | (uart_eventmanager_pending_w[1] & uart_eventmanager_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
always @(*) begin
uart_tx_fifo_wrport_adr <= 4'd0;
if (uart_tx_fifo_replace) begin
uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
end else begin
uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
always @(*) begin
uart_rx_fifo_wrport_adr <= 4'd0;
if (uart_rx_fifo_replace) begin
uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
end else begin
uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
assign timer0_zero_trigger = (timer0_value != 1'd0);
assign timer0_eventmanager_status_w = timer0_zero_status;
always @(*) begin
timer0_zero_clear <= 1'd0;
if ((timer0_eventmanager_pending_re & timer0_eventmanager_pending_r)) begin
timer0_zero_clear <= 1'd1;
end
end
assign timer0_eventmanager_pending_w = timer0_zero_pending;
assign timer0_irq = (timer0_eventmanager_pending_w & timer0_eventmanager_storage);
assign timer0_zero_status = timer0_zero_trigger;
assign interface_dat_w = bus_wishbone_dat_w;
assign bus_wishbone_dat_r = interface_dat_r;
always @(*) begin
next_state <= 1'd0;
interface_adr <= 14'd0;
interface_we <= 1'd0;
bus_wishbone_ack <= 1'd0;
next_state <= state;
case (state)
1'd1: begin
bus_wishbone_ack <= 1'd1;
next_state <= 1'd0;
end
default: begin
if ((bus_wishbone_cyc & bus_wishbone_stb)) begin
interface_adr <= bus_wishbone_adr;
interface_we <= bus_wishbone_we;
next_state <= 1'd1;
end
end
endcase
end
assign reset = (~cpu_reset);
assign sys_clk = clkout_buf;
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign interface0_soc_bus_dat_r = shared_dat_r;
assign interface1_soc_bus_dat_r = shared_dat_r;
assign interface0_soc_bus_ack = (shared_ack & (grant == 1'd0));
assign interface1_soc_bus_ack = (shared_ack & (grant == 1'd1));
assign interface0_soc_bus_err = (shared_err & (grant == 1'd0));
assign interface1_soc_bus_err = (shared_err & (grant == 1'd1));
assign request = {interface1_soc_bus_cyc, interface0_soc_bus_cyc};
always @(*) begin
slave_sel <= 3'd0;
slave_sel[0] <= (shared_adr[28:13] == 1'd0);
slave_sel[1] <= (shared_adr[28:13] == 10'd512);
slave_sel[2] <= (shared_adr[28:22] == 2'd2);
end
assign rom_bus_adr = shared_adr;
assign rom_bus_dat_w = shared_dat_w;
assign rom_bus_sel = shared_sel;
assign rom_bus_stb = shared_stb;
assign rom_bus_we = shared_we;
assign rom_bus_cti = shared_cti;
assign rom_bus_bte = shared_bte;
assign sram_bus_adr = shared_adr;
assign sram_bus_dat_w = shared_dat_w;
assign sram_bus_sel = shared_sel;
assign sram_bus_stb = shared_stb;
assign sram_bus_we = shared_we;
assign sram_bus_cti = shared_cti;
assign sram_bus_bte = shared_bte;
assign bus_wishbone_adr = shared_adr;
assign bus_wishbone_dat_w = shared_dat_w;
assign bus_wishbone_sel = shared_sel;
assign bus_wishbone_stb = shared_stb;
assign bus_wishbone_we = shared_we;
assign bus_wishbone_cti = shared_cti;
assign bus_wishbone_bte = shared_bte;
assign rom_bus_cyc = (shared_cyc & slave_sel[0]);
assign sram_bus_cyc = (shared_cyc & slave_sel[1]);
assign bus_wishbone_cyc = (shared_cyc & slave_sel[2]);
assign shared_err = ((rom_bus_err | sram_bus_err) | bus_wishbone_err);
assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
always @(*) begin
shared_ack <= 1'd0;
error <= 1'd0;
shared_dat_r <= 32'd0;
shared_ack <= ((rom_bus_ack | sram_bus_ack) | bus_wishbone_ack);
shared_dat_r <= ((({32{slave_sel_r[0]}} & rom_bus_dat_r) | ({32{slave_sel_r[1]}} & sram_bus_dat_r)) | ({32{slave_sel_r[2]}} & bus_wishbone_dat_r));
if (done) begin
shared_dat_r <= 32'd4294967295;
shared_ack <= 1'd1;
error <= 1'd1;
end
end
assign done = (count == 1'd0);
assign csrbankarray_csrbank0_sel = (csrbankarray_interface0_bank_bus_adr[13:9] == 1'd0);
assign ctrl_reset_reset_r = csrbankarray_interface0_bank_bus_dat_w[0];
assign ctrl_reset_reset_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd0));
assign ctrl_reset_reset_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd0));
assign csrbankarray_csrbank0_scratch3_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch3_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd1));
assign csrbankarray_csrbank0_scratch3_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd1));
assign csrbankarray_csrbank0_scratch2_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch2_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd2));
assign csrbankarray_csrbank0_scratch2_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd2));
assign csrbankarray_csrbank0_scratch1_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch1_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd3));
assign csrbankarray_csrbank0_scratch1_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd3));
assign csrbankarray_csrbank0_scratch0_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch0_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd4));
assign csrbankarray_csrbank0_scratch0_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd4));
assign csrbankarray_csrbank0_bus_errors3_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors3_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd5));
assign csrbankarray_csrbank0_bus_errors3_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd5));
assign csrbankarray_csrbank0_bus_errors2_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors2_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd6));
assign csrbankarray_csrbank0_bus_errors2_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd6));
assign csrbankarray_csrbank0_bus_errors1_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors1_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd7));
assign csrbankarray_csrbank0_bus_errors1_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd7));
assign csrbankarray_csrbank0_bus_errors0_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors0_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 4'd8));
assign csrbankarray_csrbank0_bus_errors0_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 4'd8));
assign csrbankarray_csrbank0_scratch3_w = ctrl_storage[31:24];
assign csrbankarray_csrbank0_scratch2_w = ctrl_storage[23:16];
assign csrbankarray_csrbank0_scratch1_w = ctrl_storage[15:8];
assign csrbankarray_csrbank0_scratch0_w = ctrl_storage[7:0];
assign csrbankarray_csrbank0_bus_errors3_w = ctrl_bus_errors_status[31:24];
assign csrbankarray_csrbank0_bus_errors2_w = ctrl_bus_errors_status[23:16];
assign csrbankarray_csrbank0_bus_errors1_w = ctrl_bus_errors_status[15:8];
assign csrbankarray_csrbank0_bus_errors0_w = ctrl_bus_errors_status[7:0];
assign ctrl_bus_errors_we = csrbankarray_csrbank0_bus_errors0_we;
assign csrbankarray_sel = (csrbankarray_sram_bus_adr[13:9] == 3'd4);
always @(*) begin
csrbankarray_sram_bus_dat_r <= 8'd0;
if (csrbankarray_sel_r) begin
csrbankarray_sram_bus_dat_r <= csrbankarray_dat_r;
end
end
assign csrbankarray_adr = csrbankarray_sram_bus_adr[3:0];
assign csrbankarray_csrbank1_sel = (csrbankarray_interface1_bank_bus_adr[13:9] == 3'd5);
assign csrbankarray_csrbank1_load3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbankarray_csrbank1_load3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbankarray_csrbank1_load2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbankarray_csrbank1_load2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbankarray_csrbank1_load1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbankarray_csrbank1_load1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbankarray_csrbank1_load0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbankarray_csrbank1_load0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbankarray_csrbank1_reload3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbankarray_csrbank1_reload3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbankarray_csrbank1_reload2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbankarray_csrbank1_reload2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbankarray_csrbank1_reload1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbankarray_csrbank1_reload1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbankarray_csrbank1_reload0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbankarray_csrbank1_reload0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbankarray_csrbank1_en0_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign csrbankarray_csrbank1_en0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbankarray_csrbank1_en0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbankarray_csrbank1_update_value0_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign csrbankarray_csrbank1_update_value0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbankarray_csrbank1_update_value0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbankarray_csrbank1_value3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbankarray_csrbank1_value3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbankarray_csrbank1_value2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbankarray_csrbank1_value2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbankarray_csrbank1_value1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbankarray_csrbank1_value1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbankarray_csrbank1_value0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd13));
assign csrbankarray_csrbank1_value0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd13));
assign timer0_eventmanager_status_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign timer0_eventmanager_status_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd14));
assign timer0_eventmanager_status_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd14));
assign timer0_eventmanager_pending_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign timer0_eventmanager_pending_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd15));
assign timer0_eventmanager_pending_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbankarray_csrbank1_ev_enable0_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign csrbankarray_csrbank1_ev_enable0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbankarray_csrbank1_ev_enable0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbankarray_csrbank1_load3_w = timer0_load_storage[31:24];
assign csrbankarray_csrbank1_load2_w = timer0_load_storage[23:16];
assign csrbankarray_csrbank1_load1_w = timer0_load_storage[15:8];
assign csrbankarray_csrbank1_load0_w = timer0_load_storage[7:0];
assign csrbankarray_csrbank1_reload3_w = timer0_reload_storage[31:24];
assign csrbankarray_csrbank1_reload2_w = timer0_reload_storage[23:16];
assign csrbankarray_csrbank1_reload1_w = timer0_reload_storage[15:8];
assign csrbankarray_csrbank1_reload0_w = timer0_reload_storage[7:0];
assign csrbankarray_csrbank1_en0_w = timer0_en_storage;
assign csrbankarray_csrbank1_update_value0_w = timer0_update_value_storage;
assign csrbankarray_csrbank1_value3_w = timer0_value_status[31:24];
assign csrbankarray_csrbank1_value2_w = timer0_value_status[23:16];
assign csrbankarray_csrbank1_value1_w = timer0_value_status[15:8];
assign csrbankarray_csrbank1_value0_w = timer0_value_status[7:0];
assign timer0_value_we = csrbankarray_csrbank1_value0_we;
assign csrbankarray_csrbank1_ev_enable0_w = timer0_eventmanager_storage;
assign csrbankarray_csrbank2_sel = (csrbankarray_interface2_bank_bus_adr[13:9] == 2'd3);
assign uart_rxtx_r = csrbankarray_interface2_bank_bus_dat_w[7:0];
assign uart_rxtx_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
assign uart_rxtx_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
assign csrbankarray_csrbank2_txfull_r = csrbankarray_interface2_bank_bus_dat_w[0];
assign csrbankarray_csrbank2_txfull_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
assign csrbankarray_csrbank2_txfull_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
assign csrbankarray_csrbank2_rxempty_r = csrbankarray_interface2_bank_bus_dat_w[0];
assign csrbankarray_csrbank2_rxempty_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
assign csrbankarray_csrbank2_rxempty_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
assign uart_eventmanager_status_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
assign uart_eventmanager_status_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
assign uart_eventmanager_status_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
assign uart_eventmanager_pending_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
assign uart_eventmanager_pending_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
assign uart_eventmanager_pending_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
assign csrbankarray_csrbank2_ev_enable0_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
assign csrbankarray_csrbank2_ev_enable0_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
assign csrbankarray_csrbank2_ev_enable0_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
assign csrbankarray_csrbank2_txfull_w = uart_txfull_status;
assign uart_txfull_we = csrbankarray_csrbank2_txfull_we;
assign csrbankarray_csrbank2_rxempty_w = uart_rxempty_status;
assign uart_rxempty_we = csrbankarray_csrbank2_rxempty_we;
assign csrbankarray_csrbank2_ev_enable0_w = uart_eventmanager_storage[1:0];
assign csrbankarray_csrbank3_sel = (csrbankarray_interface3_bank_bus_adr[13:9] == 2'd2);
assign csrbankarray_csrbank3_tuning_word3_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word3_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd0));
assign csrbankarray_csrbank3_tuning_word3_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd0));
assign csrbankarray_csrbank3_tuning_word2_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word2_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd1));
assign csrbankarray_csrbank3_tuning_word2_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd1));
assign csrbankarray_csrbank3_tuning_word1_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word1_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd2));
assign csrbankarray_csrbank3_tuning_word1_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd2));
assign csrbankarray_csrbank3_tuning_word0_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word0_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd3));
assign csrbankarray_csrbank3_tuning_word0_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd3));
assign csrbankarray_csrbank3_tuning_word3_w = uart_phy_storage[31:24];
assign csrbankarray_csrbank3_tuning_word2_w = uart_phy_storage[23:16];
assign csrbankarray_csrbank3_tuning_word1_w = uart_phy_storage[15:8];
assign csrbankarray_csrbank3_tuning_word0_w = uart_phy_storage[7:0];
assign csrcon_adr = interface_adr;
assign csrcon_we = interface_we;
assign csrcon_dat_w = interface_dat_w;
assign interface_dat_r = csrcon_dat_r;
assign csrbankarray_interface0_bank_bus_adr = csrcon_adr;
assign csrbankarray_interface1_bank_bus_adr = csrcon_adr;
assign csrbankarray_interface2_bank_bus_adr = csrcon_adr;
assign csrbankarray_interface3_bank_bus_adr = csrcon_adr;
assign csrbankarray_sram_bus_adr = csrcon_adr;
assign csrbankarray_interface0_bank_bus_we = csrcon_we;
assign csrbankarray_interface1_bank_bus_we = csrcon_we;
assign csrbankarray_interface2_bank_bus_we = csrcon_we;
assign csrbankarray_interface3_bank_bus_we = csrcon_we;
assign csrbankarray_sram_bus_we = csrcon_we;
assign csrbankarray_interface0_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_interface1_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_interface2_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_interface3_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_sram_bus_dat_w = csrcon_dat_w;
assign csrcon_dat_r = ((((csrbankarray_interface0_bank_bus_dat_r | csrbankarray_interface1_bank_bus_dat_r) | csrbankarray_interface2_bank_bus_dat_r) | csrbankarray_interface3_bank_bus_dat_r) | csrbankarray_sram_bus_dat_r);
always @(*) begin
array_muxed0 <= 30'd0;
case (grant)
1'd0: begin
array_muxed0 <= interface0_soc_bus_adr;
end
default: begin
array_muxed0 <= interface1_soc_bus_adr;
end
endcase
end
always @(*) begin
array_muxed1 <= 32'd0;
case (grant)
1'd0: begin
array_muxed1 <= interface0_soc_bus_dat_w;
end
default: begin
array_muxed1 <= interface1_soc_bus_dat_w;
end
endcase
end
always @(*) begin
array_muxed2 <= 4'd0;
case (grant)
1'd0: begin
array_muxed2 <= interface0_soc_bus_sel;
end
default: begin
array_muxed2 <= interface1_soc_bus_sel;
end
endcase
end
always @(*) begin
array_muxed3 <= 1'd0;
case (grant)
1'd0: begin
array_muxed3 <= interface0_soc_bus_cyc;
end
default: begin
array_muxed3 <= interface1_soc_bus_cyc;
end
endcase
end
always @(*) begin
array_muxed4 <= 1'd0;
case (grant)
1'd0: begin
array_muxed4 <= interface0_soc_bus_stb;
end
default: begin
array_muxed4 <= interface1_soc_bus_stb;
end
endcase
end
always @(*) begin
array_muxed5 <= 1'd0;
case (grant)
1'd0: begin
array_muxed5 <= interface0_soc_bus_we;
end
default: begin
array_muxed5 <= interface1_soc_bus_we;
end
endcase
end
always @(*) begin
array_muxed6 <= 3'd0;
case (grant)
1'd0: begin
array_muxed6 <= interface0_soc_bus_cti;
end
default: begin
array_muxed6 <= interface1_soc_bus_cti;
end
endcase
end
always @(*) begin
array_muxed7 <= 2'd0;
case (grant)
1'd0: begin
array_muxed7 <= interface0_soc_bus_bte;
end
default: begin
array_muxed7 <= interface1_soc_bus_bte;
end
endcase
end
assign uart_phy_rx = regs1;
assign xilinxasyncresetsynchronizerimpl = ((~locked) | reset);
always @(posedge sys_clk) begin
if ((ctrl_bus_errors != 32'd4294967295)) begin
if (ctrl_bus_error) begin
ctrl_bus_errors <= (ctrl_bus_errors + 1'd1);
end
end
rom_bus_ack <= 1'd0;
if (((rom_bus_cyc & rom_bus_stb) & (~rom_bus_ack))) begin
rom_bus_ack <= 1'd1;
end
sram_bus_ack <= 1'd0;
if (((sram_bus_cyc & sram_bus_stb) & (~sram_bus_ack))) begin
sram_bus_ack <= 1'd1;
end
uart_phy_sink_ready <= 1'd0;
if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin
uart_phy_tx_reg <= uart_phy_sink_payload_data;
uart_phy_tx_bitcount <= 1'd0;
uart_phy_tx_busy <= 1'd1;
serial_tx <= 1'd0;
end else begin
if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin
uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1);
if ((uart_phy_tx_bitcount == 4'd8)) begin
serial_tx <= 1'd1;
end else begin
if ((uart_phy_tx_bitcount == 4'd9)) begin
serial_tx <= 1'd1;
uart_phy_tx_busy <= 1'd0;
uart_phy_sink_ready <= 1'd1;
end else begin
serial_tx <= uart_phy_tx_reg[0];
uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]};
end
end
end
end
if (uart_phy_tx_busy) begin
{uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage);
end else begin
{uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= 1'd0;
end
uart_phy_source_valid <= 1'd0;
uart_phy_rx_r <= uart_phy_rx;
if ((~uart_phy_rx_busy)) begin
if (((~uart_phy_rx) & uart_phy_rx_r)) begin
uart_phy_rx_busy <= 1'd1;
uart_phy_rx_bitcount <= 1'd0;
end
end else begin
if (uart_phy_uart_clk_rxen) begin
uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1);
if ((uart_phy_rx_bitcount == 1'd0)) begin
if (uart_phy_rx) begin
uart_phy_rx_busy <= 1'd0;
end
end else begin
if ((uart_phy_rx_bitcount == 4'd9)) begin
uart_phy_rx_busy <= 1'd0;
if (uart_phy_rx) begin
uart_phy_source_payload_data <= uart_phy_rx_reg;
uart_phy_source_valid <= 1'd1;
end
end else begin
uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]};
end
end
end
end
if (uart_phy_rx_busy) begin
{uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage);
end else begin
{uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648;
end
if (uart_tx_clear) begin
uart_tx_pending <= 1'd0;
end
uart_tx_old_trigger <= uart_tx_trigger;
if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin
uart_tx_pending <= 1'd1;
end
if (uart_rx_clear) begin
uart_rx_pending <= 1'd0;
end
uart_rx_old_trigger <= uart_rx_trigger;
if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin
uart_rx_pending <= 1'd1;
end
if (uart_tx_fifo_syncfifo_re) begin
uart_tx_fifo_readable <= 1'd1;
end else begin
if (uart_tx_fifo_re) begin
uart_tx_fifo_readable <= 1'd0;
end
end
if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
end
if (uart_tx_fifo_do_read) begin
uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
end
if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
if ((~uart_tx_fifo_do_read)) begin
uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (uart_tx_fifo_do_read) begin
uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
end
end
if (uart_rx_fifo_syncfifo_re) begin
uart_rx_fifo_readable <= 1'd1;
end else begin
if (uart_rx_fifo_re) begin
uart_rx_fifo_readable <= 1'd0;
end
end
if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
end
if (uart_rx_fifo_do_read) begin
uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
end
if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
if ((~uart_rx_fifo_do_read)) begin
uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (uart_rx_fifo_do_read) begin
uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
end
end
if (uart_reset) begin
uart_tx_pending <= 1'd0;
uart_tx_old_trigger <= 1'd0;
uart_rx_pending <= 1'd0;
uart_rx_old_trigger <= 1'd0;
uart_tx_fifo_readable <= 1'd0;
uart_tx_fifo_level0 <= 5'd0;
uart_tx_fifo_produce <= 4'd0;
uart_tx_fifo_consume <= 4'd0;
uart_rx_fifo_readable <= 1'd0;
uart_rx_fifo_level0 <= 5'd0;
uart_rx_fifo_produce <= 4'd0;
uart_rx_fifo_consume <= 4'd0;
end
if (timer0_en_storage) begin
if ((timer0_value == 1'd0)) begin
timer0_value <= timer0_reload_storage;
end else begin
timer0_value <= (timer0_value - 1'd1);
end
end else begin
timer0_value <= timer0_load_storage;
end
if (timer0_update_value_re) begin
timer0_value_status <= timer0_value;
end
if (timer0_zero_clear) begin
timer0_zero_pending <= 1'd0;
end
timer0_zero_old_trigger <= timer0_zero_trigger;
if (((~timer0_zero_trigger) & timer0_zero_old_trigger)) begin
timer0_zero_pending <= 1'd1;
end
state <= next_state;
case (grant)
1'd0: begin
if ((~request[0])) begin
if (request[1]) begin
grant <= 1'd1;
end
end
end
1'd1: begin
if ((~request[1])) begin
if (request[0]) begin
grant <= 1'd0;
end
end
end
endcase
slave_sel_r <= slave_sel;
if (wait_1) begin
if ((~done)) begin
count <= (count - 1'd1);
end
end else begin
count <= 20'd1000000;
end
csrbankarray_interface0_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank0_sel) begin
case (csrbankarray_interface0_bank_bus_adr[3:0])
1'd0: begin
csrbankarray_interface0_bank_bus_dat_r <= ctrl_reset_reset_w;
end
1'd1: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch3_w;
end
2'd2: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch2_w;
end
2'd3: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch1_w;
end
3'd4: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch0_w;
end
3'd5: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors3_w;
end
3'd6: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors2_w;
end
3'd7: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors1_w;
end
4'd8: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors0_w;
end
endcase
end
if (csrbankarray_csrbank0_scratch3_re) begin
ctrl_storage[31:24] <= csrbankarray_csrbank0_scratch3_r;
end
if (csrbankarray_csrbank0_scratch2_re) begin
ctrl_storage[23:16] <= csrbankarray_csrbank0_scratch2_r;
end
if (csrbankarray_csrbank0_scratch1_re) begin
ctrl_storage[15:8] <= csrbankarray_csrbank0_scratch1_r;
end
if (csrbankarray_csrbank0_scratch0_re) begin
ctrl_storage[7:0] <= csrbankarray_csrbank0_scratch0_r;
end
ctrl_re <= csrbankarray_csrbank0_scratch0_re;
csrbankarray_sel_r <= csrbankarray_sel;
csrbankarray_interface1_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank1_sel) begin
case (csrbankarray_interface1_bank_bus_adr[4:0])
1'd0: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load3_w;
end
1'd1: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load2_w;
end
2'd2: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load1_w;
end
2'd3: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load0_w;
end
3'd4: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload3_w;
end
3'd5: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload2_w;
end
3'd6: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload1_w;
end
3'd7: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload0_w;
end
4'd8: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_en0_w;
end
4'd9: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_update_value0_w;
end
4'd10: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value3_w;
end
4'd11: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value2_w;
end
4'd12: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value1_w;
end
4'd13: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value0_w;
end
4'd14: begin
csrbankarray_interface1_bank_bus_dat_r <= timer0_eventmanager_status_w;
end
4'd15: begin
csrbankarray_interface1_bank_bus_dat_r <= timer0_eventmanager_pending_w;
end
5'd16: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_ev_enable0_w;
end
endcase
end
if (csrbankarray_csrbank1_load3_re) begin
timer0_load_storage[31:24] <= csrbankarray_csrbank1_load3_r;
end
if (csrbankarray_csrbank1_load2_re) begin
timer0_load_storage[23:16] <= csrbankarray_csrbank1_load2_r;
end
if (csrbankarray_csrbank1_load1_re) begin
timer0_load_storage[15:8] <= csrbankarray_csrbank1_load1_r;
end
if (csrbankarray_csrbank1_load0_re) begin
timer0_load_storage[7:0] <= csrbankarray_csrbank1_load0_r;
end
timer0_load_re <= csrbankarray_csrbank1_load0_re;
if (csrbankarray_csrbank1_reload3_re) begin
timer0_reload_storage[31:24] <= csrbankarray_csrbank1_reload3_r;
end
if (csrbankarray_csrbank1_reload2_re) begin
timer0_reload_storage[23:16] <= csrbankarray_csrbank1_reload2_r;
end
if (csrbankarray_csrbank1_reload1_re) begin
timer0_reload_storage[15:8] <= csrbankarray_csrbank1_reload1_r;
end
if (csrbankarray_csrbank1_reload0_re) begin
timer0_reload_storage[7:0] <= csrbankarray_csrbank1_reload0_r;
end
timer0_reload_re <= csrbankarray_csrbank1_reload0_re;
if (csrbankarray_csrbank1_en0_re) begin
timer0_en_storage <= csrbankarray_csrbank1_en0_r;
end
timer0_en_re <= csrbankarray_csrbank1_en0_re;
if (csrbankarray_csrbank1_update_value0_re) begin
timer0_update_value_storage <= csrbankarray_csrbank1_update_value0_r;
end
timer0_update_value_re <= csrbankarray_csrbank1_update_value0_re;
if (csrbankarray_csrbank1_ev_enable0_re) begin
timer0_eventmanager_storage <= csrbankarray_csrbank1_ev_enable0_r;
end
timer0_eventmanager_re <= csrbankarray_csrbank1_ev_enable0_re;
csrbankarray_interface2_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank2_sel) begin
case (csrbankarray_interface2_bank_bus_adr[2:0])
1'd0: begin
csrbankarray_interface2_bank_bus_dat_r <= uart_rxtx_w;
end
1'd1: begin
csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_txfull_w;
end
2'd2: begin
csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_rxempty_w;
end
2'd3: begin
csrbankarray_interface2_bank_bus_dat_r <= uart_eventmanager_status_w;
end
3'd4: begin
csrbankarray_interface2_bank_bus_dat_r <= uart_eventmanager_pending_w;
end
3'd5: begin
csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_ev_enable0_w;
end
endcase
end
if (csrbankarray_csrbank2_ev_enable0_re) begin
uart_eventmanager_storage[1:0] <= csrbankarray_csrbank2_ev_enable0_r;
end
uart_eventmanager_re <= csrbankarray_csrbank2_ev_enable0_re;
csrbankarray_interface3_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank3_sel) begin
case (csrbankarray_interface3_bank_bus_adr[1:0])
1'd0: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word3_w;
end
1'd1: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word2_w;
end
2'd2: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word1_w;
end
2'd3: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word0_w;
end
endcase
end
if (csrbankarray_csrbank3_tuning_word3_re) begin
uart_phy_storage[31:24] <= csrbankarray_csrbank3_tuning_word3_r;
end
if (csrbankarray_csrbank3_tuning_word2_re) begin
uart_phy_storage[23:16] <= csrbankarray_csrbank3_tuning_word2_r;
end
if (csrbankarray_csrbank3_tuning_word1_re) begin
uart_phy_storage[15:8] <= csrbankarray_csrbank3_tuning_word1_r;
end
if (csrbankarray_csrbank3_tuning_word0_re) begin
uart_phy_storage[7:0] <= csrbankarray_csrbank3_tuning_word0_r;
end
uart_phy_re <= csrbankarray_csrbank3_tuning_word0_re;
if (sys_rst) begin
ctrl_storage <= 32'd305419896;
ctrl_re <= 1'd0;
ctrl_bus_errors <= 32'd0;
rom_bus_ack <= 1'd0;
sram_bus_ack <= 1'd0;
serial_tx <= 1'd1;
uart_phy_storage <= 32'd4947802;
uart_phy_re <= 1'd0;
uart_phy_sink_ready <= 1'd0;
uart_phy_uart_clk_txen <= 1'd0;
uart_phy_phase_accumulator_tx <= 32'd0;
uart_phy_tx_reg <= 8'd0;
uart_phy_tx_bitcount <= 4'd0;
uart_phy_tx_busy <= 1'd0;
uart_phy_source_valid <= 1'd0;
uart_phy_source_payload_data <= 8'd0;
uart_phy_uart_clk_rxen <= 1'd0;
uart_phy_phase_accumulator_rx <= 32'd0;
uart_phy_rx_r <= 1'd0;
uart_phy_rx_reg <= 8'd0;
uart_phy_rx_bitcount <= 4'd0;
uart_phy_rx_busy <= 1'd0;
uart_tx_pending <= 1'd0;
uart_tx_old_trigger <= 1'd0;
uart_rx_pending <= 1'd0;
uart_rx_old_trigger <= 1'd0;
uart_eventmanager_storage <= 2'd0;
uart_eventmanager_re <= 1'd0;
uart_tx_fifo_readable <= 1'd0;
uart_tx_fifo_level0 <= 5'd0;
uart_tx_fifo_produce <= 4'd0;
uart_tx_fifo_consume <= 4'd0;
uart_rx_fifo_readable <= 1'd0;
uart_rx_fifo_level0 <= 5'd0;
uart_rx_fifo_produce <= 4'd0;
uart_rx_fifo_consume <= 4'd0;
timer0_load_storage <= 32'd0;
timer0_load_re <= 1'd0;
timer0_reload_storage <= 32'd0;
timer0_reload_re <= 1'd0;
timer0_en_storage <= 1'd0;
timer0_en_re <= 1'd0;
timer0_update_value_storage <= 1'd0;
timer0_update_value_re <= 1'd0;
timer0_value_status <= 32'd0;
timer0_zero_pending <= 1'd0;
timer0_zero_old_trigger <= 1'd0;
timer0_eventmanager_storage <= 1'd0;
timer0_eventmanager_re <= 1'd0;
timer0_value <= 32'd0;
state <= 1'd0;
grant <= 1'd0;
slave_sel_r <= 3'd0;
count <= 20'd1000000;
csrbankarray_interface0_bank_bus_dat_r <= 8'd0;
csrbankarray_sel_r <= 1'd0;
csrbankarray_interface1_bank_bus_dat_r <= 8'd0;
csrbankarray_interface2_bank_bus_dat_r <= 8'd0;
csrbankarray_interface3_bank_bus_dat_r <= 8'd0;
end
regs0 <= serial_rx;
regs1 <= regs0;
end
reg [31:0] mem[0:8191];
reg [31:0] memdat;
always @(posedge sys_clk) begin
memdat <= mem[rom_adr];
end
assign rom_dat_r = memdat;
initial begin
$readmemh("mem.init", mem);
end
reg [31:0] mem_1[0:8191];
reg [12:0] memadr;
always @(posedge sys_clk) begin
if (sram_we[0])
mem_1[sram_adr][7:0] <= sram_dat_w[7:0];
if (sram_we[1])
mem_1[sram_adr][15:8] <= sram_dat_w[15:8];
if (sram_we[2])
mem_1[sram_adr][23:16] <= sram_dat_w[23:16];
if (sram_we[3])
mem_1[sram_adr][31:24] <= sram_dat_w[31:24];
memadr <= sram_adr;
end
assign sram_dat_r = mem_1[memadr];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [9:0] storage[0:15];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
if (uart_tx_fifo_wrport_we)
storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
memdat_1 <= storage[uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (uart_tx_fifo_rdport_re)
memdat_2 <= storage[uart_tx_fifo_rdport_adr];
end
assign uart_tx_fifo_wrport_dat_r = memdat_1;
assign uart_tx_fifo_rdport_dat_r = memdat_2;
reg [9:0] storage_1[0:15];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
if (uart_rx_fifo_wrport_we)
storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
memdat_3 <= storage_1[uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (uart_rx_fifo_rdport_re)
memdat_4 <= storage_1[uart_rx_fifo_rdport_adr];
end
assign uart_rx_fifo_wrport_dat_r = memdat_3;
assign uart_rx_fifo_rdport_dat_r = memdat_4;
reg [7:0] mem_2[0:9];
reg [3:0] memadr_1;
always @(posedge sys_clk) begin
memadr_1 <= csrbankarray_adr;
end
assign csrbankarray_dat_r = mem_2[memadr_1];
initial begin
$readmemh("mem_2.init", mem_2);
end
BUFG BUFG_OUT(
.I(clkout),
.O(clkout_buf)
);
VexRiscv VexRiscv(
.clk(sys_clk),
.dBusWishbone_ACK(vexriscv_dbus_ack),
.dBusWishbone_DAT_MISO(vexriscv_dbus_dat_r),
.dBusWishbone_ERR(vexriscv_dbus_err),
.externalInterruptArray(vexriscv_interrupt),
.externalResetVector(1'd0),
.iBusWishbone_ACK(vexriscv_ibus_ack),
.iBusWishbone_DAT_MISO(vexriscv_ibus_dat_r),
.iBusWishbone_ERR(vexriscv_ibus_err),
.reset((sys_rst | vexriscv_reset)),
.softwareInterrupt(1'd0),
.timerInterrupt(1'd0),
.dBusWishbone_ADR(vexriscv_dbus_adr),
.dBusWishbone_BTE(vexriscv_dbus_bte),
.dBusWishbone_CTI(vexriscv_dbus_cti),
.dBusWishbone_CYC(vexriscv_dbus_cyc),
.dBusWishbone_DAT_MOSI(vexriscv_dbus_dat_w),
.dBusWishbone_SEL(vexriscv_dbus_sel),
.dBusWishbone_STB(vexriscv_dbus_stb),
.dBusWishbone_WE(vexriscv_dbus_we),
.iBusWishbone_ADR(vexriscv_ibus_adr),
.iBusWishbone_BTE(vexriscv_ibus_bte),
.iBusWishbone_CTI(vexriscv_ibus_cti),
.iBusWishbone_CYC(vexriscv_ibus_cyc),
.iBusWishbone_DAT_MOSI(vexriscv_ibus_dat_w),
.iBusWishbone_SEL(vexriscv_ibus_sel),
.iBusWishbone_STB(vexriscv_ibus_stb),
.iBusWishbone_WE(vexriscv_ibus_we)
);
BUFG BUFG_IN(
.I(clk100),
.O(clkin)
);
PLLE2_ADV #(
.CLKFBOUT_MULT(5'd16),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(5'd16),
.CLKOUT0_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(pll_fb),
.CLKIN1(clkin),
.CLKFBOUT(pll_fb),
.CLKOUT0(clkout),
.LOCKED(locked)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
.C(sys_clk),
.CE(1'd1),
.D(1'd0),
.PRE(xilinxasyncresetsynchronizerimpl),
.Q(xilinxasyncresetsynchronizerimpl_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(sys_clk),
.CE(1'd1),
.D(xilinxasyncresetsynchronizerimpl_rst_meta),
.PRE(xilinxasyncresetsynchronizerimpl),
.Q(sys_rst)
);
endmodule |
module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v2_0_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v2_0_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v2_0_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule |
module PLLE2_BASE_tb();
wire CLKOUT[0:5];
wire CLKFBOUT;
wire LOCKED;
reg CLKIN1;
reg PWRDWN;
reg RST;
wire CLKFBIN;
integer pass_count;
integer fail_count;
/* change according to the number of test cases */
localparam total = 23;
reg reset;
wire [31:0] period_1000[0:5];
wire [31:0] period_1000_fb;
wire dcc_fail[0:5];
wire dcc_fail_fb;
wire psc_fail[0:5];
wire psc_fail_fb;
wire [31:0] CLKOUT_DIVIDE[0:5];
assign CLKOUT_DIVIDE[0] = `CLKOUT0_DIVIDE;
assign CLKOUT_DIVIDE[1] = `CLKOUT1_DIVIDE;
assign CLKOUT_DIVIDE[2] = `CLKOUT2_DIVIDE;
assign CLKOUT_DIVIDE[3] = `CLKOUT3_DIVIDE;
assign CLKOUT_DIVIDE[4] = `CLKOUT4_DIVIDE;
assign CLKOUT_DIVIDE[5] = `CLKOUT5_DIVIDE;
wire [31:0] CLKOUT_DUTY_CYCLE_1000[0:5];
assign CLKOUT_DUTY_CYCLE_1000[0] = (`CLKOUT0_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[1] = (`CLKOUT1_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[2] = (`CLKOUT2_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[3] = (`CLKOUT3_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[4] = (`CLKOUT4_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[5] = (`CLKOUT5_DUTY_CYCLE * 1000);
wire [31:0] CLKOUT_PHASE_1000[0:5];
assign CLKOUT_PHASE_1000[0] = (`CLKOUT0_PHASE * 1000);
assign CLKOUT_PHASE_1000[1] = (`CLKOUT1_PHASE * 1000);
assign CLKOUT_PHASE_1000[2] = (`CLKOUT2_PHASE * 1000);
assign CLKOUT_PHASE_1000[3] = (`CLKOUT3_PHASE * 1000);
assign CLKOUT_PHASE_1000[4] = (`CLKOUT4_PHASE * 1000);
assign CLKOUT_PHASE_1000[5] = (`CLKOUT5_PHASE * 1000);
/* instantiate PLLE2_BASE with default values for all the attributes */
PLLE2_BASE #(
.BANDWIDTH(`BANDWIDTH),
.CLKFBOUT_MULT(`CLKFBOUT_MULT),
.CLKFBOUT_PHASE(`CLKFBOUT_PHASE),
.CLKIN1_PERIOD(`CLKIN1_PERIOD),
.CLKOUT0_DIVIDE(`CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE(`CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(`CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(`CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(`CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(`CLKOUT5_DIVIDE),
.CLKOUT0_DUTY_CYCLE(`CLKOUT0_DUTY_CYCLE),
.CLKOUT1_DUTY_CYCLE(`CLKOUT1_DUTY_CYCLE),
.CLKOUT2_DUTY_CYCLE(`CLKOUT2_DUTY_CYCLE),
.CLKOUT3_DUTY_CYCLE(`CLKOUT3_DUTY_CYCLE),
.CLKOUT4_DUTY_CYCLE(`CLKOUT4_DUTY_CYCLE),
.CLKOUT5_DUTY_CYCLE(`CLKOUT5_DUTY_CYCLE),
.CLKOUT0_PHASE(`CLKOUT0_PHASE),
.CLKOUT1_PHASE(`CLKOUT1_PHASE),
.CLKOUT2_PHASE(`CLKOUT2_PHASE),
.CLKOUT3_PHASE(`CLKOUT3_PHASE),
.CLKOUT4_PHASE(`CLKOUT4_PHASE),
.CLKOUT5_PHASE(`CLKOUT5_PHASE),
.DIVCLK_DIVIDE(`DIVCLK_DIVIDE),
.REF_JITTER1(`REF_JITTER1),
.STARTUP_WAIT(`STARTUP_WAIT))
dut (
.CLKOUT0(CLKOUT[0]),
.CLKOUT1(CLKOUT[1]),
.CLKOUT2(CLKOUT[2]),
.CLKOUT3(CLKOUT[3]),
.CLKOUT4(CLKOUT[4]),
.CLKOUT5(CLKOUT[5]),
.CLKFBOUT(CLKFBOUT),
.LOCKED(LOCKED),
.CLKIN1(CLKIN1),
.PWRDWN(PWRDWN),
.RST(RST),
.CLKFBIN(CLKFBIN)
);
genvar i;
generate
for (i = 0; i <= 5; i = i + 1) begin : period_count
period_count period_count (
.RST(reset),
.clk(CLKOUT[i]),
.period_length_1000(period_1000[i]));
end
for (i = 0; i <= 5; i = i + 1) begin : dcc
duty_cycle_check dcc (
.desired_duty_cycle_1000(CLKOUT_DUTY_CYCLE_1000[i]),
.clk_period_1000((`CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * CLKOUT_DIVIDE[i]) / `CLKFBOUT_MULT)) * 1000),
.clk(CLKOUT[i]),
.reset(reset),
.LOCKED(LOCKED),
.fail(dcc_fail[i]));
end
for (i = 0; i <= 5; i = i + 1) begin : psc
phase_shift_check psc (
.desired_shift_1000(CLKOUT_PHASE_1000[i]),
.clk_period_1000(1000 * `CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * CLKOUT_DIVIDE[i]) / `CLKFBOUT_MULT)),
.clk_shifted(CLKOUT[i]),
.clk(CLKFBOUT),
.rst(RST),
.LOCKED(LOCKED),
.fail(psc_fail[i]));
end
endgenerate
period_count period_count_fb (
.RST(reset),
.clk(CLKFBOUT),
.period_length_1000(period_1000_fb));
phase_shift_check pscfb (
.desired_shift_1000(`CLKFBOUT_PHASE * 1000),
.clk_period_1000(`CLKIN1_PERIOD * (`DIVCLK_DIVIDE / `CLKFBOUT_MULT) * 1000),
.clk_shifted(CLKFBOUT),
.clk(CLKIN1),
.rst(RST),
.LOCKED(LOCKED),
.fail(psc_fail_fb));
/* ------------ BEGIN TEST CASES ------------- */
/* default loop variable */
integer k;
initial begin
$dumpfile("plle2_base_tb.vcd");
$dumpvars(0, PLLE2_BASE_tb);
pass_count = 0;
fail_count = 0;
reset = 0;
CLKIN1 = 0;
RST = 0;
PWRDWN = 0;
#10;
reset = 1;
RST = 1;
#10;
if ((CLKOUT[0] & CLKOUT[1] & CLKOUT[2] & CLKOUT[3] & CLKOUT[4] & CLKOUT[5] & CLKFBOUT & LOCKED) == 0) begin
$display("PASSED: RST signal");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST signal");
fail_count = fail_count + 1;
end
reset = 0;
RST = 0;
/* Test for correct number of highs for the given parameters.
* This is down for all six outputs and the feedback output.
*/
#`WAIT_INTERVAL;
if (LOCKED === 1'b1) begin
$display("PASSED: LOCKED");
pass_count = pass_count + 1;
end else begin
$display("FAILED: LOCKED");
fail_count = fail_count + 1;
end
/*------- FREQUENCY ---------*/
for (k = 0; k <= 5; k = k + 1) begin
if ((period_1000[k] / 1000.0 == `CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * CLKOUT_DIVIDE[k] * 1.0) / `CLKFBOUT_MULT))) begin
$display("PASSED: CLKOUT%0d frequency", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d frequency", k);
fail_count = fail_count + 1;
end
end
if ((period_1000_fb / 1000.0) == (`CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * 1.0) / `CLKFBOUT_MULT))) begin
$display("PASSED: CLKFBOUT frequency");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT frequency");
fail_count = fail_count + 1;
end
/*------- DUTY CYCLE ---------*/
for (k = 0; k <= 5; k = k + 1) begin
if (dcc_fail[k] !== 1'b1) begin
$display("PASSED: CLKOUT%0d duty cycle", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d duty cycle", k);
fail_count = fail_count + 1;
end
end
/*------- PHASE SHIFT ---------*/
for (k = 0; k <= 5; k = k + 1) begin
if (psc_fail[k] !== 1'b1) begin
$display("PASSED: CLKOUT%0d phase shift", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d phase shift", k);
fail_count = fail_count + 1;
end
end
if (psc_fail_fb !== 1'b1) begin
$display("PASSED: CLKOUTFB phase shift");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUTFB phase shift");
fail_count = fail_count + 1;
end
PWRDWN = 1;
#100;
if ((CLKOUT[0] & CLKOUT[1] & CLKOUT[2] & CLKOUT[3] & CLKOUT[4] & CLKOUT[5] & CLKFBOUT) === 1'bx) begin
$display("PASSED: PWRDWN");
pass_count = pass_count + 1;
end else begin
$display("FAILED: PWRDWN");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
/* connect CLKFBIN with CLKFBOUT to use internal feedback */
assign CLKFBIN = CLKFBOUT;
always #(`CLKIN1_PERIOD / 2) CLKIN1 = ~CLKIN1;
endmodule |
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
endmodule |
module nios_solo_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [31:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [29:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_solo_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule |
module is regenerated
parameter ENABLE_ALT_RECONFIG = 1;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [0:0] reconfig_fromgxb = sub_wire2[0:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
alt2gxb alt2gxb_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.rx_seriallpbken (rx_seriallpbken),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.tx_ctrlenable (tx_ctrlenable),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16)
// synopsys translate_off
,
.aeq_fromgxb (),
.aeq_togxb (),
.cal_blk_calibrationstatus (),
.cal_blk_powerdown (),
.coreclkout (),
.debug_rx_phase_comp_fifo_error (),
.debug_tx_phase_comp_fifo_error (),
.fixedclk (),
.gxb_enable (),
.pipe8b10binvpolarity (),
.pipedatavalid (),
.pipeelecidle (),
.pipephydonestatus (),
.pipestatus (),
.pll_inclk_alt (),
.pll_inclk_rx_cruclk (),
.pll_locked_alt (),
.powerdn (),
.reconfig_fromgxb_oe (),
.rx_a1a2size (),
.rx_a1a2sizeout (),
.rx_a1detect (),
.rx_a2detect (),
.rx_bistdone (),
.rx_bisterr (),
.rx_bitslip (),
.rx_byteorderalignstatus (),
.rx_channelaligned (),
.rx_coreclk (),
.rx_cruclk_alt (),
.rx_dataoutfull (),
.rx_enabyteord (),
.rx_enapatternalign (),
.rx_invpolarity (),
.rx_k1detect (),
.rx_k2detect (),
.rx_locktodata (),
.rx_locktorefclk (),
.rx_phfifooverflow (),
.rx_phfifordenable (),
.rx_phfiforeset (),
.rx_phfifounderflow (),
.rx_phfifowrdisable (),
.rx_pll_locked (),
.rx_powerdown (),
.rx_revbitorderwa (),
.rx_revbyteorderwa (),
.rx_rmfifoalmostempty (),
.rx_rmfifoalmostfull (),
.rx_rmfifoempty (),
.rx_rmfifofull (),
.rx_rmfifordena (),
.rx_rmfiforeset (),
.rx_rmfifowrena (),
.rx_signaldetect (),
.tx_coreclk (),
.tx_datainfull (),
.tx_detectrxloop (),
.tx_dispval (),
.tx_forcedisp (),
.tx_forcedispcompliance (),
.tx_forceelecidle (),
.tx_invpolarity (),
.tx_phfifooverflow (),
.tx_phfiforeset (),
.tx_phfifounderflow (),
.tx_revparallellpbken ()
// synopsys translate_on
);
defparam
alt2gxb_component.starting_channel_number = starting_channel_number,
alt2gxb_component.cmu_pll_inclock_period = 8000,
alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
alt2gxb_component.digitalreset_port_width = 1,
alt2gxb_component.en_local_clk_div_ctrl = "true",
alt2gxb_component.equalizer_ctrl_a_setting = 0,
alt2gxb_component.equalizer_ctrl_b_setting = 0,
alt2gxb_component.equalizer_ctrl_c_setting = 0,
alt2gxb_component.equalizer_ctrl_d_setting = 0,
alt2gxb_component.equalizer_ctrl_v_setting = 0,
alt2gxb_component.equalizer_dcgain_setting = 0,
alt2gxb_component.gen_reconfig_pll = "false",
alt2gxb_component.intended_device_family = "Stratix II GX",
alt2gxb_component.loopback_mode = "slb",
alt2gxb_component.lpm_type = "alt2gxb",
alt2gxb_component.number_of_channels = 1,
alt2gxb_component.operation_mode = "duplex",
alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
alt2gxb_component.protocol = "gige",
alt2gxb_component.receiver_termination = "oct_100_ohms",
alt2gxb_component.reconfig_dprio_mode = ENABLE_ALT_RECONFIG,
alt2gxb_component.reverse_loopback_mode = "none",
alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
alt2gxb_component.rx_8b_10b_mode = "normal",
alt2gxb_component.rx_align_pattern = "0101111100",
alt2gxb_component.rx_align_pattern_length = 10,
alt2gxb_component.rx_allow_align_polarity_inversion = "false",
alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
alt2gxb_component.rx_bandwidth_mode = 1,
alt2gxb_component.rx_bitslip_enable = "false",
alt2gxb_component.rx_byte_ordering_mode = "none",
alt2gxb_component.rx_channel_width = 8,
alt2gxb_component.rx_common_mode = "0.9v",
alt2gxb_component.rx_cru_inclock_period = 8000,
alt2gxb_component.rx_cru_pre_divide_by = 1,
alt2gxb_component.rx_datapath_protocol = "basic",
alt2gxb_component.rx_data_rate = 1250,
alt2gxb_component.rx_data_rate_remainder = 0,
alt2gxb_component.rx_disable_auto_idle_insertion = "true",
alt2gxb_component.rx_enable_bit_reversal = "false",
alt2gxb_component.rx_enable_lock_to_data_sig = "false",
alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
alt2gxb_component.rx_enable_self_test_mode = "false",
alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
alt2gxb_component.rx_force_signal_detect = "true",
alt2gxb_component.rx_ppmselect = 32,
alt2gxb_component.rx_rate_match_back_to_back = "true",
alt2gxb_component.rx_rate_match_fifo_mode = "normal",
alt2gxb_component.rx_rate_match_fifo_mode_manual_control = "none",
alt2gxb_component.rx_rate_match_ordered_set_based = "true",
alt2gxb_component.rx_rate_match_pattern1 = "10100010010101111100",
alt2gxb_component.rx_rate_match_pattern2 = "10101011011010000011",
alt2gxb_component.rx_rate_match_pattern_size = 20,
alt2gxb_component.rx_rate_match_skip_set_based = "true",
alt2gxb_component.rx_run_length = 5,
alt2gxb_component.rx_run_length_enable = "true",
alt2gxb_component.rx_signal_detect_threshold = 2,
alt2gxb_component.rx_use_align_state_machine = "true",
alt2gxb_component.rx_use_clkout = "true",
alt2gxb_component.rx_use_coreclk = "false",
alt2gxb_component.rx_use_cruclk = "true",
alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
alt2gxb_component.rx_use_deskew_fifo = "false",
alt2gxb_component.rx_use_double_data_mode = "false",
alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
alt2gxb_component.transmitter_termination = "oct_100_ohms",
alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
alt2gxb_component.tx_8b_10b_mode = "normal",
alt2gxb_component.tx_allow_polarity_inversion = "false",
alt2gxb_component.tx_analog_power = "1.5v",
alt2gxb_component.tx_channel_width = 8,
alt2gxb_component.tx_common_mode = "0.6v",
alt2gxb_component.tx_data_rate = 1250,
alt2gxb_component.tx_data_rate_remainder = 0,
alt2gxb_component.tx_enable_bit_reversal = "false",
alt2gxb_component.tx_enable_idle_selection = "true",
alt2gxb_component.tx_enable_self_test_mode = "false",
alt2gxb_component.tx_refclk_divide_by = 1,
alt2gxb_component.tx_transmit_protocol = "basic",
alt2gxb_component.tx_use_coreclk = "false",
alt2gxb_component.tx_use_double_data_mode = "false",
alt2gxb_component.tx_use_serializer_double_data_mode = "false",
alt2gxb_component.use_calibration_block = "true",
alt2gxb_component.vod_ctrl_setting = 3;
endmodule |
module srl_init_tester #
(
parameter [255:0] PATTERN = 256'hFE1AB3FE7610D3D205D9A526C103C40F6477E986F53C53FA663A9CE45E851D30,
parameter SRL_LENGTH = 32
)
(
input wire clk,
input wire rst,
input wire ce,
output reg srl_sh,
output wire [SRL_BITS-1:0] srl_a,
output wire srl_d,
input wire srl_q,
output reg error
);
// ============================================================================
// ROM
wire [7:0] rom_adr;
wire rom_dat;
ROM #(.CONTENT(PATTERN)) rom
(
.clk (clk),
.adr (rom_adr),
.dat (rom_dat)
);
// ============================================================================
// Control
localparam SRL_BITS = $clog2(SRL_LENGTH);
// Bit counter
reg[SRL_BITS-1:0] bit_cnt;
always @(posedge clk)
if (rst)
bit_cnt <= SRL_LENGTH - 1;
else if (ce)
bit_cnt <= bit_cnt - 1;
// Data readout
assign rom_adr = bit_cnt;
// SRL32 control
assign srl_a = SRL_LENGTH - 1;
assign srl_d = srl_q;
initial srl_sh <= 1'b0;
always @(posedge clk)
srl_sh <= ce & !rst;
// Error check
initial error <= 1'b0;
always @(posedge clk)
if (rst)
error <= 1'b0;
else if(ce)
error <= rom_dat ^ srl_q;
endmodule |
module sync_gray #(
// Bit-width of the counter
parameter DATA_WIDTH = 1,
// Whether the input and output clock are asynchronous, if set to 0 the
// synchronizer will be bypassed and out_count will be in_count.
parameter ASYNC_CLK = 1)(
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count);
generate if (ASYNC_CLK == 1) begin
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = out_count_m;
end else begin
assign out_count = in_count;
end endgenerate
endmodule |
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_ORI_BURST_SIZE_H (100),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (120),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_TRANS_LOCK (106),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_ORI_BURST_SIZE_H (136),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule |
module sky130_fd_sc_hs__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule |
module dmac_src_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input eot,
input en,
input [C_DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
input fifo_ready,
output fifo_valid,
output [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
reg valid = 1'b0;
wire ready;
reg [C_DATA_WIDTH-1:0] buffer = 'h00;
reg buffer_sync = 1'b0;
reg needs_sync = 1'b0;
wire has_sync = ~needs_sync | buffer_sync;
wire sync_valid = valid & has_sync;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (ready && valid && buffer_sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
valid <= 1'b0;
overflow <= 1'b0;
end else begin
if (enable) begin
if (en) begin
buffer <= din;
buffer_sync <= sync;
valid <= 1'b1;
end else if (ready) begin
valid <= 1'b0;
end
overflow <= en & valid & ~ready;
end else begin
if (ready)
valid <= 1'b0;
overflow <= en;
end
end
end
assign sync_id_ret = sync_id;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(buffer),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
);
endmodule |
module jserialaddertb;
wire [3:0]y;
wire carryout,isValid;
wire currentsum, currentcarryout;
wire [1:0]currentbitcount;
reg clk, rst;
reg a,b,carryin;
reg [3:0]A,B;// temporary variables to ease the testing
integer timeLapsed;
integer i;
jserialadder jsa(y,carryout,isValid,currentsum,currentcarryout,currentbitcount,clk,rst,a,b,carryin);
//always #5 clk = ~clk;// THIS can NOT be done as we have to control the inputs with the clock
initial
begin
// The general concept of testing is to put the block of statement within the clock change
$display("INITIALIZING");
timeLapsed = 0;
i = 0;
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// First time initialization
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("\nTESTING");
$display("RSLT\tTIME(ns)\ta A\tb B\tCYIN\t\tCYOUT\tSUM\tISVALID\t\tBITT\tCCRY\tCSUM");
//$display("NEXT Reset");
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 5; B =5; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 0 ) && (y === 10))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 10; B = 5; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 0 ) && (y === 15))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 6; B = 10; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 1 ) && (y === 0))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 15; B = 15; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 1 ) && (y === 14))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
end
endmodule |
module jserialaddlabtb;
reg clk, reset, a, b;
wire sum, carry, cout;
wire [2:0] count;
wire [3:0] so;
jserialaddlab jslab(a,b,clk,reset,sum,carry,cout,count,so);
initial
begin
clk=1;reset=1;
a=0; b=0;
#10;
reset=0;
// Now send a = 0101 and b = 1010
a=1;b=0;
#10;
a=0;b=1;
#10;
a=1;b=0;
#10;
a=0;b=1;
#10;
// After four cycles the reset should be out
// check for 5 + 10 = 15 i.e. y = 1111 and carry = 0
// Now send a = 0100 and b = 0110
a=0;b=0;
#10
a=0;b=1;
#10;
a=1;b=1;
#10
a=0;b=0;
#10;
// After four cycles the reset should be out
// check for 4 + 6 = 10 i.e. y = 1010 and carry = 0
#100;
#10;
// why would the above line not break
#10;
end
always #5 clk=~clk;
always @(posedge clk)
begin
if(count == 3'b100)
$display("The carry and sum are = %d %d", carry, so);
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule |
module sky130_fd_sc_ms__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module DATA_PHYSICAL(
input wire SD_CLK,
input wire RESET_L,
input wire strobe_IN_DATA_Phy,
input wire ack_IN_DATA_Phy,
input wire [15:0] timeout_Reg_DATA_Phy,
input wire [3:0] blocks_DATA_Phy,
input wire writeRead_DATA_Phy,
input wire multiple_DATA_Phy,
input wire idle_in_DATA_Phy,
input wire transmission_complete_PS_Phy,
input wire reception_complete_SP_Phy,
input wire [31:0] data_read_SP_Phy,
input wire [31:0] dataFromFIFO_FIFO_Phy,
output reg serial_Ready_Phy_DATA,
output reg complete_Phy_DATA,
output reg ack_OUT_Phy_DATA,
output reg data_timeout_Phy_DATA,
output reg reset_Wrapper_Phy_PS,
output reg enable_pts_Wrapper_Phy_PS,
output reg enable_stp_Wrapper_Phy_SP,
output reg [31:0] dataParallel_Phy_PS,
output reg pad_state_Phy_PAD,
output reg pad_enable_Phy_PAD,
output reg writeFIFO_enable_Phy_FIFO,
output reg readFIFO_enable_Phy_FIFO,
output reg [31:0] dataReadToFIFO_Phy_FIFO,
output reg IO_enable_Phy_SD_CARD
);
//Definición y condificación de estados one-hot
parameter RESET = 11'b00000000001;
parameter IDLE = 11'b00000000010;
parameter FIFO_READ = 11'b00000000100;
parameter LOAD_WRITE = 11'b00000001000;
parameter SEND = 11'b00000010000;
parameter WAIT_RESPONSE = 11'b00000100000;
parameter READ = 11'b00001000000;
parameter READ_FIFO_WRITE = 11'b00010000000;
parameter READ_WRAPPER_RESET = 11'b00100000000;
parameter WAIT_ACK = 11'b01000000000;
parameter SEND_ACK = 11'b10000000000;
//registros internos de interés
reg [15:0] timeout_input;
reg [3:0] blocks;
reg [10:0] STATE;
reg [10:0] NEXT_STATE;
//Inicializar, en el estado IDLE, los contadores para timeout_Reg_DATA_Phy y bloques
//timeout_input es el contador para el timeout_Reg_DATA_Phy;
//blocks es el contador para blocks_DATA_Phy;
//NEXT_STATE logic (always_ff)
always @ (posedge SD_CLK)
begin
if (!RESET_L)
begin
STATE <= RESET;
end
else
begin
STATE <= NEXT_STATE;
end
end
//--------------------------------
//CURRENT_STATE logic (always comb)
always @ (*)
begin
case (STATE)
RESET:
begin
//se ponen todas las salidas a 0 excepto reset_Wrapper_Phy_PS
serial_Ready_Phy_DATA = 0;
complete_Phy_DATA = 0;
ack_OUT_Phy_DATA = 0;
data_timeout_Phy_DATA = 0;
reset_Wrapper_Phy_PS = 1; //solo esta en 1 porque el wrapper se resetea en 0
enable_pts_Wrapper_Phy_PS = 0;
enable_stp_Wrapper_Phy_SP = 0;
dataParallel_Phy_PS = 32'b0;
pad_state_Phy_PAD = 0;
pad_enable_Phy_PAD = 0;
writeFIFO_enable_Phy_FIFO = 0;
readFIFO_enable_Phy_FIFO = 0;
dataReadToFIFO_Phy_FIFO = 32'b0;
IO_enable_Phy_SD_CARD = 0; //por default el host recibe datos desde la tarjeta SD
//avanza automaticamente a IDLE
NEXT_STATE = IDLE;
end
//------------------------------
IDLE:
begin
// estado por defecto en caso de interrupcion
// afirma la salida serial_Ready_Phy_DATA
serial_Ready_Phy_DATA = 1;
//reiniciar blocks_DATA_Phy y timeout_Reg_DATA_Phy
blocks = 4'b0;
timeout_input = 16'b0;
if (strobe_IN_DATA_Phy && writeRead_DATA_Phy)
begin
NEXT_STATE = FIFO_READ;
end
else
begin
NEXT_STATE = READ;
end
end
//-------------------------------
FIFO_READ:
begin
//se afirma writeFIFO_enable_Phy_FIFO
writeFIFO_enable_Phy_FIFO = 1;
dataParallel_Phy_PS = dataFromFIFO_FIFO_Phy;
//se avanza al estado LOAD_WRITE
NEXT_STATE = LOAD_WRITE;
end
//--------------------------------
LOAD_WRITE:
begin
//se carga al convertidor PS los datos que venían del FIFO mediante la
//combinación de señales:
enable_pts_Wrapper_Phy_PS = 1;
IO_enable_Phy_SD_CARD = 0;
pad_state_Phy_PAD = 1;
pad_enable_Phy_PAD = 1;
//se avanza al estado SEND
NEXT_STATE = SEND;
end
//---------------------------------
SEND:
begin
//avisar al hardware que se entregarán datos
IO_enable_Phy_SD_CARD = 1;
//se avanza al estado WAIT_RESPONSE
NEXT_STATE = WAIT_RESPONSE;
end
//---------------------------------
WAIT_RESPONSE:
begin
//desabilitar convertidor PS
enable_pts_Wrapper_Phy_PS = 0;
//habilitar el convertidor SP
enable_stp_Wrapper_Phy_SP = 1;
//preparar el PAD para su uso
pad_state_Phy_PAD = 0;
//comienza la cuenta de timeout_input y genera interrupcion si se pasa
timeout_input = timeout_input + 1;
if (timeout_input == timeout_Reg_DATA_Phy)
begin
data_timeout_Phy_DATA = 1;
end
else
begin
data_timeout_Phy_DATA = 0;
end
if (reception_complete_SP_Phy)
begin
//se incrementa en 1 los bloques transmitidos
blocks = blocks + 1;
//y se decide el estado
if (!multiple_DATA_Phy || (blocks==blocks_DATA_Phy))
begin
NEXT_STATE = WAIT_ACK;
end
else
begin
//continúa la transmisión del siguiente bloque
NEXT_STATE = FIFO_READ;
end
end
else
begin
NEXT_STATE = WAIT_RESPONSE;
end
end
//-----------------------------------
READ:
begin
//se afirma la señal pad_enable_Phy_PAD
pad_enable_Phy_PAD = 1;
//pad_state_Phy_PAD se pone en bajo para usarlo como entrada
pad_state_Phy_PAD = 0;
//habilitar convertidad SP
enable_stp_Wrapper_Phy_SP = 1;
//se realiza una cuenta de timeout
timeout_input = timeout_input + 1;
//genera interrupcion si se pasa
if (timeout_input == timeout_Reg_DATA_Phy)
begin
data_timeout_Phy_DATA = 1;
end
else
begin
data_timeout_Phy_DATA = 0;
end
//revisar si la transmisión está completa
if (reception_complete_SP_Phy)
begin
//se incrementa en 1 los bloques transmitidos
blocks = blocks + 1;
NEXT_STATE = READ_FIFO_WRITE;
end
else
begin
NEXT_STATE = READ;
end
end
//------------------------------------
READ_FIFO_WRITE:
begin
//afirma la señal readFIFO_enable_Phy_FIFO
readFIFO_enable_Phy_FIFO = 1;
//se coloca la salida dataReadToFIFO_Phy_FIFO en data_read_SP_Phy
dataReadToFIFO_Phy_FIFO = data_read_SP_Phy;
//se desabilita el convertidor SP
enable_stp_Wrapper_Phy_SP = 0;
if ((blocks == blocks_DATA_Phy) || !multiple_DATA_Phy)
begin
NEXT_STATE = WAIT_ACK;
end
else
begin
NEXT_STATE = READ_WRAPPER_RESET;
end
end
//------------------------------------
READ_WRAPPER_RESET:
begin
//reiniciar los wrappers
reset_Wrapper_Phy_PS = 1;
NEXT_STATE = READ;
end
//------------------------------------
WAIT_ACK:
begin
//afirma la señal complete_Phy_DATA para indicar que se terminó la transacción de DATA
complete_Phy_DATA = 1;
if (ack_IN_DATA_Phy)
begin
NEXT_STATE = SEND_ACK;
end
else
begin
NEXT_STATE = WAIT_ACK;
end
end
//-------------------------------------
SEND_ACK:
begin
//afirma la señal ack_OUT_Phy_DATA para reconocer que se recibió ack_IN_DATA_Phy por parte del CONTROLADOR DATA
ack_OUT_Phy_DATA = 1;
NEXT_STATE = IDLE;
end
//-------------------------------------
default:
begin
NEXT_STATE = IDLE; //estado por defecto
end
endcase
end //always
endmodule |
module red_pitaya_pfd_block
#(
parameter ISR = 0
)
( input rstn_i,
input clk_i,
input s1, //signal 1
input s2, //signal 2
output [14-1:0] integral_o
);
reg l1; //s1 from last cycle
reg l2; //s2 from last cycle
wire e1;
wire e2;
reg [14+ISR-1:0] integral;
assign e1 = ( {s1,l1} == 2'b10 ) ? 1'b1 : 1'b0;
assign e2 = ( {s2,l2} == 2'b10 ) ? 1'b1 : 1'b0;
assign integral_o = integral[14+ISR-1:ISR];
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
l1 <= 1'b0;
l2 <= 1'b0;
integral <= {(14+ISR){1'b0}};
end
else begin
l1 <= s1;
l2 <= s2;
if (integral == {1'b0,{14+ISR-1{1'b1}}}) //auto-reset or positive saturation
//integral <= {INTBITS{1'b0}};
integral <= integral + {14+ISR{1'b1}}; //decrement by one
else if (integral == {1'b1,{14+ISR-1{1'b0}}}) //auto-reset or negative saturation
//integral <= {INTBITS{1'b0}};
integral <= integral + {{14+ISR-1{1'b0}},1'b1};
//output signal is proportional to frequency difference of s1-s2
else if ({e1,e2}==2'b10)
integral <= integral + {{14+ISR-1{1'b0}},1'b1};
else if ({e1,e2}==2'b01)
integral <= integral + {14+ISR{1'b1}};
end
end
endmodule |
module sky130_fd_sc_hdll__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule |
module top (
input wire clk,
input wire [7:0] sw,
output wire [7:0] led,
output wire [3:0] io_out,
input wire [3:0] io_inp
);
// PLL (to get clock division and still keep 50% duty cycle)
wire fb;
wire clk_ddr;
wire clk_ddr_nobuf;
PLLE2_ADV # (
.CLKFBOUT_MULT (16),
.CLKOUT0_DIVIDE (64) // 25MHz
) pll (
.CLKIN1 (clk),
.CLKFBIN (fb),
.CLKFBOUT (fb),
.CLKOUT0 (clk_ddr_nobuf)
);
BUFG bufg (.I(clk_ddr_nobuf), .O(clk_ddr));
// Heartbeat
reg [23:0] cnt;
always @(posedge clk_ddr)
cnt <= cnt + 1;
assign led[7] = cnt[23];
// IDELAYCTRL
IDELAYCTRL idelayctrl (
.REFCLK (clk_ddr),
.RDY (led[6])
);
// Testers
ioddr_tester #(.DDR_CLK_EDGE("SAME_EDGE"))
tester0 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[0]), .Q(io_out[0]), .D(io_inp[0]));
ioddr_tester #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), .USE_IDELAY(1))
tester1 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[1]), .Q(io_out[1]), .D(io_inp[1]));
ioddr_tester #(.DDR_CLK_EDGE("OPPOSITE_EDGE"))
tester2 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[2]), .Q(io_out[2]), .D(io_inp[2]));
ioddr_tester #(.USE_PHY_ODDR(0))
tester3 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[3]), .Q(io_out[3]), .D(io_inp[3]));
// Unused LEDs
assign led[5:4] = |sw;
endmodule |
module outputs)
wire to_pad; // From ctl_edgelogic of dram_ctl_edgelogic.v
// End of automatics
// INSTANTIATING PAD LOGIC
dram_ctl_edgelogic ctl_edgelogic(/*AUTOINST*/
// Outputs
.ctl_pad_clk_so(ctl_pad_clk_so),
.to_pad(to_pad),
// Inputs
.clk (clk),
.rst_l (rst_l),
.testmode_l(testmode_l),
.ctl_pad_clk_se(ctl_pad_clk_se),
.ctl_pad_clk_si(ctl_pad_clk_si),
.data (data));
// SSTL LOGIC
/*dram_sstl_pad AUTO_TEMPLATE(
.pad (pad),
.oe (1'b1),
.to_core (),
.odt_enable_mask (1'b1),
.data_in (to_pad));
*/
dram_sstl_pad sstl_pad(/*AUTOINST*/
// Outputs
.bso (bso),
.to_core (), // Templated
// Inouts
.pad (pad), // Templated
// Inputs
.bsi (bsi),
.cbd (cbd[8:1]),
.cbu (cbu[8:1]),
.clock_dr (clock_dr),
.data_in (to_pad), // Templated
.hiz_n (hiz_n),
.mode_ctrl (mode_ctrl),
.odt_enable_mask (1'b1), // Templated
.oe (1'b1), // Templated
.shift_dr (shift_dr),
.update_dr (update_dr),
.vdd_h (vdd_h),
.vrefcode (vrefcode[7:0]));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [12:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [12:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [12:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [12:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [12:0]bram_addr_a;
wire [12:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [12:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [12:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "11" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "2048" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "13" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO
(E,
bid_gets_fifo_load,
bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
D,
axi_wdata_full_cmb114_out,
SR,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
Q,
s_axi_awid,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output [0:0]E;
output bid_gets_fifo_load;
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output [11:0]D;
output axi_wdata_full_cmb114_out;
input [0:0]SR;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input [11:0]Q;
input [11:0]s_axi_awid;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire [11:0]D;
wire D_0;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire [11:0]Q;
wire S;
wire S0_out;
wire S1_out;
wire [0:0]SR;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[11]_i_3_n_0 ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire [11:0]bid_fifo_ld;
wire bid_fifo_not_empty;
wire [11:0]bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire [11:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D_0),
.Q(bid_fifo_not_empty),
.R(SR));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D_0));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[11]),
.Q(bid_fifo_rd[11]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.O(bid_fifo_ld[11]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[10].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[1]),
.Q(bid_fifo_rd[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[10].SRL16E_I_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.O(bid_fifo_ld[1]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[11].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[0]),
.Q(bid_fifo_rd[0]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[11].SRL16E_I_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.O(bid_fifo_ld[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[10]),
.Q(bid_fifo_rd[10]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[1].SRL16E_I_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.O(bid_fifo_ld[10]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[9]),
.Q(bid_fifo_rd[9]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[2].SRL16E_I_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.O(bid_fifo_ld[9]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[8]),
.Q(bid_fifo_rd[8]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[3].SRL16E_I_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.O(bid_fifo_ld[8]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[7]),
.Q(bid_fifo_rd[7]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[4].SRL16E_I_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.O(bid_fifo_ld[7]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[6]),
.Q(bid_fifo_rd[6]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[5].SRL16E_I_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.O(bid_fifo_ld[6]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[5]),
.Q(bid_fifo_rd[5]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[6].SRL16E_I_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.O(bid_fifo_ld[5]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[4]),
.Q(bid_fifo_rd[4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[7].SRL16E_I_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.O(bid_fifo_ld[4]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[8].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[3]),
.Q(bid_fifo_rd[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[8].SRL16E_I_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.O(bid_fifo_ld[3]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[9].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[2]),
.Q(bid_fifo_rd[2]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[9].SRL16E_I_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.O(bid_fifo_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[0]_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[10]_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[10]),
.O(D[10]));
LUT2 #(
.INIT(4'hE))
\axi_bid_int[11]_i_1
(.I0(bid_gets_fifo_load),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[11]_i_2
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[11]),
.O(D[11]));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[11]_i_3
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[1]_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[2]_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[3]_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[4]_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[5]_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[6]_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[7]_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[8]_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[9]_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [11:0]s_axi_awid;
input [12:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [12:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [12:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [12:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [12:2]\^bram_addr_a ;
wire [12:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [12:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [12:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[12:2] = \^bram_addr_a [12:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[12:2] = \^bram_addr_b [12:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[12:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[12:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [10:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [10:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [10:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [10:0]bram_addr_a;
wire [10:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [10:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [10:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [10:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [10:0]bram_addr_a;
wire [10:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b[9:0]),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_b(bram_addr_b[10]),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.SR(bram_rst_a),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
bram_en_b,
Q,
s_axi_arready,
bram_addr_b,
s_axi_rid,
s_axi_araddr,
s_axi_aclk,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_rready,
s_axi_aresetn,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arid,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output bram_en_b;
output [9:0]Q;
output s_axi_arready;
output [0:0]bram_addr_b;
output [11:0]s_axi_rid;
input [10:0]s_axi_araddr;
input s_axi_aclk;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_rready;
input s_axi_aresetn;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [11:0]s_axi_arid;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_4_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_5_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[10]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp[1]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[2]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[3]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[4]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[5]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[6]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[7]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[8]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [9:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [11:0]axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_3_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire [11:0]axi_rid_temp;
wire [11:0]axi_rid_temp2;
wire [11:0]axi_rid_temp20_in;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire [0:0]bram_addr_b;
wire bram_addr_ld_en;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one0;
wire brst_one_i_1_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_10_n_0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_26_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(I_WRAP_BRST_n_23),
.O(p_48_out));
LUT6 #(
.INIT(64'h00CC304400000044))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCDCDCDDDCCCCCCCC))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I3(end_brst_rd),
.I4(brst_zero),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'h808880808088A280))
\GEN_AR_DUAL.ar_active_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(rd_data_sm_cs[1]),
.I2(\GEN_AR_DUAL.ar_active_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
LUT6 #(
.INIT(64'h0010000000000000))
\GEN_AR_DUAL.ar_active_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h1))
\GEN_AR_DUAL.ar_active_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(\GEN_AR_DUAL.ar_active_i_4_n_0 ));
LUT6 #(
.INIT(64'h8A88000000000000))
\GEN_AR_DUAL.ar_active_i_5
(.I0(I_WRAP_BRST_n_24),
.I1(brst_zero),
.I2(axi_b2b_brst),
.I3(end_brst_rd),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(\GEN_AR_DUAL.ar_active_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(I_WRAP_BRST_n_23),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[0]),
.Q(axi_arid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[10]),
.Q(axi_arid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[11]),
.Q(axi_arid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[1]),
.Q(axi_arid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[2]),
.Q(axi_arid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[3]),
.Q(axi_arid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[4]),
.Q(axi_arid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[5]),
.Q(axi_arid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[6]),
.Q(axi_arid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[7]),
.Q(axi_arid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[8]),
.Q(axi_arid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[9]),
.Q(axi_arid_pipe[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(I_WRAP_BRST_n_23),
.I1(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[7]),
.I1(s_axi_arlen[1]),
.I2(s_axi_arlen[3]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[5]),
.I1(s_axi_arlen[4]),
.I2(s_axi_arlen[2]),
.I3(s_axi_arlen[6]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_20),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hE2))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(I_WRAP_BRST_n_21),
.I1(I_WRAP_BRST_n_7),
.I2(bram_addr_b),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_10),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_9),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ),
.Q(bram_addr_b),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_18),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_17),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_16),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_15),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_14),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_13),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_12),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_11),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAEAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[3]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT4 #(
.INIT(16'h08FF))
\GEN_RID.axi_rid_int[11]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_int[11]_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[0]),
.Q(s_axi_rid[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[10]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[10]),
.Q(s_axi_rid[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[11]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[11]),
.Q(s_axi_rid[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[1]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[1]),
.Q(s_axi_rid[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[2]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[2]),
.Q(s_axi_rid[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[3]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[3]),
.Q(s_axi_rid[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[4]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[4]),
.Q(s_axi_rid[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[5]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[5]),
.Q(s_axi_rid[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[6]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[6]),
.Q(s_axi_rid[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[7]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[7]),
.Q(s_axi_rid[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[8]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[8]),
.Q(s_axi_rid[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[9]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[9]),
.Q(s_axi_rid[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.O(axi_rid_temp20_in[0]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.O(axi_rid_temp20_in[10]));
LUT2 #(
.INIT(4'h8))
\GEN_RID.axi_rid_temp2[11]_i_1
(.I0(axi_rid_temp_full),
.I1(bram_addr_ld_en),
.O(p_26_out));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.O(axi_rid_temp20_in[11]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.O(axi_rid_temp20_in[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.O(axi_rid_temp20_in[2]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.O(axi_rid_temp20_in[3]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.O(axi_rid_temp20_in[4]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.O(axi_rid_temp20_in[5]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.O(axi_rid_temp20_in[6]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.O(axi_rid_temp20_in[7]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.O(axi_rid_temp20_in[8]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.O(axi_rid_temp20_in[9]));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[0]),
.Q(axi_rid_temp2[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[10]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[10]),
.Q(axi_rid_temp2[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[11]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[11]),
.Q(axi_rid_temp2[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[1]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[1]),
.Q(axi_rid_temp2[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[2]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[2]),
.Q(axi_rid_temp2[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[3]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[3]),
.Q(axi_rid_temp2[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[4]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[4]),
.Q(axi_rid_temp2[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[5]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[5]),
.Q(axi_rid_temp2[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[6]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[6]),
.Q(axi_rid_temp2[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[7]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[7]),
.Q(axi_rid_temp2[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[8]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[8]),
.Q(axi_rid_temp2[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[9]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[9]),
.Q(axi_rid_temp2[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[0]),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[10]),
.O(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hA0FFA0E0))
\GEN_RID.axi_rid_temp[11]_i_1
(.I0(p_4_out),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.O(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[11]),
.O(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[1]),
.O(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[2]),
.O(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[3]),
.O(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[4]),
.O(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[5]),
.O(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[6]),
.O(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[7]),
.O(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[8]),
.O(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[9]),
.O(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ),
.Q(axi_rid_temp[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ),
.Q(axi_rid_temp[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ),
.Q(axi_rid_temp[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ),
.Q(axi_rid_temp[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ),
.Q(axi_rid_temp[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ),
.Q(axi_rid_temp[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ),
.Q(axi_rid_temp[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ),
.Q(axi_rid_temp[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ),
.Q(axi_rid_temp[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ),
.Q(axi_rid_temp[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ),
.Q(axi_rid_temp[9]),
.R(bram_rst_a));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18}),
.E(I_WRAP_BRST_n_6),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] (axi_arlen_pipe[3:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_7),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (I_WRAP_BRST_n_8),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 (Q),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_20),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ),
.Q(rd_data_sm_cs),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_b2b_brst_reg(I_WRAP_BRST_n_24),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.rd_adv_buf67_out(rd_adv_buf67_out),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_22),
.\rd_data_sm_cs_reg[3] (I_WRAP_BRST_n_25),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[12]_0 (I_WRAP_BRST_n_21),
.\save_init_bram_addr_ld_reg[12]_1 (I_WRAP_BRST_n_23),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_4),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_5));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8A8A8))
act_rd_burst_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(act_rd_burst_i_4_n_0),
.I2(axi_b2b_brst_i_3_n_0),
.I3(\rd_data_sm_cs[2]_i_4_n_0 ),
.I4(last_bram_addr_i_8_n_0),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h02000004FFFFFFFF))
act_rd_burst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(\rd_data_sm_cs[3]_i_6_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h4440))
act_rd_burst_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.O(act_rd_burst_i_4_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCC0CCC55CC0CCCCC))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_24),
.I1(axi_b2b_brst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(axi_b2b_brst_i_3_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000088880080))
axi_b2b_brst_i_3
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(rd_adv_buf67_out),
.I2(end_brst_rd),
.I3(axi_b2b_brst),
.I4(brst_zero),
.I5(I_WRAP_BRST_n_24),
.O(axi_b2b_brst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000004))
axi_rd_burst_i_2
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(axi_rd_burst_i_3_n_0),
.I2(I_WRAP_BRST_n_4),
.I3(\brst_cnt[7]_i_3_n_0 ),
.I4(I_WRAP_BRST_n_3),
.I5(I_WRAP_BRST_n_2),
.O(axi_rd_burst_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
axi_rd_burst_i_3
(.I0(s_axi_arlen[5]),
.I1(axi_arlen_pipe[5]),
.I2(s_axi_arlen[4]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[4]),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hAAAABAAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(axi_rvalid_clr_ok_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(I_WRAP_BRST_n_23),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEEEEFFFEEEEE000E))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(I_WRAP_BRST_n_25),
.I4(bram_en_int_i_6_n_0),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
LUT6 #(
.INIT(64'hFFFF777FFFFFFFFF))
bram_en_int_i_10
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(act_rd_burst),
.I3(act_rd_burst_two),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_10_n_0));
LUT6 #(
.INIT(64'hD0D000F0D0D0F0F0))
bram_en_int_i_11
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(I_WRAP_BRST_n_24),
.I2(rd_data_sm_cs[1]),
.I3(brst_one),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'h00000000FDF50000))
bram_en_int_i_2
(.I0(rd_data_sm_cs[2]),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_7_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAEEAFAAAAAAEE))
bram_en_int_i_3
(.I0(I_WRAP_BRST_n_0),
.I1(bram_addr_ld_en),
.I2(p_0_in13_in),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'h000F007F0000007F))
bram_en_int_i_4
(.I0(pend_rd_op),
.I1(rd_adv_buf67_out),
.I2(\rd_data_sm_cs[0]_i_3_n_0 ),
.I3(bram_en_int_i_9_n_0),
.I4(bram_addr_ld_en),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h1010111111111110))
bram_en_int_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(bram_en_int_i_11_n_0),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h3330131003001310))
bram_en_int_i_7
(.I0(\rd_data_sm_cs[2]_i_5_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(axi_rd_burst_two_reg_n_0),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(bram_en_int_i_7_n_0));
LUT6 #(
.INIT(64'h1111111111111000))
bram_en_int_i_9
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(brst_zero),
.I5(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_3),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
\brst_cnt[4]_i_2
(.I0(brst_cnt[2]),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.I3(brst_cnt[3]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_8),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[3]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000E0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_7_n_0),
.O(brst_one_i_1_n_0));
LUT6 #(
.INIT(64'h80FF808080808080))
brst_one_i_2
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_5),
.I2(axi_rd_burst_i_2_n_0),
.I3(brst_cnt[0]),
.I4(brst_cnt[1]),
.I5(last_bram_addr_i_9_n_0),
.O(brst_one0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_7_n_0),
.I2(s_axi_aresetn),
.I3(last_bram_addr_i_3_n_0),
.O(brst_zero_i_1_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hFE7D0000FE7DFE7D))
disable_b2b_brst_i_3
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst),
.I5(disable_b2b_brst_i_4_n_0),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'hDFDFDFDFDFDFDFFF))
disable_b2b_brst_i_4
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(brst_zero),
.I4(end_brst_rd),
.I5(brst_one),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFEFEFEFF10100000))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[0]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF57550000))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(last_bram_addr_i_3_n_0),
.I2(last_bram_addr_i_4_n_0),
.I3(last_bram_addr_i_5_n_0),
.I4(last_bram_addr_i_6_n_0),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_10
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_10_n_0));
LUT6 #(
.INIT(64'hAABFFFBFFFBFFFBF))
last_bram_addr_i_2
(.I0(rd_data_sm_cs[2]),
.I1(last_bram_addr_i_8_n_0),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(p_0_in13_in),
.O(last_bram_addr_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h8A80AAAA))
last_bram_addr_i_3
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(last_bram_addr_i_3_n_0));
LUT6 #(
.INIT(64'hDDDDDDDDFFFDFFFF))
last_bram_addr_i_4
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(last_bram_addr_i_4_n_0));
LUT4 #(
.INIT(16'h8880))
last_bram_addr_i_5
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(bram_addr_ld_en),
.I3(pend_rd_op),
.O(last_bram_addr_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h81))
last_bram_addr_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.O(last_bram_addr_i_6_n_0));
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_7
(.I0(last_bram_addr_i_9_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h02A2))
last_bram_addr_i_8
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(last_bram_addr_i_8_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_9
(.I0(I_WRAP_BRST_n_8),
.I1(last_bram_addr_i_10_n_0),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.I5(brst_cnt[7]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAAAAA88C8AAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_25),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAFFFEAAAA0002))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(pend_rd_op_i_4_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_5_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_3
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_3_n_0));
LUT6 #(
.INIT(64'h00000000BBBABB00))
pend_rd_op_i_4
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_data_sm_cs[0]),
.I2(pend_rd_op_i_5_n_0),
.I3(bram_addr_ld_en),
.I4(pend_rd_op_i_7_n_0),
.I5(I_WRAP_BRST_n_25),
.O(pend_rd_op_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_5
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h8000FFFF))
pend_rd_op_i_6
(.I0(pend_rd_op),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(pend_rd_op_i_6_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF0008888))
pend_rd_op_i_7
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.I2(ar_active),
.I3(end_brst_rd),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[1]),
.O(pend_rd_op_i_7_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEAAAAAAFEAAFEAA))
\rd_data_sm_cs[0]_i_2
(.I0(I_WRAP_BRST_n_25),
.I1(act_rd_burst_two),
.I2(act_rd_burst),
.I3(disable_b2b_brst_i_2_n_0),
.I4(bram_addr_ld_en),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000300BF0003008F))
\rd_data_sm_cs[0]_i_4
(.I0(rd_adv_buf67_out),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(I_WRAP_BRST_n_25),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(I_WRAP_BRST_n_22),
.I5(\rd_data_sm_cs[1]_i_3_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC0CCCCCC88888888))
\rd_data_sm_cs[1]_i_3
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(I_WRAP_BRST_n_24),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAABAAABAEAFAAAB))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(\rd_data_sm_cs[2]_i_3_n_0 ),
.I4(\rd_data_sm_cs[2]_i_4_n_0 ),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000DF00000))
\rd_data_sm_cs[2]_i_2
(.I0(bram_addr_ld_en),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00C0FFFF33F3BBBB))
\rd_data_sm_cs[2]_i_3
(.I0(axi_rd_burst),
.I1(rd_data_sm_cs[0]),
.I2(rd_adv_buf67_out),
.I3(I_WRAP_BRST_n_24),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_5
(.I0(brst_zero),
.I1(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFCCCBBBB3000B888))
\rd_data_sm_cs[3]_i_1
(.I0(\rd_data_sm_cs[3]_i_3_n_0 ),
.I1(\rd_data_sm_cs[3]_i_4_n_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(\rd_data_sm_cs[3]_i_5_n_0 ),
.I5(bram_addr_ld_en),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h0000004050005040))
\rd_data_sm_cs[3]_i_2
(.I0(I_WRAP_BRST_n_25),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF5EFFFF))
\rd_data_sm_cs[3]_i_3
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hBFAD))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0035))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h1FFF))
\rd_data_sm_cs[3]_i_6
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
LUT3 #(
.INIT(8'hBA))
\rd_data_sm_cs[3]_i_7
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1110011001100110))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(s_axi_rready),
.I5(s_axi_rvalid),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hF0F010F00F00F000))
rddata_mux_sel_i_2
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.I5(rd_adv_buf67_out),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hF700070FF70F070F))
rddata_mux_sel_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
bram_addr_a,
s_axi_bid,
bram_we_a,
SR,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awid,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output [3:0]bram_we_a;
input [0:0]SR;
input s_axi_aclk;
input [10:0]s_axi_awaddr;
input s_axi_aresetn;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input [11:0]s_axi_awid;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_0;
wire BID_FIFO_n_10;
wire BID_FIFO_n_11;
wire BID_FIFO_n_12;
wire BID_FIFO_n_13;
wire BID_FIFO_n_14;
wire BID_FIFO_n_15;
wire BID_FIFO_n_3;
wire BID_FIFO_n_4;
wire BID_FIFO_n_5;
wire BID_FIFO_n_6;
wire BID_FIFO_n_7;
wire BID_FIFO_n_8;
wire BID_FIFO_n_9;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [0:0]SR;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire [11:0]axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [10:0]bram_addr_a;
wire bram_addr_inc;
wire [10:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_awlen_reg_1_or_2_i_3_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO BID_FIFO
(.D({BID_FIFO_n_4,BID_FIFO_n_5,BID_FIFO_n_6,BID_FIFO_n_7,BID_FIFO_n_8,BID_FIFO_n_9,BID_FIFO_n_10,BID_FIFO_n_11,BID_FIFO_n_12,BID_FIFO_n_13,BID_FIFO_n_14,BID_FIFO_n_15}),
.E(BID_FIFO_n_0),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.Q(axi_awid_pipe),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_3),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_17),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_16),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_18),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_18),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(SR));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(SR));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_17),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_17),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[0]),
.Q(axi_awid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[10]),
.Q(axi_awid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[11]),
.Q(axi_awid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[1]),
.Q(axi_awid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[2]),
.Q(axi_awid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[3]),
.Q(axi_awid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[4]),
.Q(axi_awid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[5]),
.Q(axi_awid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[6]),
.Q(axi_awid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[7]),
.Q(axi_awid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[8]),
.Q(axi_awid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[9]),
.Q(axi_awid_pipe[9]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_14),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(bram_addr_a[10]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_ld),
.I3(I_WRAP_BRST_n_0),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_4),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_3),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ),
.Q(bram_addr_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_6),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_5),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(SR));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(SR));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(SR));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst I_WRAP_BRST
(.D({I_WRAP_BRST_n_3,I_WRAP_BRST_n_4,I_WRAP_BRST_n_5,I_WRAP_BRST_n_6,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_14),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_19),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_20),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[12]_0 (bram_addr_ld),
.\save_init_bram_addr_ld_reg[12]_1 (I_WRAP_BRST_n_16),
.\save_init_bram_addr_ld_reg[12]_2 (I_WRAP_BRST_n_17),
.\save_init_bram_addr_ld_reg[12]_3 (I_WRAP_BRST_n_18),
.wr_addr_sm_cs(wr_addr_sm_cs));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_15),
.Q(s_axi_bid[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[10]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_5),
.Q(s_axi_bid[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[11]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_4),
.Q(s_axi_bid[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[1]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_14),
.Q(s_axi_bid[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[2]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_13),
.Q(s_axi_bid[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[3]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_12),
.Q(s_axi_bid[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[4]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_11),
.Q(s_axi_bid[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[5]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_10),
.Q(s_axi_bid[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[6]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_9),
.Q(s_axi_bid[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[7]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_8),
.Q(s_axi_bid[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[8]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_7),
.Q(s_axi_bid[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[9]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_6),
.Q(s_axi_bid[9]),
.R(SR));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_3),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(SR));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(SR));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(SR));
LUT6 #(
.INIT(64'h5000303050003000))
curr_awlen_reg_1_or_2_i_1
(.I0(axi_awlen_pipe[3]),
.I1(s_axi_awlen[3]),
.I2(curr_awlen_reg_1_or_2_i_2_n_0),
.I3(curr_awlen_reg_1_or_2_i_3_n_0),
.I4(axi_awaddr_full),
.I5(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.O(curr_awlen_reg_1_or_20));
LUT5 #(
.INIT(32'h00053305))
curr_awlen_reg_1_or_2_i_2
(.I0(s_axi_awlen[2]),
.I1(axi_awlen_pipe[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[1]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
LUT5 #(
.INIT(32'h00000100))
curr_awlen_reg_1_or_2_i_3
(.I0(axi_awlen_pipe[4]),
.I1(axi_awlen_pipe[7]),
.I2(axi_awlen_pipe[6]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[5]),
.O(curr_awlen_reg_1_or_2_i_3_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_19),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_20),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
bram_addr_ld_en_mod,
E,
D,
\save_init_bram_addr_ld_reg[12]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[12]_1 ,
\save_init_bram_addr_ld_reg[12]_2 ,
\save_init_bram_addr_ld_reg[12]_3 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
SR,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output bram_addr_ld_en_mod;
output [0:0]E;
output [9:0]D;
output [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[12]_1 ;
output \save_init_bram_addr_ld_reg[12]_2 ;
output \save_init_bram_addr_ld_reg[12]_3 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [10:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input [0:0]SR;
input s_axi_aclk;
wire [9:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [10:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [12:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[12]_i_6_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
wire \save_init_bram_addr_ld_reg[12]_1 ;
wire \save_init_bram_addr_ld_reg[12]_2 ;
wire \save_init_bram_addr_ld_reg[12]_3 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_3_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[1]_i_2__0_n_0 ;
wire \wrap_burst_total[1]_i_3__0_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total[2]_i_3_n_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(curr_fixed_burst_reg_reg));
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[12]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[12]_1 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[12]_2 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[12]_3 ),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[12]_i_2
(.I0(save_init_bram_addr_ld[12]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(\save_init_bram_addr_ld_reg[12]_0 ));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[12]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[12]_1 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[12]_i_4
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[12]_2 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[12]_i_5
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[12]_3 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h1))
\save_init_bram_addr_ld[12]_i_6
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ),
.O(\save_init_bram_addr_ld[12]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld_reg[12]_0 ),
.Q(save_init_bram_addr_ld[12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(SR));
LUT6 #(
.INIT(64'h0000A22200000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total[0]_i_3_n_0 ),
.I2(Q[1]),
.I3(Q[2]),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.I5(\wrap_burst_total[1]_i_2__0_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hCCA533A5FFA5FFA5))
\wrap_burst_total[0]_i_2__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.I5(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h08000800F3000000))
\wrap_burst_total[1]_i_1__0
(.I0(\wrap_burst_total[2]_i_3_n_0 ),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total[1]_i_2__0_n_0 ),
.I4(\wrap_burst_total[1]_i_3__0_n_0 ),
.I5(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2__0
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[0]),
.O(\wrap_burst_total[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3__0
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hA000000088008800))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[0]),
.I2(Q[0]),
.I3(\wrap_burst_total[2]_i_3_n_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_2__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_3
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.O(\wrap_burst_total[2]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(SR));
endmodule |
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\save_init_bram_addr_ld_reg[12]_0 ,
\rd_data_sm_cs_reg[1] ,
\save_init_bram_addr_ld_reg[12]_1 ,
axi_b2b_brst_reg,
\rd_data_sm_cs_reg[3] ,
rd_adv_buf67_out,
end_brst_rd,
brst_zero,
Q,
axi_rvalid_int_reg,
s_axi_rready,
s_axi_aresetn,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ,
axi_arsize_pipe,
axi_araddr_full,
s_axi_arlen,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
rd_addr_sm_cs,
last_bram_addr,
ar_active,
pend_rd_op,
no_ar_ack,
s_axi_arvalid,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [0:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
output [9:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
output \rd_data_sm_cs_reg[1] ;
output \save_init_bram_addr_ld_reg[12]_1 ;
output axi_b2b_brst_reg;
output \rd_data_sm_cs_reg[3] ;
output rd_adv_buf67_out;
input end_brst_rd;
input brst_zero;
input [3:0]Q;
input axi_rvalid_int_reg;
input s_axi_rready;
input s_axi_aresetn;
input [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
input [0:0]axi_arsize_pipe;
input axi_araddr_full;
input [3:0]s_axi_arlen;
input curr_fixed_burst_reg;
input [10:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input rd_addr_sm_cs;
input last_bram_addr;
input ar_active;
input pend_rd_op;
input no_ar_ack;
input s_axi_arvalid;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [9:0]D;
wire [0:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_b2b_brst_reg;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire \rd_data_sm_cs_reg[1] ;
wire \rd_data_sm_cs_reg[3] ;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[12]_i_3__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
wire \save_init_bram_addr_ld_reg[12]_1 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_3__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ),
.I2(curr_fixed_burst_reg),
.O(E));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0E0F0F0E0E0FFF0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I4(Q[1]),
.I5(Q[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0
(.I0(axi_rd_burst_two_reg),
.I1(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h0000000080800080))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(Q[0]),
.I1(axi_rvalid_int_reg),
.I2(s_axi_rready),
.I3(end_brst_rd),
.I4(axi_b2b_brst),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.O(D[0]));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(axi_rvalid_int_reg),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
LUT5 #(
.INIT(32'hFFFDFFFF))
axi_b2b_brst_i_2
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(axi_b2b_brst_reg));
LUT2 #(
.INIT(4'hB))
bram_en_int_i_5
(.I0(Q[3]),
.I1(Q[2]),
.O(\rd_data_sm_cs_reg[3] ));
LUT6 #(
.INIT(64'h0010000000000000))
bram_en_int_i_8
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(Q[2]),
.I3(Q[0]),
.I4(axi_rvalid_int_reg),
.I5(s_axi_rready),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h000F000E000F0000))
\rd_data_sm_cs[1]_i_2
(.I0(axi_rd_burst_two_reg),
.I1(axi_rd_burst),
.I2(Q[3]),
.I3(Q[2]),
.I4(Q[1]),
.I5(Q[0]),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h02AA0202))
\save_init_bram_addr_ld[12]_i_1__0
(.I0(axi_aresetn_d2),
.I1(rd_addr_sm_cs),
.I2(\save_init_bram_addr_ld[12]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[12]_1 ),
.I4(last_bram_addr),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[12]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(\save_init_bram_addr_ld_reg[12]_0 ));
LUT5 #(
.INIT(32'hFEFEFEFF))
\save_init_bram_addr_ld[12]_i_3__0
(.I0(ar_active),
.I1(pend_rd_op),
.I2(no_ar_ack),
.I3(s_axi_arvalid),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld[12]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\save_init_bram_addr_ld[12]_i_4__0
(.I0(axi_b2b_brst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(\rd_data_sm_cs_reg[3] ),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\save_init_bram_addr_ld_reg[12]_1 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld_reg[12]_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h3202010100000000))
\wrap_burst_total[0]_i_1
(.I0(\wrap_burst_total_reg[0]_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(\wrap_burst_total[0]_i_3__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I4(\wrap_burst_total_reg[0]_2 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h20CF000000000000))
\wrap_burst_total[1]_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_arsize_pipe),
.I2(axi_araddr_full),
.I3(\wrap_burst_total_reg[0]_1 ),
.I4(\wrap_burst_total_reg[0]_3 ),
.I5(\wrap_burst_total_reg[0]_2 ),
.O(\wrap_burst_total[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_3 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_4
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000D580))
\wrap_burst_total[2]_i_1
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.I2(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I3(s_axi_arlen[2]),
.I4(\wrap_burst_total[2]_i_2_n_0 ),
.O(\wrap_burst_total[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FFF5F5F3FFFFFFF))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[3]),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I2(\wrap_burst_total_reg[0]_3 ),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I4(axi_araddr_full),
.I5(s_axi_arlen[1]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule |
module sky130_fd_sc_lp__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule |
module sky130_fd_sc_ms__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
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